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| author | Anusha Reddy Rangareddygari <anusrang@in.ibm.com> | 2017-06-30 03:28:03 -0400 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-07-12 01:01:55 -0400 |
| commit | ceab789089358c5bec527d11748b9e6912521a74 (patch) | |
| tree | 1fb29272e35947a96480d631416d2fc7c2799a7e /src/import/chips/p9/procedures/hwp/perv | |
| parent | 9bcb3484cb0191a53084d8fb3af7a9afb44286c3 (diff) | |
| download | talos-sbe-ceab789089358c5bec527d11748b9e6912521a74.tar.gz talos-sbe-ceab789089358c5bec527d11748b9e6912521a74.zip | |
p9_sbe_chiplet_reset updates
Added sim ony delay to work with
NEST_PLL_BUCKET = 1 to support MV
GSD2PIB
Change-Id: I68b8f255c26b85e7b77fde01ac538b3208c13c49
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42641
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: Abhishek Agarwal <abagarw8@in.ibm.com>
Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42792
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/perv')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C index 1b3a8b2f..9e05481f 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C @@ -1422,7 +1422,9 @@ static fapi2::ReturnCode p9_sbe_chiplet_reset_all_obus_scan0( FAPI_DBG("Force PLL out enable for PLLs"); FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WOR, l_data)); +#ifdef SIM_ONLY_DELAY fapi2::delay(10000, (40 * 400)); +#endif l_data.flush<1>(); l_data.clearBit<PERV_1_NET_CTRL0_PCB_EP_RESET>(); |
