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| author | Joe Dery <dery@us.ibm.com> | 2017-06-21 12:06:03 -0400 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-06-23 19:51:15 -0400 |
| commit | 8242086d77cdff35e0e8e0d909b3d5cb9849489a (patch) | |
| tree | afdd93282f8790d49daa623f4addd9853233810f /src/import/chips/p9/procedures/hwp/perv | |
| parent | bd968b0f6b1f9ad8edbe05a27535cfe70dbd2a34 (diff) | |
| download | talos-sbe-8242086d77cdff35e0e8e0d909b3d5cb9849489a.tar.gz talos-sbe-8242086d77cdff35e0e8e0d909b3d5cb9849489a.zip | |
p9_sbe_tp_chiplet_init1: Set TP_TCPERV_SRAM_ENABLE_DC
Set TP_TCPERV_SRAM_ENABLE_DC at end, after CHIPLET_ENABLE/scan0
CQ: HW414015
Change-Id: I28ea1bd84eaab79d2db249c5902c1f88a7fcd1e2
Depends-On: I5a4b929fad4aa954ad413eb73861ab1e53135360
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42226
Dev-Ready: Joachim Fenkes <fenkes@de.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42231
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/perv')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C index 4669fecd..6fac9410 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C @@ -40,6 +40,7 @@ #include "p9_sbe_tp_chiplet_init1.H" #include <p9_perv_scom_addresses.H> #include <p9_perv_scom_addresses_fld.H> +#include <p9n2_perv_scom_addresses_fld.H> #include <p9_perv_sbe_cmn.H> @@ -126,6 +127,10 @@ fapi2::ReturnCode p9_sbe_tp_chiplet_init1(const fapi2::TARGET_STATE_FUNCTIONAL)[0], l_regions, SCAN_TYPES_EXCEPT_TIME_GPTR_REPR)); + FAPI_DBG("Set TP_TCPERV_SRAM_ENABLE_DC"); + l_data64_perv_ctrl0.setBit<P9N2_PERV_PERV_CTRL0_TP_TCPERV_SRAM_ENABLE_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64_perv_ctrl0)); + FAPI_INF("p9_sbe_tp_chiplet_init1: Exiting ..."); fapi_try_exit: |
