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| author | Joe McGill <jmcgill@us.ibm.com> | 2017-06-30 15:41:53 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-07-19 05:46:39 -0400 |
| commit | ce5ffaa904f41b495b56cb7d4fcf09cabb3e69f3 (patch) | |
| tree | 8912158ca4ddaa22d1d3529daa2954bfd9890959 /src/import/chips/p9/procedures/hwp/perv | |
| parent | 666c149f54245ec1ed56d7ff7d7a1d30baba72fc (diff) | |
| download | talos-sbe-ce5ffaa904f41b495b56cb7d4fcf09cabb3e69f3.tar.gz talos-sbe-ce5ffaa904f41b495b56cb7d4fcf09cabb3e69f3.zip | |
updates for thread control, ramming with STOP enabled
remove pre-stop checks in p9_thread_control_stop, just attempt stop
and confirm final expected state is reached:
- after special wakeup from STOP2, existing threads_stopped check will fail
given that the thread does not reach maintenance mode
- the threads_running check will also fail
assert ram_active in ram_setup function, if the thread is found
to be inactive at the time ram is requested
Change-Id: Iad8fd9e8a14395102b6c1b31d6595300a2da111f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42674
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42676
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/perv')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C b/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C index 79d753d7..0e744683 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -180,6 +180,14 @@ fapi2::ReturnCode RamCore::ram_setup() FAPI_DBG("THREAD_INFO:%#lx", l_data()); FAPI_TRY(l_data.extractToRight(l_thread_active, C_THREAD_INFO_VTID0_ACTIVE + iv_thread, 1)); + if (!l_thread_active) + { + FAPI_TRY(l_data.setBit(C_THREAD_INFO_RAM_THREAD_ACTIVE + iv_thread)); + FAPI_TRY(fapi2::putScom(iv_target, C_THREAD_INFO, l_data)); + FAPI_TRY(fapi2::getScom(iv_target, C_THREAD_INFO, l_data)); + FAPI_TRY(l_data.extractToRight(l_thread_active, C_THREAD_INFO_VTID0_ACTIVE + iv_thread, 1)); + } + FAPI_ASSERT(l_thread_active, fapi2::P9_RAM_THREAD_INACTIVE_ERR() .set_THREAD(iv_thread), |
