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path: root/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
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* add shifts to addressing mode 1Rafael Espindola2006-09-131-4/+8
* partial implementation of the ARM Addressing Mode 1Rafael Espindola2006-09-111-4/+4
* Completely eliminate def&use operands. Now a register operand is EITHER aChris Lattner2006-09-051-2/+2
* add a "load effective address"Rafael Espindola2006-08-171-1/+2
* Declare the callee saved regsRafael Espindola2006-08-161-8/+10
* correctly set LocalAreaOffset of TargetFrameInfoRafael Espindola2006-08-091-5/+0
* fix the spill codeRafael Espindola2006-08-091-7/+9
* fix the loading of the link register in emitepilogueRafael Espindola2006-08-091-1/+3
* change the addressing mode of the str instruction to reg+immRafael Espindola2006-08-081-4/+2
* initial support for variable number of argumentsRafael Espindola2006-08-081-8/+17
* implemented subRafael Espindola2006-07-211-3/+8
* initial prologue and epilogue implementation. Need to define add and sub befo...Rafael Espindola2006-07-181-0/+20
* add the memri memory operandRafael Espindola2006-07-111-8/+18
* create the raddr addressing mode that matches any register and the frame indexRafael Espindola2006-07-101-1/+1
* handle the "mov reg1, reg2" case in isMoveInstrRafael Espindola2006-06-271-1/+1
* initial implementation of ARMRegisterInfo::eliminateFrameIndexRafael Espindola2006-06-181-1/+23
* implement movriRafael Espindola2006-05-181-1/+1
* getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.Evan Cheng2006-05-181-0/+11
* added a skeleton of the ARM backendRafael Espindola2006-05-141-0/+91
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