summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Expand)AuthorAgeFilesLines
...
* [SLP] Don't allow Div/Rem as alternate opcodesAndrei Elovikov2020-01-231-1/+17
* [PGO][PGSO] Update BFI in CodeGenPrepare::optimizeSelectInst.Hiroshi Yamauchi2020-01-231-0/+1
* [InstCombine] Fix worklist management in DSE (PR44552)Nikita Popov2020-01-231-2/+5
* [AArch64] Don't rename registers with pseudo defs in Ld/St opt.Florian Hahn2020-01-221-0/+13
* [StackColoring] Remap FixedStackPseudoSourceValue frame index referenced by M...Fangrui Song2020-01-211-0/+19
* [Transforms][RISCV] Remove a "using namespace llvm" from an include file. Fix...Craig Topper2020-01-171-2/+2
* Revert rG6078f2fedcac5797ac39ee5ef3fd7a35ef1202d5 - "[AArch64][GlobalISel]: S...Simon Pilgrim2020-01-151-38/+1
* [RISCV] Support ABI checking with per function target-featuresZakk Chen2020-01-153-10/+27
* Revert "[RISCV] Support ABI checking with per function target-features"Zakk Chen2020-01-153-27/+10
* RegisterClassInfo::computePSetLimit - assert that we actually find a register.Simon Pilgrim2020-01-151-0/+1
* Fix "pointer is null" static analyzer warning. NFCI.Simon Pilgrim2020-01-151-2/+1
* [yaml2obj/obj2yaml] - Add support for SHT_RELR sections.Georgii Rymar2020-01-152-7/+50
* [AArch64][SVE] Fold variable into assert to silence unused variable warnings ...Benjamin Kramer2020-01-151-2/+2
* Revert "[yaml2obj/obj2yaml] - Add support for SHT_RELR sections."Georgii Rymar2020-01-152-47/+7
* [AArch64][SVE] Add ptest intrinsicsCullen Rhodes2020-01-154-1/+54
* [yaml2obj/obj2yaml] - Add support for SHT_RELR sections.Georgii Rymar2020-01-152-7/+47
* [RISCV] Support ABI checking with per function target-featuresZakk Chen2020-01-153-10/+27
* [DWARF] Fix DWARFDebugAranges to support 64-bit CU offsets.Igor Kudrin2020-01-151-2/+2
* [AMDGPU] Invert the handling of skip insertion.cdevadas2020-01-156-6/+173
* [VE] Minimal codegen for empty functionsKazushi (Jam) Marukawa2020-01-1536-18/+2549
* [X86] Don't call LowerUINT_TO_FP_i32 for i32->f80 on 32-bit targets with sse2.Craig Topper2020-01-151-1/+1
* [Attributor] AAValueConstantRange: Value range analysis using constant rangeHideto Ueno2020-01-151-7/+499
* [Scheduler] Adjust interface of CreateTargetMIHazardRecognizer to use Schedul...David Green2020-01-151-3/+3
* [PowerPC] Fix powerpcspe subtarget enablement in llvm backendJustin Hibbits2020-01-142-4/+3
* CMake: Make most target symbols hidden by defaultTom Stellard2020-01-14105-105/+114
* DWARFDebugLine.cpp: Restore LF line endingsHubert Tong2020-01-141-1188/+1188
* [BranchAlign] Add master --x86-branches-within-32B-boundaries flagPhilip Reames2020-01-141-2/+23
* [Win64] Handle FP arguments more gracefully under -mno-sseReid Kleckner2020-01-142-22/+31
* [X86] Drop an unneeded FIXME. NFCCraig Topper2020-01-141-1/+0
* [X86] Swap the 0 and the fudge factor in the constant pool for the 32-bit mod...Craig Topper2020-01-141-4/+4
* [codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU.Michael Liao2020-01-142-1/+10
* [DAGCombine] Replace `getIntPtrConstant()` with `getVectorIdxTy()`.Michael Liao2020-01-141-1/+2
* [AArch64][GlobalISel]: Support @llvm.{return,frame}address selection.Amara Emerson2020-01-141-1/+38
* [LegalizeTypes] Remove untested code from ExpandIntOp_UINT_TO_FPCraig Topper2020-01-141-70/+2
* [InstCombine] Fix worklist management when removing guard intrinsicNikita Popov2020-01-141-10/+10
* [SVE] Add patterns for MUL immediate instruction.Danilo Carvalho Grael2020-01-142-2/+7
* [NewPM] Port MergeFunctions passNikita Popov2020-01-144-15/+36
* [InstCombine] Fix infinite loop due to bitcast <-> phi transformsNikita Popov2020-01-141-3/+8
* [InstCombine] Make combineLoadToNewType a method; NFCNikita Popov2020-01-142-13/+15
* [InstCombine] Fix user iterator invalidation in bitcast of phi transformNikita Popov2020-01-141-1/+4
* [MachineScheduler] Reduce reordering due to mem op clusteringJay Foad2020-01-141-0/+2
* [RISCV] Allow shrink wrapping for RISC-Vlewis-revill2020-01-141-4/+16
* [ThinLTO/WPD] Remove an overly-aggressive assertTeresa Johnson2020-01-141-8/+3
* [X86] Directly emit a BROADCAST_LOAD from constant pool in lowerUINT_TO_FP_vX...Craig Topper2020-01-141-2/+12
* [AIX][XCOFF] Supporting the ReadOnlyWithRel SectionKnddiggerlin2020-01-142-3/+5
* [InstCombine] Let combineLoadToNewType preserve ABI alignment of the load (PR...Juneyoung Lee2020-01-151-1/+8
* Removed PointerUnion3 and PointerUnion4 aliases in favor of the variadic temp...Dmitri Gribenko2020-01-141-1/+1
* [IR] fix potential crash in Constant::isElementWiseEqual()Sanjay Patel2020-01-141-4/+9
* [ARM][MVE] VTP Block Pass fixSjoerd Meijer2020-01-141-2/+2
* [AArch64] Fix save register pairing for Windows AAPCSSanne Wouda2020-01-141-4/+16
OpenPOWER on IntegriCloud