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* Adding support for while loopLarry Doolittle2017-11-201-0/+28
* Align the prototypes for dsp in dsp and genericmapLarry Doolittle2017-11-202-4/+3
* Beginning support for assertionsLarry Doolittle2017-11-181-0/+1
* Simple fix to genericmap exampleLarry Doolittle2017-11-181-2/+2
* Modified the Makefile to run GHDl and iVerilog always but only if installedRodrigo Alejandro Melo2017-11-171-1/+3
* Added (partial) support for to_integer functionRodrigo Alejandro Melo2017-11-161-2/+6
* Changes on genericmap due to unsupported port assignmentRodrigo Alejandro Melo2017-11-162-5/+24
* The resulting files of the GHDL analysis were moved to temp/vhdlRodrigo Alejandro Melo2017-11-161-2/+5
* Added the special file examples/todo.vhdRodrigo Alejandro Melo2017-11-161-0/+20
* Examples were corrected according to GHDL complainsRodrigo Alejandro Melo2017-11-165-8/+10
* Squelch some trailing whitespaceLarry Doolittle2017-11-124-17/+16
* Rework some examples so resulting Verilog compilesLarry Doolittle2017-11-104-7/+94
* New make target: verilogcheckLarry Doolittle2017-11-102-0/+23
* New rem before END PROCESSLarry Doolittle2017-11-101-0/+32
* Experiment with OTHERS logicLarry Doolittle2017-11-091-0/+17
* Fixes in examples and translated examples to avoid some complains of iVerilogRodrigo Alejandro Melo2017-02-194-14/+14
* Promoted unsupported BASED NUMBER from warning to errorRodrigo Alejandro Melo2017-02-191-1/+1
* Added analysis of examples with GHDLRodrigo Alejandro Melo2017-02-1413-33/+37
* Added scientific notation supports for integers and floatsRodrigo Alejandro Melo2017-02-091-0/+13
* vhd2vl-2.4Larry Doolittle2015-09-201-0/+3
* vhd2vl-2.3Larry Doolittle2015-09-201-0/+205
* vhd2vl-2.2Larry Doolittle2015-09-2011-0/+1314
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