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path: root/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
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* Add PROC_MEM_TO_USE to SBEspashabk-in2018-04-131-1/+1
* Abist proc update for SBE changesAbhishek Agarwal2018-04-091-0/+4
* Scommable check before L2/L3 Purge in MPIPL PathRaja Das2018-03-221-0/+7
* Adding attribute to detect which processor we can use for alt-memoryElizabeth Liner2018-03-071-0/+4
* Axone support to TP stopclocksSoma BhanuTej2018-03-021-0/+4
* Remove workaround for DD1 SW reset for XIVESachin Gupta2018-01-261-4/+0
* MCD disable workaround for HW423589 (option1)Joe McGill2018-01-121-1/+5
* disable ECC bypass for Cumulus DD1.0Joe McGill2017-12-191-0/+4
* support customized application of filter PLL buckets from AW MVPD keywordJoe McGill2017-12-121-0/+4
* Adding attribute to turn memory early data onLuke C. Murray2017-12-051-0/+4
* Chip address extension workaround for HW423589 (option2), part1Joe McGill2017-12-011-0/+16
* remove NV iovalid assertion from FW and add scan inits to resolve glsmux xstateJoe McGill2017-11-281-0/+4
* Axone UpdateAnusha Reddy Rangareddygari2017-10-241-0/+10
* Remove HB incorrect setting of ATTR_DD1_SLOW_PCI_REF_CLOCKThi Tran2017-10-041-1/+1
* Update p9_sbe_load_bootloader Hwp to receive the addr-key stash-2Raja Das2017-08-111-0/+4
* Use DD1 SW reset for XIVE unit until we get HW reset working in DD2crgeddes2017-07-311-1/+4
* TP, Nest FIR updates -- DD2 updates to match RAS XMLJoe McGill2017-07-261-0/+4
* p9_sbe_tracearray: Nimbus DD2 updatesJoachim Fenkes2017-07-241-0/+4
* PM: Delete deprecated attributesGreg Still2017-07-141-1/+1
* Create dmi.pll.scan.initfileBen Gass2017-07-141-0/+4
* HW414700 checkstop on UEs and disable core ECC counterLuke C. Murray2017-07-131-0/+4
* mc_pll_bucket attributeAnusha Reddy Rangareddygari2017-07-121-0/+4
* dcc skew adjust procedure updateAnusha Reddy Rangareddygari2017-07-121-0/+9
* Cumulus proc updatesAnusha Reddy Rangareddygari2017-07-121-0/+5
* p9_sbe_select_ex: add fused core booting supportGreg Still2017-07-031-0/+5
* L3 update -- p9_suspend_ioThi Tran2017-06-261-1/+4
* add support for OBUS PLL bucketsJoe McGill2017-06-231-0/+16
* Check Scratch Register 3 bit 7 and set new ATTR_SECURE_SETTINGSMike Baiocchi2017-06-071-0/+4
* future proof EC feature attributes, add missing P9N DD2 initsJoe McGill2017-05-311-2/+2
* L3 updates -- p9_build_smp, p9_fbc_utilsJoe McGill2017-05-281-0/+5
* p9_sbe_nest_initf -- add HWP support to scan n3_br_fureJoe McGill2017-05-191-0/+5
* p9_hcd_cache_dcc_skewadjust_setupAnusha Reddy Rangareddygari2017-05-111-0/+9
* NMMU Nimbus dd2 scom/scan updates, updated commentsEmmanuel Sacristan2017-05-111-0/+4
* p9_sbe_attributes.xml -- add entries for effective FBC IDsJoe McGill2017-05-041-0/+8
* Fix for HW397129-set bit 52 in the ALTD_OPTION reg to keep MC fastpath enabledCHRISTINA L. GRAVES2017-04-061-0/+6
* p9_sbe_chiplet_reset,p9_sbe_arrayinitAnusha Reddy Rangareddygari2017-03-291-0/+8
* Attribute support of customization of Nimbus DD1 PCI reference clock speed.Thi Tran2017-03-231-1/+5
* Add ec_abst ring to p9n.hw_imageThi Tran2017-03-101-0/+4
* HW399609: DD1 changing core/nest hang limit or hang pulse dividerYue Du2017-02-241-0/+4
* Removing ATTR_PROC_FABRIC_ADDR_BAR_MODEThi Tran2017-02-211-4/+0
* Make ATTR_CHIP_UNIT_POS virtualSantosh Puranik2017-02-191-65/+2
* Workaround to fix issue where Powerbus loses track of EQs in DD1Raja Das2017-02-161-0/+4
* ATTR_CHIP_EC_FEATURE_CORE_TRACE_SCOMABLE attribute in SBEspashabk-in2017-02-031-0/+4
* Control NDL training updateAnusha Reddy Rangareddygari2017-01-311-0/+4
* VITAL cleaning for DD2Anusha Reddy Rangareddygari2017-01-241-5/+1
* p9_sbe_tp_chiplet_init3 -- disable TP TOD hang pulseJoe McGill2017-01-241-0/+4
* Set plck as default mode in ATTR_BOOT_FLAGSSantosh Puranik2017-01-221-1/+1
* p9_sbe_chiplet_reset -- drive PCIE PLL from SS filter PLL for DD1.xJoe McGill2017-01-171-1/+5
* HW396520: DD1 workaround skip flushmode inhibit drop in cache hwpYue Du2016-12-201-0/+4
* Remove unused SBE attributesSantosh Puranik2016-11-281-126/+1
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