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author | Joe McGill <jmcgill@us.ibm.com> | 2017-05-19 08:11:55 -0500 |
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committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-05-31 04:38:57 -0400 |
commit | 63b18ac1cc2cc13ba60eced75f363c5ec3f30ec2 (patch) | |
tree | c24c8f3db78279b22191851405f16ccc736a9195 /src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml | |
parent | 5a69ee27dc16621ee71b65a460b52bf9eeb65b38 (diff) | |
download | talos-sbe-63b18ac1cc2cc13ba60eced75f363c5ec3f30ec2.tar.gz talos-sbe-63b18ac1cc2cc13ba60eced75f363c5ec3f30ec2.zip |
future proof EC feature attributes, add missing P9N DD2 inits
redefine EC feature attributes, using inverse logic where required, to qualify
inits specific to P9N DD1 where possible, to eliminate need for updates for
future chips in plan
attempt to remove usage of generic P9N_DD1_SPY_NAMES and P9N_DD2_SPY_NAMES
attributes added to support initial P9NDD2 engineering data -- several spies
were not being set as a result
-----------------
initfile updates:
-----------------
p9.cme.scan.initfile
add HW391162, SCAN_SICR_TLBIE_QUIESCE feature attributes
p9.core.common.scan.initfile
remove fused core init, it was applying scan default for P9N DD1 and is
not needed for P9N DD2+ given fuse controls
p9.core.scan.initfile
add CORE_P9NDD1 to qualify P9N DD1 specific register hierarchy and
dial programming
replace usage of P9N_DD1_SPY_NAMES, P9N_DD2_SPY_NAMES using CORE_P9NDD1
and inverse, to pick up initial pass at P9C DD1 inits
p9.cxa.scom.initfile
add CXA_P9NDD1_SPY_NAMES to qualify P9N DD1 specific register hierarchy
p9.ddrphy.scom.initfile
add DDRPHY_P9NDD1_SPY_NAMES to qualify P9N DD1 specific register hierarchy
p9.dpll.scan.initfile
remove POSTDD1N_DPLL_SETTINGS feature attribute, use DD1_DPLL_SETTINGS
attribute and inverse to drive inits
p9.l2.scan.initfile
invert definition of OPTIMAL_LARX_STCX_PERF, HW409069 feature attributes
p9.l3.scan.initfile
p9.l3.scom.initifle
remove OPTIMAL_LCO_SCOM, HW396230_SCOM feature attributes
use HW386657, HW396230 attributes to drive inits
p9.mca.scom.initfile
add MCA_P9NDD1_ASYNC to differentiate asynchronous boundary crossing
programming and dial name differences between P9N DD1, P9N DD2
p9.mmu.scan.initfile
p9.mmu.scom.initfile
invert definition of NMMU_DMT_DD2, NMMU_ISS734_DD2_1 feature attributes
p9.ncu.scan.initfile
p9.ncu.scom.initifle
remove HW396230_SCOM, use HW396230 attribute to drive inits
p9.npu.scom.initfile
remove usage of P9N_DD1_SPY_NAMES, refactor CONFIG_ENABLE_PBUS specification
to work for both P9NDD1, P9NDD2 ENGD
p9.obus.scan.initfile
remove EC qualification of OBUS FIR mask for simulation
sample.ec.scan.initfile
remove testcase requiring use of P9N_DD1_SPY_NAMES, properties of
testcase are covered by other tests
-----------------
HWP updates:
-----------------
p9_xip_customize
add customization of epsilon attributes for NMMU application
p9_chiplet_scominit
invert definition of P9_NDL_IOVALID feature attribute
remove usage of P9N_DD1_SPY_NAMES
p9_npu_scominit
replace usage of P9N_DD1_SPY_NAMES with SETUP_BARS_NPU_DD1_ADDR
p9_sbe_tracearray
invert definition of CORE_TRACE_SCOMABLE feature attribute
p9_sim_get_nia
remove usage of P9N_DD1_SPY_NAMES, directly process CT/EC attributes
(ok as this HWP is used for VBU sim only and not consumed by FW)
Change-Id: I63bfe8a4bfb8824b94e35a3688a6c69eecc1cf01
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40911
Reviewed-by: SHELTON LEUNG <sleung@us.ibm.com>
Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40915
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml')
-rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml index cac558af..e00c1e77 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml @@ -326,7 +326,7 @@ attribute tank <!-- Pervasive EC attributes --> <entry> - <name>ATTR_CHIP_EC_FEATURE_CORE_TRACE_SCOMABLE</name> + <name>ATTR_CHIP_EC_FEATURE_CORE_TRACE_NOT_SCOMABLE</name> <virtual/> </entry> <entry> @@ -401,7 +401,7 @@ attribute tank </entry> <entry> - <name>ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2</name> + <name>ATTR_CHIP_EC_FEATURE_NMMU_NDD1</name> <virtual/> </entry> <entry> |