| Commit message (Collapse) | Author | Age | Files | Lines |
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using SBE_AXONE_CONFIG compile flag for axone specific changes
Change-Id: Ibbbb69d6f8d87b4cbbd011fa5af4f496e5106335
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64915
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64917
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
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As a temporary workaround for SW440738, ignore errors after LPC init
so we don't halt the IPL for a benign LPC error on the alt master LPC.
If the master LPC happens to have a problem we'll find out soon enough.
Change-Id: I2d97efe6b49bfab83b834dde31ed878588339bd0
CQ: SW440738
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65767
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65776
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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This reverts commit 19228973bc00b3b9433470177c1878c46ab65450.
Change-Id: I131098b902f3ce99c9aab35bab5ff20b3e2a4548
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64801
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64812
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I90c6ecd6e553d36b2f34ba0949cdfce3938ce1c1
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64297
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64299
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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- Enabled EX check. even if it's EQ is functional
- one more check of clock power off which is
required for mpipl case.
- had one bug during l2/l3 stop clock which fixes status bit update.
Actually clock was stopped but the status bit was not set
in EQ_CLOCK_STAT register.
Key_Cronus_Test=PM_REGRESS
Change-Id: I7e8dbea00235ade5a692198dde7c2e6758809b9f
CQ:SW443537
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65360
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65364
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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This reverts commit 77b6c7e6b123b32e37d07db91b0478a938a4d4a7.
Change-Id: I95ffbf3404932c027093ea614ff979178292edeb
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65113
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65129
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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The LPC host controller has an interesting way to decode the timeout
value. The left 4 bits are used for the "short wait" timeout, while
the entire 8 bits are used for the "long wait" timeout. If the "short
wait" timeout is 0xF, it is taken to be infinite, causing the host
controller to hang if the slave doesn't respond.
Change the timeout value from 0xFE to 0xEF, the correct maximum value
that is not decoded to be infinity.
Change-Id: Iaf1a5119a87338c24b1e324d814ade0b30353360
CQ: SW442999
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64850
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
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Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64856
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
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-Code was using EX target, which only results in core 0 working
Change-Id: I2106a836f9ab73b32a37665758fbc6f8ab3a888c
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64403
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Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64404
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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HW 446279 - disable update for compat and native modes
HW 439321 - disable update for compat, enable for native mode
HW 443004 - disable update for compat and native modes
HW 446453 - disable update for compat, enable for native mode
Change-Id: I3dd1ed6075ff473adbaf342671dd977c53fb2f06
CQ: HW446279
CQ: HW439321
CQ: HW443004
CQ: HW446453
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64067
Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com>
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Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64082
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Create EC feature attribute and user override attribute to control application
of synchronized spreading. Default to enable synchronized spreading on
Axone only.
p9_sbe_npll_setup
Conditionally skip existing unsynchronized spread enablement
p9_tod_init
Conditionally invoke spread sync routine after TOD network is running
p9_ss_pll_sync
Remove from repository, shift code into p9_tod_init to prevent
need for mirroring into downstream repositories for FW consumption
Change-Id: Ic32c800d58c260136b45fe9561989987d0a97ceb
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63494
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Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63503
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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- set URMOR if MSR[S] bit is set in p9_sbe_load_bootloader
- clear CPMMR[Runtime Wakeup Mode] in all cores in p9_sbe_select_ex to ensure
Hostboot starts from known state
Change-Id: I572a1d9e0ebf8e194c811e2b8c176d145b7361e3
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/61812
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
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Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/61817
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Including the dummy file so that the platforms could mirror
this file without breaking existing implementation.
Will follow up with separation of lpc_rw into source file on
top of mirrored commits
Change-Id: I4596af3a8740cb9593f135a0138e84299a5946ac
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64298
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Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65269
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
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No secure accelerators in P9, so avoid enabling nmmu smf bits
that will otherwise cause sm table walk hangs. Nmmu will gate off addr15
when mm_cfg_xlat_ctl_urmor(0:2)=0b000.
Change-Id: Ib008d6be5d32f45ebb2b66600e45828decf6fbf4
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64064
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Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Emmanuel Sacristan <esacris@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64070
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Key_Cronus_Test=PM_REGRESS
Change-Id: I34f08519d2c86fec2f0ee0feb96a62bd826e31fa
CQ: SW440301
cmvc-prereq: 1063483
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/61438
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Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62502
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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The sequence to switch the LPC HC clock onto the nest clock temporarily
was incorrect as it used the TP CPLT_CTRL0 register inasted of N3, so it
never really switched the clocks during reset. Also, for good measure,
keep the clock switched to the nest clock while we're resetting the LPC
bus.
(Bonus change: Decrease the sim delay cycles waiting for a command to
complete.)
Change-Id: I5e77fa056204639a96aad9c1eec4b7bc76d8e54b
CQ: SW439536
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63279
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Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63286
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: Ieba2a677f48c9632e41020b9a48be7375c6eb31a
CQ: SW437518
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62384
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
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Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62400
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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62028 added a workaround for SW 430383, using a manual re-scan of the ring
hardcoded to flip the desired bits because engineering data was not yet
available for the necessary spies
This commit removes the SBE manual scan sequence and sets the necessary
chicken switches by the newly added spy entries
Change-Id: I912f190ab44c320f9bd142ce626570d34ec0b00f
CQ: SW438480
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62675
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Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62710
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Key_Cronus_Test=PM_REGRESS
Change-Id: I388c81cc1af356231daa4a11702a3a84dcc222c9
CQ: SW437797
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62302
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Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62326
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I7e3b39bb75ad8ee3983f4b4352d08369fe6bfc5c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62065
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Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62074
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Reseting the engines potentially causes another to send the PM Malf
Alert to PHYP. Disable in PM Reset and let SGPE re-enable in PM Init.
Added a similar safe check and disable in MPIPL path for pm_suspend
Change-Id: If9fd572d156a8f280b0fd204175e5ccf0969b249
CQ: SW436905
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62135
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Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62298
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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p9_mss_eff_grouping.C:
- determines whether secure mem is requested, reserves smf space
- always reserve smf at end of range because of end-of-range bit
- set addr15 when reporting smf base address
- mask off group_id(0) via chip address extension if smf is enabled
- updated to set value of attr_smf_enabled
- enhanced error reporting with smf config/supported values
- made values reported to attr_mss_mcs_group_32 more clear
p9_mss_setup_bars.C:
- set MCFGPA/MCFGPMA registers with SMF data
- fixed scom registers for MCFGPA/MCFGPMA hole setup
- added note to leave MCFIR_invalid_smf masked for HW451708/HW451711
- added assert to check for HOLE1 and SMF enable overlaps
p9_query_mssinfo.C:
- updated to print out SMF reservations
- print out HTM/OCC/SMF reservations regardless of mirroring enable
p9_fbc_utils.C:
- prevent group_id(0)=1 from affecting mappable memory ranges
p9_sbe_fabricinit.C:
- mask off group_id(0) via chip address extension if smf is enabled
p9_setup_sbe_config.C, p9_sbe_attr_setup.C:
- use scratch_reg6 bit(16) to pass smf_config value
initfiles:
- removed setup to use other addr bits as secure bit; core only uses addr15
- added setup for ncu addr15 value in hcode
- always set addr15 config bit in bridge unit if smf is supported
- set addr15 bit across all mcs if smf is enabled
- added in settings to enable smf in nmmu unit
- hardcode group_id(0) bit in chipext mask for bridge unit if smf is supported
attributes:
- ATTR_SMF_ENABLE is a system level attribute
- changed SMF_ENABLE->SMF_CONFIG; smf_enabled will be (config && supported)
CQ:HW451708
CQ:HW451711
Change-Id: I6cf85600354baa322e959c922f596ecc5c68a458
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57322
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Dev-Ready: Brent Wieman <bwieman@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57347
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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CQ: SW437571
Change-Id: I9101adc63225a97aeddf445519fa660d961c3d9c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61463
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61471
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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52512 removed code related to the DD1 SW based INT reset sequence, to leave
only the HW based reset in production code for DD2 and beyond. It also
erroneously removed the call to/code for p9_int_scrub_caches.
This commit restores the subroutine, and invokes it prior to the HW
quiesce/sync reset into order to scrub/flush the EQC, VPC, IVC, and SBC caches.
Change-Id: I051117e3a18c55aea7267e53eea1652f0cff9790
CQ: SW431898
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62227
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62243
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I2d9aed7833a1bf43c797689d50ff32794ef54cff
CQ: SW430383
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62028
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62042
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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On Cumulus, set up the oscerr mask (0102001A) such that errors on
unused MF/PCI oscillators are masked (based on the setup in RC3),
making sure the corresponding FIR bit (TP LFIR bit 37) will not
report false positives.
Keep the mask constant for Nimbus as only MF oscillator 0 is in use
there.
This reverts most of commit ce194c5cd773bdabd093b3aa44c2b3d3bcfb58e5
because a correct mask setting here obviates the need for selective
FIR masking.
Change-Id: Ib49704fb50fc1e62168cc4cd06841d068c488914
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61365
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61370
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Add an external FFDC collection procedure that will dump the LPC
register spaces, make sure it is called if after LPC setup an OPB
error is registered.
Change-Id: I91046a6a3814ba94abd878f860e08f1b1338390b
CQ: SW435433
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57803
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60994
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: Ic7cab359607c84eeec32e2e95270706e8c0075f1
CQ: SW434802
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61193
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61204
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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During the clock_test2 substep, the procedure would unconditionally
clear use_osc_1_0 from ROOT_CTRL3, which turns the use_osc field (that
has been set up in istep 0) into an invalid value and breaks redundant
PCI clock failover.
Not removing that piece of code altogether because it does not appear
to hurt anything on Nimbus and it was explicitly requested by Uli back
in the Nimbus days, even though we don't remember his rationale.
Change-Id: Ieffe1946980a65c302f60d80f83b527e24d74b3b
CQ: SW434930
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61188
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Manish K. Chowdhary <manichow@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61230
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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p9_adu_access.C
p9_adu_setup.C
save current_err to local return code object at start of exit path,
and return the saved value at exit (prior code was clobbering
current_err by call to cleanup routines)
Change-Id: I2f247ba2e93c673b3581e3ebe1504d4f05cb3a24
CQ: SW434090
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60607
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60618
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: Ib2614f887a3da7801db9d8680520e21daef90fba
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60435
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60443
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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1. On PENDING/INVALID_STATE RCs, need some FFDC and service actions on FSP
using regular FAPI mechanisms like FAPI_ASSERT and register ffdc colletion
2. SBE still uses existing mechanism and restrictions - optimized for space
a. no fapi error xml based callbacks
b. no fapi error xml based register ffdc collection
c. max local ffdc members < 20
d. depends on p9_collect_deadman_ffdc for FFDC with RC TIMEOUT
3. Compile out extra code on SBE builds
Change-Id: Id35f9a7dbfc7e423bd7cf0846f493a8270a48cd6
CQ: SW430391
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60320
Reviewed-by: RANGANATHPRASAD BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60391
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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p9_sbe_scominit:
unmask all OBUS EXTFIR bits, use PB CENT FIR 14 to mark update
for downstream code (qualify XBUS/OBUS EXTFIR updates to apply to PPE
platform only)
p9_fab_iovalid:
conditionally unmask OBUS EXTFIR based on state of PB CENT FIR 14
(will handle unmasking here when insecure -- Cronus or old SBE images)
p9_obus_extfir_setup:
new HWP for HB to call, mask OBUS EXTFIR bits for unused busses
Change-Id: I07e7da4a7c61c041451ff4ddfeec3c266385d404
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60358
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
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Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60361
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TP LFIR 37 is meant to be marked recoverable for Cumulus
60118 unmasked the bit, but the default action register settings
are programmed to trigger a checkstop. This adjust the action1 register
default to recoverable.
Change-Id: I8d07fdac8eb060ba10929133fdbe93621b8b53e7
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60244
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Dev-Ready: Brent Wieman <bwieman@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60261
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: Id216f65d5c240d88c4db62e374c9f3278d623fbb
CQ: SW432374
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60118
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Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60125
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I9c0a7224c3880ab40bb9111d8f66449912029e2f
CQ: SW431474
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59707
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59713
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Put the oscswitches into reset by deasserting PGOOD before we turn on
clocks, to make sure they fall into a reliable defined state when we
assert PGOOD during p9_clock_test.
Update the set values of root controls with preliminary sys oscswitch
tweak bits; to be refined after full redundant oscillator bringup.
Refactor some code to make procedure more readable.
Change-Id: Ib634d135b1932c2b7d5d88ba1689c5e3a20a9c7e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58826
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Dev-Ready: Joachim Fenkes <fenkes@de.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59053
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I641636e54dcc615cdf8f2de6f43d6878275113bf
CQ: SW427932
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59591
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59606
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I6ec5550871bcdbab64749bd90f2f8bf4354fd2b8
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58400
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58568
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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pervasive_attribues.xml:
Create new platinit attribute -- ATTR_MRW_FILTER_PLL_BUCKET
System specific value for Filter PLL bucket selector (init=0), set by MRW
- if non-zero, this value will directly set ATTR_FILTER_PLL_BUCKET,
which is used by SBE to select the override to apply
- if zero, MVPD MK keyword will set ATTR_FILTER_PLL_BUCKET
p9.filter.pll.override.scan.initfile:
Repurpose overrides built for Cumulus, to produce 0.2% down spread
Nimbus overrides still enable control of BGoffset
p9_xip_customize.C:
Consume ATTR_MRW_FILTER_PLL_BUCKET and use logic above to
set ATTR_FILTER_PLL_BUCKET
Change-Id: I2ea799179632d36251027a1d4468c6c89bfa6e00
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57988
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Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58003
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Commit addresses some coding errors in HWP. As a result of these
FFDC variables were getting populated with register data. Commit
also adds HWP wrapper for assisting debug in cronus environment.
Key_Cronus_Test=PM_REGRESS
CQ: SW427994
Change-Id: I5acff6bf85b5cfb9b1a582cb879dcb282e9d6809
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58417
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Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58430
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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- configure the fabric & unit snooper logic to operate in ordered/p8 tlbie mode
- prohibit the nest mmu from snooping tlbie
- adjust NCU tlbie stall settings
- revert HW419330 fix on Cumulus only
Change-Id: Idf18f81b08c4fb6e372fa4c544c023a8820bb37b
CQ: HW440920
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56406
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56415
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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-Fixes DPLL Ownership issues during Pstate Start
-Fixes WOF Enablement and Quad/Core Active Update(STOP11/5) livelock
scenario
-Fixes PM Complex Suspend and Quad/Core Active Update(STOP11/5)
livelock scenario
-Fixes VDM Droop Suspend STOP entries livelock scenario
Key_Cronus_Test=PM_REGRESS
Change-Id: I14a0dece4c74bc04618f7d1f3838dbe273bace94
CQ: SW425778
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57191
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57255
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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CMVC-Prereq: 1051830
Change-Id: I21b0d9187443f2727f83df310bca2fb3ae0fd80c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55376
Dev-Ready: Matt K. Light <mklight@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56834
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I4907eea62c2fa85bdf9ed193d1820fba84afc82f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57530
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57534
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
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- Increase timeout in PM Complex Suspend from 10ms -> 500ms
- Disable CME monitoring of PGPE heart beat loss before halting PGPE
Key_Cronus_Test=PM_REGRESS
Change-Id: I3fbb435ce694e7590e9e9570107347a621828402
CQ: SW424102
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56884
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56903
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Change-Id: I938d01f60907444b65b2f3b08d0fdfc59433dc79
CQ: SW424941
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57399
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57404
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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In core stopstate2, only checking the vdd_pfet_disable_core is not
enough before scoming for C_CLOCK_STAT_SL, since in stopstate2 fences
are up, so need to check for fenced bit as well in C_NET_CTRL0 reg.
Change-Id: If99dd3d357b6e07c56417edae0868c03f2f0b720
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52993
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53809
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Change-Id: Ideb3c3d2bbdbce8b773d51b86d9f97f2e654ca56
RTC:189091
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56197
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56203
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Adding additional delay during polling for LPC status
Issue encountered in GSD2PIB mode Awan simulations only
Change-Id: I220843de8c37fa578ea26ea253345a380666a1d7
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56724
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Abhishek Agarwal <abagarw8@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56779
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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55058 added inits to prime the PPE for xlink psave
the register touched is in the blacklist, so it can't be touched
on slave chips via FSI in the ioe tl SCOM initifle -- this was
triggering HW CI failures
this commit simply shifts the register setup into the SBE,
where it can be performed securely
Change-Id: I57504ccfe4c5f7e71397d11c7468da42ec09f059
CQ: SW421691
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56252
Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56256
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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