shift OBUS FIR programming inits for secure boot

p9_sbe_scominit:
unmask all OBUS EXTFIR bits, use PB CENT FIR 14 to mark update
for downstream code (qualify XBUS/OBUS EXTFIR updates to apply to PPE
platform only)

p9_fab_iovalid:
conditionally unmask OBUS EXTFIR based on state of PB CENT FIR 14
(will handle unmasking here when insecure -- Cronus or old SBE images)

p9_obus_extfir_setup:
new HWP for HB to call, mask OBUS EXTFIR bits for unused busses

Change-Id: I07e7da4a7c61c041451ff4ddfeec3c266385d404
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60358
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60361

2 files changed, 8 insertions, 3 deletions

diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C
index a5ccda6d..1f6fc5d3 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C
@@ -250,13 +250,16 @@ p9_sbe_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
         FAPI_TRY(fapi2::putScom(i_target, PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG, l_scom_data),
                  "Error from putScom (PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG)");
 
-        // set spare/masked FIR bit as a signal to HB that the SBE will handle
-        // setup of XBUS related FIRs
+        // set spare/masked FIRs bit as a signal to HB that the SBE will handle
+        // setup of XBUS/OBUS related EXTIR bits
+#ifdef __PPE__
         FAPI_TRY(fapi2::getScom(i_target, PU_PB_CENT_SM0_PB_CENT_FIR_REG, l_scom_data),
                  "Error from getScom (PU_PB_CENT_SM0_PB_CENT_FIR_REG)");
         l_scom_data.setBit<PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_13>();
+        l_scom_data.setBit<PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_14>();
         FAPI_TRY(fapi2::putScom(i_target, PU_PB_CENT_SM0_PB_CENT_FIR_REG, l_scom_data),
                  "Error from putScom (PU_PB_CENT_SM0_PB_CENT_FIR_REG)");
+#endif
 
         // WEST
         FAPI_DBG("Configuring FBC WEST FIR");
@@ -309,8 +312,10 @@ p9_sbe_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
                  "Error from putScom (PU_PB_CENT_SM1_EXTFIR_ACTION0_REG)");
         FAPI_TRY(fapi2::putScom(i_target, PU_PB_CENT_SM1_EXTFIR_ACTION1_REG, FBC_EXT_FIR_ACTION1),
                  "Error from putScom (PU_PB_CENT_SM1_EXTFIR_ACTION1_REG)");
+#ifdef __PPE__
         FAPI_TRY(fapi2::putScom(i_target, PU_PB_CENT_SM1_EXTFIR_MASK_REG, FBC_EXT_FIR_MASK),
                  "Error from putScom (PU_PB_CENT_SM1_EXTFIR_MASK_REG)");
+#endif
     }
 
     // configure PBA mode switches & FIRs
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_xbus_fir_utils.H b/src/import/chips/p9/procedures/hwp/nest/p9_xbus_fir_utils.H
index eb54cdab..cd4f383b 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_xbus_fir_utils.H
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_xbus_fir_utils.H
@@ -62,7 +62,7 @@ const uint32_t X_PG_PBIOX2_REGION_BIT = 11;
 // one register per chip (encompassing all links), in N3 chiplet
 const uint64_t FBC_EXT_FIR_ACTION0       = 0x0000000000000000ULL;
 const uint64_t FBC_EXT_FIR_ACTION1       = 0x0000000000000000ULL;
-const uint64_t FBC_EXT_FIR_MASK          = 0x1F00000000000000ULL;
+const uint64_t FBC_EXT_FIR_MASK          = 0x0100000000000000ULL;
 
 const uint64_t FBC_EXT_FIR_MASK_X0_NF    = 0x8000000000000000ULL;
 const uint64_t FBC_EXT_FIR_MASK_X1_NF    = 0x4000000000000000ULL;