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| author | Yue Du <daviddu@us.ibm.com> | 2018-06-26 21:52:31 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-08-01 09:55:50 -0500 |
| commit | 77f8505ebf7819fe8bd04a5db50aca90b788c4b6 (patch) | |
| tree | 0e5d164863385ef4d2a19d30f41024c83801544a /src/import/chips/p9/procedures/hwp | |
| parent | e6fa241970133f461c9dc4bc37a18bfc383c55c7 (diff) | |
| download | talos-sbe-77f8505ebf7819fe8bd04a5db50aca90b788c4b6.tar.gz talos-sbe-77f8505ebf7819fe8bd04a5db50aca90b788c4b6.zip | |
PM: Prevent Core-L2 Quiesce from removing PM_EXIT upon SPWU
Key_Cronus_Test=PM_REGRESS
Change-Id: I34f08519d2c86fec2f0ee0feb96a62bd826e31fa
CQ: SW440301
cmvc-prereq: 1063483
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/61438
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62502
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C index a9967879..3d8a81ed 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -181,6 +181,16 @@ p9_hcd_core_stopclocks( } #endif + + //if a core is only in special wakeup and asserting pm_exit, + //then setting 6,7 of SICR will cause pm_exit to drop and + //the core will re-enter a power saving state + FAPI_DBG("Prevent Core-L2 Quiesce from removing PM_EXIT CME_SCOM_LMCR[22]"); + FAPI_TRY(putScom(l_quad, + (l_attr_chip_unit_pos < 2) ? + EX_0_CME_SCOM_LMCR_OR : EX_1_CME_SCOM_LMCR_OR, + (BIT64(22)))); + FAPI_DBG("Assert Core-L2/CC Quiesces via CME_SCOM_SICR[6,8]/[7,9]"); FAPI_TRY(putScom(l_quad, (l_attr_chip_unit_pos < 2) ? |
