summaryrefslogtreecommitdiffstats
path: root/src/import/chips/p9/procedures/hwp
Commit message (Collapse)AuthorAgeFilesLines
* Replaces NVDIMM flush sequence with CCSTsung Yeung2019-11-052-162/+179
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The current design relies on the power control logic to put the nvdimm into STR. There have been several defects opened on the nvdimm failing to save due to STR not entered but no indication of the function failing to execute. Therefore, the decision has been made to leverage CCS to issue STR and assert RESETn. This gives us full control of what goes onto the bus and not have to worry about STR getting exit due to unwanted mainline traffic. The same CCS sequence has already been exercised numerous times on AC powerloss path. Change-Id: Idd422beea72ee5902674562f5834c1ac9e79fe00 CQ:SW477735 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/85831 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/85880 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* PM: Fix DB0 HangRahul Batra2019-08-261-0/+1
| | | | | | | | | | | | | | | | | | | Key_Cronus_Test=PM_REGRESS Change-Id: I706ec7b87e777b736153d5765ced0a3f6cea5d96 CQ: SW470688 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81266 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: YUE DU <daviddu@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81560 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Add slbv, slbe extraction to p9_ram_core procedureJenny Huynh2019-08-251-1/+13
| | | | | | | | | | | | | Change-Id: I6efe5d4f8fbb9f893a2371acd108d9d1d3002ecd Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82496 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K Light <mklight@us.ibm.com> Reviewed-by: Thi N Tran <thi@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82502 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* p9_proc_gettracearray -- updates for AxoneJoe McGill2019-08-252-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p9_tracearray_defs.H: - adjust value of PROC_TB_LAST_AXONE_CHIP_TARGET, to cover NPU busses only - introduce PROC_TB_LAST_AXONE_MC_TARGET, to cover OMI busses that logically associate with MC pervasive targets p9_proc_gettracearray.H: - update proc_gettracearray_target_type to return TARGET_TYPE_MC for Axone OMI busses p9_sbe_tracearray.H: - update p9_sbe_tracearray_target_type to return TARGET_TYPE_PERV for Axone OMI busses p9_proc_gettracearray_wrap.C: - add eCMD looper to determine chip type - use chip type to swizzle target type returned by proc_gettracearray_target_type from MCBIST to MC, when running on Axone or Cumulus Change-Id: I5c729385c685ed3b1aac02f1f63b2c81f3e2f0e0 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82308 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Adam S Hale <adam.samuel.hale@ibm.com> Dev-Ready: Joseph J McGill <jmcgill@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82361 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Account for OMI technology in initial mcs setup for AxoneChristian Geddes2019-08-061-17/+65
| | | | | | | | | | | | | | | | | | | The scom registers that setup the memory channel's intial state get written during the SBE steps. The hwp that does this needs to be updated to account for the changes to the MCFGP0 register that happened between P9N/P9C and P9A. Change-Id: Icfa50177f9fefca3acabbbc41b60f65d280348e7 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81458 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Adam S Hale <adam.samuel.hale@ibm.com> Reviewed-by: Christian R Geddes <crgeddes@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81482 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Move to long term CLSCOM workaroundAdam Hale2019-08-061-2/+1
| | | | | | | | | | | | | | | | Change-Id: I33ff7d349b63c54794bf6acf806c89d22e5d9ac0 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81474 Reviewed-by: Adam S Hale <adam.samuel.hale@ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Dev-Ready: Adam S Hale <adam.samuel.hale@ibm.com> Reviewed-by: Devon A Baughen <devon.baughen1@ibm.com> Reviewed-by: SHELTON LEUNG <sleung@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81486 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Streamline the way PIB/NET are initialized between SBE and CronusJoachim Fenkes2019-07-303-73/+55
| | | | | | | | | | | | | | | | | | | | | | | | | Instead of p9_start_cbs swinging the PCB mux to PIB2PCB, do it in p9_sbe_tp_chiplet_init1. The PIBMEM repair code on the SBE does it this way already so no change is needed there. This way, even if we start the SBE but then run isteps in Cronus, both pieces of code will work correctly since they don't depend on previous steps leaving the mux in a specific state. Change-Id: I4a2bd53f813cbb0a00486effb156a3c2a7f4336a CQ: SW470122 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81162 Reviewed-by: Joseph J McGill <jmcgill@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Milton D Miller <miltonm@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Dev-Ready: Joachim Fenkes <fenkes@de.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81191 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* temporary mc inits to enable wider teamAdam Hale2019-07-171-2/+3
| | | | | | | | | | | | | | | Change-Id: Ic9adb821799b3383b90b8e9feb86815c9b28f7f2 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/79669 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Devon A. Baughen <devon.baughen1@ibm.com> Reviewed-by: BRIANA E. FOXWORTH <befoxwor@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/79874 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Disable BAR Temporarily to prevent STR exit during nvdimm handoverTsung Yeung2019-06-242-27/+85
| | | | | | | | | | | | | | | Change-Id: Ib7e95d8aa0b77570fec9c76211e78d790f540b06 CQ:SW468134 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/79219 Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/79375 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* update i2c bit rate divisor for p9aJoe McGill2019-06-151-2/+7
| | | | | | | | | | | | | | | | | p9a i2cm HW changes require nest/4/2/4 programming Change-Id: Ib29c307fa2250f5096578809e3d0cb10a027086e Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78640 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78664 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Add polling after STR entry to ensure port is in STR before asserting RESETnTsung Yeung2019-06-141-1/+55
| | | | | | | | | | | | | | | | Change-Id: Ic28ca541a578daccc0b9df6d8ffa99622c9eda38 CQ:SW465520 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78505 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78869 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* PM: WOV(OCS) HW Procedures Changes (1/2)Rahul Batra2019-06-141-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | 1st commit in the series of 2 commits for WOV(Over Current Sampling, OCS) Commit 1: WOV(OCS) HW procedures updates Commit 2: WOV(OCS) PGPE Hcode updates Key_Cronus_Test=PM_REGRESS HW-Image-Prereq: Ieabbc383d2bbbd1df8cf5a2ed5b503c860518cd8 Change-Id: I6234f0f60b9ed57b8b144159f3fe9c0b756df1e3 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70513 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70816 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* p9_sbe_npll_setup -- update SS enablement for p9aJoe McGill2019-06-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | Axone has two spread PLLs that can individually synchronized, so the TOD timer facility grew two enable bits. Set both of them to synchronize both PLLs at the same time. The enable bits are don't care on Nimbus/Cumulus so the procedure will still work the same way there. Check only the status of one PLL, knowing that if both are enabled, either both or none will get started by the TOD. This maintains Nimbus/Cumulus compatibility on the checking part. Change-Id: Ife3a5164037362f1c392146bd7e27ef69bb1a0cd Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78221 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78230 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* p9_sbe_chiplet_reset: Add missing OB3 clock muxes for AxoneJoachim Fenkes2019-05-161-2/+5
| | | | | | | | | | | | | Change-Id: Ied8f97e50aedad42d9a3b5f7d2156743b3f89dc1 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77289 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77372 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* p9_sbe_tracearray: Updates for AxoneJoachim Fenkes2019-05-053-35/+59
| | | | | | | | | | | | | | | | | | | | | | | | Add new trace bus names and trace array definitions for Axone. Some trace buses are just renamed, but I decided to add separate constants for clarity. Simplify the "can I dump the core trace arrays?" logic since no chips of the P9 family can have their core traces dumped via SCOM. Improve SBE size of ta_defs. Change-Id: I276f867a7fe9387fec9b7b216137767154ba1928 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67593 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67599 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* p9_sbe_nest_enable_ridi: Open up PCIe refclk driversJoachim Fenkes2019-04-281-1/+2
| | | | | | | | | | | | | | | | | As a fix for an X-state issue on Axone (HW476237), we added a root control bit that will inhibit the PCIe refclk drivers. Once the PCIe chiplets are initialized, we can lift this inhibit. Change-Id: I22562b3bb3d75c3a0d67a271c49d5c0f22218c3d Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70376 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70385 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* PM: Fixed error path handling of getscoms in HWP p9_query_core_access_state.Prem Shanker Jha2019-04-161-86/+58
| | | | | | | | | | | | | | | | | | | | | | | | When is core is in STOP2 or greater, HWP will not be able to SCOM clock status register of core. Use of FAPI_TRY to scom such a register returns failure to caller. With thisi, caller fails to understand if output status variables are good or not. Commit modifies this behavior to always return SUCCESS and a core state which is consistent with known status of core. Key_Cronus_Test=PM_REGRESS Change-Id: I6365ff0e52c3eb77d9d8ac749f9649a81cdadcac CQ: SW460324 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75267 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75338 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Update p9_mss_eff_grouping for Axone supportBen Gass2019-04-023-5/+5
| | | | | | | | | | | | | | | | Add p9a_omi_setup_bars procedure Add eclipse project files to .gitignore Change-Id: Ia18cd213ac8b3682e5718b3c631dad631b97170f Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67755 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67763 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* cleanup references to chip-centric EC feature attributesJoe McGill2019-03-221-5/+5
| | | | | | | | | | | | | | | | Change-Id: Ib777b27c6013a647ae86e6ff5973bab19faceb56 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71994 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Reviewed-by: Christopher W. Steffen <cwsteffen@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71999 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Update p9_l2_flush to check if purge is busy on anything prior to flush.Ben Gass2019-03-222-5/+89
| | | | | | | | | | | | | | | | | | | | | | | | | The previous check was only checking once if CMD_REG_BUSY is off. This will now check if CMD_PRGSM_BUSY is off, indicating the Purge engine is not busy with any requests at all. It will also poll on busy prior to issuing the flush. If PURGE_CMD_ERR is on prior to starting flush a warning will be printed via FAPI_DBG. PURGE_CMD_ERR will be cleared prior to issuing the purge. Change-Id: I120cc9a00d26da8cf2ca4ec6dd7d8f3006633b61 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72562 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: MURULIDHAR NATARAJU <murulidhar@in.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72582 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* PM HWP: Fix bug in stop clock procedure that effects mpiplPrasad Bg Ranganath2019-02-283-25/+39
| | | | | | | | | | | | | | | CQ:SW455762 Change-Id: I43080c575355499cddf19b6ee094e23c94445e66 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71581 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71596 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* HWP:Cache stop clocks complete fixPrasad Bg Ranganath2019-02-281-0/+9
| | | | | | | | | | | | | | | CQ:SW455762 Change-Id: Ia41ad689ebe7d1468855e8a9240a6701c372c435 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71955 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: YUE DU <daviddu@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71963 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* p9_sbe_npll_setup: Enable spread spectrum before starting PLLJoachim Fenkes2019-02-251-18/+8
| | | | | | | | | | | | | | | | | | | | | | | | | There's a synchronizer missing on the sscgen input of the filter PLLs, thus any changes to that input must be made before the PLL is taken out of reset, or the spread generator inside the PLL might start up in a skewed state, resulting in a broken spread profile. Thus, change the procedure to enable spread before taking the PLL out of reset, and also make sure we never try to synchronously enable spread. Change-Id: Ie0e545a6baf492d394a7d63d99ba5b83a0c46423 CQ: SW457204 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71886 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71912 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* p9_sbe_tp_chiplet_init3: Mask TOD error bit 62 (osclite switched)Joachim Fenkes2019-02-251-2/+2
| | | | | | | | | | | | | | | | | The bit is merely an indication about the cause of fail to TOD recovery, it should not be reported to PRD, so we mask it off. Change-Id: I99672b706a601dce43ef2f53d2583c94d6e3ca45 CQ: SW450308 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71184 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Lakshminarayana R. Kammath <lkammath@in.ibm.com> Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71827 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Adjust STR enter sequence to enable immediate entryTsung Yeung2019-02-131-8/+25
| | | | | | | | | | | | | | | | | Change-Id: Id6f2e59fbc3feb7cae69e39685b3c183fba6f2a1 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71532 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: Matt Derksen <mderkse1@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71536 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Implement PBA Cache-Inhibited 8B Rd/Wr AccessChristopher M Riedl2019-02-124-31/+68
| | | | | | | | | | | | | | | | | | | | | The PBA supports 8B cache-inhibited rd/wr operations via the OCB indirect-OCI access path. Also implemented necessary changes in the wrapper to support the PBA cache-inhibited operations. Turns out that the ADU cache-inhibited ops are broken in the wrapper so I undocumented them in the wrapper's usage/help string. Change-Id: Ic6f3d358a548a1750a779a7f17b223a275983419 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71166 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Kahn C. Evans <kahnevan@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71180 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* P9: NVDIMM SBE Support to Trigger Catastrophic SaveTsung Yeung2019-01-112-0/+293
| | | | | | | | | | | | | | | | | | | | - Adds attribute to indicate which ports contain NVDIMM - Subroutine to trigger CSAVE on ports with NVDIMM Change-Id: Ie77e23f7d15ccab3a8bb4ef0e6c35fec7829299d Original-Change-Id: I5fc9ead249dda0062ca3ac5237113688a22eb50c CQ:SW452306 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69314 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sunil Kumar <skumar8j@in.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70333 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* apply HW423589 option1 (MCD disable) workaround for p9n DD2.1Joe McGill2018-12-171-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | Current FW uses option2 (alternate MCD configuration) to workaround HW423589 for p9n DD2.1 hardware, which is desired for OP releases supporting GPUs. This commit adjusts the DD2.1 solution to option1 instead, and can be cherry-picked into the enterprise release branches to remove the per-socket memory resrictions which come as a side effect of the current option2 setup. Change-Id: I24ecf918a81964a3df6b1e3e18e60375d7646b45 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69718 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69845 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Leave scratch valid bits alone to allow HB to queryDean Sanner2018-11-291-15/+4
| | | | | | | | | | | | | | | | | | | | Current behavior of SBE is to set all the scratch 8 valid bits for all of the scratch registers, always. This behavior makes it impossible for Hostboot to determine if there was an actual override. Since the SBE always ensures valid settings in the scratch regs, leave the valid bits in original state so Hostboot can make its own determination. Change-Id: Iade385b289cb2300a4b7ed745981c4cac95a8b9c CQ: SW451891 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68101 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68107 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* p9_sbe_tp_chiplet_init: Fix missing semicolonsJoel Stanley2018-11-011-2/+2
| | | | | | | | | | | | | | | | | | The FAPI_DBG calls are missing closing semicolons which breaks the build for some users. Change-Id: If6b3b76668140a35910875d6329000451f046727 Signed-off-by: Joel Stanley <joel.stanley@au1.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67809 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67811 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Revert "Clear INT_CQ related firs after completing sync_reset in MPIPL"Christian R. Geddes2018-11-012-51/+0
| | | | | | | | | | | | | This reverts commit 9b1a1383bb554e9810f45717c3f44782c79411f3. Change-Id: I31b958d11dc1bbe058712e48831baa5945823af9 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68201 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68203 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Clear INT_CQ related firs after completing sync_reset in MPIPLChristian Geddes2018-11-012-0/+51
| | | | | | | | | | | | | | | | | | | | | | In the SBE steps of the MPIPL, the SBE calls a HWP called p9_sbe_check_quiesce. This function ensures that traffic on the powerbus is stopped prior to cycling the master core on and off. During this HWP a sync_reset is performed on the INT component. After this reset we have been told to clear out all of the related' INT_CQ firs. This commit adds in a new function which is called immediatly after sync reset and will clear all relevent scoms. Change-Id: Ia99a2f2d3f855823472f81b32baf44d25d7c4cad CQ:SW448121 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68020 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68023 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Mask NMMUFIR(7), NMMUFIR(36:39)Jenny Huynh2018-10-091-2/+2
| | | | | | | | | | | | | | | | | Mask nmmu internal timeout checkers to allow higher-level timeouts to handle proc callouts. Change-Id: I4484cd94666e0335bcc2169ffd9c9ab8dce4335a CQ:SW447361 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67020 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67028 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* SMF: clear HRMOR[15] in all modes so that secure mode won't hang coreGreg Still2018-10-051-5/+7
| | | | | | | | | | | | | | | | | Key_Cronus_Test=PM_REGRESS Change-Id: I26a98dfce1eb8123c79b35f2f4dc1783e16e411e Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66687 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Dev-Ready: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: YUE DU <daviddu@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66693 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* STOP:Dont clear pmc_pcb_intr_type0_pending in OISR1/OIMR1 registerPrasad Bg Ranganath2018-09-271-15/+26
| | | | | | | | | | | | | | | Key_Cronus_Test=PM_REGRESS Change-Id: I71aac7f826b0daa594de5f4db7a45ccd693f964f CQ:SW444760 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66511 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66519 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Mask early hang indicators from nmmu/vas unitJenny Huynh2018-09-261-4/+4
| | | | | | | | | | | | | | | | | | | | Masking nmmucqfir(1) and vasfir(15) since they are unit-level indicators of early hang. This will allow pbcentfir(9) to handle the reporting of any early hang conditions. Change-Id: I86acb2d781a6653d9d8c8622ed80da426fa66452 CQ: SW446662 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66492 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com> Reviewed-by: Daniel J. Henderson <hende@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66499 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Support 1byte data access on LPCspashabk-in2018-09-212-6/+40
| | | | | | | | | | | | | | | | | | | | Currently LPC driver supports only 4bytes data access, with this commit introducing support for 1byte and also a way to extend this to 2bytes. RTC: 194000 Change-Id: I7cb258425100c2d2a3e78f35f0aaf7da1c0e8508 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64174 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64176 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Move lpc_rw to a source filespashabk-in2018-09-193-66/+83
| | | | | | | | | | | | | | | | | | | Moving lpc_rw to its source file to avoid code duplication if more than one file includes lpc_utils.H. This is mainly required by SBE to use lpc_rw for virtual PNOR access. Change-Id: I7de30bcbae932307e0b63d8d42ae6ce050753339 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64296 Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64309 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* RAS_XML: updates to sync the XML with actual values from hardwareZane Shelley2018-09-171-1/+1
| | | | | | | | | | | | | | | | Change-Id: I590d6790cd391ff4be984001acd41c6a1ba48a06 CQ: SW445620 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63398 Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com> Reviewed-by: Benjamin J. Weisenbeck <bweisenb@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63841 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* IPL/STOP: Disable LCO when only two EXes are configuredYue Du2018-09-171-13/+1
| | | | | | | | | | | | | | | | | Key_Cronus_Test=PM_REGRESS Change-Id: I168f03dbd45da9da1c7f80e37ea508d7b56deec4 CQ: HW463903 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66065 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66066 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Axone only-IPL Procedures update to support SBE changesAbhishek Agarwal2018-09-104-35/+219
| | | | | | | | | | | | | | | Using SBE_AXONE_CONFIG compile flag for Axone specific changes Change-Id: I3d67c8f9ebba9fc18925ae02d1fff3cca8a9440b Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/53714 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/53735
* Initf procedure updates for Axone OMI ringsAnusha Reddy Rangareddygari2018-09-073-2/+83
| | | | | | | | | | | | | | | using SBE_AXONE_CONFIG compile flag for axone specific changes Change-Id: Ibbbb69d6f8d87b4cbbd011fa5af4f496e5106335 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64915 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64917 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* p9_sbe_lpc_init: Skip final error check for Fleetwood GA1Joachim Fenkes2018-09-071-0/+2
| | | | | | | | | | | | | | | | | | | As a temporary workaround for SW440738, ignore errors after LPC init so we don't halt the IPL for a benign LPC error on the alt master LPC. If the master LPC happens to have a problem we'll find out soon enough. Change-Id: I2d97efe6b49bfab83b834dde31ed878588339bd0 CQ: SW440738 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65767 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65776 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Revert "Initf procedure updates for OMI rings for Axone"Jennifer A. Stofer2018-09-073-65/+2
| | | | | | | | | | | | | This reverts commit 19228973bc00b3b9433470177c1878c46ab65450. Change-Id: I131098b902f3ce99c9aab35bab5ff20b3e2a4548 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64801 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64812 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Initf procedure updates for OMI rings for AxoneAnusha Reddy Rangareddygari2018-09-073-2/+65
| | | | | | | | | | | | | Change-Id: I90c6ecd6e553d36b2f34ba0949cdfce3938ce1c1 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64297 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64299 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PM:Some more cleanups in update_ec_eq procedure for core unit xstop casePrasad Bg Ranganath2018-08-314-0/+79
| | | | | | | | | | | | | | | | | | | | | | | | - Enabled EX check. even if it's EQ is functional - one more check of clock power off which is required for mpipl case. - had one bug during l2/l3 stop clock which fixes status bit update. Actually clock was stopped but the status bit was not set in EQ_CLOCK_STAT register. Key_Cronus_Test=PM_REGRESS Change-Id: I7e8dbea00235ade5a692198dde7c2e6758809b9f CQ:SW443537 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65360 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: YUE DU <daviddu@us.ibm.com> Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65364 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Revert "lpc_init: Correct LPC host controller timeout value"Jennifer A. Stofer2018-08-291-1/+1
| | | | | | | | | | | | | This reverts commit 77b6c7e6b123b32e37d07db91b0478a938a4d4a7. Change-Id: I95ffbf3404932c027093ea614ff979178292edeb Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65113 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65129 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* lpc_init: Correct LPC host controller timeout valueJoachim Fenkes2018-08-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | The LPC host controller has an interesting way to decode the timeout value. The left 4 bits are used for the "short wait" timeout, while the entire 8 bits are used for the "long wait" timeout. If the "short wait" timeout is 0xF, it is taken to be infinite, causing the host controller to hang if the slave doesn't respond. Change the timeout value from 0xFE to 0xEF, the correct maximum value that is not decoded to be infinity. Change-Id: Iaf1a5119a87338c24b1e324d814ade0b30353360 CQ: SW442999 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64850 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64856 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Use core target for HRMOR/URMOR scoms in p9_sbe_load_bootloaderDean Sanner2018-08-291-2/+2
| | | | | | | | | | | | | | | -Code was using EX target, which only results in core 0 working Change-Id: I2106a836f9ab73b32a37665758fbc6f8ab3a888c Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64403 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64404 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* nest updates for p9c DD1.3 native and p9c DD1.2 compatibility modesJoe McGill2018-08-291-4/+4
| | | | | | | | | | | | | | | | | | | | | | | HW 446279 - disable update for compat and native modes HW 439321 - disable update for compat, enable for native mode HW 443004 - disable update for compat and native modes HW 446453 - disable update for compat, enable for native mode Change-Id: I3dd1ed6075ff473adbaf342671dd977c53fb2f06 CQ: HW446279 CQ: HW439321 CQ: HW443004 CQ: HW446453 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64067 Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64082 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
OpenPOWER on IntegriCloud