diff options
Diffstat (limited to 'src/usr')
574 files changed, 62775 insertions, 10229 deletions
diff --git a/src/usr/cxxtest/TestSuite.C b/src/usr/cxxtest/TestSuite.C index 92feb4886..3b1499889 100755 --- a/src/usr/cxxtest/TestSuite.C +++ b/src/usr/cxxtest/TestSuite.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2017 */ +/* Contributors Listed Below - COPYRIGHT 2011,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -32,7 +32,6 @@ #include <stdarg.h> #include <arch/ppc.H> #include <string.h> - #include <cxxtest/TestSuite.H> trace_desc_t *g_trac_test = NULL; @@ -43,6 +42,9 @@ namespace CxxTest /******************************************************************************/ // Globals/Constants /******************************************************************************/ +//This is a list of testcases that are expected to run in a serial manner +// example: std::vector<const char *> CxxSerialTests{"libtestrtloader.so"}; +std::vector<const char *> CxxSerialTests{"libtesthwas.so"}; // // TestSuite members @@ -104,6 +106,43 @@ void doFailTest( ) } +void sortTests(std::vector<const char *> & i_list, + std::vector<const char *> & o_serial_list, + std::vector<const char *> & o_parallel_list) +{ + o_serial_list.clear(); + o_serial_list.reserve(32); + o_parallel_list.clear(); + o_parallel_list.reserve(32); + + //Loop through list of all tests + for(std::vector<const char *>::const_iterator i = i_list.begin(); + i != i_list.end(); ++i) + { + bool is_serial = false; + + for(std::vector<const char *>::const_iterator j = CxxSerialTests.begin(); + j != CxxSerialTests.end(); ++j) + { + if (0 == strcmp(*i, *j)) + { + is_serial = true; + } + } + + if (is_serial) + { + TRACFCOMP( g_trac_test, "%s is a serial test",*i); + o_serial_list.push_back(*i); + } + else + { + TRACFCOMP( g_trac_test, "%s is a parallel test",*i); + o_parallel_list.push_back(*i); + } + } +} + /** * @brief Implement Fail action in unit tests * @@ -115,10 +154,11 @@ void doFailTest( ) void doFailTest( const char *filename, uint32_t linenum ) { - TRACDCOMP( g_trac_test, + TRACFCOMP( g_trac_test, "!!! > Test %s Failed at line %d ", filename, linenum ); + if(g_FailedTests < CXXTEST_FAIL_LIST_SIZE) { memcpy(g_FailedTestList[g_FailedTests].failTestFile, diff --git a/src/usr/cxxtest/cxxtestexec.C b/src/usr/cxxtest/cxxtestexec.C index 145537f66..b32c661f2 100644 --- a/src/usr/cxxtest/cxxtestexec.C +++ b/src/usr/cxxtest/cxxtestexec.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2017 */ +/* Contributors Listed Below - COPYRIGHT 2011,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -32,7 +32,6 @@ #include <sys/sync.h> #include <errl/errlentry.H> #include <errl/errlmanager.H> -# #include <initservice/taskargs.H> #include <cxxtest/TestSuite.H> @@ -46,7 +45,6 @@ namespace CxxTest // prototype void cxxinit( errlHndl_t &io_taskRetErrl ); - trace_desc_t *g_trac_cxxtest = NULL; TRAC_INIT(&g_trac_cxxtest, CXXTEST_COMP_NAME, KILOBYTE ); @@ -75,6 +73,8 @@ void cxxinit( errlHndl_t &io_taskRetErrl ) } cxxtask; errlHndl_t l_errl = NULL; std::vector<const char *> module_list; + std::vector<const char *> parallel_module_list; + std::vector<const char *> serial_module_list; std::vector<cxxtask_t> tasks; tid_t tidrc = 0; @@ -94,12 +94,16 @@ void cxxinit( errlHndl_t &io_taskRetErrl ) // count up the number of viable modules ahead of time TRACDCOMP( g_trac_cxxtest, "Counting CxxTestExec modules:" ); + //Get all modules, then sort into parallel and serial lists VFS::find_test_modules(module_list); - // start executing the CxxTest modules + CxxTest::sortTests(module_list, serial_module_list, parallel_module_list); - TRACFCOMP( g_trac_cxxtest, ENTER_MRK "Execute CxxTestExec, totalmodules=%d.", - module_list.size()); + // start executing the CxxTest modules + TRACFCOMP( g_trac_cxxtest, ENTER_MRK "Execute CxxTestExec, totalparallelmodules=%d, totalserialmodules=%d (overall total:%d)", + parallel_module_list.size(), + serial_module_list.size(), + parallel_module_list.size()+serial_module_list.size()); printkd( "\n Begin CxxTest...\n"); __sync_add_and_fetch(&CxxTest::g_ModulesStarted, 1); @@ -111,8 +115,58 @@ void cxxinit( errlHndl_t &io_taskRetErrl ) TS_FAIL("Error logs committed previously during IPL."); } - for(std::vector<const char *>::const_iterator i = module_list.begin(); - i != module_list.end(); ++i) + for(std::vector<const char *>::const_iterator i = serial_module_list.begin(); + i != serial_module_list.end(); ++i) + { + __sync_add_and_fetch(&CxxTest::g_ModulesStarted, 1); + + TRACFCOMP( g_trac_cxxtest, + "Now executing Serial Test Cases!"); + + // load module and call _init() + l_errl = VFS::module_load( *i ); + if ( l_errl ) + { + // vfs could not load a module and returned an errorlog. + // commit the errorlog, mark the test failed, and + // move on. + TS_FAIL( "ERROR: Task %s could not be loaded, committing errorlog", + *i ); + errlCommit( l_errl, CXXTEST_COMP_ID ); + continue; + } + + //First run all serial testcases + tidrc = task_exec( *i, NULL ); + TRACFCOMP( g_trac_cxxtest, "Launched serial task: %s tidrc=%d", + *i, tidrc ); + int status = 0; + task_wait_tid(tidrc, &status, NULL); + + if (status != TASK_STATUS_EXITED_CLEAN) + { + TRACFCOMP( g_trac_cxxtest, "Task %d crashed with status %d.", + tidrc, status ); + if(CxxTest::g_FailedTests < CxxTest::CXXTEST_FAIL_LIST_SIZE) + { + CxxTest::CxxTestFailedEntry *l_failedEntry = + &CxxTest::g_FailedTestList[CxxTest::g_FailedTests]; + sprintf(l_failedEntry->failTestFile, + "%s crashed", + *i); + l_failedEntry->failTestData = tidrc; + } + __sync_add_and_fetch(&CxxTest::g_FailedTests, 1); + } + else + { + TRACFCOMP( g_trac_cxxtest, "Task %d finished.", tidrc ); + } + } + + //Then run all parallel testcases + for(std::vector<const char *>::const_iterator i = parallel_module_list.begin(); + i != parallel_module_list.end(); ++i) { __sync_add_and_fetch(&CxxTest::g_ModulesStarted, 1); diff --git a/src/usr/diag/attn/common/attnprd.C b/src/usr/diag/attn/common/attnprd.C index 65f2fafd9..e3f98335a 100644 --- a/src/usr/diag/attn/common/attnprd.C +++ b/src/usr/diag/attn/common/attnprd.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014,2016 */ +/* Contributors Listed Below - COPYRIGHT 2014,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -41,7 +41,6 @@ #include <errl/errlmanager.H> // Custom compile configs -#include <config.h> #if !defined(__HOSTBOOT_RUNTIME) && defined(CONFIG_ENABLE_CHECKSTOP_ANALYSIS) #include <prdf/prdfMain_ipl.H> diff --git a/src/usr/diag/attn/ipl/attn.C b/src/usr/diag/attn/ipl/attn.C index 7d59a3965..cd8762d49 100644 --- a/src/usr/diag/attn/ipl/attn.C +++ b/src/usr/diag/attn/ipl/attn.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014,2018 */ +/* Contributors Listed Below - COPYRIGHT 2014,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -44,7 +44,6 @@ #include <targeting/common/utilFilter.H> // Custom compile configs -#include <config.h> #ifdef CONFIG_ENABLE_CHECKSTOP_ANALYSIS #include "ipl/attnfilereg.H" diff --git a/src/usr/diag/attn/ipl/attnsvc.C b/src/usr/diag/attn/ipl/attnsvc.C index 17d87100f..0f4bddbb3 100644 --- a/src/usr/diag/attn/ipl/attnsvc.C +++ b/src/usr/diag/attn/ipl/attnsvc.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014,2018 */ +/* Contributors Listed Below - COPYRIGHT 2014,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -40,7 +40,6 @@ #include <initservice/initserviceif.H> // for hostboot TI // Custom compile configs -#include <config.h> using namespace std; using namespace PRDF; diff --git a/src/usr/diag/attn/ipl/attnsvc.H b/src/usr/diag/attn/ipl/attnsvc.H index 8e49fca1f..eabcb2176 100644 --- a/src/usr/diag/attn/ipl/attnsvc.H +++ b/src/usr/diag/attn/ipl/attnsvc.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014,2018 */ +/* Contributors Listed Below - COPYRIGHT 2014,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -36,7 +36,6 @@ #include "common/attnsvc_common.H" // Custom compile configs -#include <config.h> namespace ATTN { diff --git a/src/usr/diag/attn/runtime/attn_rt.C b/src/usr/diag/attn/runtime/attn_rt.C index 810e79bbe..92b225c7d 100644 --- a/src/usr/diag/attn/runtime/attn_rt.C +++ b/src/usr/diag/attn/runtime/attn_rt.C @@ -28,7 +28,7 @@ #include "common/attnmem.H" #include "common/attnbits.H" #include <runtime/interface.h> -#include <runtime/rt_targeting.H> +#include <targeting/runtime/rt_targeting.H> #include <targeting/common/target.H> #include <targeting/common/targetservice.H> #include <targeting/common/utilFilter.H> diff --git a/src/usr/diag/attn/runtime/test/attntestRtAttns.H b/src/usr/diag/attn/runtime/test/attntestRtAttns.H index 6e22b094e..b2bd1fd8e 100644 --- a/src/usr/diag/attn/runtime/test/attntestRtAttns.H +++ b/src/usr/diag/attn/runtime/test/attntestRtAttns.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014,2016 */ +/* Contributors Listed Below - COPYRIGHT 2014,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -38,7 +38,7 @@ #include "../../common/attntrace.H" #include "../../common/attntarget.H" #include <runtime/interface.h> -#include <runtime/rt_targeting.H> +#include <targeting/runtime/rt_targeting.H> #include <targeting/common/targetservice.H> using namespace ATTN; @@ -79,8 +79,8 @@ class AttnCheckForRtAttentionsTest : public CxxTest::TestSuite } proc = procList[0]; - RT_TARG::rtChipId_t chipId = 0; - errlHndl_t err = RT_TARG::getRtTarget( proc, chipId ); + TARGETING::rtChipId_t chipId = 0; + errlHndl_t err = TARGETING::getRtTarget( proc, chipId ); if( NULL != err ) { TS_FAIL("getRtTarget() failed for 0x%08X", @@ -153,7 +153,7 @@ class AttnCheckForRtAttentionsTest : public CxxTest::TestSuite break; } - RT_TARG::rtChipId_t chipId = 0; + TARGETING::rtChipId_t chipId = 0; errlHndl_t err = RT_TARG::getRtTarget( proc, chipId ); if( NULL != err ) { diff --git a/src/usr/diag/mdia/makefile b/src/usr/diag/mdia/makefile index fff17dd96..c6279ee5c 100644 --- a/src/usr/diag/mdia/makefile +++ b/src/usr/diag/mdia/makefile @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2012,2017 +# Contributors Listed Below - COPYRIGHT 2012,2019 # [+] International Business Machines Corp. # # @@ -50,6 +50,11 @@ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/centaur/common/include EXTRAINCDIR += ${ROOTPATH}/src/import/chips/centaur/procedures/hwp/memory EXTRAINCDIR += ${ROOTPATH}/src/import/chips/centaur/procedures/hwp/memory/lib/shared +EXTRAINCDIR += ${ROOTPATH}/src/import/generic/memory/lib/prd/ +EXTRAINCDIR += ${ROOTPATH}/src/import/generic/memory/lib/utils/mcbist/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/explorer/common/include/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/explorer/procedures/hwp/memory/ + MODULE = mdia OBJS += mdiamonitor.o diff --git a/src/usr/diag/mdia/mdia.C b/src/usr/diag/mdia/mdia.C index a13f28e59..f75ca1b60 100644 --- a/src/usr/diag/mdia/mdia.C +++ b/src/usr/diag/mdia/mdia.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2018 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -115,14 +115,16 @@ errlHndl_t runStep(const TargetHandleList & i_targetList) // ensure threads and pools are shutdown when finished - doStepCleanup(globals); + if(nullptr == err) + { + err = doStepCleanup(globals); + } // If this step completes without the need for a reconfig due to an RCD // parity error, clear all RCD parity error counters. ATTR_RECONFIGURE_LOOP_type attr = top->getAttr<ATTR_RECONFIGURE_LOOP>(); if ( 0 == (attr & RECONFIGURE_LOOP_RCD_PARITY_ERROR) ) { - //TODO RTC 201293 - may need to update this for axone as well TargetHandleList trgtList; getAllChiplets( trgtList, TYPE_MCA ); for ( auto & trgt : trgtList ) { @@ -140,13 +142,14 @@ errlHndl_t runStep(const TargetHandleList & i_targetList) } -void doStepCleanup(const Globals & i_globals) +errlHndl_t doStepCleanup(const Globals & i_globals) { // stop the state machine - Singleton<StateMachine>::instance().shutdown(); + errlHndl_t l_errl = Singleton<StateMachine>::instance().shutdown(); // TODO ... stop the command monitor + return l_errl; } errlHndl_t processEvent(MaintCommandEvent & i_event) diff --git a/src/usr/diag/mdia/mdiafwd.H b/src/usr/diag/mdia/mdiafwd.H index e3395781e..eae069588 100644 --- a/src/usr/diag/mdia/mdiafwd.H +++ b/src/usr/diag/mdia/mdiafwd.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2018 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -211,8 +211,10 @@ errlHndl_t getWorkFlow( * @brief doStepCleanup shut down threads and pools on step exit * * @param[in] i_globals contains objects to be cleaned up + * + * @return nullptr on success; non-nullptr on error */ -void doStepCleanup(const Globals & i_globals); +errlHndl_t doStepCleanup(const Globals & i_globals); /** * @brief check if hw state has been changed for an mba diff --git a/src/usr/diag/mdia/mdiasm.C b/src/usr/diag/mdia/mdiasm.C index bb1c123cf..ba00de6b0 100644 --- a/src/usr/diag/mdia/mdiasm.C +++ b/src/usr/diag/mdia/mdiasm.C @@ -43,12 +43,12 @@ #include <errl/errludlogregister.H> #include <initservice/istepdispatcherif.H> #include <ipmi/ipmiwatchdog.H> -#include <config.h> #include <initservice/initserviceif.H> #include <sys/time.h> #include <p9c_mss_maint_cmds.H> #include <dimmBadDqBitmapFuncs.H> #include <sys/misc.h> +#include <hwp_wrappers.H> using namespace TARGETING; using namespace ERRORLOG; @@ -632,16 +632,17 @@ void StateMachine::processCommandTimeout(const MonitorIDs & i_monitorIDs) // target type is MCBIST else if ( TYPE_MCBIST == trgtType ) { + #ifndef CONFIG_AXONE fapi2::Target<fapi2::TARGET_TYPE_MCBIST> fapiMcbist(target); - FAPI_INVOKE_HWP( err, mss::memdiags::stop, fapiMcbist ); + FAPI_INVOKE_HWP( err, nim_stop, fapiMcbist ); if ( nullptr != err ) { - MDIA_ERR("sm: mss::memdiags::stop failed"); + MDIA_ERR("sm: nim_stop failed"); errlCommit(err, MDIA_COMP_ID); } - //mss::memdiags::stop will set the command complete attention so + //nim_stop will set the command complete attention so //we need to clear those bitMask = ~bitMask; @@ -654,22 +655,23 @@ void StateMachine::processCommandTimeout(const MonitorIDs & i_monitorIDs) "0x%08X", firAddr, get_huid(target) ); errlCommit(err, MDIA_COMP_ID); } + #endif } // target type is OCMB_CHIP else if ( TYPE_OCMB_CHIP == trgtType ) { - /* TODO RTC 201293 uncomment once we have hwp support + #ifdef CONFIG_AXONE fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> fapiOcmb(target); - FAPI_INVOKE_HWP( err, mss::memdiags::stop, fapiOcmb ); + FAPI_INVOKE_HWP( err, exp_stop, fapiOcmb ); if ( nullptr != err ) { - MDIA_ERR("sm: mss::memdiags::stop failed"); + MDIA_ERR("sm: exp_stop failed"); errlCommit(err, MDIA_COMP_ID); } - // mss::memdiags::stop will set the command complete + // exp_stop will set the command complete // attention so we need to clear those bitMask = ~bitMask; @@ -682,7 +684,7 @@ void StateMachine::processCommandTimeout(const MonitorIDs & i_monitorIDs) "0x%08X", firAddr, get_huid(target) ); errlCommit(err, MDIA_COMP_ID); } - */ + #endif } // Assert if unsupported type else @@ -782,7 +784,15 @@ void StateMachine::setup(const WorkFlowAssocMap & i_list) p->timeoutCnt = 0; p->data = NULL; - p->chipUnit = it->first->getAttr<ATTR_CHIP_UNIT>(); + if ( TYPE_OCMB_CHIP == it->first->getAttr<ATTR_TYPE>() ) + { + // There is no chip unit attribute for OCMBs, so just use 0 + p->chipUnit = 0; + } + else + { + p->chipUnit = it->first->getAttr<ATTR_CHIP_UNIT>(); + } iv_workFlowProperties.push_back(p); } @@ -1242,14 +1252,15 @@ errlHndl_t StateMachine::doMaintCommand(WorkFlowProperties & i_wfp) //target type is MCBIST else if (TYPE_MCBIST == trgtType) { + #ifndef CONFIG_AXONE fapi2::Target<fapi2::TARGET_TYPE_MCBIST> fapiMcbist(target); - mss::mcbist::stop_conditions stopCond; + mss::mcbist::stop_conditions<mss::mc_type::NIMBUS> stopCond; switch(workItem) { case START_RANDOM_PATTERN: - FAPI_INVOKE_HWP( err, mss::memdiags::sf_init, fapiMcbist, + FAPI_INVOKE_HWP( err, nim_sf_init, fapiMcbist, mss::mcbist::PATTERN_RANDOM ); MDIA_FAST("sm: random init %p on: %x", fapiMcbist, get_huid(target)); @@ -1270,7 +1281,7 @@ errlHndl_t StateMachine::doMaintCommand(WorkFlowProperties & i_wfp) stopCond.set_pause_on_nce_hard(mss::ON); } - FAPI_INVOKE_HWP( err, mss::memdiags::sf_read, fapiMcbist, + FAPI_INVOKE_HWP( err, nim_sf_read, fapiMcbist, stopCond ); MDIA_FAST("sm: scrub %p on: %x", fapiMcbist, get_huid(target)); @@ -1285,7 +1296,7 @@ errlHndl_t StateMachine::doMaintCommand(WorkFlowProperties & i_wfp) case START_PATTERN_6: case START_PATTERN_7: - FAPI_INVOKE_HWP( err, mss::memdiags::sf_init, fapiMcbist, + FAPI_INVOKE_HWP( err, nim_sf_init, fapiMcbist, workItem ); MDIA_FAST("sm: init %p on: %x", fapiMcbist, get_huid(target)); @@ -1301,19 +1312,20 @@ errlHndl_t StateMachine::doMaintCommand(WorkFlowProperties & i_wfp) MDIA_FAST("sm: Running Maint Cmd failed"); i_wfp.data = nullptr; } + #endif } // target type is OCMB_CHIP else if ( TYPE_OCMB_CHIP == trgtType ) { - /* TODO RTC 201293 - uncomment with hwp support + #ifdef CONFIG_AXONE fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> fapiOcmb(target); - mss::mcbist::stop_conditions stopCond; + mss::mcbist::stop_conditions<mss::mc_type::EXPLORER> stopCond; switch(workItem) { case START_RANDOM_PATTERN: - FAPI_INVOKE_HWP( err, mss::memdiags::sf_init, fapiOcmb, + FAPI_INVOKE_HWP( err, exp_sf_init, fapiOcmb, mss::mcbist::PATTERN_RANDOM ); MDIA_FAST("sm: random init %p on: %x", fapiOcmb, get_huid(target)); @@ -1334,7 +1346,7 @@ errlHndl_t StateMachine::doMaintCommand(WorkFlowProperties & i_wfp) stopCond.set_pause_on_nce_hard(mss::ON); } - FAPI_INVOKE_HWP( err, mss::memdiags::sf_read, fapiOcmb, + FAPI_INVOKE_HWP( err, exp_sf_read, fapiOcmb, stopCond ); MDIA_FAST( "sm: scrub %p on: %x", fapiOcmb, get_huid(target) ); @@ -1349,7 +1361,7 @@ errlHndl_t StateMachine::doMaintCommand(WorkFlowProperties & i_wfp) case START_PATTERN_6: case START_PATTERN_7: - FAPI_INVOKE_HWP( err, mss::memdiags::sf_init, fapiOcmb, + FAPI_INVOKE_HWP( err, exp_sf_init, fapiOcmb, workItem ); MDIA_FAST( "sm: init %p on: %x", fapiOcmb, get_huid(target) ); @@ -1365,7 +1377,7 @@ errlHndl_t StateMachine::doMaintCommand(WorkFlowProperties & i_wfp) MDIA_FAST("sm: Running Maint Cmd failed"); i_wfp.data = nullptr; } - */ + #endif } else { @@ -1571,37 +1583,39 @@ bool StateMachine::processMaintCommandEvent(const MaintCommandEvent & i_event) //target type is MCBIST else if ( TYPE_MCBIST == trgtType ) { + #ifndef CONFIG_AXONE if(flags & STOP_CMD) { MDIA_FAST("sm: stopping command: %p", target); fapi2::Target<fapi2::TARGET_TYPE_MCBIST> fapiMcbist(target); - FAPI_INVOKE_HWP( err, mss::memdiags::stop, fapiMcbist ); + FAPI_INVOKE_HWP( err, nim_stop, fapiMcbist ); if(nullptr != err) { - MDIA_ERR("sm: mss::memdiags::stop failed"); + MDIA_ERR("sm: nim_stop failed"); errlCommit(err, MDIA_COMP_ID); } } + #endif } // target type is OCMB_CHIP else if ( TYPE_OCMB_CHIP == trgtType ) { + #ifdef CONFIG_AXONE if(flags & STOP_CMD) { MDIA_FAST("sm: stopping command: %p", target); - /* TODO RTC 201293 - reenable with hwp support fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> fapiOcmb(target); - FAPI_INVOKE_HWP( err, mss::memdiags::stop, fapiOcmb ); + FAPI_INVOKE_HWP( err, exp_stop, fapiOcmb ); if(nullptr != err) { - MDIA_ERR("sm: mss::memdiags::stop failed"); + MDIA_ERR("sm: exp_stop failed"); errlCommit(err, MDIA_COMP_ID); } - */ } + #endif } else { @@ -1665,10 +1679,12 @@ void StateMachine::reset() mutex_unlock(&iv_mutex); } -void StateMachine::shutdown() +errlHndl_t StateMachine::shutdown() { mutex_lock(&iv_mutex); + errlHndl_t l_errl = nullptr; + Util::ThreadPool<WorkItem> * tp = iv_tp; CommandMonitor * monitor = iv_monitor; @@ -1684,7 +1700,7 @@ void StateMachine::shutdown() if(tp) { MDIA_FAST("Stopping threadPool..."); - tp->shutdown(); + l_errl = tp->shutdown(); delete tp; } @@ -1696,11 +1712,16 @@ void StateMachine::shutdown() } MDIA_FAST("sm: ...shutdown complete"); + return l_errl; } StateMachine::~StateMachine() { - shutdown(); + errlHndl_t l_errl = shutdown(); + if(l_errl) + { + errlCommit(l_errl, MDIA_COMP_ID); + } sync_cond_destroy(&iv_cond); mutex_destroy(&iv_mutex); diff --git a/src/usr/diag/mdia/mdiasm.H b/src/usr/diag/mdia/mdiasm.H index 924af567a..55cc8ed74 100644 --- a/src/usr/diag/mdia/mdiasm.H +++ b/src/usr/diag/mdia/mdiasm.H @@ -106,8 +106,10 @@ class StateMachine /** * @brief shutdown state machine + * + * @retval nullptr on success; non-nullptr on error */ - void shutdown(); + errlHndl_t shutdown(); /** * @brief processMaintCommandEvent process maint command event from prd diff --git a/src/usr/diag/mdia/test/mdiatestmba.H b/src/usr/diag/mdia/test/mdiatestmba.H index bca85c11d..97360c80a 100644 --- a/src/usr/diag/mdia/test/mdiatestmba.H +++ b/src/usr/diag/mdia/test/mdiatestmba.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2016 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -47,33 +47,43 @@ class MdiaMbaTest : public CxxTest::TestSuite using namespace MDIA; using namespace TARGETING; - TS_TRACE(ENTER_MRK "testGetDiagnosticMode"); + TS_TRACE( ENTER_MRK "testGetDiagnosticMode" ); - TargetHandleList mbaList; - getAllChiplets(mbaList, TYPE_MBA); + TargetHandleList list; + fapi2::TargetType type = getMdiaTargetType(); + if ( fapi2::TARGET_TYPE_MBA_CHIPLET == type ) + { + TARGETING::getAllChiplets( list, TYPE_MBA ); + } + else if ( fapi2::TARGET_TYPE_MCBIST == type ) + { + TARGETING::getAllChiplets( list, TYPE_MCBIST ); + } + else if ( fapi2::TARGET_TYPE_OCMB_CHIP == type ) + { + TARGETING::getAllChiplets( list, TYPE_OCMB_CHIP ); + } - if( !mbaList.empty() ) + if( !list.empty() ) { DiagMode mode; Globals globals; - TargetHandle_t mba = mbaList[0]; + TargetHandle_t trgt = list[0]; - errlHndl_t err = getDiagnosticMode( - globals, mba, mode); + errlHndl_t err = getDiagnosticMode( globals, trgt, mode ); if(err) { - TS_FAIL("getDiagnosticMode failed " - "unexpectedly"); + TS_FAIL( "getDiagnosticMode failed unexpectedly" ); } if(mode != ONE_PATTERN) { - TS_FAIL("mode != ONE_PATTERN"); + TS_FAIL( "mode != ONE_PATTERN" ); } } - TS_TRACE(EXIT_MRK "testGetDiagnosticMode"); + TS_TRACE( EXIT_MRK "testGetDiagnosticMode" ); } void testGetWorkFlow(void) @@ -81,63 +91,74 @@ class MdiaMbaTest : public CxxTest::TestSuite using namespace MDIA; using namespace TARGETING; - TS_TRACE(ENTER_MRK "testGetWorkFlow"); + TS_TRACE( ENTER_MRK "testGetWorkFlow" ); Globals globals; - TargetHandle_t mba = 0; + TargetHandle_t trgt = 0; DiagMode mode; errlHndl_t err = NULL; - TargetHandleList mbaList; - getAllChiplets(mbaList, TYPE_MBA); - if( !mbaList.empty() ) + TargetHandleList list; + fapi2::TargetType type = getMdiaTargetType(); + if ( fapi2::TARGET_TYPE_MBA_CHIPLET == type ) { - mba = mbaList[0]; - err = getDiagnosticMode( - globals, mba, mode); + TARGETING::getAllChiplets( list, TYPE_MBA ); + } + else if ( fapi2::TARGET_TYPE_MCBIST == type ) + { + TARGETING::getAllChiplets( list, TYPE_MCBIST ); + } + else if ( fapi2::TARGET_TYPE_OCMB_CHIP == type ) + { + TARGETING::getAllChiplets( list, TYPE_OCMB_CHIP ); + } - if(err) + if( !list.empty() ) + { + trgt = list[0]; + err = getDiagnosticMode( globals, trgt, mode ); + + if( err ) { - TS_FAIL("getDiagnosticMode " - "failed unexpectedly"); + TS_FAIL( "getDiagnosticMode failed unexpectedly" ); } - if(mode != ONE_PATTERN) + if( mode != ONE_PATTERN ) { - TS_FAIL("mode != ONE_PATTERN"); + TS_FAIL( "mode != ONE_PATTERN" ); } - } - WorkFlow wf, expected; + WorkFlow wf, expected; - expected.push_back(RESTORE_DRAM_REPAIRS); - expected.push_back(START_PATTERN_0); - expected.push_back(START_SCRUB); - expected.push_back(CLEAR_HW_CHANGED_STATE); + expected.push_back( RESTORE_DRAM_REPAIRS ); + expected.push_back( START_PATTERN_0 ); + expected.push_back( START_SCRUB ); + expected.push_back( CLEAR_HW_CHANGED_STATE ); - err = getWorkFlow(mode, wf, globals); + err = getWorkFlow( mode, wf, globals ); - if(err) - { - TS_FAIL("getWorkFlow failed unexpectedly"); - } + if( err ) + { + TS_FAIL( "getWorkFlow failed unexpectedly" ); + } - if(wf.size() != expected.size()) - { - TS_FAIL("incorrect workflow size for init only mode"); - } + if( wf.size() != expected.size() ) + { + TS_FAIL( "incorrect workflow size for init only mode" ); + } - int64_t index = wf.size(); + int64_t index = wf.size(); - while(index-- != 0) - { - if(wf[index] != expected[index]) + while( index-- != 0 ) { - TS_FAIL("workflow entry incorrect or out of order"); + if( wf[index] != expected[index] ) + { + TS_FAIL( "workflow entry incorrect or out of order" ); + } } } - TS_TRACE(EXIT_MRK "testGetWorkFlow"); + TS_TRACE( EXIT_MRK "testGetWorkFlow" ); } }; #endif diff --git a/src/usr/diag/prdf/common/framework/config/iipSystem.h b/src/usr/diag/prdf/common/framework/config/iipSystem.h index ef4ed9322..b1b6ad1f4 100755 --- a/src/usr/diag/prdf/common/framework/config/iipSystem.h +++ b/src/usr/diag/prdf/common/framework/config/iipSystem.h @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 1996,2018 */ +/* Contributors Listed Below - COPYRIGHT 1996,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -87,9 +87,7 @@ #include <vector> #include <map> -#ifndef IIPCONST_H #include <iipconst.h> //TARGETING::TargetHandle_t, DOMAIN_ID_TYPE -#endif #include <iipsdbug.h> // Include file for ATTENTION_TYPE diff --git a/src/usr/diag/prdf/common/framework/register/iipCaptureData.h b/src/usr/diag/prdf/common/framework/register/iipCaptureData.h index e65e94d3f..9aae2880c 100755 --- a/src/usr/diag/prdf/common/framework/register/iipCaptureData.h +++ b/src/usr/diag/prdf/common/framework/register/iipCaptureData.h @@ -78,9 +78,7 @@ #include <list> -#ifndef IIPCONST_H #include <iipconst.h> -#endif #include <prdfPlatServices.H> #include <functional> // @jl04 a Needed for the unary function in new predicate. diff --git a/src/usr/diag/prdf/common/framework/register/iipErrorRegisterMask.h b/src/usr/diag/prdf/common/framework/register/iipErrorRegisterMask.h index fb1443df8..af67c68aa 100755 --- a/src/usr/diag/prdf/common/framework/register/iipErrorRegisterMask.h +++ b/src/usr/diag/prdf/common/framework/register/iipErrorRegisterMask.h @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2017 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -70,9 +70,7 @@ #include <iipErrorRegisterFilter.h> #endif -#ifndef IIPBITS_H -#include <iipbits.h> -#endif +#include <prdfBitString.H> namespace PRDF { diff --git a/src/usr/diag/prdf/common/framework/register/iipMopRegisterAccess.h b/src/usr/diag/prdf/common/framework/register/iipMopRegisterAccess.h deleted file mode 100755 index 1e7ad5947..000000000 --- a/src/usr/diag/prdf/common/framework/register/iipMopRegisterAccess.h +++ /dev/null @@ -1,184 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/diag/prdf/common/framework/register/iipMopRegisterAccess.h $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2017 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -#ifndef iipMopRegisterAccess_h -#define iipMopRegisterAccess_h - -// Class Specification ************************************************* -// -// Class name: MopRegisterAccess -// Parent class: None. -// -// Summary: This class provides access to hardware register via -// a MOP routine. A single pure virtual function Access() -// is declared for this purpose. -// -// Cardinality: 0 -// -// Performance/Implementation: -// Space Complexity: Constant -// Time Complexity: All member functions constant unless otherwise -// stated. -// -// Usage Examples: -// -// -// void foo(MopRegisterAccess & mra) -// { -// BitStringBuffer bitString(80); // 80 bits -// -// mra.Access(bitString, READ); -// ... -// -// } -// -// -// End Class Specification ********************************************* - -// Includes -#if !defined(IIPCONST_H) -#include <iipconst.h> -#endif -#include <prdfPlatServices.H> - -namespace PRDF -{ -// Forward References -class BitString; - -class MopRegisterAccess -{ -public: - - enum Operation - { - READ = 0, - WRITE = 1 - }; - - // MopRegisterAccess(void); - // Function Specification ******************************************** - // - // Purpose: Initialization - // Parameters: None. - // Returns: No value returned. - // Requirements: None. - // Promises: All data members are initialized. - // Exceptions: None. - // Concurrency: N/A - // Notes: This constructor is not declared. This compiler generated - // default definition is sufficient. - // - // End Function Specification ////////////////////////////////////// - - // MopRegisterAccess(const MopRegisterAccess & scr); - // Function Specification ******************************************** - // - // Purpose: Copy - // Parameters: scr: Reference to instance to copy - // Returns: No value returned. - // Requirements: None. - // Promises: All data members will be copied (Deep copy). - // Exceptions: None. - // Concurrency: N/A. - // Notes: This constructor is not declared. This compiler generated - // default definition is sufficient. - // - // End Function Specification **************************************** - - virtual ~MopRegisterAccess() {} - - // Function Specification ******************************************** - // - // Purpose: Destruction - // Parameters: None. - // Returns: No value returned - // Requirements: None. - // Promises: None. - // Exceptions: None. - // Concurrency: N/A - // - // End Function Specification **************************************** - - // MopRegisterAccess & operator=(const MopRegisterAccess & scr); - // Function Specification ******************************************** - // - // Purpose: Assigment - // Parameters: d: Reference to instance to assign from - // Returns: Reference to this instance - // Requirements: None. - // Promises: All data members are assigned to - // Exceptions: None. - // Concurrency: N/A. - // Notes: This assingment operator is not declared. The compiler - // generated default definition is sufficient. - // - // End Function Specification **************************************** - - virtual uint32_t Access(BitString & bs, - uint64_t registerId, - Operation operation) const = 0; - // Function Specification ******************************************** - // - // Purpose: This function reads or writes the hardware according - // to the specified operation. - // Parameters: bs: Bit string to retrieve(for write) or store data - // (from read) - // registerId: SCR Address or scan offset - // operation: Indicates either read or write operation - // Returns: Hardware OPs return code - // Requirements: bs.Length() == long enough - // Promises: For read operation, bs is modified to reflect hardware - // register state - // Exceptions: None. - // Concurrency: Nonreentrant. - // Note: The first bs.Length() bits from the Hardware OPs read - // are set/reset in bs (from left to right) - // For a write, the first bs.Length() bits are written - // to the hardware register with right padded 0's if - // needed - // - // End Function Specification **************************************** - //Get Ids and count - virtual const TARGETING::TargetHandle_t * GetChipIds(int & count) const = 0; - // Function Specification ******************************************** - // - // Purpose: Access Chip Ids and # of chips to access - // Parameters: count: Var to return chip count of valid IDs - // Returns: ptr to Chip ids - // Requirements: None - // Promises: None - // Exceptions: None. - // Concurrency: Reentrant. - // - // End Function Specification **************************************** - - private: - - }; - -} // end namespace PRDF - -#endif diff --git a/src/usr/diag/prdf/common/framework/register/iipMopRegisterAccessScanComm.h b/src/usr/diag/prdf/common/framework/register/iipMopRegisterAccessScanComm.h deleted file mode 100755 index e87d70210..000000000 --- a/src/usr/diag/prdf/common/framework/register/iipMopRegisterAccessScanComm.h +++ /dev/null @@ -1,158 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/diag/prdf/common/framework/register/iipMopRegisterAccessScanComm.h $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 1996,2017 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -#ifndef iipMopRegisterAccessScanComm_h -#define iipMopRegisterAccessScanComm_h - -// Class Specification ************************************************* -// -// Class name: MopRegisterAccessScanComm -// Parent class: MopRegisterAccess. -// -// Summary: This class provides access to hardware register data via -// a MOP Scan Comm routine. -// -// Cardinality: 0 -// -// Performance/Implementation: -// Space Complexity: Constant -// Time Complexity: All member functions constant unless otherwise -// stated. -// -// Usage Examples: -// -// -// -// End Class Specification ********************************************* - -// Includes - -#pragma interface - -#ifndef iipMopRegisterAccess_h -#include <iipMopRegisterAccess.h> -#endif - -namespace PRDF -{ - -// Forward References -class MopRegisterAccessScanComm : public MopRegisterAccess -{ -public: - - // Function Specification ******************************************** - // - // Purpose: CTOR - // Parameters: None - // Returns: No value returned. - // Requirements: None. - // Promises: All data members are initialized. - // Exceptions: None. - // Concurrency: N/A - // Note: Multiple chip IDs are for chips that MOPs must - // access at the same time when performing a Scan - // Comm operation (ie STINGER & ARROW chips) - // - // End Function Specification ////////////////////////////////////// - - // MopRegisterAccessScanComm(const MopRegisterAccessScanComm & scr); - // Function Specification ******************************************** - // - // Purpose: Copy - // Parameters: scr: Reference to instance to copy - // Returns: No value returned. - // Requirements: None. - // Promises: All data members will be copied (Deep copy). - // Exceptions: None. - // Concurrency: N/A. - // Notes: This constructor is not declared. This compiler generated - // default definition is sufficient. - // - // End Function Specification **************************************** - - // virtual ~MopRegisterAccessScanComm(void); - // Function Specification ******************************************** - // - // Purpose: Destruction - // Parameters: None. - // Returns: No value returned - // Requirements: None. - // Promises: None. - // Exceptions: None. - // Concurrency: N/A - // Notes: This destructor is not declared. This compiler generated - // default definition is sufficient. - // - // End Function Specification **************************************** - - // MopRegisterAccessScanComm & operator=(const MopRegisterAccessScanComm & scr); - // Function Specification ******************************************** - // - // Purpose: Assigment - // Parameters: d: Reference to instance to assign from - // Returns: Reference to this instance - // Requirements: None. - // Promises: All data members are assigned to - // Exceptions: None. - // Concurrency: N/A. - // Notes: This assingment operator is not declared. The compiler - // generated default definition is sufficient. - // - // End Function Specification **************************************** - - virtual uint32_t Access(BitString & bs, - uint32_t registerId, - Operation operation) const; - // Function Specification ******************************************** - // - // Purpose: This function reads or writes the hardware according - // to the specified operation. - // Parameters: bs: Bit string to retrieve(for write) or store data - // (from read) - // registerId: ScanComm register address - // operation: Indicates either read or write operation - // Returns: Hardware OPs return code - // Requirements: bs.Length() == long enough - // Promises: For read operation, bs is modified to reflect hardware - // register state - // Exceptions: None. - // Concurrency: Nonreentrant. - // Note: The first bs.Length() bits from the Hardware OPs read - // are set/reset in bs (from left to right) - // For a write, the first bs.Length() bits are written - // to the hardware register with right padded 0's if - // needed - // - // End Function Specification **************************************** - - -private: // DATA - -}; - -} // end namespace PRDF - -#endif diff --git a/src/usr/diag/prdf/common/framework/register/iipscr.C b/src/usr/diag/prdf/common/framework/register/iipscr.C index d4d7017a2..6834c6415 100755 --- a/src/usr/diag/prdf/common/framework/register/iipscr.C +++ b/src/usr/diag/prdf/common/framework/register/iipscr.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 1997,2017 */ +/* Contributors Listed Below - COPYRIGHT 1997,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -41,7 +41,7 @@ /* Includes */ /*--------------------------------------------------------------------*/ -#include <iipbits.h> +#include <prdfBitString.H> #include <iipscr.h> #include <iipconst.h> diff --git a/src/usr/diag/prdf/common/framework/register/iipscr.h b/src/usr/diag/prdf/common/framework/register/iipscr.h index 53c9bfa5a..cd1243dc6 100755 --- a/src/usr/diag/prdf/common/framework/register/iipscr.h +++ b/src/usr/diag/prdf/common/framework/register/iipscr.h @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2017 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -43,7 +43,7 @@ // Includes //---------------------------------------------------------------------- -#include <iipbits.h> +#include <prdfBitString.H> #include <iipconst.h> #include <iipsdbug.h> #include <prdfMain.H> diff --git a/src/usr/diag/prdf/common/framework/register/prdfCaptureData.C b/src/usr/diag/prdf/common/framework/register/prdfCaptureData.C index 39113507b..5ddb11a4c 100755 --- a/src/usr/diag/prdf/common/framework/register/prdfCaptureData.C +++ b/src/usr/diag/prdf/common/framework/register/prdfCaptureData.C @@ -31,7 +31,7 @@ // Includes //---------------------------------------------------------------------- -#include <iipbits.h> +#include <prdfBitString.H> #include <prdfHomRegisterAccess.H> // dg06a #include <prdfScomRegister.H> #include <iipchip.h> diff --git a/src/usr/diag/prdf/common/framework/register/prdfErrorRegister.C b/src/usr/diag/prdf/common/framework/register/prdfErrorRegister.C index 3244022c7..450a7bc9c 100755 --- a/src/usr/diag/prdf/common/framework/register/prdfErrorRegister.C +++ b/src/usr/diag/prdf/common/framework/register/prdfErrorRegister.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2018 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -40,7 +40,7 @@ #include <prdfMain.H> #include <prdfAssert.h> #include <iipstep.h> -#include <iipbits.h> +#include <prdfBitString.H> #include <iipResolution.h> #include <iipscr.h> #include <prdfErrorSignature.H> diff --git a/src/usr/diag/prdf/common/framework/register/prdfHomRegisterAccess.C b/src/usr/diag/prdf/common/framework/register/prdfHomRegisterAccess.C index a9d2a615a..c7bf802a4 100755 --- a/src/usr/diag/prdf/common/framework/register/prdfHomRegisterAccess.C +++ b/src/usr/diag/prdf/common/framework/register/prdfHomRegisterAccess.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2017 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -30,11 +30,10 @@ //---------------------------------------------------------------------- // Includes //---------------------------------------------------------------------- -#define prdfHomRegisterAccess_C #include <prdfHomRegisterAccess.H> #include <prdf_service_codes.H> -#include <iipbits.h> +#include <prdfBitString.H> #include <prdfMain.H> #include <prdfPlatServices.H> #include <prdfGlobal.H> @@ -46,9 +45,6 @@ #include <p9_stop_api.H> #endif -#undef prdfHomRegisterAccess_C - - using namespace TARGETING; namespace PRDF @@ -117,7 +113,7 @@ void ScomService::setScomAccessor(ScomAccessor & i_ScomAccessor) uint32_t ScomService::Access(TargetHandle_t i_target, BitString & bs, uint64_t registerId, - MopRegisterAccess::Operation operation) const + RegisterAccess::Operation operation) const { PRDF_DENTER("ScomService::Access()"); uint32_t rc = SUCCESS; @@ -136,7 +132,7 @@ uint32_t ScomService::Access(TargetHandle_t i_target, uint32_t ScomAccessor::Access(TargetHandle_t i_target, BitString & bs, uint64_t registerId, - MopRegisterAccess::Operation operation) const + RegisterAccess::Operation operation) const { PRDF_DENTER("ScomAccessor::Access()"); @@ -146,7 +142,7 @@ uint32_t ScomAccessor::Access(TargetHandle_t i_target, { switch (operation) { - case MopRegisterAccess::WRITE: + case RegisterAccess::WRITE: { rc = PRDF::PlatServices::putScom(i_target, bs, registerId); @@ -198,7 +194,7 @@ uint32_t ScomAccessor::Access(TargetHandle_t i_target, break; } - case MopRegisterAccess::READ: + case RegisterAccess::READ: bs.clearAll(); // clear all bits rc = PRDF::PlatServices::getScom(i_target, bs, registerId); diff --git a/src/usr/diag/prdf/common/framework/register/prdfHomRegisterAccess.H b/src/usr/diag/prdf/common/framework/register/prdfHomRegisterAccess.H index 6426b4ac3..d26f173f6 100755 --- a/src/usr/diag/prdf/common/framework/register/prdfHomRegisterAccess.H +++ b/src/usr/diag/prdf/common/framework/register/prdfHomRegisterAccess.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2017 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -35,7 +35,6 @@ // Includes //-------------------------------------------------------------------- -#include <iipMopRegisterAccess.h> #include <vector> #include <prdfPlatServices.H> #include <prdfErrlUtil.H> @@ -47,6 +46,15 @@ namespace PRDF { +namespace RegisterAccess +{ + enum Operation + { + READ = 0, + WRITE = 1, + }; +} + class ScomAccessor { public: @@ -75,7 +83,7 @@ class ScomAccessor virtual uint32_t Access( TARGETING::TargetHandle_t i_target, BitString & bs, uint64_t registerId, - MopRegisterAccess::Operation operation) const; + RegisterAccess::Operation operation) const; private: @@ -142,7 +150,7 @@ class ScomService virtual uint32_t Access(TARGETING::TargetHandle_t i_target, BitString & bs, uint64_t registerId, - MopRegisterAccess::Operation operation) const; + RegisterAccess::Operation operation) const; private: diff --git a/src/usr/diag/prdf/common/framework/register/prdfRegisterCache.H b/src/usr/diag/prdf/common/framework/register/prdfRegisterCache.H index be34884a3..8d069b3cb 100644 --- a/src/usr/diag/prdf/common/framework/register/prdfRegisterCache.H +++ b/src/usr/diag/prdf/common/framework/register/prdfRegisterCache.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2017 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -29,7 +29,7 @@ /** @file prdfRegisterCache.H */ #include <map> -#include <iipbits.h> +#include <prdfBitString.H> #include <prdfGlobal.H> #include <prdfScanFacility.H> #include <prdfScomRegisterAccess.H> diff --git a/src/usr/diag/prdf/common/framework/register/prdfScomRegister.C b/src/usr/diag/prdf/common/framework/register/prdfScomRegister.C index 7e4cce81b..f8a445b20 100755 --- a/src/usr/diag/prdf/common/framework/register/prdfScomRegister.C +++ b/src/usr/diag/prdf/common/framework/register/prdfScomRegister.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2017 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -37,7 +37,7 @@ #include <iipchip.h> #include <prdfScomRegister.H> #include <iipconst.h> -#include <iipbits.h> +#include <prdfBitString.H> #include <prdfMain.H> #include <prdfRasServices.H> #include <prdfRegisterCache.H> @@ -155,7 +155,7 @@ uint32_t ScomRegister::ForceRead() const } // Read hardware. - o_rc = Access( readCache(), MopRegisterAccess::READ ); + o_rc = Access( readCache(), RegisterAccess::READ ); if ( SUCCESS != o_rc ) { // The read failed. Remove the entry from the cache so a subsequent @@ -201,7 +201,7 @@ uint32_t ScomRegister::Write() } // Write hardware. - o_rc = Access( readCache(), MopRegisterAccess::WRITE ); + o_rc = Access( readCache(), RegisterAccess::WRITE ); } while (0); @@ -213,7 +213,7 @@ uint32_t ScomRegister::Write() //------------------------------------------------------------------------------ uint32_t ScomRegister::Access( BitString & bs, - MopRegisterAccess::Operation op ) const + RegisterAccess::Operation op ) const { int32_t l_rc = SCR_ACCESS_FAILED; TARGETING::TargetHandle_t i_pchipTarget = getChip()->GetChipHandle(); diff --git a/src/usr/diag/prdf/common/framework/register/prdfScomRegister.H b/src/usr/diag/prdf/common/framework/register/prdfScomRegister.H index 655f4d523..e3d14a0dc 100755 --- a/src/usr/diag/prdf/common/framework/register/prdfScomRegister.H +++ b/src/usr/diag/prdf/common/framework/register/prdfScomRegister.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 1996,2017 */ +/* Contributors Listed Below - COPYRIGHT 1996,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -37,8 +37,8 @@ */ #include <iipscr.h> -#include <iipbits.h> -#include <iipMopRegisterAccess.h> +#include <prdfBitString.H> +#include <prdfHomRegisterAccess.H> #include <prdfTrace.H> namespace PRDF @@ -80,6 +80,9 @@ class ScomRegister : public SCAN_COMM_REGISTER_CLASS iv_operationType( ACCESS_NONE ) {} + /** @brief Destructor. */ + virtual ~ScomRegister() = default; + /** * @brief Returns the pointer to bit string * @param i_type attention type @@ -201,7 +204,7 @@ class ScomRegister : public SCAN_COMM_REGISTER_CLASS * @return [SUCCESS|FAIL] */ uint32_t Access( BitString & bs, - MopRegisterAccess::Operation op )const; + RegisterAccess::Operation op )const; /** * @brief Returns rulechip pointer associated with the register diff --git a/src/usr/diag/prdf/common/framework/resolution/prdfCalloutMap.H b/src/usr/diag/prdf/common/framework/resolution/prdfCalloutMap.H index 7bedec637..269e432cf 100644 --- a/src/usr/diag/prdf/common/framework/resolution/prdfCalloutMap.H +++ b/src/usr/diag/prdf/common/framework/resolution/prdfCalloutMap.H @@ -195,7 +195,9 @@ PRDF_TARGET_TYPE_ALIAS( TYPE_MI, TARGETING::TYPE_MI ) PRDF_TARGET_TYPE_ALIAS( TYPE_DMI, TARGETING::TYPE_DMI ) PRDF_TARGET_TYPE_ALIAS( TYPE_MCC, TARGETING::TYPE_MCC ) PRDF_TARGET_TYPE_ALIAS( TYPE_OMIC, TARGETING::TYPE_OMIC ) +PRDF_TARGET_TYPE_ALIAS( TYPE_OMI, TARGETING::TYPE_OMI ) PRDF_TARGET_TYPE_ALIAS( TYPE_OCMB_CHIP, TARGETING::TYPE_OCMB_CHIP ) +PRDF_TARGET_TYPE_ALIAS( TYPE_MEM_PORT, TARGETING::TYPE_MEM_PORT ) PRDF_TARGET_TYPE_ALIAS( TYPE_MEMBUF, TARGETING::TYPE_MEMBUF ) PRDF_TARGET_TYPE_ALIAS( TYPE_L4, TARGETING::TYPE_L4 ) PRDF_TARGET_TYPE_ALIAS( TYPE_MBA, TARGETING::TYPE_MBA ) diff --git a/src/usr/diag/prdf/common/framework/resolution/prdfThresholdResolutions.H b/src/usr/diag/prdf/common/framework/resolution/prdfThresholdResolutions.H index e412460dc..b61699159 100755 --- a/src/usr/diag/prdf/common/framework/resolution/prdfThresholdResolutions.H +++ b/src/usr/diag/prdf/common/framework/resolution/prdfThresholdResolutions.H @@ -5,7 +5,9 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2003,2014 */ +/* Contributors Listed Below - COPYRIGHT 2003,2019 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ @@ -100,10 +102,11 @@ class ThresholdResolution : public MaskResolution enum TimeBase { - ONE_SEC = 1, - ONE_MIN = ONE_SEC * 60, - ONE_HOUR = ONE_MIN * 60, - ONE_DAY = ONE_HOUR * 24, + ONE_SEC = 1, + ONE_MIN = ONE_SEC * 60, + ONE_HOUR = ONE_MIN * 60, + TEN_HOURS = ONE_HOUR * 10, + ONE_DAY = ONE_HOUR * 24, NONE = 0xffffffff, }; diff --git a/src/usr/diag/prdf/common/framework/service/iipServiceDataCollector.h b/src/usr/diag/prdf/common/framework/service/iipServiceDataCollector.h index 704dddf70..e8cdb79a5 100755 --- a/src/usr/diag/prdf/common/framework/service/iipServiceDataCollector.h +++ b/src/usr/diag/prdf/common/framework/service/iipServiceDataCollector.h @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2018 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -628,6 +628,11 @@ public: void clearMruListGard(); /** + * @brief Iterates the MRU list and clears gard for any NVDIMM targets. + */ + void clearNvdimmMruListGard(); + + /** * @brief Iterates the MRU list and returns true if at least on target in * the list is set to be garded. * @return True if there is at least one target set to be garded. diff --git a/src/usr/diag/prdf/common/framework/service/prdfServiceDataCollector.C b/src/usr/diag/prdf/common/framework/service/prdfServiceDataCollector.C index d9681d66b..731102a26 100755 --- a/src/usr/diag/prdf/common/framework/service/prdfServiceDataCollector.C +++ b/src/usr/diag/prdf/common/framework/service/prdfServiceDataCollector.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2015 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -177,6 +177,88 @@ void ServiceDataCollector::clearMruListGard() //------------------------------------------------------------------------------ +void ServiceDataCollector::clearNvdimmMruListGard() +{ + #define PRDF_FUNC "[ServiceDataCollector::clearNvdimmMruListGard] " + + #ifdef CONFIG_NVDIMM + #ifdef __HOSTBOOT_MODULE + // Loop through the MRU list. + for ( auto & mru : xMruList ) + { + PRDcallout callout = mru.callout; + PRDcalloutData::MruType mruType = callout.getType(); + + if ( mruType == PRDcalloutData::TYPE_TARGET ) + { + TargetHandle_t trgt = callout.getTarget(); + + // If the callout target is an NVDIMM send a message to + // PHYP/Hostboot that a save/restore may work, and if we are at + // IPL, clear Gard on the NVDIMM. + if ( TYPE_DIMM == PlatServices::getTargetType(trgt) && + isNVDIMM(trgt) ) + { + // Send the message to PHYP/Hostboot if a predictive log + if ( queryServiceCall() ) + { + uint32_t l_rc = PlatServices::nvdimmNotifyProtChange( trgt, + NVDIMM::NVDIMM_RISKY_HW_ERROR ); + if ( SUCCESS != l_rc ) + { + PRDF_TRAC( PRDF_FUNC "nvdimmNotifyProtChange(0x%08x) " + "failed.", PlatServices::getHuid(trgt) ); + continue; + } + } + #ifndef __HOSTBOOT_RUNTIME + // IPL, clear Gard + mru.gardState = NO_GARD; + #endif + } + } + else if ( mruType == PRDcalloutData::TYPE_MEMMRU ) + { + MemoryMru memMru( callout.flatten() ); + TargetHandleList dimmList = memMru.getCalloutList(); + + for ( auto & dimm : dimmList ) + { + // If the callout target is an NVDIMM send a message to + // PHYP/Hostboot that a save/restore may work, and if we are at + // IPL, clear Gard on the NVDIMM. + if ( TYPE_DIMM == PlatServices::getTargetType(dimm) && + isNVDIMM(dimm) ) + { + // Send the message to PHYP/Hostboot if a predictive log + if ( queryServiceCall() ) + { + uint32_t l_rc = PlatServices::nvdimmNotifyProtChange( + dimm, NVDIMM::NVDIMM_RISKY_HW_ERROR ); + if ( SUCCESS != l_rc ) + { + PRDF_TRAC( PRDF_FUNC "nvdimmNotifyProtChange" + "(0x%08x) failed.", + PlatServices::getHuid(dimm) ); + continue; + } + } + #ifndef __HOSTBOOT_RUNTIME + // IPL, clear Gard + mru.gardState = NO_GARD; + #endif + } + } + } + } + #endif // __HOSTBOOT_MODULE + #endif // CONFIG_NVDIMM + + #undef PRDF_FUNC +} + +//------------------------------------------------------------------------------ + bool ServiceDataCollector::isGardRequested() { bool gardRecordExit = false; diff --git a/src/usr/diag/prdf/common/iipconst.h b/src/usr/diag/prdf/common/iipconst.h index 07c5ded16..5c71cf8f7 100755 --- a/src/usr/diag/prdf/common/iipconst.h +++ b/src/usr/diag/prdf/common/iipconst.h @@ -65,12 +65,13 @@ namespace PRDF /* Constants */ /*--------------------------------------------------------------------*/ +// Return code constants #ifndef SUCCESS -#define SUCCESS 0 +static const int32_t SUCCESS = 0; #endif #ifndef FAIL -#define FAIL -1 +static const int32_t FAIL = -1; #endif enum DOMAIN_ID diff --git a/src/usr/diag/prdf/common/plat/axone/axone_mc.rule b/src/usr/diag/prdf/common/plat/axone/axone_mc.rule index 4f63011fc..f23fee7d2 100644 --- a/src/usr/diag/prdf/common/plat/axone/axone_mc.rule +++ b/src/usr/diag/prdf/common/plat/axone/axone_mc.rule @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2018 +# Contributors Listed Below - COPYRIGHT 2018,2019 # [+] International Business Machines Corp. # # @@ -141,39 +141,39 @@ chip axone_mc }; ############################################################################ - # P9 MC target MCBISTFIR + # P9 MC target MCMISCFIR ############################################################################ - register MCBISTFIR + register MCMISCFIR { - name "P9 MC target MCBISTFIR"; + name "P9 MC target MCMISCFIR"; scomaddr 0x07012300; reset (&, 0x07012301); mask (|, 0x07012305); capture group default; }; - register MCBISTFIR_MASK + register MCMISCFIR_MASK { - name "P9 MC target MCBISTFIR MASK"; + name "P9 MC target MCMISCFIR MASK"; scomaddr 0x07012303; capture group default; }; - register MCBISTFIR_ACT0 + register MCMISCFIR_ACT0 { - name "P9 MC target MCBISTFIR ACT0"; + name "P9 MC target MCMISCFIR ACT0"; scomaddr 0x07012306; capture group default; - capture req nonzero("MCBISTFIR"); + capture req nonzero("MCMISCFIR"); }; - register MCBISTFIR_ACT1 + register MCMISCFIR_ACT1 { - name "P9 MC target MCBISTFIR ACT1"; + name "P9 MC target MCMISCFIR ACT1"; scomaddr 0x07012307; capture group default; - capture req nonzero("MCBISTFIR"); + capture req nonzero("MCMISCFIR"); }; # Include registers not defined by the xml @@ -253,9 +253,9 @@ group gMC_CHIPLET_FIR attntype CHECK_STOP, RECOVERABLE (rMC_CHIPLET_FIR, bit(11)) ? analyzeConnectedMCC3; /** MC_CHIPLET_FIR[12] - * Attention from MCBISTFIR + * Attention from MCMISCFIR */ - (rMC_CHIPLET_FIR, bit(12)) ? analyzeMCBISTFIR; + (rMC_CHIPLET_FIR, bit(12)) ? analyzeMCMISCFIR; /** MC_CHIPLET_FIR[13] * Attention from IOOMIFIR 0 @@ -358,9 +358,9 @@ group gMC_CHIPLET_UCS_FIR attntype UNIT_CS (rMC_CHIPLET_UCS_FIR, bit(8)) ? analyzeConnectedMCC3; /** MC_CHIPLET_UCS_FIR[9] - * Attention from MCBISTFIR + * Attention from MCMISCFIR */ - (rMC_CHIPLET_UCS_FIR, bit(9)) ? analyzeMCBISTFIR; + (rMC_CHIPLET_UCS_FIR, bit(9)) ? analyzeMCMISCFIR; /** MC_CHIPLET_UCS_FIR[10] * Attention from IOOMIFIR 0 @@ -448,9 +448,9 @@ group gMC_CHIPLET_HA_FIR attntype HOST_ATTN (rMC_CHIPLET_HA_FIR, bit(8)) ? analyzeConnectedMCC3; /** MC_CHIPLET_HA_FIR[9] - * Attention from MCBISTFIR + * Attention from MCMISCFIR */ - (rMC_CHIPLET_HA_FIR, bit(9)) ? analyzeMCBISTFIR; + (rMC_CHIPLET_HA_FIR, bit(9)) ? analyzeMCMISCFIR; }; @@ -563,94 +563,94 @@ group gMC_LFIR }; ################################################################################ -# P9 MC target MCBISTFIR +# P9 MC target MCMISCFIR ################################################################################ -rule rMCBISTFIR +rule rMCMISCFIR { CHECK_STOP: - MCBISTFIR & ~MCBISTFIR_MASK & ~MCBISTFIR_ACT0 & ~MCBISTFIR_ACT1; + MCMISCFIR & ~MCMISCFIR_MASK & ~MCMISCFIR_ACT0 & ~MCMISCFIR_ACT1; RECOVERABLE: - MCBISTFIR & ~MCBISTFIR_MASK & ~MCBISTFIR_ACT0 & MCBISTFIR_ACT1; + MCMISCFIR & ~MCMISCFIR_MASK & ~MCMISCFIR_ACT0 & MCMISCFIR_ACT1; HOST_ATTN: - MCBISTFIR & ~MCBISTFIR_MASK & MCBISTFIR_ACT0 & ~MCBISTFIR_ACT1; + MCMISCFIR & ~MCMISCFIR_MASK & MCMISCFIR_ACT0 & ~MCMISCFIR_ACT1; UNIT_CS: - MCBISTFIR & ~MCBISTFIR_MASK & MCBISTFIR_ACT0 & MCBISTFIR_ACT1; + MCMISCFIR & ~MCMISCFIR_MASK & MCMISCFIR_ACT0 & MCMISCFIR_ACT1; }; -group gMCBISTFIR +group gMCMISCFIR filter singlebit, cs_root_cause { - /** MCBISTFIR[0] + /** MCMISCFIR[0] * WAT debug bus attn */ - (rMCBISTFIR, bit(0)) ? defaultMaskedError; + (rMCMISCFIR, bit(0)) ? defaultMaskedError; - /** MCBISTFIR[1] + /** MCMISCFIR[1] * WAT debug register parity error */ - (rMCBISTFIR, bit(1)) ? defaultMaskedError; + (rMCMISCFIR, bit(1)) ? defaultMaskedError; - /** MCBISTFIR[2] + /** MCMISCFIR[2] * SCOM recoverable register parity error */ - (rMCBISTFIR, bit(2)) ? defaultMaskedError; + (rMCMISCFIR, bit(2)) ? self_th_1; - /** MCBISTFIR[3] + /** MCMISCFIR[3] * Spare */ - (rMCBISTFIR, bit(3)) ? defaultMaskedError; + (rMCMISCFIR, bit(3)) ? defaultMaskedError; - /** MCBISTFIR[4] + /** MCMISCFIR[4] * Chan 0A application interrupt */ - (rMCBISTFIR, bit(4)) ? defaultMaskedError; + (rMCMISCFIR, bit(4)) ? defaultMaskedError; - /** MCBISTFIR[5] + /** MCMISCFIR[5] * Chan 0B application interrupt */ - (rMCBISTFIR, bit(5)) ? defaultMaskedError; + (rMCMISCFIR, bit(5)) ? defaultMaskedError; - /** MCBISTFIR[6] + /** MCMISCFIR[6] * Chan 1A application interrupt */ - (rMCBISTFIR, bit(6)) ? defaultMaskedError; + (rMCMISCFIR, bit(6)) ? defaultMaskedError; - /** MCBISTFIR[7] + /** MCMISCFIR[7] * Chan 1B application interrupt */ - (rMCBISTFIR, bit(7)) ? defaultMaskedError; + (rMCMISCFIR, bit(7)) ? defaultMaskedError; - /** MCBISTFIR[8] + /** MCMISCFIR[8] * Chan 2A application interrupt */ - (rMCBISTFIR, bit(8)) ? defaultMaskedError; + (rMCMISCFIR, bit(8)) ? defaultMaskedError; - /** MCBISTFIR[9] + /** MCMISCFIR[9] * Chan 2B application interrupt */ - (rMCBISTFIR, bit(9)) ? defaultMaskedError; + (rMCMISCFIR, bit(9)) ? defaultMaskedError; - /** MCBISTFIR[10] + /** MCMISCFIR[10] * Chan 3A application interrupt */ - (rMCBISTFIR, bit(10)) ? defaultMaskedError; + (rMCMISCFIR, bit(10)) ? defaultMaskedError; - /** MCBISTFIR[11] + /** MCMISCFIR[11] * Chan 3B application interrupt */ - (rMCBISTFIR, bit(11)) ? defaultMaskedError; + (rMCMISCFIR, bit(11)) ? defaultMaskedError; - /** MCBISTFIR[12] + /** MCMISCFIR[12] * Internal SCOM error */ - (rMCBISTFIR, bit(12)) ? defaultMaskedError; + (rMCMISCFIR, bit(12)) ? defaultMaskedError; - /** MCBISTFIR[13] + /** MCMISCFIR[13] * Internal SCOM error clone */ - (rMCBISTFIR, bit(13)) ? defaultMaskedError; + (rMCMISCFIR, bit(13)) ? defaultMaskedError; }; diff --git a/src/usr/diag/prdf/common/plat/axone/axone_mc_actions.rule b/src/usr/diag/prdf/common/plat/axone/axone_mc_actions.rule index aab2297ef..7c639bf5e 100644 --- a/src/usr/diag/prdf/common/plat/axone/axone_mc_actions.rule +++ b/src/usr/diag/prdf/common/plat/axone/axone_mc_actions.rule @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2017,2018 +# Contributors Listed Below - COPYRIGHT 2017,2019 # [+] International Business Machines Corp. # # @@ -28,7 +28,7 @@ ############################################################################### actionclass analyzeMC_LFIR { analyze(gMC_LFIR); }; -actionclass analyzeMCBISTFIR { analyze(gMCBISTFIR); }; +actionclass analyzeMCMISCFIR { analyze(gMCMISCFIR); }; ############################################################################### # Analyze connected diff --git a/src/usr/diag/prdf/common/plat/axone/axone_mc_regs.rule b/src/usr/diag/prdf/common/plat/axone/axone_mc_regs.rule new file mode 100644 index 000000000..150e6895a --- /dev/null +++ b/src/usr/diag/prdf/common/plat/axone/axone_mc_regs.rule @@ -0,0 +1,47 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/axone/axone_mc_regs.rule $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2019 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +################################################################################ +# Additional registers for MC target, not defined in XML +################################################################################ + + ############################################################################ + # PCB Slave Error Regs + ############################################################################ + + register MC_ERROR_REG + { + name "MC PCB Slave error reg"; + scomaddr 0x070F001F; + capture group PllFIRs; + }; + + register MC_CONFIG_REG + { + name "MC PCB Slave config reg"; + scomaddr 0x070F001E; + capture group PllFIRs; + }; + diff --git a/src/usr/diag/prdf/common/plat/axone/axone_mcc.rule b/src/usr/diag/prdf/common/plat/axone/axone_mcc.rule index bf632abbb..31f663c77 100644 --- a/src/usr/diag/prdf/common/plat/axone/axone_mcc.rule +++ b/src/usr/diag/prdf/common/plat/axone/axone_mcc.rule @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2018 +# Contributors Listed Below - COPYRIGHT 2018,2019 # [+] International Business Machines Corp. # # @@ -180,22 +180,22 @@ rule rDSTLFIR group gDSTLFIR filter singlebit, - cs_root_cause + cs_root_cause(0,4) { /** DSTLFIR[0] * AFU initiated Checkstop on Subchannel A */ - (rDSTLFIR, bit(0)) ? defaultMaskedError; + (rDSTLFIR, bit(0)) ? analyze_ocmb_chnl0_UERE; /** DSTLFIR[1] * AFU initiated Recoverable Attn on Subchannel A */ - (rDSTLFIR, bit(1)) ? defaultMaskedError; + (rDSTLFIR, bit(1)) ? analyze_ocmb_chnl0; /** DSTLFIR[2] * AFU initiated Special Attn on Subchannel A */ - (rDSTLFIR, bit(2)) ? defaultMaskedError; + (rDSTLFIR, bit(2)) ? analyze_ocmb_chnl0; /** DSTLFIR[3] * AFU initiated Application Interrupt Attn on Subchannel A @@ -205,17 +205,17 @@ group gDSTLFIR /** DSTLFIR[4] * AFU initiated Checkstop on Subchannel B */ - (rDSTLFIR, bit(4)) ? defaultMaskedError; + (rDSTLFIR, bit(4)) ? analyze_ocmb_chnl1_UERE; /** DSTLFIR[5] * AFU initiated Recoverable Attn on Subchannel B */ - (rDSTLFIR, bit(5)) ? defaultMaskedError; + (rDSTLFIR, bit(5)) ? analyze_ocmb_chnl1; /** DSTLFIR[6] * AFU initiated Special Attn on Subchannel B */ - (rDSTLFIR, bit(6)) ? defaultMaskedError; + (rDSTLFIR, bit(6)) ? analyze_ocmb_chnl1; /** DSTLFIR[7] * AFU initiated Application Interrupt Attn on Subchannel B @@ -225,52 +225,52 @@ group gDSTLFIR /** DSTLFIR[8] * Async crossing parity error */ - (rDSTLFIR, bit(8)) ? defaultMaskedError; + (rDSTLFIR, bit(8)) ? self_th_1; /** DSTLFIR[9] * Async crossing sequence error */ - (rDSTLFIR, bit(9)) ? defaultMaskedError; + (rDSTLFIR, bit(9)) ? self_th_1; /** DSTLFIR[10] * Config reg recoverable parity error */ - (rDSTLFIR, bit(10)) ? defaultMaskedError; + (rDSTLFIR, bit(10)) ? self_th_1; /** DSTLFIR[11] * Config reg fatal parity error */ - (rDSTLFIR, bit(11)) ? defaultMaskedError; + (rDSTLFIR, bit(11)) ? self_th_1; /** DSTLFIR[12] * Subchannel A counter error */ - (rDSTLFIR, bit(12)) ? defaultMaskedError; + (rDSTLFIR, bit(12)) ? chnl0_omi_bus_th_1; /** DSTLFIR[13] * Subchannel B counter error */ - (rDSTLFIR, bit(13)) ? defaultMaskedError; + (rDSTLFIR, bit(13)) ? chnl1_omi_bus_th_1; /** DSTLFIR[14] * Subchannel A timeout error */ - (rDSTLFIR, bit(14)) ? defaultMaskedError; + (rDSTLFIR, bit(14)) ? chnl0_omi_bus_th_32_perDay; /** DSTLFIR[15] * Subchannel B timeout error */ - (rDSTLFIR, bit(15)) ? defaultMaskedError; + (rDSTLFIR, bit(15)) ? chnl1_omi_bus_th_32_perDay; /** DSTLFIR[16] * Subchannel A buffer overuse error */ - (rDSTLFIR, bit(16)) ? defaultMaskedError; + (rDSTLFIR, bit(16)) ? chnl0_ocmb_th_1; /** DSTLFIR[17] * Subchannel B buffer overuse error */ - (rDSTLFIR, bit(17)) ? defaultMaskedError; + (rDSTLFIR, bit(17)) ? chnl1_ocmb_th_1; /** DSTLFIR[18] * Subchannel A DL link down @@ -293,14 +293,29 @@ group gDSTLFIR (rDSTLFIR, bit(21)) ? defaultMaskedError; /** DSTLFIR[22] - * Internal SCOM error + * DSTLFIR channel timeout on subch A */ - (rDSTLFIR, bit(22)) ? defaultMaskedError; + (rDSTLFIR, bit(22)) ? chnl0_omi_bus_th_1; /** DSTLFIR[23] - * Internal SCOM error clone + * DSTLFIR channel timeout on subch B + */ + (rDSTLFIR, bit(23)) ? chnl1_omi_bus_th_1; + + /** DSTLFIR[24:25] + * spare + */ + (rDSTLFIR, bit(24|25)) ? defaultMaskedError; + + /** DSTLFIR[26] + * Internal SCOM Error + */ + (rDSTLFIR, bit(26)) ? defaultMaskedError; + + /** DSTLFIR[27] + * Internal SCOM Error Clone */ - (rDSTLFIR, bit(23)) ? defaultMaskedError; + (rDSTLFIR, bit(27)) ? defaultMaskedError; }; @@ -327,22 +342,22 @@ group gUSTLFIR /** USTLFIR[0] * Chan A unexpected data error */ - (rUSTLFIR, bit(0)) ? defaultMaskedError; + (rUSTLFIR, bit(0)) ? chnl0_ocmb_th_1; /** USTLFIR[1] * Chan B unexpected data error */ - (rUSTLFIR, bit(1)) ? defaultMaskedError; + (rUSTLFIR, bit(1)) ? chnl1_ocmb_th_1; /** USTLFIR[2] * Chan A invalid template error */ - (rUSTLFIR, bit(2)) ? defaultMaskedError; + (rUSTLFIR, bit(2)) ? chnl0_ocmb_th_1; /** USTLFIR[3] * Chan B invalid template error */ - (rUSTLFIR, bit(3)) ? defaultMaskedError; + (rUSTLFIR, bit(3)) ? chnl1_ocmb_th_1; /** USTLFIR[4] * Chan A half speed mode @@ -357,12 +372,12 @@ group gUSTLFIR /** USTLFIR[6] * WDF buffer CE */ - (rUSTLFIR, bit(6)) ? defaultMaskedError; + (rUSTLFIR, bit(6)) ? self_th_32perDay; /** USTLFIR[7] * WDF buffer UE */ - (rUSTLFIR, bit(7)) ? defaultMaskedError; + (rUSTLFIR, bit(7)) ? self_th_1; /** USTLFIR[8] * WDF buffer SUE @@ -372,32 +387,32 @@ group gUSTLFIR /** USTLFIR[9] * WDF buffer overrun */ - (rUSTLFIR, bit(9)) ? defaultMaskedError; + (rUSTLFIR, bit(9)) ? self_th_1; /** USTLFIR[10] * WDF tag parity error */ - (rUSTLFIR, bit(10)) ? defaultMaskedError; + (rUSTLFIR, bit(10)) ? self_th_1; /** USTLFIR[11] * WDF scom sequencer error */ - (rUSTLFIR, bit(11)) ? defaultMaskedError; + (rUSTLFIR, bit(11)) ? self_th_1; /** USTLFIR[12] * WDF pwctl sequencer error */ - (rUSTLFIR, bit(12)) ? defaultMaskedError; + (rUSTLFIR, bit(12)) ? self_th_1; /** USTLFIR[13] * WDF misc_reg parity error */ - (rUSTLFIR, bit(13)) ? defaultMaskedError; + (rUSTLFIR, bit(13)) ? self_th_1; /** USTLFIR[14] * WDF MCA async error */ - (rUSTLFIR, bit(14)) ? defaultMaskedError; + (rUSTLFIR, bit(14)) ? self_th_1; /** USTLFIR[15] * WDF Data Syndrome NE0 @@ -407,32 +422,32 @@ group gUSTLFIR /** USTLFIR[16] * WDF CMT parity error */ - (rUSTLFIR, bit(16)) ? defaultMaskedError; + (rUSTLFIR, bit(16)) ? self_th_1; /** USTLFIR[17] - * TBD + * spare */ (rUSTLFIR, bit(17)) ? defaultMaskedError; /** USTLFIR[18] - * TBD + * spare */ (rUSTLFIR, bit(18)) ? defaultMaskedError; /** USTLFIR[19] - * TBD + * Read Buffers overflowed/underflowed */ - (rUSTLFIR, bit(19)) ? defaultMaskedError; + (rUSTLFIR, bit(19)) ? all_ocmb_and_mcc_th_1; /** USTLFIR[20] * WRT Buffer CE */ - (rUSTLFIR, bit(20)) ? defaultMaskedError; + (rUSTLFIR, bit(20)) ? parent_proc_th_32perDay; /** USTLFIR[21] * WRT Buffer UE */ - (rUSTLFIR, bit(21)) ? defaultMaskedError; + (rUSTLFIR, bit(21)) ? parent_proc_th_1; /** USTLFIR[22] * WRT Buffer SUE @@ -442,12 +457,12 @@ group gUSTLFIR /** USTLFIR[23] * WRT scom sequencer error */ - (rUSTLFIR, bit(23)) ? defaultMaskedError; + (rUSTLFIR, bit(23)) ? self_th_1; /** USTLFIR[24] * WRT misc_reg parity error */ - (rUSTLFIR, bit(24)) ? defaultMaskedError; + (rUSTLFIR, bit(24)) ? self_th_1; /** USTLFIR[25:26] * WRT error information spares @@ -457,22 +472,22 @@ group gUSTLFIR /** USTLFIR[27] * Chan A fail response checkstop */ - (rUSTLFIR, bit(27)) ? defaultMaskedError; + (rUSTLFIR, bit(27)) ? chnl0_ocmb_th_1; /** USTLFIR[28] * Chan B fail response checkstop */ - (rUSTLFIR, bit(28)) ? defaultMaskedError; + (rUSTLFIR, bit(28)) ? chnl1_ocmb_th_1; /** USTLFIR[29] * Chan A fail response recoverable */ - (rUSTLFIR, bit(29)) ? defaultMaskedError; + (rUSTLFIR, bit(29)) ? threshold_and_mask_chnl0_ocmb_th_1; /** USTLFIR[30] * Chan B fail response recoverable */ - (rUSTLFIR, bit(30)) ? defaultMaskedError; + (rUSTLFIR, bit(30)) ? threshold_and_mask_chnl1_ocmb_th_1; /** USTLFIR[31] * Chan A lol drop checkstop @@ -487,72 +502,72 @@ group gUSTLFIR /** USTLFIR[33] * Chan A lol drop recoverable */ - (rUSTLFIR, bit(33)) ? defaultMaskedError; + (rUSTLFIR, bit(33)) ? chnl0_ocmb_H_omi_L_th_1; /** USTLFIR[34] * Chan B lol drop recoverable */ - (rUSTLFIR, bit(34)) ? defaultMaskedError; + (rUSTLFIR, bit(34)) ? chnl1_ocmb_H_omi_L_th_1; /** USTLFIR[35] * Chan A flit parity error */ - (rUSTLFIR, bit(35)) ? defaultMaskedError; + (rUSTLFIR, bit(35)) ? chnl0_omi_th_1; /** USTLFIR[36] * Chan B flit parity error */ - (rUSTLFIR, bit(36)) ? defaultMaskedError; + (rUSTLFIR, bit(36)) ? chnl1_omi_th_1; /** USTLFIR[37] * Chan A fatal parity error */ - (rUSTLFIR, bit(37)) ? defaultMaskedError; + (rUSTLFIR, bit(37)) ? chnl0_omi_th_1; /** USTLFIR[38] * Chan B fatal parity error */ - (rUSTLFIR, bit(38)) ? defaultMaskedError; + (rUSTLFIR, bit(38)) ? chnl1_omi_th_1; /** USTLFIR[39] * Chan A more than 2 data flits for template 9 */ - (rUSTLFIR, bit(39)) ? defaultMaskedError; + (rUSTLFIR, bit(39)) ? chnl0_ocmb_th_1; /** USTLFIR[40] * Chan B more than 2 data flits for template 9 */ - (rUSTLFIR, bit(40)) ? defaultMaskedError; + (rUSTLFIR, bit(40)) ? chnl1_ocmb_th_1; /** USTLFIR[41] * Chan A excess bad data bits */ - (rUSTLFIR, bit(41)) ? defaultMaskedError; + (rUSTLFIR, bit(41)) ? chnl0_ocmb_th_1; /** USTLFIR[42] * Chan B excess bad data bits */ - (rUSTLFIR, bit(42)) ? defaultMaskedError; + (rUSTLFIR, bit(42)) ? chnl1_ocmb_th_1; /** USTLFIR[43] * Chan A memory read data returned in template 0 */ - (rUSTLFIR, bit(43)) ? defaultMaskedError; + (rUSTLFIR, bit(43)) ? chnl0_ocmb_th_1; /** USTLFIR[44] * Chan B memory read data returned in template 0 */ - (rUSTLFIR, bit(44)) ? defaultMaskedError; + (rUSTLFIR, bit(44)) ? chnl1_ocmb_th_1; /** USTLFIR[45] * Chan A MMIO in lol mode */ - (rUSTLFIR, bit(45)) ? defaultMaskedError; + (rUSTLFIR, bit(45)) ? chnl0_omi_th_1; /** USTLFIR[46] * Chan B MMIO in lol mode */ - (rUSTLFIR, bit(46)) ? defaultMaskedError; + (rUSTLFIR, bit(46)) ? chnl1_omi_th_1; /** USTLFIR[47] * Chan A bad data @@ -567,62 +582,62 @@ group gUSTLFIR /** USTLFIR[49] * Chan A excess data error */ - (rUSTLFIR, bit(49)) ? defaultMaskedError; + (rUSTLFIR, bit(49)) ? chnl0_ocmb_th_1; /** USTLFIR[50] * Chan B excess data error */ - (rUSTLFIR, bit(50)) ? defaultMaskedError; + (rUSTLFIR, bit(50)) ? chnl1_ocmb_th_1; /** USTLFIR[51] * Chan A Bad CRC data not valid error */ - (rUSTLFIR, bit(51)) ? defaultMaskedError; + (rUSTLFIR, bit(51)) ? chnl0_omi_th_1; /** USTLFIR[52] * Chan B Bad CRC data not valid error */ - (rUSTLFIR, bit(52)) ? defaultMaskedError; + (rUSTLFIR, bit(52)) ? chnl1_omi_th_1; /** USTLFIR[53] * Chan A FIFO overflow error */ - (rUSTLFIR, bit(53)) ? defaultMaskedError; + (rUSTLFIR, bit(53)) ? chnl0_omi_th_1; /** USTLFIR[54] * Chan B FIFO overflow error */ - (rUSTLFIR, bit(54)) ? defaultMaskedError; + (rUSTLFIR, bit(54)) ? chnl1_omi_th_1; /** USTLFIR[55] * Chan A invalid cmd error */ - (rUSTLFIR, bit(55)) ? defaultMaskedError; + (rUSTLFIR, bit(55)) ? chnl0_ocmb_th_1; /** USTLFIR[56] * Chan B invalid cmd error */ - (rUSTLFIR, bit(56)) ? defaultMaskedError; + (rUSTLFIR, bit(56)) ? chnl1_ocmb_th_1; /** USTLFIR[57] * Fatal reg parity error */ - (rUSTLFIR, bit(57)) ? defaultMaskedError; + (rUSTLFIR, bit(57)) ? self_th_1; /** USTLFIR[58] * Recoverable reg parity error */ - (rUSTLFIR, bit(58)) ? defaultMaskedError; + (rUSTLFIR, bit(58)) ? self_th_1; /** USTLFIR[59] * Chan A invalid DL DP combo */ - (rUSTLFIR, bit(59)) ? defaultMaskedError; + (rUSTLFIR, bit(59)) ? chnl0_ocmb_th_1; /** USTLFIR[60] * Chan B invalid DL DP combo */ - (rUSTLFIR, bit(60)) ? defaultMaskedError; + (rUSTLFIR, bit(60)) ? chnl1_ocmb_th_1; /** USTLFIR[61] * spare diff --git a/src/usr/diag/prdf/common/plat/axone/axone_mcc_actions.rule b/src/usr/diag/prdf/common/plat/axone/axone_mcc_actions.rule index 38edbaaea..e34035165 100644 --- a/src/usr/diag/prdf/common/plat/axone/axone_mcc_actions.rule +++ b/src/usr/diag/prdf/common/plat/axone/axone_mcc_actions.rule @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2018 +# Contributors Listed Below - COPYRIGHT 2018,2019 # [+] International Business Machines Corp. # # @@ -24,9 +24,163 @@ # IBM_PROLOG_END_TAG ################################################################################ +# Callouts +################################################################################ + +actionclass chnl0_omi +{ + callout(connected(TYPE_OMI,0), MRU_MED); +}; + +actionclass chnl1_omi +{ + callout(connected(TYPE_OMI,1), MRU_MED); +}; + +actionclass chnl0_omi_L +{ + callout(connected(TYPE_OMI,0), MRU_LOW); +}; + +actionclass chnl1_omi_L +{ + callout(connected(TYPE_OMI,1), MRU_LOW); +}; + +actionclass chnl0_ocmb +{ + callout(connected(TYPE_OCMB_CHIP,0), MRU_MED); +}; + +actionclass chnl1_ocmb +{ + callout(connected(TYPE_OCMB_CHIP,1), MRU_MED); +}; + +actionclass chnl0_omi_bus +{ + funccall("omiParentCalloutBusInterfacePlugin_0"); +}; + +actionclass chnl1_omi_bus +{ + funccall("omiParentCalloutBusInterfacePlugin_1"); +}; + +actionclass chnl0_omi_bus_th_1 +{ + chnl0_omi_bus; + threshold1; +}; + +actionclass chnl1_omi_bus_th_1 +{ + chnl1_omi_bus; + threshold1; +}; + +actionclass chnl0_omi_bus_th_32_perDay +{ + chnl0_omi_bus; + threshold32pday; +}; + +actionclass chnl1_omi_bus_th_32_perDay +{ + chnl1_omi_bus; + threshold32pday; +}; + +actionclass chnl0_omi_th_1 +{ + chnl0_omi; + threshold1; +}; + +actionclass chnl1_omi_th_1 +{ + chnl1_omi; + threshold1; +}; + +actionclass chnl0_ocmb_th_1 +{ + chnl0_ocmb; + threshold1; +}; + +actionclass chnl1_ocmb_th_1 +{ + chnl1_ocmb; + threshold1; +}; + +actionclass all_ocmb_and_mcc_th_1 +{ + chnl0_ocmb; + chnl1_ocmb; + calloutSelfMed; + threshold1; +}; + +actionclass chnl0_ocmb_H_omi_L_th_1 +{ + chnl0_ocmb; + chnl0_omi_L; + threshold1; +}; + +actionclass chnl1_ocmb_H_omi_L_th_1 +{ + chnl1_ocmb; + chnl1_omi_L; + threshold1; +}; + +actionclass threshold_and_mask_chnl0_ocmb_th_1 +{ + threshold_and_mask; + chnl0_ocmb; + threshold1; +}; + +actionclass threshold_and_mask_chnl1_ocmb_th_1 +{ + threshold_and_mask; + chnl1_ocmb; + threshold1; +}; + +################################################################################ # Analyze groups ################################################################################ actionclass analyzeDSTLFIR { analyze(gDSTLFIR); }; actionclass analyzeUSTLFIR { analyze(gUSTLFIR); }; +################################################################################ +# Analyze connected +################################################################################ + +actionclass analyze_ocmb_chnl0 +{ + try( funccall("checkOcmb_0"), analyze(connected(TYPE_OCMB_CHIP, 0)) ); +}; + +actionclass analyze_ocmb_chnl1 +{ + try( funccall("checkOcmb_1"), analyze(connected(TYPE_OCMB_CHIP, 1)) ); +}; + +actionclass analyze_ocmb_chnl0_UERE +{ + SueSource; + analyze_ocmb_chnl0; +}; + +actionclass analyze_ocmb_chnl1_UERE +{ + SueSource; + analyze_ocmb_chnl1; +}; + diff --git a/src/usr/diag/prdf/common/plat/axone/axone_mcc_regs.rule b/src/usr/diag/prdf/common/plat/axone/axone_mcc_regs.rule new file mode 100644 index 000000000..001a54e5c --- /dev/null +++ b/src/usr/diag/prdf/common/plat/axone/axone_mcc_regs.rule @@ -0,0 +1,80 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/axone/axone_mcc_regs.rule $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2019 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + + +############################################################################### +# Additional registers for mcc, not defined in XML +############################################################################### + + ########################################################################### + # P9 Axone target Channel Fail Config registers + ########################################################################### + + register DSTLCFG2 + { + name "P9 Axone DSTL Error Injection Register"; + scomaddr 0x0701090E; + capture group default; + }; + + register USTLFAILMASK + { + name "P9 Axone USTL Fail Response Channel Fail Mask"; + scomaddr 0x07010A13; + capture group default; + }; + + ########################################################################### + # P9 Axone target DSTLFIR + ########################################################################### + + register DSTLFIR_AND + { + name "P9 MCC target DSTLFIR atomic AND"; + scomaddr 0x07010901; + capture group never; + access write_only; + }; + + register DSTLFIR_MASK_OR + { + name "P9 MCC target DSTLFIR MASK atomic OR"; + scomaddr 0x07010905; + capture group never; + access write_only; + }; + + ########################################################################### + # P9 Axone target USTLFIR + ########################################################################### + + register USTLFIR_MASK_OR + { + name "P9 MCC target USTLFIR MASK atomic OR"; + scomaddr 0x07010A05; + capture group never; + access write_only; + }; + diff --git a/src/usr/diag/prdf/common/plat/axone/axone_mi.rule b/src/usr/diag/prdf/common/plat/axone/axone_mi.rule index 078163819..56366a7f5 100644 --- a/src/usr/diag/prdf/common/plat/axone/axone_mi.rule +++ b/src/usr/diag/prdf/common/plat/axone/axone_mi.rule @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2018 +# Contributors Listed Below - COPYRIGHT 2018,2019 # [+] International Business Machines Corp. # # @@ -148,27 +148,27 @@ group gMCFIR /** MCFIR[0] * MC internal recoverable error */ - (rMCFIR, bit(0)) ? defaultMaskedError; + (rMCFIR, bit(0)) ? self_th_1; /** MCFIR[1] * MC internal non recoverable error */ - (rMCFIR, bit(1)) ? defaultMaskedError; + (rMCFIR, bit(1)) ? parent_proc_th_1; /** MCFIR[2] * Powerbus protocol error */ - (rMCFIR, bit(2)) ? defaultMaskedError; + (rMCFIR, bit(2)) ? level2_th_1; /** MCFIR[3] * Inband bar hit with incorrect ttype */ - (rMCFIR, bit(3)) ? defaultMaskedError; + (rMCFIR, bit(3)) ? level2_M_self_L_th_1; /** MCFIR[4] * Multiple bar */ - (rMCFIR, bit(4)) ? defaultMaskedError; + (rMCFIR, bit(4)) ? self_th_1; /** MCFIR[5] * PB write ECC syndrome NE0 @@ -183,7 +183,7 @@ group gMCFIR /** MCFIR[8] * Command list timeout */ - (rMCFIR, bit(8)) ? defaultMaskedError; + (rMCFIR, bit(8)) ? threshold_and_mask_level2; /** MCFIR[9:10] * reserved diff --git a/src/usr/diag/prdf/common/plat/axone/axone_mi_regs.rule b/src/usr/diag/prdf/common/plat/axone/axone_mi_regs.rule index 0e47e05a5..d9441d719 100644 --- a/src/usr/diag/prdf/common/plat/axone/axone_mi_regs.rule +++ b/src/usr/diag/prdf/common/plat/axone/axone_mi_regs.rule @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2018 +# Contributors Listed Below - COPYRIGHT 2018,2019 # [+] International Business Machines Corp. # # @@ -48,34 +48,66 @@ capture group default; }; - register MCFGP + register MCFGP0 { - name "MCFGP"; - scomaddr 0x501080A; + name "MCFGP0"; + scomaddr 0x0501080A; capture group default; capture group MirrorConfig; }; - register MCFGPA + register MCFGP1 { - name "MCFGPA"; + name "MCFGP1"; scomaddr 0x0501080B; capture group default; capture group MirrorConfig; }; - register MCFGPM + register MCFGP0A { - name "MCFGPM"; - scomaddr 0x501080C; + name "MCFGP0A"; + scomaddr 0x0501080E; capture group default; capture group MirrorConfig; }; - register MCFGPMA + register MCFGP1A { - name "MCFGPMA"; - scomaddr 0x0501080D; + name "MCFGP1A"; + scomaddr 0x0501080F; + capture group default; + capture group MirrorConfig; + }; + + register MCFGPM0 + { + name "MCFGPM0"; + scomaddr 0x5010820; + capture group default; + capture group MirrorConfig; + }; + + register MCFGPM0A + { + name "MCFGPM0A"; + scomaddr 0x05010821; + capture group default; + capture group MirrorConfig; + }; + + register MCFGPM1 + { + name "MCFGPM1"; + scomaddr 0x5010830; + capture group default; + capture group MirrorConfig; + }; + + register MCFGPM1A + { + name "MCFGPM1A"; + scomaddr 0x05010831; capture group default; capture group MirrorConfig; }; diff --git a/src/usr/diag/prdf/common/plat/axone/axone_npu.rule b/src/usr/diag/prdf/common/plat/axone/axone_npu.rule index ede5ef5cc..49c71d74a 100644 --- a/src/usr/diag/prdf/common/plat/axone/axone_npu.rule +++ b/src/usr/diag/prdf/common/plat/axone/axone_npu.rule @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2018 +# Contributors Listed Below - COPYRIGHT 2018,2019 # [+] International Business Machines Corp. # # @@ -214,7 +214,7 @@ rule rNPU0FIR group gNPU0FIR filter singlebit, - cs_root_cause(1,2,3,4,5,6,7,9,10,16,18,29,31,42,44) + cs_root_cause(1,2,3,4,5,6,7,9,10,16,18,19,25,29,31,40,42,44,45) { /** NPU0FIR[0] * NTL array CE @@ -354,7 +354,7 @@ group gNPU0FIR /** NPU0FIR[27] * Invalid access to secure memory attempted */ - (rNPU0FIR, bit(27)) ? defaultMaskedError; + (rNPU0FIR, bit(27)) ? self_th_1; /** NPU0FIR[28] * spare @@ -489,12 +489,12 @@ rule rNPU1FIR group gNPU1FIR filter singlebit, - cs_root_cause + cs_root_cause(0,2,4,6,8,10,13,14,15,20,22,25,27,29,31,32,33,34,35,37,39,40,41,42,47,49,51,53,55,57) { /** NPU1FIR[0] * NDL Brick0 stall */ - (rNPU1FIR, bit(0)) ? defaultMaskedError; + (rNPU1FIR, bit(0)) ? self_th_1; /** NPU1FIR[1] * NDL Brick0 nostall @@ -504,7 +504,7 @@ group gNPU1FIR /** NPU1FIR[2] * NDL Brick1 stall */ - (rNPU1FIR, bit(2)) ? defaultMaskedError; + (rNPU1FIR, bit(2)) ? self_th_1; /** NPU1FIR[3] * NDL Brick1 nostall @@ -514,7 +514,7 @@ group gNPU1FIR /** NPU1FIR[4] * NDL Brick2 stall */ - (rNPU1FIR, bit(4)) ? defaultMaskedError; + (rNPU1FIR, bit(4)) ? self_th_1; /** NPU1FIR[5] * NDL Brick2 nostall @@ -524,7 +524,7 @@ group gNPU1FIR /** NPU1FIR[6] * NDL Brick3 stall */ - (rNPU1FIR, bit(6)) ? defaultMaskedError; + (rNPU1FIR, bit(6)) ? self_th_1; /** NPU1FIR[7] * NDL Brick3 nostall @@ -534,7 +534,7 @@ group gNPU1FIR /** NPU1FIR[8] * NDL Brick4 stall */ - (rNPU1FIR, bit(8)) ? defaultMaskedError; + (rNPU1FIR, bit(8)) ? self_th_1; /** NPU1FIR[9] * NDL Brick4 nostall @@ -544,7 +544,7 @@ group gNPU1FIR /** NPU1FIR[10] * NDL Brick5 stall */ - (rNPU1FIR, bit(10)) ? defaultMaskedError; + (rNPU1FIR, bit(10)) ? self_th_1; /** NPU1FIR[11] * NDL Brick5 nostall @@ -554,22 +554,22 @@ group gNPU1FIR /** NPU1FIR[12] * MISC Register ring error (ie noack) */ - (rNPU1FIR, bit(12)) ? defaultMaskedError; + (rNPU1FIR, bit(12)) ? self_th_32perDay; /** NPU1FIR[13] - * MISC Parity error from ibr addr regi + * MISC Parity error on MISC Cntrl reg */ - (rNPU1FIR, bit(13)) ? defaultMaskedError; + (rNPU1FIR, bit(13)) ? self_th_1; /** NPU1FIR[14] * MISC Parity error on SCOM D/A addr reg */ - (rNPU1FIR, bit(14)) ? defaultMaskedError; + (rNPU1FIR, bit(14)) ? self_th_1; /** NPU1FIR[15] * MISC Parity error on MISC Cntrl reg */ - (rNPU1FIR, bit(15)) ? defaultMaskedError; + (rNPU1FIR, bit(15)) ? self_th_1; /** NPU1FIR[16] * Reserved @@ -594,7 +594,7 @@ group gNPU1FIR /** NPU1FIR[20] * ATS Effective Address hit multiple TCE */ - (rNPU1FIR, bit(20)) ? defaultMaskedError; + (rNPU1FIR, bit(20)) ? self_th_1; /** NPU1FIR[21] * ATS TCE Page access error @@ -604,72 +604,72 @@ group gNPU1FIR /** NPU1FIR[22] * ATS Timeout on TCE tree walk */ - (rNPU1FIR, bit(22)) ? defaultMaskedError; + (rNPU1FIR, bit(22)) ? self_th_1; /** NPU1FIR[23] * ATS Parity error on TCE cache dir array */ - (rNPU1FIR, bit(23)) ? defaultMaskedError; + (rNPU1FIR, bit(23)) ? self_th_32perDay; /** NPU1FIR[24] * ATS Parity error on TCE cache data array */ - (rNPU1FIR, bit(24)) ? defaultMaskedError; + (rNPU1FIR, bit(24)) ? self_th_32perDay; /** NPU1FIR[25] * ATS ECC UE on Effective Address array */ - (rNPU1FIR, bit(25)) ? defaultMaskedError; + (rNPU1FIR, bit(25)) ? self_th_1; /** NPU1FIR[26] * ATS ECC CE on Effective Address array */ - (rNPU1FIR, bit(26)) ? defaultMaskedError; + (rNPU1FIR, bit(26)) ? self_th_32perDay; /** NPU1FIR[27] * ATS ECC UE on TDRmem array */ - (rNPU1FIR, bit(27)) ? defaultMaskedError; + (rNPU1FIR, bit(27)) ? self_th_1; /** NPU1FIR[28] * ATS ECC CE on TDRmem array */ - (rNPU1FIR, bit(28)) ? defaultMaskedError; + (rNPU1FIR, bit(28)) ? self_th_32perDay; /** NPU1FIR[29] * ATS ECC UE on CQ CTL DMA Read */ - (rNPU1FIR, bit(29)) ? defaultMaskedError; + (rNPU1FIR, bit(29)) ? self_th_1; /** NPU1FIR[30] * ATS ECC CE on CQ CTL DMA Read */ - (rNPU1FIR, bit(30)) ? defaultMaskedError; + (rNPU1FIR, bit(30)) ? self_th_32perDay; /** NPU1FIR[31] * ATS Parity error on TVT entry */ - (rNPU1FIR, bit(31)) ? defaultMaskedError; + (rNPU1FIR, bit(31)) ? self_th_1; /** NPU1FIR[32] * ATS Parity err on IODA Address Reg */ - (rNPU1FIR, bit(32)) ? defaultMaskedError; + (rNPU1FIR, bit(32)) ? self_th_1; /** NPU1FIR[33] * ATS Parity error on ATS Control Register */ - (rNPU1FIR, bit(33)) ? defaultMaskedError; + (rNPU1FIR, bit(33)) ? self_th_1; /** NPU1FIR[34] - * ATS Parity error on ATS Timeout Control Register + * ATS Parity error on ATS reg */ - (rNPU1FIR, bit(34)) ? defaultMaskedError; + (rNPU1FIR, bit(34)) ? self_th_1; /** NPU1FIR[35] * ATS Invalid IODA Table Select entry */ - (rNPU1FIR, bit(35)) ? defaultMaskedError; + (rNPU1FIR, bit(35)) ? self_th_1; /** NPU1FIR[36] * Reserved @@ -679,7 +679,7 @@ group gNPU1FIR /** NPU1FIR[37] * Kill xlate epoch timeout */ - (rNPU1FIR, bit(37)) ? defaultMaskedError; + (rNPU1FIR, bit(37)) ? self_th_1; /** NPU1FIR[38] * PEE secure SMF not secure @@ -689,17 +689,32 @@ group gNPU1FIR /** NPU1FIR[39] * XSL in suspend mode when OTL sends cmd */ - (rNPU1FIR, bit(39)) ? defaultMaskedError; + (rNPU1FIR, bit(39)) ? self_th_1; + + /** NPU1FIR[40] + * Unsupported page size + */ + (rNPU1FIR, bit(40)) ? self_th_1; + + /** NPU1FIR[41] + * Unexpected XLATE release + */ + (rNPU1FIR, bit(41)) ? self_th_1; + + /** NPU1FIR[42] + * Kill XLATE done fail + */ + (rNPU1FIR, bit(42)) ? self_th_1; - /** NPU1FIR[40:46] + /** NPU1FIR[43:46] * Reserved */ - (rNPU1FIR, bit(40|41|42|43|44|45|46)) ? defaultMaskedError; + (rNPU1FIR, bit(43|44|45|46)) ? defaultMaskedError; /** NPU1FIR[47] * NDL Brick6 stall */ - (rNPU1FIR, bit(47)) ? defaultMaskedError; + (rNPU1FIR, bit(47)) ? self_th_1; /** NPU1FIR[48] * NDL Brick6 nostall @@ -709,7 +724,7 @@ group gNPU1FIR /** NPU1FIR[49] * NDL Brick7 stall */ - (rNPU1FIR, bit(49)) ? defaultMaskedError; + (rNPU1FIR, bit(49)) ? self_th_1; /** NPU1FIR[50] * NDL Brick7 nostall @@ -719,7 +734,7 @@ group gNPU1FIR /** NPU1FIR[51] * NDL Brick8 stall */ - (rNPU1FIR, bit(51)) ? defaultMaskedError; + (rNPU1FIR, bit(51)) ? self_th_1; /** NPU1FIR[52] * NDL Brick8 nostall @@ -729,7 +744,7 @@ group gNPU1FIR /** NPU1FIR[53] * NDL Brick9 stall */ - (rNPU1FIR, bit(53)) ? defaultMaskedError; + (rNPU1FIR, bit(53)) ? self_th_1; /** NPU1FIR[54] * NDL Brick9 nostall @@ -739,7 +754,7 @@ group gNPU1FIR /** NPU1FIR[55] * NDL Brick10 stall */ - (rNPU1FIR, bit(55)) ? defaultMaskedError; + (rNPU1FIR, bit(55)) ? self_th_1; /** NPU1FIR[56] * NDL Brick10 nostall @@ -749,7 +764,7 @@ group gNPU1FIR /** NPU1FIR[57] * NDL Brick11 stall */ - (rNPU1FIR, bit(57)) ? defaultMaskedError; + (rNPU1FIR, bit(57)) ? self_th_1; /** NPU1FIR[58] * NDL Brick11 nostall @@ -762,22 +777,22 @@ group gNPU1FIR (rNPU1FIR, bit(59)) ? defaultMaskedError; /** NPU1FIR[60] - * MISC SCOM ring 0 sat 0 signaled internal FSM err + * Misc SCOM ring 0 sat 0 signalled internal FSM error */ (rNPU1FIR, bit(60)) ? defaultMaskedError; /** NPU1FIR[61] - * MISC SCOM ring 0 sat 1 signaled internal FSM err + * Misc SCOM ring 0 sat 1 signalled internal FSM error */ (rNPU1FIR, bit(61)) ? defaultMaskedError; /** NPU1FIR[62] - * Scom Error + * scom error */ (rNPU1FIR, bit(62)) ? defaultMaskedError; /** NPU1FIR[63] - * Scom Error + * scom error */ (rNPU1FIR, bit(63)) ? defaultMaskedError; @@ -799,7 +814,7 @@ rule rNPU2FIR group gNPU2FIR filter singlebit, - cs_root_cause + cs_root_cause(4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,20,21,22,23,24,25,26,27,28,29,30,31,36,37,38,39,40,41,42,43,45,47,48,50,51,52) { /** NPU2FIR[0] * OTL Brick2 translation fault @@ -824,145 +839,145 @@ group gNPU2FIR /** NPU2FIR[4] * OTL TL credit ctr overflow */ - (rNPU2FIR, bit(4)) ? defaultMaskedError; + (rNPU2FIR, bit(4)) ? self_th_1; /** NPU2FIR[5] * OTL RX acTag invalid */ - (rNPU2FIR, bit(5)) ? defaultMaskedError; + (rNPU2FIR, bit(5)) ? self_th_1; /** NPU2FIR[6] * OTL RX acTag points to an invalid entry. */ - (rNPU2FIR, bit(6)) ? defaultMaskedError; + (rNPU2FIR, bit(6)) ? self_th_1; /** NPU2FIR[7] * OTL RX reserved opcode used. */ - (rNPU2FIR, bit(7)) ? defaultMaskedError; + (rNPU2FIR, bit(7)) ? self_th_1; /** NPU2FIR[8] * OTL RX rtn_tl_credit cmd outside slot0. */ - (rNPU2FIR, bit(8)) ? defaultMaskedError; + (rNPU2FIR, bit(8)) ? self_th_1; /** NPU2FIR[9] * OTL RX bad opcode and template combo */ - (rNPU2FIR, bit(9)) ? defaultMaskedError; + (rNPU2FIR, bit(9)) ? self_th_1; /** NPU2FIR[10] * OTL RX unsupported template format. */ - (rNPU2FIR, bit(10)) ? defaultMaskedError; + (rNPU2FIR, bit(10)) ? self_th_1; /** NPU2FIR[11] * OTL RX bad template x00 format. */ - (rNPU2FIR, bit(11)) ? defaultMaskedError; + (rNPU2FIR, bit(11)) ? self_th_1; /** NPU2FIR[12] * OTL RX control flit overrun. */ - (rNPU2FIR, bit(12)) ? defaultMaskedError; + (rNPU2FIR, bit(12)) ? self_th_1; /** NPU2FIR[13] * OTL RX unexpected data flit. */ - (rNPU2FIR, bit(13)) ? defaultMaskedError; + (rNPU2FIR, bit(13)) ? self_th_1; /** NPU2FIR[14] * OTL RX DL link down. */ - (rNPU2FIR, bit(14)) ? defaultMaskedError; + (rNPU2FIR, bit(14)) ? self_th_1; /** NPU2FIR[15] * OTL RX bad data received on command. */ - (rNPU2FIR, bit(15)) ? defaultMaskedError; + (rNPU2FIR, bit(15)) ? self_th_1; /** NPU2FIR[16] * OTL RX bad data received on response. */ - (rNPU2FIR, bit(16)) ? defaultMaskedError; + (rNPU2FIR, bit(16)) ? self_th_1; /** NPU2FIR[17] * OTL RX AP response not allowed */ - (rNPU2FIR, bit(17)) ? defaultMaskedError; + (rNPU2FIR, bit(17)) ? self_th_1; /** NPU2FIR[18] * OR of all OTL parity errors. */ - (rNPU2FIR, bit(18)) ? defaultMaskedError; + (rNPU2FIR, bit(18)) ? self_th_1; /** NPU2FIR[19] * OR of all OTL ECC CE errors. */ - (rNPU2FIR, bit(19)) ? defaultMaskedError; + (rNPU2FIR, bit(19)) ? self_th_32perDay; /** NPU2FIR[20] * OR of all OTL ECC UE errors. */ - (rNPU2FIR, bit(20)) ? defaultMaskedError; + (rNPU2FIR, bit(20)) ? self_th_1; /** NPU2FIR[21] * RXO OP Errors. */ - (rNPU2FIR, bit(21)) ? defaultMaskedError; + (rNPU2FIR, bit(21)) ? self_th_1; /** NPU2FIR[22] * RXO Internal Errors. */ - (rNPU2FIR, bit(22)) ? defaultMaskedError; + (rNPU2FIR, bit(22)) ? self_th_1; /** NPU2FIR[23] * OTL RXI fifo overrun. */ - (rNPU2FIR, bit(23)) ? defaultMaskedError; + (rNPU2FIR, bit(23)) ? self_th_1; /** NPU2FIR[24] * OTL RXI ctrl flit data run len invalid. */ - (rNPU2FIR, bit(24)) ? defaultMaskedError; + (rNPU2FIR, bit(24)) ? self_th_1; /** NPU2FIR[25] * OTL RXI opcode specifies dL=0b00. */ - (rNPU2FIR, bit(25)) ? defaultMaskedError; + (rNPU2FIR, bit(25)) ? self_th_1; /** NPU2FIR[26] * OTL RXI bad data received vc2 */ - (rNPU2FIR, bit(26)) ? defaultMaskedError; + (rNPU2FIR, bit(26)) ? self_th_1; /** NPU2FIR[27] * OTL RXI dcp2 fifo overrun */ - (rNPU2FIR, bit(27)) ? defaultMaskedError; + (rNPU2FIR, bit(27)) ? self_th_1; /** NPU2FIR[28] * OTL RXI vc1 fifo overrun */ - (rNPU2FIR, bit(28)) ? defaultMaskedError; + (rNPU2FIR, bit(28)) ? self_th_1; /** NPU2FIR[29] * OTL RXI vc2 fifo overrun */ - (rNPU2FIR, bit(29)) ? defaultMaskedError; + (rNPU2FIR, bit(29)) ? self_th_1; /** NPU2FIR[30] - * Reserved + * OTL RXI Data link not supported */ - (rNPU2FIR, bit(30)) ? defaultMaskedError; + (rNPU2FIR, bit(30)) ? self_th_1; /** NPU2FIR[31] * OTL TXI opcode error */ - (rNPU2FIR, bit(31)) ? defaultMaskedError; + (rNPU2FIR, bit(31)) ? self_th_1; /** NPU2FIR[32] - * Malformed packet error type 4 + * OTL RXI reserved field not equal to 0 */ (rNPU2FIR, bit(32)) ? defaultMaskedError; @@ -974,42 +989,42 @@ group gNPU2FIR /** NPU2FIR[36] * MMIO invalidate while one in progress. */ - (rNPU2FIR, bit(36)) ? defaultMaskedError; + (rNPU2FIR, bit(36)) ? self_th_1; /** NPU2FIR[37] * Unexpected ITAG on itag completion pt 0 */ - (rNPU2FIR, bit(37)) ? defaultMaskedError; + (rNPU2FIR, bit(37)) ? self_th_1; /** NPU2FIR[38] * Unexpected ITAG on itag completion pt 1 */ - (rNPU2FIR, bit(38)) ? defaultMaskedError; + (rNPU2FIR, bit(38)) ? self_th_1; /** NPU2FIR[39] * Unexpected Read PEE completion. */ - (rNPU2FIR, bit(39)) ? defaultMaskedError; + (rNPU2FIR, bit(39)) ? self_th_1; /** NPU2FIR[40] * Unexpected Checkout response. */ - (rNPU2FIR, bit(40)) ? defaultMaskedError; + (rNPU2FIR, bit(40)) ? self_th_1; /** NPU2FIR[41] * Translation request but SPAP is invalid. */ - (rNPU2FIR, bit(41)) ? defaultMaskedError; + (rNPU2FIR, bit(41)) ? self_th_1; /** NPU2FIR[42] * Read a PEE which was not valid. */ - (rNPU2FIR, bit(42)) ? defaultMaskedError; + (rNPU2FIR, bit(42)) ? self_th_1; /** NPU2FIR[43] * Bloom filter protection error. */ - (rNPU2FIR, bit(43)) ? defaultMaskedError; + (rNPU2FIR, bit(43)) ? self_th_1; /** NPU2FIR[44] * Translation request to non-valid TA @@ -1017,44 +1032,44 @@ group gNPU2FIR (rNPU2FIR, bit(44)) ? defaultMaskedError; /** NPU2FIR[45] - * TA Translation request to an invalid TA + * TA translation request to an invalid TA */ - (rNPU2FIR, bit(45)) ? defaultMaskedError; + (rNPU2FIR, bit(45)) ? self_th_1; /** NPU2FIR[46] * correctable array error (SBE). */ - (rNPU2FIR, bit(46)) ? defaultMaskedError; + (rNPU2FIR, bit(46)) ? self_th_32perDay; /** NPU2FIR[47] * array error (UE or parity). */ - (rNPU2FIR, bit(47)) ? defaultMaskedError; + (rNPU2FIR, bit(47)) ? self_th_1; /** NPU2FIR[48] * S/TLBI buffer overflow. */ - (rNPU2FIR, bit(48)) ? defaultMaskedError; + (rNPU2FIR, bit(48)) ? self_th_1; /** NPU2FIR[49] * SBE CE on Pb cout rsp or PEE read data. */ - (rNPU2FIR, bit(49)) ? defaultMaskedError; + (rNPU2FIR, bit(49)) ? self_th_32perDay; /** NPU2FIR[50] * UE on Pb cut rsp or PEE read data. */ - (rNPU2FIR, bit(50)) ? defaultMaskedError; + (rNPU2FIR, bit(50)) ? self_th_1; /** NPU2FIR[51] * SUE on Pb chkout rsp or Pb PEE rd data. */ - (rNPU2FIR, bit(51)) ? defaultMaskedError; + (rNPU2FIR, bit(51)) ? self_th_1; /** NPU2FIR[52] - * PA mem_hit when bar mode is nonzero + * PA mem hit when bar mode is nonzero */ - (rNPU2FIR, bit(52)) ? defaultMaskedError; + (rNPU2FIR, bit(52)) ? self_th_1; /** NPU2FIR[53] * XSL Reserved, macro bit 17. diff --git a/src/usr/diag/prdf/common/plat/axone/axone_obus.rule b/src/usr/diag/prdf/common/plat/axone/axone_obus.rule index a079fac59..1a346c417 100644 --- a/src/usr/diag/prdf/common/plat/axone/axone_obus.rule +++ b/src/usr/diag/prdf/common/plat/axone/axone_obus.rule @@ -469,12 +469,12 @@ group gIOOLFIR /** IOOLFIR[8] * link0 nak received */ - (rIOOLFIR, bit(8)) ? defaultMaskedError; + (rIOOLFIR, bit(8)) ? threshold_and_mask_self_non_smp_only; /** IOOLFIR[9] * link1 nak received */ - (rIOOLFIR, bit(9)) ? defaultMaskedError; + (rIOOLFIR, bit(9)) ? threshold_and_mask_self_non_smp_only; /** IOOLFIR[10] * link0 replay buffer full @@ -499,22 +499,22 @@ group gIOOLFIR /** IOOLFIR[14] * link0 sl ecc correctable */ - (rIOOLFIR, bit(14)) ? threshold_and_mask_self; + (rIOOLFIR, bit(14)) ? threshold_and_mask_self_smp_only; /** IOOLFIR[15] * link1 sl ecc correctable */ - (rIOOLFIR, bit(15)) ? threshold_and_mask_self; + (rIOOLFIR, bit(15)) ? threshold_and_mask_self_smp_only; /** IOOLFIR[16] * link0 sl ecc ue */ - (rIOOLFIR, bit(16)) ? threshold_and_mask_self; + (rIOOLFIR, bit(16)) ? threshold_and_mask_self_smp_only; /** IOOLFIR[17] * link1 sl ecc ue */ - (rIOOLFIR, bit(17)) ? threshold_and_mask_self; + (rIOOLFIR, bit(17)) ? threshold_and_mask_self_smp_only; /** IOOLFIR[18] * link0 retrain threshold @@ -597,12 +597,12 @@ group gIOOLFIR (rIOOLFIR, bit(33)) ? defaultMaskedError; /** IOOLFIR[34] - * link0 num replay + * link0 num replay or no forward progress */ (rIOOLFIR, bit(34)) ? defaultMaskedError; /** IOOLFIR[35] - * link1 num replay + * link1 num replay or no forward progress */ (rIOOLFIR, bit(35)) ? defaultMaskedError; @@ -619,12 +619,12 @@ group gIOOLFIR /** IOOLFIR[38] * link0 prbs select error */ - (rIOOLFIR, bit(38)) ? threshold_and_mask_self; + (rIOOLFIR, bit(38)) ? threshold_and_mask_self_smp_only; /** IOOLFIR[39] * link1 prbs select error */ - (rIOOLFIR, bit(39)) ? threshold_and_mask_self; + (rIOOLFIR, bit(39)) ? threshold_and_mask_self_smp_only; /** IOOLFIR[40] * link0 tcomplete bad @@ -639,102 +639,102 @@ group gIOOLFIR /** IOOLFIR[42] * link0 no spare lane available */ - (rIOOLFIR, bit(42)) ? obusSmpCallout_L0; + (rIOOLFIR, bit(42)) ? obusSmpCallout_L0_smp_only; /** IOOLFIR[43] * link1 no spare lane available */ - (rIOOLFIR, bit(43)) ? obusSmpCallout_L1; + (rIOOLFIR, bit(43)) ? obusSmpCallout_L1_smp_only; /** IOOLFIR[44] - * link0 spare done + * link0 spare done or degraded mode */ - (rIOOLFIR, bit(44)) ? obusSmpCallout_th32_L0; + (rIOOLFIR, bit(44)) ? spare_lane_degraded_mode_L0; /** IOOLFIR[45] - * link1 spare done + * link1 spare done or degraded mode */ - (rIOOLFIR, bit(45)) ? obusSmpCallout_th32_L1; + (rIOOLFIR, bit(45)) ? spare_lane_degraded_mode_L1; /** IOOLFIR[46] * link0 too many crc errors */ - (rIOOLFIR, bit(46)) ? obusSmpCallout_L0; + (rIOOLFIR, bit(46)) ? obusSmpCallout_L0_smp_only; /** IOOLFIR[47] * link1 too many crc errors */ - (rIOOLFIR, bit(47)) ? obusSmpCallout_L1; + (rIOOLFIR, bit(47)) ? obusSmpCallout_L1_smp_only; /** IOOLFIR[48] - * link0 npu error + * link0 npu error or orx otx dlx errors */ (rIOOLFIR, bit(48)) ? threshold_and_mask_self; /** IOOLFIR[49] - * link1 npu error + * link1 npu error or orx otx dlx errors */ (rIOOLFIR, bit(49)) ? threshold_and_mask_self; /** IOOLFIR[50] * linkx npu error */ - (rIOOLFIR, bit(50)) ? threshold_and_mask_self; + (rIOOLFIR, bit(50)) ? threshold_and_mask_self_smp_only; /** IOOLFIR[51] * osc switch */ - (rIOOLFIR, bit(51)) ? threshold_and_mask_self; + (rIOOLFIR, bit(51)) ? threshold_and_mask_self_smp_only; /** IOOLFIR[52] * link0 correctable array error */ - (rIOOLFIR, bit(52)) ? obusSmpCallout_th32_L0; + (rIOOLFIR, bit(52)) ? self_th_32perDay; /** IOOLFIR[53] * link1 correctable array error */ - (rIOOLFIR, bit(53)) ? obusSmpCallout_th32_L1; + (rIOOLFIR, bit(53)) ? self_th_32perDay; /** IOOLFIR[54] * link0 uncorrectable array error */ - (rIOOLFIR, bit(54)) ? obusSmpFailure_L0; + (rIOOLFIR, bit(54)) ? self_th_1; /** IOOLFIR[55] * link1 uncorrectable array error */ - (rIOOLFIR, bit(55)) ? obusSmpFailure_L1; + (rIOOLFIR, bit(55)) ? self_th_1; /** IOOLFIR[56] * link0 training failed */ - (rIOOLFIR, bit(56)) ? obusSmpFailure_L0; + (rIOOLFIR, bit(56)) ? training_failure_L0; /** IOOLFIR[57] * link1 training failed */ - (rIOOLFIR, bit(57)) ? obusSmpFailure_L1; + (rIOOLFIR, bit(57)) ? training_failure_L1; /** IOOLFIR[58] * link0 unrecoverable error */ - (rIOOLFIR, bit(58)) ? obusSmpFailure_L0; + (rIOOLFIR, bit(58)) ? unrecoverable_error_L0; /** IOOLFIR[59] * link1 unrecoverable error */ - (rIOOLFIR, bit(59)) ? obusSmpFailure_L1; + (rIOOLFIR, bit(59)) ? unrecoverable_error_L1; /** IOOLFIR[60] * link0 internal error */ - (rIOOLFIR, bit(60)) ? obusSmpFailure_L0; + (rIOOLFIR, bit(60)) ? internal_error_L0; /** IOOLFIR[61] * link1 internal error */ - (rIOOLFIR, bit(61)) ? obusSmpFailure_L1; + (rIOOLFIR, bit(61)) ? internal_error_L1; /** IOOLFIR[62] * fir scom err dup diff --git a/src/usr/diag/prdf/common/plat/axone/axone_omic.rule b/src/usr/diag/prdf/common/plat/axone/axone_omic.rule index 09ed59f2d..7b26f7a3a 100644 --- a/src/usr/diag/prdf/common/plat/axone/axone_omic.rule +++ b/src/usr/diag/prdf/common/plat/axone/axone_omic.rule @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2018 +# Contributors Listed Below - COPYRIGHT 2018,2020 # [+] International Business Machines Corp. # # @@ -196,8 +196,10 @@ rule rOMIC }; group gOMIC attntype CHECK_STOP, RECOVERABLE, UNIT_CS, HOST_ATTN - filter singlebit + filter priority(2,0,1) { + # We need to prioritize analysis to the OMIDLFIR here because of potential + # Channel Fail attentions in that FIR that will be reported as RECOVERABLE. (rOMIC, bit(0)) ? analyzeIOOMIFIR; (rOMIC, bit(1)) ? analyzeMCPPEFIR; (rOMIC, bit(2)) ? analyzeOMIDLFIR; @@ -226,17 +228,17 @@ group gIOOMIFIR /** IOOMIFIR[0] * RX invalid state or parity error */ - (rIOOMIFIR, bit(0)) ? defaultMaskedError; + (rIOOMIFIR, bit(0)) ? self_th_1; /** IOOMIFIR[1] * TX invalid state or parity error */ - (rIOOMIFIR, bit(1)) ? defaultMaskedError; + (rIOOMIFIR, bit(1)) ? self_th_1; /** IOOMIFIR[2] * GCR hang error */ - (rIOOMIFIR, bit(2)) ? defaultMaskedError; + (rIOOMIFIR, bit(2)) ? self_th_1; /** IOOMIFIR[3:47] * Unused @@ -359,306 +361,306 @@ rule rOMIDLFIR }; group gOMIDLFIR - filter singlebit, - cs_root_cause + filter priority(0,20,40), + cs_root_cause(0,20,40) { /** OMIDLFIR[0] - * DL0 fatal error + * OMI-DL0 fatal error */ - (rOMIDLFIR, bit(0)) ? defaultMaskedError; + (rOMIDLFIR, bit(0)) ? dl0_fatal_error; /** OMIDLFIR[1] - * DL0 data UE + * OMI-DL0 UE on data flit */ - (rOMIDLFIR, bit(1)) ? defaultMaskedError; + (rOMIDLFIR, bit(1)) ? dl0_omi_th_1; /** OMIDLFIR[2] - * DL0 flit CE + * OMI-DL0 CE on TL flit */ - (rOMIDLFIR, bit(2)) ? defaultMaskedError; + (rOMIDLFIR, bit(2)) ? dl0_omi_th_32perDay; /** OMIDLFIR[3] - * DL0 CRC error + * OMI-DL0 detected a CRC error */ (rOMIDLFIR, bit(3)) ? defaultMaskedError; /** OMIDLFIR[4] - * DL0 nack + * OMI-DL0 received a nack */ (rOMIDLFIR, bit(4)) ? defaultMaskedError; /** OMIDLFIR[5] - * DL0 X4 mode + * OMI-DL0 running in degraded mode */ - (rOMIDLFIR, bit(5)) ? defaultMaskedError; + (rOMIDLFIR, bit(5)) ? dl0_omi_bus_th_1; /** OMIDLFIR[6] - * DL0 EDPL + * OMI-DL0 parity error detection on a lane */ (rOMIDLFIR, bit(6)) ? defaultMaskedError; /** OMIDLFIR[7] - * DL0 timeout + * OMI-DL0 retrained due to no forward progress */ - (rOMIDLFIR, bit(7)) ? defaultMaskedError; + (rOMIDLFIR, bit(7)) ? dl0_omi_bus_th_32perDay; /** OMIDLFIR[8] - * DL0 remote retrain + * OMI-DL0 remote side initiated a retrain */ (rOMIDLFIR, bit(8)) ? defaultMaskedError; /** OMIDLFIR[9] - * DL0 error retrain + * OMI-DL0 retrain due to internal error or software initiated */ - (rOMIDLFIR, bit(9)) ? defaultMaskedError; + (rOMIDLFIR, bit(9)) ? dl0_omi_bus_th_32perDay; /** OMIDLFIR[10] - * DL0 EDPL retrain + * OMI-DL0 threshold reached */ - (rOMIDLFIR, bit(10)) ? defaultMaskedError; + (rOMIDLFIR, bit(10)) ? dl0_omi_bus_th_32perDay; /** OMIDLFIR[11] - * DL0 trained + * OMI-DL0 trained */ (rOMIDLFIR, bit(11)) ? defaultMaskedError; /** OMIDLFIR[12] - * DL0 endpoint bit 0 + * OMI-DL0 endpoint error bit 0 */ (rOMIDLFIR, bit(12)) ? defaultMaskedError; /** OMIDLFIR[13] - * DL0 endpoint bit 1 + * OMI-DL0 endpoint error bit 1 */ (rOMIDLFIR, bit(13)) ? defaultMaskedError; /** OMIDLFIR[14] - * DL0 endpoint bit 2 + * OMI-DL0 endpoint error bit 2 */ (rOMIDLFIR, bit(14)) ? defaultMaskedError; /** OMIDLFIR[15] - * DL0 endpoint bit 3 + * OMI-DL0 endpoint error bit 3 */ (rOMIDLFIR, bit(15)) ? defaultMaskedError; /** OMIDLFIR[16] - * DL0 endpoint bit 4 + * OMI-DL0 endpoint error bit 4 */ (rOMIDLFIR, bit(16)) ? defaultMaskedError; /** OMIDLFIR[17] - * DL0 endpoint bit 5 + * OMI-DL0 endpoint error bit 5 */ (rOMIDLFIR, bit(17)) ? defaultMaskedError; /** OMIDLFIR[18] - * DL0 endpoint bit 6 + * OMI-DL0 endpoint error bit 6 */ (rOMIDLFIR, bit(18)) ? defaultMaskedError; /** OMIDLFIR[19] - * DL0 endpoint bit 7 + * OMI-DL0 endpoint error bit 7 */ (rOMIDLFIR, bit(19)) ? defaultMaskedError; /** OMIDLFIR[20] - * DL1 fatal error + * OMI-DL1 fatal error */ - (rOMIDLFIR, bit(20)) ? defaultMaskedError; + (rOMIDLFIR, bit(20)) ? dl1_fatal_error; /** OMIDLFIR[21] - * DL1 data UE + * OMI-DL1 UE on data flit */ - (rOMIDLFIR, bit(21)) ? defaultMaskedError; + (rOMIDLFIR, bit(21)) ? dl1_omi_th_1; /** OMIDLFIR[22] - * DL1 flit CE + * OMI-DL1 CE on TL flit */ - (rOMIDLFIR, bit(22)) ? defaultMaskedError; + (rOMIDLFIR, bit(22)) ? dl1_omi_th_32perDay; /** OMIDLFIR[23] - * DL1 CRC error + * OMI-DL1 detected a CRC error */ (rOMIDLFIR, bit(23)) ? defaultMaskedError; /** OMIDLFIR[24] - * DL1 nack + * OMI-DL1 received a nack */ (rOMIDLFIR, bit(24)) ? defaultMaskedError; /** OMIDLFIR[25] - * DL1 X4 mode + * OMI-DL1 running in degraded mode */ - (rOMIDLFIR, bit(25)) ? defaultMaskedError; + (rOMIDLFIR, bit(25)) ? dl1_omi_bus_th_1; /** OMIDLFIR[26] - * DL1 EDPL + * OMI-DL1 parity error detection on a lane */ (rOMIDLFIR, bit(26)) ? defaultMaskedError; /** OMIDLFIR[27] - * DL1 timeout + * OMI-DL1 retrained due to no forward progress */ - (rOMIDLFIR, bit(27)) ? defaultMaskedError; + (rOMIDLFIR, bit(27)) ? dl1_omi_bus_th_32perDay; /** OMIDLFIR[28] - * DL1 remote retrain + * OMI-DL1 remote side initiated a retrain */ (rOMIDLFIR, bit(28)) ? defaultMaskedError; /** OMIDLFIR[29] - * DL1 error retrain + * OMI-DL1 retrain due to internal error or software initiated */ - (rOMIDLFIR, bit(29)) ? defaultMaskedError; + (rOMIDLFIR, bit(29)) ? dl1_omi_bus_th_32perDay; /** OMIDLFIR[30] - * DL1 EDPL retrain + * OMI-DL1 threshold reached */ - (rOMIDLFIR, bit(30)) ? defaultMaskedError; + (rOMIDLFIR, bit(30)) ? dl1_omi_bus_th_32perDay; /** OMIDLFIR[31] - * DL1 trained + * OMI-DL1 trained */ (rOMIDLFIR, bit(31)) ? defaultMaskedError; /** OMIDLFIR[32] - * DL1 endpoint bit 0 + * OMI-DL1 endpoint error bit 0 */ (rOMIDLFIR, bit(32)) ? defaultMaskedError; /** OMIDLFIR[33] - * DL1 endpoint bit 1 + * OMI-DL1 endpoint error bit 1 */ (rOMIDLFIR, bit(33)) ? defaultMaskedError; /** OMIDLFIR[34] - * DL1 endpoint bit 2 + * OMI-DL1 endpoint error bit 2 */ (rOMIDLFIR, bit(34)) ? defaultMaskedError; /** OMIDLFIR[35] - * DL1 endpoint bit 3 + * OMI-DL1 endpoint error bit 3 */ (rOMIDLFIR, bit(35)) ? defaultMaskedError; /** OMIDLFIR[36] - * DL1 endpoint bit 4 + * OMI-DL1 endpoint error bit 4 */ (rOMIDLFIR, bit(36)) ? defaultMaskedError; /** OMIDLFIR[37] - * DL1 endpoint bit 5 + * OMI-DL1 endpoint error bit 5 */ (rOMIDLFIR, bit(37)) ? defaultMaskedError; /** OMIDLFIR[38] - * DL1 endpoint bit 6 + * OMI-DL1 endpoint error bit 6 */ (rOMIDLFIR, bit(38)) ? defaultMaskedError; /** OMIDLFIR[39] - * DL1 endpoint bit 7 + * OMI-DL1 endpoint error bit 7 */ (rOMIDLFIR, bit(39)) ? defaultMaskedError; /** OMIDLFIR[40] - * DL2 fatal error + * OMI-DL2 fatal error */ - (rOMIDLFIR, bit(40)) ? defaultMaskedError; + (rOMIDLFIR, bit(40)) ? dl2_fatal_error; /** OMIDLFIR[41] - * DL2 data UE + * OMI-DL2 UE on data flit */ - (rOMIDLFIR, bit(41)) ? defaultMaskedError; + (rOMIDLFIR, bit(41)) ? dl2_omi_th_1; /** OMIDLFIR[42] - * DL2 flit CE + * OMI-DL2 CE on TL flit */ - (rOMIDLFIR, bit(42)) ? defaultMaskedError; + (rOMIDLFIR, bit(42)) ? dl2_omi_th_32perDay; /** OMIDLFIR[43] - * DL2 CRC error + * OMI-DL2 detected a CRC error */ (rOMIDLFIR, bit(43)) ? defaultMaskedError; /** OMIDLFIR[44] - * DL2 nack + * OMI-DL2 received a nack */ (rOMIDLFIR, bit(44)) ? defaultMaskedError; /** OMIDLFIR[45] - * DL2 X4 mode + * OMI-DL2 running in degraded mode */ - (rOMIDLFIR, bit(45)) ? defaultMaskedError; + (rOMIDLFIR, bit(45)) ? dl2_omi_bus_th_1; /** OMIDLFIR[46] - * DL2 EDPL + * OMI-DL2 parity error detection on a lane */ (rOMIDLFIR, bit(46)) ? defaultMaskedError; /** OMIDLFIR[47] - * DL2 timeout + * OMI-DL2 retrained due to no forward progress */ - (rOMIDLFIR, bit(47)) ? defaultMaskedError; + (rOMIDLFIR, bit(47)) ? dl2_omi_bus_th_32perDay; /** OMIDLFIR[48] - * DL2 remote retrain + * OMI-DL2 remote side initiated a retrain */ (rOMIDLFIR, bit(48)) ? defaultMaskedError; /** OMIDLFIR[49] - * DL2 error retrain + * OMI-DL2 retrain due to internal error or software initiated */ - (rOMIDLFIR, bit(49)) ? defaultMaskedError; + (rOMIDLFIR, bit(49)) ? dl2_omi_bus_th_32perDay; /** OMIDLFIR[50] - * DL2 EDPL retrain + * OMI-DL2 threshold reached */ - (rOMIDLFIR, bit(50)) ? defaultMaskedError; + (rOMIDLFIR, bit(50)) ? dl2_omi_bus_th_32perDay; /** OMIDLFIR[51] - * DL2 trained + * OMI-DL2 trained */ (rOMIDLFIR, bit(51)) ? defaultMaskedError; /** OMIDLFIR[52] - * DL2 endpoint bit 0 + * OMI-DL2 endpoint error bit 0 */ (rOMIDLFIR, bit(52)) ? defaultMaskedError; /** OMIDLFIR[53] - * DL2 endpoint bit 1 + * OMI-DL2 endpoint error bit 1 */ (rOMIDLFIR, bit(53)) ? defaultMaskedError; /** OMIDLFIR[54] - * DL2 endpoint bit 2 + * OMI-DL2 endpoint error bit 2 */ (rOMIDLFIR, bit(54)) ? defaultMaskedError; /** OMIDLFIR[55] - * DL2 endpoint bit 3 + * OMI-DL2 endpoint error bit 3 */ (rOMIDLFIR, bit(55)) ? defaultMaskedError; /** OMIDLFIR[56] - * DL2 endpoint bit 4 + * OMI-DL2 endpoint error bit 4 */ (rOMIDLFIR, bit(56)) ? defaultMaskedError; /** OMIDLFIR[57] - * DL2 endpoint bit 5 + * OMI-DL2 endpoint error bit 5 */ (rOMIDLFIR, bit(57)) ? defaultMaskedError; /** OMIDLFIR[58] - * DL2 endpoint bit 6 + * OMI-DL2 endpoint error bit 6 */ (rOMIDLFIR, bit(58)) ? defaultMaskedError; /** OMIDLFIR[59] - * DL2 endpoint bit 7 + * OMI-DL2 endpoint error bit 7 */ (rOMIDLFIR, bit(59)) ? defaultMaskedError; @@ -667,6 +669,21 @@ group gOMIDLFIR */ (rOMIDLFIR, bit(60)) ? defaultMaskedError; + /** OMIDLFIR[61] + * reserved + */ + (rOMIDLFIR, bit(61)) ? defaultMaskedError; + + /** OMIDLFIR[62] + * LFIR internal parity error + */ + (rOMIDLFIR, bit(62)) ? defaultMaskedError; + + /** OMIDLFIR[63] + * SCOM Satellite Error + */ + (rOMIDLFIR, bit(63)) ? defaultMaskedError; + }; ############################################################################## diff --git a/src/usr/diag/prdf/common/plat/axone/axone_omic_actions.rule b/src/usr/diag/prdf/common/plat/axone/axone_omic_actions.rule index ecb6626a8..dbf563b47 100644 --- a/src/usr/diag/prdf/common/plat/axone/axone_omic_actions.rule +++ b/src/usr/diag/prdf/common/plat/axone/axone_omic_actions.rule @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2018 +# Contributors Listed Below - COPYRIGHT 2018,2019 # [+] International Business Machines Corp. # # @@ -24,6 +24,133 @@ # IBM_PROLOG_END_TAG ################################################################################ +# OMIC Actions # +################################################################################ + +actionclass dl0_omi +{ + callout(connected(TYPE_OMI,0), MRU_MED); +}; + +actionclass dl1_omi +{ + callout(connected(TYPE_OMI,1), MRU_MED); +}; + +actionclass dl2_omi +{ + callout(connected(TYPE_OMI,2), MRU_MED); +}; + +actionclass dl0_omi_bus +{ + funccall("omiParentCalloutBusInterfacePlugin_0"); +}; + +actionclass dl1_omi_bus +{ + funccall("omiParentCalloutBusInterfacePlugin_1"); +}; + +actionclass dl2_omi_bus +{ + funccall("omiParentCalloutBusInterfacePlugin_2"); +}; + +/** OMI-DL0 Fatal Error */ +actionclass dl0_fatal_error +{ + try( funccall("DlFatalError_0"), dl0_omi_bus ); + threshold1; +}; + +/** OMI-DL1 Fatal Error */ +actionclass dl1_fatal_error +{ + try( funccall("DlFatalError_1"), dl1_omi_bus ); + threshold1; +}; + +/** OMI-DL2 Fatal Error */ +actionclass dl2_fatal_error +{ + try( funccall("DlFatalError_2"), dl2_omi_bus ); + threshold1; +}; + +actionclass dl0_omi_th_1 +{ + dl0_omi; + threshold1; +}; + +actionclass dl1_omi_th_1 +{ + dl1_omi; + threshold1; +}; + +actionclass dl2_omi_th_1 +{ + dl2_omi; + threshold1; +}; + +actionclass dl0_omi_th_32perDay +{ + dl0_omi; + threshold32pday; +}; + +actionclass dl1_omi_th_32perDay +{ + dl1_omi; + threshold32pday; +}; + +actionclass dl2_omi_th_32perDay +{ + dl2_omi; + threshold32pday; +}; + +actionclass dl0_omi_bus_th_1 +{ + dl0_omi_bus; + threshold1; +}; + +actionclass dl1_omi_bus_th_1 +{ + dl1_omi_bus; + threshold1; +}; + +actionclass dl2_omi_bus_th_1 +{ + dl2_omi_bus; + threshold1; +}; + +actionclass dl0_omi_bus_th_32perDay +{ + dl0_omi_bus; + threshold1; +}; + +actionclass dl1_omi_bus_th_32perDay +{ + dl1_omi_bus; + threshold1; +}; + +actionclass dl2_omi_bus_th_32perDay +{ + dl2_omi_bus; + threshold1; +}; + +################################################################################ # Analyze groups ################################################################################ diff --git a/src/usr/diag/prdf/common/plat/axone/axone_omic_regs.rule b/src/usr/diag/prdf/common/plat/axone/axone_omic_regs.rule new file mode 100644 index 000000000..e698652a6 --- /dev/null +++ b/src/usr/diag/prdf/common/plat/axone/axone_omic_regs.rule @@ -0,0 +1,62 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/axone/axone_omic_regs.rule $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2019 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +############################################################################### +# Additional registers for omic, not defined in XML +############################################################################### + + + ########################################################################### + # P9 Axone target OMIDLFIR + ########################################################################### + + register OMIDLFIR_MASK_OR + { + name "P9 OMIC target OMIDLFIR MASK atomic OR"; + scomaddr 0x07013345; + capture group never; + access write_only; + }; + + register DL0_ERROR_HOLD + { + name "P9 Axone target DL0 Error Hold Register"; + scomaddr 0x07013353; + capture group default; + }; + + register DL1_ERROR_HOLD + { + name "P9 Axone target DL1 Error Hold Register"; + scomaddr 0x07013363; + capture group default; + }; + + register DL2_ERROR_HOLD + { + name "P9 Axone target DL2 Error Hold Register"; + scomaddr 0x07013373; + capture group default; + }; diff --git a/src/usr/diag/prdf/common/plat/axone/axone_phb.rule b/src/usr/diag/prdf/common/plat/axone/axone_phb.rule index 844739ee2..1c5bb566d 100644 --- a/src/usr/diag/prdf/common/plat/axone/axone_phb.rule +++ b/src/usr/diag/prdf/common/plat/axone/axone_phb.rule @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2018 +# Contributors Listed Below - COPYRIGHT 2018,2019 # [+] International Business Machines Corp. # # @@ -212,7 +212,7 @@ group gPHBNFIR /** PHBNFIR[0] * BAR Parity Error */ - (rPHBNFIR, bit(0)) ? self_th_1; + (rPHBNFIR, bit(0)) ? parent_proc_th_1; /** PHBNFIR[1] * Parity Errors on Registers besides BAR @@ -252,12 +252,12 @@ group gPHBNFIR /** PHBNFIR[8] * Register Array Parity Error */ - (rPHBNFIR, bit(8)) ? self_th_1; + (rPHBNFIR, bit(8)) ? parent_proc_th_1; /** PHBNFIR[9] * Power Bus Interface Parity Error */ - (rPHBNFIR, bit(9)) ? self_th_1; + (rPHBNFIR, bit(9)) ? parent_proc_th_1; /** PHBNFIR[10] * Power Bus Data Hang @@ -297,7 +297,7 @@ group gPHBNFIR /** PHBNFIR[17] * Hardware Error */ - (rPHBNFIR, bit(17)) ? self_th_1; + (rPHBNFIR, bit(17)) ? parent_proc_th_1; /** PHBNFIR[18] * Unsolicited Power Bus Data diff --git a/src/usr/diag/prdf/common/plat/axone/axone_proc.rule b/src/usr/diag/prdf/common/plat/axone/axone_proc.rule index c37c103be..b936106e2 100644 --- a/src/usr/diag/prdf/common/plat/axone/axone_proc.rule +++ b/src/usr/diag/prdf/common/plat/axone/axone_proc.rule @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2018 +# Contributors Listed Below - COPYRIGHT 2018,2019 # [+] International Business Machines Corp. # # @@ -950,42 +950,6 @@ chip axone_proc }; ############################################################################ - # P9 chip ENHCAFIR - ############################################################################ - - register ENHCAFIR - { - name "P9 chip ENHCAFIR"; - scomaddr 0x05012940; - reset (&, 0x05012941); - mask (|, 0x05012945); - capture group default; - }; - - register ENHCAFIR_MASK - { - name "P9 chip ENHCAFIR MASK"; - scomaddr 0x05012943; - capture group default; - }; - - register ENHCAFIR_ACT0 - { - name "P9 chip ENHCAFIR ACT0"; - scomaddr 0x05012946; - capture group default; - capture req nonzero("ENHCAFIR"); - }; - - register ENHCAFIR_ACT1 - { - name "P9 chip ENHCAFIR ACT1"; - scomaddr 0x05012947; - capture group default; - capture req nonzero("ENHCAFIR"); - }; - - ############################################################################ # P9 chip PBAMFIR ############################################################################ @@ -2758,7 +2722,7 @@ group gNXCQFIR /** NXCQFIR[19] * Uncorrectable error on ERAT arrays */ - (rNXCQFIR, bit(19)) ? nx_th_32perDay; + (rNXCQFIR, bit(19)) ? nx_th_1; /** NXCQFIR[20] * SUE on ERAT arrays @@ -4077,14 +4041,14 @@ group gN3_CHIPLET_FIR (rN3_CHIPLET_FIR, bit(14)) ? analyzePBPPEFIR; /** N3_CHIPLET_FIR[15] - * Attention from PBIOEFIR + * Attention from PBIOOFIR */ - (rN3_CHIPLET_FIR, bit(15)) ? analyzePBIOEFIR; + (rN3_CHIPLET_FIR, bit(15)) ? analyzePBIOOFIR; /** N3_CHIPLET_FIR[16] - * Attention from PBIOOFIR + * Attention from NPU0FIR 1 */ - (rN3_CHIPLET_FIR, bit(16)) ? analyzePBIOOFIR; + (rN3_CHIPLET_FIR, bit(16)) ? analyzeConnectedNPU1; /** N3_CHIPLET_FIR[17] * Attention from INTCQFIR @@ -4106,15 +4070,10 @@ group gN3_CHIPLET_FIR */ (rN3_CHIPLET_FIR, bit(20)) ? analyzePBAMFIR; - /** N3_CHIPLET_FIR[21] - * Attention from NPU0FIR 1 - */ - (rN3_CHIPLET_FIR, bit(21)) ? analyzeConnectedNPU1; - /** N3_CHIPLET_FIR[22] - * Attention from ENHCAFIR + * Attention from PBIOEFIR */ - (rN3_CHIPLET_FIR, bit(22)) ? analyzeENHCAFIR; + (rN3_CHIPLET_FIR, bit(22)) ? analyzePBIOEFIR; /** N3_CHIPLET_FIR[23] * Attention from NPU2FIR 0 @@ -5145,144 +5104,6 @@ group gPSIHBFIR }; ################################################################################ -# P9 chip ENHCAFIR -################################################################################ - -rule rENHCAFIR -{ - CHECK_STOP: - ENHCAFIR & ~ENHCAFIR_MASK & ~ENHCAFIR_ACT0 & ~ENHCAFIR_ACT1; - RECOVERABLE: - ENHCAFIR & ~ENHCAFIR_MASK & ~ENHCAFIR_ACT0 & ENHCAFIR_ACT1; -}; - -group gENHCAFIR - filter singlebit, - cs_root_cause -{ - /** ENHCAFIR[0] - * PB0 data UE - */ - (rENHCAFIR, bit(0)) ? defaultMaskedError; - - /** ENHCAFIR[1] - * PB0 data SUE - */ - (rENHCAFIR, bit(1)) ? defaultMaskedError; - - /** ENHCAFIR[2] - * PB0 data ue - */ - (rENHCAFIR, bit(2)) ? defaultMaskedError; - - /** ENHCAFIR[3] - * spare - */ - (rENHCAFIR, bit(3)) ? defaultMaskedError; - - /** ENHCAFIR[4] - * Castout Drop Counter Full - */ - (rENHCAFIR, bit(4)) ? defaultMaskedError; - - /** ENHCAFIR[5] - * Data Hang Detect - */ - (rENHCAFIR, bit(5)) ? defaultMaskedError; - - /** ENHCAFIR[6] - * Unexpected data or cresp - */ - (rENHCAFIR, bit(6)) ? defaultMaskedError; - - /** ENHCAFIR[7] - * Internal Error - */ - (rENHCAFIR, bit(7)) ? defaultMaskedError; - - /** ENHCAFIR[8] - * ADU checkstop error from power bus data - */ - (rENHCAFIR, bit(8)) ? defaultMaskedError; - - /** ENHCAFIR[9] - * ADU checkstop error from alter display - */ - (rENHCAFIR, bit(9)) ? defaultMaskedError; - - /** ENHCAFIR[10] - * ADU checkstop error from xsco m - */ - (rENHCAFIR, bit(10)) ? defaultMaskedError; - - /** ENHCAFIR[11] - * ADU checkstop from power bus cmd - */ - (rENHCAFIR, bit(11)) ? defaultMaskedError; - - /** ENHCAFIR[12] - * ADU checkstop error from power bus send - */ - (rENHCAFIR, bit(12)) ? defaultMaskedError; - - /** ENHCAFIR[13] - * ADU checkstop from power bus receive - */ - (rENHCAFIR, bit(13)) ? defaultMaskedError; - - /** ENHCAFIR[14] - * ADU recoverable error from pb data - */ - (rENHCAFIR, bit(14)) ? defaultMaskedError; - - /** ENHCAFIR[15] - * ADU recoverable error from alter display - */ - (rENHCAFIR, bit(15)) ? defaultMaskedError; - - /** ENHCAFIR[16] - * ADU recoverable error from xscom - */ - (rENHCAFIR, bit(16)) ? defaultMaskedError; - - /** ENHCAFIR[17] - * ADU recoverable from power bus cmd - */ - (rENHCAFIR, bit(17)) ? defaultMaskedError; - - /** ENHCAFIR[18] - * ADU recoverable error from pb send - */ - (rENHCAFIR, bit(18)) ? defaultMaskedError; - - /** ENHCAFIR[19] - * ADU recoverable error from pb receive - */ - (rENHCAFIR, bit(19)) ? defaultMaskedError; - - /** ENHCAFIR[20] - * NHTM scom error - */ - (rENHCAFIR, bit(20)) ? defaultMaskedError; - - /** ENHCAFIR[21] - * spare - */ - (rENHCAFIR, bit(21)) ? defaultMaskedError; - - /** ENHCAFIR[22] - * scom error - */ - (rENHCAFIR, bit(22)) ? defaultMaskedError; - - /** ENHCAFIR[23] - * scom error - */ - (rENHCAFIR, bit(23)) ? defaultMaskedError; - -}; - -################################################################################ # P9 chip PBAMFIR ################################################################################ diff --git a/src/usr/diag/prdf/common/plat/axone/prdfMccPlugins.C b/src/usr/diag/prdf/common/plat/axone/prdfMccPlugins.C new file mode 100644 index 000000000..804418717 --- /dev/null +++ b/src/usr/diag/prdf/common/plat/axone/prdfMccPlugins.C @@ -0,0 +1,142 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/diag/prdf/common/plat/axone/prdfMccPlugins.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +// Framework includes +#include <iipServiceDataCollector.h> +#include <prdfExtensibleChip.H> +#include <prdfPluginMap.H> + +// Platform includes +#include <prdfMemUtils.H> +#include <prdfPlatServices.H> +#include <prdfMemExtraSig.H> + +using namespace TARGETING; + +namespace PRDF +{ + +using namespace PlatServices; + +namespace axone_mcc +{ + +//############################################################################## +// +// Special plugins +// +//############################################################################## + +/** + * @brief Analysis code that is called before the main analyze() function. + * @param i_chip A MCC chip. + * @param io_sc The step code data struct. + * @param o_analyzed True if analysis is done on this chip, false otherwise. + * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. + */ +int32_t PreAnalysis( ExtensibleChip * i_chip, STEP_CODE_DATA_STRUCT & io_sc, + bool & o_analyzed ) +{ + // Check for a channel failure before analyzing this chip. + o_analyzed = MemUtils::analyzeChnlFail<TYPE_MCC>( i_chip, io_sc ); + + return SUCCESS; +} +PRDF_PLUGIN_DEFINE( axone_mcc, PreAnalysis ); + +/** + * @brief Plugin function called after analysis is complete but before PRD + * exits. + * @param i_chip A MCC chip. + * @param io_sc The step code data struct. + * @note This is especially useful for any analysis that still needs to be + * done after the framework clears the FIR bits that were at attention. + * @return SUCCESS. + */ +int32_t PostAnalysis( ExtensibleChip * i_chip, STEP_CODE_DATA_STRUCT & io_sc ) +{ + // If there was a channel failure some cleanup is required to ensure + // there are no more attentions from this channel. + MemUtils::cleanupChnlFail<TYPE_MCC>( i_chip, io_sc ); + + return SUCCESS; +} +PRDF_PLUGIN_DEFINE( axone_mcc, PostAnalysis ); + +//############################################################################## +// +// DSTLFIR +// +//############################################################################## + +/** + * @brief Plugin function called to avoid analyzing to a checkstop on an OCMB. + * @param i_chip A MCC chip. + * @param io_sc The step code data struct. + * @param i_pos Position of the OMI/OCMB relative to the MCC. + * @return SUCCESS if the primary attn is CS, else PRD_SCAN_COMM_REGISTER_ZERO. + */ +int32_t checkOcmb( ExtensibleChip * i_chip, STEP_CODE_DATA_STRUCT & io_sc, + uint8_t i_pos ) +{ + int32_t rc = PRD_SCAN_COMM_REGISTER_ZERO; + + #ifdef CONFIG_ENABLE_CHECKSTOP_ANALYSIS + // We do not have support for the OCMB in the checkstop analysis path. + // As such, we will simply indicate there is an attention from the OCMB and + // add second level support and both sides of the bus as callouts. + if ( CHECK_STOP == io_sc.service_data->getPrimaryAttnType() ) + { + TargetHandle_t omi = getConnectedChild( i_chip->getTrgt(), TYPE_OMI, + i_pos ); + ExtensibleChip * ocmb = getConnectedChild( i_chip, TYPE_OCMB_CHIP, + i_pos ); + + io_sc.service_data->SetCallout( LEVEL2_SUPPORT, MRU_MED, NO_GARD ); + io_sc.service_data->SetCallout( omi, MRU_LOW, NO_GARD ); + io_sc.service_data->SetCallout( ocmb->getTrgt(), MRU_LOW, NO_GARD ); + + rc = SUCCESS; + } + #endif + + return rc; +} + +#define CHECK_OCMB_PLUGIN( POS ) \ +int32_t checkOcmb_##POS( ExtensibleChip * i_chip, \ + STEP_CODE_DATA_STRUCT & io_sc ) \ +{ \ + return checkOcmb( i_chip, io_sc, POS ); \ +} \ +PRDF_PLUGIN_DEFINE( axone_mcc, checkOcmb_##POS ); + +CHECK_OCMB_PLUGIN( 0 ); +CHECK_OCMB_PLUGIN( 1 ); + +} // end namespace axone_mcc + +} // end namespace PRDF + diff --git a/src/usr/diag/prdf/common/plat/axone/prdfOmicPlugins.C b/src/usr/diag/prdf/common/plat/axone/prdfOmicPlugins.C new file mode 100644 index 000000000..f6ea182b9 --- /dev/null +++ b/src/usr/diag/prdf/common/plat/axone/prdfOmicPlugins.C @@ -0,0 +1,173 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/diag/prdf/common/plat/axone/prdfOmicPlugins.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +// Framework includes +#include <iipServiceDataCollector.h> +#include <prdfExtensibleChip.H> +#include <prdfPluginMap.H> + +// Platform includes +#include <prdfMemUtils.H> +#include <prdfPlatServices.H> + +using namespace TARGETING; + +namespace PRDF +{ + +using namespace PlatServices; + +namespace axone_omic +{ + +//############################################################################## +// +// Special plugins +// +//############################################################################## + +/** + * @brief Analysis code that is called before the main analyze() function. + * @param i_chip An OMIC chip. + * @param io_sc The step code data struct. + * @param o_analyzed True if analysis is done on this chip, false otherwise. + * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. + */ +int32_t PreAnalysis( ExtensibleChip * i_chip, STEP_CODE_DATA_STRUCT & io_sc, + bool & o_analyzed ) +{ + // Check for a channel failure before analyzing this chip. + o_analyzed = MemUtils::analyzeChnlFail<TYPE_OMIC>( i_chip, io_sc ); + + return SUCCESS; +} +PRDF_PLUGIN_DEFINE( axone_omic, PreAnalysis ); + +/** + * @brief Plugin function called after analysis is complete but before PRD + * exits. + * @param i_chip An OMIC chip. + * @param io_sc The step code data struct. + * @note This is especially useful for any analysis that still needs to be + * done after the framework clears the FIR bits that were at attention. + * @return SUCCESS. + */ +int32_t PostAnalysis( ExtensibleChip * i_chip, STEP_CODE_DATA_STRUCT & io_sc ) +{ + // If there was a channel failure some cleanup is required to ensure + // there are no more attentions from this channel. + MemUtils::cleanupChnlFail<TYPE_OMIC>( i_chip, io_sc ); + + return SUCCESS; +} +PRDF_PLUGIN_DEFINE( axone_omic, PostAnalysis ); + +//############################################################################## +// +// OMIDLFIR +// +//############################################################################## + +/** + * @brief OMIDLFIR[0|20|40] - OMI-DL Fatal Error + * @param i_chip An OMIC chip. + * @param io_sc The step code data struct. + * @param i_dl The DL relative to the OMIC. + * @return PRD_SCAN_COMM_REGISTER_ZERO for the bus callout, else SUCCESS + */ +int32_t DlFatalError( ExtensibleChip * i_chip, STEP_CODE_DATA_STRUCT & io_sc, + uint8_t i_dl ) +{ + #define PRDF_FUNC "[axone_omic::DlFatalError] " + + int32_t rc = SUCCESS; + + do + { + // Note: The OMIDLFIR can't actually be set up to report UNIT_CS + // attentions, instead, as a workaround, the relevant channel fail + // bits will be set as recoverable bits and we will manually set + // the attention types to UNIT_CS in our handling of these errors. + io_sc.service_data->setPrimaryAttnType( UNIT_CS ); + + char reg[64]; + sprintf( reg, "DL%d_ERROR_HOLD", i_dl ); + + // Check DL#_ERROR_HOLD[52:63] to determine callout + SCAN_COMM_REGISTER_CLASS * dl_error_hold = i_chip->getRegister( reg ); + + if ( SUCCESS != dl_error_hold->Read() ) + { + PRDF_ERR( PRDF_FUNC "Read() Failed on DL%d_ERROR_HOLD: " + "i_chip=0x%08x", i_dl, i_chip->getHuid() ); + break; + } + + if ( dl_error_hold->IsBitSet(53) || + dl_error_hold->IsBitSet(55) || + dl_error_hold->IsBitSet(57) || + dl_error_hold->IsBitSet(58) || + dl_error_hold->IsBitSet(59) || + dl_error_hold->IsBitSet(60) || + dl_error_hold->IsBitSet(62) || + dl_error_hold->IsBitSet(63) ) + { + // Get and callout the OMI target + TargetHandle_t omi = getConnectedChild( i_chip->getTrgt(), TYPE_OMI, + i_dl ); + io_sc.service_data->SetCallout( omi ); + } + else if ( dl_error_hold->IsBitSet(54) || + dl_error_hold->IsBitSet(56) || + dl_error_hold->IsBitSet(61) ) + { + // callout the OMI target, the OMI bus, and the OCMB + // Return PRD_SCAN_COMM_REGISTER_ZERO so the rule code makes + // the appropriate callout. + rc = PRD_SCAN_COMM_REGISTER_ZERO; + } + + }while(0); + + return rc; + + #undef PRDF_FUNC +} + +#define DL_FATAL_ERROR_PLUGIN( POS ) \ +int32_t DlFatalError_##POS( ExtensibleChip * i_chip, \ + STEP_CODE_DATA_STRUCT & io_sc ) \ +{ \ + return DlFatalError( i_chip, io_sc, POS ); \ +} \ +PRDF_PLUGIN_DEFINE( axone_omic, DlFatalError_##POS ); + +DL_FATAL_ERROR_PLUGIN( 0 ); +DL_FATAL_ERROR_PLUGIN( 1 ); +DL_FATAL_ERROR_PLUGIN( 2 ); + +} // end namespace axone_omic + +} // end namespace PRDF diff --git a/src/usr/diag/prdf/common/plat/axone/prdf_plat_axone.mk b/src/usr/diag/prdf/common/plat/axone/prdf_plat_axone.mk index ea76f9121..24acb5bb6 100644 --- a/src/usr/diag/prdf/common/plat/axone/prdf_plat_axone.mk +++ b/src/usr/diag/prdf/common/plat/axone/prdf_plat_axone.mk @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2016,2018 +# Contributors Listed Below - COPYRIGHT 2016,2019 # [+] International Business Machines Corp. # # @@ -37,5 +37,7 @@ prd_incpath += ${PRD_SRC_PATH}/common/plat/axone # Object files common to both FSP and Hostboot ################################################################################ -# plat/cumulus/ (rule plugin related) +# plat/axone/ (rule plugin related) +prd_rule_plugin += prdfMccPlugins.o +prd_rule_plugin += prdfOmicPlugins.o diff --git a/src/usr/diag/prdf/common/plat/cumulus/cumulus_mc_regs.rule b/src/usr/diag/prdf/common/plat/cumulus/cumulus_mc_regs.rule index 50a0170c2..027a0c08c 100644 --- a/src/usr/diag/prdf/common/plat/cumulus/cumulus_mc_regs.rule +++ b/src/usr/diag/prdf/common/plat/cumulus/cumulus_mc_regs.rule @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2018 +# Contributors Listed Below - COPYRIGHT 2018,2019 # [+] International Business Machines Corp. # # @@ -50,3 +50,20 @@ capture group default; }; + ############################################################################ + # PCB Slave Error Regs + ############################################################################ + + register MC_ERROR_REG + { + name "MC PCB Slave error reg"; + scomaddr 0x070F001F; + capture group PllFIRs; + }; + + register MC_CONFIG_REG + { + name "MC PCB Slave config reg"; + scomaddr 0x070F001E; + capture group PllFIRs; + }; diff --git a/src/usr/diag/prdf/common/plat/cumulus/cumulus_obus.rule b/src/usr/diag/prdf/common/plat/cumulus/cumulus_obus.rule index 8c950bbc7..7275e26a3 100644 --- a/src/usr/diag/prdf/common/plat/cumulus/cumulus_obus.rule +++ b/src/usr/diag/prdf/common/plat/cumulus/cumulus_obus.rule @@ -469,12 +469,12 @@ group gIOOLFIR /** IOOLFIR[8] * link0 nak received */ - (rIOOLFIR, bit(8)) ? defaultMaskedError; + (rIOOLFIR, bit(8)) ? threshold_and_mask_self_non_smp_only; /** IOOLFIR[9] * link1 nak received */ - (rIOOLFIR, bit(9)) ? defaultMaskedError; + (rIOOLFIR, bit(9)) ? threshold_and_mask_self_non_smp_only; /** IOOLFIR[10] * link0 replay buffer full @@ -499,22 +499,22 @@ group gIOOLFIR /** IOOLFIR[14] * link0 sl ecc correctable */ - (rIOOLFIR, bit(14)) ? threshold_and_mask_self; + (rIOOLFIR, bit(14)) ? threshold_and_mask_self_smp_only; /** IOOLFIR[15] * link1 sl ecc correctable */ - (rIOOLFIR, bit(15)) ? threshold_and_mask_self; + (rIOOLFIR, bit(15)) ? threshold_and_mask_self_smp_only; /** IOOLFIR[16] * link0 sl ecc ue */ - (rIOOLFIR, bit(16)) ? threshold_and_mask_self; + (rIOOLFIR, bit(16)) ? threshold_and_mask_self_smp_only; /** IOOLFIR[17] * link1 sl ecc ue */ - (rIOOLFIR, bit(17)) ? threshold_and_mask_self; + (rIOOLFIR, bit(17)) ? threshold_and_mask_self_smp_only; /** IOOLFIR[18] * link0 retrain threshold @@ -597,12 +597,12 @@ group gIOOLFIR (rIOOLFIR, bit(33)) ? defaultMaskedError; /** IOOLFIR[34] - * link0 num replay + * link0 num replay or no forward progress */ (rIOOLFIR, bit(34)) ? defaultMaskedError; /** IOOLFIR[35] - * link1 num replay + * link1 num replay or no forward progress */ (rIOOLFIR, bit(35)) ? defaultMaskedError; @@ -619,12 +619,12 @@ group gIOOLFIR /** IOOLFIR[38] * link0 prbs select error */ - (rIOOLFIR, bit(38)) ? threshold_and_mask_self; + (rIOOLFIR, bit(38)) ? threshold_and_mask_self_smp_only; /** IOOLFIR[39] * link1 prbs select error */ - (rIOOLFIR, bit(39)) ? threshold_and_mask_self; + (rIOOLFIR, bit(39)) ? threshold_and_mask_self_smp_only; /** IOOLFIR[40] * link0 tcomplete bad @@ -639,102 +639,102 @@ group gIOOLFIR /** IOOLFIR[42] * link0 no spare lane available */ - (rIOOLFIR, bit(42)) ? obusSmpCallout_L0; + (rIOOLFIR, bit(42)) ? obusSmpCallout_L0_smp_only; /** IOOLFIR[43] * link1 no spare lane available */ - (rIOOLFIR, bit(43)) ? obusSmpCallout_L1; + (rIOOLFIR, bit(43)) ? obusSmpCallout_L1_smp_only; /** IOOLFIR[44] - * link0 spare done + * link0 spare done or degraded mode */ - (rIOOLFIR, bit(44)) ? obusSmpCallout_th32_L0; + (rIOOLFIR, bit(44)) ? spare_lane_degraded_mode_L0; /** IOOLFIR[45] - * link1 spare done + * link1 spare done or degraded mode */ - (rIOOLFIR, bit(45)) ? obusSmpCallout_th32_L1; + (rIOOLFIR, bit(45)) ? spare_lane_degraded_mode_L1; /** IOOLFIR[46] * link0 too many crc errors */ - (rIOOLFIR, bit(46)) ? obusSmpCallout_L0; + (rIOOLFIR, bit(46)) ? obusSmpCallout_L0_smp_only; /** IOOLFIR[47] * link1 too many crc errors */ - (rIOOLFIR, bit(47)) ? obusSmpCallout_L1; + (rIOOLFIR, bit(47)) ? obusSmpCallout_L1_smp_only; /** IOOLFIR[48] - * link0 npu error + * link0 npu error or orx otx dlx errors */ (rIOOLFIR, bit(48)) ? threshold_and_mask_self; /** IOOLFIR[49] - * link1 npu error + * link1 npu error or orx otx dlx errors */ (rIOOLFIR, bit(49)) ? threshold_and_mask_self; /** IOOLFIR[50] * linkx npu error */ - (rIOOLFIR, bit(50)) ? threshold_and_mask_self; + (rIOOLFIR, bit(50)) ? threshold_and_mask_self_smp_only; /** IOOLFIR[51] * osc switch */ - (rIOOLFIR, bit(51)) ? threshold_and_mask_self; + (rIOOLFIR, bit(51)) ? threshold_and_mask_self_smp_only; /** IOOLFIR[52] * link0 correctable array error */ - (rIOOLFIR, bit(52)) ? obusSmpCallout_th32_L0; + (rIOOLFIR, bit(52)) ? self_th_32perDay; /** IOOLFIR[53] * link1 correctable array error */ - (rIOOLFIR, bit(53)) ? obusSmpCallout_th32_L1; + (rIOOLFIR, bit(53)) ? self_th_32perDay; /** IOOLFIR[54] * link0 uncorrectable array error */ - (rIOOLFIR, bit(54)) ? obusSmpFailure_L0; + (rIOOLFIR, bit(54)) ? self_th_1; /** IOOLFIR[55] * link1 uncorrectable array error */ - (rIOOLFIR, bit(55)) ? obusSmpFailure_L1; + (rIOOLFIR, bit(55)) ? self_th_1; /** IOOLFIR[56] * link0 training failed */ - (rIOOLFIR, bit(56)) ? obusSmpFailure_L0; + (rIOOLFIR, bit(56)) ? training_failure_L0; /** IOOLFIR[57] * link1 training failed */ - (rIOOLFIR, bit(57)) ? obusSmpFailure_L1; + (rIOOLFIR, bit(57)) ? training_failure_L1; /** IOOLFIR[58] * link0 unrecoverable error */ - (rIOOLFIR, bit(58)) ? obusSmpFailure_L0; + (rIOOLFIR, bit(58)) ? unrecoverable_error_L0; /** IOOLFIR[59] * link1 unrecoverable error */ - (rIOOLFIR, bit(59)) ? obusSmpFailure_L1; + (rIOOLFIR, bit(59)) ? unrecoverable_error_L1; /** IOOLFIR[60] * link0 internal error */ - (rIOOLFIR, bit(60)) ? obusSmpFailure_L0; + (rIOOLFIR, bit(60)) ? internal_error_L0; /** IOOLFIR[61] * link1 internal error */ - (rIOOLFIR, bit(61)) ? obusSmpFailure_L1; + (rIOOLFIR, bit(61)) ? internal_error_L1; /** IOOLFIR[62] * fir scom err dup diff --git a/src/usr/diag/prdf/common/plat/cumulus/cumulus_phb.rule b/src/usr/diag/prdf/common/plat/cumulus/cumulus_phb.rule index 9c8dcce38..88c917458 100644 --- a/src/usr/diag/prdf/common/plat/cumulus/cumulus_phb.rule +++ b/src/usr/diag/prdf/common/plat/cumulus/cumulus_phb.rule @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2016,2018 +# Contributors Listed Below - COPYRIGHT 2016,2019 # [+] International Business Machines Corp. # # @@ -212,7 +212,7 @@ group gPHBNFIR /** PHBNFIR[0] * BAR Parity Error */ - (rPHBNFIR, bit(0)) ? self_th_1; + (rPHBNFIR, bit(0)) ? parent_proc_th_1; /** PHBNFIR[1] * Parity Errors on Registers besides BAR @@ -252,12 +252,12 @@ group gPHBNFIR /** PHBNFIR[8] * Register Array Parity Error */ - (rPHBNFIR, bit(8)) ? self_th_1; + (rPHBNFIR, bit(8)) ? parent_proc_th_1; /** PHBNFIR[9] * Power Bus Interface Parity Error */ - (rPHBNFIR, bit(9)) ? self_th_1; + (rPHBNFIR, bit(9)) ? parent_proc_th_1; /** PHBNFIR[10] * Power Bus Data Hang @@ -297,7 +297,7 @@ group gPHBNFIR /** PHBNFIR[17] * Hardware Error */ - (rPHBNFIR, bit(17)) ? self_th_1; + (rPHBNFIR, bit(17)) ? parent_proc_th_1; /** PHBNFIR[18] * Unsolicited Power Bus Data diff --git a/src/usr/diag/prdf/common/plat/cumulus/cumulus_proc.rule b/src/usr/diag/prdf/common/plat/cumulus/cumulus_proc.rule index 187cd2a44..ae8e6bb80 100644 --- a/src/usr/diag/prdf/common/plat/cumulus/cumulus_proc.rule +++ b/src/usr/diag/prdf/common/plat/cumulus/cumulus_proc.rule @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2016,2018 +# Contributors Listed Below - COPYRIGHT 2016,2019 # [+] International Business Machines Corp. # # @@ -2893,7 +2893,7 @@ group gNXCQFIR /** NXCQFIR[19] * Uncorrectable error on ERAT arrays */ - (rNXCQFIR, bit(19)) ? nx_th_32perDay; + (rNXCQFIR, bit(19)) ? nx_th_1; /** NXCQFIR[20] * SUE on ERAT arrays diff --git a/src/usr/diag/prdf/common/plat/cumulus/cumulus_proc_actions.rule b/src/usr/diag/prdf/common/plat/cumulus/cumulus_proc_actions.rule index 26d62e95f..91298d653 100644 --- a/src/usr/diag/prdf/common/plat/cumulus/cumulus_proc_actions.rule +++ b/src/usr/diag/prdf/common/plat/cumulus/cumulus_proc_actions.rule @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2018 +# Contributors Listed Below - COPYRIGHT 2018,2019 # [+] International Business Machines Corp. # # @@ -23,6 +23,12 @@ # # IBM_PROLOG_END_TAG +################################################################################ +# Analyze +################################################################################ + +actionclass analyzeENHCAFIR { analyze(gENHCAFIR); }; + ############################################################################### # Analyze connected ############################################################################### diff --git a/src/usr/diag/prdf/common/plat/explorer/explorer_ocmb.rule b/src/usr/diag/prdf/common/plat/explorer/explorer_ocmb.rule index 1abd08c96..c1e5c15a8 100644 --- a/src/usr/diag/prdf/common/plat/explorer/explorer_ocmb.rule +++ b/src/usr/diag/prdf/common/plat/explorer/explorer_ocmb.rule @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2018 +# Contributors Listed Below - COPYRIGHT 2018,2019 # [+] International Business Machines Corp. # # @@ -44,82 +44,82 @@ chip explorer_ocmb ############################################################################# ############################################################################ - # MB Chiplet FIR + # OCMB Chiplet FIR ############################################################################ - register MB_CHIPLET_CS_FIR + register OCMB_CHIPLET_CS_FIR { - name "MB Chiplet Checkstop FIR"; + name "OCMB Chiplet Checkstop FIR"; scomaddr 0x08040000; capture group default; }; - register MB_CHIPLET_RE_FIR + register OCMB_CHIPLET_RE_FIR { - name "MB Chiplet Recoverable FIR"; + name "OCMB Chiplet Recoverable FIR"; scomaddr 0x08040001; capture group default; }; - register MB_CHIPLET_FIR_MASK + register OCMB_CHIPLET_FIR_MASK { - name "MB Chiplet FIR MASK"; + name "OCMB Chiplet FIR MASK"; scomaddr 0x08040002; capture group default; }; ############################################################################ - # MB Chiplet Special Attention FIR + # OCMB Chiplet Special Attention FIR ############################################################################ - register MB_CHIPLET_SPA_FIR + register OCMB_CHIPLET_SPA_FIR { - name "MB Chiplet Special Attention FIR"; + name "OCMB Chiplet Special Attention FIR"; scomaddr 0x08040004; capture group default; }; - register MB_CHIPLET_SPA_FIR_MASK + register OCMB_CHIPLET_SPA_FIR_MASK { - name "MB Chiplet Special Attention FIR MASK"; + name "OCMB Chiplet Special Attention FIR MASK"; scomaddr 0x08040007; capture group default; }; ############################################################################ - # Explorer chip MB_LFIR + # Explorer chip OCMB_LFIR ############################################################################ - register MB_LFIR + register OCMB_LFIR { - name "Explorer chip MB_LFIR"; + name "Explorer chip OCMB_LFIR"; scomaddr 0x0804000a; reset (&, 0x0804000b); mask (|, 0x0804000f); capture group default; }; - register MB_LFIR_MASK + register OCMB_LFIR_MASK { - name "Explorer chip MB_LFIR MASK"; + name "Explorer chip OCMB_LFIR MASK"; scomaddr 0x0804000d; capture group default; }; - register MB_LFIR_ACT0 + register OCMB_LFIR_ACT0 { - name "Explorer chip MB_LFIR ACT0"; + name "Explorer chip OCMB_LFIR ACT0"; scomaddr 0x08040010; capture group default; - capture req nonzero("MB_LFIR"); + capture req nonzero("OCMB_LFIR"); }; - register MB_LFIR_ACT1 + register OCMB_LFIR_ACT1 { - name "Explorer chip MB_LFIR ACT1"; + name "Explorer chip OCMB_LFIR ACT1"; scomaddr 0x08040011; capture group default; - capture req nonzero("MB_LFIR"); + capture req nonzero("OCMB_LFIR"); }; ############################################################################ @@ -355,174 +355,261 @@ chip explorer_ocmb ############################################################################## ################################################################################ -# MB Chiplet FIR +# OCMB Chiplet FIR ################################################################################ -rule rMB_CHIPLET_FIR +rule rOCMB_CHIPLET_FIR { UNIT_CS: - MB_CHIPLET_CS_FIR & ~MB_CHIPLET_FIR_MASK & `1fffffffffffffff`; + OCMB_CHIPLET_CS_FIR & ~OCMB_CHIPLET_FIR_MASK & `1fffffffffffffff`; RECOVERABLE: - (MB_CHIPLET_RE_FIR >> 2) & ~MB_CHIPLET_FIR_MASK & `1fffffffffffffff`; + (OCMB_CHIPLET_RE_FIR >> 2) & ~OCMB_CHIPLET_FIR_MASK & `1fffffffffffffff`; }; -group gMB_CHIPLET_FIR attntype CHECK_STOP, RECOVERABLE +# NOTE: RDFFIR[14|34] are possible side effects of OCMB_LFIR[38], as such, +# OCMB_LFIR must be analyzed first for correct handling. If changes are +# made so the RDFFIR is analyzed first, additional changes to the handling +# of those bits will be required. +group gOCMB_CHIPLET_FIR attntype UNIT_CS, RECOVERABLE filter singlebit { - /** MB_CHIPLET_FIR[3] - * Attention from MB_LFIR + /** OCMB_CHIPLET_FIR[3] + * Attention from OCMB_LFIR */ - (rMB_CHIPLET_FIR, bit(3)) ? analyzeMB_LFIR; + (rOCMB_CHIPLET_FIR, bit(3)) ? analyzeOCMB_LFIR; - /** MB_CHIPLET_FIR[4] + /** OCMB_CHIPLET_FIR[4] * Attention from MMIOFIR */ - (rMB_CHIPLET_FIR, bit(4)) ? analyzeMMIOFIR; + (rOCMB_CHIPLET_FIR, bit(4)) ? analyzeMMIOFIR; - /** MB_CHIPLET_FIR[7] + /** OCMB_CHIPLET_FIR[7] * Attention from SRQFIR */ - (rMB_CHIPLET_FIR, bit(7)) ? analyzeSRQFIR; + (rOCMB_CHIPLET_FIR, bit(7)) ? analyzeSRQFIR; - /** MB_CHIPLET_FIR[8] + /** OCMB_CHIPLET_FIR[8] * Attention from MCBISTFIR */ - (rMB_CHIPLET_FIR, bit(8)) ? analyzeMCBISTFIR; + (rOCMB_CHIPLET_FIR, bit(8)) ? analyzeMCBISTFIR; - /** MB_CHIPLET_FIR[9] + /** OCMB_CHIPLET_FIR[9] * Attention from RDFFIR */ - (rMB_CHIPLET_FIR, bit(9)) ? analyzeRDFFIR; + (rOCMB_CHIPLET_FIR, bit(9)) ? analyzeRDFFIR; - /** MB_CHIPLET_FIR[11] + /** OCMB_CHIPLET_FIR[11] * Attention from TLXFIR */ - (rMB_CHIPLET_FIR, bit(11)) ? analyzeTLXFIR; + (rOCMB_CHIPLET_FIR, bit(11)) ? analyzeTLXFIR; - /** MB_CHIPLET_FIR[12] + /** OCMB_CHIPLET_FIR[12] * Attention from OMIDLFIR */ - (rMB_CHIPLET_FIR, bit(12)) ? analyzeOMIDLFIR; + (rOCMB_CHIPLET_FIR, bit(12)) ? analyzeOMIDLFIR; }; ################################################################################ -# MB Chiplet Special Attention FIR +# OCMB Chiplet Special Attention FIR ################################################################################ -rule rMB_CHIPLET_SPA_FIR +rule rOCMB_CHIPLET_SPA_FIR { HOST_ATTN: - MB_CHIPLET_SPA_FIR & ~MB_CHIPLET_SPA_FIR_MASK; + OCMB_CHIPLET_SPA_FIR & ~OCMB_CHIPLET_SPA_FIR_MASK; }; -group gMB_CHIPLET_SPA_FIR attntype HOST_ATTN +group gOCMB_CHIPLET_SPA_FIR attntype HOST_ATTN filter singlebit { - /** MB_CHIPLET_SPA_FIR[1] + /** OCMB_CHIPLET_SPA_FIR[1] * Attention from MMIOFIR */ - (rMB_CHIPLET_SPA_FIR, bit(1)) ? analyzeMMIOFIR; + (rOCMB_CHIPLET_SPA_FIR, bit(1)) ? analyzeMMIOFIR; - /** MB_CHIPLET_SPA_FIR[4] + /** OCMB_CHIPLET_SPA_FIR[4] * Attention from SRQFIR */ - (rMB_CHIPLET_SPA_FIR, bit(4)) ? analyzeSRQFIR; + (rOCMB_CHIPLET_SPA_FIR, bit(4)) ? analyzeSRQFIR; - /** MB_CHIPLET_SPA_FIR[5] + /** OCMB_CHIPLET_SPA_FIR[5] * Attention from MCBISTFIR */ - (rMB_CHIPLET_SPA_FIR, bit(5)) ? analyzeMCBISTFIR; + (rOCMB_CHIPLET_SPA_FIR, bit(5)) ? analyzeMCBISTFIR; - /** MB_CHIPLET_SPA_FIR[6] + /** OCMB_CHIPLET_SPA_FIR[6] * Attention from RDFFIR */ - (rMB_CHIPLET_SPA_FIR, bit(6)) ? analyzeRDFFIR; + (rOCMB_CHIPLET_SPA_FIR, bit(6)) ? analyzeRDFFIR; - /** MB_CHIPLET_SPA_FIR[8] + /** OCMB_CHIPLET_SPA_FIR[8] * Attention from TLXFIR */ - (rMB_CHIPLET_SPA_FIR, bit(8)) ? analyzeTLXFIR; + (rOCMB_CHIPLET_SPA_FIR, bit(8)) ? analyzeTLXFIR; - /** MB_CHIPLET_SPA_FIR[9] + /** OCMB_CHIPLET_SPA_FIR[9] * Attention from OMIDLFIR */ - (rMB_CHIPLET_SPA_FIR, bit(9)) ? analyzeOMIDLFIR; + (rOCMB_CHIPLET_SPA_FIR, bit(9)) ? analyzeOMIDLFIR; }; ################################################################################ -# Explorer chip MB_LFIR +# Explorer chip OCMB_LFIR ################################################################################ -rule rMB_LFIR +rule rOCMB_LFIR { UNIT_CS: - MB_LFIR & ~MB_LFIR_MASK & ~MB_LFIR_ACT0 & ~MB_LFIR_ACT1; + OCMB_LFIR & ~OCMB_LFIR_MASK & ~OCMB_LFIR_ACT0 & ~OCMB_LFIR_ACT1; RECOVERABLE: - MB_LFIR & ~MB_LFIR_MASK & ~MB_LFIR_ACT0 & MB_LFIR_ACT1; - HOST_ATTN: - MB_LFIR & ~MB_LFIR_MASK & MB_LFIR_ACT0 & ~MB_LFIR_ACT1; + OCMB_LFIR & ~OCMB_LFIR_MASK & ~OCMB_LFIR_ACT0 & OCMB_LFIR_ACT1; }; -group gMB_LFIR +group gOCMB_LFIR filter singlebit, cs_root_cause { - /** MB_LFIR[0] + /** OCMB_LFIR[0] * CFIR access PCB error */ - (rMB_LFIR, bit(0)) ? defaultMaskedError; + (rOCMB_LFIR, bit(0)) ? self_th_32perDay; - /** MB_LFIR[1] + /** OCMB_LFIR[1] * CFIR internal parity error */ - (rMB_LFIR, bit(1)) ? defaultMaskedError; + (rOCMB_LFIR, bit(1)) ? self_th_32perDay; - /** MB_LFIR[2] + /** OCMB_LFIR[2] * LFIR internal parity error */ - (rMB_LFIR, bit(2)) ? defaultMaskedError; + (rOCMB_LFIR, bit(2)) ? self_th_32perDay; - /** MB_LFIR[3] + /** OCMB_LFIR[3] * Debug scom satellite error */ - (rMB_LFIR, bit(3)) ? defaultMaskedError; + (rOCMB_LFIR, bit(3)) ? defaultMaskedError; - /** MB_LFIR[4] + /** OCMB_LFIR[4] * PSCOM Logic: PCB Access Error */ - (rMB_LFIR, bit(4)) ? defaultMaskedError; + (rOCMB_LFIR, bit(4)) ? defaultMaskedError; - /** MB_LFIR[5] + /** OCMB_LFIR[5] * PSCOM Logic: Summarized internal errors */ - (rMB_LFIR, bit(5)) ? defaultMaskedError; + (rOCMB_LFIR, bit(5)) ? defaultMaskedError; - /** MB_LFIR[6] + /** OCMB_LFIR[6] * Trace Logic : Scom Satellite Error - Trace0 */ - (rMB_LFIR, bit(6)) ? defaultMaskedError; + (rOCMB_LFIR, bit(6)) ? defaultMaskedError; - /** MB_LFIR[7] + /** OCMB_LFIR[7] * Trace Logic : Scom Satellite Error - Trace1 */ - (rMB_LFIR, bit(7)) ? defaultMaskedError; + (rOCMB_LFIR, bit(7)) ? defaultMaskedError; - /** MB_LFIR[8] - * unused + /** OCMB_LFIR[8] + * PIB2GIF parity error on FSM or Registers */ - (rMB_LFIR, bit(8)) ? defaultMaskedError; + (rOCMB_LFIR, bit(8)) ? self_th_32perDay; - /** MB_LFIR[9] + /** OCMB_LFIR[9] * MSG access PCB error */ - (rMB_LFIR, bit(9)) ? defaultMaskedError; + (rOCMB_LFIR, bit(9)) ? defaultMaskedError; + + /** OCMB_LFIR[10:18] + * unused + */ + (rOCMB_LFIR, bit(10|11|12|13|14|15|16|17|18)) ? defaultMaskedError; + + /** OCMB_LFIR[19] + * DLL IRQ + */ + (rOCMB_LFIR, bit(19)) ? defaultMaskedError; + + /** OCMB_LFIR[20] + * Watchdog timer interrupt + */ + (rOCMB_LFIR, bit(20)) ? self_th_1; + + /** OCMB_LFIR[21] + * internal temp sensor tripped a threshold + */ + (rOCMB_LFIR, bit(21)) ? defaultMaskedError; + + /** OCMB_LFIR[22] + * GPBC_FATAL_ERROR + */ + (rOCMB_LFIR, bit(22)) ? self_th_1; + + /** OCMB_LFIR[23] + * GPBC_NON_FATAL_ERROR + */ + (rOCMB_LFIR, bit(23)) ? self_th_1; + + /** OCMB_LFIR[24] + * early power off warning + */ + (rOCMB_LFIR, bit(24)) ? defaultMaskedError; + + /** OCMB_LFIR[25] + * TOP fatal interrupts + */ + (rOCMB_LFIR, bit(25)) ? self_th_1; + + /** OCMB_LFIR[26] + * TOP non fatal interrupts + */ + (rOCMB_LFIR, bit(26)) ? level2_M_self_L_th_1; + + /** OCMB_LFIR[27:34] + * Interrupt from OPSe to OCMB + */ + (rOCMB_LFIR, bit(27|28|29|30|31|32|33|34)) ? defaultMaskedError; + + /** OCMB_LFIR[35] + * DDR thermal event + */ + (rOCMB_LFIR, bit(35)) ? defaultMaskedError; + + /** OCMB_LFIR[36] + * DDR4 PHY fatal + */ + (rOCMB_LFIR, bit(36)) ? self_th_1; + + /** OCMB_LFIR[37] + * DDR4 PHY non fatal + */ + (rOCMB_LFIR, bit(37)) ? self_th_32perDay; + + /** OCMB_LFIR[38] + * DDR4 PHY interrupt + */ + (rOCMB_LFIR, bit(38)) ? ddr4_phy_interrupt; - /** MB_LFIR[10:62] - * bits from the microsemi message register (0 to 52) + /** OCMB_LFIR[39:46] + * foxhound fatal */ - (rMB_LFIR, bit(10|11|12|13|14|15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39|40|41|42|43|44|45|46|47|48|49|50|51|52|53|54|55|56|57|58|59|60|61|62)) ? defaultMaskedError; + (rOCMB_LFIR, bit(39|40|41|42|43|44|45|46)) ? foxhound_fatal; + + /** OCMB_LFIR[47:54] + * foxhound non fatal + */ + (rOCMB_LFIR, bit(47|48|49|50|51|52|53|54)) ? defaultMaskedError; + + /** OCMB_LFIR[55:62] + * foxhound serdes interrupt + */ + (rOCMB_LFIR, bit(55|56|57|58|59|60|61|62)) ? defaultMaskedError; + + /** OCMB_LFIR[63] + * GIF2PCB parity error on FSM or Registers + */ + (rOCMB_LFIR, bit(63)) ? self_th_32perDay; }; @@ -557,27 +644,27 @@ group gMMIOFIR /** MMIOFIR[2] * SCOM err */ - (rMMIOFIR, bit(2)) ? defaultMaskedError; + (rMMIOFIR, bit(2)) ? self_th_32perDay; /** MMIOFIR[3] - * FSM err + * FSM perr */ - (rMMIOFIR, bit(3)) ? defaultMaskedError; + (rMMIOFIR, bit(3)) ? self_th_1; /** MMIOFIR[4] * FIFO overflow */ - (rMMIOFIR, bit(4)) ? defaultMaskedError; + (rMMIOFIR, bit(4)) ? self_th_1; /** MMIOFIR[5] * Ctl reg parity err */ - (rMMIOFIR, bit(5)) ? defaultMaskedError; + (rMMIOFIR, bit(5)) ? self_th_1; /** MMIOFIR[6] * Info reg parity error */ - (rMMIOFIR, bit(6)) ? defaultMaskedError; + (rMMIOFIR, bit(6)) ? self_th_1; /** MMIOFIR[7] * SNSC both starts err @@ -622,22 +709,22 @@ rule rSRQFIR group gSRQFIR filter singlebit, - cs_root_cause + cs_root_cause(18) { /** SRQFIR[0] * SRQ recoverable error */ - (rSRQFIR, bit(0)) ? defaultMaskedError; + (rSRQFIR, bit(0)) ? mem_port_th_1; /** SRQFIR[1] * SRQ nonrecoverable error */ - (rSRQFIR, bit(1)) ? defaultMaskedError; + (rSRQFIR, bit(1)) ? mem_port_th_1; /** SRQFIR[2] * Refresh overrun */ - (rSRQFIR, bit(2)) ? defaultMaskedError; + (rSRQFIR, bit(2)) ? mem_port_th_32perDay; /** SRQFIR[3] * WAT error @@ -647,12 +734,12 @@ group gSRQFIR /** SRQFIR[4] * RCD parity error */ - (rSRQFIR, bit(4)) ? defaultMaskedError; + (rSRQFIR, bit(4)) ? srq_rcd_parity_error; /** SRQFIR[5] * MCB logic error */ - (rSRQFIR, bit(5)) ? defaultMaskedError; + (rSRQFIR, bit(5)) ? mem_port_th_1; /** SRQFIR[6] * Emergency throttle @@ -662,7 +749,7 @@ group gSRQFIR /** SRQFIR[7] * NCF MCB parity error */ - (rSRQFIR, bit(7)) ? defaultMaskedError; + (rSRQFIR, bit(7)) ? mem_port_th_1; /** SRQFIR[8] * DDR MBA event n @@ -672,82 +759,82 @@ group gSRQFIR /** SRQFIR[9] * WRQ RRQ hang err */ - (rSRQFIR, bit(9)) ? defaultMaskedError; + (rSRQFIR, bit(9)) ? mem_port_th_1; /** SRQFIR[10] * SM one hot error */ - (rSRQFIR, bit(10)) ? defaultMaskedError; + (rSRQFIR, bit(10)) ? mem_port_th_1; /** SRQFIR[11] * Reg parity error */ - (rSRQFIR, bit(11)) ? defaultMaskedError; + (rSRQFIR, bit(11)) ? mem_port_th_1; /** SRQFIR[12] * Cmd parity error */ - (rSRQFIR, bit(12)) ? defaultMaskedError; + (rSRQFIR, bit(12)) ? mem_port_th_1; /** SRQFIR[13] * Port fail */ - (rSRQFIR, bit(13)) ? defaultMaskedError; + (rSRQFIR, bit(13)) ? mem_port_failure; /** SRQFIR[14] - * Spare + * informational register parity error bit */ - (rSRQFIR, bit(14)) ? defaultMaskedError; + (rSRQFIR, bit(14)) ? threshold_and_mask_mem_port; /** SRQFIR[15] * Debug parity error */ - (rSRQFIR, bit(15)) ? defaultMaskedError; + (rSRQFIR, bit(15)) ? threshold_and_mask_mem_port; /** SRQFIR[16] * WDF unrecoverable mainline error */ - (rSRQFIR, bit(16)) ? defaultMaskedError; + (rSRQFIR, bit(16)) ? mem_port_th_1; /** SRQFIR[17] * WDF mmio error */ - (rSRQFIR, bit(17)) ? defaultMaskedError; + (rSRQFIR, bit(17)) ? mem_port_th_1; /** SRQFIR[18] * WDF array UE on mainline operations (SUE put in mem) */ - (rSRQFIR, bit(18)) ? defaultMaskedError; + (rSRQFIR, bit(18)) ? mem_port_th_1_UERE; /** SRQFIR[19] * WDF mainline dataflow error (SUE not reliably put in mem) */ - (rSRQFIR, bit(19)) ? defaultMaskedError; + (rSRQFIR, bit(19)) ? mem_port_th_1; /** SRQFIR[20] * WDF scom register parity err, affecting mainline config */ - (rSRQFIR, bit(20)) ? defaultMaskedError; + (rSRQFIR, bit(20)) ? mem_port_th_1; /** SRQFIR[21] * WDF scom register parity err, affecting scom ops only */ - (rSRQFIR, bit(21)) ? defaultMaskedError; + (rSRQFIR, bit(21)) ? mem_port_th_1; /** SRQFIR[22] * WDF SCOM fsm parity error */ - (rSRQFIR, bit(22)) ? defaultMaskedError; + (rSRQFIR, bit(22)) ? mem_port_th_1; /** SRQFIR[23] * WDF write buffer array CE */ - (rSRQFIR, bit(23)) ? defaultMaskedError; + (rSRQFIR, bit(23)) ? mem_port_th_32perDay; /** SRQFIR[24] * NCF UE */ - (rSRQFIR, bit(24)) ? defaultMaskedError; + (rSRQFIR, bit(24)) ? mem_port_th_1; /** SRQFIR[25] * TBD @@ -757,17 +844,17 @@ group gSRQFIR /** SRQFIR[26] * NCF logic error */ - (rSRQFIR, bit(26)) ? defaultMaskedError; + (rSRQFIR, bit(26)) ? mem_port_th_1; /** SRQFIR[27] * NCF parity error */ - (rSRQFIR, bit(27)) ? defaultMaskedError; + (rSRQFIR, bit(27)) ? mem_port_th_1; /** SRQFIR[28] * NCF correctable error */ - (rSRQFIR, bit(28)) ? defaultMaskedError; + (rSRQFIR, bit(28)) ? mem_port_th_32perDay; /** SRQFIR[29] * Internal scom error @@ -807,17 +894,17 @@ group gMCBISTFIR /** MCBISTFIR[1] * Command address timeout */ - (rMCBISTFIR, bit(1)) ? defaultMaskedError; + (rMCBISTFIR, bit(1)) ? self_th_1; /** MCBISTFIR[2] * Internal FSM error */ - (rMCBISTFIR, bit(2)) ? defaultMaskedError; + (rMCBISTFIR, bit(2)) ? self_th_1; /** MCBISTFIR[3] * MCBIST broadcast out of sync */ - (rMCBISTFIR, bit(3)) ? defaultMaskedError; + (rMCBISTFIR, bit(3)) ? self_th_1; /** MCBISTFIR[4] * MCBIST data error @@ -852,7 +939,7 @@ group gMCBISTFIR /** MCBISTFIR[10] * MCBIST program complete */ - (rMCBISTFIR, bit(10)) ? defaultMaskedError; + (rMCBISTFIR, bit(10)) ? mcbist_program_complete; /** MCBISTFIR[11] * MCBIST CCS subtest done @@ -865,14 +952,14 @@ group gMCBISTFIR (rMCBISTFIR, bit(12)) ? defaultMaskedError; /** MCBISTFIR[13] - * SCOM recoverable reg parity error + * SCOM recoverable register parity error */ - (rMCBISTFIR, bit(13)) ? defaultMaskedError; + (rMCBISTFIR, bit(13)) ? self_th_1; /** MCBISTFIR[14] * SCOM fatal reg parity error */ - (rMCBISTFIR, bit(14)) ? defaultMaskedError; + (rMCBISTFIR, bit(14)) ? self_th_1; /** MCBISTFIR[15] * SCOM WAT and debug reg parity error @@ -917,57 +1004,57 @@ rule rRDFFIR group gRDFFIR filter singlebit, - cs_root_cause + cs_root_cause(14,15,17,35,37) { /** RDFFIR[0] * Mainline read MPE on rank 0 */ - (rRDFFIR, bit(0)) ? defaultMaskedError; + (rRDFFIR, bit(0)) ? verify_chip_mark_0; /** RDFFIR[1] * Mainline read MPE on rank 1 */ - (rRDFFIR, bit(1)) ? defaultMaskedError; + (rRDFFIR, bit(1)) ? verify_chip_mark_1; /** RDFFIR[2] * Mainline read MPE on rank 2 */ - (rRDFFIR, bit(2)) ? defaultMaskedError; + (rRDFFIR, bit(2)) ? verify_chip_mark_2; /** RDFFIR[3] - * Maineline read MPE on rank 3 + * Mainline read MPE on rank 3 */ - (rRDFFIR, bit(3)) ? defaultMaskedError; + (rRDFFIR, bit(3)) ? verify_chip_mark_3; /** RDFFIR[4] * Mainline read MPE on rank 4 */ - (rRDFFIR, bit(4)) ? defaultMaskedError; + (rRDFFIR, bit(4)) ? verify_chip_mark_4; /** RDFFIR[5] * Mainline read MPE on rank 5 */ - (rRDFFIR, bit(5)) ? defaultMaskedError; + (rRDFFIR, bit(5)) ? verify_chip_mark_5; /** RDFFIR[6] * Mainline read MPE on rank 6 */ - (rRDFFIR, bit(6)) ? defaultMaskedError; + (rRDFFIR, bit(6)) ? verify_chip_mark_6; /** RDFFIR[7] * Mainline read MPE on rank 7 */ - (rRDFFIR, bit(7)) ? defaultMaskedError; + (rRDFFIR, bit(7)) ? verify_chip_mark_7; /** RDFFIR[8] * Mainline read NCE */ - (rRDFFIR, bit(8)) ? defaultMaskedError; + (rRDFFIR, bit(8)) ? mainline_nce_tce_handling; /** RDFFIR[9] * Mainline read TCE */ - (rRDFFIR, bit(9)) ? defaultMaskedError; + (rRDFFIR, bit(9)) ? mainline_nce_tce_handling; /** RDFFIR[10] * Mainline read SCE @@ -987,27 +1074,27 @@ group gRDFFIR /** RDFFIR[13] * Mainline read AUE */ - (rRDFFIR, bit(13)) ? defaultMaskedError; + (rRDFFIR, bit(13)) ? mainline_aue_iaue_handling; /** RDFFIR[14] * Mainline read UE */ - (rRDFFIR, bit(14)) ? defaultMaskedError; + (rRDFFIR, bit(14)) ? mainline_ue_handling_UERE; /** RDFFIR[15] * Mainline read RCD */ - (rRDFFIR, bit(15)) ? defaultMaskedError; + (rRDFFIR, bit(15)) ? rdf_rcd_parity_error_UERE; /** RDFFIR[16] * Mainline read IAUE */ - (rRDFFIR, bit(16)) ? defaultMaskedError; + (rRDFFIR, bit(16)) ? mainline_aue_iaue_handling; /** RDFFIR[17] * Mainline read IUE */ - (rRDFFIR, bit(17)) ? defaultMaskedError; + (rRDFFIR, bit(17)) ? mainline_iue_handling; /** RDFFIR[18] * Mainline read IRCD @@ -1017,7 +1104,7 @@ group gRDFFIR /** RDFFIR[19] * Mainline read IMPE */ - (rRDFFIR, bit(19)) ? defaultMaskedError; + (rRDFFIR, bit(19)) ? memory_impe_handling; /** RDFFIR[20:27] * Maintenance MPE @@ -1052,7 +1139,7 @@ group gRDFFIR /** RDFFIR[33] * Maintenance AUE */ - (rRDFFIR, bit(33)) ? defaultMaskedError; + (rRDFFIR, bit(33)) ? maintenance_aue_handling; /** RDFFIR[34] * Maintenance UE @@ -1062,72 +1149,72 @@ group gRDFFIR /** RDFFIR[35] * Maintenance RCD */ - (rRDFFIR, bit(35)) ? defaultMaskedError; + (rRDFFIR, bit(35)) ? rdf_rcd_parity_error_UERE; /** RDFFIR[36] * Maintenance IAUE */ - (rRDFFIR, bit(36)) ? defaultMaskedError; + (rRDFFIR, bit(36)) ? maintenance_iaue_handling; /** RDFFIR[37] * Maintenance IUE */ - (rRDFFIR, bit(37)) ? defaultMaskedError; + (rRDFFIR, bit(37)) ? maintenance_iue_handling; /** RDFFIR[38] - * Maintenance IRCD + * Maintenance IRCD */ (rRDFFIR, bit(38)) ? defaultMaskedError; /** RDFFIR[39] * Maintenance IMPE */ - (rRDFFIR, bit(39)) ? defaultMaskedError; + (rRDFFIR, bit(39)) ? memory_impe_handling; /** RDFFIR[40] * RDDATA valid error */ - (rRDFFIR, bit(40)) ? defaultMaskedError; + (rRDFFIR, bit(40)) ? mem_port_th_32perDay; /** RDFFIR[41] * SCOM status register parity error */ - (rRDFFIR, bit(41)) ? defaultMaskedError; + (rRDFFIR, bit(41)) ? threshold_and_mask_mem_port; /** RDFFIR[42] * SCOM recoverable register parity error */ - (rRDFFIR, bit(42)) ? defaultMaskedError; + (rRDFFIR, bit(42)) ? mem_port_th_1; /** RDFFIR[43] * SCOM unrecoverable register parity error */ - (rRDFFIR, bit(43)) ? defaultMaskedError; + (rRDFFIR, bit(43)) ? mem_port_th_1; /** RDFFIR[44] * ECC corrector internal parity error */ - (rRDFFIR, bit(44)) ? defaultMaskedError; + (rRDFFIR, bit(44)) ? mem_port_th_1; /** RDFFIR[45] * Rd Buff ECC CHK Cor CE DW0 Detected */ - (rRDFFIR, bit(45)) ? defaultMaskedError; + (rRDFFIR, bit(45)) ? mem_port_th_32perDay; /** RDFFIR[46] * Rd Buff ECC CHK Cor CE DW1 Detected */ - (rRDFFIR, bit(46)) ? defaultMaskedError; + (rRDFFIR, bit(46)) ? mem_port_th_32perDay; /** RDFFIR[47] * Rd Buff ECC CHK Cor UE DW0 Detected */ - (rRDFFIR, bit(47)) ? defaultMaskedError; + (rRDFFIR, bit(47)) ? mem_port_th_1; /** RDFFIR[48] * Rd Buff ECC CHK Cor UE DW1 Detected */ - (rRDFFIR, bit(48)) ? defaultMaskedError; + (rRDFFIR, bit(48)) ? mem_port_th_1; /** RDFFIR[49:59] * Reserved @@ -1177,67 +1264,67 @@ group gTLXFIR /** TLXFIR[0] * Info reg parity error */ - (rTLXFIR, bit(0)) ? defaultMaskedError; + (rTLXFIR, bit(0)) ? threshold_and_mask_self; /** TLXFIR[1] * Ctrl reg parity error */ - (rTLXFIR, bit(1)) ? defaultMaskedError; + (rTLXFIR, bit(1)) ? self_th_1; /** TLXFIR[2] * TLX VC0 return credit counter overflow */ - (rTLXFIR, bit(2)) ? defaultMaskedError; + (rTLXFIR, bit(2)) ? omi_bus_th_1; /** TLXFIR[3] * TLX VC1 return credit counter overflow */ - (rTLXFIR, bit(3)) ? defaultMaskedError; + (rTLXFIR, bit(3)) ? omi_bus_th_1; /** TLXFIR[4] * TLX dcp0 return credit counter overflow */ - (rTLXFIR, bit(4)) ? defaultMaskedError; + (rTLXFIR, bit(4)) ? omi_bus_th_1; /** TLXFIR[5] * TLX dcp1 return credit counter overflow */ - (rTLXFIR, bit(5)) ? defaultMaskedError; + (rTLXFIR, bit(5)) ? omi_bus_th_1; /** TLXFIR[6] * TLX credit management block error */ - (rTLXFIR, bit(6)) ? defaultMaskedError; + (rTLXFIR, bit(6)) ? self_th_1; /** TLXFIR[7] * TLX credit management block parity error */ - (rTLXFIR, bit(7)) ? defaultMaskedError; + (rTLXFIR, bit(7)) ? self_th_1; /** TLXFIR[8] * TLXT fatal parity error */ - (rTLXFIR, bit(8)) ? defaultMaskedError; + (rTLXFIR, bit(8)) ? self_th_1; /** TLXFIR[9] * TLXT recoverable error */ - (rTLXFIR, bit(9)) ? defaultMaskedError; + (rTLXFIR, bit(9)) ? analyzeTLXERR1; /** TLXFIR[10] * TLXT configuration error */ - (rTLXFIR, bit(10)) ? defaultMaskedError; + (rTLXFIR, bit(10)) ? level2_M_self_L_th_1; /** TLXFIR[11] * TLXT informational parity error */ - (rTLXFIR, bit(11)) ? defaultMaskedError; + (rTLXFIR, bit(11)) ? self_th_1; /** TLXFIR[12] * TLXT hard error */ - (rTLXFIR, bit(12)) ? defaultMaskedError; + (rTLXFIR, bit(12)) ? self_th_1; /** TLXFIR[13:15] * Reserved @@ -1257,47 +1344,47 @@ group gTLXFIR /** TLXFIR[18] * OC malformed */ - (rTLXFIR, bit(18)) ? defaultMaskedError; + (rTLXFIR, bit(18)) ? omi_bus_th_1; /** TLXFIR[19] * OC protocol error */ - (rTLXFIR, bit(19)) ? defaultMaskedError; + (rTLXFIR, bit(19)) ? omi_th_1; /** TLXFIR[20] * Address translate error */ - (rTLXFIR, bit(20)) ? defaultMaskedError; + (rTLXFIR, bit(20)) ? self_th_1; /** TLXFIR[21] * Metadata unc or data parity error */ - (rTLXFIR, bit(21)) ? defaultMaskedError; + (rTLXFIR, bit(21)) ? self_th_1; /** TLXFIR[22] * OC unsupported group 2 */ - (rTLXFIR, bit(22)) ? defaultMaskedError; + (rTLXFIR, bit(22)) ? omi_bus_th_1; /** TLXFIR[23] * OC unsupported group 1 */ - (rTLXFIR, bit(23)) ? defaultMaskedError; + (rTLXFIR, bit(23)) ? omi_bus_th_1; /** TLXFIR[24] * Bit flip control error */ - (rTLXFIR, bit(24)) ? defaultMaskedError; + (rTLXFIR, bit(24)) ? self_th_1; /** TLXFIR[25] * Control HW error */ - (rTLXFIR, bit(25)) ? defaultMaskedError; + (rTLXFIR, bit(25)) ? self_th_1; /** TLXFIR[26] * ECC corrected and others */ - (rTLXFIR, bit(26)) ? defaultMaskedError; + (rTLXFIR, bit(26)) ? self_th_32perDay; /** TLXFIR[27] * Trace stop @@ -1316,6 +1403,37 @@ group gTLXFIR }; +rule rTLX_ERR1_REPORT +{ + RECOVERABLE: + TLX_ERR1_REPORT & ~TLX_ERR1_REPORT_MASK; +}; + +group gTLX_ERR1_REPORT + filter singlebit, + cs_root_cause +{ + /** TLX_ERR1_REPORT[37] + * TLXT FIFO CE + */ + (rTLXFIR, bit(37)) ? self_th_32perDay; + + /** TLX_ERR1_REPORT[39] + * Unexpected Interrupt Response + */ + (rTLXFIR, bit(39)) ? parent_proc_th_32perDay; + + /** TLX_ERR1_REPORT[40] + * BDI Poisoned + */ + (rTLXFIR, bit(40)) ? self_th_1; + + /** TLX_ERR1_REPORT[41] + * TLXT Metadata UE + */ + (rTLXFIR, bit(41)) ? self_th_1; +}; + ################################################################################ # Explorer chip OMIDLFIR ################################################################################ @@ -1335,112 +1453,112 @@ group gOMIDLFIR cs_root_cause { /** OMIDLFIR[0] - * DL0 fatal error + * OMI-DL0 fatal error */ - (rOMIDLFIR, bit(0)) ? defaultMaskedError; + (rOMIDLFIR, bit(0)) ? dl_fatal_error; /** OMIDLFIR[1] - * Dl0 data UE + * OMI-DL0 UE on data flit */ - (rOMIDLFIR, bit(1)) ? defaultMaskedError; + (rOMIDLFIR, bit(1)) ? self_th_1; /** OMIDLFIR[2] - * Dl0 flit CE + * OMI-DL0 CE on TL flit */ - (rOMIDLFIR, bit(2)) ? defaultMaskedError; + (rOMIDLFIR, bit(2)) ? self_th_32perDay; /** OMIDLFIR[3] - * Dl0 CRC error + * OMI-DL0 detected a CRC error */ (rOMIDLFIR, bit(3)) ? defaultMaskedError; /** OMIDLFIR[4] - * DL0 nack + * OMI-DL0 received a nack */ (rOMIDLFIR, bit(4)) ? defaultMaskedError; /** OMIDLFIR[5] - * DL0 X4 mode + * OMI-DL0 running in degraded mode */ - (rOMIDLFIR, bit(5)) ? defaultMaskedError; + (rOMIDLFIR, bit(5)) ? omi_bus_th_1; /** OMIDLFIR[6] - * DL0 EDPL + * OMI-DL0 parity error detection on a lane */ (rOMIDLFIR, bit(6)) ? defaultMaskedError; /** OMIDLFIR[7] - * DL0 timeout + * OMI-DL0 retrained due to no forward progress */ - (rOMIDLFIR, bit(7)) ? defaultMaskedError; + (rOMIDLFIR, bit(7)) ? omi_bus_th_32perDay; /** OMIDLFIR[8] - * DL0 remote retrain + * OMI-DL0 remote side initiated a retrain */ (rOMIDLFIR, bit(8)) ? defaultMaskedError; /** OMIDLFIR[9] - * DL0 error retrain + * OMI-DL0 retrain due to internal error or software initiated */ - (rOMIDLFIR, bit(9)) ? defaultMaskedError; + (rOMIDLFIR, bit(9)) ? omi_bus_th_32perDay; /** OMIDLFIR[10] - * DL0 EDPL retrain + * OMI-DL0 threshold reached */ - (rOMIDLFIR, bit(10)) ? defaultMaskedError; + (rOMIDLFIR, bit(10)) ? omi_bus_th_32perDay; /** OMIDLFIR[11] - * DL0 trained + * OMI-DL0 trained */ (rOMIDLFIR, bit(11)) ? defaultMaskedError; /** OMIDLFIR[12] - * DL0 endpoint bit 0 + * OMI-DL0 endpoint error bit 0 */ (rOMIDLFIR, bit(12)) ? defaultMaskedError; /** OMIDLFIR[13] - * DL0 endpoint bit 1 + * OMI-DL0 endpoint error bit 1 */ (rOMIDLFIR, bit(13)) ? defaultMaskedError; /** OMIDLFIR[14] - * DL0 endpoint bit 2 + * OMI-DL0 endpoint error bit 2 */ (rOMIDLFIR, bit(14)) ? defaultMaskedError; /** OMIDLFIR[15] - * DL0 endpoint bit 3 + * OMI-DL0 endpoint error bit 3 */ (rOMIDLFIR, bit(15)) ? defaultMaskedError; /** OMIDLFIR[16] - * DL0 endpoint bit 4 + * OMI-DL0 endpoint error bit 4 */ (rOMIDLFIR, bit(16)) ? defaultMaskedError; /** OMIDLFIR[17] - * DL0 endpoint bit 5 + * OMI-DL0 endpoint error bit 5 */ (rOMIDLFIR, bit(17)) ? defaultMaskedError; /** OMIDLFIR[18] - * DL0 endpoint bit 6 + * OMI-DL0 endpoint error bit 6 */ (rOMIDLFIR, bit(18)) ? defaultMaskedError; /** OMIDLFIR[19] - * DL0 endpoint bit 7 + * OMI-DL0 endpoint error bit 7 */ (rOMIDLFIR, bit(19)) ? defaultMaskedError; /** OMIDLFIR[20:39] - * DL1 reserved + * OMI-DL1 reserved */ (rOMIDLFIR, bit(20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39)) ? defaultMaskedError; /** OMIDLFIR[40:59] - * DL2 reserved + * OMI-DL2 reserved */ (rOMIDLFIR, bit(40|41|42|43|44|45|46|47|48|49|50|51|52|53|54|55|56|57|58|59)) ? defaultMaskedError; @@ -1449,6 +1567,21 @@ group gOMIDLFIR */ (rOMIDLFIR, bit(60)) ? defaultMaskedError; + /** OMIDLFIR[61] + * reserved + */ + (rOMIDLFIR, bit(61)) ? defaultMaskedError; + + /** OMIDLFIR[62] + * LFIR internal parity error + */ + (rOMIDLFIR, bit(62)) ? defaultMaskedError; + + /** OMIDLFIR[63] + * SCOM Satellite Error + */ + (rOMIDLFIR, bit(63)) ? defaultMaskedError; + }; ############################################################################## @@ -1463,6 +1596,5 @@ group gOMIDLFIR ############################################################################## # Include the actions defined for this target -.include "p9_common_actions.rule"; .include "explorer_ocmb_actions.rule"; diff --git a/src/usr/diag/prdf/common/plat/explorer/explorer_ocmb_actions.rule b/src/usr/diag/prdf/common/plat/explorer/explorer_ocmb_actions.rule index 023821b0d..d5b6e3fad 100644 --- a/src/usr/diag/prdf/common/plat/explorer/explorer_ocmb_actions.rule +++ b/src/usr/diag/prdf/common/plat/explorer/explorer_ocmb_actions.rule @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2018 +# Contributors Listed Below - COPYRIGHT 2018,2019 # [+] International Business Machines Corp. # # @@ -55,22 +55,12 @@ actionclass threshold32pday threshold( field(32 / day) ); }; -################################################################################ -# Threshold and Mask policy -################################################################################ - -/** - * Threshold 32/day (field) and 1 (mnfg). Do not predictively callout on - * threshold in the field, instead just mask. - */ -actionclass threshold_and_mask +/** Threshold of 5 per day */ +actionclass threshold5pday { - threshold32pday; - funccall("ClearServiceCallFlag"); + threshold( field(5 / day) ); }; -actionclass threshold_and_mask_self { calloutSelfMed; threshold_and_mask; }; - ################################################################################ # Special Flags # ################################################################################ @@ -99,6 +89,50 @@ actionclass callout2ndLvlMed actionclass calloutSelfLowNoGard { callout(MRU_LOW, NO_GARD); }; +actionclass level2_M_self_L +{ + callout2ndLvlMed; + calloutSelfLow; +}; + +actionclass omi +{ + callout(connected(TYPE_OMI), MRU_MED); +}; + +actionclass omi_bus +{ + calloutSelfMedA; + callout(connected(TYPE_OMI), MRU_MEDA); + funccall("calloutBusInterfacePlugin"); +}; + +actionclass mem_port +{ + callout(connected(TYPE_MEM_PORT,0), MRU_MED); +}; + +actionclass mem_port_L +{ + callout(connected(TYPE_MEM_PORT,0), MRU_LOW); +}; + +actionclass all_dimm_H +{ + funccall("CalloutAttachedDimmsHigh"); +}; + +actionclass all_dimm_H_memport_L +{ + all_dimm_H; + mem_port_L; +}; + +actionclass parent_proc +{ + callout(connected(TYPE_PROC), MRU_MED); +}; + ################################################################################ # Callouts with thresholds # ################################################################################ @@ -109,15 +143,15 @@ actionclass self_th_1 threshold1; }; -actionclass self_th_5perHour +actionclass self_th_32perDay { calloutSelfMed; - threshold5phour; + threshold32pday; }; -actionclass self_th_32perDay +actionclass parent_proc_th_32perDay { - calloutSelfMed; + parent_proc; threshold32pday; }; @@ -127,12 +161,83 @@ actionclass level2_th_1 threshold1; }; +actionclass level2_th_32perDay +{ + callout2ndLvlMed; + threshold32pday; +}; + +actionclass level2_M_self_L_th_1 +{ + level2_M_self_L; + threshold1; +}; + +actionclass omi_th_1 +{ + omi; + threshold1; +}; + +actionclass omi_bus_th_1 +{ + omi_bus; + threshold1; +}; + +actionclass omi_bus_th_32perDay +{ + omi_bus; + threshold32pday; +}; + +actionclass mem_port_th_1 +{ + mem_port; + threshold1; +}; + +actionclass mem_port_th_32perDay +{ + mem_port; + threshold32pday; +}; + +################################################################################ +# Special # +################################################################################ + +/** + * Threshold 32/day (field) and 1 (mnfg). Do not predictively callout on + * threshold in the field, instead just mask. + */ +actionclass threshold_and_mask +{ + threshold32pday; + funccall("ClearServiceCallFlag"); +}; + +actionclass threshold_and_mask_self { calloutSelfMed; threshold_and_mask; }; + +actionclass threshold_and_mask_level2 +{ + level2_th_32perDay; + threshold_and_mask; +}; + +actionclass threshold_and_mask_mem_port +{ + mem_port_th_32perDay; + threshold_and_mask; +}; + ################################################################################ # Callouts with flags # ################################################################################ -actionclass self_th_1_UERE { self_th_1; SueSource; }; -actionclass level2_th_1_UERE { level2_th_1; SueSource; }; +actionclass self_th_1_UERE { self_th_1; SueSource; }; +actionclass level2_th_1_UERE { level2_th_1; SueSource; }; +actionclass mem_port_th_1_UERE { mem_port_th_1; SueSource; }; ################################################################################ # Default callouts # @@ -153,14 +258,166 @@ actionclass TBDDefaultCallout }; ################################################################################ +# OCMB Actions # +################################################################################ + +/** DDR4 PHY Interrupt */ +actionclass ddr4_phy_interrupt +{ + calloutSelfHigh; + threshold5pday; + funccall("Ddr4PhyInterrupt"); +}; + +/** Foxhound Fatal */ +actionclass foxhound_fatal +{ + funccall("FoxhoundFatal"); + threshold1; +}; + +/** OMI-DL Fatal Error */ +actionclass dl_fatal_error +{ + try( funccall("DlFatalError"), omi_bus ); + threshold1; +}; + +/** MCBIST program complete */ +actionclass mcbist_program_complete +{ + funccall("McbistCmdComplete"); +}; + +/** Verify Chip Mark */ +actionclass verify_chip_mark_0 { funccall("AnalyzeFetchMpe_0"); }; +actionclass verify_chip_mark_1 { funccall("AnalyzeFetchMpe_1"); }; +actionclass verify_chip_mark_2 { funccall("AnalyzeFetchMpe_2"); }; +actionclass verify_chip_mark_3 { funccall("AnalyzeFetchMpe_3"); }; +actionclass verify_chip_mark_4 { funccall("AnalyzeFetchMpe_4"); }; +actionclass verify_chip_mark_5 { funccall("AnalyzeFetchMpe_5"); }; +actionclass verify_chip_mark_6 { funccall("AnalyzeFetchMpe_6"); }; +actionclass verify_chip_mark_7 { funccall("AnalyzeFetchMpe_7"); }; + +/** Mainline NCE/TCE handling */ +actionclass mainline_nce_tce_handling +{ + funccall("AnalyzeFetchNceTce"); +}; + +/** Handle Mainline AUEs/IAUEs */ +actionclass mainline_aue_iaue_handling +{ + funccall("AnalyzeFetchAueIaue"); + mem_port_L; + threshold1; +}; + +/** Mainline UE handling */ +actionclass mainline_ue_handling +{ + threshold( field(33 / 30 min ) ); # To prevent flooding. Will be unmasked + # when background scrubbing resumes after + # targeted diagnostics is complete. + funccall("AnalyzeFetchUe"); +}; + +actionclass mainline_ue_handling_UERE +{ + SueSource; + mainline_ue_handling; +}; + +/** Handle Mainline IUEs */ +actionclass mainline_iue_handling +{ + # An IUE itself is not a SUE source, however, a threshold of IUEs will + # trigger a port failure, which will generate SUEs. The port failure could + # also crash the machine so we want to make sure this bit is flagged as an + # SUE just in case it is needed in the checkstop analysis. + SueSource; + # Thresholding done in the plugin + funccall("AnalyzeMainlineIue"); +}; + +/** Handle Maintenance IUEs */ +actionclass maintenance_iue_handling +{ + # An IUE itself is not a SUE source, however, a threshold of IUEs will + # trigger a port failure, which will generate SUEs. The port failure could + # also crash the machine so we want to make sure this bit is flagged as an + # SUE just in case it is needed in the checkstop analysis. + SueSource; + # Thresholding done in the plugin + funccall("AnalyzeMaintIue"); +}; + +actionclass memory_impe_handling +{ + funccall("AnalyzeImpe"); +}; + +/** Handle Maintenance AUEs */ +actionclass maintenance_aue_handling +{ + funccall("AnalyzeMaintAue"); + mem_port_L; + threshold1; +}; + +/** Handle Maintenance IAUEs */ +actionclass maintenance_iaue_handling +{ + all_dimm_H_memport_L; + threshold1; +}; + +/** RDF RCD Parity Error */ +actionclass rdf_rcd_parity_error +{ + funccall("RdfRcdParityError"); + threshold1; +}; + +actionclass rdf_rcd_parity_error_UERE +{ + rdf_rcd_parity_error; + SueSource; +}; + +/** SRQ RCD Parity Error */ +actionclass srq_rcd_parity_error +{ + all_dimm_H_memport_L; + threshold32pday; +}; + +actionclass srq_rcd_parity_error_UERE +{ + srq_rcd_parity_error; + SueSource; +}; + +actionclass mem_port_failure +{ + all_dimm_H_memport_L; + threshold1; # Threshold 1 +}; + +################################################################################ # Analyze groups ################################################################################ -actionclass analyzeMB_LFIR { analyze(gMB_LFIR); }; +actionclass analyzeOCMB_LFIR { analyze(gOCMB_LFIR); }; actionclass analyzeMMIOFIR { analyze(gMMIOFIR); }; actionclass analyzeSRQFIR { analyze(gSRQFIR); }; actionclass analyzeMCBISTFIR { analyze(gMCBISTFIR); }; actionclass analyzeRDFFIR { analyze(gRDFFIR); }; actionclass analyzeTLXFIR { analyze(gTLXFIR); }; +actionclass analyzeTLXERR1 +{ + analyze(gTLX_ERR1_REPORT); + funccall("clearAndMaskTlxtRe"); +}; actionclass analyzeOMIDLFIR { analyze(gOMIDLFIR); }; diff --git a/src/usr/diag/prdf/common/plat/explorer/explorer_ocmb_regs.rule b/src/usr/diag/prdf/common/plat/explorer/explorer_ocmb_regs.rule index a4a526124..c2205f2dd 100644 --- a/src/usr/diag/prdf/common/plat/explorer/explorer_ocmb_regs.rule +++ b/src/usr/diag/prdf/common/plat/explorer/explorer_ocmb_regs.rule @@ -223,3 +223,259 @@ capture group never; access write_only; }; + + ############################################################################ + # P9 Hardware Mark Stores + ############################################################################ + + register HW_MS0 + { + name "P9 Hardware Mark Store rank 0"; + scomaddr 0x08011C10; + capture group default; + }; + + register HW_MS1 + { + name "P9 Hardware Mark Store rank 1"; + scomaddr 0x08011C11; + capture group default; + }; + + register HW_MS2 + { + name "P9 Hardware Mark Store rank 2"; + scomaddr 0x08011C12; + capture group default; + }; + + register HW_MS3 + { + name "P9 Hardware Mark Store rank 3"; + scomaddr 0x08011C13; + capture group default; + }; + + register HW_MS4 + { + name "P9 Hardware Mark Store rank 4"; + scomaddr 0x08011C14; + capture group default; + }; + + register HW_MS5 + { + name "P9 Hardware Mark Store rank 5"; + scomaddr 0x08011C15; + capture group default; + }; + + register HW_MS6 + { + name "P9 Hardware Mark Store rank 6"; + scomaddr 0x08011C16; + capture group default; + }; + + register HW_MS7 + { + name "P9 Hardware Mark Store rank 7"; + scomaddr 0x08011C17; + capture group default; + }; + + ############################################################################ + # P9 Firmware Mark Stores + ############################################################################ + + register FW_MS0 + { + name "P9 Firmware Mark Store 0"; + scomaddr 0x08011C18; + capture group default; + }; + + register FW_MS1 + { + name "P9 Firmware Mark Store 1"; + scomaddr 0x08011C19; + capture group default; + }; + + register FW_MS2 + { + name "P9 Firmware Mark Store 2"; + scomaddr 0x08011C1A; + capture group default; + }; + + register FW_MS3 + { + name "P9 Firmware Mark Store 3"; + scomaddr 0x08011C1B; + capture group default; + }; + + register FW_MS4 + { + name "P9 Firmware Mark Store 4"; + scomaddr 0x08011C1C; + capture group default; + }; + + register FW_MS5 + { + name "P9 Firmware Mark Store 5"; + scomaddr 0x08011C1D; + capture group default; + }; + + register FW_MS6 + { + name "P9 Firmware Mark Store 6"; + scomaddr 0x08011C1E; + capture group default; + }; + + register FW_MS7 + { + name "P9 Firmware Mark Store 7"; + scomaddr 0x08011C1F; + capture group default; + }; + + ########################################################################### + # P9 OCMB target OMIDLFIR + ########################################################################### + + register DL0_ERROR_HOLD + { + name "P9 OCMB target DL0 Error Hold Register"; + scomaddr 0x08012813; + capture group default; + }; + + ########################################################################### + # P9 OCMB target TLXFIR + ########################################################################### + + register TLXFIR_AND + { + name "Explorer chip TLXFIR AND"; + scomaddr 0x08012401; + capture group never; + access write_only; + }; + + register TLXFIR_MASK_OR + { + name "Explorer chip TLXFIR MASK OR"; + scomaddr 0x08012405; + capture group never; + access write_only; + }; + + register TLX_ERR1_REPORT + { + name "P9 OCMB target TLX Error Report Register"; + scomaddr 0x0801241D; + reset (&, 0x0801241D); + mask (|, 0x08012415); + capture group default; + }; + + register TLX_ERR1_REPORT_MASK + { + name "P9 OCMB target TLX Error Report Register Mask"; + scomaddr 0x08012415; + capture group default; + }; + + ############################################################################ + # Explorer ECC Address Registers + ############################################################################ + + register MBNCER + { + name "Explorer Mainline NCE Address Trap Register"; + scomaddr 0x0801186A; + capture group default; + }; + + register MBRCER + { + name "Explorer Mainline RCE Address Trap Register"; + scomaddr 0x0801186B; + capture group default; + }; + + register MBMPER + { + name "Explorer Mainline MPE Address Trap Register"; + scomaddr 0x0801186C; + capture group default; + }; + + register MBUER + { + name "Explorer Mainline UE Address Trap Register"; + scomaddr 0x0801186D; + capture group default; + }; + + register MBAUER + { + name "Explorer Mainline AUE Address Trap Register"; + scomaddr 0x0801186E; + capture group default; + }; + + ############################################################################ + # Misc + ############################################################################ + + register FARB0 + { + name "MB_SIM.SRQ.MBA_FARB0Q"; + scomaddr 0x08011415; + capture group default; + }; + + register EXP_MSR + { + name "Explorer Mark Shadow Register"; + scomaddr 0x08011C0C; + capture group default; + }; + + register MC_ADDR_TRANS + { + name "P9 OCMB target address translation register0"; + scomaddr 0x0801186F; + capture group default; + }; + + register MC_ADDR_TRANS1 + { + name "P9 OCMB target address translation register1"; + scomaddr 0x08011870; + capture group default; + }; + + register MC_ADDR_TRANS2 + { + name "P9 OCMB target address translation register2"; + scomaddr 0x08011871; + capture group default; + }; + + ############################################################################ + # Interrupt status register + ############################################################################ + + register INTER_STATUS_REG + { + name "TPTOP.PIB.PCBMS.INTERRUPT_TYPE_REG"; + scomaddr 0x000F001A; + capture group default; + }; diff --git a/src/usr/diag/prdf/common/plat/explorer/prdfExplorerPlugins_common.C b/src/usr/diag/prdf/common/plat/explorer/prdfExplorerPlugins_common.C new file mode 100644 index 000000000..de385aab9 --- /dev/null +++ b/src/usr/diag/prdf/common/plat/explorer/prdfExplorerPlugins_common.C @@ -0,0 +1,574 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/diag/prdf/common/plat/explorer/prdfExplorerPlugins_common.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +// Framework includes +#include <iipServiceDataCollector.h> +#include <prdfExtensibleChip.H> +#include <prdfPluginMap.H> + +// Platform includes +#include <prdfMemDbUtils.H> +#include <prdfMemEccAnalysis.H> +#include <prdfMemUtils.H> +#include <prdfPlatServices.H> + +using namespace TARGETING; + +namespace PRDF +{ + +using namespace PlatServices; + +namespace explorer_ocmb +{ + +//############################################################################## +// +// Special plugins +// +//############################################################################## + +/** + * @brief Plugin that initializes the data bundle. + * @param i_chip An OCMB chip. + * @return SUCCESS + */ +int32_t Initialize( ExtensibleChip * i_chip ) +{ + i_chip->getDataBundle() = new OcmbDataBundle( i_chip ); + return SUCCESS; +} +PRDF_PLUGIN_DEFINE( explorer_ocmb, Initialize ); + +/** + * @brief Plugin function called after analysis is complete but before PRD + * exits. + * @param i_chip An OCMB chip. + * @param io_sc The step code data struct. + * @note This is especially useful for any analysis that still needs to be + * done after the framework clears the FIR bits that were at attention. + * @return SUCCESS. + */ +int32_t PostAnalysis( ExtensibleChip * i_chip, STEP_CODE_DATA_STRUCT & io_sc ) +{ + #define PRDF_FUNC "[explorer_ocmb::PostAnalysis] " + + #ifdef __HOSTBOOT_RUNTIME + + // If the IUE threshold in our data bundle has been reached, we trigger + // a port fail. Once we trigger the port fail, the system may crash + // right away. Since PRD is running in the hypervisor, it is possible we + // may not get the error log. To better our chances, we trigger the port + // fail here after the error log has been committed. + if ( MemEcc::queryIueTh<TYPE_OCMB_CHIP>(i_chip, io_sc) ) + { + if ( SUCCESS != MemEcc::triggerPortFail<TYPE_OCMB_CHIP>(i_chip) ) + { + PRDF_ERR( PRDF_FUNC "triggerPortFail(0x%08x) failed", + i_chip->getHuid() ); + } + } + + #endif // __HOSTBOOT_RUNTIME + + // Cleanup processor FIR bits on the other side of the channel. + MemUtils::cleanupChnlAttns<TYPE_OCMB_CHIP>( i_chip, io_sc ); + + return SUCCESS; + + #undef PRDF_FUNC +} +PRDF_PLUGIN_DEFINE( explorer_ocmb, PostAnalysis ); + + +//############################################################################## +// +// OCMB_LFIR +// +//############################################################################## + +/** + * @brief OCMB_LFIR[38] - DDR4 PHY interrupt + * @param i_chip An OCMB chip. + * @param io_sc The step code data struct. + * @return SUCCESS + */ +int32_t Ddr4PhyInterrupt( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + #define PRDF_FUNC "[explorer_ocmb::Ddr4PhyInterrupt] " + + SCAN_COMM_REGISTER_CLASS * rdffir = i_chip->getRegister( "RDFFIR" ); + + // If Mainline UE (RDFFIR[14]) or Maint UE (RDFFIR[34]) are on at the same + // time as this: + if ( rdffir->IsBitSet(14) || rdffir->IsBitSet(34) ) + { + // callout Explorer on 1st + io_sc.service_data->SetThresholdMaskId(0); + + // mask maint and mainline UE which are assumed to be side-effects + SCAN_COMM_REGISTER_CLASS * rdffir_mask_or = + i_chip->getRegister( "RDFFIR_MASK_OR" ); + + rdffir_mask_or->SetBit(14); + rdffir_mask_or->SetBit(34); + + if ( SUCCESS != rdffir_mask_or->Write() ) + { + PRDF_ERR( PRDF_FUNC "Write() failed on RDFFIR_MASK_OR: 0x%08x", + i_chip->getHuid() ); + } + } + else + { + //TODO RTC 200583 + // callout Explorer on threshold (5/day) + // NOTE: in this case we will have to clear both hw driven checkers + // manually before clearing the FIR + } + + return SUCCESS; + + #undef PRDF_FUNC +} +PRDF_PLUGIN_DEFINE( explorer_ocmb, Ddr4PhyInterrupt ); + +//------------------------------------------------------------------------------ + +/** + * @brief OCMB_LFIR[39:46] - Foxhound Fatal + * @param i_chip An OCMB chip. + * @param io_sc The step code data struct. + * @return SUCCESS + */ +int32_t FoxhoundFatal( ExtensibleChip * i_chip, STEP_CODE_DATA_STRUCT & io_sc ) +{ + #define PRDF_FUNC "[explorer_ocmb::FoxhoundFatal] " + + //TODO RTC 200583 + + return SUCCESS; + + #undef PRDF_FUNC +} +PRDF_PLUGIN_DEFINE( explorer_ocmb, FoxhoundFatal ); + +//############################################################################## +// +// OMIDLFIR +// +//############################################################################## + +/** + * @brief OMIDLFIR[0] - OMI-DL0 Fatal Error + * @param i_chip An OCMB chip. + * @param io_sc The step code data struct. + * @return PRD_SCAN_COMM_REGISTER_ZERO for the bus callout, else SUCCESS + */ +int32_t DlFatalError( ExtensibleChip * i_chip, STEP_CODE_DATA_STRUCT & io_sc ) +{ + #define PRDF_FUNC "[explorer_ocmb::DlFatalError] " + + int32_t rc = SUCCESS; + + do + { + // Check DL0_ERROR_HOLD[52:63] to determine callout + SCAN_COMM_REGISTER_CLASS * dl0_error_hold = + i_chip->getRegister( "DL0_ERROR_HOLD" ); + + if ( SUCCESS != dl0_error_hold->Read() ) + { + PRDF_ERR( PRDF_FUNC "Read() Failed on DL0_ERROR_HOLD: " + "i_chip=0x%08x", i_chip->getHuid() ); + break; + } + + if ( dl0_error_hold->IsBitSet(53) || + dl0_error_hold->IsBitSet(55) || + dl0_error_hold->IsBitSet(57) || + dl0_error_hold->IsBitSet(58) || + dl0_error_hold->IsBitSet(59) || + dl0_error_hold->IsBitSet(60) || + dl0_error_hold->IsBitSet(62) || + dl0_error_hold->IsBitSet(63) ) + { + // callout OCMB + io_sc.service_data->SetCallout( i_chip->getTrgt() ); + } + else if ( dl0_error_hold->IsBitSet(54) || + dl0_error_hold->IsBitSet(56) || + dl0_error_hold->IsBitSet(61) ) + { + // callout the OMI target, the OMI bus, and the OCMB. + // Return PRD_SCAN_COMM_REGISTER_ZERO so the rule code knows to + // make the correct callout. + rc = PRD_SCAN_COMM_REGISTER_ZERO; + } + + }while(0); + + return rc; + + #undef PRDF_FUNC +} +PRDF_PLUGIN_DEFINE( explorer_ocmb, DlFatalError ); + +//############################################################################## +// +// RDFFIR +// +//############################################################################## + +/** + * @brief Adds all attached DIMMs at HIGH priority. + * @param i_chip An OCMB chip. + * @param io_sc The step code data struct. + * @return SUCCESS + */ +int32_t CalloutAttachedDimmsHigh( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + for ( auto & dimm : getConnected(i_chip->getTrgt(), TYPE_DIMM) ) + io_sc.service_data->SetCallout( dimm, MRU_HIGH ); + + return SUCCESS; // nothing to return to rule code +} +PRDF_PLUGIN_DEFINE( explorer_ocmb, CalloutAttachedDimmsHigh ); + +//------------------------------------------------------------------------------ + +/** + * @brief RDF RCD Parity Error + * @param i_chip An OCMB chip. + * @param io_sc The step code data struct. + * @return SUCCESS + */ +int32_t RdfRcdParityError( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + #define PRDF_FUNC "[explorer_ocmb::RdfRcdParityError] " + + do + { + SCAN_COMM_REGISTER_CLASS * rdffir = i_chip->getRegister( "RDFFIR" ); + if ( SUCCESS != rdffir->Read() ) + { + PRDF_ERR( PRDF_FUNC "Read() Failed on RDFFIR: " + "i_chip=0x%08x", i_chip->getHuid() ); + break; + } + + // If RDFFIR[40] on at the same time, this is 'missing rddata valid' + // case, which returns SUE + if ( rdffir->IsBitSet(40) ) + { + // callout MEM_PORT on 1st occurrence + TargetHandle_t memPort = + getConnectedChild( i_chip->getTrgt(), TYPE_MEM_PORT, 0 ); + io_sc.service_data->SetCallout( memPort ); + } + // Else this is 'confirmed RCD parity error' case + else + { + // callout DIMM high priority, MEM_PORT low on 1st occurrence + CalloutAttachedDimmsHigh( i_chip, io_sc ); + TargetHandle_t memPort = + getConnectedChild( i_chip->getTrgt(), TYPE_MEM_PORT, 0 ); + io_sc.service_data->SetCallout( memPort, MRU_LOW ); + } + + // Mask bit 40 as well + SCAN_COMM_REGISTER_CLASS * rdffir_mask_or = + i_chip->getRegister( "RDFFIR_MASK_OR" ); + + rdffir_mask_or->SetBit(40); + if ( SUCCESS != rdffir_mask_or->Write() ) + { + PRDF_ERR( PRDF_FUNC "Write() Failed on RDFFIR_MASK_OR: " + "i_chip=0x%08x", i_chip->getHuid() ); + break; + } + + }while(0); + + return SUCCESS; + + #undef PRDF_FUNC +} +PRDF_PLUGIN_DEFINE( explorer_ocmb, RdfRcdParityError ); + +//------------------------------------------------------------------------------ + +/** + * @brief RDFFIR[0:7] - Mainline MPE. + * @param i_chip OCMB chip. + * @param io_sc The step code data struct. + * @return SUCCESS + */ +#define PLUGIN_FETCH_MPE_ERROR( RANK ) \ +int32_t AnalyzeFetchMpe_##RANK( ExtensibleChip * i_chip, \ + STEP_CODE_DATA_STRUCT & io_sc ) \ +{ \ + MemRank rank ( RANK ); \ + MemEcc::analyzeFetchMpe<TYPE_OCMB_CHIP>( i_chip, rank, io_sc ); \ + return SUCCESS; \ +} \ +PRDF_PLUGIN_DEFINE( explorer_ocmb, AnalyzeFetchMpe_##RANK ); + +PLUGIN_FETCH_MPE_ERROR( 0 ) +PLUGIN_FETCH_MPE_ERROR( 1 ) +PLUGIN_FETCH_MPE_ERROR( 2 ) +PLUGIN_FETCH_MPE_ERROR( 3 ) +PLUGIN_FETCH_MPE_ERROR( 4 ) +PLUGIN_FETCH_MPE_ERROR( 5 ) +PLUGIN_FETCH_MPE_ERROR( 6 ) +PLUGIN_FETCH_MPE_ERROR( 7 ) + +#undef PLUGIN_FETCH_MPE_ERROR + +//------------------------------------------------------------------------------ + +/** + * @brief RDFFIR[8:9] - Mainline NCE and/or TCE. + * @param i_chip OCMB chip. + * @param io_sc The step code data struct. + * @return SUCCESS + */ +int32_t AnalyzeFetchNceTce( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + MemEcc::analyzeFetchNceTce<TYPE_OCMB_CHIP>( i_chip, io_sc ); + return SUCCESS; // nothing to return to rule code +} +PRDF_PLUGIN_DEFINE( explorer_ocmb, AnalyzeFetchNceTce ); + +//------------------------------------------------------------------------------ + +/** + * @brief RDFFIR[14] - Mainline UE. + * @param i_chip OCMB chip. + * @param io_sc The step code data struct. + * @return SUCCESS + */ +int32_t AnalyzeFetchUe( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + MemEcc::analyzeFetchUe<TYPE_OCMB_CHIP>( i_chip, io_sc ); + return SUCCESS; // nothing to return to rule code +} +PRDF_PLUGIN_DEFINE( explorer_ocmb, AnalyzeFetchUe ); + +//------------------------------------------------------------------------------ + +/** + * @brief RDFFIR[17] - Mainline read IUE. + * @param i_chip OCMB chip. + * @param io_sc The step code data struct. + * @return PRD_NO_CLEAR_FIR_BITS if IUE threshold is reached, else SUCCESS. + */ +int32_t AnalyzeMainlineIue( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + int32_t rc = SUCCESS; + MemEcc::analyzeMainlineIue<TYPE_OCMB_CHIP>( i_chip, io_sc ); + + #ifdef __HOSTBOOT_MODULE + + if ( MemEcc::queryIueTh<TYPE_OCMB_CHIP>(i_chip, io_sc) ) + rc = PRD_NO_CLEAR_FIR_BITS; + + #endif + + return rc; // nothing to return to rule code +} +PRDF_PLUGIN_DEFINE( explorer_ocmb, AnalyzeMainlineIue ); + +//------------------------------------------------------------------------------ + +/** + * @brief RDFFIR[37] - Maint IUE. + * @param i_chip OCMB chip. + * @param io_sc The step code data struct. + * @return PRD_NO_CLEAR_FIR_BITS if IUE threshold is reached, else SUCCESS. + */ +int32_t AnalyzeMaintIue( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + int32_t rc = SUCCESS; + MemEcc::analyzeMaintIue<TYPE_OCMB_CHIP>( i_chip, io_sc ); + + #ifdef __HOSTBOOT_MODULE + + if ( MemEcc::queryIueTh<TYPE_OCMB_CHIP>(i_chip, io_sc) ) + rc = PRD_NO_CLEAR_FIR_BITS; + + #endif + + return rc; // nothing to return to rule code +} +PRDF_PLUGIN_DEFINE( explorer_ocmb, AnalyzeMaintIue ); + +//------------------------------------------------------------------------------ + +/** + * @brief RDFFIR[19,39] - Mainline and Maint IMPE + * @param i_chip OCMB chip. + * @param io_sc The step code data struct. + * @return SUCCESS + */ +int32_t AnalyzeImpe( ExtensibleChip * i_chip, STEP_CODE_DATA_STRUCT & io_sc ) +{ + MemEcc::analyzeImpe<TYPE_OCMB_CHIP>( i_chip, io_sc ); + return SUCCESS; // nothing to return to rule code +} +PRDF_PLUGIN_DEFINE( explorer_ocmb, AnalyzeImpe ); + +//------------------------------------------------------------------------------ + +/** + * @brief RDFFIR[13,16] - Mainline AUE and IAUE + * @param i_chip OCMB chip. + * @param io_sc The step code data struct. + * @return SUCCESS + */ +int32_t AnalyzeFetchAueIaue( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + #define PRDF_FUNC "[explorer_ocmb::AnalyzeFetchAueIaue] " + + MemAddr addr; + if ( SUCCESS != getMemReadAddr<TYPE_OCMB_CHIP>(i_chip, + MemAddr::READ_AUE_ADDR, + addr) ) + { + PRDF_ERR( PRDF_FUNC "getMemReadAddr(0x%08x,READ_AUE_ADDR) failed", + i_chip->getHuid() ); + } + else + { + MemRank rank = addr.getRank(); + MemoryMru mm { i_chip->getTrgt(), rank, MemoryMruData::CALLOUT_RANK }; + io_sc.service_data->SetCallout( mm, MRU_HIGH ); + } + + return SUCCESS; // nothing to return to rule code + + #undef PRDF_FUNC +} +PRDF_PLUGIN_DEFINE( explorer_ocmb, AnalyzeFetchAueIaue ); + +//------------------------------------------------------------------------------ + +/** + * @brief RDFFIR[33] - Maintenance AUE + * @param i_chip OCMB chip. + * @param io_sc The step code data struct. + * @return SUCCESS + */ +int32_t AnalyzeMaintAue( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + #define PRDF_FUNC "[explorer_ocmb::AnalyzeMaintAue] " + + MemAddr addr; + if ( SUCCESS != getMemMaintAddr<TYPE_OCMB_CHIP>(i_chip, addr) ) + { + PRDF_ERR( PRDF_FUNC "getMemMaintAddr(0x%08x) failed", + i_chip->getHuid() ); + } + else + { + MemRank rank = addr.getRank(); + MemoryMru mm { i_chip->getTrgt(), rank, MemoryMruData::CALLOUT_RANK }; + io_sc.service_data->SetCallout( mm, MRU_HIGH ); + } + + return SUCCESS; // nothing to return to rule code + + #undef PRDF_FUNC +} +PRDF_PLUGIN_DEFINE( explorer_ocmb, AnalyzeMaintAue ); + + +//############################################################################## +// +// TLXFIR +// +//############################################################################## + +/** + * @brief Clear/Mask TLXFIR[9] + * @param i_chip An OCMB chip. + * @param io_sc The step code data struct. + * @return SUCCESS + */ +int32_t clearAndMaskTlxtRe( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + #define PRDF_FUNC "[explorer_ocmb::clearAndMaskTlxtRe] " + + do + { + // If we are at threshold, mask TLXFIR[9]. + if ( io_sc.service_data->IsAtThreshold() ) + { + SCAN_COMM_REGISTER_CLASS * tlxfir_mask_or = + i_chip->getRegister( "TLXFIR_MASK_OR" ); + + tlxfir_mask_or->SetBit(9); + if ( SUCCESS != tlxfir_mask_or->Write() ) + { + PRDF_ERR( PRDF_FUNC "Write() Failed on TLXFIR_MASK_OR: " + "i_chip=0x%08x", i_chip->getHuid() ); + break; + } + } + + // Clear TLXFIR[9] + SCAN_COMM_REGISTER_CLASS * tlxfir_and = + i_chip->getRegister( "TLXFIR_AND" ); + tlxfir_and->setAllBits(); + + tlxfir_and->ClearBit(9); + if ( SUCCESS != tlxfir_and->Write() ) + { + PRDF_ERR( PRDF_FUNC "Write() Failed on TLXFIR_AND: " + "i_chip=0x%08x", i_chip->getHuid() ); + break; + } + }while(0); + + return SUCCESS; + + #undef PRDF_FUNC +} +PRDF_PLUGIN_DEFINE( explorer_ocmb, clearAndMaskTlxtRe ); + +} // end namespace explorer_ocmb + +} // end namespace PRDF + diff --git a/src/usr/diag/prdf/common/plat/explorer/prdf_plat_explorer.mk b/src/usr/diag/prdf/common/plat/explorer/prdf_plat_explorer.mk new file mode 100644 index 000000000..b79d5cc30 --- /dev/null +++ b/src/usr/diag/prdf/common/plat/explorer/prdf_plat_explorer.mk @@ -0,0 +1,39 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/explorer/prdf_plat_explorer.mk $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2019 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +################################################################################ +# Paths common to both FSP and Hostboot +################################################################################ + +prd_vpath += ${PRD_SRC_PATH}/common/plat/explorer + +prd_incpath += ${PRD_SRC_PATH}/common/plat/explorer + +################################################################################ +# Object files common to both FSP and Hostboot +################################################################################ + +# rule plugin related +prd_rule_plugin += prdfExplorerPlugins_common.o diff --git a/src/usr/diag/prdf/common/plat/mem/prdfMemAddress.C b/src/usr/diag/prdf/common/plat/mem/prdfMemAddress.C index 1227afeb8..654b39ba0 100644 --- a/src/usr/diag/prdf/common/plat/mem/prdfMemAddress.C +++ b/src/usr/diag/prdf/common/plat/mem/prdfMemAddress.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -46,8 +46,8 @@ using namespace PlatServices; // Class MemAddr //------------------------------------------------------------------------------ -template<> -MemAddr MemAddr::fromReadAddr<TYPE_MCBIST>( uint64_t i_addr ) +template<TARGETING::TYPE T> +MemAddr MemAddr::fromReadAddr( uint64_t i_addr ) { uint64_t mrnk = (i_addr >> 59) & 0x7; // 2: 4 uint64_t srnk = (i_addr >> 56) & 0x7; // 5: 7 @@ -58,6 +58,12 @@ MemAddr MemAddr::fromReadAddr<TYPE_MCBIST>( uint64_t i_addr ) return MemAddr( MemRank(mrnk, srnk), bnk, row, col ); } +template +MemAddr MemAddr::fromReadAddr<TYPE_MCBIST>( uint64_t i_addr ); +template +MemAddr MemAddr::fromReadAddr<TYPE_OCMB_CHIP>( uint64_t i_addr ); + + template<> MemAddr MemAddr::fromReadAddr<TYPE_MEMBUF>( uint64_t i_addr ) { @@ -73,8 +79,8 @@ MemAddr MemAddr::fromReadAddr<TYPE_MEMBUF>( uint64_t i_addr ) return MemAddr( MemRank(mrnk, srnk), bnk, row, col ); } -template<> -MemAddr MemAddr::fromMaintAddr<TYPE_MCBIST>( uint64_t i_addr ) +template<TARGETING::TYPE T> +MemAddr MemAddr::fromMaintAddr( uint64_t i_addr ) { uint64_t rslct = (i_addr >> 59) & 0x3; // 3: 4 uint64_t srnk = (i_addr >> 56) & 0x7; // 5: 7 @@ -88,6 +94,12 @@ MemAddr MemAddr::fromMaintAddr<TYPE_MCBIST>( uint64_t i_addr ) return MemAddr( MemRank(mrnk, srnk), bnk, row, col ); } +template +MemAddr MemAddr::fromMaintAddr<TYPE_MCBIST>( uint64_t i_addr ); +template +MemAddr MemAddr::fromMaintAddr<TYPE_OCMB_CHIP>( uint64_t i_addr ); + + template<> MemAddr MemAddr::fromMaintAddr<TYPE_MBA>( uint64_t i_addr ) { @@ -169,6 +181,53 @@ uint32_t getMemReadAddr<TYPE_MCBIST>( ExtensibleChip * i_chip, uint32_t i_pos, //------------------------------------------------------------------------------ template<> +uint32_t getMemReadAddr<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + MemAddr::ReadReg i_reg, + MemAddr & o_addr ) +{ + #define PRDF_FUNC "[getMemReadAddr<TYPE_OCMB_CHIP>] " + + uint32_t o_rc = SUCCESS; + + // Check parameters + PRDF_ASSERT( nullptr != i_chip ); + PRDF_ASSERT( TYPE_OCMB_CHIP == i_chip->getType() ); + + // Get the register string. + const char * reg_str = ""; + switch ( i_reg ) + { + case MemAddr::READ_NCE_ADDR: reg_str = "MBNCER"; break; + case MemAddr::READ_RCE_ADDR: reg_str = "MBRCER"; break; + case MemAddr::READ_MPE_ADDR: reg_str = "MBMPER"; break; + case MemAddr::READ_UE_ADDR : reg_str = "MBUER" ; break; + case MemAddr::READ_AUE_ADDR: reg_str = "MBAUER"; break; + default: PRDF_ASSERT( false ); + } + + // Read the address register + SCAN_COMM_REGISTER_CLASS * reg = i_chip->getRegister( reg_str ); + o_rc = reg->Read(); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "Read() failed on %s: i_chip=0x%08x", + reg_str, i_chip->getHuid() ); + } + else + { + // Get the address object. + uint64_t addr = reg->GetBitFieldJustified( 0, 64 ); + o_addr = MemAddr::fromReadAddr<TYPE_OCMB_CHIP>( addr ); + } + + return o_rc; + + #undef PRDF_FUNC +} + +//------------------------------------------------------------------------------ + +template<> uint32_t getMemReadAddr<TYPE_MEMBUF>( ExtensibleChip * i_chip, uint32_t i_pos, MemAddr::ReadReg i_reg, MemAddr & o_addr ) { @@ -247,15 +306,14 @@ uint32_t getMemReadAddr<TYPE_MBA>( ExtensibleChip * i_chip, //------------------------------------------------------------------------------ -template<> -uint32_t getMemMaintAddr<TYPE_MCBIST>( ExtensibleChip * i_chip, - MemAddr & o_addr ) +template<TARGETING::TYPE T> +uint32_t getMemMaintAddr( ExtensibleChip * i_chip, MemAddr & o_addr ) { - #define PRDF_FUNC "[getMemMaintAddr<TYPE_MCBIST>] " + #define PRDF_FUNC "[getMemMaintAddr<T>] " // Check parameters PRDF_ASSERT( nullptr != i_chip ); - PRDF_ASSERT( TYPE_MCBIST == i_chip->getType() ); + PRDF_ASSERT( T == i_chip->getType() ); // Read the address register SCAN_COMM_REGISTER_CLASS * reg = i_chip->getRegister( "MCBMCAT" ); @@ -269,7 +327,7 @@ uint32_t getMemMaintAddr<TYPE_MCBIST>( ExtensibleChip * i_chip, { // Get the address object. uint64_t addr = reg->GetBitFieldJustified( 0, 64 ); - o_addr = MemAddr::fromMaintAddr<TYPE_MCBIST>( addr ); + o_addr = MemAddr::fromMaintAddr<T>( addr ); } return o_rc; @@ -277,6 +335,13 @@ uint32_t getMemMaintAddr<TYPE_MCBIST>( ExtensibleChip * i_chip, #undef PRDF_FUNC } +template +uint32_t getMemMaintAddr<TYPE_MCBIST>( ExtensibleChip * i_chip, + MemAddr & o_addr ); +template +uint32_t getMemMaintAddr<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + MemAddr & o_addr ); + //------------------------------------------------------------------------------ template<> @@ -389,8 +454,9 @@ uint32_t getMemMaintEndAddr<TYPE_MBA>( ExtensibleChip * i_chip, #ifdef __HOSTBOOT_MODULE -uint32_t getMcbistMaintPort( ExtensibleChip * i_mcbChip, - std::vector<ExtensibleChip *> & o_mcaList ) +template<> +uint32_t getMcbistMaintPort<TYPE_MCBIST>( ExtensibleChip * i_mcbChip, + ExtensibleChipList & o_mcaList ) { #define PRDF_FUNC "[getMcbistMaintPort] " @@ -402,9 +468,9 @@ uint32_t getMcbistMaintPort( ExtensibleChip * i_mcbChip, o_mcaList.clear(); - SCAN_COMM_REGISTER_CLASS * mcbagra = i_mcbChip->getRegister( "MCBAGRA" ); - SCAN_COMM_REGISTER_CLASS * mcbmcat = i_mcbChip->getRegister( "MCBMCAT" ); - SCAN_COMM_REGISTER_CLASS * mcb_cntl = i_mcbChip->getRegister( "MCB_CNTL" ); + SCAN_COMM_REGISTER_CLASS * mcbagra = i_mcbChip->getRegister( "MCBAGRA" ); + SCAN_COMM_REGISTER_CLASS * mcbmcat = i_mcbChip->getRegister( "MCBMCAT" ); + SCAN_COMM_REGISTER_CLASS * mcb_cntl = i_mcbChip->getRegister( "MCB_CNTL" ); do { @@ -446,7 +512,7 @@ uint32_t getMcbistMaintPort( ExtensibleChip * i_mcbChip, } // Get MCAs from all targeted ports. - for ( uint8_t p = 0; p < 4; p++ ) + for ( uint8_t p = 0; p < MAX_MCA_PER_MCBIST; p++ ) { if ( 0 == (portMask & (0x8 >> p)) ) continue; diff --git a/src/usr/diag/prdf/common/plat/mem/prdfMemAddress.H b/src/usr/diag/prdf/common/plat/mem/prdfMemAddress.H index 8dc192672..f5120b3b5 100644 --- a/src/usr/diag/prdf/common/plat/mem/prdfMemAddress.H +++ b/src/usr/diag/prdf/common/plat/mem/prdfMemAddress.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -167,7 +167,7 @@ uint32_t getMemReadAddr( ExtensibleChip * i_chip, uint32_t i_pos, /** * @brief Reads the specified mainline memory read address from hardware. - * @param i_chip MCA or MBA. + * @param i_chip MCA, MBA, or OCMB. * @param i_reg The target address register. * @param o_addr The returned address from hardware. * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. @@ -189,7 +189,7 @@ uint32_t getMemReadAddr( ExtensibleChip * i_chip, MemAddr::ReadReg i_reg, * mode or not. Therefore, users must call getMcbistMaintPort() to get the port * information. * - * @param i_chip An MBA or MCBIST chip. + * @param i_chip An MBA, MCBIST, or OCMB chip. * @param o_addr The returned address from hardware. * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. */ @@ -228,11 +228,12 @@ uint32_t getMemMaintEndAddr( ExtensibleChip * i_chip, MemAddr & o_addr ); * * @note Only supported for MCBIST. * @param i_mcbChip An MCBIST chip. - * @param o_mcaList A list of all MCAs targeted by the command. + * @param o_portList A list of all MCAs targeted by the command. * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. */ +template<TARGETING::TYPE T> uint32_t getMcbistMaintPort( ExtensibleChip * i_mcbChip, - std::vector<ExtensibleChip *> & o_mcaList ); + ExtensibleChipList & o_portList ); #endif diff --git a/src/usr/diag/prdf/common/plat/mem/prdfMemCaptureData.C b/src/usr/diag/prdf/common/plat/mem/prdfMemCaptureData.C index ebef7ae29..4d55c7c50 100644 --- a/src/usr/diag/prdf/common/plat/mem/prdfMemCaptureData.C +++ b/src/usr/diag/prdf/common/plat/mem/prdfMemCaptureData.C @@ -39,6 +39,7 @@ #include <prdfCenMbaDataBundle.H> #include <prdfPlatServices.H> #include <prdfP9McaDataBundle.H> +#include <prdfOcmbDataBundle.H> #include <prdfMemRowRepair.H> @@ -65,8 +66,16 @@ void addExtMemMruData( const MemoryMru & i_memMru, errlHndl_t io_errl ) { TargetHandle_t trgt = i_memMru.getTrgt(); - // Get the DRAM width. - extMemMru.isX4Dram = isDramWidthX4( trgt ) ? 1 : 0; + if ( TYPE_OCMB_CHIP == getTargetType(trgt) ) + { + TargetHandle_t dimm = getConnectedDimm( trgt, i_memMru.getRank() ); + extMemMru.isX4Dram = isDramWidthX4( dimm ) ? 1 : 0; + } + else + { + // Get the DRAM width. + extMemMru.isX4Dram = isDramWidthX4( trgt ) ? 1 : 0; + } // Get the DIMM type. if ( TYPE_MBA == getTargetType(trgt) ) @@ -97,9 +106,9 @@ void addExtMemMruData( const MemoryMru & i_memMru, errlHndl_t io_errl ) { getDimmDqAttr<TYPE_DIMM>(partList[0], extMemMru.dqMapping); } - else if ( TYPE_MEM_PORT == getTargetType(trgt) ) + else if ( TYPE_OCMB_CHIP == getTargetType(trgt) ) { - getDimmDqAttr<TYPE_MEM_PORT>( trgt, extMemMru.dqMapping ); + getDimmDqAttr<TYPE_OCMB_CHIP>( trgt, extMemMru.dqMapping ); } else { @@ -172,7 +181,6 @@ void captureDramRepairsData( TARGETING::TargetHandle_t i_trgt, if( CEN_VPD_DIMM_SPARE_NO_SPARE != spareConfig ) data.header.isSpareDram = true; - // Iterate all ranks to get DRAM repair data for ( auto & rank : masterRanks ) { @@ -220,8 +228,11 @@ void captureDramRepairsData( TARGETING::TargetHandle_t i_trgt, if ( data.rankDataList.size() > 0 ) { data.header.rankCount = data.rankDataList.size(); - data.header.isEccSp = ( isDramWidthX4( i_trgt ) && - (TYPE_MBA == getTargetType(i_trgt)) ); + data.header.isEccSp = false; + if ( TYPE_MBA == getTargetType(i_trgt) ) + { + data.header.isEccSp = isDramWidthX4( i_trgt ); + } UtilMem dramStream; dramStream << data; @@ -459,6 +470,33 @@ void captureIueCounts<McaDataBundle*>( TARGETING::TargetHandle_t i_trgt, //------------------------------------------------------------------------------ template<> +void captureIueCounts<OcmbDataBundle*>( TARGETING::TargetHandle_t i_trgt, + OcmbDataBundle * i_db, + CaptureData & io_cd ) +{ + #ifdef __HOSTBOOT_MODULE + + uint8_t sz_capData = i_db->iv_iueTh.size()*2; + uint8_t capData[sz_capData] = {}; + uint8_t idx = 0; + + for ( auto & th_pair : i_db->iv_iueTh ) + { + capData[idx] = th_pair.first; + capData[idx+1] = th_pair.second.getCount(); + idx += 2; + } + + // Add data to capture data. + BitString bs ( sz_capData*8, (CPU_WORD *) &capData ); + io_cd.Add( i_trgt, Util::hashString("IUE_COUNTS"), bs ); + + #endif +} + +//------------------------------------------------------------------------------ + +template<> void addEccData<TYPE_MCA>( ExtensibleChip * i_chip, STEP_CODE_DATA_STRUCT & io_sc ) { @@ -497,6 +535,33 @@ void addEccData<TYPE_MCBIST>( ExtensibleChip * i_chip, } template<> +void addEccData<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + PRDF_ASSERT( TYPE_OCMB_CHIP == i_chip->getType() ); + + CaptureData & cd = io_sc.service_data->GetCaptureData(); + OcmbDataBundle * db = getOcmbDataBundle( i_chip ); + + TargetHandle_t ocmbTrgt = i_chip->getTrgt(); + + // Add DRAM repairs data from hardware. + captureDramRepairsData<TYPE_OCMB_CHIP>( ocmbTrgt, cd ); + + // Add DRAM repairs data from VPD. + captureDramRepairsVpd<TYPE_OCMB_CHIP>( ocmbTrgt, cd ); + + // Add IUE counts to capture data. + captureIueCounts<OcmbDataBundle*>( ocmbTrgt, db, cd ); + + // Add CE table to capture data. + db->iv_ceTable.addCapData( cd ); + + // Add UE table to capture data. + db->iv_ueTable.addCapData( cd ); +} + +template<> void addEccData<TYPE_MBA>( ExtensibleChip * i_chip, STEP_CODE_DATA_STRUCT & io_sc ) { @@ -558,6 +623,22 @@ void addEccData<TYPE_MBA>( TargetHandle_t i_trgt, errlHndl_t io_errl ) ErrDataService::AddCapData( cd, io_errl ); } +template<> +void addEccData<TYPE_OCMB_CHIP>( TargetHandle_t i_trgt, + errlHndl_t io_errl ) +{ + PRDF_ASSERT( TYPE_OCMB_CHIP == getTargetType(i_trgt) ); + + CaptureData cd; + + // Add DRAM repairs data from hardware. + captureDramRepairsData<TYPE_OCMB_CHIP>( i_trgt, cd ); + + // Add DRAM repairs data from VPD. + captureDramRepairsVpd<TYPE_OCMB_CHIP>( i_trgt, cd ); + + ErrDataService::AddCapData( cd, io_errl ); +} //------------------------------------------------------------------------------ diff --git a/src/usr/diag/prdf/common/plat/mem/prdfMemCeTable.C b/src/usr/diag/prdf/common/plat/mem/prdfMemCeTable.C index 16645586b..799e32e67 100644 --- a/src/usr/diag/prdf/common/plat/mem/prdfMemCeTable.C +++ b/src/usr/diag/prdf/common/plat/mem/prdfMemCeTable.C @@ -281,7 +281,7 @@ void MemCeTable<T>::addCapData( CaptureData & io_cd ) // Avoid linker errors with the template. template class MemCeTable<TYPE_MCA>; template class MemCeTable<TYPE_MBA>; -template class MemCeTable<TYPE_MEM_PORT>; +template class MemCeTable<TYPE_OCMB_CHIP>; //------------------------------------------------------------------------------ diff --git a/src/usr/diag/prdf/common/plat/mem/prdfMemDbUtils.H b/src/usr/diag/prdf/common/plat/mem/prdfMemDbUtils.H index 7605a82fa..80586976e 100644 --- a/src/usr/diag/prdf/common/plat/mem/prdfMemDbUtils.H +++ b/src/usr/diag/prdf/common/plat/mem/prdfMemDbUtils.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -28,6 +28,8 @@ #include <prdfCenMbaDataBundle.H> #include <prdfP9McaDataBundle.H> +#include <prdfOcmbDataBundle.H> +#include <prdfTargetServices.H> namespace PRDF { @@ -62,6 +64,16 @@ uint32_t addCeTableEntry<TARGETING::TYPE_MCA>( ExtensibleChip * i_chip, } template<> inline +uint32_t addCeTableEntry<TARGETING::TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + const MemAddr & i_addr, + const MemSymbol & i_symbol, + bool i_isHard ) +{ + return getOcmbDataBundle(i_chip)->iv_ceTable.addEntry( i_addr, i_symbol, + i_isHard ); +} + +template<> inline uint32_t addCeTableEntry<TARGETING::TYPE_MBA>( ExtensibleChip * i_chip, const MemAddr & i_addr, const MemSymbol & i_symbol, @@ -91,6 +103,14 @@ void addUeTableEntry<TARGETING::TYPE_MCA>( ExtensibleChip * i_chip, } template<> inline +void addUeTableEntry<TARGETING::TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + UE_TABLE::Type i_type, + const MemAddr & i_addr ) +{ + getOcmbDataBundle(i_chip)->iv_ueTable.addEntry( i_type, i_addr ); +} + +template<> inline void addUeTableEntry<TARGETING::TYPE_MBA>( ExtensibleChip * i_chip, UE_TABLE::Type i_type, const MemAddr & i_addr ) @@ -118,6 +138,14 @@ void resetEccFfdc<TARGETING::TYPE_MCA>( ExtensibleChip * i_chip, } template<> inline +void resetEccFfdc<TARGETING::TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + const MemRank & i_rank, + AddrRangeType i_type ) +{ + getOcmbDataBundle(i_chip)->iv_ceTable.deactivateRank( i_rank, i_type ); +} + +template<> inline void resetEccFfdc<TARGETING::TYPE_MBA>( ExtensibleChip * i_chip, const MemRank & i_rank, AddrRangeType i_type ) @@ -134,7 +162,7 @@ void resetEccFfdc<TARGETING::TYPE_MBA>( ExtensibleChip * i_chip, /** * @brief Generic wrapper to push a TdEntry to the Targeted Diagnostics queue. - * @param i_chip MCA or MBA. + * @param i_chip MCA, MBA, or MEM_PORT. * @param i_entry The new TdEntry. * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. */ @@ -155,6 +183,13 @@ void pushToQueue<TARGETING::TYPE_MBA>( ExtensibleChip * i_chip, getMbaDataBundle(i_chip)->getTdCtlr()->pushToQueue( i_entry ); } +template<> inline +void pushToQueue<TARGETING::TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + TdEntry * i_entry ) +{ + getOcmbDataBundle(i_chip)->getTdCtlr()->pushToQueue( i_entry ); +} + #endif // Hostboot IPL/Runtime //############################################################################## @@ -179,6 +214,13 @@ MemIplCeStats<TARGETING::TYPE_MCA> * getIplCeStats( ExtensibleChip * i_chip ) } template<> inline +MemIplCeStats<TARGETING::TYPE_OCMB_CHIP> * getIplCeStats( + ExtensibleChip * i_chip ) +{ + return getOcmbDataBundle(i_chip)->getIplCeStats(); +} + +template<> inline MemIplCeStats<TARGETING::TYPE_MBA> * getIplCeStats( ExtensibleChip * i_chip ) { return getMbaDataBundle(i_chip)->getIplCeStats(); @@ -211,6 +253,13 @@ uint32_t handleTdEvent<TARGETING::TYPE_MCA>( ExtensibleChip * i_chip, } template<> inline +uint32_t handleTdEvent<TARGETING::TYPE_OCMB_CHIP>(ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc) +{ + return getOcmbDataBundle(i_chip)->getTdCtlr()->handleTdEvent( io_sc ); +} + +template<> inline uint32_t handleTdEvent<TARGETING::TYPE_MBA>( ExtensibleChip * i_chip, STEP_CODE_DATA_STRUCT & io_sc ) { @@ -242,6 +291,16 @@ void banTps<TARGETING::TYPE_MBA>( ExtensibleChip * i_chip, getMbaDataBundle(i_chip)->getTdCtlr()->banTps( i_chip, i_rank ); } +template<> inline +void banTps<TARGETING::TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + const MemRank & i_rank ) +{ + // Ban TPS on this rank. + getOcmbDataBundle(i_chip)->getTdCtlr()->banTps( i_chip, i_rank ); + // Permanently mask mainline NCEs and TCEs because of the TPS ban. + getOcmbDataBundle(i_chip)->iv_maskMainlineNceTce = true; +} + #endif // Hostboot Runtime only } // end namespace MemDbUtils diff --git a/src/usr/diag/prdf/common/plat/mem/prdfMemDqBitmap.C b/src/usr/diag/prdf/common/plat/mem/prdfMemDqBitmap.C index 308e25dab..5db522818 100644 --- a/src/usr/diag/prdf/common/plat/mem/prdfMemDqBitmap.C +++ b/src/usr/diag/prdf/common/plat/mem/prdfMemDqBitmap.C @@ -450,6 +450,9 @@ std::vector<MemSymbol> MemDqBitmap::getSymbolList( uint8_t i_portSlct ) case TYPE_MEM_PORT: symbol = dq2Symbol<TYPE_MEM_PORT>( dq, i_portSlct ); break; + case TYPE_OCMB_CHIP: + symbol = dq2Symbol<TYPE_OCMB_CHIP>(dq, i_portSlct); + break; default: PRDF_ERR( "Invalid trgt type" ); PRDF_ASSERT( false ); @@ -700,7 +703,7 @@ uint32_t MemDqBitmap::setEccSpare( uint8_t i_pins ) // Utility Functions //############################################################################## -uint32_t setDramInVpd( ExtensibleChip * i_chip, const MemRank & i_rank, +uint32_t setDramInVpd( TargetHandle_t i_trgt, const MemRank & i_rank, MemSymbol i_symbol ) { #define PRDF_FUNC "[MemDqBitmap::__setDramInVpd] " @@ -709,14 +712,12 @@ uint32_t setDramInVpd( ExtensibleChip * i_chip, const MemRank & i_rank, do { - TARGETING::TargetHandle_t trgt = i_chip->getTrgt(); - MemDqBitmap dqBitmap; - o_rc = getBadDqBitmap( trgt, i_rank, dqBitmap ); + o_rc = getBadDqBitmap( i_trgt, i_rank, dqBitmap ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "getBadDqBitmap(0x%08x, 0x%02x) failed.", - getHuid(trgt), i_rank.getKey() ); + getHuid(i_trgt), i_rank.getKey() ); break; } @@ -727,11 +728,11 @@ uint32_t setDramInVpd( ExtensibleChip * i_chip, const MemRank & i_rank, break; } - o_rc = setBadDqBitmap( trgt, i_rank, dqBitmap ); + o_rc = setBadDqBitmap( i_trgt, i_rank, dqBitmap ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "setBadDqBitmap(0x%08x, 0x%02x) failed.", - getHuid(trgt), i_rank.getKey() ); + getHuid(i_trgt), i_rank.getKey() ); break; } }while(0); @@ -743,7 +744,7 @@ uint32_t setDramInVpd( ExtensibleChip * i_chip, const MemRank & i_rank, //------------------------------------------------------------------------------ -uint32_t clearDramInVpd( ExtensibleChip * i_chip, const MemRank & i_rank, +uint32_t clearDramInVpd( TargetHandle_t i_trgt, const MemRank & i_rank, MemSymbol i_symbol ) { #define PRDF_FUNC "[MemDqBitmap::__clearDramInVpd] " @@ -752,14 +753,12 @@ uint32_t clearDramInVpd( ExtensibleChip * i_chip, const MemRank & i_rank, do { - TARGETING::TargetHandle_t trgt = i_chip->getTrgt(); - MemDqBitmap dqBitmap; - o_rc = getBadDqBitmap( trgt, i_rank, dqBitmap ); + o_rc = getBadDqBitmap( i_trgt, i_rank, dqBitmap ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "getBadDqBitmap(0x%08x, 0x%02x) failed.", - getHuid(trgt), i_rank.getKey() ); + getHuid(i_trgt), i_rank.getKey() ); break; } @@ -770,11 +769,11 @@ uint32_t clearDramInVpd( ExtensibleChip * i_chip, const MemRank & i_rank, break; } - o_rc = setBadDqBitmap( trgt, i_rank, dqBitmap ); + o_rc = setBadDqBitmap( i_trgt, i_rank, dqBitmap ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "setBadDqBitmap(0x%08x, 0x%02x) failed.", - getHuid(trgt), i_rank.getKey() ); + getHuid(i_trgt), i_rank.getKey() ); break; } }while(0); diff --git a/src/usr/diag/prdf/common/plat/mem/prdfMemDqBitmap.H b/src/usr/diag/prdf/common/plat/mem/prdfMemDqBitmap.H index b407d9835..c3648dbc5 100644 --- a/src/usr/diag/prdf/common/plat/mem/prdfMemDqBitmap.H +++ b/src/usr/diag/prdf/common/plat/mem/prdfMemDqBitmap.H @@ -73,7 +73,22 @@ class MemDqBitmap /** @brief Constructor from components */ MemDqBitmap( TARGETING::TargetHandle_t i_trgt, const MemRank & i_rank, BitmapData i_d ) : iv_trgt(i_trgt), iv_rank(i_rank), - iv_x4Dram(PlatServices::isDramWidthX4(i_trgt)), iv_data(i_d){} + iv_x4Dram(true), iv_data(i_d) + { + if ( TARGETING::TYPE_MEM_PORT == PlatServices::getTargetType(iv_trgt) || + TARGETING::TYPE_OCMB_CHIP == + PlatServices::getTargetType(iv_trgt) ) + { + // TODO RTC 210072 - Support multiple ports + TARGETING::TargetHandle_t dimm = + PlatServices::getConnectedDimm( iv_trgt, iv_rank ); + iv_x4Dram = PlatServices::isDramWidthX4( dimm ); + } + else + { + iv_x4Dram = PlatServices::isDramWidthX4( iv_trgt ); + } + } public: // functions @@ -224,7 +239,7 @@ class MemDqBitmap private: // instance variables - TARGETING::TargetHandle_t iv_trgt; ///< Target MBA/MCA/MEM_PORT + TARGETING::TargetHandle_t iv_trgt; ///< Target MBA/MCA/MEM_PORT/OCMB_CHIP MemRank iv_rank; ///< Target rank bool iv_x4Dram; ///< TRUE if iv_trgt uses x4 DRAMs @@ -238,20 +253,21 @@ class MemDqBitmap /** * @brief Sets the inputted dram in DRAM repairs VPD. - * @param i_chip MBA or MCA chip. + * @param i_trgt MBA, MCA, MEM_PORT, or OCMB chip. * @param i_rank Target rank. * @return Non-SUCCESS if an internal function fails. SUCCESS otherwise. */ -uint32_t setDramInVpd( ExtensibleChip * i_chip, const MemRank & i_rank, +uint32_t setDramInVpd( TARGETING::TargetHandle_t i_trgt, const MemRank & i_rank, MemSymbol i_symbol ); /** * @brief Clears the inputted dram in DRAM repairs VPD. - * @param i_chip MBA or MCA chip. + * @param i_trgt MBA, MCA, MEM_PORT, or OCMB chip. * @param i_rank Target rank. * @return Non-SUCCESS if an internal function fails. SUCCESS otherwise. */ -uint32_t clearDramInVpd( ExtensibleChip * i_chip, const MemRank & i_rank, +uint32_t clearDramInVpd( TARGETING::TargetHandle_t i_trgt, + const MemRank & i_rank, MemSymbol i_symbol ); } // end namespace PRDF diff --git a/src/usr/diag/prdf/common/plat/mem/prdfMemEccAnalysis.C b/src/usr/diag/prdf/common/plat/mem/prdfMemEccAnalysis.C index 9869a8c08..f206a074e 100644 --- a/src/usr/diag/prdf/common/plat/mem/prdfMemEccAnalysis.C +++ b/src/usr/diag/prdf/common/plat/mem/prdfMemEccAnalysis.C @@ -127,6 +127,87 @@ uint32_t handleMemUe<TYPE_MCA>( ExtensibleChip * i_chip, const MemAddr & i_addr, i_chip->getHuid(), i_type ); break; } + + #ifdef __HOSTBOOT_RUNTIME + // Increment the UE counter and store the rank we're on, resetting + // the UE and CE counts if we have stopped on a new rank. + ExtensibleChip * mcb = getConnectedParent( i_chip, TYPE_MCBIST ); + McbistDataBundle * mcbdb = getMcbistDataBundle(mcb); + if ( mcbdb->iv_ceUeRank != i_addr.getRank() ) + { + mcbdb->iv_ceStopCounter.reset(); + mcbdb->iv_ueStopCounter.reset(); + } + mcbdb->iv_ueStopCounter.inc( io_sc ); + mcbdb->iv_ceUeRank = i_addr.getRank(); + #endif + } + + } while (0); + + return o_rc; + + #undef PRDF_FUNC +} + +template<> +uint32_t handleMemUe<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + const MemAddr & i_addr, + UE_TABLE::Type i_type, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + #define PRDF_FUNC "[MemEcc::handleMemUe<TYPE_OCMB_CHIP>] " + + PRDF_ASSERT( nullptr != i_chip ); + PRDF_ASSERT( TYPE_OCMB_CHIP == i_chip->getType() ); + + uint32_t o_rc = SUCCESS; + + do + { + // First check to see if this is a side-effect UE. + SCAN_COMM_REGISTER_CLASS * fir = i_chip->getRegister("OCMB_LFIR"); + o_rc = fir->Read(); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "Read() failed on OCMB_LFIR: i_chip=0x%08x", + i_chip->getHuid() ); + break; + } + + // Check OCMB_LFIR[38] to determine if this is a side-effect. + if ( fir->IsBitSet(38) ) + { + // This is a side-effect. Callout the OCMB. + PRDF_TRAC( PRDF_FUNC "Memory UE is side-effect of DDRPHY error" ); + io_sc.service_data->SetCallout( i_chip->getTrgt() ); + io_sc.service_data->setServiceCall(); + } + else + { + // Handle the memory UE. + o_rc = __handleMemUe<TYPE_OCMB_CHIP>( i_chip, i_addr, i_type, + io_sc ); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "__handleMemUe(0x%08x,%d) failed", + i_chip->getHuid(), i_type ); + break; + } + + #ifdef __HOSTBOOT_RUNTIME + // Increment the UE counter and store the rank we're on, resetting + // the UE and CE counts if we have stopped on a new rank. + OcmbDataBundle * ocmbdb = getOcmbDataBundle(i_chip); + if ( ocmbdb->iv_ceUeRank != i_addr.getRank() ) + { + ocmbdb->iv_ceStopCounter.reset(); + ocmbdb->iv_ueStopCounter.reset(); + } + ocmbdb->iv_ueStopCounter.inc( io_sc ); + ocmbdb->iv_ceUeRank = i_addr.getRank(); + #endif + } } while (0); @@ -328,6 +409,52 @@ uint32_t maskMemPort<TYPE_MCA>( ExtensibleChip * i_chip ) #undef PRDF_FUNC } +template<> +uint32_t maskMemPort<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip ) +{ + #define PRDF_FUNC "[MemEcc::maskMemPort<TYPE_OCMB_CHIP>] " + + PRDF_ASSERT( nullptr != i_chip ); + PRDF_ASSERT( TYPE_OCMB_CHIP == i_chip->getType() ); + + uint32_t o_rc = SUCCESS; + + do + { + // Mask all FIRs on the OCMB in the chiplet FIRs. + SCAN_COMM_REGISTER_CLASS * chipletMask = + i_chip->getRegister("OCMB_CHIPLET_FIR_MASK"); + SCAN_COMM_REGISTER_CLASS * chipletSpaMask = + i_chip->getRegister("OCMB_CHIPLET_SPA_FIR_MASK"); + + chipletMask->setAllBits(); + chipletSpaMask->setAllBits(); + + o_rc = chipletMask->Write() | chipletSpaMask->Write(); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "Write() failed on 0x%08x", i_chip->getHuid() ); + break; + } + + #ifdef __HOSTBOOT_RUNTIME + + // Dynamically deallocate the port. + if ( SUCCESS != MemDealloc::port<TYPE_OCMB_CHIP>( i_chip ) ) + { + PRDF_ERR( PRDF_FUNC "MemDealloc::port<TYPE_OCMB_CHIP>(0x%08x) " + "failed", i_chip->getHuid() ); + } + + #endif + + } while (0); + + return o_rc; + + #undef PRDF_FUNC +} + #endif // __HOSTBOOT_MODULE //------------------------------------------------------------------------------ @@ -390,6 +517,62 @@ uint32_t triggerPortFail<TYPE_MCA>( ExtensibleChip * i_chip ) #undef PRDF_FUNC } +template<> +uint32_t triggerPortFail<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip ) +{ + #define PRDF_FUNC "[MemEcc::triggerPortFail<TYPE_OCMB_CHIP>] " + + PRDF_ASSERT( nullptr != i_chip ); + PRDF_ASSERT( TYPE_OCMB_CHIP == i_chip->getType() ); + + uint32_t o_rc = SUCCESS; + + OcmbDataBundle * db = getOcmbDataBundle( i_chip ); + + do + { + // trigger a port fail + // set FARB0[59] - MBA_FARB0Q_CFG_INJECT_PARITY_ERR_CONSTANT and + // FARB0[40] - MBA_FARB0Q_CFG_INJECT_PARITY_ERR_ADDR5 + SCAN_COMM_REGISTER_CLASS * farb0 = i_chip->getRegister("FARB0"); + + o_rc = farb0->Read(); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "Read() FARB0 failed: i_chip=0x%08x", + i_chip->getHuid() ); + break; + } + + farb0->SetBit(59); + farb0->SetBit(40); + + o_rc = farb0->Write(); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "Write() FARB0 failed: i_chip=0x%08x", + i_chip->getHuid() ); + break; + } + + // reset thresholds to prevent issuing multiple port failures on + // the same port + for ( auto & resetTh : db->iv_iueTh ) + { + resetTh.second.reset(); + } + + db->iv_iuePortFail = true; + + break; + }while(0); + + + return o_rc; + + #undef PRDF_FUNC +} + #endif // __HOSTBOOT_RUNTIME //------------------------------------------------------------------------------ @@ -420,6 +603,30 @@ bool queryIueTh<TYPE_MCA>( ExtensibleChip * i_chip, return iueAtTh; } +template<> +bool queryIueTh<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + PRDF_ASSERT( nullptr != i_chip ); + PRDF_ASSERT( TYPE_OCMB_CHIP == i_chip->getType() ); + + bool iueAtTh = false; + + OcmbDataBundle * db = getOcmbDataBundle( i_chip ); + + // Loop through all our thresholds + for ( auto & th : db->iv_iueTh ) + { + // If threshold reached + if ( th.second.thReached(io_sc) ) + { + iueAtTh = true; + } + } + + return iueAtTh; +} + #endif //------------------------------------------------------------------------------ @@ -493,6 +700,11 @@ template uint32_t handleMpe<TYPE_MBA>( ExtensibleChip * i_chip, const MemAddr & i_addr, UE_TABLE::Type i_type, STEP_CODE_DATA_STRUCT & io_sc ); +template +uint32_t handleMpe<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + const MemAddr & i_addr, + UE_TABLE::Type i_type, + STEP_CODE_DATA_STRUCT & io_sc ); //------------------------------------------------------------------------------ @@ -581,6 +793,10 @@ template uint32_t analyzeFetchMpe<TYPE_MBA>( ExtensibleChip * i_chip, const MemRank & i_rank, STEP_CODE_DATA_STRUCT & io_sc ); +template +uint32_t analyzeFetchMpe<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + const MemRank & i_rank, + STEP_CODE_DATA_STRUCT & io_sc ); //------------------------------------------------------------------------------ @@ -794,6 +1010,9 @@ uint32_t analyzeFetchNceTce<TYPE_MCA>( ExtensibleChip * i_chip, template uint32_t analyzeFetchNceTce<TYPE_MBA>( ExtensibleChip * i_chip, STEP_CODE_DATA_STRUCT & io_sc ); +template +uint32_t analyzeFetchNceTce<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ); //------------------------------------------------------------------------------ @@ -871,6 +1090,9 @@ uint32_t analyzeFetchUe<TYPE_MCA>( ExtensibleChip * i_chip, template uint32_t analyzeFetchUe<TYPE_MBA>( ExtensibleChip * i_chip, STEP_CODE_DATA_STRUCT & io_sc ); +template +uint32_t analyzeFetchUe<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ); //------------------------------------------------------------------------------ @@ -955,16 +1177,97 @@ uint32_t handleMemIue<TYPE_MCA>( ExtensibleChip * i_chip, #undef PRDF_FUNC } -//------------------------------------------------------------------------------ - template<> -uint32_t analyzeMainlineIue<TYPE_MCA>( ExtensibleChip * i_chip, +uint32_t handleMemIue<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + const MemRank & i_rank, STEP_CODE_DATA_STRUCT & io_sc ) { + #define PRDF_FUNC "[MemEcc::handleMemIue] " + + PRDF_ASSERT( nullptr != i_chip ); + PRDF_ASSERT( TYPE_OCMB_CHIP == i_chip->getType() ); + + uint32_t o_rc = SUCCESS; + + // Add the DIMM to the callout list. + MemoryMru mm { i_chip->getTrgt(), i_rank, MemoryMruData::CALLOUT_RANK }; + io_sc.service_data->SetCallout( mm ); + + #ifdef __HOSTBOOT_MODULE + + do + { + // Nothing else to do if handling a system checkstop. + if ( CHECK_STOP == io_sc.service_data->getPrimaryAttnType() ) break; + + // Get the data bundle from chip. + OcmbDataBundle * db = getOcmbDataBundle( i_chip ); + + // If we have already caused a port fail, mask the IUE bits. + if ( true == db->iv_iuePortFail ) + { + SCAN_COMM_REGISTER_CLASS * mask_or = + i_chip->getRegister("RDFFIR_MASK_OR"); + + mask_or->SetBit(17); + mask_or->SetBit(37); + + o_rc = mask_or->Write(); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "Write() failed on 0x%08x", + i_chip->getHuid() ); + break; + } + } + + // Get the DIMM select. + uint8_t ds = i_rank.getDimmSlct(); + + // Initialize threshold if it doesn't exist yet. + if ( 0 == db->iv_iueTh.count(ds) ) + { + db->iv_iueTh[ds] = TimeBasedThreshold( getIueTh() ); + } + + // Increment the count and check if at threshold. + if ( db->iv_iueTh[ds].inc(io_sc) ) + { + // Make the error log predictive. + io_sc.service_data->setServiceCall(); + + // The port fail will be triggered in the PostAnalysis plugin after + // the error log has been committed. + + // Mask off the entire port to avoid collateral. + o_rc = MemEcc::maskMemPort<TYPE_OCMB_CHIP>( i_chip ); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "MemEcc::maskMemPort(0x%08x) failed", + i_chip->getHuid() ); + break; + } + } + + } while (0); + + #endif // __HOSTBOOT_MODULE + + return o_rc; + + #undef PRDF_FUNC +} + +//------------------------------------------------------------------------------ + +template<TARGETING::TYPE T> +uint32_t analyzeMainlineIue( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ) +{ #define PRDF_FUNC "[MemEcc::analyzeMainlineIue] " PRDF_ASSERT( nullptr != i_chip ); - PRDF_ASSERT( TYPE_MCA == i_chip->getType() ); + PRDF_ASSERT( T == i_chip->getType() ); uint32_t o_rc = SUCCESS; @@ -974,7 +1277,7 @@ uint32_t analyzeMainlineIue<TYPE_MCA>( ExtensibleChip * i_chip, // not likely that we will have two independent failure modes at the // same time. So we just assume the address is correct. MemAddr addr; - o_rc = getMemReadAddr<TYPE_MCA>( i_chip, MemAddr::READ_RCE_ADDR, addr ); + o_rc = getMemReadAddr<T>( i_chip, MemAddr::READ_RCE_ADDR, addr ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "getMemReadAddr(0x%08x, READ_RCE_ADDR) failed", @@ -983,7 +1286,7 @@ uint32_t analyzeMainlineIue<TYPE_MCA>( ExtensibleChip * i_chip, } MemRank rank = addr.getRank(); - o_rc = handleMemIue<TYPE_MCA>( i_chip, rank, io_sc ); + o_rc = handleMemIue<T>( i_chip, rank, io_sc ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "handleMemIue(0x%08x,m%ds%d) failed", @@ -998,16 +1301,23 @@ uint32_t analyzeMainlineIue<TYPE_MCA>( ExtensibleChip * i_chip, #undef PRDF_FUNC } +template +uint32_t analyzeMainlineIue<TYPE_MCA>( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ); +template +uint32_t analyzeMainlineIue<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ); + //------------------------------------------------------------------------------ -template<> -uint32_t analyzeMaintIue<TYPE_MCA>( ExtensibleChip * i_chip, - STEP_CODE_DATA_STRUCT & io_sc ) +template<TARGETING::TYPE T> +uint32_t analyzeMaintIue( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ) { #define PRDF_FUNC "[MemEcc::analyzeMaintIue] " PRDF_ASSERT( nullptr != i_chip ); - PRDF_ASSERT( TYPE_MCA == i_chip->getType() ); + PRDF_ASSERT( T == i_chip->getType() ); uint32_t o_rc = SUCCESS; @@ -1015,7 +1325,7 @@ uint32_t analyzeMaintIue<TYPE_MCA>( ExtensibleChip * i_chip, { // Use the current address in the MCBMCAT. MemAddr addr; - o_rc = getMemMaintAddr<TYPE_MCA>( i_chip, addr ); + o_rc = getMemMaintAddr<T>( i_chip, addr ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "getMemMaintAddr(0x%08x) failed", @@ -1024,7 +1334,7 @@ uint32_t analyzeMaintIue<TYPE_MCA>( ExtensibleChip * i_chip, } MemRank rank = addr.getRank(); - o_rc = handleMemIue<TYPE_MCA>( i_chip, rank, io_sc ); + o_rc = handleMemIue<T>( i_chip, rank, io_sc ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "handleMemIue(0x%08x,m%ds%d) failed", @@ -1039,6 +1349,13 @@ uint32_t analyzeMaintIue<TYPE_MCA>( ExtensibleChip * i_chip, #undef PRDF_FUNC } +template +uint32_t analyzeMaintIue<TYPE_MCA>( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ); +template +uint32_t analyzeMaintIue<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ); + //------------------------------------------------------------------------------ template<> @@ -1152,6 +1469,117 @@ uint32_t analyzeImpe<TYPE_MCA>( ExtensibleChip * i_chip, #undef PRDF_FUNC } +template<> +uint32_t analyzeImpe<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + + #define PRDF_FUNC "[MemEcc::analyzeImpe] " + + PRDF_ASSERT( TYPE_OCMB_CHIP == i_chip->getType() ); + + uint32_t o_rc = SUCCESS; + + do + { + // get the mark shadow register + SCAN_COMM_REGISTER_CLASS * msr = i_chip->getRegister("EXP_MSR"); + + o_rc = msr->Read(); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "Read() failed on EXP_MSR: i_chip=0x%08x", + i_chip->getHuid() ); + break; + } + + TargetHandle_t trgt = i_chip->getTrgt(); + + // get galois field code - bits 8:15 of MSR + uint8_t galois = msr->GetBitFieldJustified( 8, 8 ); + + // get rank - bits 16:18 of MSR + uint8_t mrnk = msr->GetBitFieldJustified( 16, 3 ); + MemRank rank( mrnk ); + + // get symbol and DRAM + MemSymbol symbol = MemSymbol::fromGalois( trgt, rank, galois ); + if ( !symbol.isValid() ) + { + PRDF_ERR( PRDF_FUNC "Galois 0x%02x from EXP_MSR is invalid: 0x%08x," + "0x%02x", galois, i_chip->getHuid(), rank.getKey() ); + o_rc = FAIL; + break; + } + + // Add the DIMM to the callout list + MemoryMru memmru( trgt, rank, MemoryMruData::CALLOUT_RANK ); + io_sc.service_data->SetCallout( memmru ); + + #ifdef __HOSTBOOT_MODULE + // get data bundle from chip + OcmbDataBundle * db = getOcmbDataBundle( i_chip ); + uint8_t dram = symbol.getDram(); + + // Increment the count and check threshold. + if ( db->getImpeThresholdCounter()->inc(rank, dram, io_sc) ) + { + // Make the error log predictive if DRAM Repairs are disabled or if + // the number of DRAMs on this rank with IMPEs has reached threshold + if ( areDramRepairsDisabled() || + db->getImpeThresholdCounter()->queryDrams(rank, dram, io_sc) ) + { + io_sc.service_data->setServiceCall(); + } + else // Otherwise, place a chip mark on the failing DRAM. + { + MemMark chipMark( trgt, rank, galois ); + o_rc = MarkStore::writeChipMark<TYPE_OCMB_CHIP>( i_chip, rank, + chipMark ); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "writeChipMark(0x%08x,0x%02x) failed", + i_chip->getHuid(), rank.getKey() ); + break; + } + + o_rc = MarkStore::chipMarkCleanup<TYPE_OCMB_CHIP>( i_chip, rank, + io_sc ); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "chipMarkCleanup(0x%08x,0x%02x) failed", + i_chip->getHuid(), rank.getKey() ); + break; + } + } + } + + // If a predictive callout is made, mask both mainline and maintenance + // attentions. + if ( io_sc.service_data->queryServiceCall() ) + { + SCAN_COMM_REGISTER_CLASS * mask + = i_chip->getRegister( "RDFFIR_MASK_OR" ); + mask->SetBit(19); // mainline + mask->SetBit(39); // maintenance + o_rc = mask->Write(); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "Write() failed on RDFFIR_MASK_OR: " + "0x%08x", i_chip->getHuid() ); + break; + } + } + #endif // __HOSTBOOT_MODULE + + } while (0); + + + return o_rc; + + #undef PRDF_FUNC +} + //------------------------------------------------------------------------------ template<> diff --git a/src/usr/diag/prdf/common/plat/mem/prdfMemEccAnalysis.H b/src/usr/diag/prdf/common/plat/mem/prdfMemEccAnalysis.H index 735ae436f..0fd71dd8b 100644 --- a/src/usr/diag/prdf/common/plat/mem/prdfMemEccAnalysis.H +++ b/src/usr/diag/prdf/common/plat/mem/prdfMemEccAnalysis.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -51,7 +51,7 @@ namespace MemEcc * @brief Adds the memory CE to the callout list and CE table. Will also issue * dynamic memory deallocation when appropriate. Returns true if TPS is * required. - * @param i_chip MCA or MBA. + * @param i_chip MCA, MBA, or OCMB. * @param i_addr Failed address. * @param i_symbol Failed symbol. * @param o_doTps True if TPS is required. False otherwise. @@ -74,7 +74,7 @@ uint32_t handleMemCe( ExtensibleChip * i_chip, const MemAddr & i_addr, * of the DIMMs, the UE table will not be updated and no dynamic memory * deallocation. * - * @param i_chip MCA or MBA. + * @param i_chip MCA, OCMB, or MBA. * @param i_addr Failed address. * @param i_type The type of UE. * @param io_sc The step code data struct. @@ -96,7 +96,7 @@ uint32_t handleMemUe( ExtensibleChip * i_chip, const MemAddr & i_addr, * the port failure is issued in the PostAnalysis plugin after the error log has * been committed. * - * @param i_chip MCA chip. + * @param i_chip MCA or OCMB chip. * @param i_rank Rank containing the IUE. * @param io_sc The step code data struct. * @return Non-SUCCESS if an interal function fails, SUCCESS otherwise. @@ -107,7 +107,7 @@ uint32_t handleMemIue( ExtensibleChip * i_chip, const MemRank & i_rank, /** * @brief Handles a MPE attention. - * @param i_chip MCA or MBA. + * @param i_chip MCA, OCMB, or MBA. * @param i_addr Failed address. * @param i_type The type of UE. * @param io_sc The step code data struct. @@ -119,7 +119,7 @@ uint32_t handleMpe( ExtensibleChip * i_chip, const MemAddr & i_addr, /** * @brief Handles a MPE attention. - * @param i_chip MCA or MBA. + * @param i_chip MCA, OCMB, or MBA. * @param i_rank Target rank. * @param i_type The type of UE. * @param io_sc The step code data struct. @@ -135,7 +135,7 @@ uint32_t handleMpe( ExtensibleChip * i_chip, const MemRank & i_rank, /** * @brief Analyzes a fetch MPE attention. - * @param i_chip MCA or MBA. + * @param i_chip MCA, OCMB, or MBA. * @param i_rank Target rank. * @param io_sc The step code data struct. * @return Non-SUCCESS if an interal function fails, SUCCESS otherwise. @@ -146,7 +146,7 @@ uint32_t analyzeFetchMpe( ExtensibleChip * i_chip, const MemRank & i_rank, /** * @brief Analyzes a fetch NCE/TCE attention. - * @param i_chip MCA or MBA. + * @param i_chip MCA, OCMB, or MBA. * @param io_sc The step code data struct. * @return Non-SUCCESS if an interal function fails, SUCCESS otherwise. */ @@ -156,7 +156,7 @@ uint32_t analyzeFetchNceTce( ExtensibleChip * i_chip, /** * @brief Analyzes a fetch UE attention. - * @param i_chip MCA or MBA. + * @param i_chip MCA, OCMB, or MBA. * @param io_sc The step code data struct. * @return Non-SUCCESS if an interal function fails, SUCCESS otherwise. */ @@ -166,7 +166,7 @@ uint32_t analyzeFetchUe( ExtensibleChip * i_chip, /** * @brief Analyzes a fetch mainline IUE attention. - * @param i_chip MCA or MBA. + * @param i_chip MCA, OCMB, or MBA. * @param io_sc The step code data struct. * @return Non-SUCCESS if an interal function fails, SUCCESS otherwise. */ @@ -177,7 +177,7 @@ uint32_t analyzeMainlineIue( ExtensibleChip * i_chip, /** * @brief Analyzes a fetch maint IUE attention. - * @param i_chip MCA or MBA. + * @param i_chip MCA, OCMB, or MBA. * @param io_sc The step code data struct. * @return Non-SUCCESS if an interal function fails, SUCCESS otherwise. */ @@ -187,7 +187,7 @@ uint32_t analyzeMaintIue( ExtensibleChip * i_chip, /** * @brief Analyzes a maint or mainline IMPE attention. - * @param i_chip MCA or MBA. + * @param i_chip MCA, OCMB, or MBA. * @param io_sc The step code data struct. * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. */ @@ -208,7 +208,7 @@ uint32_t analyzeFetchRcePue( ExtensibleChip * i_chip, /** * @brief Will trigger a port fail. - * @param i_chip MCA chip + * @param i_chip MCA/OCMB chip * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise */ template<TARGETING::TYPE T> @@ -221,7 +221,7 @@ uint32_t triggerPortFail( ExtensibleChip * i_chip ); /** * @brief Will query the data bundle and return if the IUE threshold has been * reached. - * @param i_chip MCA chip + * @param i_chip MCA/OCMB chip * @param io_sc The step code data struct. * @return True if IUE threshold is reached, false if not. */ @@ -231,7 +231,7 @@ bool queryIueTh( ExtensibleChip * i_chip, STEP_CODE_DATA_STRUCT & io_sc ); /** * @brief Will mask off an entire memory port. At runtime will issue dynamic * memory deallocation of the port. - * @param i_chip MCA chip + * @param i_chip MCA/OCMB chip * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise */ template<TARGETING::TYPE T> diff --git a/src/usr/diag/prdf/common/plat/mem/prdfMemExtraSig.H b/src/usr/diag/prdf/common/plat/mem/prdfMemExtraSig.H index 08b79922e..7bcf0e573 100644 --- a/src/usr/diag/prdf/common/plat/mem/prdfMemExtraSig.H +++ b/src/usr/diag/prdf/common/plat/mem/prdfMemExtraSig.H @@ -88,7 +88,7 @@ PRDR_ERROR_SIGNATURE(VttLost, 0xffff0084, "", "NVDIMM VTT Lost"); PRDR_ERROR_SIGNATURE(NotSelfRefr, 0xffff0085, "", "NVDIMM Dram Not Self Refresh"); PRDR_ERROR_SIGNATURE(CtrlHwErr, 0xffff0086, "", "NVDIMM Controller Hardware Error"); PRDR_ERROR_SIGNATURE(NvmCtrlErr, 0xffff0087, "", "NVDIMM NVM Controller Error"); -PRDR_ERROR_SIGNATURE(NvmLifeErr, 0xffff0088, "", "NVDIMM NVM Lifetime Error"); +PRDR_ERROR_SIGNATURE(NvmLifeErr, 0xffff0088, "", "NVDIMM Final NVM Lifetime Error"); PRDR_ERROR_SIGNATURE(InsuffEnergy, 0xffff0089, "", "NVDIMM Not enough energy for CSAVE"); PRDR_ERROR_SIGNATURE(InvFwErr, 0xffff008A, "", "NVDIMM Invalid Firmware Error"); @@ -98,8 +98,22 @@ PRDR_ERROR_SIGNATURE(EsPolNotSet, 0xffff008D, "", "NVDIMM Energy Source Policy PRDR_ERROR_SIGNATURE(EsHwFail, 0xffff008E, "", "NVDIMM Energy Source Hardware Fail"); PRDR_ERROR_SIGNATURE(EsHlthAssess, 0xffff008F, "", "NVDIMM Energy Source Health Assessment Error"); -PRDR_ERROR_SIGNATURE(EsLifeErr, 0xffff0090, "", "NVDIMM Energy Source Lifetime Error"); -PRDR_ERROR_SIGNATURE(EsTmpErr, 0xffff0091, "", "NVDIMM Energy Source Temp Error"); +PRDR_ERROR_SIGNATURE(EsLifeErr, 0xffff0090, "", "NVDIMM Final Energy Source Lifetime Error"); +PRDR_ERROR_SIGNATURE(EsTmpErrHigh, 0xffff0091, "", "NVDIMM Energy Source Temperature Error - High Temp Threshold"); +PRDR_ERROR_SIGNATURE(EsTmpErrLow, 0xffff0092, "", "NVDIMM Energy Source Temperature Error - Low Temp Threshold"); + +PRDR_ERROR_SIGNATURE(NvmLifeWarn1, 0xffff0093, "", "NVDIMM First NVM Lifetime Warning"); +PRDR_ERROR_SIGNATURE(NvmLifeWarn2, 0xffff0094, "", "NVDIMM Second NVM Lifetime Warning"); +PRDR_ERROR_SIGNATURE(EsLifeWarn1, 0xffff0095, "", "NVDIMM First Energy Source Lifetime Warning"); +PRDR_ERROR_SIGNATURE(EsLifeWarn2, 0xffff0096, "", "NVDIMM Second Energy Source Lifetime Warning"); +PRDR_ERROR_SIGNATURE(EsTmpWarnHigh, 0xffff0097, "", "NVDIMM Energy Source Temperature Warning - High Temp Threshold"); +PRDR_ERROR_SIGNATURE(EsTmpWarnLow, 0xffff0098, "", "NVDIMM Energy Source Temperature Warning - Low Temp Threshold"); +PRDR_ERROR_SIGNATURE(BelowWarnTh, 0xffff0099, "", "NVDIMM Below Warning Threshold"); +PRDR_ERROR_SIGNATURE(IntNvdimmErr, 0xffff009A, "", "NVDIMM Intermittent error"); +PRDR_ERROR_SIGNATURE(NotifStatErr, 0xffff009B, "", "NVDIMM Set Event Notification Status Error"); +PRDR_ERROR_SIGNATURE(FirEvntGone, 0xffff009C, "", "NVDIMM Event Triggering the FIR no longer present"); +PRDR_ERROR_SIGNATURE(EsTmpWarnFa, 0xffff009D, "", "NVDIMM Energy Source Temperature Warning - False Alarm"); +PRDR_ERROR_SIGNATURE(EsTmpErrFa, 0xffff009E, "", "NVDIMM Energy Source Temperature Error - False Alarm"); #endif // __prdfMemExtraSig_H diff --git a/src/usr/diag/prdf/common/plat/mem/prdfMemMark.C b/src/usr/diag/prdf/common/plat/mem/prdfMemMark.C index 83bff1876..e43d844c4 100644 --- a/src/usr/diag/prdf/common/plat/mem/prdfMemMark.C +++ b/src/usr/diag/prdf/common/plat/mem/prdfMemMark.C @@ -46,7 +46,7 @@ namespace MarkStore { //############################################################################## -// Utilities to read/write markstore (MCA) +// Utilities to read/write markstore //############################################################################## // - We have the ability to set chip marks via the FWMSx registers, but there @@ -62,15 +62,19 @@ namespace MarkStore // mark per master rank. This matches the P8 behavior. This could be improved // upon later if we have the time, but doubtful. // - Summary: -// - Chip marks will use HWMS0-7 registers (0x07010AD0-0x07010AD7). -// - Symbol marks will use FWMS0-7 registers (0x07010AD8-0x07010ADF). +// - Chip marks will use HWMS0-7 registers: +// Nimbus: (0x07010AD0-0x07010AD7) +// Axone: (0x08011C10-0x08011C17) +// - Symbol marks will use FWMS0-7 registers: +// Nimbus: (0x07010AD8-0x07010ADF) +// Axone: (0x08011C18-0x08011C1F) // - Each register maps to master ranks 0-7. -template<> -uint32_t readChipMark<TYPE_MCA>( ExtensibleChip * i_chip, - const MemRank & i_rank, MemMark & o_mark ) +template<TARGETING::TYPE T> +uint32_t readChipMark( ExtensibleChip * i_chip, const MemRank & i_rank, + MemMark & o_mark ) { - #define PRDF_FUNC "[readChipMark<TYPE_MCA>] " + #define PRDF_FUNC "[readChipMark<T>] " uint32_t o_rc = SUCCESS; o_mark = MemMark(); // ensure invalid @@ -110,14 +114,21 @@ uint32_t readChipMark<TYPE_MCA>( ExtensibleChip * i_chip, #undef PRDF_FUNC } +template +uint32_t readChipMark<TYPE_MCA>( ExtensibleChip * i_chip, + const MemRank & i_rank, MemMark & o_mark ); +template +uint32_t readChipMark<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + const MemRank & i_rank, + MemMark & o_mark ); + //------------------------------------------------------------------------------ -template<> -uint32_t writeChipMark<TYPE_MCA>( ExtensibleChip * i_chip, - const MemRank & i_rank, - const MemMark & i_mark ) +template<TARGETING::TYPE T> +uint32_t writeChipMark( ExtensibleChip * i_chip, const MemRank & i_rank, + const MemMark & i_mark ) { - #define PRDF_FUNC "[writeChipMark<TYPE_MCA>] " + #define PRDF_FUNC "[writeChipMark<T>] " PRDF_ASSERT( i_mark.isValid() ); @@ -153,13 +164,21 @@ uint32_t writeChipMark<TYPE_MCA>( ExtensibleChip * i_chip, #undef PRDF_FUNC } +template +uint32_t writeChipMark<TYPE_MCA>( ExtensibleChip * i_chip, + const MemRank & i_rank, + const MemMark & i_mark ); +template +uint32_t writeChipMark<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + const MemRank & i_rank, + const MemMark & i_mark ); + //------------------------------------------------------------------------------ -template<> -uint32_t clearChipMark<TYPE_MCA>( ExtensibleChip * i_chip, - const MemRank & i_rank ) +template<TARGETING::TYPE T> +uint32_t clearChipMark( ExtensibleChip * i_chip, const MemRank & i_rank ) { - #define PRDF_FUNC "[clearChipMark<TYPE_MCA>] " + #define PRDF_FUNC "[clearChipMark<T>] " uint32_t o_rc = SUCCESS; @@ -185,13 +204,20 @@ uint32_t clearChipMark<TYPE_MCA>( ExtensibleChip * i_chip, #undef PRDF_FUNC } +template +uint32_t clearChipMark<TYPE_MCA>( ExtensibleChip * i_chip, + const MemRank & i_rank ); +template +uint32_t clearChipMark<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + const MemRank & i_rank ); + //------------------------------------------------------------------------------ -template<> -uint32_t readSymbolMark<TYPE_MCA>( ExtensibleChip * i_chip, - const MemRank & i_rank, MemMark & o_mark ) +template<TARGETING::TYPE T> +uint32_t readSymbolMark( ExtensibleChip * i_chip, + const MemRank & i_rank, MemMark & o_mark ) { - #define PRDF_FUNC "[readSymbolMark<TYPE_MCA>] " + #define PRDF_FUNC "[readSymbolMark<T>] " uint32_t o_rc = SUCCESS; o_mark = MemMark(); // ensure invalid @@ -247,14 +273,21 @@ uint32_t readSymbolMark<TYPE_MCA>( ExtensibleChip * i_chip, #undef PRDF_FUNC } +template +uint32_t readSymbolMark<TYPE_MCA>( ExtensibleChip * i_chip, + const MemRank & i_rank, MemMark & o_mark ); +template +uint32_t readSymbolMark<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + const MemRank & i_rank, + MemMark & o_mark ); + //------------------------------------------------------------------------------ -template<> -uint32_t writeSymbolMark<TYPE_MCA>( ExtensibleChip * i_chip, - const MemRank & i_rank, - const MemMark & i_mark ) +template<TARGETING::TYPE T> +uint32_t writeSymbolMark( ExtensibleChip * i_chip, const MemRank & i_rank, + const MemMark & i_mark ) { - #define PRDF_FUNC "[writeSymbolMark<TYPE_MCA>] " + #define PRDF_FUNC "[writeSymbolMark<T>] " PRDF_ASSERT( i_mark.isValid() ); @@ -294,36 +327,47 @@ uint32_t writeSymbolMark<TYPE_MCA>( ExtensibleChip * i_chip, msName, i_chip->getHuid() ); } - // Nimbus symbol mark performance workaround - // When a symbol mark is placed at runtime - #ifdef __HOSTBOOT_RUNTIME + // Nimbus only symbol mark performance workaround + if ( T == TYPE_MCA ) + { + // When a symbol mark is placed at runtime + #ifdef __HOSTBOOT_RUNTIME - // Trigger WAT logic to 'disable bypass' - // Get the ECC Debug/WAT Control register - SCAN_COMM_REGISTER_CLASS * dbgr = i_chip->getRegister( "DBGR" ); + // Trigger WAT logic to 'disable bypass' + // Get the ECC Debug/WAT Control register + SCAN_COMM_REGISTER_CLASS * dbgr = i_chip->getRegister( "DBGR" ); - // Set DBGR[8] = 0b1 - dbgr->SetBit( 8 ); - o_rc = dbgr->Write(); - if ( SUCCESS != o_rc ) - { - PRDF_ERR( PRDF_FUNC "Write() failed on DBGR: mca=0x%08x", - i_chip->getHuid() ); + // Set DBGR[8] = 0b1 + dbgr->SetBit( 8 ); + o_rc = dbgr->Write(); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "Write() failed on DBGR: mca=0x%08x", + i_chip->getHuid() ); + } + #endif } - #endif return o_rc; #undef PRDF_FUNC } +template +uint32_t writeSymbolMark<TYPE_MCA>( ExtensibleChip * i_chip, + const MemRank & i_rank, + const MemMark & i_mark ); +template +uint32_t writeSymbolMark<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + const MemRank & i_rank, + const MemMark & i_mark ); + //------------------------------------------------------------------------------ -template<> -uint32_t clearSymbolMark<TYPE_MCA>( ExtensibleChip * i_chip, - const MemRank & i_rank ) +template<TARGETING::TYPE T> +uint32_t clearSymbolMark( ExtensibleChip * i_chip, const MemRank & i_rank ) { - #define PRDF_FUNC "[clearSymbolMark<TYPE_MCA>] " + #define PRDF_FUNC "[clearSymbolMark<T>] " uint32_t o_rc = SUCCESS; @@ -349,6 +393,13 @@ uint32_t clearSymbolMark<TYPE_MCA>( ExtensibleChip * i_chip, #undef PRDF_FUNC } +template +uint32_t clearSymbolMark<TYPE_MCA>( ExtensibleChip * i_chip, + const MemRank & i_rank ); +template +uint32_t clearSymbolMark<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + const MemRank & i_rank ); + //############################################################################## // Utilities to read/write markstore (MBA) //############################################################################## @@ -958,7 +1009,7 @@ void __addCallout( ExtensibleChip * i_chip, const MemRank & i_rank, //------------------------------------------------------------------------------ template<TARGETING::TYPE T> -uint32_t __addRowRepairCallout( ExtensibleChip * i_chip, +uint32_t __addRowRepairCallout( TargetHandle_t i_trgt, const MemRank & i_rank, STEP_CODE_DATA_STRUCT & io_sc ) { @@ -967,7 +1018,7 @@ uint32_t __addRowRepairCallout( ExtensibleChip * i_chip, uint32_t o_rc = SUCCESS; // Get the dimms on this rank on either port. - TargetHandleList dimmList = getConnectedDimms( i_chip->getTrgt(), i_rank ); + TargetHandleList dimmList = getConnectedDimms( i_trgt, i_rank ); // Check for row repairs on each dimm. for ( auto const & dimm : dimmList ) @@ -1073,8 +1124,8 @@ uint32_t __applyRasPolicies<TYPE_MBA>( ExtensibleChip * i_chip, __addCallout( i_chip, i_rank, ecc, io_sc ); // Add the row repairs to the callout list if they exist - o_rc = __addRowRepairCallout<TARGETING::TYPE_MBA>( i_chip, i_rank, - io_sc ); + o_rc = __addRowRepairCallout<TARGETING::TYPE_MBA>( + i_chip->getTrgt(), i_rank, io_sc ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "__addRowRepairCallout(0x%08x,0x%02x) " @@ -1136,6 +1187,125 @@ uint32_t __applyRasPolicies<TYPE_MBA>( ExtensibleChip * i_chip, #undef PRDF_FUNC } +template<> +uint32_t __applyRasPolicies<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + const MemRank & i_rank, + STEP_CODE_DATA_STRUCT & io_sc, + const MemMark & i_chipMark, + const MemMark & i_symMark, + TdEntry * & o_dsdEvent, + bool & o_allRepairsUsed ) +{ + #define PRDF_FUNC "[__applyRasPolicies<TYPE_OCMB_CHIP>] " + + uint32_t o_rc = SUCCESS; + + do + { + const uint8_t ps = i_chipMark.getSymbol().getPortSlct(); + const uint8_t dram = i_chipMark.getSymbol().getDram(); + + TargetHandle_t memPort = getConnectedChild( i_chip->getTrgt(), + TYPE_MEM_PORT, ps ); + + TargetHandle_t dimmTrgt = getConnectedDimm( memPort, i_rank, ps ); + + const bool isX4 = isDramWidthX4( dimmTrgt ); + + // Determine if DRAM sparing is enabled. + bool isEnabled = false; + o_rc = isDramSparingEnabled<TYPE_MEM_PORT>( memPort, i_rank, ps, + isEnabled ); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "isDramSparingEnabled() failed." ); + break; + } + + if ( isEnabled ) + { + // Sparing is enabled. Get the current spares in hardware. + MemSymbol sp0, sp1, ecc; + o_rc = mssGetSteerMux<TARGETING::TYPE_OCMB_CHIP>( i_chip->getTrgt(), + i_rank, sp0, sp1, + ecc ); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "mssGetSteerMux(0x%08x,0x%02x) failed", + i_chip->getHuid(), i_rank.getKey() ); + break; + } + + // Add the spares to the callout list if they exist. + __addCallout( i_chip, i_rank, sp0, io_sc ); + __addCallout( i_chip, i_rank, sp1, io_sc ); + __addCallout( i_chip, i_rank, ecc, io_sc ); + + // Add the row repairs to the callout list if they exist + o_rc = __addRowRepairCallout<TARGETING::TYPE_OCMB_CHIP>( memPort, + i_rank, + io_sc ); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "__addRowRepairCallout(0x%08x,0x%02x) " + "failed.", i_chip->getHuid(), i_rank.getKey() ); + break; + } + + // If the chip mark is on a spare then the spare is bad and hardware + // can not steer it to another DRAM even if one is available (e.g. + // the ECC spare). In this this case, make error log predictive. + if ( ( (0 == ps) && sp0.isValid() && (dram == sp0.getDram()) ) || + ( (1 == ps) && sp1.isValid() && (dram == sp1.getDram()) ) || + ( isX4 && ecc.isValid() && (dram == ecc.getDram()) ) ) + { + o_allRepairsUsed = true; + io_sc.service_data->setSignature( i_chip->getHuid(), + PRDFSIG_VcmBadSpare ); + break; // Nothing more to do. + } + + // Certain DIMMs may have had spares intentially made unavailable by + // the manufacturer. Check the VPD for available spares. + bool spAvail, eccAvail; + o_rc = isSpareAvailable<TYPE_MEM_PORT>( memPort, i_rank, + ps, spAvail, eccAvail ); + if ( spAvail ) + { + // A spare DRAM is available. + o_dsdEvent = new DsdEvent<TYPE_OCMB_CHIP>{ i_chip, i_rank, + i_chipMark }; + } + else if ( eccAvail ) + { + // The ECC spare is available. + o_dsdEvent = new DsdEvent<TYPE_OCMB_CHIP>{ i_chip, i_rank, + i_chipMark, true }; + } + else + { + // Chip mark is in place and sparing is not possible. + o_allRepairsUsed = true; + io_sc.service_data->setSignature( i_chip->getHuid(), + PRDFSIG_AllDramRepairs ); + } + } + // There is no DRAM sparing so simply check if both the chip and symbol + // mark have been used. + else if ( i_chipMark.isValid() && i_symMark.isValid() ) + { + o_allRepairsUsed = true; + io_sc.service_data->setSignature( i_chip->getHuid(), + PRDFSIG_AllDramRepairs ); + } + + } while (0); + + return o_rc; + + #undef PRDF_FUNC +} + //------------------------------------------------------------------------------ template<TARGETING::TYPE T> @@ -1220,6 +1390,9 @@ uint32_t applyRasPolicies( ExtensibleChip * i_chip, const MemRank & i_rank, { io_sc.service_data->setServiceCall(); + // We want to try to avoid garding NVDIMMs, so clear gard for them now. + io_sc.service_data->clearNvdimmMruListGard(); + #ifdef __HOSTBOOT_RUNTIME // No more repairs left so no point doing any more TPS procedures. MemDbUtils::banTps<T>( i_chip, i_rank ); @@ -1241,6 +1414,11 @@ uint32_t applyRasPolicies<TYPE_MBA>( ExtensibleChip * i_chip, const MemRank & i_rank, STEP_CODE_DATA_STRUCT & io_sc, TdEntry * & o_dsdEvent ); +template +uint32_t applyRasPolicies<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + const MemRank & i_rank, + STEP_CODE_DATA_STRUCT & io_sc, + TdEntry * & o_dsdEvent ); //------------------------------------------------------------------------------ @@ -1290,7 +1468,8 @@ uint32_t chipMarkCleanup( ExtensibleChip * i_chip, const MemRank & i_rank, // Set the chip mark in the DRAM Repairs VPD. if ( !areDramRepairsDisabled() ) { - o_rc = setDramInVpd( i_chip, i_rank, chipMark.getSymbol() ); + o_rc = setDramInVpd( i_chip->getTrgt(), i_rank, + chipMark.getSymbol() ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "setDramInVpd(0x%08x,0x%02x) failed", @@ -1314,6 +1493,10 @@ template uint32_t chipMarkCleanup<TYPE_MBA>( ExtensibleChip * i_chip, const MemRank & i_rank, STEP_CODE_DATA_STRUCT & io_sc ); +template +uint32_t chipMarkCleanup<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + const MemRank & i_rank, + STEP_CODE_DATA_STRUCT & io_sc ); #endif // not supported on FSP diff --git a/src/usr/diag/prdf/common/plat/mem/prdfMemMark.H b/src/usr/diag/prdf/common/plat/mem/prdfMemMark.H index 2cd28b8dd..86ffa1dc9 100644 --- a/src/usr/diag/prdf/common/plat/mem/prdfMemMark.H +++ b/src/usr/diag/prdf/common/plat/mem/prdfMemMark.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -57,7 +57,7 @@ class MemMark /** * @brief Constructor from components. - * @param i_trgt MBA or MCA target. + * @param i_trgt MBA, MCA, or OCMB target. * @param i_rank The rank this mark is on. * @param i_galois The Galois field. */ @@ -68,7 +68,7 @@ class MemMark /** * @brief Constructor from components. - * @param i_trgt MBA or MCA target. + * @param i_trgt MBA, MCA, or OCMB target. * @param i_rank The rank this mark is on. * @param i_symbol The symbol representing this mark. */ @@ -112,7 +112,7 @@ namespace MarkStore /** * @brief Reads markstore and returns the chip mark for the given rank. - * @param i_chip MBA or MCA chip. + * @param i_chip MBA, MCA, or OCMB chip. * @param i_rank Target rank. * @param o_mark The returned chip mark. * @return Non-SUCCESS if an internal function fails. SUCCESS otherwise. @@ -123,7 +123,7 @@ uint32_t readChipMark( ExtensibleChip * i_chip, const MemRank & i_rank, /** * @brief Writes a chip mark into markstore for the given rank. - * @param i_chip MBA or MCA chip. + * @param i_chip MBA, MCA, or OCMB chip. * @param i_rank Target rank. * @param i_mark Target chip mark. * @return Non-SUCCESS if an internal function fails. SUCCESS otherwise. @@ -134,7 +134,7 @@ uint32_t writeChipMark( ExtensibleChip * i_chip, const MemRank & i_rank, /** * @brief Clear chip mark in markstore for the given rank. - * @param i_chip MBA or MCA chip. + * @param i_chip MBA, MCA, or OCMB chip. * @param i_rank Target rank. * @return Non-SUCCESS if an internal function fails. SUCCESS otherwise. */ @@ -143,7 +143,7 @@ uint32_t clearChipMark( ExtensibleChip * i_chip, const MemRank & i_rank ); /** * @brief Reads markstore and returns the symbol mark for the given rank. - * @param i_chip MBA or MCA chip. + * @param i_chip MBA, MCA. or OCMB chip. * @param i_rank Target rank. * @param o_mark The returned symbol mark. * @return Non-SUCCESS if an internal function fails. SUCCESS otherwise. @@ -154,7 +154,7 @@ uint32_t readSymbolMark( ExtensibleChip * i_chip, const MemRank & i_rank, /** * @brief Writes a symbol mark into markstore for the given rank. - * @param i_chip MBA or MCA chip. + * @param i_chip MBA, MCA, or OCMB chip. * @param i_rank Target rank. * @param i_mark Target symbol mark. * @return Non-SUCCESS if an internal function fails. SUCCESS otherwise. @@ -165,7 +165,7 @@ uint32_t writeSymbolMark( ExtensibleChip * i_chip, const MemRank & i_rank, /** * @brief Clear symbol mark in markstore for the given rank. - * @param i_chip MBA or MCA chip. + * @param i_chip MBA, MCA. or OCMB chip. * @param i_rank Target rank. * @return Non-SUCCESS if an internal function fails. SUCCESS otherwise. */ @@ -187,7 +187,7 @@ uint32_t clearSymbolMark( ExtensibleChip * i_chip, const MemRank & i_rank ); * repairs have been used. * - Returns a new DsdEvent if DRAM sparing is available. * - * @param i_chip MBA or MCA chip. + * @param i_chip MBA, MCA, or OCMB chip. * @param i_rank Target rank. * @param io_sc The step code data struct. * @param o_dsdEvent A new DsdEvent if DRAM sparing is available. Otherwise, @@ -211,7 +211,7 @@ uint32_t applyRasPolicies( ExtensibleChip * i_chip, const MemRank & i_rank, * - Sets the DRAM in the DRAM Repair VPD if DRAM repairs. * - Adds a DSD procedure to the TD queue if a DRAM spare is available * - * @param i_chip MBA or MCA chip. + * @param i_chip MBA, MCA, or OCMB chip. * @param i_rank Target rank. * @param io_sc The step code data struct. * @return Non-SUCCESS if an internal function fails. SUCCESS otherwise. diff --git a/src/usr/diag/prdf/common/plat/mem/prdfMemRowRepair.C b/src/usr/diag/prdf/common/plat/mem/prdfMemRowRepair.C index 8ebe6cea8..3ff6cd099 100644 --- a/src/usr/diag/prdf/common/plat/mem/prdfMemRowRepair.C +++ b/src/usr/diag/prdf/common/plat/mem/prdfMemRowRepair.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -126,6 +126,22 @@ uint32_t getRowRepairData<TYPE_MCA>( TargetHandle_t i_dimm, o_rowRepair ); } +template<> +uint32_t getRowRepairData<TYPE_MEM_PORT>( TargetHandle_t i_dimm, + const MemRank & i_rank, MemRowRepair & o_rowRepair ) +{ + return __getRowRepairData<TYPE_MEM_PORT, fapi2::TARGET_TYPE_MEM_PORT>( + i_dimm, i_rank, o_rowRepair ); +} + +template<> +uint32_t getRowRepairData<TYPE_OCMB_CHIP>( TargetHandle_t i_dimm, + const MemRank & i_rank, MemRowRepair & o_rowRepair ) +{ + return __getRowRepairData<TYPE_OCMB_CHIP, fapi2::TARGET_TYPE_OCMB_CHIP>( + i_dimm, i_rank, o_rowRepair ); +} + //------------------------------------------------------------------------------ template<TARGETING::TYPE T, fapi2::TargetType F> @@ -190,34 +206,19 @@ uint32_t setRowRepairData<TYPE_MCA>( TargetHandle_t i_dimm, i_rowRepair ); } -//------------------------------------------------------------------------------ - -template<TARGETING::TYPE T> -void __setRowRepairDataHelper( const MemAddr & i_addr, uint32_t & io_tmp ); - template<> -void __setRowRepairDataHelper<TYPE_MBA>( const MemAddr & i_addr, - uint32_t & io_tmp ) +uint32_t setRowRepairData<TYPE_OCMB_CHIP>( TargetHandle_t i_dimm, + const MemRank & i_rank, + const MemRowRepair & i_rowRepair ) { - #ifdef __HOSTBOOT_MODULE - - // Bank is stored as MBA "(DDR4): bg1-bg0,b1-b0 (4-bit)" in a MemAddr. - // bank group - 2 bits (bg1-bg0) - io_tmp = ( io_tmp << 2 ) | ( (i_addr.getBank() >> 2) & 0x03 ); - - // bank - 3 bits (b2-b0) - io_tmp = ( io_tmp << 3 ) | ( i_addr.getBank() & 0x03 ); - - // Row is stored as "MBA: r17-r0 (18-bit)" in a MemAddr. - // row - 18 bits (r17-r0) - io_tmp = ( io_tmp << 18 ) | ( i_addr.getRow() & 0x0003ffff ); - - #endif // __HOSTBOOT_MODULE + return __setRowRepairData<TYPE_OCMB_CHIP, fapi2::TARGET_TYPE_OCMB_CHIP>( + i_dimm, i_rank, i_rowRepair ); } -template<> -void __setRowRepairDataHelper<TYPE_MCA>( const MemAddr & i_addr, - uint32_t & io_tmp ) +//------------------------------------------------------------------------------ + +template<TARGETING::TYPE T> +void __setRowRepairDataHelper( const MemAddr & i_addr, uint32_t & io_tmp ) { #ifdef __HOSTBOOT_MODULE @@ -242,6 +243,32 @@ void __setRowRepairDataHelper<TYPE_MCA>( const MemAddr & i_addr, #endif // __HOSTBOOT_MODULE } +template +void __setRowRepairDataHelper<TYPE_MCA>( const MemAddr & i_addr, + uint32_t & io_tmp ); +template +void __setRowRepairDataHelper<TYPE_OCMB_CHIP>( const MemAddr & i_addr, + uint32_t & io_tmp ); + +template<> +void __setRowRepairDataHelper<TYPE_MBA>( const MemAddr & i_addr, + uint32_t & io_tmp ) +{ + #ifdef __HOSTBOOT_MODULE + + // Bank is stored as MBA "(DDR4): bg1-bg0,b1-b0 (4-bit)" in a MemAddr. + // bank group - 2 bits (bg1-bg0) + io_tmp = ( io_tmp << 2 ) | ( (i_addr.getBank() >> 2) & 0x03 ); + + // bank - 3 bits (b2-b0) + io_tmp = ( io_tmp << 3 ) | ( i_addr.getBank() & 0x03 ); + + // Row is stored as "MBA: r17-r0 (18-bit)" in a MemAddr. + // row - 18 bits (r17-r0) + io_tmp = ( io_tmp << 18 ) | ( i_addr.getRow() & 0x0003ffff ); + + #endif // __HOSTBOOT_MODULE +} //------------------------------------------------------------------------------ @@ -297,7 +324,7 @@ uint32_t setRowRepairData( TargetHandle_t i_dimm, MemRowRepair l_rowRepair( i_dimm, i_rank, l_data ); - o_rc = setRowRepairData<TYPE_MBA>( i_dimm, i_rank, l_rowRepair ); + o_rc = setRowRepairData<T>( i_dimm, i_rank, l_rowRepair ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "setRowRepairData() failed" ); @@ -323,6 +350,11 @@ uint32_t setRowRepairData<TYPE_MCA>( TargetHandle_t i_dimm, const MemRank & i_rank, const MemAddr & i_addr, uint8_t i_dram ); +template +uint32_t setRowRepairData<TYPE_OCMB_CHIP>( TargetHandle_t i_dimm, + const MemRank & i_rank, + const MemAddr & i_addr, + uint8_t i_dram ); //------------------------------------------------------------------------------ @@ -362,6 +394,9 @@ uint32_t clearRowRepairData<TYPE_MBA>( TargetHandle_t i_dimm, template uint32_t clearRowRepairData<TYPE_MCA>( TargetHandle_t i_dimm, const MemRank & i_rank ); +template +uint32_t clearRowRepairData<TYPE_OCMB_CHIP>( TargetHandle_t i_dimm, + const MemRank & i_rank ); //------------------------------------------------------------------------------ diff --git a/src/usr/diag/prdf/common/plat/mem/prdfMemSymbol.C b/src/usr/diag/prdf/common/plat/mem/prdfMemSymbol.C index 561c11dda..d58d6a177 100755 --- a/src/usr/diag/prdf/common/plat/mem/prdfMemSymbol.C +++ b/src/usr/diag/prdf/common/plat/mem/prdfMemSymbol.C @@ -53,7 +53,7 @@ MemSymbol::MemSymbol( TARGETING::TargetHandle_t i_trgt, const MemRank & i_rank, PRDF_ASSERT( nullptr != i_trgt ); PRDF_ASSERT( TYPE_MBA == getTargetType(i_trgt) || TYPE_MCA == getTargetType(i_trgt) || - TYPE_MEM_PORT == getTargetType(i_trgt) ); + TYPE_OCMB_CHIP == getTargetType(i_trgt) ); // Allowing an invalid symbol. Use isValid() to check validity. PRDF_ASSERT( i_pins <= CEN_SYMBOL::BOTH_SYMBOL_DQS ); } @@ -83,9 +83,9 @@ MemSymbol MemSymbol::fromGalois( TargetHandle_t i_trgt, const MemRank & i_rank, if ( 0 != (i_mask & 0xaa) ) pins |= EVEN_SYMBOL_DQ; if ( 0 != (i_mask & 0x55) ) pins |= ODD_SYMBOL_DQ; } - else if ( TYPE_MCA == trgtType || TYPE_MEM_PORT == trgtType ) + else if ( TYPE_MCA == trgtType || TYPE_OCMB_CHIP == trgtType ) { - // 1 pin for MCA/MEM_PORT. + // 1 pin for MCA/TYPE_OCMB_CHIP. if ( 0 != (i_mask & 0xff) ) pins |= ODD_SYMBOL_DQ; } else @@ -112,9 +112,9 @@ uint8_t MemSymbol::getDq() const { dq = symbol2Dq<TYPE_MCA>( iv_symbol ); } - else if ( TYPE_MEM_PORT == trgtType ) + else if ( TYPE_OCMB_CHIP == trgtType ) { - dq = symbol2Dq<TYPE_MEM_PORT>( iv_symbol ); + dq = symbol2Dq<TYPE_OCMB_CHIP>( iv_symbol ); } else { @@ -140,9 +140,9 @@ uint8_t MemSymbol::getPortSlct() const { portSlct = symbol2PortSlct<TYPE_MCA>( iv_symbol ); } - else if ( TYPE_MEM_PORT == trgtType ) + else if ( TYPE_OCMB_CHIP == trgtType ) { - portSlct = symbol2PortSlct<TYPE_MEM_PORT>( iv_symbol ); + portSlct = symbol2PortSlct<TYPE_OCMB_CHIP>( iv_symbol ); } else { @@ -159,22 +159,26 @@ uint8_t MemSymbol::getDram() const { uint8_t dram = 0; TYPE trgtType = getTargetType( iv_trgt ); - bool isX4 = isDramWidthX4( iv_trgt ); + bool isX4 = true; if ( TYPE_MBA == trgtType ) { + isX4 = isDramWidthX4( iv_trgt ); dram = isX4 ? symbol2Nibble<TYPE_MBA>( iv_symbol ) : symbol2Byte <TYPE_MBA>( iv_symbol ); } else if ( TYPE_MCA == trgtType ) { + isX4 = isDramWidthX4( iv_trgt ); dram = isX4 ? symbol2Nibble<TYPE_MCA>( iv_symbol ) : symbol2Byte <TYPE_MCA>( iv_symbol ); } - else if ( TYPE_MEM_PORT == trgtType ) + else if ( TYPE_OCMB_CHIP == trgtType ) { - dram = isX4 ? symbol2Nibble<TYPE_MEM_PORT>( iv_symbol ) - : symbol2Byte <TYPE_MEM_PORT>( iv_symbol ); + TargetHandle_t dimm = getConnectedDimm(iv_trgt, iv_rank, getPortSlct()); + isX4 = isDramWidthX4( dimm ); + dram = isX4 ? symbol2Nibble<TYPE_OCMB_CHIP>( iv_symbol ) + : symbol2Byte <TYPE_OCMB_CHIP>( iv_symbol ); } else { @@ -200,14 +204,24 @@ uint8_t MemSymbol::getDramRelCenDqs() const const uint8_t X4_DRAM_SPARE_UPPER = 19; const uint8_t X8_DRAM_SPARE = 9; + bool isX4 = true; + if ( TYPE_OCMB_CHIP == getTargetType(iv_trgt) ) + { + TargetHandle_t dimm = getConnectedDimm(iv_trgt, iv_rank, getPortSlct()); + isX4 = isDramWidthX4( dimm ); + } + else + { + isX4 = isDramWidthX4( iv_trgt ); + } - uint8_t l_dramWidth = ( isDramWidthX4(iv_trgt) ) ? 4 : 8; + uint8_t l_dramWidth = ( isX4 ) ? 4 : 8; uint8_t l_dram = getDq() / l_dramWidth; // (x8: 0-9, x4: 0-19) // Adjust for spares if ( isDramSpared() ) { - if ( isDramWidthX4(iv_trgt) ) + if ( isX4 ) { uint8_t l_bit = getDq() % DQS_PER_BYTE; l_dram = ( l_bit < 4 ) ? X4_DRAM_SPARE_LOWER : X4_DRAM_SPARE_UPPER; @@ -219,7 +233,7 @@ uint8_t MemSymbol::getDramRelCenDqs() const } else if ( isEccSpared() ) { - l_dram = ( isDramWidthX4(iv_trgt) ) ? X4_ECC_SPARE : X8_ECC_SPARE; + l_dram = ( isX4 ) ? X4_ECC_SPARE : X8_ECC_SPARE; } return l_dram; @@ -231,7 +245,16 @@ uint8_t MemSymbol::getDramRelCenDqs() const uint8_t MemSymbol::getDramPins() const { TYPE trgtType = getTargetType( iv_trgt ); - bool isX4 = isDramWidthX4( iv_trgt ); + bool isX4 = true; + if ( TYPE_OCMB_CHIP == trgtType ) + { + TargetHandle_t dimm = getConnectedDimm(iv_trgt, iv_rank, getPortSlct()); + isX4 = isDramWidthX4( dimm ); + } + else + { + isX4 = isDramWidthX4( iv_trgt ); + } uint32_t dps = 0; uint32_t spd = 0; @@ -241,7 +264,7 @@ uint8_t MemSymbol::getDramPins() const dps = MBA_DQS_PER_SYMBOL; spd = isX4 ? MBA_SYMBOLS_PER_NIBBLE : MBA_SYMBOLS_PER_BYTE; } - else if ( TYPE_MCA == trgtType || TYPE_MEM_PORT == trgtType ) + else if ( TYPE_MCA == trgtType || TYPE_OCMB_CHIP == trgtType ) { dps = MEM_DQS_PER_SYMBOL; spd = isX4 ? MEM_SYMBOLS_PER_NIBBLE : MEM_SYMBOLS_PER_BYTE; @@ -261,7 +284,16 @@ uint8_t MemSymbol::getDramSymbol() const { uint8_t dramSymbol = SYMBOLS_PER_RANK; TYPE trgtType = getTargetType( iv_trgt ); - bool isX4 = isDramWidthX4( iv_trgt ); + bool isX4 = true; + if ( TYPE_OCMB_CHIP == trgtType ) + { + TargetHandle_t dimm = getConnectedDimm(iv_trgt, iv_rank, getPortSlct()); + isX4 = isDramWidthX4( dimm ); + } + else + { + isX4 = isDramWidthX4( iv_trgt ); + } uint8_t dram = getDram(); if ( TYPE_MBA == trgtType ) @@ -274,10 +306,10 @@ uint8_t MemSymbol::getDramSymbol() const dramSymbol = isX4 ? nibble2Symbol<TYPE_MCA>( dram ) : byte2Symbol <TYPE_MCA>( dram ); } - else if ( TYPE_MEM_PORT == trgtType ) + else if ( TYPE_OCMB_CHIP == trgtType ) { - dramSymbol = isX4 ? nibble2Symbol<TYPE_MEM_PORT>( dram ) - : byte2Symbol <TYPE_MEM_PORT>( dram ); + dramSymbol = isX4 ? nibble2Symbol<TYPE_OCMB_CHIP>( dram ) + : byte2Symbol <TYPE_OCMB_CHIP>( dram ); } else { @@ -435,16 +467,16 @@ uint32_t getMemReadSymbol<TYPE_MBA>( ExtensibleChip * i_chip, //------------------------------------------------------------------------------ template<> -uint32_t getMemReadSymbol<TYPE_MEM_PORT>( ExtensibleChip * i_chip, - const MemRank & i_rank, - MemSymbol & o_sym1, - MemSymbol & o_sym2 ) +uint32_t getMemReadSymbol<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + const MemRank & i_rank, + MemSymbol & o_sym1, + MemSymbol & o_sym2 ) { - #define PRDF_FUNC "[getMemReadSymbol<TYPE_MEM_PORT>] " + #define PRDF_FUNC "[getMemReadSymbol<TYPE_OCMB_CHIP>] " // Check parameters PRDF_ASSERT( nullptr != i_chip ); - PRDF_ASSERT( TYPE_MEM_PORT == i_chip->getType() ); + PRDF_ASSERT( TYPE_OCMB_CHIP == i_chip->getType() ); uint32_t o_rc = SUCCESS; @@ -453,14 +485,12 @@ uint32_t getMemReadSymbol<TYPE_MEM_PORT>( ExtensibleChip * i_chip, do { // Get the NCE/TCE galois and mask from hardware. - ExtensibleChip * ocmbChip = getConnectedParent(i_chip, TYPE_OCMB_CHIP); - - SCAN_COMM_REGISTER_CLASS * reg = ocmbChip->getRegister("MBSEVR0"); + SCAN_COMM_REGISTER_CLASS * reg = i_chip->getRegister("MBSEVR0"); o_rc = reg->Read(); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "Read() failed on MBSEVR0: " - "ocmbChip=0x%08x", ocmbChip->getHuid() ); + "i_chip=0x%08x", i_chip->getHuid() ); break; } @@ -480,8 +510,8 @@ uint32_t getMemReadSymbol<TYPE_MEM_PORT>( ExtensibleChip * i_chip, tceGalois, tceMask ); MemSymbol sp0, sp1, ecc; - o_rc = mssGetSteerMux<TYPE_MEM_PORT>( i_chip->getTrgt(), i_rank, - sp0, sp1, ecc ); + o_rc = mssGetSteerMux<TYPE_OCMB_CHIP>( i_chip->getTrgt(), i_rank, + sp0, sp1, ecc ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "mssGetSteerMux() failed. HUID: 0x%08x " diff --git a/src/usr/diag/prdf/common/plat/mem/prdfMemSymbol.H b/src/usr/diag/prdf/common/plat/mem/prdfMemSymbol.H index c16972fd8..00b0c7cfd 100755 --- a/src/usr/diag/prdf/common/plat/mem/prdfMemSymbol.H +++ b/src/usr/diag/prdf/common/plat/mem/prdfMemSymbol.H @@ -79,7 +79,7 @@ class MemSymbol /** * @brief Creates a MemSymbol from a symbol. - * @param i_trgt MBA, MCA, or MEM_PORT target. + * @param i_trgt MBA, MCA, or OCMB_CHIP target. * @param i_rank The rank this symbol is on. * @param i_symbol The input symbol. * @param i_pins See enum DqMask. @@ -95,7 +95,7 @@ class MemSymbol /** * @brief Creates a MemSymbol from a Galois field. - * @param i_trgt MBA, MCA, or MEM_PORT target. + * @param i_trgt MBA, MCA, or OCMB_CHIP target. * @param i_rank The rank this symbol is on. * @param i_galois The Galois field. * @param i_mask The bit mask. @@ -122,7 +122,7 @@ class MemSymbol MemRank getRank() const { return iv_rank; }; /** @return The port select for this symbol. Only relevant on MBA. Will - * always return 0 for MCA and MEM_PORT. */ + * always return 0 for MCA and OCMB. */ uint8_t getPortSlct() const; /** @return The DRAM index for this symbol. */ @@ -218,7 +218,7 @@ class MemSymbol /** * @brief Reads the memory NCE/TCE vector trap register from hardware. - * @param i_chip MCA, MBA, or MEM_PORT. + * @param i_chip MCA, MBA, or OCMB_CHIP. * @param i_rank The rank this symbol is on. * @param o_sym1 The first symbol. Should always be valid for both NCE/TCE. * @param o_sym2 The second symbol. Only valid for TCEs. diff --git a/src/usr/diag/prdf/common/plat/mem/prdfMemThresholds.C b/src/usr/diag/prdf/common/plat/mem/prdfMemThresholds.C index f6403f219..f9c73b739 100755 --- a/src/usr/diag/prdf/common/plat/mem/prdfMemThresholds.C +++ b/src/usr/diag/prdf/common/plat/mem/prdfMemThresholds.C @@ -173,7 +173,8 @@ void getMnfgMemCeTh( ExtensibleChip * i_chip, const MemRank & i_rank, else { // Get DRAM size - uint8_t size = MemUtils::getDramSize<T>( i_chip, i_rank.getDimmSlct() ); + uint8_t size = MemUtils::getDramSize<T>( i_chip->getTrgt(), + i_rank.getDimmSlct() ); // Get number of ranks per DIMM select. uint8_t rankCount = getNumRanksPerDimm<T>( i_chip->getTrgt(), @@ -209,7 +210,7 @@ void getMnfgMemCeTh<TYPE_MBA>( ExtensibleChip * i_chip, const MemRank & i_rank, uint32_t & o_cePerDimm ); template -void getMnfgMemCeTh<TYPE_MEM_PORT>( ExtensibleChip * i_chip, +void getMnfgMemCeTh<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, const MemRank & i_rank, uint32_t & o_cePerDram, uint32_t & o_cePerRank, uint32_t & o_cePerDimm ); @@ -236,14 +237,8 @@ uint32_t getScrubCeThreshold( ExtensibleChip * i_chip, const MemRank & i_rank ) // need these templates to avoid linker errors template -uint32_t getScrubCeThreshold<TYPE_MCA>( ExtensibleChip * i_chip, - const MemRank & i_rank ); -template uint32_t getScrubCeThreshold<TYPE_MBA>( ExtensibleChip * i_chip, const MemRank & i_rank ); -template -uint32_t getScrubCeThreshold<TYPE_MEM_PORT>( ExtensibleChip * i_chip, - const MemRank & i_rank ); } // end namespace PRDF diff --git a/src/usr/diag/prdf/common/plat/mem/prdfMemUtils.C b/src/usr/diag/prdf/common/plat/mem/prdfMemUtils.C index 744e55e69..64677f1ae 100755 --- a/src/usr/diag/prdf/common/plat/mem/prdfMemUtils.C +++ b/src/usr/diag/prdf/common/plat/mem/prdfMemUtils.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2019 */ +/* Contributors Listed Below - COPYRIGHT 2013,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -31,11 +31,14 @@ // Framework includes #include <iipServiceDataCollector.h> +#include <iipSystem.h> #include <prdfExtensibleChip.H> +#include <prdfGlobal_common.H> #include <UtilHash.H> // Platform includes #include <prdfCenMbaDataBundle.H> +#include <prdfOcmbDataBundle.H> #include <prdfCenMembufDataBundle.H> #include <prdfCenMembufExtraSig.H> #include <prdfMemSymbol.H> @@ -224,12 +227,12 @@ int32_t collectCeStats<TYPE_MCA>( ExtensibleChip * i_chip, //------------------------------------------------------------------------------ template<> -int32_t collectCeStats<TYPE_MEM_PORT>( ExtensibleChip * i_chip, - const MemRank & i_rank, - MaintSymbols & o_maintStats, - MemSymbol & o_chipMark, uint8_t i_thr ) +int32_t collectCeStats<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + const MemRank & i_rank, + MaintSymbols & o_maintStats, + MemSymbol & o_chipMark, uint8_t i_thr ) { - #define PRDF_FUNC "[MemUtils::collectCeStats<TYPE_MEM_PORT>] " + #define PRDF_FUNC "[MemUtils::collectCeStats<TYPE_OCMB_CHIP>] " int32_t o_rc = SUCCESS; o_chipMark = MemSymbol(); // Initially invalid. @@ -238,10 +241,13 @@ int32_t collectCeStats<TYPE_MEM_PORT>( ExtensibleChip * i_chip, { PRDF_ASSERT( 0 != i_thr ); - TargetHandle_t memPortTrgt = i_chip->getTrgt(); - ExtensibleChip * ocmbChip = getConnectedParent(i_chip, TYPE_OCMB_CHIP); + TargetHandle_t ocmbTrgt = i_chip->getTrgt(); - const bool isX4 = isDramWidthX4(memPortTrgt); + // TODO RTC 210072 - support for multiple ports + TargetHandle_t memPortTrgt = getConnectedChild( ocmbTrgt, + TYPE_MEM_PORT, 0 ); + TargetHandle_t dimm = getConnectedDimm( memPortTrgt, i_rank ); + const bool isX4 = isDramWidthX4( dimm ); // Use this map to keep track of the total counts per DRAM. DramCountMap dramCounts; @@ -252,7 +258,7 @@ int32_t collectCeStats<TYPE_MEM_PORT>( ExtensibleChip * i_chip, for ( uint8_t regIdx = 0; regIdx < CE_REGS_PER_PORT; regIdx++ ) { reg_str = ocmbCeStatReg[regIdx]; - reg = ocmbChip->getRegister( reg_str ); + reg = i_chip->getRegister( reg_str ); o_rc = reg->Read(); if ( SUCCESS != o_rc ) @@ -272,8 +278,8 @@ int32_t collectCeStats<TYPE_MEM_PORT>( ExtensibleChip * i_chip, uint8_t sym = baseSymbol + i; PRDF_ASSERT( sym < SYMBOLS_PER_RANK ); - uint8_t dram = isX4 ? symbol2Nibble<TYPE_MEM_PORT>( sym ) - : symbol2Byte <TYPE_MEM_PORT>( sym ); + uint8_t dram = isX4 ? symbol2Nibble<TYPE_OCMB_CHIP>( sym ) + : symbol2Byte <TYPE_OCMB_CHIP>( sym ); // Keep track of the total DRAM counts. dramCounts[dram].totalCount += count; @@ -286,7 +292,7 @@ int32_t collectCeStats<TYPE_MEM_PORT>( ExtensibleChip * i_chip, dramCounts[dram].symbolCount++; SymbolData symData; - symData.symbol = MemSymbol::fromSymbol( memPortTrgt, i_rank, + symData.symbol = MemSymbol::fromSymbol( ocmbTrgt, i_rank, sym, CEN_SYMBOL::ODD_SYMBOL_DQ ); if ( !symData.symbol.isValid() ) { @@ -329,11 +335,11 @@ int32_t collectCeStats<TYPE_MEM_PORT>( ExtensibleChip * i_chip, if ( 0 != highestCount ) { - uint8_t sym = isX4 ? nibble2Symbol<TYPE_MEM_PORT>( highestDram ) - : byte2Symbol <TYPE_MEM_PORT>( highestDram ); + uint8_t sym = isX4 ? nibble2Symbol<TYPE_OCMB_CHIP>( highestDram ) + : byte2Symbol <TYPE_OCMB_CHIP>( highestDram ); PRDF_ASSERT( sym < SYMBOLS_PER_RANK ); - o_chipMark = MemSymbol::fromSymbol( memPortTrgt, i_rank, sym ); + o_chipMark = MemSymbol::fromSymbol( ocmbTrgt, i_rank, sym ); } } while(0); @@ -514,19 +520,18 @@ int32_t collectCeStats<TYPE_MBA>( ExtensibleChip * i_chip, //------------------------------------------------------------------------------ template<> -uint8_t getDramSize<TYPE_MCA>(ExtensibleChip *i_chip, uint8_t i_dimmSlct) +uint8_t getDramSize<TYPE_MCA>( TargetHandle_t i_trgt, uint8_t i_dimmSlct ) { #define PRDF_FUNC "[MemUtils::getDramSize] " - PRDF_ASSERT( TYPE_MCA == i_chip->getType() ); + PRDF_ASSERT( TYPE_MCA == getTargetType(i_trgt) ); PRDF_ASSERT( i_dimmSlct < DIMM_SLCT_PER_PORT ); - TargetHandle_t mcaTrgt = i_chip->getTrgt(); - TargetHandle_t mcsTrgt = getConnectedParent( mcaTrgt, TYPE_MCS ); + TargetHandle_t mcsTrgt = getConnectedParent( i_trgt, TYPE_MCS ); PRDF_ASSERT( nullptr != mcsTrgt ); - uint8_t mcaRelPos = i_chip->getPos() % MAX_MCA_PER_MCS; + uint8_t mcaRelPos = getTargetPosition(i_trgt) % MAX_MCA_PER_MCS; uint8_t tmp[MAX_MCA_PER_MCS][DIMM_SLCT_PER_PORT]; @@ -542,19 +547,22 @@ uint8_t getDramSize<TYPE_MCA>(ExtensibleChip *i_chip, uint8_t i_dimmSlct) } template<> -uint8_t getDramSize<TYPE_MBA>(ExtensibleChip *i_chip, uint8_t i_dimmSlct) +uint8_t getDramSize<TYPE_MBA>( TargetHandle_t i_trgt, uint8_t i_dimmSlct ) { #define PRDF_FUNC "[MemUtils::getDramSize] " - PRDF_ASSERT( TYPE_MBA == i_chip->getType() ); + PRDF_ASSERT( TYPE_MBA == getTargetType(i_trgt) ); uint8_t o_size = 0; do { - ExtensibleChip * membufChip = getConnectedParent(i_chip, TYPE_MEMBUF); + TargetHandle_t membuf = getConnectedParent(i_trgt, TYPE_MEMBUF); + ExtensibleChip * membufChip = + (ExtensibleChip*)systemPtr->GetChip(membuf); + PRDF_ASSERT( nullptr != membufChip ); - uint32_t pos = i_chip->getPos(); + uint32_t pos = getTargetPosition(i_trgt); const char * reg_str = (0 == pos) ? "MBA0_MBAXCR" : "MBA1_MBAXCR"; SCAN_COMM_REGISTER_CLASS * reg = membufChip->getRegister( reg_str ); @@ -562,7 +570,7 @@ uint8_t getDramSize<TYPE_MBA>(ExtensibleChip *i_chip, uint8_t i_dimmSlct) if ( SUCCESS != rc ) { PRDF_ERR( PRDF_FUNC "Read() failed on %s. Target=0x%08x", - reg_str, i_chip->getHuid() ); + reg_str, getHuid(i_trgt) ); break; } @@ -579,18 +587,16 @@ uint8_t getDramSize<TYPE_MBA>(ExtensibleChip *i_chip, uint8_t i_dimmSlct) } template<> -uint8_t getDramSize<TYPE_MEM_PORT>(ExtensibleChip *i_chip, uint8_t i_dimmSlct) +uint8_t getDramSize<TYPE_MEM_PORT>( TargetHandle_t i_trgt, uint8_t i_dimmSlct ) { #define PRDF_FUNC "[MemUtils::getDramSize] " - PRDF_ASSERT( TYPE_MEM_PORT == i_chip->getType() ); + PRDF_ASSERT( TYPE_MEM_PORT == getTargetType(i_trgt) ); PRDF_ASSERT( i_dimmSlct < DIMM_SLCT_PER_PORT ); - TargetHandle_t memPortTrgt = i_chip->getTrgt(); - uint8_t tmp[DIMM_SLCT_PER_PORT]; - if ( !memPortTrgt->tryGetAttr<TARGETING::ATTR_MEM_EFF_DRAM_DENSITY>(tmp) ) + if ( !i_trgt->tryGetAttr<TARGETING::ATTR_MEM_EFF_DRAM_DENSITY>(tmp) ) { PRDF_ERR( PRDF_FUNC "Failed to get ATTR_MEM_EFF_DRAM_DENSITY" ); PRDF_ASSERT( false ); @@ -601,6 +607,25 @@ uint8_t getDramSize<TYPE_MEM_PORT>(ExtensibleChip *i_chip, uint8_t i_dimmSlct) #undef PRDF_FUNC } +template<> +uint8_t getDramSize<TYPE_OCMB_CHIP>( TargetHandle_t i_trgt, uint8_t i_dimmSlct ) +{ + #define PRDF_FUNC "[MemUtils::getDramSize] " + + PRDF_ASSERT( TYPE_OCMB_CHIP == getTargetType(i_trgt) ); + PRDF_ASSERT( i_dimmSlct < DIMM_SLCT_PER_PORT ); + + // TODO RTC 210072 - Explorer only has one port, however, multiple ports + // will be supported in the future. Updates will need to be made here so we + // can get the relevant port. + + TargetHandle_t memPort = getConnectedChild( i_trgt, TYPE_MEM_PORT, 0 ); + + return getDramSize<TYPE_MEM_PORT>( memPort, i_dimmSlct ); + + #undef PRDF_FUNC +} + //------------------------------------------------------------------------------ template<> @@ -639,6 +664,34 @@ void cleanupChnlAttns<TYPE_MEMBUF>( ExtensibleChip * i_chip, #undef PRDF_FUNC } +template<> +void cleanupChnlAttns<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + #define PRDF_FUNC "[MemUtils::cleanupChnlAttns] " + + PRDF_ASSERT( nullptr != i_chip ); + PRDF_ASSERT( TYPE_OCMB_CHIP == i_chip->getType() ); + + // No cleanup if this is a checkstop attention. + if ( CHECK_STOP == io_sc.service_data->getPrimaryAttnType() ) return; + + #ifdef __HOSTBOOT_MODULE // only do cleanup in Hostboot, no-op in FSP + + // Clear the associated FIR bits for all attention types. DSTLFIR[0:7] + ExtensibleChip * mcc = getConnectedParent( i_chip, TYPE_MCC ); + + SCAN_COMM_REGISTER_CLASS * reg = mcc->getRegister( "DSTLFIR_AND" ); + + reg->setAllBits(); + reg->SetBitFieldJustified( 0, 8, 0 ); + reg->Write(); + + #endif // Hostboot only + + #undef PRDF_FUNC +} + //------------------------------------------------------------------------------ template<TARGETING::TYPE T> @@ -1288,6 +1341,361 @@ bool analyzeChnlFail<TYPE_MC>( ExtensibleChip * i_chip, //------------------------------------------------------------------------------ +bool __queryUcsOmic( ExtensibleChip * i_omic, ExtensibleChip * i_mcc, + TargetHandle_t i_omi ) +{ + PRDF_ASSERT( nullptr != i_omic ); + PRDF_ASSERT( nullptr != i_mcc ); + PRDF_ASSERT( nullptr != i_omi ); + PRDF_ASSERT( TYPE_OMIC == i_omic->getType() ); + PRDF_ASSERT( TYPE_MCC == i_mcc->getType() ); + PRDF_ASSERT( TYPE_OMI == getTargetType(i_omi) ); + + bool o_activeAttn = false; + + do + { + // Get the DSTLCFG2 register to check whether channel fail is enabled + // NOTE: DSTLCFG2[22] = 0b0 to enable chnl fail for subchannel A + // NOTE: DSTLCFG2[23] = 0b0 to enable chnl fail for subchannel B + SCAN_COMM_REGISTER_CLASS * cnfg = i_mcc->getRegister( "DSTLCFG2" ); + + // Get the position of the inputted OMI relative to the parent MCC (0-1) + // to determine which channel we need to check. + uint8_t omiPosRelMcc = getTargetPosition(i_omi) % MAX_OMI_PER_MCC; + + // If channel fail isn't configured, no need to continue. + if ( cnfg->IsBitSet(22 + omiPosRelMcc) ) break; + + // Check the OMIDLFIR for UCS (relevant bits: 0,20,40) + SCAN_COMM_REGISTER_CLASS * fir = i_omic->getRegister("OMIDLFIR"); + SCAN_COMM_REGISTER_CLASS * mask = i_omic->getRegister("OMIDLFIR_MASK"); + SCAN_COMM_REGISTER_CLASS * act0 = i_omic->getRegister("OMIDLFIR_ACT0"); + SCAN_COMM_REGISTER_CLASS * act1 = i_omic->getRegister("OMIDLFIR_ACT1"); + + if ( SUCCESS == ( fir->Read() | mask->Read() | + act0->Read() | act1->Read() ) ) + { + // Get the position of the inputted OMI relative to the parent + // OMIC (0-2). We'll need to use ATTR_OMI_DL_GROUP_POS for this. + uint8_t omiPosRelOmic = i_omi->getAttr<ATTR_OMI_DL_GROUP_POS>(); + + // Get the bit offset for the bit relevant to the inputted OMI. + // 0 : OMI-DL 0 + // 20: OMI-DL 1 + // 40: OMI-DL 2 + uint8_t bitOff = omiPosRelOmic * 20; + + // Check if there is a UNIT_CS for the relevant bits in the OMIDLFIR + // Note: The OMIDLFIR can't actually be set up to report UNIT_CS + // attentions, instead, as a workaround, the relevant channel fail + // bits will be set as recoverable bits and we will manually set + // the attention types to UNIT_CS in our handling of those errors. + if ( fir->IsBitSet(bitOff) && !mask->IsBitSet(bitOff) && + !act0->IsBitSet(bitOff) && act1->IsBitSet(bitOff) ) + { + o_activeAttn = true; + } + } + }while(0); + + return o_activeAttn; +} + +bool __queryUcsMcc( ExtensibleChip * i_mcc, TargetHandle_t i_omi ) +{ + PRDF_ASSERT( nullptr != i_mcc ); + PRDF_ASSERT( nullptr != i_omi ); + PRDF_ASSERT( TYPE_MCC == i_mcc->getType() ); + PRDF_ASSERT( TYPE_OMI == getTargetType(i_omi) ); + + bool o_activeAttn = false; + + // Get the position of the inputted OMI relative to the parent MCC (0-1) + // to determine which channel we need to check. + uint8_t omiPos = getTargetPosition(i_omi) % MAX_OMI_PER_MCC; + + // Maps of the DSTLFIR UCS bits to their relevant channel fail + // configuration bit in DSTLCFG2. Ex: {12,28} = DSTLFIR[12], DSTLCFG2[28] + // NOTE: there is a separate map for each subchannel. + const std::map<uint8_t,uint8_t> dstlfirMapChanA = + { {12,28}, {16,30}, {22,24} }; + + const std::map<uint8_t,uint8_t> dstlfirMapChanB = + { {13,29}, {17,31}, {23,25} }; + + // Check the DSTLFIR for UCS + SCAN_COMM_REGISTER_CLASS * fir = i_mcc->getRegister( "DSTLFIR" ); + SCAN_COMM_REGISTER_CLASS * mask = i_mcc->getRegister( "DSTLFIR_MASK" ); + SCAN_COMM_REGISTER_CLASS * act0 = i_mcc->getRegister( "DSTLFIR_ACT0" ); + SCAN_COMM_REGISTER_CLASS * act1 = i_mcc->getRegister( "DSTLFIR_ACT1" ); + SCAN_COMM_REGISTER_CLASS * cnfg = i_mcc->getRegister( "DSTLCFG2" ); + + if ( SUCCESS == (fir->Read() | mask->Read() | act0->Read() | act1->Read() | + cnfg->Read()) ) + { + // Get which relevant channel we need to check. + std::map<uint8_t,uint8_t> dstlfirMap; + dstlfirMap = (0 == omiPos) ? dstlfirMapChanA : dstlfirMapChanB; + + for ( auto const & bits : dstlfirMap ) + { + uint8_t firBit = bits.first; + uint8_t cnfgBit = bits.second; + + // NOTE: Channel fail is enabled if the config bit is set to 0b0 + if ( !cnfg->IsBitSet(cnfgBit) && fir->IsBitSet(firBit) && + !mask->IsBitSet(firBit) && act0->IsBitSet(firBit) && + act1->IsBitSet(firBit) ) + { + o_activeAttn = true; + } + } + } + + // Maps of the USTLFIR UCS bits to their relevant channel fail + // config bit in USTLFAILMASK. Ex: {0,54} = USTLFIR[0], USTLFAILMASK[54] + // NOTE: there is a separate map for each subchannel. + const std::map<uint8_t,uint8_t> ustlfirMapChanA = + { { 0,54}, { 2,48}, {27,56}, {35,49}, {37,50}, {39,51}, {41,52}, {43,53}, + {49,55}, {51,50}, {53,50}, {55,48}, {59,56} }; + const std::map<uint8_t,uint8_t> ustlfirMapChanB = + { { 1,54}, { 3,48}, {28,56}, {36,49}, {38,50}, {40,51}, {42,52}, {44,53}, + {50,55}, {52,50}, {54,50}, {56,48}, {60,56} }; + + // Check the USTLFIR for UCS + fir = i_mcc->getRegister( "USTLFIR" ); + mask = i_mcc->getRegister( "USTLFIR_MASK" ); + act0 = i_mcc->getRegister( "USTLFIR_ACT0" ); + act1 = i_mcc->getRegister( "USTLFIR_ACT1" ); + cnfg = i_mcc->getRegister( "USTLFAILMASK" ); + + if ( SUCCESS == (fir->Read() | mask->Read() | act0->Read() | act1->Read() | + cnfg->Read()) ) + { + // Get which relevant channel we need to check. + std::map<uint8_t,uint8_t> ustlfirMap; + ustlfirMap = (0 == omiPos) ? ustlfirMapChanA : ustlfirMapChanB; + + for ( auto const & bits : ustlfirMap ) + { + uint8_t firBit = bits.first; + uint8_t cnfgBit = bits.second; + + // NOTE: Channel fail is enabled if the config bit is set to 0b0 + if ( !cnfg->IsBitSet(cnfgBit) && fir->IsBitSet(firBit) && + !mask->IsBitSet(firBit) && act0->IsBitSet(firBit) && + act1->IsBitSet(firBit) ) + { + o_activeAttn = true; + } + } + } + + return o_activeAttn; +} + +bool __queryUcsOcmb( ExtensibleChip * i_ocmb ) +{ + PRDF_ASSERT( nullptr != i_ocmb ); + PRDF_ASSERT( TYPE_OCMB_CHIP == i_ocmb->getType() ); + + bool o_activeAttn = false; + + // We can't use the GLOBAL_CS_FIR. It will not clear automatically when a + // channel has failed because the hardware clocks have stopped. Also, since + // it is a virtual register there really is no way to clear it. Fortunately + // we have the INTER_STATUS_REG that will tell us if there is an active + // attention. Note that we clear this register as part of the channel + // failure cleanup. So we can rely on this register to determine if there is + // a new channel failure. + + SCAN_COMM_REGISTER_CLASS * fir = i_ocmb->getRegister("INTER_STATUS_REG"); + + if ( SUCCESS == fir->Read() ) + { + o_activeAttn = fir->IsBitSet(2); // Checkstop bit. + } + + return o_activeAttn; +} + +//------------------------------------------------------------------------------ + +template<TARGETING::TYPE T> +bool __analyzeChnlFail( TargetHandle_t i_trgt, + STEP_CODE_DATA_STRUCT & io_sc ); + +template<> +bool __analyzeChnlFail<TYPE_OMI>( TargetHandle_t i_omi, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + #define PRDF_FUNC "[MemUtils::__analyzeChnlFail<TYPE_OMI>] " + + PRDF_ASSERT( nullptr != i_omi ); + PRDF_ASSERT( TYPE_OMI == getTargetType(i_omi) ); + + uint32_t o_analyzed = false; + + do + { + // Skip if currently analyzing a host attention. This is a required for + // a rare scenario when a channel failure occurs after PRD is called to + // handle the host attention. + if ( HOST_ATTN == io_sc.service_data->getPrimaryAttnType() ) break; + + // Get the needed ExtensibleChips for analysis + TargetHandle_t ocmb = getConnectedChild( i_omi, TYPE_OCMB_CHIP, 0 ); + ExtensibleChip * ocmbChip = (ExtensibleChip *)systemPtr->GetChip(ocmb); + + TargetHandle_t omic = getConnectedParent( i_omi, TYPE_OMIC ); + ExtensibleChip * omicChip = (ExtensibleChip *)systemPtr->GetChip(omic); + + TargetHandle_t mcc = getConnectedParent( i_omi, TYPE_MCC ); + ExtensibleChip * mccChip = (ExtensibleChip *)systemPtr->GetChip(mcc); + + // Do an initial query for channel fail attentions from the targets. + // This is to check whether we actually have an active channel fail + // attention before checking whether it is a side effect of some + // recoverable attention or not. + if ( !__queryUcsOmic(omicChip, mccChip, i_omi) && + !__queryUcsMcc(mccChip, i_omi) && + !__queryUcsOcmb(ocmbChip) ) + { + // If no channel fail attentions found, just break out. + break; + } + + // There was a channel fail found, so take the following actions. + + // Set the MEM_CHNL_FAIL flag in the SDC to indicate a channel failure + // has been detected and there is no need to check again. + io_sc.service_data->setMemChnlFail(); + + // Make the error log predictive and set threshold. + io_sc.service_data->setFlag( ServiceDataCollector::SERVICE_CALL ); + io_sc.service_data->setFlag( ServiceDataCollector::AT_THRESHOLD ); + + // Channel failures will always send SUEs. + io_sc.service_data->setFlag( ServiceDataCollector::UERE ); + + // Indicate cleanup is required on this channel. + getOcmbDataBundle(ocmbChip)->iv_doChnlFailCleanup = true; + + // Check for recoverable attentions that could have a channel failure + // as a side effect. These include: N/A + // TODO RTC 243518 -requires more input from the test team to determine + + // Check OMIC for unit checkstops + if ( __queryUcsOmic( omicChip, mccChip, i_omi ) ) + { + // Analyze UNIT_CS on the OMIC chip + // Note: The OMIDLFIR can't actually be set up to report UNIT_CS + // attentions, instead, as a workaround, the relevant channel fail + // bits will be set as recoverable bits and we will manually set + // the attention types to UNIT_CS in our handling of those errors. + if ( SUCCESS == omicChip->Analyze(io_sc, RECOVERABLE) ) + { + o_analyzed = true; + break; + } + } + + // Check MCC for unit checkstops + if ( __queryUcsMcc( mccChip, i_omi ) ) + { + // Analyze UNIT_CS on the MCC chip + if ( SUCCESS == mccChip->Analyze(io_sc, UNIT_CS) ) + { + o_analyzed = true; + break; + } + } + + // Check OCMB for unit checkstops + if ( __queryUcsOcmb( ocmbChip ) ) + { + // Analyze UNIT_CS on the OCMB chip + if ( SUCCESS == ocmbChip->Analyze(io_sc, UNIT_CS) ) + { + o_analyzed = true; + break; + } + + } + PRDF_INF( PRDF_FUNC "Failed channel detected on 0x%08x, but no active " + "attentions found", getHuid(i_omi) ); + }while(0); + + return o_analyzed; + + #undef PRDF_FUNC +} + +template<> +bool analyzeChnlFail<TYPE_MCC>( ExtensibleChip * i_mcc, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + PRDF_ASSERT( nullptr != i_mcc ); + PRDF_ASSERT( TYPE_MCC == i_mcc->getType() ); + + uint32_t o_analyzed = false; + + if ( !io_sc.service_data->isMemChnlFail() ) + { + // Loop through all the connected OMIs + for ( auto & omi : getConnected(i_mcc->getTrgt(), TYPE_OMI) ) + { + o_analyzed = __analyzeChnlFail<TYPE_OMI>( omi, io_sc ); + if ( o_analyzed ) break; + } + } + + return o_analyzed; +} + +template<> +bool analyzeChnlFail<TYPE_OMIC>( ExtensibleChip * i_omic, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + PRDF_ASSERT( nullptr != i_omic ); + PRDF_ASSERT( TYPE_OMIC == i_omic->getType() ); + + uint32_t o_analyzed = false; + + if ( !io_sc.service_data->isMemChnlFail() ) + { + // Loop through all the connected OMIs + for ( auto & omi : getConnected(i_omic->getTrgt(), TYPE_OMI) ) + { + o_analyzed = __analyzeChnlFail<TYPE_OMI>( omi, io_sc ); + if ( o_analyzed ) break; + } + } + + return o_analyzed; +} + +template<> +bool analyzeChnlFail<TYPE_OCMB_CHIP>( ExtensibleChip * i_ocmb, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + PRDF_ASSERT( nullptr != i_ocmb ); + PRDF_ASSERT( TYPE_OCMB_CHIP == i_ocmb->getType() ); + + uint32_t o_analyzed = false; + + if ( !io_sc.service_data->isMemChnlFail() ) + { + TargetHandle_t omi = getConnectedParent( i_ocmb->getTrgt(), TYPE_OMI ); + o_analyzed = __analyzeChnlFail<TYPE_OMI>( omi, io_sc ); + } + + return o_analyzed; +} + +//------------------------------------------------------------------------------ + template<TARGETING::TYPE T1, TARGETING::TYPE T2, TARGETING::TYPE T3> void __cleanupChnlFail( ExtensibleChip * i_chip1, ExtensibleChip * i_chip2, ExtensibleChip * i_chip3, @@ -1415,6 +1823,158 @@ void cleanupChnlFail<TYPE_MEMBUF>( ExtensibleChip * i_chip, cleanupChnlFail<TYPE_DMI>( dmiChip, io_sc ); } +template<TARGETING::TYPE T> +void __cleanupChnlFail( TargetHandle_t i_trgt, STEP_CODE_DATA_STRUCT & io_sc ); + +template<> +void __cleanupChnlFail<TYPE_OMI>( TargetHandle_t i_omi, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + #define PRDF_FUNC "[MemUtils::__cleanupChnlFail] " + + PRDF_ASSERT( nullptr != i_omi ); + PRDF_ASSERT( TYPE_OMI == getTargetType(i_omi) ); + + do + { + // No cleanup if this is a checkstop attention. + if ( CHECK_STOP == io_sc.service_data->getPrimaryAttnType() ) break; + + TargetHandle_t ocmb = getConnectedChild(i_omi, TYPE_OCMB_CHIP, 0); + ExtensibleChip * ocmbChip = (ExtensibleChip *)systemPtr->GetChip(ocmb); + + // Check if cleanup is still required or has already been done. + if ( !getOcmbDataBundle(ocmbChip)->iv_doChnlFailCleanup ) break; + + // Cleanup is complete and no longer required on this channel. + getOcmbDataBundle(ocmbChip)->iv_doChnlFailCleanup = false; + + #ifdef __HOSTBOOT_MODULE // only do cleanup in Hostboot, no-op in FSP + + TargetHandle_t omic = getConnectedParent( i_omi, TYPE_OMIC ); + ExtensibleChip * omicChip = (ExtensibleChip *)systemPtr->GetChip(omic); + + TargetHandle_t mcc = getConnectedParent( i_omi, TYPE_MCC ); + ExtensibleChip * mccChip = (ExtensibleChip *)systemPtr->GetChip(mcc); + + // Get the OMI position relative to the OMIC (0,1,2) and the MCC (0,1) + uint8_t omiPosRelOmic = i_omi->getAttr<ATTR_OMI_DL_GROUP_POS>(); + uint8_t omiPosRelMcc = getTargetPosition(i_omi) % MAX_OMI_PER_MCC; + + // Note that this is a clean up function. If there are any SCOM errors + // we will just move on and try the rest. + SCAN_COMM_REGISTER_CLASS * reg = nullptr; + + // Mask off attentions from the OMIDLFIR in the OMIC based on the + // OMI position. 0-19, 20-39, 40-59 + reg = omicChip->getRegister( "OMIDLFIR_MASK_OR" ); + reg->SetBitFieldJustified( (omiPosRelOmic * 20), 20, 0xfffff ); + reg->Write(); + + // Mask off attentions from the DSTLFIR and USTLFIR in the MCC based on + // the OMI position. + // DSTLFIR Generic Bits: 8,9,10,11,24,25,26,27 + uint64_t mask = 0x00f000f000000000ull; + if ( 0 == omiPosRelMcc ) + { + // DSTLFIR Subchannel A Bits: 0,1,2,3,12,14,16,18,20,22 + mask |= 0xf00aaa0000000000ull; + } + else + { + // DSTLFIR Subchannel B Bits: 4,5,6,7,13,15,17,19,21,23 + mask |= 0x0f05550000000000ull; + } + reg = mccChip->getRegister( "DSTLFIR_MASK_OR" ); + reg->SetBitFieldJustified( 0, 64, mask ); + reg->Write(); + + // USTLFIR Generic Bits: 6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21, + // 22,23,24,25,26,57,58,61,62,63 + mask = 0x03ffffe000000067ull; + if ( 0 == omiPosRelMcc ) + { + // USTLFIR Subchannel A Bits: 0,2,4,27,29,31,33,35,37,39,41,43,45, + // 47,49,51,53,55,59 + mask |= 0xa800001555555510ull; + } + else + { + // USTLFIR Subchannel B Bits: 1,3,5,28,30,32,34,36,38,40,42,44,46, + // 48,50,52,54,56,60 + mask |= 0x5400000aaaaaaa88ull; + } + reg = mccChip->getRegister( "USTLFIR_MASK_OR" ); + reg->SetBitFieldJustified( 0, 64, mask ); + reg->Write(); + + // Mask off all attentions from the chiplet FIRs in the OCMB + reg = ocmbChip->getRegister( "OCMB_CHIPLET_FIR_MASK" ); + reg->setAllBits(); // Blindly mask everything + reg->Write(); + + + // To ensure FSP ATTN doesn't think there is an active attention on this + // OCMB, manually clear the interrupt status register. + reg = ocmbChip->getRegister( "INTER_STATUS_REG" ); + reg->clearAllBits(); // Blindly clear everything + reg->Write(); + + // During runtime, send a dynamic memory deallocation message. + // During Memory Diagnostics, tell MDIA to stop pattern tests. + #ifdef __HOSTBOOT_RUNTIME + MemDealloc::port<TYPE_OCMB_CHIP>( ocmbChip ); + #else + if ( isInMdiaMode() ) + { + mdiaSendEventMsg( ocmb, MDIA::STOP_TESTING ); + } + #endif + + #endif // Hostboot only + + }while(0); + + #undef PRDF_FUNC +} + +template<> +void cleanupChnlFail<TYPE_MCC>( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + PRDF_ASSERT( nullptr != i_chip ); + PRDF_ASSERT( TYPE_MCC == i_chip->getType() ); + + for ( auto & omi : getConnected(i_chip->getTrgt(), TYPE_OMI) ) + { + __cleanupChnlFail<TYPE_OMI>( omi, io_sc ); + } +} + +template<> +void cleanupChnlFail<TYPE_OMIC>( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + PRDF_ASSERT( nullptr != i_chip ); + PRDF_ASSERT( TYPE_OMIC == i_chip->getType() ); + + for ( auto & omi : getConnected(i_chip->getTrgt(), TYPE_OMI) ) + { + __cleanupChnlFail<TYPE_OMI>( omi, io_sc ); + } +} + +template<> +void cleanupChnlFail<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + PRDF_ASSERT( nullptr != i_chip ); + PRDF_ASSERT( TYPE_OCMB_CHIP == i_chip->getType() ); + + TargetHandle_t omi = getConnectedParent( i_chip->getTrgt(), TYPE_OMI ); + __cleanupChnlFail<TYPE_OMI>( omi, io_sc ); +} + //------------------------------------------------------------------------------ uint64_t reverseBits( uint64_t i_val, uint64_t i_numBits ) diff --git a/src/usr/diag/prdf/common/plat/mem/prdfMemUtils.H b/src/usr/diag/prdf/common/plat/mem/prdfMemUtils.H index 9759cd010..39a6051fe 100755 --- a/src/usr/diag/prdf/common/plat/mem/prdfMemUtils.H +++ b/src/usr/diag/prdf/common/plat/mem/prdfMemUtils.H @@ -102,12 +102,12 @@ int32_t collectCeStats( ExtensibleChip * i_chip, const MemRank & i_rank, /** * @brief Gets DRAM size for an MBA, MCA, or MEM_PORT. - * @param i_chip MBA, MCA, or MEM_PORT chip. + * @param i_trgt MBA, MCA, or MEM_PORT target. * @param i_dimmSlct DIMM select. Optional for MBA chip. * @return size for a DRAM */ template<TARGETING::TYPE T> -uint8_t getDramSize( ExtensibleChip * i_chip, uint8_t i_dimmSlct = 0 ); +uint8_t getDramSize( TARGETING::TargetHandle_t i_trgt, uint8_t i_dimmSlct = 0 ); /** * @brief determines the type of Centaur based raw card associated with MBA. diff --git a/src/usr/diag/prdf/common/plat/mem/prdfMemoryMru.C b/src/usr/diag/prdf/common/plat/mem/prdfMemoryMru.C index bb911847e..4cd596514 100755 --- a/src/usr/diag/prdf/common/plat/mem/prdfMemoryMru.C +++ b/src/usr/diag/prdf/common/plat/mem/prdfMemoryMru.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2018 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -70,42 +70,78 @@ MemoryMru::MemoryMru( uint32_t i_memMru ) : PRDF_ASSERT( false ); } - // If our target is MBA, get the chnlPos from the membuf - if ( 0 == iv_memMruMeld.s.isMca ) + // If our target is MCA + if ( 1 == iv_memMruMeld.s.isMca ) { - TargetHandle_t membuf = getConnectedChild( proc, TYPE_MEMBUF, + iv_target = getConnectedChild( proc, TYPE_MCA, iv_memMruMeld.s.chnlPos ); - if ( NULL == membuf ) + if ( NULL == iv_target ) { - PRDF_ERR( PRDF_FUNC "Could not find functional membuf " + PRDF_ERR( PRDF_FUNC "Could not find functional mca " "attached to proc 0x%08X at pos: %u", getHuid( proc ), iv_memMruMeld.s.chnlPos ); PRDF_ASSERT( false ); } + } + // If our target is OCMB + else if ( 1 == iv_memMruMeld.s.isOcmb ) + { + // chnlPos specifies the position of the MCC relative to the proc + TargetHandle_t mcc = getConnectedChild( proc, TYPE_MCC, + iv_memMruMeld.s.chnlPos ); + if ( nullptr == mcc ) + { + PRDF_ERR( PRDF_FUNC "Could not find functional mcc attached to " + "proc 0x%08x at pos: %u", getHuid(proc), + iv_memMruMeld.s.chnlPos ); + PRDF_ASSERT( false ); + } - iv_target = getConnectedChild( membuf, TYPE_MBA, - iv_memMruMeld.s.mbaPos ); - if ( NULL == iv_target ) + // mbaPos specifies the position of the OMI relative to the MCC + TargetHandle_t omi = getConnectedChild( mcc, TYPE_OMI, + iv_memMruMeld.s.mbaPos ); + if ( nullptr == omi ) { - PRDF_ERR( PRDF_FUNC "Could not find functional mba attached " - "to 0x%08X at pos: %u", getHuid( membuf ), - iv_memMruMeld.s.mbaPos ); + PRDF_ERR( PRDF_FUNC "Could not find functional omi attached to " + "mcc 0x%08x at pos: %u", getHuid(mcc), + iv_memMruMeld.s.mbaPos ); + PRDF_ASSERT( false ); + } + + // There is only one OCMB attached per OMI + iv_target = getConnectedChild( omi, TYPE_OCMB_CHIP, 0 ); + if ( nullptr == iv_target ) + { + PRDF_ERR( PRDF_FUNC "Could not find functional ocmb attached to " + "omi 0x%08x", getHuid(mcc) ); PRDF_ASSERT( false ); } + + } + // If our target is MBA, get the chnlPos from the membuf else { - iv_target = getConnectedChild( proc, TYPE_MCA, + TargetHandle_t membuf = getConnectedChild( proc, TYPE_MEMBUF, iv_memMruMeld.s.chnlPos ); - if ( NULL == iv_target ) + if ( nullptr == membuf ) { - PRDF_ERR( PRDF_FUNC "Could not find functional mca " + PRDF_ERR( PRDF_FUNC "Could not find functional membuf " "attached to proc 0x%08X at pos: %u", getHuid( proc ), iv_memMruMeld.s.chnlPos ); PRDF_ASSERT( false ); } - } + iv_target = getConnectedChild( membuf, TYPE_MBA, + iv_memMruMeld.s.mbaPos ); + if ( nullptr == iv_target ) + { + PRDF_ERR( PRDF_FUNC "Could not find functional mba attached " + "to 0x%08X at pos: %u", getHuid( membuf ), + iv_memMruMeld.s.mbaPos ); + PRDF_ASSERT( false ); + } + } // Get the rank iv_rank = MemRank( iv_memMruMeld.s.mrank, iv_memMruMeld.s.srank ); @@ -247,7 +283,8 @@ TargetHandleList MemoryMru::getCalloutList() const } } } - else if ( TARGETING::TYPE_MCA == getTargetType(iv_target) ) + else if ( TARGETING::TYPE_MCA == getTargetType(iv_target) || + TARGETING::TYPE_OCMB_CHIP == getTargetType(iv_target) ) { if ( CALLOUT_ALL_MEM == iv_special ) { @@ -304,6 +341,11 @@ void MemoryMru::getCommonVars() { proc = getConnectedParent( iv_target, TYPE_PROC ); } + else if ( TYPE_OCMB_CHIP == trgtType ) + { + TargetHandle_t mcc = getConnectedParent( iv_target, TYPE_MCC ); + proc = getConnectedParent( mcc, TYPE_PROC ); + } else { PRDF_ERR( PRDF_FUNC "Invalid target type" ); @@ -323,11 +365,27 @@ void MemoryMru::getCommonVars() } // If our target is an MCA, then chnlPos will specify the MCA position // and mbaPos will be an unused field - else + else if ( TYPE_MCA == getTargetType(iv_target) ) { iv_memMruMeld.s.isMca = 1; iv_memMruMeld.s.chnlPos = getTargetPosition( iv_target ); } + // If our target is an OCMB, then chnlPos will specify the MCC position and + // mbaPos will specify the OMI position. + else if ( TYPE_OCMB_CHIP == getTargetType(iv_target) ) + { + TargetHandle_t omi = getConnectedParent( iv_target, TYPE_OMI ); + TargetHandle_t mcc = getConnectedParent( omi, TYPE_MCC ); + + iv_memMruMeld.s.isOcmb = 1; + iv_memMruMeld.s.chnlPos = getTargetPosition(mcc) % MAX_MCC_PER_PROC; + iv_memMruMeld.s.mbaPos = getTargetPosition(omi) % MAX_OMI_PER_MCC; + } + else + { + PRDF_ERR( PRDF_FUNC "Invalid target type" ); + PRDF_ASSERT(false); + } iv_memMruMeld.s.nodePos = getTargetPosition( node ); iv_memMruMeld.s.procPos = getTargetPosition( proc ); diff --git a/src/usr/diag/prdf/common/plat/mem/prdfOcmbDataBundle.H b/src/usr/diag/prdf/common/plat/mem/prdfOcmbDataBundle.H new file mode 100644 index 000000000..75d7dd53e --- /dev/null +++ b/src/usr/diag/prdf/common/plat/mem/prdfOcmbDataBundle.H @@ -0,0 +1,247 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/diag/prdf/common/plat/mem/prdfOcmbDataBundle.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +#ifndef __prdfOcmbDataBundle_H +#define __prdfOcmbDataBundle_H + +/** @file prdfOcmbDataBundle.H + * @brief Contains the data bundle for a P9 OCMB_CHIP object. + */ + +// Framework includes +#include <prdfExtensibleChip.H> + +// Platform includes +#include <prdfPlatServices.H> +#include <prdfMemCeTable.H> +#include <prdfMemUeTable.H> + +#ifdef __HOSTBOOT_MODULE + +#include <prdfMemScrubUtils.H> +#include <prdfMemTdFalseAlarm.H> +#include <prdfMemThresholds.H> +#include <prdfMemTdCtlr.H> + +#ifndef __HOSTBOOT_RUNTIME +#include <prdfMemIplCeStats.H> +#endif + +#endif // __HOSTBOOT_MODULE + +namespace PRDF +{ + +/** @brief P9 OCMB data bundle. */ +class OcmbDataBundle : public DataBundle +{ + public: // functions + + /** + * @brief Constructor. + * @param i_ocmbChip The OCMB chip. + */ + explicit OcmbDataBundle( ExtensibleChip * i_ocmbChip ) : + iv_chip(i_ocmbChip), iv_ceTable(i_ocmbChip), iv_ueTable(i_ocmbChip) + {} + + /** @brief Destructor. */ + ~OcmbDataBundle() + { + #ifdef __HOSTBOOT_MODULE + #ifdef __HOSTBOOT_RUNTIME + delete iv_vcmFalseAlarmCounter; + delete iv_tpsFalseAlarmCounter; + #else // IPL only + delete iv_iplCeStats; + #endif + delete iv_tdCtlr; iv_tdCtlr = nullptr; + #endif // __HOSTBOOT_MODULE + } + + // Don't allow copy or assignment. + OcmbDataBundle( const OcmbDataBundle & ) = delete; + const OcmbDataBundle & operator=( const OcmbDataBundle & ) = delete; + + #ifdef __HOSTBOOT_MODULE + + /** @return The Targeted Diagnostics controller. */ + MemTdCtlr<TARGETING::TYPE_OCMB_CHIP> * getTdCtlr() + { + if ( nullptr == iv_tdCtlr ) + { + iv_tdCtlr = new MemTdCtlr<TARGETING::TYPE_OCMB_CHIP>{iv_chip}; + } + + return iv_tdCtlr; + } + + /** @return The IMPE threshold counter. */ + VcmFalseAlarm * getImpeThresholdCounter() + { + if ( nullptr == iv_impeThresholdCounter ) + { + iv_impeThresholdCounter = new VcmFalseAlarm( + TimeBasedThreshold { getImpeTh() } ); + } + + return iv_impeThresholdCounter; + } + + #ifdef __HOSTBOOT_RUNTIME + + /** @return The VCM false alarm counter. */ + VcmFalseAlarm * getVcmFalseAlarmCounter() + { + if ( nullptr == iv_vcmFalseAlarmCounter ) + { + iv_vcmFalseAlarmCounter = new VcmFalseAlarm( + TimeBasedThreshold { 4, ThresholdResolution::ONE_DAY } ); + } + + return iv_vcmFalseAlarmCounter; + } + + /** @return The TPS false alarm counter. */ + TpsFalseAlarm * getTpsFalseAlarmCounter() + { + if ( nullptr == iv_tpsFalseAlarmCounter ) + { + iv_tpsFalseAlarmCounter = new TpsFalseAlarm( + TimeBasedThreshold{ 3, ThresholdResolution::ONE_DAY } ); + } + + return iv_tpsFalseAlarmCounter; + } + + #else // IPL only + + /** @return The IPL CE statistics object. */ + MemIplCeStats<TARGETING::TYPE_OCMB_CHIP> * getIplCeStats() + { + if ( nullptr == iv_iplCeStats ) + { + iv_iplCeStats = + new MemIplCeStats<TARGETING::TYPE_OCMB_CHIP>( iv_chip ); + } + + return iv_iplCeStats; + } + + #endif + + #endif // __HOSTBOOT_MODULE + + private: // instance variables + + /** The OCMB chip associated with this data bundle. */ + ExtensibleChip * const iv_chip; + + #ifdef __HOSTBOOT_MODULE + + /** The Targeted Diagnostics controller. */ + MemTdCtlr<TARGETING::TYPE_OCMB_CHIP> * iv_tdCtlr = nullptr; + + /** IMPE threshold counter. */ + VcmFalseAlarm * iv_impeThresholdCounter = nullptr; + + #endif // __HOSTBOOT_MODULE + + public: // instance variables + + MemCeTable<TARGETING::TYPE_OCMB_CHIP> iv_ceTable; ///< CE table for FFDC + MemUeTable iv_ueTable; ///< UE table for FFDC + + /** If there is a channel failure detected on this bus, there will be some + * required cleanup after analysis to mask off all further attentions from + * the bus. A channel failure could occur on either side of the bus and it + * is possible the cleanup function could be called in multiple + * PostAnalysis plugins depending on where the channel failure occurred. + * Since we only want to do one cleanup, we will use this variable to + * indicate if a cleanup is still required or has already been done. */ + bool iv_doChnlFailCleanup = false; + + #ifdef __HOSTBOOT_MODULE + + /** Threshold table for RCD parity errors. */ + TimeBasedThreshold iv_rcdParityTh = TimeBasedThreshold( getRcdParityTh() ); + + /** Threshold table for IUEs. Threshold per DIMM */ + std::map<uint8_t, TimeBasedThreshold> iv_iueTh; + + /** Bool to indicate if we've triggered a port fail because of IUEs. */ + bool iv_iuePortFail = false; + + #ifdef __HOSTBOOT_RUNTIME + + /** VCM false alarm counter. */ + VcmFalseAlarm * iv_vcmFalseAlarmCounter = nullptr; + + /** TPS false alarm counter. */ + TpsFalseAlarm * iv_tpsFalseAlarmCounter = nullptr; + + /** Set to true if mainline NCEs and TCEs should be permanently masked. This + * is checked at the end of targeted diagnostics before background + * scrubbing is resumed. */ + bool iv_maskMainlineNceTce = false; + + // These are used to limit the number of times a scrub command will stop + // on a UE or CE on a rank. This is to prevent potential flooding of + // maintenance UEs or CEs. The threshold will be 16 per rank for each. + TimeBasedThreshold iv_ueStopCounter = + TimeBasedThreshold( 16, ThresholdResolution::TEN_HOURS ); + TimeBasedThreshold iv_ceStopCounter = + TimeBasedThreshold( 16, ThresholdResolution::TEN_HOURS );; + + // If we stop on a UE or a CE, we will need to store the rank that the + // error is on so that we can clear our respective thresholds if the + // next error we stop on is on a different rank. + MemRank iv_ceUeRank; + + #else // IPL only + + /** MNFG IPL CE statistics. */ + MemIplCeStats<TARGETING::TYPE_OCMB_CHIP> * iv_iplCeStats = nullptr; + + #endif + + #endif // __HOSTBOOT_MODULE + +}; + +/** + * @brief Wrapper function for the OcmbDataBundle. + * @param i_ocmbChip The OCMB chip. + * @return This MBA's data bundle. + */ +inline OcmbDataBundle * getOcmbDataBundle( ExtensibleChip * i_ocmbChip ) +{ + return static_cast<OcmbDataBundle *>(i_ocmbChip->getDataBundle()); +} + +} // end namespace PRDF + +#endif // __prdfOcmbDataBundle_H + diff --git a/src/usr/diag/prdf/common/plat/mem/prdf_plat_mem.mk b/src/usr/diag/prdf/common/plat/mem/prdf_plat_mem.mk index 087214ece..2ea0712d3 100644 --- a/src/usr/diag/prdf/common/plat/mem/prdf_plat_mem.mk +++ b/src/usr/diag/prdf/common/plat/mem/prdf_plat_mem.mk @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2016,2018 +# Contributors Listed Below - COPYRIGHT 2016,2019 # [+] International Business Machines Corp. # # @@ -51,6 +51,7 @@ prd_obj += prdfMemoryMru.o prd_obj += prdfMemUeTable.o prd_obj += prdfMemUtils.o prd_obj += prdfMemThresholds.o +prd_obj += prdfP9OcmbChipDomain.o # rule plugin related prd_rule_plugin += prdfP9Mca_common.o diff --git a/src/usr/diag/prdf/common/plat/nimbus/nimbus_mca.rule b/src/usr/diag/prdf/common/plat/nimbus/nimbus_mca.rule index eea254545..d1a6bc290 100644 --- a/src/usr/diag/prdf/common/plat/nimbus/nimbus_mca.rule +++ b/src/usr/diag/prdf/common/plat/nimbus/nimbus_mca.rule @@ -241,7 +241,7 @@ group gMCACALFIR /** MCACALFIR[0] * A MBA recoverable error has occurred. */ - (rMCACALFIR, bit(0)) ? self_th_1; + (rMCACALFIR, bit(0)) ? nvdimm_self_th_1; /** MCACALFIR[1] * MBA Nonrecoverable Error @@ -251,7 +251,7 @@ group gMCACALFIR /** MCACALFIR[2] * Excessive refreshes to a single rank. */ - (rMCACALFIR, bit(2)) ? self_th_32perDay; + (rMCACALFIR, bit(2)) ? nvdimm_self_th_32perDay; /** MCACALFIR[3] * Err detected in the MBA debug WAT logic @@ -266,7 +266,7 @@ group gMCACALFIR /** MCACALFIR[5] * Calibration complete indication xout */ - (rMCACALFIR, bit(5)) ? self_th_32perDay; + (rMCACALFIR, bit(5)) ? nvdimm_self_th_32perDay; /** MCACALFIR[6] * Emergency Throttle @@ -279,7 +279,7 @@ group gMCACALFIR (rMCACALFIR, bit(7)) ? self_th_1; /** MCACALFIR[8] - * event_n active on DDR interface + * Active NVDIMM Attention */ (rMCACALFIR, bit(8)) ? analyzeNvdimms; @@ -533,7 +533,7 @@ group gMCAECCFIR /** MCAECCFIR[42] * SCOM_PARITY_CLASS_RECOVERABLE */ - (rMCAECCFIR, bit(42)) ? self_th_1; + (rMCAECCFIR, bit(42)) ? nvdimm_self_th_1; /** MCAECCFIR[43] * SCOM_PARITY_CLASS_UNRECOVERABLE @@ -548,7 +548,7 @@ group gMCAECCFIR /** MCAECCFIR[45] * WRITE_RMW_CE */ - (rMCAECCFIR, bit(45)) ? self_th_32perDay; + (rMCAECCFIR, bit(45)) ? nvdimm_self_th_32perDay; /** MCAECCFIR[46] * WRITE_RMW_UE @@ -686,12 +686,12 @@ group gDDRPHYFIR /** DDRPHYFIR[60] * Register PE 4 bit impact */ - (rDDRPHYFIR, bit(60)) ? self_th_1; + (rDDRPHYFIR, bit(60)) ? nvdimm_self_th_1; /** DDRPHYFIR[61] * Register PE 1 bit impact */ - (rDDRPHYFIR, bit(61)) ? self_th_1; + (rDDRPHYFIR, bit(61)) ? nvdimm_self_th_1; }; diff --git a/src/usr/diag/prdf/common/plat/nimbus/nimbus_mca_actions.rule b/src/usr/diag/prdf/common/plat/nimbus/nimbus_mca_actions.rule index da3a73f82..6d5ab9018 100644 --- a/src/usr/diag/prdf/common/plat/nimbus/nimbus_mca_actions.rule +++ b/src/usr/diag/prdf/common/plat/nimbus/nimbus_mca_actions.rule @@ -70,6 +70,7 @@ actionclass rcd_parity_error calloutSelfLowNoGard; # Self LOW # Thresholding done in plugin funccall("RcdParityError"); # Run TPS on TH for all MCA ranks + funccall("ClearNvdimmGardState"); # Clear gard for NVDIMMs }; /** Handle Mainline IUEs */ @@ -125,7 +126,7 @@ actionclass maintenance_iaue_handling /** MCA/UE algroithm, threshold 5 per day */ actionclass mca_ue_algorithm_th_5perDay { - calloutSelfMed; + try( funccall("CheckForNvdimms"), calloutSelfMed ); threshold5pday; funccall("mcaUeAlgorithm"); # must be called last }; @@ -133,12 +134,29 @@ actionclass mca_ue_algorithm_th_5perDay /** MCA/UE algroithm, threshold 1 */ actionclass mca_ue_algorithm_th_1 { - calloutSelfMed; + try( funccall("CheckForNvdimms"), calloutSelfMed ); threshold1; funccall("mcaUeAlgorithm"); # must be called last }; ################################################################################ +# NVDIMM callouts # +################################################################################ + +# Simple callouts that will avoid gard for NVDIMMs at IPL +actionclass nvdimm_self_th_1 +{ + try( funccall("CheckForNvdimms"), calloutSelfMed ); + threshold1; +}; + +actionclass nvdimm_self_th_32perDay +{ + try( funccall("CheckForNvdimms"), calloutSelfMed ); + threshold32pday; +}; + +################################################################################ # Analyze groups ################################################################################ diff --git a/src/usr/diag/prdf/common/plat/nimbus/nimbus_mcbist.rule b/src/usr/diag/prdf/common/plat/nimbus/nimbus_mcbist.rule index 1f61719a7..0a3301e2a 100644 --- a/src/usr/diag/prdf/common/plat/nimbus/nimbus_mcbist.rule +++ b/src/usr/diag/prdf/common/plat/nimbus/nimbus_mcbist.rule @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2016,2018 +# Contributors Listed Below - COPYRIGHT 2016,2019 # [+] International Business Machines Corp. # # @@ -599,7 +599,7 @@ group gMCBISTFIR /** MCBISTFIR[13] * SCOM_RECOVERABLE_REG_PE */ - (rMCBISTFIR, bit(13)) ? self_th_1; + (rMCBISTFIR, bit(13)) ? nvdimm_self_th_1; /** MCBISTFIR[14] * SCOM_FATAL_REG_PE diff --git a/src/usr/diag/prdf/common/plat/nimbus/nimbus_mcbist_actions.rule b/src/usr/diag/prdf/common/plat/nimbus/nimbus_mcbist_actions.rule index 9b2127f3f..11d499e30 100644 --- a/src/usr/diag/prdf/common/plat/nimbus/nimbus_mcbist_actions.rule +++ b/src/usr/diag/prdf/common/plat/nimbus/nimbus_mcbist_actions.rule @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2016,2018 +# Contributors Listed Below - COPYRIGHT 2016,2019 # [+] International Business Machines Corp. # # @@ -36,6 +36,17 @@ actionclass command_addr_timeout funccall("commandAddrTimeout"); }; +################################################################################ +# NVDIMM callouts # +################################################################################ + +# Simple callouts that will avoid gard for NVDIMMs at IPL +actionclass nvdimm_self_th_1 +{ + try( funccall("CheckForNvdimms"), calloutSelfMed ); + threshold1; +}; + ############################################################################### # Analyze groups ############################################################################### diff --git a/src/usr/diag/prdf/common/plat/nimbus/nimbus_mcs.rule b/src/usr/diag/prdf/common/plat/nimbus/nimbus_mcs.rule index 71a0342ab..987d68afb 100644 --- a/src/usr/diag/prdf/common/plat/nimbus/nimbus_mcs.rule +++ b/src/usr/diag/prdf/common/plat/nimbus/nimbus_mcs.rule @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2016,2018 +# Contributors Listed Below - COPYRIGHT 2016,2019 # [+] International Business Machines Corp. # # @@ -148,7 +148,7 @@ group gMCFIR /** MCFIR[0] * mc internal recoverable eror */ - (rMCFIR, bit(0)) ? self_th_1; + (rMCFIR, bit(0)) ? nvdimm_self_th_1; /** MCFIR[1] * mc internal non recovervable error diff --git a/src/usr/diag/prdf/common/plat/nimbus/nimbus_mcs_actions.rule b/src/usr/diag/prdf/common/plat/nimbus/nimbus_mcs_actions.rule index 1497cdccb..35339ccc6 100644 --- a/src/usr/diag/prdf/common/plat/nimbus/nimbus_mcs_actions.rule +++ b/src/usr/diag/prdf/common/plat/nimbus/nimbus_mcs_actions.rule @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2018 +# Contributors Listed Below - COPYRIGHT 2018,2019 # [+] International Business Machines Corp. # # @@ -24,6 +24,17 @@ # IBM_PROLOG_END_TAG ################################################################################ +# NVDIMM callouts # +################################################################################ + +# Simple callouts that will avoid gard for NVDIMMs at IPL +actionclass nvdimm_self_th_1 +{ + try( funccall("CheckForNvdimms"), calloutSelfMed ); + threshold1; +}; + +################################################################################ # Analyze groups ################################################################################ diff --git a/src/usr/diag/prdf/common/plat/nimbus/nimbus_obus.rule b/src/usr/diag/prdf/common/plat/nimbus/nimbus_obus.rule index a4ce0d02d..790537acf 100644 --- a/src/usr/diag/prdf/common/plat/nimbus/nimbus_obus.rule +++ b/src/usr/diag/prdf/common/plat/nimbus/nimbus_obus.rule @@ -469,12 +469,12 @@ group gIOOLFIR /** IOOLFIR[8] * link0 nak received */ - (rIOOLFIR, bit(8)) ? defaultMaskedError; + (rIOOLFIR, bit(8)) ? threshold_and_mask_self_non_smp_only; /** IOOLFIR[9] * link1 nak received */ - (rIOOLFIR, bit(9)) ? defaultMaskedError; + (rIOOLFIR, bit(9)) ? threshold_and_mask_self_non_smp_only; /** IOOLFIR[10] * link0 replay buffer full @@ -499,22 +499,22 @@ group gIOOLFIR /** IOOLFIR[14] * link0 sl ecc correctable */ - (rIOOLFIR, bit(14)) ? threshold_and_mask_self; + (rIOOLFIR, bit(14)) ? threshold_and_mask_self_smp_only; /** IOOLFIR[15] * link1 sl ecc correctable */ - (rIOOLFIR, bit(15)) ? threshold_and_mask_self; + (rIOOLFIR, bit(15)) ? threshold_and_mask_self_smp_only; /** IOOLFIR[16] * link0 sl ecc ue */ - (rIOOLFIR, bit(16)) ? threshold_and_mask_self; + (rIOOLFIR, bit(16)) ? threshold_and_mask_self_smp_only; /** IOOLFIR[17] * link1 sl ecc ue */ - (rIOOLFIR, bit(17)) ? threshold_and_mask_self; + (rIOOLFIR, bit(17)) ? threshold_and_mask_self_smp_only; /** IOOLFIR[18] * link0 retrain threshold @@ -597,12 +597,12 @@ group gIOOLFIR (rIOOLFIR, bit(33)) ? defaultMaskedError; /** IOOLFIR[34] - * link0 num replay + * link0 num replay or no forward progress */ (rIOOLFIR, bit(34)) ? defaultMaskedError; /** IOOLFIR[35] - * link1 num replay + * link1 num replay or no forward progress */ (rIOOLFIR, bit(35)) ? defaultMaskedError; @@ -619,12 +619,12 @@ group gIOOLFIR /** IOOLFIR[38] * link0 prbs select error */ - (rIOOLFIR, bit(38)) ? threshold_and_mask_self; + (rIOOLFIR, bit(38)) ? threshold_and_mask_self_smp_only; /** IOOLFIR[39] * link1 prbs select error */ - (rIOOLFIR, bit(39)) ? threshold_and_mask_self; + (rIOOLFIR, bit(39)) ? threshold_and_mask_self_smp_only; /** IOOLFIR[40] * link0 tcomplete bad @@ -639,102 +639,102 @@ group gIOOLFIR /** IOOLFIR[42] * link0 no spare lane available */ - (rIOOLFIR, bit(42)) ? obusSmpCallout_L0; + (rIOOLFIR, bit(42)) ? obusSmpCallout_L0_smp_only; /** IOOLFIR[43] * link1 no spare lane available */ - (rIOOLFIR, bit(43)) ? obusSmpCallout_L1; + (rIOOLFIR, bit(43)) ? obusSmpCallout_L1_smp_only; /** IOOLFIR[44] - * link0 spare done + * link0 spare done or degraded mode */ - (rIOOLFIR, bit(44)) ? obusSmpCallout_th32_L0; + (rIOOLFIR, bit(44)) ? spare_lane_degraded_mode_L0; /** IOOLFIR[45] - * link1 spare done + * link1 spare done or degraded mode */ - (rIOOLFIR, bit(45)) ? obusSmpCallout_th32_L1; + (rIOOLFIR, bit(45)) ? spare_lane_degraded_mode_L1; /** IOOLFIR[46] * link0 too many crc errors */ - (rIOOLFIR, bit(46)) ? obusSmpCallout_L0; + (rIOOLFIR, bit(46)) ? obusSmpCallout_L0_smp_only; /** IOOLFIR[47] * link1 too many crc errors */ - (rIOOLFIR, bit(47)) ? obusSmpCallout_L1; + (rIOOLFIR, bit(47)) ? obusSmpCallout_L1_smp_only; /** IOOLFIR[48] - * link0 npu error + * link0 npu error or orx otx dlx errors */ (rIOOLFIR, bit(48)) ? threshold_and_mask_self; /** IOOLFIR[49] - * link1 npu error + * link1 npu error or orx otx dlx errors */ (rIOOLFIR, bit(49)) ? threshold_and_mask_self; /** IOOLFIR[50] * linkx npu error */ - (rIOOLFIR, bit(50)) ? threshold_and_mask_self; + (rIOOLFIR, bit(50)) ? threshold_and_mask_self_smp_only; /** IOOLFIR[51] * osc switch */ - (rIOOLFIR, bit(51)) ? threshold_and_mask_self; + (rIOOLFIR, bit(51)) ? threshold_and_mask_self_smp_only; /** IOOLFIR[52] * link0 correctable array error */ - (rIOOLFIR, bit(52)) ? obusSmpCallout_th32_L0; + (rIOOLFIR, bit(52)) ? self_th_32perDay; /** IOOLFIR[53] * link1 correctable array error */ - (rIOOLFIR, bit(53)) ? obusSmpCallout_th32_L1; + (rIOOLFIR, bit(53)) ? self_th_32perDay; /** IOOLFIR[54] * link0 uncorrectable array error */ - (rIOOLFIR, bit(54)) ? obusSmpFailure_L0; + (rIOOLFIR, bit(54)) ? self_th_1; /** IOOLFIR[55] * link1 uncorrectable array error */ - (rIOOLFIR, bit(55)) ? obusSmpFailure_L1; + (rIOOLFIR, bit(55)) ? self_th_1; /** IOOLFIR[56] * link0 training failed */ - (rIOOLFIR, bit(56)) ? obusSmpFailure_L0; + (rIOOLFIR, bit(56)) ? training_failure_L0; /** IOOLFIR[57] * link1 training failed */ - (rIOOLFIR, bit(57)) ? obusSmpFailure_L1; + (rIOOLFIR, bit(57)) ? training_failure_L1; /** IOOLFIR[58] * link0 unrecoverable error */ - (rIOOLFIR, bit(58)) ? obusSmpFailure_L0; + (rIOOLFIR, bit(58)) ? unrecoverable_error_L0; /** IOOLFIR[59] * link1 unrecoverable error */ - (rIOOLFIR, bit(59)) ? obusSmpFailure_L1; + (rIOOLFIR, bit(59)) ? unrecoverable_error_L1; /** IOOLFIR[60] * link0 internal error */ - (rIOOLFIR, bit(60)) ? obusSmpFailure_L0; + (rIOOLFIR, bit(60)) ? internal_error_L0; /** IOOLFIR[61] * link1 internal error */ - (rIOOLFIR, bit(61)) ? obusSmpFailure_L1; + (rIOOLFIR, bit(61)) ? internal_error_L1; /** IOOLFIR[62] * fir scom err dup diff --git a/src/usr/diag/prdf/common/plat/nimbus/nimbus_proc.rule b/src/usr/diag/prdf/common/plat/nimbus/nimbus_proc.rule index 6ac3bc5a1..6712a5977 100644 --- a/src/usr/diag/prdf/common/plat/nimbus/nimbus_proc.rule +++ b/src/usr/diag/prdf/common/plat/nimbus/nimbus_proc.rule @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2016,2018 +# Contributors Listed Below - COPYRIGHT 2016,2019 # [+] International Business Machines Corp. # # @@ -2872,7 +2872,7 @@ group gNXCQFIR /** NXCQFIR[19] * Uncorrectable error on ERAT arrays */ - (rNXCQFIR, bit(19)) ? nx_th_32perDay; + (rNXCQFIR, bit(19)) ? nx_th_1; /** NXCQFIR[20] * SUE on ERAT arrays diff --git a/src/usr/diag/prdf/common/plat/nimbus/nimbus_proc_actions.rule b/src/usr/diag/prdf/common/plat/nimbus/nimbus_proc_actions.rule index 826308710..1960da53b 100644 --- a/src/usr/diag/prdf/common/plat/nimbus/nimbus_proc_actions.rule +++ b/src/usr/diag/prdf/common/plat/nimbus/nimbus_proc_actions.rule @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2018 +# Contributors Listed Below - COPYRIGHT 2018,2019 # [+] International Business Machines Corp. # # @@ -23,9 +23,15 @@ # # IBM_PROLOG_END_TAG -############################################################################### +################################################################################ +# Analyze +################################################################################ + +actionclass analyzeENHCAFIR { analyze(gENHCAFIR); }; + +################################################################################ # Analyze connected -############################################################################### +################################################################################ actionclass analyzeConnectedMCBIST0 { analyze(connected(TYPE_MCBIST, 0)); }; actionclass analyzeConnectedMCBIST1 { analyze(connected(TYPE_MCBIST, 1)); }; diff --git a/src/usr/diag/prdf/common/plat/p9/p9_common_actions.rule b/src/usr/diag/prdf/common/plat/p9/p9_common_actions.rule index 669d3e5b5..2e7e32869 100644 --- a/src/usr/diag/prdf/common/plat/p9/p9_common_actions.rule +++ b/src/usr/diag/prdf/common/plat/p9/p9_common_actions.rule @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2016,2018 +# Contributors Listed Below - COPYRIGHT 2016,2019 # [+] International Business Machines Corp. # # @@ -208,6 +208,12 @@ actionclass parent_proc_th_1 threshold1; }; +actionclass parent_proc_th_32perDay +{ + callout(connected(TYPE_PROC), MRU_MED); + threshold32pday; +}; + actionclass level2_M_proc_L_th_1 { callout2ndLvlMed; @@ -273,4 +279,3 @@ actionclass chip_to_chip calloutSelfMed; threshold1; }; - diff --git a/src/usr/diag/prdf/common/plat/p9/p9_common_obus_actions.rule b/src/usr/diag/prdf/common/plat/p9/p9_common_obus_actions.rule index 6590bb122..700e87649 100644 --- a/src/usr/diag/prdf/common/plat/p9/p9_common_obus_actions.rule +++ b/src/usr/diag/prdf/common/plat/p9/p9_common_obus_actions.rule @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2018 +# Contributors Listed Below - COPYRIGHT 2018,2019 # [+] International Business Machines Corp. # # @@ -88,6 +88,150 @@ actionclass obusSmpFailure_L1 threshold1; }; +actionclass smp_masked +{ + # If SMP mode, does defaultMaskedError action and returns SUCCESS. + # Otherwise, returns PRD_SCAN_COMM_REGISTER_ZERO. + funccall( "smp_masked" ); # If SMP mode +}; + +actionclass non_smp_masked +{ + # If NOT in SMP mode, does defaultMaskedError action and returns SUCCESS. + # Otherwise, returns PRD_SCAN_COMM_REGISTER_ZERO. + funccall( "non_smp_masked" ); +}; + +actionclass non_smp_callout_bus_th_1 +{ + # NOTE: We cannot put the threshold action in this actionclass because it + # will affect the SMP action in the try() statement. Therefore, the + # plugin must handle the thresholding if in non-SMP mode. + + # If NOT in SMP mode: + # - calls out this OBUS + # - indicates the probably may be somewhere between this OBUS and whatever + # is on the other side (which we know nothing about) + # - sets threshold + # - sets service call + # - returns SUCCESS + # Otherwise + # - returns PRD_SCAN_COMM_REGISTER_ZERO + funccall( "non_smp_callout_bus_th_1" ); +}; + +actionclass non_smp_callout_lvl2_th_1 +{ + # NOTE: We cannot put the threshold action in this actionclass because it + # will affect the SMP action in the try() statement. Therefore, the + # plugin must handle the thresholding if in non-SMP mode. + + # If NOT in SMP mode: + # - calls out level 2 support + # - sets threshold + # - sets service call + # - returns SUCCESS + # Otherwise + # - returns PRD_SCAN_COMM_REGISTER_ZERO + funccall( "non_smp_callout_lvl2_th_1" ); +}; + +actionclass non_smp_callout_self_th_32perDay +{ + threshold32pday; # This is ok because it is greater than threshold1. + + # If NOT in SMP mode: + # - calls out this OBUS + # - returns SUCCESS + # Otherwise + # - returns PRD_SCAN_COMM_REGISTER_ZERO + funccall( "non_smp_callout_self" ); +}; + +actionclass threshold_and_mask_self_non_smp_only +{ + # SMP: masked + # Non-SMP: threshold_and_mask_self + try ( smp_masked, threshold_and_mask_self ); +}; + +actionclass threshold_and_mask_self_smp_only +{ + # SMP: threshold_and_mask_self + # Non-SMP: masked + try ( non_smp_masked, threshold_and_mask_self ); +}; + +actionclass obusSmpCallout_L0_smp_only +{ + # SMP: obusSmpCallout_L0 + # Non-SMP: masked + try ( non_smp_masked, obusSmpCallout_L0 ); +}; + +actionclass obusSmpCallout_L1_smp_only +{ + # SMP: obusSmpCallout_L1 + # Non-SMP: masked + try ( non_smp_masked, obusSmpCallout_L1 ); +}; + +actionclass spare_lane_degraded_mode_L0 +{ + # SMP: obusSmpCallout_th32_L0 (lane spare) + # Non-SMP: non_smp_callout_bus_th_1 (degraded mode) + try ( non_smp_callout_bus_th_1, obusSmpCallout_th32_L0 ); +}; + +actionclass spare_lane_degraded_mode_L1 +{ + # SMP: obusSmpCallout_th32_L1 (lane spare) + # Non-SMP: non_smp_callout_bus_th_1 (degraded mode) + try ( non_smp_callout_bus_th_1, obusSmpCallout_th32_L1 ); +}; + +actionclass training_failure_L0 +{ + # SMP: obusSmpFailure_L0 + # Non-SMP: non_smp_callout_lvl2_th_1 + try ( non_smp_callout_lvl2_th_1, obusSmpFailure_L0 ); +}; + +actionclass training_failure_L1 +{ + # SMP: obusSmpFailure_L1 + # Non-SMP: non_smp_callout_lvl2_th_1 + try ( non_smp_callout_lvl2_th_1, obusSmpFailure_L1 ); +}; + +actionclass unrecoverable_error_L0 +{ + # SMP: obusSmpFailure_L0 + # Non-SMP: non_smp_callout_bus_th_1 + try ( non_smp_callout_bus_th_1, obusSmpFailure_L0 ); +}; + +actionclass unrecoverable_error_L1 +{ + # SMP: obusSmpFailure_L1 + # Non-SMP: non_smp_callout_bus_th_1 + try ( non_smp_callout_bus_th_1, obusSmpFailure_L1 ); +}; + +actionclass internal_error_L0 +{ + # SMP: obusSmpFailure_L0 + # Non-SMP: non_smp_callout_self_th_32perDay + try ( non_smp_callout_self_th_32perDay, obusSmpFailure_L0 ); +}; + +actionclass internal_error_L1 +{ + # SMP: obusSmpFailure_L1 + # Non-SMP: non_smp_callout_self_th_32perDay + try ( non_smp_callout_self_th_32perDay, obusSmpFailure_L1 ); +}; + ############################################################################### # Analyze groups ############################################################################### diff --git a/src/usr/diag/prdf/common/plat/p9/p9_common_obus_regs.rule b/src/usr/diag/prdf/common/plat/p9/p9_common_obus_regs.rule index 461fbc664..bc25fba5d 100644 --- a/src/usr/diag/prdf/common/plat/p9/p9_common_obus_regs.rule +++ b/src/usr/diag/prdf/common/plat/p9/p9_common_obus_regs.rule @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2016,2018 +# Contributors Listed Below - COPYRIGHT 2016,2019 # [+] International Business Machines Corp. # # @@ -85,6 +85,13 @@ capture group default; }; + register MISC_ERROR_STATUS + { + name "P9 OBUS target Misc Error Status register"; + scomaddr 0x09010829; + capture group default; + }; + ############################################################################ # P9 OBUS targets for cable FFDC # One additional reg (IOOLFIR) is in default group diff --git a/src/usr/diag/prdf/common/plat/p9/p9_common_proc_actions.rule b/src/usr/diag/prdf/common/plat/p9/p9_common_proc_actions.rule index aacf978bd..e5700c34b 100644 --- a/src/usr/diag/prdf/common/plat/p9/p9_common_proc_actions.rule +++ b/src/usr/diag/prdf/common/plat/p9/p9_common_proc_actions.rule @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2017,2018 +# Contributors Listed Below - COPYRIGHT 2017,2019 # [+] International Business Machines Corp. # # @@ -670,7 +670,6 @@ actionclass analyzePBIOOFIR { analyze(gPBIOOFIR ); }; actionclass analyzePBAFIR { analyze(gPBAFIR ); }; actionclass analyzePSIHBFIR { analyze(gPSIHBFIR ); }; actionclass analyzePBAMFIR { analyze(gPBAMFIR ); }; -actionclass analyzeENHCAFIR { analyze(gENHCAFIR ); }; actionclass analyzeXB_LFIR { analyze(gXB_LFIR ); }; actionclass analyzeXBPPEFIR { analyze(gXBPPEFIR ); }; diff --git a/src/usr/diag/prdf/common/plat/p9/prdfCommonPlugins.C b/src/usr/diag/prdf/common/plat/p9/prdfCommonPlugins.C index ece3fc1a8..730f99f09 100644 --- a/src/usr/diag/prdf/common/plat/p9/prdfCommonPlugins.C +++ b/src/usr/diag/prdf/common/plat/p9/prdfCommonPlugins.C @@ -127,6 +127,88 @@ PRDF_PLUGIN_DEFINE_NS(nimbus_proc, CommonPlugins, ClearServiceCallFlag_mnfgInfo PRDF_PLUGIN_DEFINE_NS(cumulus_proc, CommonPlugins, ClearServiceCallFlag_mnfgInfo); PRDF_PLUGIN_DEFINE_NS(axone_proc, CommonPlugins, ClearServiceCallFlag_mnfgInfo); +/** + * @brief Will change the gard state of any NVDIMMs in the callout list to + * NO_GARD. + * @param i_chip The chip. + * @param io_sc The step code data struct. + * @returns SUCCESS + */ +int32_t ClearNvdimmGardState( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + #ifdef __HOSTBOOT_MODULE + + // Call the sdc to clear the NVDIMM mru list. + io_sc.service_data->clearNvdimmMruListGard(); + + #endif + + return SUCCESS; +} +PRDF_PLUGIN_DEFINE_NS(nimbus_mca, CommonPlugins, ClearNvdimmGardState); + +/** + * @brief Will check if any of the DIMMs connected to this chip are NVDIMMs + * and send a message to PHYP/Hostboot that save/restore may work. If + * we are at IPL, we will callout self no gard instead of garding. + * @param i_chip The chip of the DIMM parent. + * @param io_sc The step code data struct. + * @returns SUCCESS if NVDIMMs found at IPL, PRD_SCAN_COMM_REGISTER_ZERO if not. + */ +int32_t CheckForNvdimms( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + int32_t rc = PRD_SCAN_COMM_REGISTER_ZERO; + + #ifdef CONFIG_NVDIMM + #ifdef __HOSTBOOT_MODULE + + TargetHandleList dimmList = getConnected( i_chip->getTrgt(), TYPE_DIMM ); + + // Always loop through all the dimms so we send the + // nvdimmNotifyProtChange message for all the NVDIMMs on the target. + for ( auto & dimm : dimmList ) + { + // If the callout target is an NVDIMM send a message to + // PHYP/Hostboot that a save/restore may work, and if we are at + // IPL, do not gard the target. + if ( isNVDIMM(dimm) ) + { + // Send the message to PHYP/Hostboot + uint32_t l_rc = PlatServices::nvdimmNotifyProtChange( dimm, + NVDIMM::NVDIMM_RISKY_HW_ERROR ); + if ( SUCCESS != l_rc ) + { + PRDF_TRAC( "CheckForNvdimms: nvdimmNotifyProtChange(0x%08x)" + " failed.", PlatServices::getHuid(dimm) ); + continue; + } + + #ifndef __HOSTBOOT_RUNTIME + // IPL + // We will callout self, no gard. No need for another self callout + // from the rule code, so return SUCCESS. + rc = SUCCESS; + #endif + } + } + + if ( SUCCESS == rc ) + { + // Callout self, no gard + io_sc.service_data->SetCallout( i_chip->getTrgt(), MRU_MED, NO_GARD ); + } + + #endif // __HOSTBOOT_MODULE + #endif // CONFIG_NVDIMM + + return rc; +} +PRDF_PLUGIN_DEFINE_NS(nimbus_mcs, CommonPlugins, CheckForNvdimms); +PRDF_PLUGIN_DEFINE_NS(nimbus_mca, CommonPlugins, CheckForNvdimms); +PRDF_PLUGIN_DEFINE_NS(nimbus_mcbist, CommonPlugins, CheckForNvdimms); + } // namespace CommonPlugins ends }// namespace PRDF ends diff --git a/src/usr/diag/prdf/common/plat/p9/prdfLaneRepair.C b/src/usr/diag/prdf/common/plat/p9/prdfLaneRepair.C index 6cb4e6535..6ad889fd5 100644 --- a/src/usr/diag/prdf/common/plat/p9/prdfLaneRepair.C +++ b/src/usr/diag/prdf/common/plat/p9/prdfLaneRepair.C @@ -75,6 +75,16 @@ TargetHandle_t getTxBusEndPt( TargetHandle_t i_rxTrgt) // grab connected DMI parent o_txTrgt = getConnectedParent( i_rxTrgt, TYPE_DMI ); } + else if ( TYPE_OMI == busType ) + { + // Get connected child OCMB (one OCMB per OMI) + o_txTrgt = getConnectedChild( i_rxTrgt, TYPE_OCMB_CHIP, 0 ); + } + else if ( TYPE_OCMB_CHIP == busType ) + { + // Get connected parent OMI + o_txTrgt = getConnectedParent( i_rxTrgt, TYPE_OMI ); + } PRDF_ASSERT(nullptr != o_txTrgt); return o_txTrgt; @@ -310,38 +320,6 @@ int32_t __handleLaneRepairEvent( ExtensibleChip * i_chip, #undef PRDF_FUNC } -template<> -int32_t __handleLaneRepairEvent<TYPE_OBUS, TYPE_OBUS>( ExtensibleChip * i_chip, - STEP_CODE_DATA_STRUCT & i_sc, - bool i_spareDeployed ) -{ - TargetHandle_t rxBusTgt = i_chip->getTrgt(); - - // Make predictive on first occurrence in MFG - if ( isLaneRepairDisabled<TYPE_OBUS>() ) - { - i_sc.service_data->setServiceCall(); - } - - // RTC 174485 - // Need HWPs for this. Just callout bus interface for now. - if ( obusInSmpMode(rxBusTgt) ) - { - calloutBusInterface( i_chip, i_sc, MRU_LOW ); - i_sc.service_data->setServiceCall(); - } - else - { - PRDF_ERR( "__handleLaneRepairEvent: Lane repair only supported " - "in SMP mode obus: 0x%08x", getHuid(rxBusTgt) ); - i_sc.service_data->SetCallout( LEVEL2_SUPPORT, MRU_MED, NO_GARD ); - i_sc.service_data->SetCallout( SP_CODE, MRU_MED, NO_GARD ); - i_sc.service_data->setServiceCall(); - } - return SUCCESS; -} - - int32_t handleLaneRepairEvent( ExtensibleChip * i_chip, STEP_CODE_DATA_STRUCT & i_sc, bool i_spareDeployed ) @@ -350,10 +328,6 @@ int32_t handleLaneRepairEvent( ExtensibleChip * i_chip, TYPE trgtType = getTargetType(i_chip->getTrgt()); switch (trgtType) { - case TYPE_OBUS: - rc = __handleLaneRepairEvent<TYPE_OBUS,TYPE_OBUS>( i_chip, i_sc, - i_spareDeployed ); - break; case TYPE_XBUS: rc = __handleLaneRepairEvent<TYPE_XBUS,TYPE_XBUS>( i_chip, i_sc, i_spareDeployed ); @@ -729,6 +703,8 @@ void obus_clearMaskFail( errlHndl_t &io_errl, TargetHandle_t &i_rxTrgt, PRDF_ASSERT( NULL != i_txTrgt ); PRDF_ASSERT( NULL != io_errl ); +#ifdef __HOSTBOOT_MODULE // register writes not allowed on FSP + uint32_t l_rc = SUCCESS; ExtensibleChip *l_rxChip = (ExtensibleChip *)systemPtr->GetChip( i_rxTrgt ); @@ -790,6 +766,8 @@ void obus_clearMaskFail( errlHndl_t &io_errl, TargetHandle_t &i_rxTrgt, } while (0); +#endif // __HOSTBOOT_MODULE + } // end obus_clearMaskFail @@ -924,7 +902,7 @@ PRDF_PLUGIN_DEFINE_NS( cumulus_proc, LaneRepair, captureSmpObus3 ); PRDF_PLUGIN_DEFINE_NS( nimbus_proc, LaneRepair, captureSmpObus3 ); PRDF_PLUGIN_DEFINE_NS( axone_proc, LaneRepair, captureSmpObus3 ); -int32_t calloutBusInterface( ExtensibleChip * i_chip, +int32_t calloutBusInterface( TargetHandle_t i_rxTrgt, STEP_CODE_DATA_STRUCT & i_sc, PRDpriority i_priority ) { @@ -934,10 +912,9 @@ int32_t calloutBusInterface( ExtensibleChip * i_chip, do { // Get both endpoints - TargetHandle_t rxTrgt = i_chip->getTrgt(); - TYPE rxType = getTargetType(rxTrgt); + TYPE rxType = getTargetType(i_rxTrgt); - if ( rxType == TYPE_OBUS && !obusInSmpMode( rxTrgt ) ) + if ( rxType == TYPE_OBUS && !obusInSmpMode( i_rxTrgt ) ) { // There is no support in hostboot for calling out the other end of // an NV or openCAPI bus. By design, any FIR bits associated with @@ -945,7 +922,7 @@ int32_t calloutBusInterface( ExtensibleChip * i_chip, // action. So if we hit this case, just make a default callout. PRDF_ERR( PRDF_FUNC "Lane repair only supported in SMP mode " - "obus: 0x%08x", getHuid(rxTrgt) ); + "obus: 0x%08x", getHuid(i_rxTrgt) ); i_sc.service_data->SetCallout( LEVEL2_SUPPORT, MRU_MED, NO_GARD ); i_sc.service_data->SetCallout( SP_CODE, MRU_MED, NO_GARD ); @@ -953,11 +930,11 @@ int32_t calloutBusInterface( ExtensibleChip * i_chip, break; } - TargetHandle_t txTrgt = getTxBusEndPt(rxTrgt); + TargetHandle_t txTrgt = getTxBusEndPt(i_rxTrgt); TYPE txType = getTargetType(txTrgt); // Add the endpoint target callouts - i_sc.service_data->SetCallout( rxTrgt, MRU_MEDA ); + i_sc.service_data->SetCallout( i_rxTrgt, MRU_MEDA ); i_sc.service_data->SetCallout( txTrgt, MRU_MEDA); // Get the HWAS bus type. @@ -975,6 +952,11 @@ int32_t calloutBusInterface( ExtensibleChip * i_chip, { hwasType = HWAS::DMI_BUS_TYPE; } + else if ( (TYPE_OMI == rxType && TYPE_OCMB_CHIP == txType) || + (TYPE_OCMB_CHIP == rxType && TYPE_OMI == txType) ) + { + hwasType = HWAS::OMI_BUS_TYPE; + } else { PRDF_ASSERT( false ); @@ -990,7 +972,7 @@ int32_t calloutBusInterface( ExtensibleChip * i_chip, } // Callout this bus interface. - PRDF_ADD_BUS_CALLOUT( errl, rxTrgt, txTrgt, hwasType, i_priority ); + PRDF_ADD_BUS_CALLOUT( errl, i_rxTrgt, txTrgt, hwasType, i_priority ); } while(0); @@ -1020,9 +1002,6 @@ int32_t spareDeployed( ExtensibleChip * i_chip, PRDF_PLUGIN_DEFINE_NS( nimbus_xbus, LaneRepair, spareDeployed ); PRDF_PLUGIN_DEFINE_NS( cumulus_xbus, LaneRepair, spareDeployed ); PRDF_PLUGIN_DEFINE_NS( axone_xbus, LaneRepair, spareDeployed ); -PRDF_PLUGIN_DEFINE_NS( nimbus_obus, LaneRepair, spareDeployed ); -PRDF_PLUGIN_DEFINE_NS( cumulus_obus, LaneRepair, spareDeployed ); -PRDF_PLUGIN_DEFINE_NS( axone_obus, LaneRepair, spareDeployed ); PRDF_PLUGIN_DEFINE_NS( centaur_membuf, LaneRepair, spareDeployed ); /** @@ -1042,9 +1021,6 @@ int32_t maxSparesExceeded( ExtensibleChip * i_chip, PRDF_PLUGIN_DEFINE_NS( nimbus_xbus, LaneRepair, maxSparesExceeded ); PRDF_PLUGIN_DEFINE_NS( cumulus_xbus, LaneRepair, maxSparesExceeded ); PRDF_PLUGIN_DEFINE_NS( axone_xbus, LaneRepair, maxSparesExceeded ); -PRDF_PLUGIN_DEFINE_NS( nimbus_obus, LaneRepair, maxSparesExceeded ); -PRDF_PLUGIN_DEFINE_NS( cumulus_obus, LaneRepair, maxSparesExceeded ); -PRDF_PLUGIN_DEFINE_NS( axone_obus, LaneRepair, maxSparesExceeded ); PRDF_PLUGIN_DEFINE_NS( centaur_membuf, LaneRepair, maxSparesExceeded ); /** @@ -1064,9 +1040,6 @@ int32_t tooManyBusErrors( ExtensibleChip * i_chip, PRDF_PLUGIN_DEFINE_NS( nimbus_xbus, LaneRepair, tooManyBusErrors ); PRDF_PLUGIN_DEFINE_NS( cumulus_xbus, LaneRepair, tooManyBusErrors ); PRDF_PLUGIN_DEFINE_NS( axone_xbus, LaneRepair, tooManyBusErrors ); -PRDF_PLUGIN_DEFINE_NS( nimbus_obus, LaneRepair, tooManyBusErrors ); -PRDF_PLUGIN_DEFINE_NS( cumulus_obus, LaneRepair, tooManyBusErrors ); -PRDF_PLUGIN_DEFINE_NS( axone_obus, LaneRepair, tooManyBusErrors ); PRDF_PLUGIN_DEFINE_NS( centaur_membuf, LaneRepair, tooManyBusErrors ); /** @@ -1078,18 +1051,53 @@ PRDF_PLUGIN_DEFINE_NS( centaur_membuf, LaneRepair, tooManyBusErrors ); int32_t calloutBusInterfacePlugin( ExtensibleChip * i_chip, STEP_CODE_DATA_STRUCT & io_sc ) { - calloutBusInterface(i_chip, io_sc, MRU_LOW); + calloutBusInterface(i_chip->getTrgt(), io_sc, MRU_LOW); return SUCCESS; } PRDF_PLUGIN_DEFINE_NS( nimbus_xbus, LaneRepair, calloutBusInterfacePlugin ); PRDF_PLUGIN_DEFINE_NS( cumulus_xbus, LaneRepair, calloutBusInterfacePlugin ); PRDF_PLUGIN_DEFINE_NS( axone_xbus, LaneRepair, calloutBusInterfacePlugin ); -PRDF_PLUGIN_DEFINE_NS( nimbus_obus, LaneRepair, calloutBusInterfacePlugin ); -PRDF_PLUGIN_DEFINE_NS( cumulus_obus, LaneRepair, calloutBusInterfacePlugin ); -PRDF_PLUGIN_DEFINE_NS( axone_obus, LaneRepair, calloutBusInterfacePlugin ); +PRDF_PLUGIN_DEFINE_NS( explorer_ocmb, LaneRepair, calloutBusInterfacePlugin ); PRDF_PLUGIN_DEFINE_NS( cumulus_dmi, LaneRepair, calloutBusInterfacePlugin ); PRDF_PLUGIN_DEFINE_NS( centaur_membuf, LaneRepair, calloutBusInterfacePlugin ); +/** + * @brief Add callouts for a BUS interface inputting an OMIC or MCC target + * @param i_chip OMIC/MCC chip + * @param io_sc Step code data struct. + * @param i_pos The position of the OMI relative to the OMIC/MCC. + * @return SUCCESS always + */ + +int32_t omiParentCalloutBusInterfacePlugin( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc, + uint8_t i_pos ) +{ + TargetHandle_t omi = getConnectedChild(i_chip->getTrgt(), TYPE_OMI, i_pos); + TargetHandle_t ocmb = getConnectedChild( omi, TYPE_OCMB_CHIP, 0 ); + + // Callout both ends of the bus as well (OMI and OCMB) + io_sc.service_data->SetCallout( omi, MRU_MEDA ); + io_sc.service_data->SetCallout( ocmb, MRU_MEDA ); + + calloutBusInterface(omi, io_sc, MRU_LOW); + return SUCCESS; +} + +#define OMI_PARENT_CALL_BUS_PLUGIN( POS ) \ +int32_t omiParentCalloutBusInterfacePlugin_##POS( ExtensibleChip * i_chip, \ + STEP_CODE_DATA_STRUCT & io_sc ) \ +{ \ + return omiParentCalloutBusInterfacePlugin( i_chip, io_sc, POS ); \ +} \ +PRDF_PLUGIN_DEFINE_NS( axone_omic, LaneRepair, \ + omiParentCalloutBusInterfacePlugin_##POS );\ +PRDF_PLUGIN_DEFINE_NS( axone_mcc, LaneRepair, \ + omiParentCalloutBusInterfacePlugin_##POS ); + +OMI_PARENT_CALL_BUS_PLUGIN( 0 ); +OMI_PARENT_CALL_BUS_PLUGIN( 1 ); +OMI_PARENT_CALL_BUS_PLUGIN( 2 ); //------------------------------------------------------------------------------ diff --git a/src/usr/diag/prdf/common/plat/p9/prdfLaneRepair.H b/src/usr/diag/prdf/common/plat/p9/prdfLaneRepair.H index afc834e29..3f5a3f33c 100644 --- a/src/usr/diag/prdf/common/plat/p9/prdfLaneRepair.H +++ b/src/usr/diag/prdf/common/plat/p9/prdfLaneRepair.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -56,12 +56,12 @@ int32_t handleLaneRepairEvent (ExtensibleChip * i_chip, /** * @brief Will add target bus interface endpoints and all parts in between the * endpoints to the global error log in RasServices. - * @param i_chip RX-side chip of bus interface - * @param i_sc The step code data struct. + * @param i_rxTrgt RX-side target of bus interface + * @param i_sc The step code data struct. * @param i_priority Callout priority (default MRU_LOW). * @return Non-SUCCESS if an internal function fails. SUCCESS otherwise. */ -int32_t calloutBusInterface( ExtensibleChip * i_chip, +int32_t calloutBusInterface( TARGETING::TargetHandle_t i_rxTrgt, STEP_CODE_DATA_STRUCT & i_sc, PRDpriority i_priority = MRU_LOW ); diff --git a/src/usr/diag/prdf/common/plat/p9/prdfP9Configurator.C b/src/usr/diag/prdf/common/plat/p9/prdfP9Configurator.C index e37cffcd3..7c3033dc2 100755 --- a/src/usr/diag/prdf/common/plat/p9/prdfP9Configurator.C +++ b/src/usr/diag/prdf/common/plat/p9/prdfP9Configurator.C @@ -243,7 +243,7 @@ errlHndl_t PlatConfigurator::addDomainChips( TARGETING::TYPE i_type, { errlHndl_t errl = nullptr; - std::map<TARGETING::MODEL, std::map<TARGETING::TYPE, const char *>> fnMap = + std::map<uint32_t, std::map<TARGETING::TYPE, const char *>> fnMap = { { MODEL_NIMBUS, { { TYPE_PROC, nimbus_proc }, { TYPE_EQ, nimbus_eq }, @@ -285,7 +285,14 @@ errlHndl_t PlatConfigurator::addDomainChips( TARGETING::TYPE i_type, { TYPE_MI, axone_mi }, { TYPE_MCC, axone_mcc }, { TYPE_OMIC, axone_omic }, } }, - { MODEL_EXPLORER, { { TYPE_OCMB_CHIP, explorer_ocmb }, } }, + #ifdef __HOSTBOOT_MODULE + { POWER_CHIPID::EXPLORER_16, { { TYPE_OCMB_CHIP, explorer_ocmb }, } }, + #endif + // OCMB is not supported on FSP, however we need support here for the + // MODEL_OCMB model for our simulator to work. + #ifdef ESW_SIM_COMPILE + { MODEL_OCMB, { { TYPE_OCMB_CHIP, explorer_ocmb }, } }, + #endif }; // Get references to factory objects. @@ -299,7 +306,19 @@ errlHndl_t PlatConfigurator::addDomainChips( TARGETING::TYPE i_type, // Iterate all the targets for this type and add to given domain. for ( const auto & trgt : getFunctionalTargetList(i_type) ) { - TARGETING::MODEL model = getChipModel( trgt ); + uint32_t model = getChipModel( trgt ); + + #ifdef __HOSTBOOT_MODULE + // Special case for OCMBs (hostboot only issue for P9). + if ( MODEL_OCMB == model ) + { + // Use the chip ID instead of model. + model = getChipId( trgt ); + + // Skip Gemini OCMBs. They can exist, but PRD won't support them. + if ( POWER_CHIPID::GEMINI_16 == model ) continue; + } + #endif // Ensure this model is supported. if ( fnMap.end() == fnMap.find(model) ) @@ -350,8 +369,6 @@ errlHndl_t PlatConfigurator::addDomainChips( TARGETING::TYPE i_type, scanFac, resFac ); break; - // TODO RTC 199020 - add the pll domains for axone - default: ; } } diff --git a/src/usr/diag/prdf/common/plat/p9/prdfP9Obus.C b/src/usr/diag/prdf/common/plat/p9/prdfP9Obus.C new file mode 100644 index 000000000..6117c6edc --- /dev/null +++ b/src/usr/diag/prdf/common/plat/p9/prdfP9Obus.C @@ -0,0 +1,193 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/diag/prdf/common/plat/p9/prdfP9Obus.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + + +// Framework includes +#include <iipServiceDataCollector.h> +#include <prdfExtensibleChip.H> +#include <prdfPluginMap.H> + +// Platform includes +#include <prdfPlatServices.H> + +using namespace TARGETING; + +namespace PRDF +{ + +using namespace PlatServices; + +namespace obus +{ + +//############################################################################## +// +// IOOLFIR +// +//############################################################################## + +/** + * @brief If OBUS is in SMP mode, does defaultMaskedError actions and returns + * SUCCESS. Otherwise, returns PRD_SCAN_COMM_REGISTER_ZERO. + */ +int32_t smp_masked( ExtensibleChip * i_chip, STEP_CODE_DATA_STRUCT & io_sc ) +{ + if ( obusInSmpMode(i_chip->getTrgt()) ) + { + // SMP mode: This attention should be masked. + io_sc.service_data->SetCallout( LEVEL2_SUPPORT, MRU_MED, NO_GARD ); + io_sc.service_data->setFlag( ServiceDataCollector::AT_THRESHOLD ); + io_sc.service_data->setFlag( ServiceDataCollector::SERVICE_CALL ); + return SUCCESS; + } + else + { + // Non-SMP mode: Try some other action. + return PRD_SCAN_COMM_REGISTER_ZERO; + } +} +PRDF_PLUGIN_DEFINE_NS( nimbus_obus, obus, smp_masked ); +PRDF_PLUGIN_DEFINE_NS( cumulus_obus, obus, smp_masked ); +PRDF_PLUGIN_DEFINE_NS( axone_obus, obus, smp_masked ); + +//------------------------------------------------------------------------------ + +/** + * @brief If OBUS is NOT in SMP mode, does defaultMaskedError actions and + * returns SUCCESS. Otherwise, returns PRD_SCAN_COMM_REGISTER_ZERO. + */ +int32_t non_smp_masked( ExtensibleChip * i_chip, STEP_CODE_DATA_STRUCT & io_sc ) +{ + if ( obusInSmpMode(i_chip->getTrgt()) ) + { + // SMP mode: Try some other action. + return PRD_SCAN_COMM_REGISTER_ZERO; + } + else + { + // Non-SMP mode: This attention should be masked. + io_sc.service_data->SetCallout( LEVEL2_SUPPORT, MRU_MED, NO_GARD ); + io_sc.service_data->setFlag( ServiceDataCollector::AT_THRESHOLD ); + io_sc.service_data->setFlag( ServiceDataCollector::SERVICE_CALL ); + return SUCCESS; + } +} +PRDF_PLUGIN_DEFINE_NS( nimbus_obus, obus, non_smp_masked ); +PRDF_PLUGIN_DEFINE_NS( cumulus_obus, obus, non_smp_masked ); +PRDF_PLUGIN_DEFINE_NS( axone_obus, obus, non_smp_masked ); + +//------------------------------------------------------------------------------ + +/** + * @brief If OBUS is NOT in SMP mode, calls out this bus on first occurrence and + * returns SUCCESS. Otherwise, returns PRD_SCAN_COMM_REGISTER_ZERO. + */ +int32_t non_smp_callout_bus_th_1( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + if ( obusInSmpMode(i_chip->getTrgt()) ) + { + // SMP mode: Try some other action. + return PRD_SCAN_COMM_REGISTER_ZERO; + } + else + { + // Non-SMP mode: Callout this bus. Note that Hostboot does not know what + // is on the other side of this bus and does not have any control over + // garding/deconfiguring. Therefore, we cannot gard since we will never + // know if the other side of the bus has been replaced. Also, there is + // a small probability that the fault could be between the two + // endpoints. Usually, we would do a procedure callout or call some HWP + // that would take care of the "everything in between" scenario. + // However, there is no existing mechanism. For now callout level 2 + // support at low priority. + io_sc.service_data->SetCallout( i_chip->getTrgt(), MRU_MED, NO_GARD ); + io_sc.service_data->SetCallout( LEVEL2_SUPPORT, MRU_LOW, NO_GARD ); + io_sc.service_data->setFlag( ServiceDataCollector::AT_THRESHOLD ); + io_sc.service_data->setFlag( ServiceDataCollector::SERVICE_CALL ); + return SUCCESS; + } +} +PRDF_PLUGIN_DEFINE_NS( nimbus_obus, obus, non_smp_callout_bus_th_1 ); +PRDF_PLUGIN_DEFINE_NS( cumulus_obus, obus, non_smp_callout_bus_th_1 ); +PRDF_PLUGIN_DEFINE_NS( axone_obus, obus, non_smp_callout_bus_th_1 ); + +//------------------------------------------------------------------------------ + +/** + * @brief If OBUS is NOT in SMP mode, calls out level 2 support on first + * occurrence and returns SUCCESS. Otherwise, returns + * PRD_SCAN_COMM_REGISTER_ZERO. + */ +int32_t non_smp_callout_lvl2_th_1( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + if ( obusInSmpMode(i_chip->getTrgt()) ) + { + // SMP mode: Try some other action. + return PRD_SCAN_COMM_REGISTER_ZERO; + } + else + { + // Non-SMP mode: Callout this bus on first occurrence. + io_sc.service_data->SetCallout( LEVEL2_SUPPORT, MRU_MED, NO_GARD ); + io_sc.service_data->setFlag( ServiceDataCollector::AT_THRESHOLD ); + io_sc.service_data->setFlag( ServiceDataCollector::SERVICE_CALL ); + return SUCCESS; + } +} +PRDF_PLUGIN_DEFINE_NS( nimbus_obus, obus, non_smp_callout_lvl2_th_1 ); +PRDF_PLUGIN_DEFINE_NS( cumulus_obus, obus, non_smp_callout_lvl2_th_1 ); +PRDF_PLUGIN_DEFINE_NS( axone_obus, obus, non_smp_callout_lvl2_th_1 ); + +//------------------------------------------------------------------------------ + +/** + * @brief If OBUS is NOT in SMP mode, calls out this OBUS target and returns + * SUCCESS. Otherwise, returns PRD_SCAN_COMM_REGISTER_ZERO. + */ +int32_t non_smp_callout_self( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + if ( obusInSmpMode(i_chip->getTrgt()) ) + { + // SMP mode: Try some other action. + return PRD_SCAN_COMM_REGISTER_ZERO; + } + else + { + // Non-SMP mode: Callout this OBUS target. + io_sc.service_data->SetCallout( i_chip->getTrgt() ); + return SUCCESS; + } +} +PRDF_PLUGIN_DEFINE_NS( nimbus_obus, obus, non_smp_callout_self ); +PRDF_PLUGIN_DEFINE_NS( cumulus_obus, obus, non_smp_callout_self ); +PRDF_PLUGIN_DEFINE_NS( axone_obus, obus, non_smp_callout_self ); + +} // end namespace obus + +} // end namespace PRDF + diff --git a/src/usr/diag/prdf/common/plat/p9/prdfP9OcmbChipDomain.C b/src/usr/diag/prdf/common/plat/p9/prdfP9OcmbChipDomain.C new file mode 100644 index 000000000..2f6c25646 --- /dev/null +++ b/src/usr/diag/prdf/common/plat/p9/prdfP9OcmbChipDomain.C @@ -0,0 +1,78 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/diag/prdf/common/plat/p9/prdfP9OcmbChipDomain.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/** + * @file prdfP9OcmbChipDomain.C + * @brief chip Plug-in code for OCMB domain + */ + +#include <prdfP9OcmbChipDomain.H> + +// Framework includes +#include <prdfExtensibleChip.H> +#include <prdfPlatServices.H> +#include <prdfTrace.H> +#include <prdfOcmbDataBundle.H> + +using namespace TARGETING; + +namespace PRDF +{ + +using namespace PlatServices; + +#ifdef __HOSTBOOT_RUNTIME +void OcmbChipDomain::handleRrFo() +{ + #define PRDF_FUNC "[OcmbChipDomain::handleRrFo] " + + do + { + uint32_t domainSize = GetSize(); + // Iterate all OCMBs in the domain. + for ( uint32_t i = 0; i < domainSize; ++i ) + { + RuleChip * ocmbChip = LookUp(i); + + // Start background scrub if required. + OcmbDataBundle * ocmbdb = getOcmbDataBundle( ocmbChip ); + int32_t l_rc = ocmbdb->getTdCtlr()->handleRrFo(); + if ( SUCCESS != l_rc ) + { + // Let us not fail here. If problem is contained within an OCMB + // we will discover it again during normal TD procedures. + PRDF_ERR( PRDF_FUNC "handleRrFo() failed: OCMB=0x%08x", + ocmbChip->GetId() ); + continue; // Keep going. + } + } + + } while (0); + + #undef PRDF_FUNC +} +#endif + +} // end namespace PRDF diff --git a/src/usr/diag/prdf/common/plat/p9/prdfP9OcmbChipDomain.H b/src/usr/diag/prdf/common/plat/p9/prdfP9OcmbChipDomain.H index 5546d9453..9f5776cac 100644 --- a/src/usr/diag/prdf/common/plat/p9/prdfP9OcmbChipDomain.H +++ b/src/usr/diag/prdf/common/plat/p9/prdfP9OcmbChipDomain.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -54,6 +54,16 @@ class OcmbChipDomain : public RuleChipDomain virtual bool Query( ATTENTION_TYPE i_attnType ) { return false; } + #ifdef __HOSTBOOT_RUNTIME + + /** + * @brief Starts memory background scrubbing or VCM procedure for OCMB + * during R/R and F/O if required. + */ + void handleRrFo(); + + #endif + }; } // end namespace PRDF diff --git a/src/usr/diag/prdf/common/plat/p9/prdf_plat_p9.mk b/src/usr/diag/prdf/common/plat/p9/prdf_plat_p9.mk index cb69cad14..64092650f 100644 --- a/src/usr/diag/prdf/common/plat/p9/prdf_plat_p9.mk +++ b/src/usr/diag/prdf/common/plat/p9/prdf_plat_p9.mk @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2016,2018 +# Contributors Listed Below - COPYRIGHT 2016,2019 # [+] International Business Machines Corp. # # @@ -56,4 +56,5 @@ prd_rule_plugin += prdfP9Eq.o prd_rule_plugin += prdfP9TodPlugins.o prd_rule_plugin += prdfP9Dmi_common.o prd_rule_plugin += prdfP9Mc_common.o +prd_rule_plugin += prdfP9Obus.o diff --git a/src/usr/diag/prdf/common/plat/prdfPlatServices_common.C b/src/usr/diag/prdf/common/plat/prdfPlatServices_common.C index f99427d61..5cabaedc8 100644 --- a/src/usr/diag/prdf/common/plat/prdfPlatServices_common.C +++ b/src/usr/diag/prdf/common/plat/prdfPlatServices_common.C @@ -48,7 +48,6 @@ #include <p9_io_xbus_pdwn_lanes.H> #include <p9_io_xbus_clear_firs.H> #include <p9_io_erepairAccessorHwpFuncs.H> -#include <config.h> #include <p9_io_cen_read_erepair.H> #include <p9_io_cen_pdwn_lanes.H> #include <p9_io_dmi_read_erepair.H> @@ -695,6 +694,10 @@ uint32_t getBadDqBitmap( TargetHandle_t i_trgt, const MemRank & i_rank, o_rc = __getBadDqBitmap<fapi2::TARGET_TYPE_MEM_PORT>( i_trgt, i_rank, o_bitmap ); break; + case TYPE_OCMB_CHIP: + o_rc = __getBadDqBitmap<fapi2::TARGET_TYPE_OCMB_CHIP>( i_trgt, + i_rank, o_bitmap ); + break; default: PRDF_ERR( PRDF_FUNC "Invalid trgt type" ); o_rc = FAIL; @@ -777,6 +780,10 @@ uint32_t setBadDqBitmap( TargetHandle_t i_trgt, const MemRank & i_rank, o_rc = __setBadDqBitmap<fapi2::TARGET_TYPE_MEM_PORT>( i_trgt, i_rank, i_bitmap ); break; + case TYPE_OCMB_CHIP: + o_rc = __setBadDqBitmap<fapi2::TARGET_TYPE_OCMB_CHIP>( i_trgt, + i_rank, i_bitmap ); + break; default: PRDF_ERR( PRDF_FUNC "Invalid trgt type" ); o_rc = FAIL; @@ -872,6 +879,17 @@ void getDimmDqAttr<TYPE_MEM_PORT>( TargetHandle_t i_target, } // end function getDimmDqAttr template<> +void getDimmDqAttr<TYPE_OCMB_CHIP>( TargetHandle_t i_target, + uint8_t (&o_dqMapPtr)[DQS_PER_DIMM] ) +{ + PRDF_ASSERT( TYPE_OCMB_CHIP == getTargetType(i_target) ); + + // TODO RTC 210072 - Support for multiple ports per OCMB + TargetHandle_t memPort = getConnectedChild( i_target, TYPE_MEM_PORT, 0 ); + getDimmDqAttr<TYPE_MEM_PORT>( memPort, o_dqMapPtr ); +} + +template<> void getDimmDqAttr<TYPE_DIMM>( TargetHandle_t i_target, uint8_t (&o_dqMapPtr)[DQS_PER_DIMM] ) { @@ -947,15 +965,15 @@ int32_t mssGetSteerMux<TYPE_MBA>( TargetHandle_t i_mba, const MemRank & i_rank, } template<> -int32_t mssGetSteerMux<TYPE_MEM_PORT>( TargetHandle_t i_memPort, - const MemRank & i_rank, - MemSymbol & o_port0Spare, - MemSymbol & o_port1Spare, - MemSymbol & o_eccSpare ) +int32_t mssGetSteerMux<TYPE_OCMB_CHIP>( TargetHandle_t i_ocmb, + const MemRank & i_rank, + MemSymbol & o_port0Spare, + MemSymbol & o_port1Spare, + MemSymbol & o_eccSpare ) { int32_t o_rc = SUCCESS; - /* TODO RTC 207273 - sparing support + /* TODO RTC 199032 - sparing support // called by FSP code so can't just move to hostboot side #ifdef __HOSTBOOT_MODULE @@ -963,7 +981,7 @@ int32_t mssGetSteerMux<TYPE_MEM_PORT>( TargetHandle_t i_memPort, uint8_t port0Spare, port1Spare, eccSpare; - fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT> fapiPort(i_memPort); + fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> fapiPort(i_ocmb); FAPI_INVOKE_HWP( errl, mss_check_steering, fapiPort, i_rank.getMaster(), port0Spare, port1Spare, eccSpare ); @@ -971,15 +989,15 @@ int32_t mssGetSteerMux<TYPE_MEM_PORT>( TargetHandle_t i_memPort, { PRDF_ERR( "[PlatServices::mssGetSteerMux] mss_check_steering() " "failed. HUID: 0x%08x rank: %d", - getHuid(i_memPort), i_rank.getMaster() ); + getHuid(i_ocmb), i_rank.getMaster() ); PRDF_COMMIT_ERRL( errl, ERRL_ACTION_REPORT ); o_rc = FAIL; } else { - o_port0Spare = MemSymbol::fromSymbol( i_memPort, i_rank, port0Spare ); - o_port1Spare = MemSymbol::fromSymbol( i_memPort, i_rank, port1Spare ); - o_eccSpare = MemSymbol::fromSymbol( i_memPort, i_rank, eccSpare ); + o_port0Spare = MemSymbol::fromSymbol( i_ocmb, i_rank, port0Spare ); + o_port1Spare = MemSymbol::fromSymbol( i_ocmb, i_rank, port1Spare ); + o_eccSpare = MemSymbol::fromSymbol( i_ocmb, i_rank, eccSpare ); } #endif */ @@ -1020,20 +1038,22 @@ int32_t mssSetSteerMux<TYPE_MBA>( TargetHandle_t i_mba, const MemRank & i_rank, } template<> -int32_t mssSetSteerMux<TYPE_MEM_PORT>( TargetHandle_t i_memPort, +int32_t mssSetSteerMux<TYPE_OCMB_CHIP>( TargetHandle_t i_memPort, const MemRank & i_rank, const MemSymbol & i_symbol, bool i_x4EccSpare ) { int32_t o_rc = SUCCESS; - /* TODO RTC 207273 - sparing support + /* TODO RTC 199032 - sparing support #ifdef __HOSTBOOT_MODULE errlHndl_t errl = NULL; fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT> fapiPort(i_memPort); + TargetHandle_t dimm = getConnectedDimm( i_memPort, i_rank, + i_symbol.getPortSlct() ); uint8_t l_dramSymbol = PARSERUTILS::dram2Symbol<TYPE_MBA>( i_symbol.getDram(), - isDramWidthX4(i_memPort) ); + isDramWidthX4(dimm) ); FAPI_INVOKE_HWP( errl, mss_do_steering, fapiPort, i_rank.getMaster(), l_dramSymbol, @@ -1105,7 +1125,9 @@ int32_t getDimmSpareConfig<TYPE_MEM_PORT>( TargetHandle_t i_memPort, bool isFullByte = ( ENUM_ATTR_MEM_EFF_DIMM_SPARE_FULL_BYTE == o_spareConfig ); - bool isX4Dram = isDramWidthX4(i_memPort); + + TargetHandle_t dimm = getConnectedDimm( i_memPort, i_rank, i_ps ); + bool isX4Dram = isDramWidthX4(dimm); if ( ( isX4Dram && isFullByte ) || ( !isX4Dram && !isFullByte ) ) { @@ -1122,6 +1144,15 @@ int32_t getDimmSpareConfig<TYPE_MEM_PORT>( TargetHandle_t i_memPort, } template<> +int32_t getDimmSpareConfig<TYPE_OCMB_CHIP>( TargetHandle_t i_ocmb, + MemRank i_rank, uint8_t i_ps, uint8_t & o_spareConfig ) +{ + TargetHandle_t memPort = getConnectedChild( i_ocmb, TYPE_MEM_PORT, i_ps ); + return getDimmSpareConfig<TYPE_MEM_PORT>( memPort, i_rank, i_ps, + o_spareConfig ); +} + +template<> int32_t getDimmSpareConfig<TYPE_MBA>( TargetHandle_t i_mba, MemRank i_rank, uint8_t i_ps, uint8_t & o_spareConfig ) { @@ -1207,7 +1238,8 @@ uint32_t isDramSparingEnabled<TYPE_MEM_PORT>( TARGETING::TargetHandle_t i_trgt, do { - const bool isX4 = isDramWidthX4( i_trgt ); + TargetHandle_t dimm = getConnectedDimm( i_trgt, i_rank, i_ps ); + const bool isX4 = isDramWidthX4( dimm ); if ( isX4 ) { // Always an ECC spare in x4 mode. @@ -1216,9 +1248,7 @@ uint32_t isDramSparingEnabled<TYPE_MEM_PORT>( TARGETING::TargetHandle_t i_trgt, } // Check for any DRAM spares. - // TODO RTC 207273 - no TARGETING support for attr yet - //uint8_t cnfg = TARGETING::MEM_EFF_DIMM_SPARE_NO_SPARE; - uint8_t cnfg = 0; + uint8_t cnfg = TARGETING::MEM_EFF_DIMM_SPARE_NO_SPARE; o_rc = getDimmSpareConfig<TYPE_MEM_PORT>( i_trgt, i_rank, i_ps, cnfg ); if ( SUCCESS != o_rc ) { @@ -1226,9 +1256,7 @@ uint32_t isDramSparingEnabled<TYPE_MEM_PORT>( TARGETING::TargetHandle_t i_trgt, "failed", getHuid(i_trgt), i_rank.getKey(), i_ps ); break; } - // TODO RTC 207273 - no TARGETING support for attr yet - //o_spareEnable = (TARGETING::MEM_EFF_DIMM_SPARE_NO_SPARE; != cnfg); - o_spareEnable = (0 != cnfg); + o_spareEnable = (TARGETING::MEM_EFF_DIMM_SPARE_NO_SPARE != cnfg); }while(0); @@ -1303,12 +1331,22 @@ uint32_t isSpareAvailable( TARGETING::TargetHandle_t i_trgt, MemRank i_rank, if ( !dramSparingEnabled ) break; // Get the current spares in hardware + TargetHandle_t steerTrgt = i_trgt; MemSymbol sp0, sp1, ecc; - o_rc = mssGetSteerMux<T>( i_trgt, i_rank, sp0, sp1, ecc ); + if ( TYPE_MEM_PORT == T ) + { + steerTrgt = getConnectedParent( i_trgt, TYPE_OCMB_CHIP ); + o_rc = mssGetSteerMux<TYPE_OCMB_CHIP>( steerTrgt, i_rank, sp0, sp1, + ecc ); + } + else + { + o_rc = mssGetSteerMux<T>( steerTrgt, i_rank, sp0, sp1, ecc ); + } if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "mssGetSteerMux(0x%08x,0x%02x) failed", - getHuid(i_trgt), i_rank.getKey() ); + getHuid(steerTrgt), i_rank.getKey() ); break; } @@ -1353,6 +1391,10 @@ template uint32_t isSpareAvailable<TYPE_MBA>( TARGETING::TargetHandle_t i_trgt, MemRank i_rank, uint8_t i_ps, bool & o_spAvail, bool & o_eccAvail ); +template +uint32_t isSpareAvailable<TYPE_MEM_PORT>( TARGETING::TargetHandle_t i_trgt, + MemRank i_rank, uint8_t i_ps, bool & o_spAvail, bool & o_eccAvail ); + //------------------------------------------------------------------------------ template<> diff --git a/src/usr/diag/prdf/common/plat/prdfPlatServices_common.H b/src/usr/diag/prdf/common/plat/prdfPlatServices_common.H index 5d41d96e0..203703b42 100755 --- a/src/usr/diag/prdf/common/plat/prdfPlatServices_common.H +++ b/src/usr/diag/prdf/common/plat/prdfPlatServices_common.H @@ -193,7 +193,7 @@ bool obusInSmpMode(TARGETING::TargetHandle_t obusTgt); /** * @brief Reads the bad DQ bitmap attribute for both ports of the target rank. - * @param i_trgt A MCA/MBA/MEM_PORT target. + * @param i_trgt A MCA/MBA/MEM_PORT/OCMB_CHIP target. * @param i_rank Target rank. * @param o_bitmap DQ bitmap container. * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. @@ -203,7 +203,7 @@ uint32_t getBadDqBitmap( TARGETING::TargetHandle_t i_trgt, /** * @brief Writes the bad DQ bitmap attribute for both ports of the target rank. - * @param i_trgt A MCA/MBA/MEM_PORT target. + * @param i_trgt A MCA/MBA/MEM_PORT/OCMB_CHIP target. * @param i_rank Target rank. * @param i_bitmap DQ bitmap container. * @note This is a no-op if DRAM Repairs are disabled in manufacturing. @@ -215,7 +215,7 @@ uint32_t setBadDqBitmap( TARGETING::TargetHandle_t i_trgt, /** * @brief Clears the bad DQ bitmap attribute for all ports of the target rank. - * @param i_trgt A MCA/MBA/MEM_PORT target. + * @param i_trgt A MCA/MBA/MEM_PORT/OCMB_CHIP target. * @param i_rank Target rank. * @note This is a no-op if DRAM Repairs are disabled in manufacturing. * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. diff --git a/src/usr/diag/prdf/common/plat/prdfRasServices_common.C b/src/usr/diag/prdf/common/plat/prdfRasServices_common.C index 3f9ba2322..2742286b3 100755 --- a/src/usr/diag/prdf/common/plat/prdfRasServices_common.C +++ b/src/usr/diag/prdf/common/plat/prdfRasServices_common.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -891,12 +891,21 @@ void ErrDataService::deallocateDimms( const SDC_MRU_LIST & i_mruList ) for ( SDC_MRU_LIST::const_iterator it = i_mruList.begin(); it != i_mruList.end(); ++it ) { + PRDcallout thiscallout = it->callout; if ( PRDcalloutData::TYPE_TARGET == thiscallout.getType() ) { TargetHandle_t calloutTgt = thiscallout.getTarget(); TYPE tgtType = getTargetType( calloutTgt ); + #ifdef CONFIG_NVDIMM + // If the MRU's gard policy is set to NO_GARD, skip it. + if ( NO_GARD == it->gardState && isNVDIMM(calloutTgt) ) + { + continue; + } + #endif + if ( TYPE_L4 == tgtType ) { calloutTgt = getConnectedParent( calloutTgt, TYPE_MEMBUF ); @@ -932,7 +941,17 @@ void ErrDataService::deallocateDimms( const SDC_MRU_LIST & i_mruList ) dimm != dimms.end(); ++dimm ) { if ( TYPE_DIMM == getTargetType(*dimm) ) + { + #ifdef CONFIG_NVDIMM + // If the MRU's gard policy is set to NO_GARD, skip it. + if ( NO_GARD == it->gardState && isNVDIMM(*dimm) ) + { + continue; + } + #endif + dimmList.push_back(*dimm); + } } } } diff --git a/src/usr/diag/prdf/common/plat/prdfTargetServices.C b/src/usr/diag/prdf/common/plat/prdfTargetServices.C index 65f8b9cdc..d34c980ad 100755 --- a/src/usr/diag/prdf/common/plat/prdfTargetServices.C +++ b/src/usr/diag/prdf/common/plat/prdfTargetServices.C @@ -365,6 +365,20 @@ TARGETING::MODEL getChipModel( TARGETING::TargetHandle_t i_trgt ) //------------------------------------------------------------------------------ +#ifdef __HOSTBOOT_MODULE +uint32_t getChipId( TARGETING::TargetHandle_t i_trgt ) +{ + PRDF_ASSERT( NULL != i_trgt ); + + TargetHandle_t parent = getParentChip( i_trgt ); + PRDF_ASSERT( NULL != parent ); + + return parent->getAttr<ATTR_CHIP_ID>(); +} +#endif + +//------------------------------------------------------------------------------ + uint8_t getChipLevel( TARGETING::TargetHandle_t i_trgt ) { PRDF_ASSERT( NULL != i_trgt ); @@ -566,6 +580,7 @@ TargetService::ASSOCIATION_TYPE getAssociationType( TargetHandle_t i_target, { TYPE_MC, TYPE_PROC, TargetService::PARENT_BY_AFFINITY }, { TYPE_MC, TYPE_MI, TargetService::CHILD_BY_AFFINITY }, { TYPE_MC, TYPE_OMIC, TargetService::CHILD_BY_AFFINITY }, + { TYPE_MC, TYPE_MCC, TargetService::CHILD_BY_AFFINITY }, { TYPE_MC, TYPE_DMI, TargetService::CHILD_BY_AFFINITY }, { TYPE_MC, TYPE_DIMM, TargetService::CHILD_BY_AFFINITY }, @@ -579,13 +594,16 @@ TargetService::ASSOCIATION_TYPE getAssociationType( TargetHandle_t i_target, { TYPE_OMIC, TYPE_OMI, TargetService::CHILD_BY_AFFINITY }, { TYPE_MCC, TYPE_PROC, TargetService::PARENT_BY_AFFINITY }, + { TYPE_MCC, TYPE_MC, TargetService::PARENT_BY_AFFINITY }, { TYPE_MCC, TYPE_MI, TargetService::PARENT_BY_AFFINITY }, { TYPE_MCC, TYPE_OMI, TargetService::CHILD_BY_AFFINITY }, + { TYPE_MCC, TYPE_OCMB_CHIP, TargetService::CHILD_BY_AFFINITY }, { TYPE_OMI, TYPE_OMIC, TargetService::PARENT_BY_AFFINITY }, { TYPE_OMI, TYPE_MCC, TargetService::PARENT_BY_AFFINITY }, { TYPE_OMI, TYPE_OCMB_CHIP, TargetService::CHILD_BY_AFFINITY }, + { TYPE_OCMB_CHIP, TYPE_MCC, TargetService::PARENT_BY_AFFINITY }, { TYPE_OCMB_CHIP, TYPE_OMI, TargetService::PARENT_BY_AFFINITY }, { TYPE_OCMB_CHIP, TYPE_MEM_PORT,TargetService::CHILD_BY_AFFINITY }, { TYPE_OCMB_CHIP, TYPE_DIMM, TargetService::CHILD_BY_AFFINITY }, @@ -648,14 +666,30 @@ TargetHandleList getConnAssoc( TargetHandle_t i_target, TYPE i_connType, TargetHandleList o_list; // Default empty list - // Match any class, specified type, and functional. - PredicateCTM predType( CLASS_NA, i_connType ); - PredicateIsFunctional predFunc; - PredicatePostfixExpr predAnd; - predAnd.push(&predType).push(&predFunc).And(); + TYPE trgtType = getTargetType( i_target ); - targetService().getAssociated( o_list, i_target, i_assocType, - TargetService::ALL, &predAnd ); + // OMIC -> OMI and vice versa require special handling. + if ( TYPE_OMIC == trgtType && TYPE_OMI == i_connType ) + { + getChildOmiTargetsByState( o_list, i_target, CLASS_NA, TYPE_OMI, + UTIL_FILTER_FUNCTIONAL ); + } + else if ( TYPE_OMI == trgtType && TYPE_OMIC == i_connType ) + { + getParentOmicTargetsByState( o_list, i_target, CLASS_NA, TYPE_OMIC, + UTIL_FILTER_FUNCTIONAL ); + } + else + { + // Match any class, specified type, and functional. + PredicateCTM predType( CLASS_NA, i_connType ); + PredicateIsFunctional predFunc; + PredicatePostfixExpr predAnd; + predAnd.push(&predType).push(&predFunc).And(); + + targetService().getAssociated( o_list, i_target, i_assocType, + TargetService::ALL, &predAnd ); + } // Sort by target position. std::sort( o_list.begin(), o_list.end(), @@ -866,6 +900,17 @@ TargetHandle_t getConnectedChild( TargetHandle_t i_target, TYPE i_connType, (i_connPos == (miPos % MAX_MI_PER_MC)); } ); } + else if ( TYPE_MC == trgtType && TYPE_MCC == i_connType ) + { + // i_connPos is position relative to MC (0-3) + itr = std::find_if( list.begin(), list.end(), + [&](const TargetHandle_t & t) + { + uint32_t mccPos = getTargetPosition(t); + return (trgtPos == (mccPos / MAX_MCC_PER_MC)) && + (i_connPos == (mccPos % MAX_MCC_PER_MC)); + } ); + } else if ( TYPE_MC == trgtType && TYPE_DMI == i_connType ) { // i_connPos is position relative to MC (0-3) @@ -929,6 +974,17 @@ TargetHandle_t getConnectedChild( TargetHandle_t i_target, TYPE i_connType, (i_connPos == (omiPos % MAX_OMI_PER_MCC)); } ); } + else if ( TYPE_MCC == trgtType && TYPE_OCMB_CHIP == i_connType ) + { + // i_connPos is position relative to MCC (0-1) + itr = std::find_if( list.begin(), list.end(), + [&](const TargetHandle_t & t) + { + uint32_t ocmbPos = getTargetPosition(t); + return (trgtPos == (ocmbPos / MAX_OCMB_PER_MCC)) && + (i_connPos == (ocmbPos % MAX_OCMB_PER_MCC)); + } ); + } else if ( TYPE_MC == trgtType && TYPE_OMIC == i_connType ) { // i_connPos is position relative to MC (0-2) @@ -943,13 +999,17 @@ TargetHandle_t getConnectedChild( TargetHandle_t i_target, TYPE i_connType, else if ( TYPE_OMIC == trgtType && TYPE_OMI == i_connType ) { // i_connPos is position relative to OMIC (0-2) - itr = std::find_if( list.begin(), list.end(), - [&](const TargetHandle_t & t) - { - uint32_t omiPos = getTargetPosition(t); - return (trgtPos == (omiPos / MAX_OMI_PER_OMIC)) && - (i_connPos == (omiPos % MAX_OMI_PER_OMIC)); - } ); + for ( TargetHandleList::iterator trgtIt = list.begin(); + trgtIt != list.end(); trgtIt++ ) + { + uint8_t omiPos = 0; + if ( (*trgtIt)->tryGetAttr<ATTR_OMI_DL_GROUP_POS>(omiPos) && + (i_connPos == omiPos) ) + { + itr = trgtIt; + break; + } + } } else if ( TYPE_PROC == trgtType && TYPE_NPU == i_connType ) { @@ -991,7 +1051,12 @@ ExtensibleChipList getConnected( ExtensibleChip * i_chip, TYPE i_connType ) TargetHandleList list = getConnected( i_chip->getTrgt(), i_connType ); for ( auto & trgt : list ) { - o_list.push_back( (ExtensibleChip *)systemPtr->GetChip(trgt) ); + // Check to make sure that if we have a non-null Target, we also + // get back a non-null ExtensibleChip. + ExtensibleChip * chip = (ExtensibleChip *)systemPtr->GetChip(trgt); + PRDF_ASSERT( nullptr != chip ); + + o_list.push_back( chip ); } return o_list; @@ -1007,7 +1072,12 @@ ExtensibleChip * getConnectedParent( ExtensibleChip * i_child, TargetHandle_t trgt = getConnectedParent( i_child->getTrgt(), i_parentType ); - return (ExtensibleChip *)systemPtr->GetChip( trgt ); + // Check to make sure that if we have a non-null Target, we also + // get back a non-null ExtensibleChip. + ExtensibleChip * chip = (ExtensibleChip *)systemPtr->GetChip( trgt ); + PRDF_ASSERT( nullptr != chip ); + + return chip; } //------------------------------------------------------------------------------ @@ -1026,6 +1096,10 @@ ExtensibleChip * getConnectedChild( ExtensibleChip * i_parent, if ( nullptr != trgt ) { o_child = (ExtensibleChip *)systemPtr->GetChip( trgt ); + + // Check to make sure that if we have a non-null Target, we also + // get back a non-null ExtensibleChip. + PRDF_ASSERT( nullptr != o_child ); } return o_child; @@ -1471,7 +1545,9 @@ bool isDramWidthX4( TargetHandle_t i_trgt ) bool o_dramWidthX4 = false; PRDF_ASSERT( nullptr != i_trgt ); - //uint8_t dramWidths = 0; + uint8_t dramWidths[MAX_DIMM_PER_PORT]; + uint8_t dimmSlct = 0; + TargetHandle_t memPort = nullptr; switch ( getTargetType(i_trgt) ) { @@ -1485,12 +1561,17 @@ bool isDramWidthX4( TargetHandle_t i_trgt ) break; case TYPE_DIMM: - // TODO RTC 207273 - attribute not in TARGETING code yet - //TargetHandle_t memPort = getConnectedParent(i_trgt, TYPE_MEM_PORT); - //dramWidths = memPort->getAttr<ATTR_MEM_EFF_DRAM_WIDTH>(); - //uint8_t dimmSlct = getDimmSlct( i_trgt ); - //o_dramWidthX4 = - // (fapi2::ENUM_ATTR_MEM_EFF_DRAM_WIDTH_X4 == dramWidths[dimmSlct]); + memPort = getConnectedParent(i_trgt, TYPE_MEM_PORT); + if ( !memPort->tryGetAttr<ATTR_MEM_EFF_DRAM_WIDTH>(dramWidths) ) + { + PRDF_ERR( "isDramWidthX4: Unable to access " + "ATTR_MEM_EFF_DRAM_WIDTH i_trgt=0x%08x.", + getHuid(memPort) ); + PRDF_ASSERT( false ); + } + dimmSlct = getDimmSlct( i_trgt ); + o_dramWidthX4 = + (TARGETING::MEM_EFF_DRAM_WIDTH_X4 == dramWidths[dimmSlct]); break; default: @@ -1538,15 +1619,12 @@ void __getMasterRanks( TargetHandle_t i_trgt, std::vector<MemRank> & o_ranks, } else if ( MODEL_AXONE == l_procModel ) { - PRDF_ERR( PRDF_FUNC "Axone attribute not supported yet" ); - /* TODO RTC 207273 - no targeting support for attr yet if ( !i_trgt->tryGetAttr<ATTR_MEM_EFF_DIMM_RANKS_CONFIGED>(info[0]) ) { PRDF_ERR( PRDF_FUNC "tryGetAttr<ATTR_MEM_EFF_DIMM_RANKS_CONFIGED> " "failed: i_trgt=0x%08x", getHuid(i_trgt) ); PRDF_ASSERT( false ); // attribute does not exist for target } - */ } else { @@ -1605,17 +1683,21 @@ void getMasterRanks<TYPE_MBA>( TargetHandle_t i_trgt, } template<> -void getMasterRanks<TYPE_MEM_PORT>( TargetHandle_t i_trgt, - std::vector<MemRank> & o_ranks, - uint8_t i_ds ) -{ - __getMasterRanks<TYPE_MEM_PORT>( i_trgt, o_ranks, 0, i_ds ); +void getMasterRanks<TYPE_OCMB_CHIP>( TargetHandle_t i_trgt, + std::vector<MemRank> & o_ranks, + uint8_t i_ds ) +{ + // TODO RTC 210072 - Explorer only has one port, however, multiple ports + // will be supported in the future. Updates will need to be made here so we + // can get the relevant port. + TargetHandle_t memPort = getConnectedChild( i_trgt, TYPE_MEM_PORT, 0 ); + __getMasterRanks<TYPE_MEM_PORT>( memPort, o_ranks, 0, i_ds ); } //------------------------------------------------------------------------------ template<TARGETING::TYPE T> -void __getSlaveRanks( TargetHandle_t i_trgt, std::vector<MemRank> & o_ranks, +void getSlaveRanks( TargetHandle_t i_trgt, std::vector<MemRank> & o_ranks, uint8_t i_ds ) { PRDF_ASSERT( nullptr != i_trgt ); @@ -1656,29 +1738,18 @@ void __getSlaveRanks( TargetHandle_t i_trgt, std::vector<MemRank> & o_ranks, } } -template<> +template void getSlaveRanks<TYPE_MCA>( TargetHandle_t i_trgt, std::vector<MemRank> & o_ranks, - uint8_t i_ds ) -{ - __getSlaveRanks<TYPE_MCA>( i_trgt, o_ranks, i_ds ); -} - -template<> + uint8_t i_ds ); +template void getSlaveRanks<TYPE_MBA>( TargetHandle_t i_trgt, std::vector<MemRank> & o_ranks, - uint8_t i_ds ) -{ - __getSlaveRanks<TYPE_MBA>( i_trgt, o_ranks, i_ds ); -} - -template<> -void getSlaveRanks<TYPE_MEM_PORT>( TargetHandle_t i_trgt, - std::vector<MemRank> & o_ranks, - uint8_t i_ds ) -{ - __getSlaveRanks<TYPE_MEM_PORT>( i_trgt, o_ranks, i_ds ); -} + uint8_t i_ds ); +template +void getSlaveRanks<TYPE_OCMB_CHIP>( TargetHandle_t i_trgt, + std::vector<MemRank> & o_ranks, + uint8_t i_ds ); //------------------------------------------------------------------------------ @@ -1774,12 +1845,15 @@ uint8_t getNumMasterRanksPerDimm<TYPE_MBA>( TargetHandle_t i_trgt, } template<> -uint8_t getNumMasterRanksPerDimm<TYPE_MEM_PORT>( TargetHandle_t i_trgt, - uint8_t i_ds ) -{ - return __getNumMasterRanksPerDimm<TYPE_MEM_PORT>( i_trgt, 0, i_ds ); +uint8_t getNumMasterRanksPerDimm<TYPE_OCMB_CHIP>( TargetHandle_t i_trgt, + uint8_t i_ds ) +{ + // TODO RTC 210072 - Explorer only has one port, however, multiple ports + // will be supported in the future. Updates will need to be made here so we + // can get the relevant port. + TargetHandle_t memPort = getConnectedChild( i_trgt, TYPE_MEM_PORT, 0 ); + return __getNumMasterRanksPerDimm<TYPE_MEM_PORT>( memPort, 0, i_ds ); } - //------------------------------------------------------------------------------ template<TARGETING::TYPE T> @@ -1822,10 +1896,10 @@ uint8_t __getNumRanksPerDimm( TargetHandle_t i_trgt, } else if ( MODEL_AXONE == l_procModel ) { - ATTR_MEM_EFF_NUM_RANKS_PER_DIMM_type attr; - if ( !i_trgt->tryGetAttr<ATTR_MEM_EFF_NUM_RANKS_PER_DIMM>(attr) ) + ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM_type attr; + if ( !i_trgt->tryGetAttr<ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM>(attr) ) { - PRDF_ERR( PRDF_FUNC "tryGetAttr<ATTR_MEM_EFF_NUM_RANKS_PER_DIMM> " + PRDF_ERR( PRDF_FUNC "tryGetAttr<ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM> " "failed: i_trgt=0x%08x", getHuid(i_trgt) ); PRDF_ASSERT( false ); // attribute does not exist for target } @@ -1869,9 +1943,13 @@ uint8_t getNumRanksPerDimm<TYPE_MBA>( TargetHandle_t i_trgt, uint8_t i_ds ) } template<> -uint8_t getNumRanksPerDimm<TYPE_MEM_PORT>( TargetHandle_t i_trgt, uint8_t i_ds ) +uint8_t getNumRanksPerDimm<TYPE_OCMB_CHIP>(TargetHandle_t i_trgt, uint8_t i_ds) { - return __getNumRanksPerDimm<TYPE_MEM_PORT>( i_trgt, 0, i_ds ); + // TODO RTC 210072 - Explorer only has one port, however, multiple ports + // will be supported in the future. Updates will need to be made here so we + // can get the relevant port. + TargetHandle_t memPort = getConnectedChild( i_trgt, TYPE_MEM_PORT, 0 ); + return __getNumRanksPerDimm<TYPE_MEM_PORT>( memPort, 0, i_ds ); } //############################################################################## diff --git a/src/usr/diag/prdf/common/plat/prdfTargetServices.H b/src/usr/diag/prdf/common/plat/prdfTargetServices.H index 8793e8c61..34af865d7 100755 --- a/src/usr/diag/prdf/common/plat/prdfTargetServices.H +++ b/src/usr/diag/prdf/common/plat/prdfTargetServices.H @@ -42,6 +42,10 @@ #include <targeting/common/target.H> #include <prdfParserEnums.H> +#ifdef __HOSTBOOT_MODULE + #include <chipids.H> +#endif + //------------------------------------------------------------------------------ namespace PRDF @@ -145,6 +149,20 @@ TARGETING::CLASS getTargetClass( TARGETING::TargetHandle_t i_target ); */ TARGETING::MODEL getChipModel( TARGETING::TargetHandle_t i_trgt ); +#ifdef __HOSTBOOT_MODULE + +// NOTE: This should be used instead of getChipModel() because of the case of +// MODEL_OCMB, where we need the chip ID to distinguish between Explorer +// and Gemini. + +/** + * @param i_trgt A chip target or any unit target within the chip. + * @return The chip ID. + */ +uint32_t getChipId( TARGETING::TargetHandle_t i_trgt ); + +#endif + /** * @param i_trgt A chip target or any unit target within the chip. * @return The level (EC level) of a chip. @@ -293,7 +311,7 @@ TARGETING::TargetHandle_t getConnectedPeerTarget( TARGETING::TargetHandle_t i_tgt); /** - * @param i_trgt The target MBA, MCA, or MEM_PORT. + * @param i_trgt The target MBA, MCA, OCMB_CHIP, or MEM_PORT. * @param i_rank The target rank. * @return A list of DIMMs connected to the target and rank. */ @@ -301,10 +319,10 @@ TARGETING::TargetHandleList getConnectedDimms( TARGETING::TargetHandle_t i_trgt, const MemRank & i_rank ); /** - * @param i_trgt The target MBA, MCA, or MEM_PORT. + * @param i_trgt The target MBA, MCA, OCMB_CHIP, or MEM_PORT. * @param i_rank The target rank. - * @param i_port Port select, only needed for MBA. MCA and MEM_PORT are - * targets equivalent to the port already. + * @param i_port Port select, only needed for MBA and OCMB_CHIP. MCA and + * MEM_PORT are targets equivalent to the port already. * @return The DIMM connected to the target and rank on a port. */ TARGETING::TargetHandle_t getConnectedDimm( TARGETING::TargetHandle_t i_trgt, @@ -434,7 +452,7 @@ uint8_t getColNumConfig( TARGETING::TargetHandle_t i_trgt ); /** * @brief Returns a sorted list of configured master ranks for an MCA or MBA. - * @param i_trgt MCA, MBA, or MEM_PORT target. + * @param i_trgt MCA, MBA, or OCMB_CHIP target. * @param o_ranks The returned list. * @param i_ds When used, this function will only return the list of ranks * for the target DIMM select. Otherwise, the default is to @@ -450,7 +468,7 @@ void getMasterRanks( TARGETING::TargetHandle_t i_trgt, /** * @brief Returns a sorted list of configured slave ranks for an MCA or MBA. - * @param i_trgt MCA, MBA, or MEM_PORT target. + * @param i_trgt MCA, MBA, or OCMB_CHIP target. * @param o_ranks The returned list. * @param i_ds When used, this function will only return the list of ranks * for the target DIMM select. Otherwise, the default is to @@ -466,7 +484,7 @@ void getSlaveRanks( TARGETING::TargetHandle_t i_trgt, /** * @brief Obtains the number of master ranks per DIMM select. - * @param i_trgt MCA, MBA, or MEM_PORT target. + * @param i_trgt MCA, MBA, or OCMB_CHIP target. * @param i_ds DIMM select. * @return Total number of master ranks configured per DIMM select. */ @@ -477,7 +495,7 @@ uint8_t getNumMasterRanksPerDimm( TARGETING::TargetHandle_t i_trgt, /** * @brief Obtains the total number of ranks (including slave ranks) per DIMM * select. - * @param i_trgt MCA, MBA, or MEM_PORT target. + * @param i_trgt MCA, MBA, or OCMB_CHIP target. * @param i_ds DIMM select. * @return Total number of ranks configured per DIMM select. */ diff --git a/src/usr/diag/prdf/common/plugins/prdfLogParse_common.C b/src/usr/diag/prdf/common/plugins/prdfLogParse_common.C index c6cd47d0b..08aa11600 100644 --- a/src/usr/diag/prdf/common/plugins/prdfLogParse_common.C +++ b/src/usr/diag/prdf/common/plugins/prdfLogParse_common.C @@ -237,6 +237,18 @@ void getTargetInfo( HUID i_chipId, TARGETING::TYPE & o_targetType, l_node, l_chip, l_chiplet ); break; + case TYPE_OCMB_CHIP: + snprintf( o_chipName, i_sz_chipName, "ocmb(n%dp%d)", + l_node, l_chip ); + break; + + case TYPE_MEM_PORT: + l_chip = l_chip / MAX_PORT_PER_OCMB; + l_chiplet = l_chiplet % MAX_PORT_PER_OCMB; + snprintf( o_chipName, i_sz_chipName, "memport(n%dp%dc%d)", + l_node, l_chip, l_chiplet ); + break; + case TYPE_MCS: l_chip = l_chip / MAX_MCS_PER_PROC; l_chiplet = l_chiplet % MAX_MCS_PER_PROC; @@ -286,6 +298,13 @@ void getTargetInfo( HUID i_chipId, TARGETING::TYPE & o_targetType, l_node, l_chip, l_chiplet ); break; + case TYPE_OMI: + l_chip = l_chip / MAX_OMI_PER_PROC; + l_chiplet = l_chiplet % MAX_OMI_PER_PROC; + snprintf( o_chipName, i_sz_chipName, "omi(n%dp%dc%d)", + l_node, l_chip, l_chiplet ); + break; + case TYPE_MEMBUF: snprintf( o_chipName, i_sz_chipName, "mb(n%dp%d)", l_node, l_chip ); diff --git a/src/usr/diag/prdf/common/plugins/prdfMemLogParse.C b/src/usr/diag/prdf/common/plugins/prdfMemLogParse.C index 390178f6e..1518319d1 100644 --- a/src/usr/diag/prdf/common/plugins/prdfMemLogParse.C +++ b/src/usr/diag/prdf/common/plugins/prdfMemLogParse.C @@ -2848,17 +2848,22 @@ void initMemMruStrings( MemoryMruData::MemMruMeld i_mm, bool & o_addDramSite, memset( o_header, '\0', HEADER_SIZE ); memset( o_data, '\0', DATA_SIZE ); - // Get the position info (default MCA). - const char * compStr = "mca"; + // Get the position info (default MBA). + + const char * compStr = "mba"; uint8_t nodePos = i_mm.s.nodePos; - uint8_t chipPos = i_mm.s.procPos; - uint8_t compPos = i_mm.s.chnlPos; + uint8_t chipPos = (i_mm.s.procPos << 3) | i_mm.s.chnlPos; + uint8_t compPos = i_mm.s.mbaPos; - if ( !i_mm.s.isMca ) // MBA + if ( i_mm.s.isMca ) // MCA + { + compStr = "mca"; + chipPos = i_mm.s.procPos; + compPos = i_mm.s.chnlPos; + } + else if ( i_mm.s.isOcmb ) // OCMB { - compStr = "mba"; - chipPos = (i_mm.s.procPos << 3) | i_mm.s.chnlPos; - compPos = i_mm.s.mbaPos; + compStr = "ocmb"; } // Build the header string. @@ -2953,13 +2958,13 @@ void addDramSiteString( const MemoryMruData::ExtendedData & i_extMemMru, } } } - else // IS DIMMs + else // Dram site locations not supported { // Add DQ info. char tmp[DATA_SIZE] = { '\0' }; strcat( io_data, "DQ:" ); - if ( mm.s.isMca ) // MCA + if ( mm.s.isMca || mm.s.isOcmb ) // MCA, OCMB { // There is only one DQ per symbol. snprintf( tmp, DATA_SIZE, "%d", i_extMemMru.dqMapping[dqIdx] ); diff --git a/src/usr/diag/prdf/common/plugins/prdfMemoryMruData.H b/src/usr/diag/prdf/common/plugins/prdfMemoryMruData.H index a9a4498d3..f2fdaff26 100644 --- a/src/usr/diag/prdf/common/plugins/prdfMemoryMruData.H +++ b/src/usr/diag/prdf/common/plugins/prdfMemoryMruData.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2017 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -88,6 +88,10 @@ union MemMruMeld // version field so that the error log parser know which format to // used. + // NOTE: For OCMBs, specified by the isOcmb field, chnlPos will specify + // the MCC position within the proc and mbaPos will specify the + // OMI position within the channel. + #if !( __BYTE_ORDER == __LITTLE_ENDIAN ) uint32_t valid : 1; ///< Used to indicate nothing failed while @@ -106,13 +110,15 @@ union MemMruMeld uint32_t eccSpared : 1; ///< True if symbol is on ECC DRAM uint32_t srank : 3; ///< Slave rank (0-7) // If isMca is specified, then chnlPos above will specify the MCA pos - // and the mbaPos field will be unused + // and the mbaPos field will be unused. See above note for OCMB usage. uint32_t isMca : 1; ///< True if MCA is used as opposed to MBA - uint32_t unused : 3; ///< 3 Bits currently unused + uint32_t isOcmb : 1; ///< True if OCMB is used + uint32_t unused : 2; ///< 2 Bits currently unused #else // Need to reverse this to make the uint32_t look right in the // simulator. - uint32_t unused : 3; + uint32_t unused : 2; + uint32_t isOcmb : 1; uint32_t isMca : 1; uint32_t srank : 3; uint32_t eccSpared : 1; diff --git a/src/usr/diag/prdf/common/plugins/prdfParserEnums.H b/src/usr/diag/prdf/common/plugins/prdfParserEnums.H index af346e57b..1001e185f 100644 --- a/src/usr/diag/prdf/common/plugins/prdfParserEnums.H +++ b/src/usr/diag/prdf/common/plugins/prdfParserEnums.H @@ -109,8 +109,14 @@ enum PositionBounds MAX_OMI_PER_MCC = 2, MAX_OMI_PER_OMIC = 3, + MAX_OMI_PER_MC = 8, + MAX_OMI_PER_PROC = MAX_OMI_PER_MC * MAX_MC_PER_PROC, MAX_OCMB_PER_OMI = 1, + MAX_OCMB_PER_MCC = MAX_OCMB_PER_OMI * MAX_OMI_PER_MCC, + + // TODO RTC 210072 - Support multiple ports + MAX_PORT_PER_OCMB = 1, MAX_SUB_PORT = 2, diff --git a/src/usr/diag/prdf/common/plugins/prdfParserUtils.C b/src/usr/diag/prdf/common/plugins/prdfParserUtils.C index 9d2233e75..2f9bdb458 100644 --- a/src/usr/diag/prdf/common/plugins/prdfParserUtils.C +++ b/src/usr/diag/prdf/common/plugins/prdfParserUtils.C @@ -87,9 +87,9 @@ uint8_t symbol2Dq<TARGETING::TYPE_MCA>( uint8_t i_symbol ) //------------------------------------------------------------------------------ template<> -uint8_t symbol2Dq<TARGETING::TYPE_MEM_PORT>( uint8_t i_symbol ) +uint8_t symbol2Dq<TARGETING::TYPE_OCMB_CHIP>( uint8_t i_symbol ) { - // MEM_PORT case is identical to MCA + // OCMB_CHIP case is identical to MCA return symbol2Dq<TARGETING::TYPE_MCA>(i_symbol); } @@ -122,10 +122,12 @@ uint8_t symbol2PortSlct<TARGETING::TYPE_MCA>( uint8_t i_symbol ) //------------------------------------------------------------------------------ template<> -uint8_t symbol2PortSlct<TARGETING::TYPE_MEM_PORT>( uint8_t i_symbol ) +uint8_t symbol2PortSlct<TARGETING::TYPE_OCMB_CHIP>( uint8_t i_symbol ) { - // Port select does not exist on MEM_PORT. Always return 0 so that code will - // continue to work. + // TODO RTC 210072 - Explorer only has one port, as such we can just + // return 0. However, multiple ports will be supported in the future, + // We'll need to figure out how to convert the symbol to a port select for + // OCMB at that time. return 0; } @@ -149,8 +151,8 @@ uint8_t dq2Symbol<TARGETING::TYPE_MBA>( uint8_t i_dq, uint8_t i_ps ) //------------------------------------------------------------------------------ -template<> -uint8_t dq2Symbol<TARGETING::TYPE_MCA>( uint8_t i_dq, uint8_t i_ps ) +template<TARGETING::TYPE T> +uint8_t dq2Symbol( uint8_t i_dq, uint8_t i_ps ) { uint8_t symbol = SYMBOLS_PER_RANK; @@ -175,14 +177,12 @@ uint8_t dq2Symbol<TARGETING::TYPE_MCA>( uint8_t i_dq, uint8_t i_ps ) return symbol; } -//------------------------------------------------------------------------------ - -template<> -uint8_t dq2Symbol<TARGETING::TYPE_MEM_PORT>( uint8_t i_dq, uint8_t i_ps ) -{ - // MEM_PORT case is identical to MCA - return dq2Symbol<TARGETING::TYPE_MCA>( i_dq, i_ps ); -} +template +uint8_t dq2Symbol<TARGETING::TYPE_MCA>( uint8_t i_dq, uint8_t i_ps ); +template +uint8_t dq2Symbol<TARGETING::TYPE_MEM_PORT>( uint8_t i_dq, uint8_t i_ps ); +template +uint8_t dq2Symbol<TARGETING::TYPE_OCMB_CHIP>( uint8_t i_dq, uint8_t i_ps ); //------------------------------------------------------------------------------ @@ -218,9 +218,9 @@ uint8_t nibble2Symbol<TARGETING::TYPE_MCA>( uint8_t i_x4Dram ) //------------------------------------------------------------------------------ template<> -uint8_t nibble2Symbol<TARGETING::TYPE_MEM_PORT>( uint8_t i_x4Dram ) +uint8_t nibble2Symbol<TARGETING::TYPE_OCMB_CHIP>( uint8_t i_x4Dram ) { - // MEM_PORT case is identical to MCA + // OCMB_CHIP case is identical to MCA return nibble2Symbol<TARGETING::TYPE_MCA>(i_x4Dram); } @@ -258,9 +258,9 @@ uint8_t byte2Symbol<TARGETING::TYPE_MCA>( uint8_t i_x8Dram ) //------------------------------------------------------------------------------ template<> -uint8_t byte2Symbol<TARGETING::TYPE_MEM_PORT>( uint8_t i_x8Dram ) +uint8_t byte2Symbol<TARGETING::TYPE_OCMB_CHIP>( uint8_t i_x8Dram ) { - // MEM_PORT case is identical to MCA + // OCMB_CHIP case is identical to MCA return byte2Symbol<TARGETING::TYPE_MCA>(i_x8Dram); } @@ -286,9 +286,9 @@ uint8_t symbol2Nibble<TARGETING::TYPE_MCA>( uint8_t i_symbol ) //------------------------------------------------------------------------------ template<> -uint8_t symbol2Nibble<TARGETING::TYPE_MEM_PORT>( uint8_t i_symbol ) +uint8_t symbol2Nibble<TARGETING::TYPE_OCMB_CHIP>( uint8_t i_symbol ) { - // MEM_PORT case is identical to MCA + // OCMB_CHIP case is identical to MCA return symbol2Nibble<TARGETING::TYPE_MCA>(i_symbol); } @@ -314,9 +314,9 @@ uint8_t symbol2Byte<TARGETING::TYPE_MCA>( uint8_t i_symbol ) //------------------------------------------------------------------------------ template<> -uint8_t symbol2Byte<TARGETING::TYPE_MEM_PORT>( uint8_t i_symbol ) +uint8_t symbol2Byte<TARGETING::TYPE_OCMB_CHIP>( uint8_t i_symbol ) { - // MEM_PORT case is identical to MCA + // OCMB_CHIP case is identical to MCA return symbol2Byte<TARGETING::TYPE_MCA>(i_symbol); } diff --git a/src/usr/diag/prdf/common/prdfMain_common.C b/src/usr/diag/prdf/common/prdfMain_common.C index fd23cf4d1..09cfe2212 100755 --- a/src/usr/diag/prdf/common/prdfMain_common.C +++ b/src/usr/diag/prdf/common/prdfMain_common.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2018 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -47,6 +47,7 @@ #ifdef __HOSTBOOT_RUNTIME #include <prdfP9McbistDomain.H> +#include <prdfP9OcmbChipDomain.H> #include <prdfCenMbaDomain.H> #endif @@ -172,6 +173,10 @@ errlHndl_t noLock_initialize() { ((MbaDomain *)systemPtr->GetDomain(MBA_DOMAIN))->handleRrFo(); } + else if ( MODEL_AXONE == procModel ) + { + ((OcmbChipDomain *)systemPtr->GetDomain(OCMB_DOMAIN))->handleRrFo(); + } else { PRDF_ERR( PRDF_FUNC "Master PROC model %d not supported", procModel ); diff --git a/src/usr/diag/prdf/framework/prdfFileRegisterAccess.C b/src/usr/diag/prdf/framework/prdfFileRegisterAccess.C index dfdaabf9c..ed5d3ec0d 100755 --- a/src/usr/diag/prdf/framework/prdfFileRegisterAccess.C +++ b/src/usr/diag/prdf/framework/prdfFileRegisterAccess.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -37,7 +37,7 @@ uint32_t FileScomAccessor::Access( TargetHandle_t i_target, BitString & bs, uint64_t registerId, - MopRegisterAccess::Operation operation) const + RegisterAccess::Operation operation) const { #define PRDF_FUNC "[FileScomAccessor::Access()] " @@ -48,13 +48,13 @@ uint32_t FileScomAccessor::Access( switch (operation) { - case MopRegisterAccess::WRITE: + case RegisterAccess::WRITE: // TODO: RTC 62076 move BitString class to 64-bit data = (((uint64_t)bs.getFieldJustify( 0, 32)) << 32) | ((uint64_t)bs.getFieldJustify(32, 32)); firData.putScom( i_target, registerId, data); break; - case MopRegisterAccess::READ: + case RegisterAccess::READ: firData.getScom( i_target, registerId, data); // TODO: RTC 62076 move BitString class to 64-bit bs.setFieldJustify( 0, 32, data >> 32); diff --git a/src/usr/diag/prdf/framework/prdfFileRegisterAccess.H b/src/usr/diag/prdf/framework/prdfFileRegisterAccess.H index 61d255e8a..84b749a58 100755 --- a/src/usr/diag/prdf/framework/prdfFileRegisterAccess.H +++ b/src/usr/diag/prdf/framework/prdfFileRegisterAccess.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -71,7 +71,7 @@ class FileScomAccessor : public ScomAccessor virtual uint32_t Access(TARGETING::TargetHandle_t i_target, BitString & bs, uint64_t registerId, - MopRegisterAccess::Operation operation) const; + RegisterAccess::Operation operation) const; }; } // End namespace PRDF diff --git a/src/usr/diag/prdf/makefile b/src/usr/diag/prdf/makefile index ed8b7c1ce..8fda714ed 100755 --- a/src/usr/diag/prdf/makefile +++ b/src/usr/diag/prdf/makefile @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2012,2018 +# Contributors Listed Below - COPYRIGHT 2012,2019 # [+] International Business Machines Corp. # # @@ -39,13 +39,16 @@ include prdf_hb_only.mk # Will define PRD_SRC_PATH and PRD_INC_PATH include common/prdf_common_fsp_and_hb.mk include common/framework/prdf_framework.mk include common/plat/p9/prdf_plat_p9.mk +include common/plat/axone/prdf_plat_axone.mk include common/plat/cen/prdf_plat_cen.mk include common/plat/mem/prdf_plat_mem.mk include common/plat/centaur/prdf_plat_centaur.mk include common/plat/cumulus/prdf_plat_cumulus.mk include common/plat/nimbus/prdf_plat_nimbus.mk +include common/plat/explorer/prdf_plat_explorer.mk include plat/cen/prdf_plat_cen_hb_only.mk include plat/mem/prdf_plat_mem_hb_only.mk +include plat/explorer/prdf_plat_explorer_hb_only.mk include plat/p9/prdf_plat_p9_hb_only.mk VPATH += ${prd_vpath} diff --git a/src/usr/diag/prdf/occ_firdata/prdfWriteHomerFirData.C b/src/usr/diag/prdf/occ_firdata/prdfWriteHomerFirData.C index d3b8a72ee..2e9b6f963 100644 --- a/src/usr/diag/prdf/occ_firdata/prdfWriteHomerFirData.C +++ b/src/usr/diag/prdf/occ_firdata/prdfWriteHomerFirData.C @@ -621,28 +621,11 @@ void getAddresses( TrgtMap_t & io_targMap ) 0x07013340, // OMIDLFIR }; - io_targMap[TRGT_OCMB][REG_GLBL] = + io_targMap[TRGT_OMIC][REG_REG] = { - 0x08040000, // MB_CHIPLET_CS_FIR - 0x08040001, // MB_CHIPLET_RE_FIR - 0x08040004, // MB_CHIPLET_SPA_FIR - }; - - io_targMap[TRGT_OCMB][REG_FIR] = - { - 0x0804000a, // MB_LFIR - 0x08010870, // MMIOFIR - 0x08011400, // SRQFIR - 0x08011800, // MCBISTFIR - 0x08011c00, // RDFFIR - 0x08012400, // TLXFIR - 0x08012800, // OMIDLFIR - }; - - io_targMap[TRGT_OCMB][REG_REG] = - { - 0x08040002, // MB_CHIPLET_FIR_MASK - 0x08040007, // MB_CHIPLET_SPA_FIR_MASK + 0x07013353, // DL0_ERROR_HOLD + 0x07013363, // DL1_ERROR_HOLD + 0x07013373, // DL2_ERROR_HOLD }; // EC level handling will be done with a @@ -721,15 +704,22 @@ void __initChipInfo( TargetHandle_t i_chip, HOMER_ChipType_t i_chipModel, uint32_t chipPos = getTargetPosition( i_chip ); PRDF_ASSERT( chipPos < i_maxChipsPerNode ); - // Get the chip FSI address. - FSI::FsiLinkInfo_t fsiInfo; - FSI::getFsiLinkInfo( i_chip, fsiInfo ); - // Fill in the HOMER chip info. o_chipInfo.hChipType = HOMER_getChip( i_chipModel ); o_chipInfo.hChipType.chipPos = chipPos; - o_chipInfo.hChipType.fsiBaseAddr = fsiInfo.baseAddr; o_chipInfo.hChipType.chipEcLevel = i_chip->getAttr<ATTR_EC>(); + + if( HOMER_CHIP_EXPLORER == i_chipModel ) + { + //@todo - RTC:201781 - Add i2c information + } + else + { + // Get the chip FSI address. + FSI::FsiLinkInfo_t fsiInfo; + FSI::getFsiLinkInfo( i_chip, fsiInfo ); + o_chipInfo.hChipType.fsiBaseAddr = fsiInfo.baseAddr; + } } // Returns a right justified config mask of the unit @@ -942,20 +932,26 @@ errlHndl_t getHwConfig( std::vector<HOMER_ChipInfo_t> & o_chipInfVector, // Iterate all of the OCMB chips. for ( auto & ocmb : getFunctionalTargetList(TYPE_OCMB_CHIP) ) { - // Get the chip model type. - HOMER_ChipType_t modelType = HOMER_CHIP_INVALID; - switch ( getChipModel(ocmb) ) + // Get the OCMB chip type. + HOMER_ChipType_t ocmbType = HOMER_CHIP_INVALID; + switch ( getChipId(ocmb) ) { - case MODEL_EXPLORER: modelType = HOMER_CHIP_EXPLORER; break; + case POWER_CHIPID::GEMINI_16: + // Skip Gemini OCMBs. They can exist, but PRD won't support + // them (set invalid). + ocmbType = HOMER_CHIP_INVALID; break; + case POWER_CHIPID::EXPLORER_16: + ocmbType = HOMER_CHIP_EXPLORER; break; default: - PRDF_ERR( FUNC "Unsupported chip model %d on 0x%08x", - modelType, getHuid(ocmb) ); + PRDF_ERR( FUNC "Unsupported chip ID 0x%08x on 0x%08x", + getChipId(ocmb), getHuid(ocmb) ); PRDF_ASSERT( false ); } + if ( HOMER_CHIP_INVALID == ocmbType ) continue; // Init the chip info. HOMER_ChipInfo_t ci; - __initChipInfo( ocmb, modelType, MAX_OCMB_PER_NODE, ci ); + __initChipInfo( ocmb, ocmbType, MAX_OCMB_PER_NODE, ci ); // NOTE: Explorer does not have any unit data. diff --git a/src/usr/diag/prdf/plat/explorer/prdfExplorerPlugins.C b/src/usr/diag/prdf/plat/explorer/prdfExplorerPlugins.C new file mode 100644 index 000000000..4a8dba1a2 --- /dev/null +++ b/src/usr/diag/prdf/plat/explorer/prdfExplorerPlugins.C @@ -0,0 +1,89 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/diag/prdf/plat/explorer/prdfExplorerPlugins.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +// Framework includes +#include <iipServiceDataCollector.h> +#include <prdfExtensibleChip.H> +#include <prdfPluginMap.H> + +// Platform includes +#include <prdfMemDbUtils.H> +#include <prdfMemEccAnalysis.H> +//#include <prdfOcmbDataBundle.H> +#include <prdfPlatServices.H> + +using namespace TARGETING; + +namespace PRDF +{ + +using namespace PlatServices; + +namespace explorer_ocmb +{ + +//############################################################################## +// +// MCBISTFIR +// +//############################################################################## + +/** + * @brief MCBISTFIR[10] - MCBIST Command Complete. + * @param i_chip An OCMB chip. + * @param io_sc The step code data struct. + * @return SUCCESS + */ +int32_t McbistCmdComplete( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + #define PRDF_FUNC "[explorer_ocmb::McbistCmdComplete] " + + return SUCCESS; + + // Tell the TD controller there was a command complete attention. + OcmbDataBundle * db = getOcmbDataBundle( i_chip ); + if ( SUCCESS != db->getTdCtlr()->handleCmdComplete(io_sc) ) + { + // Something failed. It is possible the command complete attention has + // not been cleared. Make the rule code do it. + return SUCCESS; + } + else + { + // Everything was successful. Whether we started a new command or told + // MDIA to do it, the command complete bit has already been cleared. + // Don't do it again. + return PRD_NO_CLEAR_FIR_BITS; + } + + #undef PRDF_FUNC +} +PRDF_PLUGIN_DEFINE( explorer_ocmb, McbistCmdComplete ); + +} // end namespace explorer_ocmb + +} // end namespace PRDF + diff --git a/src/usr/diag/prdf/plat/explorer/prdf_plat_explorer_hb_only.mk b/src/usr/diag/prdf/plat/explorer/prdf_plat_explorer_hb_only.mk new file mode 100644 index 000000000..ee1464d3e --- /dev/null +++ b/src/usr/diag/prdf/plat/explorer/prdf_plat_explorer_hb_only.mk @@ -0,0 +1,42 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/plat/explorer/prdf_plat_explorer_hb_only.mk $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2019 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +# NOTE: PRD_SRC_PATH and PRD_INC_PATH must be defined before including this file + +################################################################################ +# Paths common to both IPL and runtime +################################################################################ + +prd_vpath += ${PRD_SRC_PATH}/plat/explorer + +prd_incpath += ${PRD_SRC_PATH}/plat/explorer + +################################################################################ +# Hostboot only object files common to both IPL and runtime +################################################################################ + +# plat/mem/ (rule plugin related) +prd_rule_plugin += prdfExplorerPlugins.o + diff --git a/src/usr/diag/prdf/plat/mem/prdfMemDsd.H b/src/usr/diag/prdf/plat/mem/prdfMemDsd.H index 5990a902e..063e92775 100644 --- a/src/usr/diag/prdf/plat/mem/prdfMemDsd.H +++ b/src/usr/diag/prdf/plat/mem/prdfMemDsd.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -47,7 +47,7 @@ class DsdEvent : public TdEntry /** * @brief Constructor - * @param i_chip MCA or MBA. + * @param i_chip MCA, MBA, or OCMB. * @param i_rank Rank reporting chip mark. */ DsdEvent<T>( ExtensibleChip * i_chip, const MemRank & i_rank, diff --git a/src/usr/diag/prdf/plat/mem/prdfMemDsd_ipl.C b/src/usr/diag/prdf/plat/mem/prdfMemDsd_ipl.C index 70a6be7f2..9dbaeeb3c 100644 --- a/src/usr/diag/prdf/plat/mem/prdfMemDsd_ipl.C +++ b/src/usr/diag/prdf/plat/mem/prdfMemDsd_ipl.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -30,6 +30,8 @@ #include <prdfMemDqBitmap.H> #include <prdfMemDsd.H> +#include <hwp_wrappers.H> + using namespace TARGETING; namespace PRDF @@ -37,18 +39,12 @@ namespace PRDF using namespace PlatServices; -//############################################################################## -// -// Specializations for MBA -// -//############################################################################## - -template<> -uint32_t DsdEvent<TYPE_MBA>::checkEcc( const uint32_t & i_eccAttns, - STEP_CODE_DATA_STRUCT & io_sc, - bool & o_done ) +template<TARGETING::TYPE T> +uint32_t DsdEvent<T>::checkEcc( const uint32_t & i_eccAttns, + STEP_CODE_DATA_STRUCT & io_sc, + bool & o_done ) { - #define PRDF_FUNC "[DsdEvent<TYPE_MBA>::checkEcc] " + #define PRDF_FUNC "[DsdEvent<T>::checkEcc] " uint32_t o_rc = SUCCESS; @@ -71,7 +67,7 @@ uint32_t DsdEvent<TYPE_MBA>::checkEcc( const uint32_t & i_eccAttns, // At this point we don't actually have an address for the UE. The // best we can do is get the address in which the command stopped. MemAddr addr; - o_rc = getMemMaintAddr<TYPE_MBA>( iv_chip, addr ); + o_rc = getMemMaintAddr<T>( iv_chip, addr ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "getMemMaintAddr(0x%08x) failed", @@ -79,8 +75,8 @@ uint32_t DsdEvent<TYPE_MBA>::checkEcc( const uint32_t & i_eccAttns, break; } - o_rc = MemEcc::handleMemUe<TYPE_MBA>( iv_chip, addr, - UE_TABLE::SCRUB_UE, io_sc ); + o_rc = MemEcc::handleMemUe<T>( iv_chip, addr, + UE_TABLE::SCRUB_UE, io_sc ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "handleMemUe(0x%08x,0x%02x) failed", @@ -101,12 +97,12 @@ uint32_t DsdEvent<TYPE_MBA>::checkEcc( const uint32_t & i_eccAttns, //------------------------------------------------------------------------------ -template<> -uint32_t DsdEvent<TYPE_MBA>::verifySpare( const uint32_t & i_eccAttns, - STEP_CODE_DATA_STRUCT & io_sc, - bool & o_done ) +template<TARGETING::TYPE T> +uint32_t DsdEvent<T>::verifySpare( const uint32_t & i_eccAttns, + STEP_CODE_DATA_STRUCT & io_sc, + bool & o_done ) { - #define PRDF_FUNC "[DsdEvent<TYPE_MBA>::verifySpare] " + #define PRDF_FUNC "[DsdEvent<T>::verifySpare] " uint32_t o_rc = SUCCESS; @@ -166,7 +162,7 @@ uint32_t DsdEvent<TYPE_MBA>::verifySpare( const uint32_t & i_eccAttns, PRDFSIG_DsdDramSpared ); // Remove the chip mark. - o_rc = MarkStore::clearChipMark<TYPE_MBA>( iv_chip, iv_rank ); + o_rc = MarkStore::clearChipMark<T>( iv_chip, iv_rank ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "clearChipMark(0x%08x,0x%02x) failed", @@ -190,7 +186,7 @@ uint32_t DsdEvent<TYPE_MBA>::verifySpare( const uint32_t & i_eccAttns, template<> uint32_t DsdEvent<TYPE_MBA>::startCmd() { - #define PRDF_FUNC "[DsdEvent::startCmd] " + #define PRDF_FUNC "[DsdEvent<TYPE_MBA>::startCmd] " uint32_t o_rc = SUCCESS; @@ -231,7 +227,54 @@ uint32_t DsdEvent<TYPE_MBA>::startCmd() //------------------------------------------------------------------------------ template<> -uint32_t DsdEvent<TYPE_MBA>::startNextPhase( STEP_CODE_DATA_STRUCT & io_sc ) +uint32_t DsdEvent<TYPE_OCMB_CHIP>::startCmd() +{ + #define PRDF_FUNC "[DsdEvent<TYPE_OCMB_CHIP>::startCmd] " + + uint32_t o_rc = SUCCESS; + + #ifdef CONFIG_AXONE + + mss::mcbist::stop_conditions<mss::mc_type::EXPLORER> stopCond; + + switch ( iv_phase ) + { + case TD_PHASE_1: + // Start the steer cleanup procedure on this master rank. + o_rc = startTdSteerCleanup<TYPE_OCMB_CHIP>( iv_chip, iv_rank, + MASTER_RANK, stopCond ); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "startTdSteerCleanup(0x%08x,0x%2x) failed", + iv_chip->getHuid(), getKey() ); + } + break; + + case TD_PHASE_2: + // Start the superfast read procedure on this master rank. + o_rc = startTdSfRead<TYPE_OCMB_CHIP>( iv_chip, iv_rank, MASTER_RANK, + stopCond ); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "startTdSfRead(0x%08x,0x%2x) failed", + iv_chip->getHuid(), getKey() ); + } + break; + + default: PRDF_ASSERT( false ); // invalid phase + } + + #endif + + return o_rc; + + #undef PRDF_FUNC +} + +//------------------------------------------------------------------------------ + +template<TARGETING::TYPE T> +uint32_t DsdEvent<T>::startNextPhase( STEP_CODE_DATA_STRUCT & io_sc ) { uint32_t signature = 0; @@ -260,5 +303,9 @@ uint32_t DsdEvent<TYPE_MBA>::startNextPhase( STEP_CODE_DATA_STRUCT & io_sc ) //------------------------------------------------------------------------------ +// Avoid linker errors with the template. +template class DsdEvent<TYPE_MBA>; +template class DsdEvent<TYPE_OCMB_CHIP>; + } // end namespace PRDF diff --git a/src/usr/diag/prdf/plat/mem/prdfMemDsd_rt.C b/src/usr/diag/prdf/plat/mem/prdfMemDsd_rt.C index 42b7eb9fc..1478a666d 100644 --- a/src/usr/diag/prdf/plat/mem/prdfMemDsd_rt.C +++ b/src/usr/diag/prdf/plat/mem/prdfMemDsd_rt.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -29,6 +29,8 @@ #include <prdfCenMbaExtraSig.H> #include <prdfMemDsd.H> +#include <hwp_wrappers.H> + using namespace TARGETING; namespace PRDF @@ -36,18 +38,12 @@ namespace PRDF using namespace PlatServices; -//############################################################################## -// -// Specializations for MBA -// -//############################################################################## - -template<> -uint32_t DsdEvent<TYPE_MBA>::checkEcc( const uint32_t & i_eccAttns, - STEP_CODE_DATA_STRUCT & io_sc, - bool & o_done ) +template<TARGETING::TYPE T> +uint32_t DsdEvent<T>::checkEcc( const uint32_t & i_eccAttns, + STEP_CODE_DATA_STRUCT & io_sc, + bool & o_done ) { - #define PRDF_FUNC "[DsdEvent<TYPE_MBA>::checkEcc] " + #define PRDF_FUNC "[DsdEvent<T>::checkEcc] " uint32_t o_rc = SUCCESS; @@ -64,7 +60,7 @@ uint32_t DsdEvent<TYPE_MBA>::checkEcc( const uint32_t & i_eccAttns, // At this point we don't actually have an address for the UE. The // best we can do is get the address in which the command stopped. MemAddr addr; - o_rc = getMemMaintAddr<TYPE_MBA>( iv_chip, addr ); + o_rc = getMemMaintAddr<T>( iv_chip, addr ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "getMemMaintAddr(0x%08x) failed", @@ -72,8 +68,8 @@ uint32_t DsdEvent<TYPE_MBA>::checkEcc( const uint32_t & i_eccAttns, break; } - o_rc = MemEcc::handleMemUe<TYPE_MBA>( iv_chip, addr, - UE_TABLE::SCRUB_UE, io_sc ); + o_rc = MemEcc::handleMemUe<T>( iv_chip, addr, + UE_TABLE::SCRUB_UE, io_sc ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "handleMemUe(0x%08x,0x%02x) failed", @@ -83,7 +79,7 @@ uint32_t DsdEvent<TYPE_MBA>::checkEcc( const uint32_t & i_eccAttns, // Because of the UE, any further TPS requests will likely have no // effect. So ban all subsequent requests. - MemDbUtils::banTps<TYPE_MBA>( iv_chip, addr.getRank() ); + MemDbUtils::banTps<T>( iv_chip, addr.getRank() ); // Leave the mark in place and abort this procedure. o_done = true; break; @@ -114,12 +110,12 @@ uint32_t DsdEvent<TYPE_MBA>::checkEcc( const uint32_t & i_eccAttns, //------------------------------------------------------------------------------ -template<> -uint32_t DsdEvent<TYPE_MBA>::verifySpare( const uint32_t & i_eccAttns, - STEP_CODE_DATA_STRUCT & io_sc, - bool & o_done ) +template<TARGETING::TYPE T> +uint32_t DsdEvent<T>::verifySpare( const uint32_t & i_eccAttns, + STEP_CODE_DATA_STRUCT & io_sc, + bool & o_done ) { - #define PRDF_FUNC "[DsdEvent<TYPE_MBA>::verifySpare] " + #define PRDF_FUNC "[DsdEvent<T>::verifySpare] " uint32_t o_rc = SUCCESS; @@ -134,7 +130,7 @@ uint32_t DsdEvent<TYPE_MBA>::verifySpare( const uint32_t & i_eccAttns, // error (i.e. a UE). bool lastAddr = false; - o_rc = didCmdStopOnLastAddr<TYPE_MBA>( iv_chip, MASTER_RANK, lastAddr ); + o_rc = didCmdStopOnLastAddr<T>( iv_chip, MASTER_RANK, lastAddr ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "didCmdStopOnLastAddr(0x%08x) failed", @@ -155,7 +151,7 @@ uint32_t DsdEvent<TYPE_MBA>::verifySpare( const uint32_t & i_eccAttns, io_sc.service_data->setSignature( iv_chip->getHuid(), PRDFSIG_DsdDramSpared ); // Remove the chip mark. - o_rc = MarkStore::clearChipMark<TYPE_MBA>( iv_chip, iv_rank ); + o_rc = MarkStore::clearChipMark<T>( iv_chip, iv_rank ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "clearChipMark(0x%08x,0x%02x) failed", @@ -179,7 +175,7 @@ uint32_t DsdEvent<TYPE_MBA>::verifySpare( const uint32_t & i_eccAttns, template<> uint32_t DsdEvent<TYPE_MBA>::startCmd() { - #define PRDF_FUNC "[DsdEvent::startCmd] " + #define PRDF_FUNC "[DsdEvent<TYPE_MBA>::startCmd] " uint32_t o_rc = SUCCESS; @@ -224,7 +220,38 @@ uint32_t DsdEvent<TYPE_MBA>::startCmd() //------------------------------------------------------------------------------ template<> -uint32_t DsdEvent<TYPE_MBA>::startNextPhase( STEP_CODE_DATA_STRUCT & io_sc ) +uint32_t DsdEvent<TYPE_OCMB_CHIP>::startCmd() +{ + #define PRDF_FUNC "[DsdEvent<TYPE_OCMB_CHIP>::startCmd] " + + uint32_t o_rc = SUCCESS; + + #ifdef CONFIG_AXONE + + mss::mcbist::stop_conditions<mss::mc_type::EXPLORER> stopCond; + + stopCond.set_pause_on_ue(mss::ON); + + // Start the time based scrub procedure on this master rank. + o_rc = startTdScrub<TYPE_OCMB_CHIP>( iv_chip, iv_rank, MASTER_RANK, + stopCond ); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "startTdScrub(0x%08x,0x%2x) failed", + iv_chip->getHuid(), getKey() ); + } + + #endif + + return o_rc; + + #undef PRDF_FUNC +} + +//------------------------------------------------------------------------------ + +template<TARGETING::TYPE T> +uint32_t DsdEvent<T>::startNextPhase( STEP_CODE_DATA_STRUCT & io_sc ) { uint32_t signature = 0; @@ -258,5 +285,9 @@ uint32_t DsdEvent<TYPE_MBA>::startNextPhase( STEP_CODE_DATA_STRUCT & io_sc ) //------------------------------------------------------------------------------ +// Avoid linker errors with the template. +template class DsdEvent<TYPE_MBA>; +template class DsdEvent<TYPE_OCMB_CHIP>; + } // end namespace PRDF diff --git a/src/usr/diag/prdf/plat/mem/prdfMemDynDealloc.C b/src/usr/diag/prdf/plat/mem/prdfMemDynDealloc.C index 41b0de3ea..40653ee09 100644 --- a/src/usr/diag/prdf/plat/mem/prdfMemDynDealloc.C +++ b/src/usr/diag/prdf/plat/mem/prdfMemDynDealloc.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017,2018 */ +/* Contributors Listed Below - COPYRIGHT 2017,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -64,7 +64,7 @@ bool isEnabled() !isMfgAvpEnabled() && !isMfgHdatAvpEnabled() ); } -int32_t __getAddrConfig( ExtensibleChip * i_mcaChip, uint8_t i_dslct, +int32_t __getAddrConfig( ExtensibleChip * i_chip, uint8_t i_dslct, bool & o_twoDimmConfig, uint8_t & o_mrnkBits, uint8_t & o_srnkBits, uint8_t & o_extraRowBits ) { @@ -72,12 +72,12 @@ int32_t __getAddrConfig( ExtensibleChip * i_mcaChip, uint8_t i_dslct, int32_t o_rc = SUCCESS; - SCAN_COMM_REGISTER_CLASS * reg = i_mcaChip->getRegister( "MC_ADDR_TRANS" ); + SCAN_COMM_REGISTER_CLASS * reg = i_chip->getRegister( "MC_ADDR_TRANS" ); o_rc = reg->Read(); if ( SUCCESS != o_rc ) { - PRDF_ERR( PRDF_FUNC "Read failed on MC_ADDR_TRANS: i_mcaChip=0x%08x", - i_mcaChip->getHuid() ); + PRDF_ERR( PRDF_FUNC "Read failed on MC_ADDR_TRANS: i_chip=0x%08x", + i_chip->getHuid() ); return o_rc; } @@ -98,8 +98,8 @@ int32_t __getAddrConfig( ExtensibleChip * i_mcaChip, uint8_t i_dslct, // for some reason B2 is valid, there is definitely a bug. if ( reg->IsBitSet(i_dslct ? 28:12) ) { - PRDF_ERR( PRDF_FUNC "B2 enabled in MC_ADDR_TRANS: i_mcaChip=0x%08x " - "i_dslct=%d", i_mcaChip->getHuid(), i_dslct ); + PRDF_ERR( PRDF_FUNC "B2 enabled in MC_ADDR_TRANS: i_chip=0x%08x " + "i_dslct=%d", i_chip->getHuid(), i_dslct ); return FAIL; } @@ -386,7 +386,7 @@ int32_t __getPortAddr<TYPE_MCA>( ExtensibleChip * i_chip, MemAddr i_addr, // Local vars for address fields uint64_t col = reverseBits(i_addr.getCol(), 7); // C9 C8 C7 C6 C5 C4 C3 uint64_t row = reverseBits(i_addr.getRow(), 18); // R17 R16 R15 .. R1 R0 - uint64_t bnk = i_addr.getBank(); // BG0 BG1 B0 B1 B2 + uint64_t bnk = i_addr.getBank(); // B0 B1 B2 BG0 BG1 uint64_t srnk = i_addr.getRank().getSlave(); // S0 S1 S2 uint64_t mrnk = i_addr.getRank().getRankSlct(); // M0 M1 uint64_t dslct = i_addr.getRank().getDimmSlct(); // D @@ -473,6 +473,266 @@ int32_t __getPortAddr<TYPE_MCA>( ExtensibleChip * i_chip, MemAddr i_addr, return o_rc; } +void __adjustCapiAddrBitPos( uint8_t & io_bitPos ) +{ + // Note: the translation bitmaps are all 5 bits that are defined + // consistently as: + // 00000 = CAPI_Address(5) + // 00001 = CAPI_Address(6) + // 00010 = CAPI_Address(7) + // ... + // 01010 = CAPI_Address(15) + // 01011 = CAPI_Address(31) + // 01100 = CAPI_Address(32) + // ... + // 10011 = CAPI_Address(39) + // So the value from the regs can be converted to the CAPI address bit pos + // by adding 5 if the value is less than or equal to 10, or by adding 20 + // if it is above 10. + + if ( io_bitPos <= 10 ) + { + io_bitPos += 5; + } + else + { + io_bitPos += 20; + } +} + +template <> +int32_t __getPortAddr<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, MemAddr i_addr, + uint64_t & o_addr ) +{ + #define PRDF_FUNC "[MemDealloc::__getPortAddr<TYPE_OCMB_CHIP>] " + + int32_t o_rc = SUCCESS; + + o_addr = 0; + + // Local vars for address fields + uint64_t col = reverseBits(i_addr.getCol(), 7); // C9 C8 C7 C6 C5 C4 C3 + uint64_t row = reverseBits(i_addr.getRow(), 18); // R17 R16 R15 .. R1 R0 + uint64_t bnk = i_addr.getBank(); // B0 B1 B2 BG0 BG1 + uint64_t srnk = i_addr.getRank().getSlave(); // S0 S1 S2 + uint64_t mrnk = i_addr.getRank().getRankSlct(); // M0 M1 + uint64_t dslct = i_addr.getRank().getDimmSlct(); // D + + // Determine if a two DIMM config is used. Also, determine how many + // mrank (M0-M1), srnk (S0-S2), or extra row (R17-R15) bits are used. + bool twoDimmConfig; + uint8_t mrnkBits, srnkBits, extraRowBits; + o_rc = __getAddrConfig( i_chip, dslct, twoDimmConfig, mrnkBits, srnkBits, + extraRowBits ); + if ( SUCCESS != o_rc ) return o_rc; + + // Mask off the non-configured bits. If this address came from hardware, + // this would not be a problem. However, the get_mrank_range() and + // get_srank_range() HWPS got lazy just set the entire fields and did not + // take into account the actual bit ranges. + mrnk = __maskBits( mrnk, mrnkBits ); + srnk = __maskBits( srnk, srnkBits ); + row = __maskBits( row, 15 + extraRowBits ); + + // Insert the needed bits based on the config defined in the MC Address + // Translation Registers. + + uint8_t bitPos = 0; + + // Split the row into its components. + uint8_t r17 = (row & 0x20000) >> 17; + uint8_t r16 = (row & 0x10000) >> 16; + uint8_t r15 = (row & 0x08000) >> 15; + uint16_t r14_r0 = (row & 0x07fff); + + // Split the master rank and slave rank into their components + uint8_t m0 = (mrnk & 0x2) >> 1; + uint8_t m1 = (mrnk & 0x1); + + uint8_t s0 = (srnk & 0x4) >> 2; + uint8_t s1 = (srnk & 0x2) >> 1; + uint8_t s2 = (srnk & 0x1); + + // Split the column into its components + uint8_t c9 = (col & 0x40) >> 6; + uint8_t c8 = (col & 0x20) >> 5; + uint8_t c7 = (col & 0x10) >> 4; + uint8_t c6 = (col & 0x08) >> 3; + uint8_t c5 = (col & 0x04) >> 2; + uint8_t c4 = (col & 0x02) >> 1; + uint8_t c3 = (col & 0x01); + + // Split the bank and bank group into their components + // Note: B2 is not used for OCMB + uint8_t b0 = (bnk & 0x10) >> 4; + uint8_t b1 = (bnk & 0x08) >> 3; + + uint8_t bg0 = (bnk & 0x2) >> 1; + uint8_t bg1 = (bnk & 0x1); + + // Row bits 14:0 are always at CAPI addr position 30:16 + o_addr |= (r14_r0 << 16); + + // Check MC_ADDR_TRANS0 register for bit positions + SCAN_COMM_REGISTER_CLASS * reg = i_chip->getRegister( "MC_ADDR_TRANS" ); + o_rc = reg->Read(); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "Read failed on MC_ADDR_TRANS: i_chip=0x%08x", + i_chip->getHuid() ); + return o_rc; + } + + // If the DIMM select is valid, insert that bit + if ( twoDimmConfig ) + { + // DIMM bitmap: MC_ADDR_TRANS0[33:37] + bitPos = reg->GetBitFieldJustified( 33, 5 ); + __adjustCapiAddrBitPos( bitPos ); + o_addr |= (dslct << bitPos); + } + + // Insert any of the master rank bits that are valid + switch( mrnkBits ) + { + case 2: + // Master rank 0 bitmap: MC_ADDR_TRANS0[38:42] + bitPos = reg->GetBitFieldJustified( 38, 5 ); + __adjustCapiAddrBitPos( bitPos ); + o_addr |= (m0 << bitPos); + case 1: + // Master rank 1 bitmap: MC_ADDR_TRANS0[43:47] + bitPos = reg->GetBitFieldJustified( 43, 5 ); + __adjustCapiAddrBitPos( bitPos ); + o_addr |= (m1 << bitPos); + break; + } + + // Insert any extra row bits (17:15) that are valid + switch ( extraRowBits ) + { + case 3: + // Row 17 bitmap: MC_ADDR_TRANS0[49:53] + bitPos = reg->GetBitFieldJustified( 49, 5 ); + __adjustCapiAddrBitPos( bitPos ); + o_addr |= (r17 << bitPos); + case 2: + // Row 16 bitmap: MC_ADDR_TRANS0[54:58] + bitPos = reg->GetBitFieldJustified( 54, 5 ); + __adjustCapiAddrBitPos( bitPos ); + o_addr |= (r16 << bitPos); + case 1: + // Row 15 bitmap: MC_ADDR_TRANS0[59:63] + bitPos = reg->GetBitFieldJustified( 59, 5 ); + __adjustCapiAddrBitPos( bitPos ); + o_addr |= (r15 << bitPos); + break; + } + + // Check MC_ADDR_TRANS1 register for bit positions + reg = i_chip->getRegister( "MC_ADDR_TRANS1" ); + o_rc = reg->Read(); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "Read failed on MC_ADDR_TRANS1: i_chip=0x%08x", + i_chip->getHuid() ); + return o_rc; + } + + // Insert any of the slave rank bits that are valid + switch ( srnkBits ) + { + case 3: + // Slave rank 0 bitmap: MC_ADDR_TRANS1[3:7] + bitPos = reg->GetBitFieldJustified( 3, 5 ); + __adjustCapiAddrBitPos( bitPos ); + o_addr |= (s0 << bitPos); + case 2: + // Slave rank 1 bitmap: MC_ADDR_TRANS1[11:15] + bitPos = reg->GetBitFieldJustified( 11, 5 ); + __adjustCapiAddrBitPos( bitPos ); + o_addr |= (s1 << bitPos); + case 1: + // Slave rank 2 bitmap: MC_ADDR_TRANS1[19:23] + bitPos = reg->GetBitFieldJustified( 19, 5 ); + __adjustCapiAddrBitPos( bitPos ); + o_addr |= (s2 << bitPos); + break; + } + + // Column 3 bitmap: MC_ADDR_TRANS1[30:34] + bitPos = reg->GetBitFieldJustified( 30, 5 ); + __adjustCapiAddrBitPos( bitPos ); + o_addr |= (c3 << bitPos); + + // Column 4 bitmap: MC_ADDR_TRANS1[35:39] + bitPos = reg->GetBitFieldJustified( 35, 5 ); + __adjustCapiAddrBitPos( bitPos ); + o_addr |= (c4 << bitPos); + + // Column 5 bitmap: MC_ADDR_TRANS1[43:47] + bitPos = reg->GetBitFieldJustified( 43, 5 ); + __adjustCapiAddrBitPos( bitPos ); + o_addr |= (c5 << bitPos); + + // Column 6 bitmap: MC_ADDR_TRANS1[51:55] + bitPos = reg->GetBitFieldJustified( 51, 5 ); + __adjustCapiAddrBitPos( bitPos ); + o_addr |= (c6 << bitPos); + + // Column 7 bitmap: MC_ADDR_TRANS1[59:63] + bitPos = reg->GetBitFieldJustified( 59, 5 ); + __adjustCapiAddrBitPos( bitPos ); + o_addr |= (c7 << bitPos); + + // Check MC_ADDR_TRANS2 register for bit positions + reg = i_chip->getRegister( "MC_ADDR_TRANS2" ); + o_rc = reg->Read(); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "Read failed on MC_ADDR_TRANS2: i_chip=0x%08x", + i_chip->getHuid() ); + return o_rc; + } + + // Column 8 bitmap: MC_ADDR_TRANS2[3:7] + bitPos = reg->GetBitFieldJustified( 3, 5 ); + __adjustCapiAddrBitPos( bitPos ); + o_addr |= (c8 << bitPos); + + // Column 9 bitmap: MC_ADDR_TRANS2[11:15] + bitPos = reg->GetBitFieldJustified( 11, 5 ); + __adjustCapiAddrBitPos( bitPos ); + o_addr |= (c9 << bitPos); + + // Bank 0 bitmap: MC_ADDR_TRANS2[19:23] + bitPos = reg->GetBitFieldJustified( 19, 5 ); + __adjustCapiAddrBitPos( bitPos ); + o_addr |= (b0 << bitPos ); + + // Bank 1 bitmap: MC_ADDR_TRANS2[27:31] + bitPos = reg->GetBitFieldJustified( 27, 5 ); + __adjustCapiAddrBitPos( bitPos ); + o_addr |= (b1 << bitPos); + + // Bank 2 bitmap: MC_ADDR_TRANS2[35:39] + // Note: Bank2 not used for OCMB + + // Bank group 0 bitmap: MC_ADDR_TRANS2[43:47] + bitPos = reg->GetBitFieldJustified( 43, 5 ); + __adjustCapiAddrBitPos( bitPos ); + o_addr |= (bg0 << bitPos); + + // Bank group 1 bitmap: MC_ADDR_TRANS2[51:55] + bitPos = reg->GetBitFieldJustified( 51, 5 ); + __adjustCapiAddrBitPos( bitPos ); + o_addr |= (bg1 << bitPos); + + return o_rc; + + #undef PRDF_FUNC +} + template <> int32_t __getPortAddr<TYPE_MBA>( ExtensibleChip * i_chip, MemAddr i_addr, uint64_t & o_addr ) @@ -566,12 +826,12 @@ int32_t __getPortAddr<TYPE_MBA>( ExtensibleChip * i_chip, MemAddr i_addr, //------------------------------------------------------------------------------ template<TYPE T> -void __getGrpPrms( ExtensibleChip * i_chip, uint8_t o_portPos, +void __getGrpPrms( ExtensibleChip * i_chip, uint8_t & o_portPos, SCAN_COMM_REGISTER_CLASS * &o_mcfgp, SCAN_COMM_REGISTER_CLASS * &o_mcfgpm ); template<> -void __getGrpPrms<TYPE_MCA>( ExtensibleChip * i_chip, uint8_t o_portPos, +void __getGrpPrms<TYPE_MCA>( ExtensibleChip * i_chip, uint8_t & o_portPos, SCAN_COMM_REGISTER_CLASS * &o_mcfgp, SCAN_COMM_REGISTER_CLASS * &o_mcfgpm ) { @@ -585,7 +845,33 @@ void __getGrpPrms<TYPE_MCA>( ExtensibleChip * i_chip, uint8_t o_portPos, } template<> -void __getGrpPrms<TYPE_MBA>( ExtensibleChip * i_chip, uint8_t o_portPos, +void __getGrpPrms<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, uint8_t & o_portPos, + SCAN_COMM_REGISTER_CLASS * &o_mcfgp, + SCAN_COMM_REGISTER_CLASS * &o_mcfgpm ) +{ + // Get the connected parent MI; + ExtensibleChip * mcc = getConnectedParent( i_chip, TYPE_MCC ); + ExtensibleChip * mi = getConnectedParent( mcc, TYPE_MI ); + + // TODO RTC 210072 - support for multiple ports + o_portPos = 0; + + // Get the position of the MCC relative to the MI (0:1) + uint8_t chnlPos = mcc->getPos() % MAX_MCC_PER_MI; + + char mcfgpName[64]; + sprintf( mcfgpName, "MCFGP%d", chnlPos ); + + char mcfgpmName[64]; + sprintf( mcfgpmName, "MCFGPM%d", chnlPos ); + + o_mcfgp = mi->getRegister( mcfgpName ); + o_mcfgpm = mi->getRegister( mcfgpmName ); + +} + +template<> +void __getGrpPrms<TYPE_MBA>( ExtensibleChip * i_chip, uint8_t & o_portPos, SCAN_COMM_REGISTER_CLASS * &o_mcfgp, SCAN_COMM_REGISTER_CLASS * &o_mcfgpm ) { @@ -686,12 +972,67 @@ uint32_t __getGrpInfo( ExtensibleChip * i_chip, uint64_t & o_grpChnls, #undef PRDF_FUNC } +template<> +uint32_t __getGrpInfo<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + uint64_t & o_grpChnls, + uint64_t & o_grpId, uint64_t & o_grpSize, + uint64_t & o_grpBar ) +{ + #define PRDF_FUNC "[MemDealloc::__getGrpInfo] " + + uint32_t o_rc = SUCCESS; + + do + { + // Get portPos and MCFGP/M registers + uint8_t portPos = 0xFF; + SCAN_COMM_REGISTER_CLASS * mcfgp = nullptr; + SCAN_COMM_REGISTER_CLASS * mcfgpm = nullptr; + __getGrpPrms<TYPE_OCMB_CHIP>( i_chip, portPos, mcfgp, mcfgpm ); + + o_rc = mcfgp->Read(); if ( SUCCESS != o_rc ) break; + + // Get the number of channels in this group: MCFGP[40:42] + uint8_t mcGrpCnfg = mcfgp->GetBitFieldJustified( 40, 3 ); + switch ( mcGrpCnfg ) + { + case 0: o_grpChnls = 8; break; // 8MCS + case 1: o_grpChnls = 1; break; // 1MCS + case 2: o_grpChnls = 2; break; // 2MCS + case 3: o_grpChnls = 3; break; // 3MCS + case 4: o_grpChnls = 4; break; // 4MCS + case 5: o_grpChnls = 6; break; // 6MCS + default: + PRDF_ERR( PRDF_FUNC "Invalid MC channels per group value: 0x%x " + "on 0x%08x", mcGrpCnfg, i_chip->getHuid() ); + o_rc = FAIL; + } + if ( SUCCESS != o_rc ) break; + + // Get the group ID and group size. + o_grpId = mcfgp->GetBitFieldJustified( 43, 3 ); // MCFGP[43:45] + o_grpSize = mcfgp->GetBitFieldJustified( 25, 15 ); // MCFGP[25:39] + + // TODO RTC 210072 - support for multiple ports, see generic handling + + // Get the base address (BAR). + // Channel 0 is always from the MCFGP. + o_grpBar = mcfgp->GetBitFieldJustified(1, 24); // MCFGP[1:24] + + } while (0); + + return o_rc; + + #undef PRDF_FUNC +} + //------------------------------------------------------------------------------ -uint32_t __insertGrpId( uint64_t & io_addr, uint64_t i_grpChnls, - uint64_t i_grpId ) +template <TYPE T> +uint32_t __insertGrpId( ExtensibleChip * i_chip, uint64_t & io_addr, + uint64_t i_grpChnls, uint64_t i_grpId ) { - #define PRDF_FUNC "[MemDealloc::__insertGrpId] " + #define PRDF_FUNC "[MemDealloc::__insertGrpId<T>] " uint32_t o_rc = SUCCESS; @@ -742,6 +1083,108 @@ uint32_t __insertGrpId( uint64_t & io_addr, uint64_t i_grpChnls, #undef PRDF_FUNC } +template<> +uint32_t __insertGrpId<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + uint64_t & io_addr, uint64_t i_grpChnls, + uint64_t i_grpId ) +{ + #define PRDF_FUNC "[MemDealloc::__insertGrpId<TYPE_OCMB_CHIP>] " + + uint32_t o_rc = SUCCESS; + + uint64_t upper33 = io_addr & 0xFFFFFFFF80ull; + uint64_t lower7 = io_addr & 0x000000007full; + + bool subChanAEnable = false; + bool subChanBEnable = false; + bool bothSubChansEnabled = false; + + ExtensibleChip * mcc = getConnectedParent( i_chip, TYPE_MCC ); + + // Check both subchannels whether we can get the connected OCMB to + // determine whether they are enabled. + // Check for subchannel A + ExtensibleChip * subchanA = getConnectedChild( mcc, TYPE_OCMB_CHIP, 0 ); + if ( nullptr != subchanA ) subChanAEnable = true; + + // Check for subchannel B + ExtensibleChip * subchanB = getConnectedChild( mcc, TYPE_OCMB_CHIP, 1 ); + if ( nullptr != subchanB ) subChanBEnable = true; + + // Check if both subchannels were enabled + if ( subChanAEnable && subChanBEnable ) bothSubChansEnabled = true; + + // If both subchannels are enabled, bit 56 of the address will contain the + // subchannel select bit. + if ( bothSubChansEnabled ) + { + uint8_t ocmbChnl = i_chip->getPos() % MAX_OCMB_PER_MCC; // 0:1 + uint8_t bitInsert = 0; + + switch ( i_grpChnls ) + { + case 1: // insert 1 bit for subchannel select + case 3: + case 6: + bitInsert = ( ocmbChnl & 0x1 ); + io_addr = (upper33 << 1) | (bitInsert << 7) | lower7; + break; + + case 2: // insert 1 bit for subchannel select and 1 bit for grpId + bitInsert = ( ((i_grpId & 0x1) << 1) | (ocmbChnl & 0x1) ); + io_addr = (upper33 << 2) | (bitInsert << 7) | lower7; + break; + + case 4: // insert 1 bit for subchannel select and 2 bits for grpId + bitInsert = ( ((i_grpId & 0x3) << 1) | (ocmbChnl & 0x1) ); + io_addr = (upper33 << 3) | (bitInsert << 7) | lower7; + break; + + case 8: // insert 1 bit for subchannel select and 3 bits for grpId + bitInsert = ( ((i_grpId & 0x7) << 1) | (ocmbChnl & 0x1) ); + io_addr = (upper33 << 4) | (bitInsert << 7) | lower7; + break; + + default: + PRDF_ERR( PRDF_FUNC "Invalid MC channels per group value %d", + i_grpChnls ); + o_rc = FAIL; + } + } + else + { + switch ( i_grpChnls ) + { + case 1: // no shifting + case 3: + case 6: + break; + + case 2: // insert 1 bit + io_addr = (upper33 << 1) | ((i_grpId & 0x1) << 7) | lower7; + break; + + case 4: // insert 2 bits + io_addr = (upper33 << 2) | ((i_grpId & 0x3) << 7) | lower7; + break; + + case 8: // insert 3 bits + io_addr = (upper33 << 3) | ((i_grpId & 0x7) << 7) | lower7; + break; + + default: + PRDF_ERR( PRDF_FUNC "Invalid MC channels per group value %d", + i_grpChnls ); + o_rc = FAIL; + } + } + + return o_rc; + + #undef PRDF_FUNC + +} + //------------------------------------------------------------------------------ // The hardware uses a mod3 hashing algorithm to calculate which memory channel @@ -849,7 +1292,7 @@ void __addBar( uint64_t & io_addr, uint64_t i_grpBar ) template<TYPE T> uint32_t getSystemAddr( ExtensibleChip * i_chip, MemAddr i_addr, - uint64_t & o_addr ) + uint64_t & o_addr ) { #define PRDF_FUNC "[MemDealloc::getSystemAddr] " @@ -867,7 +1310,7 @@ uint32_t getSystemAddr( ExtensibleChip * i_chip, MemAddr i_addr, if ( SUCCESS != o_rc ) break; // Insert the group ID. - o_rc = __insertGrpId( o_addr, grpChnls, grpId ); + o_rc = __insertGrpId<T>( i_chip, o_addr, grpChnls, grpId ); if ( SUCCESS != o_rc ) break; // Notes on 3 and 6 channel per group configs: @@ -915,8 +1358,8 @@ uint32_t getSystemAddrRange( ExtensibleChip * i_chip, if ( SUCCESS != o_rc ) break; // Insert the group ID. - o_rc = __insertGrpId( o_saddr, grpChnls, grpId ); - o_rc |= __insertGrpId( o_eaddr, grpChnls, grpId ); + o_rc = __insertGrpId<T>( i_chip, o_saddr, grpChnls, grpId ); + o_rc |= __insertGrpId<T>( i_chip, o_eaddr, grpChnls, grpId ); if ( SUCCESS != o_rc ) break; // Notes on 3 and 6 channel per group configs: @@ -975,6 +1418,7 @@ int32_t page( ExtensibleChip * i_chip, MemAddr i_addr ) } template int32_t page<TYPE_MCA>( ExtensibleChip * i_chip, MemAddr i_addr ); template int32_t page<TYPE_MBA>( ExtensibleChip * i_chip, MemAddr i_addr ); +template int32_t page<TYPE_OCMB_CHIP>(ExtensibleChip * i_chip, MemAddr i_addr); //------------------------------------------------------------------------------ @@ -1025,6 +1469,7 @@ int32_t rank( ExtensibleChip * i_chip, MemRank i_rank ) } template int32_t rank<TYPE_MCA>( ExtensibleChip * i_chip, MemRank i_rank ); template int32_t rank<TYPE_MBA>( ExtensibleChip * i_chip, MemRank i_rank ); +template int32_t rank<TYPE_OCMB_CHIP>(ExtensibleChip * i_chip, MemRank i_rank); //------------------------------------------------------------------------------ @@ -1074,6 +1519,7 @@ int32_t port( ExtensibleChip * i_chip ) } template int32_t port<TYPE_MCA>( ExtensibleChip * i_chip ); template int32_t port<TYPE_MBA>( ExtensibleChip * i_chip ); +template int32_t port<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip ); //------------------------------------------------------------------------------ @@ -1236,6 +1682,22 @@ int32_t dimmList( TargetHandleList & i_dimmList ) sendPredDeallocRequest( ssAddr, seAddr ); PRDF_TRAC( PRDF_FUNC "Predictive dealloc for start addr: 0x%016llx " "end addr: 0x%016llx", ssAddr, seAddr ); + + #ifdef CONFIG_NVDIMM + // If the DIMM is an NVDIMM, send a message to PHYP that a save/restore + // may work. + if ( isNVDIMM(*it) ) + { + uint32_t l_rc = PlatServices::nvdimmNotifyProtChange( *it, + NVDIMM::NVDIMM_RISKY_HW_ERROR ); + if ( SUCCESS != l_rc ) + { + PRDF_TRAC( PRDF_FUNC "nvdimmNotifyProtChange(0x%08x) " + "failed.", getHuid(*it) ); + continue; + } + } + #endif } return o_rc; @@ -1278,6 +1740,14 @@ int32_t dimmList( TargetHandleList & i_dimmList ) break; } + // Third, check for OCMBs. + list = getConnected( dimmTrgt, TYPE_OCMB_CHIP ); + if ( !list.empty() ) + { + o_rc = dimmList<TYPE_OCMB_CHIP>( i_dimmList ); + break; + } + // If we get here we did not find a supported target. PRDF_ERR( PRDF_FUNC "Unsupported connected parent to dimm 0x%08x", getHuid(dimmTrgt) ); diff --git a/src/usr/diag/prdf/plat/mem/prdfMemIplCeStats.C b/src/usr/diag/prdf/plat/mem/prdfMemIplCeStats.C index 869aa92e8..b257d0874 100755 --- a/src/usr/diag/prdf/plat/mem/prdfMemIplCeStats.C +++ b/src/usr/diag/prdf/plat/mem/prdfMemIplCeStats.C @@ -83,8 +83,8 @@ void MemIplCeStats<TYPE_MCA>::banAnalysis( uint8_t i_dimmSlct, //------------------------------------------------------------------------------ template<> -void MemIplCeStats<TYPE_MEM_PORT>::banAnalysis( uint8_t i_dimmSlct, - uint8_t i_portSlct ) +void MemIplCeStats<TYPE_OCMB_CHIP>::banAnalysis( uint8_t i_dimmSlct, + uint8_t i_portSlct ) { PRDF_ASSERT( i_dimmSlct < MAX_DIMM_PER_PORT ); PRDF_ASSERT( 0 == i_portSlct ); @@ -117,9 +117,9 @@ void MemIplCeStats<TYPE_MCA>::banAnalysis( uint8_t i_dimmSlct ) //------------------------------------------------------------------------------ template<> -void MemIplCeStats<TYPE_MEM_PORT>::banAnalysis( uint8_t i_dimmSlct ) +void MemIplCeStats<TYPE_OCMB_CHIP>::banAnalysis( uint8_t i_dimmSlct ) { - // Only one DIMM per DIMM select on MEM_PORT. + // Only one DIMM per DIMM select on OCMB_CHIP. banAnalysis( i_dimmSlct, 0 ); } @@ -481,6 +481,6 @@ void MemIplCeStats<T>::addMruAndCommitErrl( const MemoryMru & i_memmru, // need these templates to avoid linker errors template class MemIplCeStats<TYPE_MCA>; template class MemIplCeStats<TYPE_MBA>; -template class MemIplCeStats<TYPE_MEM_PORT>; +template class MemIplCeStats<TYPE_OCMB_CHIP>; } // end namespace PRDF diff --git a/src/usr/diag/prdf/plat/mem/prdfMemScrubUtils.C b/src/usr/diag/prdf/plat/mem/prdfMemScrubUtils.C index 5351b842a..bececfa21 100644 --- a/src/usr/diag/prdf/plat/mem/prdfMemScrubUtils.C +++ b/src/usr/diag/prdf/plat/mem/prdfMemScrubUtils.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2019 */ +/* Contributors Listed Below - COPYRIGHT 2016,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -106,17 +106,6 @@ uint32_t clearCmdCompleteAttn<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip ) } template<> -uint32_t clearCmdCompleteAttn<TYPE_MEM_PORT>( ExtensibleChip * i_chip ) -{ - PRDF_ASSERT( nullptr != i_chip ); - PRDF_ASSERT( TYPE_MEM_PORT == i_chip->getType() ); - - ExtensibleChip * ocmbChip = getConnectedParent( i_chip, TYPE_OCMB_CHIP ); - - return clearCmdCompleteAttn<TYPE_OCMB_CHIP>( ocmbChip ); -} - -template<> uint32_t clearCmdCompleteAttn<TYPE_MBA>( ExtensibleChip * i_chip ) { // Clear MBASPA[0,8]. @@ -194,17 +183,6 @@ uint32_t clearEccCounters<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip ) } template<> -uint32_t clearEccCounters<TYPE_MEM_PORT>( ExtensibleChip * i_chip ) -{ - PRDF_ASSERT( nullptr != i_chip ); - PRDF_ASSERT( TYPE_MEM_PORT == i_chip->getType() ); - - ExtensibleChip * ocmbChip = getConnectedParent( i_chip, TYPE_OCMB_CHIP ); - - return clearEccCounters<TYPE_OCMB_CHIP>( ocmbChip ); -} - -template<> uint32_t clearEccCounters<TYPE_MBA>( ExtensibleChip * i_chip ) { PRDF_ASSERT( nullptr != i_chip ); @@ -306,17 +284,6 @@ uint32_t clearEccFirs<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip ) } template<> -uint32_t clearEccFirs<TYPE_MEM_PORT>( ExtensibleChip * i_chip ) -{ - PRDF_ASSERT( nullptr != i_chip ); - PRDF_ASSERT( TYPE_MEM_PORT == i_chip->getType() ); - - ExtensibleChip * ocmbChip = getConnectedParent( i_chip, TYPE_OCMB_CHIP ); - - return clearEccFirs<TYPE_OCMB_CHIP>( ocmbChip ); -} - -template<> uint32_t clearEccFirs<TYPE_MBA>( ExtensibleChip * i_chip ) { uint32_t o_rc = SUCCESS; @@ -409,22 +376,20 @@ uint32_t checkEccFirs<TYPE_MCA>( ExtensibleChip * i_chip, //------------------------------------------------------------------------------ template<> -uint32_t checkEccFirs<TYPE_MEM_PORT>( ExtensibleChip * i_chip, - uint32_t & o_eccAttns ) +uint32_t checkEccFirs<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + uint32_t & o_eccAttns ) { - #define PRDF_FUNC "[checkEccFirs<TYPE_MEM_PORT>] " + #define PRDF_FUNC "[checkEccFirs<TYPE_OCMB_CHIP>] " uint32_t o_rc = SUCCESS; o_eccAttns = MAINT_NO_ERROR; PRDF_ASSERT( nullptr != i_chip ); - PRDF_ASSERT( TYPE_MEM_PORT == i_chip->getType() ); - - ExtensibleChip * ocmbChip = getConnectedParent( i_chip, TYPE_OCMB_CHIP ); + PRDF_ASSERT( TYPE_OCMB_CHIP == i_chip->getType() ); - SCAN_COMM_REGISTER_CLASS * rdffir = ocmbChip->getRegister( "RDFFIR" ); - SCAN_COMM_REGISTER_CLASS * mcbistfir = ocmbChip->getRegister( "MCBISTFIR" ); + SCAN_COMM_REGISTER_CLASS * rdffir = i_chip->getRegister( "RDFFIR" ); + SCAN_COMM_REGISTER_CLASS * mcbistfir = i_chip->getRegister( "MCBISTFIR" ); do { @@ -453,7 +418,7 @@ uint32_t checkEccFirs<TYPE_MEM_PORT>( ExtensibleChip * i_chip, if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "Read() failed on MCBISTFIR: mcbChip=0x%08x", - ocmbChip->getHuid() ); + i_chip->getHuid() ); break; } @@ -733,11 +698,11 @@ uint32_t setBgScrubThresholds<TYPE_MBA>( ExtensibleChip * i_chip, //------------------------------------------------------------------------------ -template<> -uint32_t didCmdStopOnLastAddr<TYPE_MBA>( ExtensibleChip * i_chip, - AddrRangeType i_rangeType, - bool & o_stoppedOnLastAddr, - bool i_rowRepair ) +template<TARGETING::TYPE T> +uint32_t didCmdStopOnLastAddr( ExtensibleChip * i_chip, + AddrRangeType i_rangeType, + bool & o_stoppedOnLastAddr, + bool i_rowRepair ) { #define PRDF_FUNC "[didCmdStopOnLastAddr] " @@ -749,7 +714,7 @@ uint32_t didCmdStopOnLastAddr<TYPE_MBA>( ExtensibleChip * i_chip, { // Get the current address. MemAddr curAddr; - o_rc = getMemMaintAddr<TYPE_MBA>( i_chip, curAddr ); + o_rc = getMemMaintAddr<T>( i_chip, curAddr ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "getMemMaintAddr(0x%08x) failed", @@ -759,7 +724,7 @@ uint32_t didCmdStopOnLastAddr<TYPE_MBA>( ExtensibleChip * i_chip, // Get the end address of the current rank. MemAddr junk, endAddr; - o_rc = getMemAddrRange<TYPE_MBA>( i_chip, curAddr.getRank(), junk, + o_rc = getMemAddrRange<T>( i_chip, curAddr.getRank(), junk, endAddr, i_rangeType ); if ( SUCCESS != o_rc ) { @@ -784,7 +749,16 @@ uint32_t didCmdStopOnLastAddr<TYPE_MBA>( ExtensibleChip * i_chip, #undef PRDF_FUNC } - +template +uint32_t didCmdStopOnLastAddr<TYPE_MBA>( ExtensibleChip * i_chip, + AddrRangeType i_rangeType, + bool & o_stoppedOnLastAddr, + bool i_rowRepair ); +template +uint32_t didCmdStopOnLastAddr<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + AddrRangeType i_rangeType, + bool & o_stoppedOnLastAddr, + bool i_rowRepair ); //------------------------------------------------------------------------------ } // end namespace PRDF diff --git a/src/usr/diag/prdf/plat/mem/prdfMemTdCtlr.C b/src/usr/diag/prdf/plat/mem/prdfMemTdCtlr.C index f86110458..5d310c51b 100644 --- a/src/usr/diag/prdf/plat/mem/prdfMemTdCtlr.C +++ b/src/usr/diag/prdf/plat/mem/prdfMemTdCtlr.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -248,8 +248,8 @@ uint32_t __analyzeCmdComplete<TYPE_MCBIST>( ExtensibleChip * i_chip, do { // Get all ports in which the command was run. - std::vector<ExtensibleChip *> portList; - o_rc = getMcbistMaintPort( i_chip, portList ); + ExtensibleChipList portList; + o_rc = getMcbistMaintPort<TYPE_MCBIST>( i_chip, portList ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "getMcbistMaintPort(0x%08x) failed", @@ -291,6 +291,43 @@ uint32_t __analyzeCmdComplete<TYPE_MCBIST>( ExtensibleChip * i_chip, } template<> +uint32_t __analyzeCmdComplete<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + TdRankListEntry & o_stoppedRank, + const MemAddr & i_addr, + bool & o_errorsFound, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + #define PRDF_FUNC "[__analyzeCmdComplete] " + + uint32_t o_rc = SUCCESS; + + o_errorsFound = false; + + do + { + // Update iv_stoppedRank. + o_stoppedRank = __getStopRank<TYPE_OCMB_CHIP>( i_chip, i_addr ); + + // Check the OCMB for ECC errors. + bool errorsFound; + o_rc = __checkEcc<TYPE_OCMB_CHIP>( i_chip, i_addr, errorsFound, io_sc ); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "__checkEcc<TYPE_OCMB_CHIP>(0x%08x) failed", + i_chip->getHuid() ); + break; + } + + if ( errorsFound ) o_errorsFound = true; + + } while (0); + + return o_rc; + + #undef PRDF_FUNC +} + +template<> uint32_t __analyzeCmdComplete<TYPE_MBA>( ExtensibleChip * i_chip, TdRankListEntry & o_stoppedRank, const MemAddr & i_addr, @@ -346,7 +383,7 @@ uint32_t MemTdCtlr<T>::analyzeCmdComplete( bool & o_errorsFound, // of in defaultStep() because a TD procedure could have been run // before defaultStep() and it is possible that canResumeBgScrub() // could give as a false positive in that case. - o_rc = canResumeBgScrub( iv_resumeBgScrub ); + o_rc = canResumeBgScrub( iv_resumeBgScrub, io_sc ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "canResumeBgScrub(0x%08x) failed", @@ -397,9 +434,15 @@ void MemTdCtlr<T>::collectStateCaptureData( STEP_CODE_DATA_STRUCT & io_sc, // Get the version to use. uint8_t version = TD_CTLR_DATA::VERSION_1; + bool isNimbus = false; if ( MODEL_NIMBUS == getChipModel(getMasterProc()) ) { version = TD_CTLR_DATA::VERSION_2; + isNimbus = true; + } + else if ( MODEL_AXONE == getChipModel(getMasterProc()) ) + { + version = TD_CTLR_DATA::VERSION_2; } // Get the IPL state. @@ -443,6 +486,11 @@ void MemTdCtlr<T>::collectStateCaptureData( STEP_CODE_DATA_STRUCT & io_sc, if ( TD_CTLR_DATA::VERSION_2 == version ) { curPort = iv_curProcedure->getChip()->getPos() % MAX_MCA_PER_MCBIST; + if ( !isNimbus ) + { + TargetHandle_t portTrgt = iv_curProcedure->getChip()->getTrgt(); + curPort = portTrgt->getAttr<ATTR_REL_POS>(); + } } } @@ -475,6 +523,11 @@ void MemTdCtlr<T>::collectStateCaptureData( STEP_CODE_DATA_STRUCT & io_sc, if ( TD_CTLR_DATA::VERSION_2 == version ) { itPort = queue[n]->getChip()->getPos() % MAX_MCA_PER_MCBIST; + if ( !isNimbus ) + { + TargetHandle_t portTrgt = queue[n]->getChip()->getTrgt(); + itPort = portTrgt->getAttr<ATTR_REL_POS>(); + } } bsb.setFieldJustify( pos, 3, itMrnk ); pos+=3; @@ -502,6 +555,7 @@ void MemTdCtlr<T>::collectStateCaptureData( STEP_CODE_DATA_STRUCT & io_sc, // Avoid linker errors with the template. template class MemTdCtlr<TYPE_MCBIST>; template class MemTdCtlr<TYPE_MBA>; +template class MemTdCtlr<TYPE_OCMB_CHIP>; //------------------------------------------------------------------------------ diff --git a/src/usr/diag/prdf/plat/mem/prdfMemTdCtlr.H b/src/usr/diag/prdf/plat/mem/prdfMemTdCtlr.H index 332109b48..da969e2c1 100644 --- a/src/usr/diag/prdf/plat/mem/prdfMemTdCtlr.H +++ b/src/usr/diag/prdf/plat/mem/prdfMemTdCtlr.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -54,14 +54,14 @@ class MemTdCtlr /** * @brief Constructor * - * This contructor will only be called in the MCBIST or MBA data bundle, - * which already checks for a valid type. + * This contructor will only be called in the MCBIST, MBA, or OCMB data + * bundle, which already checks for a valid type. * * Need to initialize iv_stoppedRank to a valid entry in iv_rankList. Use * the last entry in the list so that the 'next' rank is the first entry * in the list. * - * @param i_chip An MCBIST or MBA chip. + * @param i_chip An MCBIST, MBA, or OCMB chip. */ explicit MemTdCtlr( ExtensibleChip * i_chip ) : iv_chip( i_chip ), iv_rankList( i_chip ), @@ -122,7 +122,7 @@ class MemTdCtlr /** * @brief Bans TPS on the given rank. Any attempts to add a TPS procedure * to the queue for this rank will be ignored. - * @param i_chip MCA or MBA chip. + * @param i_chip MCA, MBA, or OCMB chip. * @param i_rank The target slave rank. */ void banTps( ExtensibleChip * i_chip, const MemRank & i_rank ) @@ -294,15 +294,17 @@ class MemTdCtlr /** * @param o_canResume True, if background scrubbing can be resumed. False, * if a new background scrub command must be started. + * @param io_sc The step code data struct. * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. */ - uint32_t canResumeBgScrub( bool & o_canResume ); + uint32_t canResumeBgScrub( bool & o_canResume, + STEP_CODE_DATA_STRUCT & io_sc ); #endif private: // instance variables - /** An MCBIST or MBA chip associated with this TD controller. */ + /** An MCBIST, MBA, or OCMB chip associated with this TD controller. */ ExtensibleChip * const iv_chip; /** The TD queue that contains all of the pending TD procedures. */ diff --git a/src/usr/diag/prdf/plat/mem/prdfMemTdCtlr_ipl.C b/src/usr/diag/prdf/plat/mem/prdfMemTdCtlr_ipl.C index ea04d2964..401a48042 100644 --- a/src/usr/diag/prdf/plat/mem/prdfMemTdCtlr_ipl.C +++ b/src/usr/diag/prdf/plat/mem/prdfMemTdCtlr_ipl.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -160,6 +160,14 @@ bool __mnfgCeCheck<TYPE_MCA>( uint32_t i_eccAttns ) } template<> inline +bool __mnfgCeCheck<TYPE_OCMB_CHIP>( uint32_t i_eccAttns ) +{ + return ( ( 0 != (i_eccAttns & MAINT_HARD_NCE_ETE) ) && + ( (0 != (i_eccAttns & MAINT_NCE)) || + (0 != (i_eccAttns & MAINT_TCE)) ) ); +} + +template<> inline bool __mnfgCeCheck<TYPE_MBA>( uint32_t i_eccAttns ) { return ( 0 != (i_eccAttns & MAINT_HARD_NCE_ETE) ); @@ -251,12 +259,18 @@ template uint32_t __checkEcc<TYPE_MBA>( ExtensibleChip * i_chip, const MemAddr & i_addr, bool & o_errorsFound, STEP_CODE_DATA_STRUCT & io_sc ); +template +uint32_t __checkEcc<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + const MemAddr & i_addr, + bool & o_errorsFound, + STEP_CODE_DATA_STRUCT & io_sc ); //------------------------------------------------------------------------------ // Avoid linker errors with the template. template class MemTdCtlr<TYPE_MCBIST>; template class MemTdCtlr<TYPE_MBA>; +template class MemTdCtlr<TYPE_OCMB_CHIP>; //------------------------------------------------------------------------------ diff --git a/src/usr/diag/prdf/plat/mem/prdfMemTdCtlr_rt.C b/src/usr/diag/prdf/plat/mem/prdfMemTdCtlr_rt.C index d52ef2d1d..5565e217f 100644 --- a/src/usr/diag/prdf/plat/mem/prdfMemTdCtlr_rt.C +++ b/src/usr/diag/prdf/plat/mem/prdfMemTdCtlr_rt.C @@ -107,6 +107,36 @@ void __recaptureRegs<TYPE_MCBIST>( STEP_CODE_DATA_STRUCT & io_sc, } template<> +void __recaptureRegs<TYPE_OCMB_CHIP>( STEP_CODE_DATA_STRUCT & io_sc, + ExtensibleChip * i_chip ) +{ + #define PRDF_FUNC "[__recaptureRegs<TYPE_OCMB_CHIP>] " + + RegDataCache & cache = RegDataCache::getCachedRegisters(); + CaptureData & cd = io_sc.service_data->GetCaptureData(); + + // refresh and recapture the ocmb registers + const char * ocmbRegs[] = + { + "MCBISTFIR", "RDFFIR", "MBSEC0", "MBSEC1", "OCMB_MBSSYMEC0", + "OCMB_MBSSYMEC1", "OCMB_MBSSYMEC2", "OCMB_MBSSYMEC3", + "OCMB_MBSSYMEC4", "OCMB_MBSSYMEC5", "OCMB_MBSSYMEC6", + "OCMB_MBSSYMEC7", "OCMB_MBSSYMEC8", "MBSMSEC", "MCBMCAT", + }; + + for ( uint32_t i = 0; i < sizeof(ocmbRegs)/sizeof(char*); i++ ) + { + SCAN_COMM_REGISTER_CLASS * reg = + i_chip->getRegister( ocmbRegs[i] ); + cache.flush( i_chip, reg ); + } + + i_chip->CaptureErrorData( cd, Util::hashString("MaintCmdRegs_ocmb") ); + + #undef PRDF_FUNC +} + +template<> void __recaptureRegs<TYPE_MBA>( STEP_CODE_DATA_STRUCT & io_sc, ExtensibleChip * i_chip ) { @@ -283,7 +313,7 @@ uint32_t MemTdCtlr<T>::defaultStep( STEP_CODE_DATA_STRUCT & io_sc ) PRDF_TRAC( PRDF_FUNC "Calling resumeBgScrub<T>(0x%08x)", iv_chip->getHuid() ); - o_rc = resumeBgScrub<T>( iv_chip ); + o_rc = resumeBgScrub<T>( iv_chip, io_sc ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "resumeBgScrub<T>(0x%08x) failed", @@ -358,9 +388,48 @@ uint32_t __handleNceEte( ExtensibleChip * i_chip, uint32_t count = symData.size(); switch ( T ) { - case TYPE_MCA: PRDF_ASSERT( 1 <= count && count <= 2 ); break; - case TYPE_MBA: PRDF_ASSERT( 1 == count ); break; - default: PRDF_ASSERT( false ); + case TYPE_MCA: + { + PRDF_ASSERT( 1 <= count && count <= 2 ); + // Increment the CE counter and store the rank we're on, + // reset the UE and CE counts if we have stopped on a new rank. + ExtensibleChip * mcb = getConnectedParent(i_chip, TYPE_MCBIST); + McbistDataBundle * mcbdb = getMcbistDataBundle(mcb); + if ( mcbdb->iv_ceUeRank != i_addr.getRank() ) + { + mcbdb->iv_ceStopCounter.reset(); + mcbdb->iv_ueStopCounter.reset(); + } + mcbdb->iv_ceStopCounter.inc( io_sc ); + mcbdb->iv_ceUeRank = i_addr.getRank(); + + break; + } + case TYPE_MBA: + { + PRDF_ASSERT( 1 == count ); + break; + } + case TYPE_OCMB_CHIP: + { + PRDF_ASSERT( 1 <= count && count <= 2 ); + // Increment the UE counter and store the rank we're on, + // reset the UE and CE counts if we have stopped on a new rank. + OcmbDataBundle * ocmbdb = getOcmbDataBundle(i_chip); + if ( ocmbdb->iv_ceUeRank != i_addr.getRank() ) + { + ocmbdb->iv_ceStopCounter.reset(); + ocmbdb->iv_ueStopCounter.reset(); + } + ocmbdb->iv_ceStopCounter.inc( io_sc ); + ocmbdb->iv_ceUeRank = i_addr.getRank(); + + break; + } + default: + { + PRDF_ASSERT( false ); + } } for ( auto & d : symData ) @@ -408,6 +477,14 @@ uint32_t __handleSoftInterCeEte<TYPE_MCA>( ExtensibleChip * i_chip, } template<> +uint32_t __handleSoftInterCeEte<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + const MemAddr & i_addr, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + return __handleNceEte<TYPE_OCMB_CHIP>( i_chip, i_addr, io_sc ); +} + +template<> uint32_t __handleSoftInterCeEte<TYPE_MBA>( ExtensibleChip * i_chip, const MemAddr & i_addr, STEP_CODE_DATA_STRUCT & io_sc ) @@ -480,6 +557,52 @@ uint32_t __handleRceEte<TYPE_MCA>( ExtensibleChip * i_chip, } template<> +uint32_t __handleRceEte<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + const MemRank & i_rank, + bool & o_errorsFound, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + #define PRDF_FUNC "[__handleRceEte] " + + uint32_t o_rc = SUCCESS; + + // Should only get this attention in MNFG mode. + PRDF_ASSERT( mfgMode() ); + + do + { + // The RCE ETE attention could be from IUE, IMPE, or IRCD. Need to check + // RDFFIR[37] to determine if there was at least one IUE. + SCAN_COMM_REGISTER_CLASS * fir = i_chip->getRegister( "RDFFIR" ); + o_rc = fir->Read(); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "Read() failed on RDFFIR: i_chip=0x%08x", + i_chip->getHuid() ); + break; + } + if ( !fir->IsBitSet(37) ) break; // nothing else to do + + // Handle the IUE. + o_errorsFound = true; + io_sc.service_data->AddSignatureList( i_chip->getTrgt(), + PRDFSIG_MaintIUE ); + o_rc = MemEcc::handleMemIue<TYPE_OCMB_CHIP>( i_chip, i_rank, io_sc ); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "analyzeMaintIue(0x%08x) failed", + i_chip->getHuid() ); + break; + } + + } while (0); + + return o_rc; + + #undef PRDF_FUNC +} + +template<> uint32_t __handleRceEte<TYPE_MBA>( ExtensibleChip * i_chip, const MemRank & i_rank, bool & o_errorsFound, STEP_CODE_DATA_STRUCT & io_sc ) @@ -698,6 +821,11 @@ template uint32_t __checkEcc<TYPE_MBA>( ExtensibleChip * i_chip, const MemAddr & i_addr, bool & o_errorsFound, STEP_CODE_DATA_STRUCT & io_sc ); +template +uint32_t __checkEcc<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + const MemAddr & i_addr, + bool & o_errorsFound, + STEP_CODE_DATA_STRUCT & io_sc ); //------------------------------------------------------------------------------ @@ -786,6 +914,76 @@ uint32_t MemTdCtlr<TYPE_MCBIST>::unmaskEccAttns() //------------------------------------------------------------------------------ template<> +uint32_t MemTdCtlr<TYPE_OCMB_CHIP>::maskEccAttns() +{ + #define PRDF_FUNC "[MemTdCtlr<TYPE_OCMB_CHIP>::maskEccAttns] " + + uint32_t o_rc = SUCCESS; + + SCAN_COMM_REGISTER_CLASS * mask = iv_chip->getRegister( "RDFFIR_MASK_OR" ); + + mask->clearAllBits(); + mask->SetBit(8); // Mainline read NCE + mask->SetBit(9); // Mainline read TCE + + o_rc = mask->Write(); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "Write() failed on RDFFIR_MASK_OR" ); + } + + return o_rc; + + #undef PRDF_FUNC +} + +//------------------------------------------------------------------------------ + +template<> +uint32_t MemTdCtlr<TYPE_OCMB_CHIP>::unmaskEccAttns() +{ + #define PRDF_FUNC "[MemTdCtlr<TYPE_OCMB_CHIP>::unmaskEccAttns] " + + uint32_t o_rc = SUCCESS; + + // Memory CEs were masked at the beginning of the TD procedure, so + // clear and unmask them. Also, it is possible that memory UEs have + // thresholded so clear and unmask them as well. + + SCAN_COMM_REGISTER_CLASS * fir = iv_chip->getRegister( "RDFFIR_AND" ); + SCAN_COMM_REGISTER_CLASS * mask = iv_chip->getRegister( "RDFFIR_MASK_AND" ); + + fir->setAllBits(); mask->setAllBits(); + + // Do not unmask NCE and TCE attentions if they have been permanently + // masked due to certain TPS conditions. + if ( !(getOcmbDataBundle(iv_chip)->iv_maskMainlineNceTce) ) + { + fir->ClearBit(8); mask->ClearBit(8); // Mainline read NCE + fir->ClearBit(9); mask->ClearBit(9); // Mainline read TCE + } + fir->ClearBit(14); mask->ClearBit(14); // Mainline read UE + + o_rc = fir->Write(); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "Write() failed on RDFFIR_AND" ); + } + + o_rc = mask->Write(); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "Write() failed on RDFFIR_MASK_AND" ); + } + + return o_rc; + + #undef PRDF_FUNC +} + +//------------------------------------------------------------------------------ + +template<> uint32_t MemTdCtlr<TYPE_MBA>::maskEccAttns() { #define PRDF_FUNC "[MemTdCtlr<TYPE_MBA>::maskEccAttns] " @@ -887,6 +1085,13 @@ SCAN_COMM_REGISTER_CLASS * __getEccFirAnd<TYPE_MCA>( ExtensibleChip * i_chip ) } template<> +SCAN_COMM_REGISTER_CLASS * __getEccFirAnd<TYPE_OCMB_CHIP>( + ExtensibleChip * i_chip ) +{ + return i_chip->getRegister( "RDFFIR_AND" ); +} + +template<> SCAN_COMM_REGISTER_CLASS * __getEccFirAnd<TYPE_MBA>( ExtensibleChip * i_chip ) { ExtensibleChip * membChip = getConnectedParent( i_chip, TYPE_MEMBUF ); @@ -1009,6 +1214,45 @@ uint32_t MemTdCtlr<TYPE_MCBIST>::initialize() } template<> +uint32_t MemTdCtlr<TYPE_OCMB_CHIP>::initialize() +{ + #define PRDF_FUNC "[MemTdCtlr<TYPE_OCMB_CHIP>::initialize] " + + uint32_t o_rc = SUCCESS; + + do + { + if ( iv_initialized ) break; // nothing to do + + // Unmask the fetch attentions just in case there were masked during a + // TD procedure prior to a reset/reload. + o_rc = unmaskEccAttns(); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "unmaskEccAttns() failed" ); + break; + } + + // Find all unverified chip marks. + o_rc = __findChipMarks<TYPE_OCMB_CHIP>( iv_rankList ); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "__findChipMarks() failed on 0x%08x", + iv_chip->getHuid() ); + break; + } + + // At this point, the TD controller is initialized. + iv_initialized = true; + + } while (0); + + return o_rc; + + #undef PRDF_FUNC +} + +template<> uint32_t MemTdCtlr<TYPE_MBA>::initialize() { #define PRDF_FUNC "[MemTdCtlr<TYPE_MBA>::initialize] " @@ -1162,6 +1406,118 @@ uint32_t MemTdCtlr<TYPE_MCBIST>::handleRrFo() //------------------------------------------------------------------------------ template<> +uint32_t MemTdCtlr<TYPE_OCMB_CHIP>::handleRrFo() +{ + #define PRDF_FUNC "[MemTdCtlr<TYPE_OCMB_CHIP>::handleRrFo] " + + uint32_t o_rc = SUCCESS; + + do + { + // Check if maintenance command complete attention is set. + SCAN_COMM_REGISTER_CLASS * mcbistfir = + iv_chip->getRegister("MCBISTFIR"); + o_rc = mcbistfir->Read(); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "Read() failed on MCBISTFIR"); + break; + } + + // If there is a command complete attention, nothing to do, break out. + if ( mcbistfir->IsBitSet(10) ) + break; + + + // Check if a command is not running. + // If bit 0 of MCB_CNTLSTAT is on, a mcbist run is in progress. + SCAN_COMM_REGISTER_CLASS * mcb_cntlstat = + iv_chip->getRegister("MCB_CNTLSTAT"); + o_rc = mcb_cntlstat->Read(); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "Read() failed on MCB_CNTLSTAT" ); + break; + } + + // If a command is not running, set command complete attn, break. + if ( !mcb_cntlstat->IsBitSet(0) ) + { + SCAN_COMM_REGISTER_CLASS * mcbistfir_or = + iv_chip->getRegister("MCBISTFIR_OR"); + mcbistfir_or->SetBit( 10 ); + + mcbistfir_or->Write(); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "Write() failed on MCBISTFIR_OR" ); + } + break; + } + + // Check if there are unverified chip marks. + std::vector<TdRankListEntry> vectorList = iv_rankList.getList(); + + for ( auto & entry : vectorList ) + { + ExtensibleChip * ocmbChip = entry.getChip(); + MemRank rank = entry.getRank(); + + // Get the chip mark + MemMark chipMark; + o_rc = MarkStore::readChipMark<TYPE_OCMB_CHIP>( ocmbChip, rank, + chipMark ); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "readChipMark<TYPE_OCMB_CHIP>(0x%08x,%d) " + "failed", ocmbChip->getHuid(), rank.getMaster() ); + break; + } + + if ( !chipMark.isValid() ) continue; // no chip mark present + + // Get the DQ Bitmap data. + MemDqBitmap dqBitmap; + + o_rc = getBadDqBitmap( ocmbChip->getTrgt(), rank, dqBitmap ); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "getBadDqBitmap(0x%08x, %d)", + ocmbChip->getHuid(), rank.getMaster() ); + break; + } + + // Check if the chip mark is verified or not. + bool cmVerified = false; + o_rc = dqBitmap.isChipMark( chipMark.getSymbol(), cmVerified ); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "dqBitmap.isChipMark failed." ); + break; + } + + // If there are any unverified chip marks, stop the command, break. + if ( !cmVerified ) + { + o_rc = stopBgScrub<TYPE_OCMB_CHIP>( iv_chip ); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "stopBgScrub<TYPE_OCMB_CHIP>(0x%08x) " + "failed", iv_chip->getHuid() ); + } + break; + } + } + + } while (0); + + return o_rc; + #undef PRDF_FUNC +} + +//------------------------------------------------------------------------------ + +template<> uint32_t MemTdCtlr<TYPE_MBA>::handleRrFo() { #define PRDF_FUNC "[MemTdCtlr<TYPE_MBA>::handleRrFo] " @@ -1289,7 +1645,8 @@ uint32_t MemTdCtlr<TYPE_MBA>::handleRrFo() //------------------------------------------------------------------------------ template<> -uint32_t MemTdCtlr<TYPE_MCBIST>::canResumeBgScrub( bool & o_canResume ) +uint32_t MemTdCtlr<TYPE_MCBIST>::canResumeBgScrub( bool & o_canResume, + STEP_CODE_DATA_STRUCT & io_sc ) { #define PRDF_FUNC "[MemTdCtlr<TYPE_MCBIST>::canResumeBgScrub] " @@ -1305,21 +1662,124 @@ uint32_t MemTdCtlr<TYPE_MCBIST>::canResumeBgScrub( bool & o_canResume ) // can use the stop conditions, which should be unique for background scrub, // to determine if it has been configured. - SCAN_COMM_REGISTER_CLASS * reg = iv_chip->getRegister( "MBSTR" ); - o_rc = reg->Read(); - if ( SUCCESS != o_rc ) + do { - PRDF_ERR( PRDF_FUNC "Read() failed on MBSTR: iv_chip=0x%08x", - iv_chip->getHuid() ); - } - else if ( 0xf != reg->GetBitFieldJustified(0,4) && // NCE int TH - 0xf != reg->GetBitFieldJustified(4,4) && // NCE soft TH - 0xf != reg->GetBitFieldJustified(8,4) && // NCE hard TH - reg->IsBitSet(34) && // pause on MPE - reg->IsBitSet(35) ) // pause on UE + SCAN_COMM_REGISTER_CLASS * reg = iv_chip->getRegister( "MBSTR" ); + o_rc = reg->Read(); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "Read() failed on MBSTR: iv_chip=0x%08x", + iv_chip->getHuid() ); + break; + } + // Note: The stop conditions for background scrubbing can now be + // variable depending on whether we have hit threshold for the number + // of UEs or CEs that we have stopped on on a rank. + + // If we haven't hit CE or UE threshold, check the CE stop conditions + if ( !getMcbistDataBundle(iv_chip)->iv_ceStopCounter.thReached(io_sc) && + !getMcbistDataBundle(iv_chip)->iv_ueStopCounter.thReached(io_sc) ) + { + // If the stop conditions aren't set, just break out. + if ( !(0xf != reg->GetBitFieldJustified(0,4) && // NCE int TH + 0xf != reg->GetBitFieldJustified(4,4) && // NCE soft TH + 0xf != reg->GetBitFieldJustified(8,4)) ) // NCE hard TH + { + break; + } + + } + + // If we haven't hit UE threshold yet, check the UE stop condition + if ( !getMcbistDataBundle(iv_chip)->iv_ueStopCounter.thReached(io_sc) ) + { + // If the stop condition isn't set, just break out + if ( !reg->IsBitSet(35) ) // pause on UE + { + break; + } + } + + // Need to check the stop on mpe stop condition regardless of whether + // we hit the UE or CE threshold. + if ( reg->IsBitSet(34) ) // pause on MPE + { + // If we reach here, all the stop conditions are set for background + // scrub, so we can resume. + o_canResume = true; + } + }while(0); + + return o_rc; + + #undef PRDF_FUNC +} + +template<> +uint32_t MemTdCtlr<TYPE_OCMB_CHIP>::canResumeBgScrub( bool & o_canResume, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + #define PRDF_FUNC "[MemTdCtlr<TYPE_OCMB_CHIP>::canResumeBgScrub] " + + uint32_t o_rc = SUCCESS; + + o_canResume = false; + + // It is possible that we were running a TD procedure and the PRD service + // was reset. Therefore, we must check if background scrubbing was actually + // configured. There really is not a good way of doing this. A scrub command + // is a scrub command the only difference is the speed. Unfortunately, that + // speed can change depending on how the hardware team tunes it. For now, we + // can use the stop conditions, which should be unique for background scrub, + // to determine if it has been configured. + + do { - o_canResume = true; - } + SCAN_COMM_REGISTER_CLASS * reg = iv_chip->getRegister( "MBSTR" ); + o_rc = reg->Read(); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "Read() failed on MBSTR: iv_chip=0x%08x", + iv_chip->getHuid() ); + break; + } + // Note: The stop conditions for background scrubbing can now be + // variable depending on whether we have hit threshold for the number + // of UEs or CEs that we have stopped on on a rank. + + // If we haven't hit CE or UE threshold, check the CE stop conditions + if ( !getOcmbDataBundle(iv_chip)->iv_ceStopCounter.thReached(io_sc) && + !getOcmbDataBundle(iv_chip)->iv_ueStopCounter.thReached(io_sc) ) + { + // If the stop conditions aren't set, just break out. + if ( !(0xf != reg->GetBitFieldJustified(0,4) && // NCE int TH + 0xf != reg->GetBitFieldJustified(4,4) && // NCE soft TH + 0xf != reg->GetBitFieldJustified(8,4)) ) // NCE hard TH + { + break; + } + + } + + // If we haven't hit UE threshold yet, check the UE stop condition + if ( !getOcmbDataBundle(iv_chip)->iv_ueStopCounter.thReached(io_sc) ) + { + // If the stop condition isn't set, just break out + if ( !reg->IsBitSet(35) ) // pause on UE + { + break; + } + } + + // Need to check the stop on mpe stop condition regardless of whether + // we hit the UE or CE threshold. + if ( reg->IsBitSet(34) ) // pause on MPE + { + // If we reach here, all the stop conditions are set for background + // scrub, so we can resume. + o_canResume = true; + } + }while(0); return o_rc; @@ -1327,7 +1787,8 @@ uint32_t MemTdCtlr<TYPE_MCBIST>::canResumeBgScrub( bool & o_canResume ) } template<> -uint32_t MemTdCtlr<TYPE_MBA>::canResumeBgScrub( bool & o_canResume ) +uint32_t MemTdCtlr<TYPE_MBA>::canResumeBgScrub( bool & o_canResume, + STEP_CODE_DATA_STRUCT & io_sc ) { #define PRDF_FUNC "[MemTdCtlr<TYPE_MBA>::canResumeBgScrub] " @@ -1365,6 +1826,7 @@ uint32_t MemTdCtlr<TYPE_MBA>::canResumeBgScrub( bool & o_canResume ) // Avoid linker errors with the template. template class MemTdCtlr<TYPE_MCBIST>; template class MemTdCtlr<TYPE_MBA>; +template class MemTdCtlr<TYPE_OCMB_CHIP>; //------------------------------------------------------------------------------ diff --git a/src/usr/diag/prdf/plat/mem/prdfMemTdRankList.H b/src/usr/diag/prdf/plat/mem/prdfMemTdRankList.H index e61389ea2..2e833a12a 100644 --- a/src/usr/diag/prdf/plat/mem/prdfMemTdRankList.H +++ b/src/usr/diag/prdf/plat/mem/prdfMemTdRankList.H @@ -80,8 +80,8 @@ class TdRankListEntry private: - ExtensibleChip * iv_chip = nullptr; ///< MCA, MBA, or MEM_PORT chip. - MemRank iv_rank = MemRank(0); ///< Any rank on the MCA/MBA/MEM_PORT + ExtensibleChip * iv_chip = nullptr; ///< MCA, MBA, or OCMB chip. + MemRank iv_rank = MemRank(0); ///< Any rank on the MCA/MBA/OCMB }; /** @@ -95,7 +95,7 @@ class TdRankList /** * @brief Constructor. - * @param MCBIST or MBA chip. + * @param MCBIST, OCMB, or MBA chip. */ explicit TdRankList( ExtensibleChip * i_chip ); @@ -191,17 +191,13 @@ inline TdRankList<TARGETING::TYPE_OCMB_CHIP>::TdRankList( PRDF_ASSERT( TYPE_OCMB_CHIP == i_chip->getType() ); - ExtensibleChipList memPortChipList = getConnected( i_chip, TYPE_MEM_PORT ); - for ( auto & memPortChip : memPortChipList ) - { - std::vector<MemRank> rankList; - getSlaveRanks<TYPE_MEM_PORT>( memPortChip->getTrgt(), rankList ); - PRDF_ASSERT( !rankList.empty() ); // target configured with no ranks + std::vector<MemRank> rankList; + getSlaveRanks<TYPE_OCMB_CHIP>( i_chip->getTrgt(), rankList ); + PRDF_ASSERT( !rankList.empty() ); // target configured with no ranks - for ( auto & rank : rankList ) - { - iv_list.push_back( TdRankListEntry(memPortChip, rank) ); - } + for ( auto & rank : rankList ) + { + iv_list.push_back( TdRankListEntry(i_chip, rank) ); } } diff --git a/src/usr/diag/prdf/plat/mem/prdfMemTps_ipl.C b/src/usr/diag/prdf/plat/mem/prdfMemTps_ipl.C index de3e62e23..64eb74648 100644 --- a/src/usr/diag/prdf/plat/mem/prdfMemTps_ipl.C +++ b/src/usr/diag/prdf/plat/mem/prdfMemTps_ipl.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -36,6 +36,8 @@ #include <prdfP9McaExtraSig.H> #include <prdfPlatServices.H> +#include <hwp_wrappers.H> + using namespace TARGETING; namespace PRDF @@ -125,6 +127,12 @@ bool __iueCheck<TYPE_MCA>( uint32_t i_eccAttns ) } template<> inline +bool __iueCheck<TYPE_OCMB_CHIP>( uint32_t i_eccAttns ) +{ + return ( 0 != (i_eccAttns & MAINT_IUE) ); +} + +template<> inline bool __iueCheck<TYPE_MBA>( uint32_t i_eccAttns ) { // IUES are reported via RCE ETE on Centaur @@ -252,13 +260,15 @@ uint32_t TpsEvent<TYPE_MCA>::startCmd() uint32_t o_rc = SUCCESS; + #ifndef CONFIG_AXONE + // We don't need to set any stop-on-error conditions or thresholds for // soft/inter/hard CEs during Memory Diagnostics. The design is to let the // command continue to the end of the rank and we do diagnostics on the // CE counts found in the per-symbol counters. Therefore, all we need to do // is tell the hardware which CE types to count. - mss::mcbist::stop_conditions stopCond; + mss::mcbist::stop_conditions<mss::mc_type::NIMBUS> stopCond; switch ( iv_phase ) { @@ -284,6 +294,8 @@ uint32_t TpsEvent<TYPE_MCA>::startCmd() iv_chip->getHuid(), getKey() ); } + #endif + return o_rc; #undef PRDF_FUNC @@ -362,11 +374,66 @@ uint32_t TpsEvent<TYPE_MBA>::startCmd() #undef PRDF_FUNC } +//############################################################################## +// +// Specializations for OCMB +// +//############################################################################## + +template<> +uint32_t TpsEvent<TYPE_OCMB_CHIP>::startCmd() +{ + #define PRDF_FUNC "[TpsEvent::startCmd] " + + uint32_t o_rc = SUCCESS; + + #ifdef CONFIG_AXONE + + // We don't need to set any stop-on-error conditions or thresholds for + // soft/inter/hard CEs during Memory Diagnostics. The design is to let the + // command continue to the end of the rank and we do diagnostics on the + // CE counts found in the per-symbol counters. Therefore, all we need to do + // is tell the hardware which CE types to count. + + mss::mcbist::stop_conditions<mss::mc_type::EXPLORER> stopCond; + + switch ( iv_phase ) + { + case TD_PHASE_1: + // Set the per symbol counters to count only soft/inter CEs. + stopCond.set_nce_soft_symbol_count_enable( mss::ON); + stopCond.set_nce_inter_symbol_count_enable(mss::ON); + break; + + case TD_PHASE_2: + // Set the per symbol counters to count only hard CEs. + stopCond.set_nce_hard_symbol_count_enable(mss::ON); + break; + + default: PRDF_ASSERT( false ); // invalid phase + } + + // Start the time based scrub procedure on this slave rank. + o_rc = startTdScrub<TYPE_OCMB_CHIP>(iv_chip, iv_rank, SLAVE_RANK, stopCond); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "startTdScrub(0x%08x,0x%2x) failed", + iv_chip->getHuid(), getKey() ); + } + + #endif + + return o_rc; + + #undef PRDF_FUNC +} + //------------------------------------------------------------------------------ // Avoid linker errors with the template. template class TpsEvent<TYPE_MCA>; template class TpsEvent<TYPE_MBA>; +template class TpsEvent<TYPE_OCMB_CHIP>; //------------------------------------------------------------------------------ diff --git a/src/usr/diag/prdf/plat/mem/prdfMemTps_rt.C b/src/usr/diag/prdf/plat/mem/prdfMemTps_rt.C index 187b9b28d..8b3b220c6 100644 --- a/src/usr/diag/prdf/plat/mem/prdfMemTps_rt.C +++ b/src/usr/diag/prdf/plat/mem/prdfMemTps_rt.C @@ -37,6 +37,8 @@ #include <prdfP9McaExtraSig.H> #include <prdfTargetServices.H> +#include <hwp_wrappers.H> + using namespace TARGETING; namespace PRDF @@ -54,6 +56,13 @@ static const char *mcbCeStatReg[CE_REGS_PER_PORT] = "MCB_MBSSYMEC6", "MCB_MBSSYMEC7", "MCB_MBSSYMEC8" }; +static const char *ocmbCeStatReg[CE_REGS_PER_PORT] = + { + "OCMB_MBSSYMEC0", "OCMB_MBSSYMEC1", "OCMB_MBSSYMEC2", + "OCMB_MBSSYMEC3", "OCMB_MBSSYMEC4", "OCMB_MBSSYMEC5", + "OCMB_MBSSYMEC6", "OCMB_MBSSYMEC7", "OCMB_MBSSYMEC8" + }; + //------------------------------------------------------------------------------ template <TARGETING::TYPE T> @@ -66,6 +75,13 @@ TpsFalseAlarm * __getTpsFalseAlarmCounter<TYPE_MCA>( ExtensibleChip * i_chip ) } template<> +TpsFalseAlarm * __getTpsFalseAlarmCounter<TYPE_OCMB_CHIP>( + ExtensibleChip * i_chip ) +{ + return getOcmbDataBundle(i_chip)->getTpsFalseAlarmCounter(); +} + +template<> TpsFalseAlarm * __getTpsFalseAlarmCounter<TYPE_MBA>( ExtensibleChip * i_chip ) { return getMbaDataBundle(i_chip)->getTpsFalseAlarmCounter(); @@ -73,6 +89,23 @@ TpsFalseAlarm * __getTpsFalseAlarmCounter<TYPE_MBA>( ExtensibleChip * i_chip ) //------------------------------------------------------------------------------ +template <TARGETING::TYPE T> +void __maskMainlineNceTces( ExtensibleChip * i_chip ); + +template<> +void __maskMainlineNceTces<TYPE_MCA>( ExtensibleChip * i_chip ) +{ + getMcaDataBundle(i_chip)->iv_maskMainlineNceTce = true; +} + +template<> +void __maskMainlineNceTces<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip ) +{ + getOcmbDataBundle(i_chip)->iv_maskMainlineNceTce = true; +} + +//------------------------------------------------------------------------------ + template<TARGETING::TYPE T> void __getNextPhase( ExtensibleChip * i_chip, const MemRank & i_rank, STEP_CODE_DATA_STRUCT & io_sc, @@ -98,12 +131,7 @@ void __getNextPhase( ExtensibleChip * i_chip, const MemRank & i_rank, //------------------------------------------------------------------------------ template<TARGETING::TYPE T> -bool __badDqCount( MemUtils::MaintSymbols i_nibbleStats, - CeCount & io_badDqCount ); - -template<> -bool __badDqCount<TYPE_MCA>( MemUtils::MaintSymbols i_nibbleStats, - CeCount & io_badDqCount ) +bool __badDqCount(MemUtils::MaintSymbols i_nibbleStats, CeCount & io_badDqCount) { bool badDqFound = false; @@ -142,11 +170,7 @@ bool __badDqCount<TYPE_MCA>( MemUtils::MaintSymbols i_nibbleStats, template<TARGETING::TYPE T> bool __badChipCount( MemUtils::MaintSymbols i_nibbleStats, - CeCount & io_badChipCount ); - -template<> -bool __badChipCount<TYPE_MCA>( MemUtils::MaintSymbols i_nibbleStats, - CeCount & io_badChipCount ) + CeCount & io_badChipCount ) { bool badChipFound = false; uint8_t nonZeroCount = 0; @@ -191,11 +215,7 @@ bool __badChipCount<TYPE_MCA>( MemUtils::MaintSymbols i_nibbleStats, template<TARGETING::TYPE T> void __sumAboveOneCount( MemUtils::MaintSymbols i_nibbleStats, - CeCount & io_sumAboveOneCount ); - -template<> -void __sumAboveOneCount<TYPE_MCA>( MemUtils::MaintSymbols i_nibbleStats, - CeCount & io_sumAboveOneCount ) + CeCount & io_sumAboveOneCount ) { uint8_t sum = 0; MemUtils::MaintSymbols symList; @@ -226,11 +246,7 @@ void __sumAboveOneCount<TYPE_MCA>( MemUtils::MaintSymbols i_nibbleStats, template<TARGETING::TYPE T> void __singleSymbolCount( MemUtils::MaintSymbols i_nibbleStats, - CeCount & io_singleSymCount ); - -template<> -void __singleSymbolCount<TYPE_MCA>( MemUtils::MaintSymbols i_nibbleStats, - CeCount & io_singleSymCount ) + CeCount & io_singleSymCount ) { uint8_t count = 0; bool multNonZeroSyms = false; @@ -315,12 +331,12 @@ uint32_t __updateVpdSumAboveOne( CeCount i_sumAboveOneCount, //------------------------------------------------------------------------------ -template <> -uint32_t TpsEvent<TYPE_MCA>::analyzeEccErrors( const uint32_t & i_eccAttns, - STEP_CODE_DATA_STRUCT & io_sc, - bool & o_done ) +template <TARGETING::TYPE T> +uint32_t TpsEvent<T>::analyzeEccErrors( const uint32_t & i_eccAttns, + STEP_CODE_DATA_STRUCT & io_sc, + bool & o_done ) { - #define PRDF_FUNC "[TpsEvent<TYPE_MCA>::analyzeEccErrors] " + #define PRDF_FUNC "[TpsEvent<T>::analyzeEccErrors] " uint32_t o_rc = SUCCESS; @@ -338,7 +354,7 @@ uint32_t TpsEvent<TYPE_MCA>::analyzeEccErrors( const uint32_t & i_eccAttns, // At this point we don't actually have an address for the UE. The // best we can do is get the address in which the command stopped. MemAddr addr; - o_rc = getMemMaintAddr<TYPE_MCA>( iv_chip, addr ); + o_rc = getMemMaintAddr<T>( iv_chip, addr ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "getMemMaintAddr(0x%08x) failed", @@ -346,8 +362,8 @@ uint32_t TpsEvent<TYPE_MCA>::analyzeEccErrors( const uint32_t & i_eccAttns, break; } - o_rc = MemEcc::handleMemUe<TYPE_MCA>( iv_chip, addr, - UE_TABLE::SCRUB_UE, io_sc ); + o_rc = MemEcc::handleMemUe<T>( iv_chip, addr, + UE_TABLE::SCRUB_UE, io_sc ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "handleMemUe(0x%08x,0x%02x) failed", @@ -357,7 +373,7 @@ uint32_t TpsEvent<TYPE_MCA>::analyzeEccErrors( const uint32_t & i_eccAttns, // Because of the UE, any further TPS requests will likely have no // effect. So ban all subsequent requests. - MemDbUtils::banTps<TYPE_MCA>( iv_chip, addr.getRank() ); + MemDbUtils::banTps<T>( iv_chip, addr.getRank() ); // Abort this procedure because additional repairs will likely // not help (also avoids complication of having UE and MPE at @@ -371,7 +387,7 @@ uint32_t TpsEvent<TYPE_MCA>::analyzeEccErrors( const uint32_t & i_eccAttns, io_sc.service_data->setSignature( iv_chip->getHuid(), PRDFSIG_MaintIUE ); - o_rc = MemEcc::handleMemIue<TYPE_MCA>( iv_chip, iv_rank, io_sc ); + o_rc = MemEcc::handleMemIue<T>( iv_chip, iv_rank, io_sc ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "handleMemIue(0x%08x,0x%02x) failed", @@ -397,8 +413,8 @@ uint32_t TpsEvent<TYPE_MCA>::analyzeEccErrors( const uint32_t & i_eccAttns, io_sc.service_data->setSignature( iv_chip->getHuid(), PRDFSIG_MaintMPE ); - o_rc = MemEcc::handleMpe<TYPE_MCA>( iv_chip, iv_rank, - UE_TABLE::SCRUB_MPE, io_sc ); + o_rc = MemEcc::handleMpe<T>( iv_chip, iv_rank, + UE_TABLE::SCRUB_MPE, io_sc ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "handleMpe<T>(0x%08x, 0x%02x) failed", @@ -419,36 +435,51 @@ uint32_t TpsEvent<TYPE_MCA>::analyzeEccErrors( const uint32_t & i_eccAttns, } +template +uint32_t TpsEvent<TYPE_MCA>::analyzeEccErrors( const uint32_t & i_eccAttns, + STEP_CODE_DATA_STRUCT & io_sc, + bool & o_done ); +template +uint32_t TpsEvent<TYPE_OCMB_CHIP>::analyzeEccErrors(const uint32_t & i_eccAttns, + STEP_CODE_DATA_STRUCT & io_sc, + bool & o_done); + //------------------------------------------------------------------------------ -template<> -uint32_t TpsEvent<TYPE_MCA>::handleFalseAlarm( STEP_CODE_DATA_STRUCT & io_sc ) +template<TARGETING::TYPE T> +uint32_t TpsEvent<T>::handleFalseAlarm( STEP_CODE_DATA_STRUCT & io_sc ) { io_sc.service_data->setSignature( iv_chip->getHuid(), PRDFSIG_TpsFalseAlarm ); // Increase false alarm counter and check threshold. - if ( __getTpsFalseAlarmCounter<TYPE_MCA>(iv_chip)->inc( iv_rank, io_sc) ) + if ( __getTpsFalseAlarmCounter<T>(iv_chip)->inc( iv_rank, io_sc) ) { io_sc.service_data->setSignature( iv_chip->getHuid(), PRDFSIG_TpsFalseAlarmTH ); // Permanently mask mainline NCEs and TCEs - getMcaDataBundle(iv_chip)->iv_maskMainlineNceTce = true; + __maskMainlineNceTces<T>( iv_chip ); } return SUCCESS; } +template +uint32_t TpsEvent<TYPE_MCA>::handleFalseAlarm( STEP_CODE_DATA_STRUCT & io_sc ); +template +uint32_t TpsEvent<TYPE_OCMB_CHIP>::handleFalseAlarm( + STEP_CODE_DATA_STRUCT & io_sc ); + //------------------------------------------------------------------------------ -template<> -uint32_t TpsEvent<TYPE_MCA>::analyzeCeSymbolCounts( CeCount i_badDqCount, +template<TARGETING::TYPE T> +uint32_t TpsEvent<T>::analyzeCeSymbolCounts( CeCount i_badDqCount, CeCount i_badChipCount, CeCount i_sumAboveOneCount, CeCount i_singleSymCount, STEP_CODE_DATA_STRUCT & io_sc ) { - #define PRDF_FUNC "[TpsEvent<TYPE_MCA>::analyzeCeSymbolCounts] " + #define PRDF_FUNC "[TpsEvent<T>::analyzeCeSymbolCounts] " uint32_t o_rc = SUCCESS; @@ -457,33 +488,33 @@ uint32_t TpsEvent<TYPE_MCA>::analyzeCeSymbolCounts( CeCount i_badDqCount, bool tpsFalseAlarm = false; // Get the Bad DQ Bitmap. - TargetHandle_t mcaTrgt = iv_chip->getTrgt(); + TargetHandle_t trgt = iv_chip->getTrgt(); MemDqBitmap dqBitmap; - o_rc = getBadDqBitmap( mcaTrgt, iv_rank, dqBitmap ); + o_rc = getBadDqBitmap( trgt, iv_rank, dqBitmap ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "getBadDqBitmap(0x%08x, 0x%02x) failed", - getHuid(mcaTrgt), iv_rank.getKey() ); + getHuid(trgt), iv_rank.getKey() ); break; } // Get the symbol mark. MemMark symMark; - o_rc = MarkStore::readSymbolMark<TYPE_MCA>( iv_chip, iv_rank, symMark ); + o_rc = MarkStore::readSymbolMark<T>( iv_chip, iv_rank, symMark ); if ( SUCCESS != o_rc ) { - PRDF_ERR( PRDF_FUNC "readSymbolMark<TYPE_MCA>(0x%08x, 0x%02x) " + PRDF_ERR( PRDF_FUNC "readSymbolMark<T>(0x%08x, 0x%02x) " "failed", iv_chip->getHuid(), iv_rank.getKey() ); break; } // Get the chip mark. MemMark chipMark; - o_rc = MarkStore::readChipMark<TYPE_MCA>( iv_chip, iv_rank, chipMark ); + o_rc = MarkStore::readChipMark<T>( iv_chip, iv_rank, chipMark ); if ( SUCCESS != o_rc ) { - PRDF_ERR( PRDF_FUNC "readChipMark<TYPE_MCA>(0x%08x, 0x%02x) " + PRDF_ERR( PRDF_FUNC "readChipMark<T>(0x%08x, 0x%02x) " "failed", iv_chip->getHuid(), iv_rank.getKey() ); break; } @@ -512,9 +543,9 @@ uint32_t TpsEvent<TYPE_MCA>::analyzeCeSymbolCounts( CeCount i_badDqCount, // TCE. Both are still correctable after a symbol mark // is placed. // Place a symbol mark on this bad DQ. - MemMark newSymMark( mcaTrgt, iv_rank, + MemMark newSymMark( trgt, iv_rank, i_badDqCount.symList[0].symbol ); - o_rc = MarkStore::writeSymbolMark<TYPE_MCA>( iv_chip, + o_rc = MarkStore::writeSymbolMark<T>( iv_chip, iv_rank, newSymMark ); if ( SUCCESS != o_rc ) { @@ -552,7 +583,7 @@ uint32_t TpsEvent<TYPE_MCA>::analyzeCeSymbolCounts( CeCount i_badDqCount, io_sc.service_data->setServiceCall(); // Permanently mask mainline NCEs and TCEs. - getMcaDataBundle(iv_chip)->iv_maskMainlineNceTce = true; + __maskMainlineNceTces<T>( iv_chip ); } } else @@ -566,7 +597,7 @@ uint32_t TpsEvent<TYPE_MCA>::analyzeCeSymbolCounts( CeCount i_badDqCount, else if ( 2 == i_badDqCount.count && 0 == i_badChipCount.count ) { // Permanently mask mainline NCEs and TCEs. - getMcaDataBundle(iv_chip)->iv_maskMainlineNceTce = true; + __maskMainlineNceTces<T>( iv_chip ); // If the symbol mark is available. if ( !symMark.isValid() ) @@ -587,9 +618,9 @@ uint32_t TpsEvent<TYPE_MCA>::analyzeCeSymbolCounts( CeCount i_badDqCount, highSym = sym; } - MemMark newSymMark( mcaTrgt, iv_rank, + MemMark newSymMark( trgt, iv_rank, highSym.symbol ); - o_rc = MarkStore::writeSymbolMark<TYPE_MCA>( iv_chip, + o_rc = MarkStore::writeSymbolMark<T>( iv_chip, iv_rank, newSymMark ); if ( SUCCESS != o_rc ) { @@ -669,10 +700,10 @@ uint32_t TpsEvent<TYPE_MCA>::analyzeCeSymbolCounts( CeCount i_badDqCount, // This means we have only one more potential bad DQ, which // is still correctable after a chip mark is placed. // Place a chip mark on this bad chip. - MemMark newChipMark( mcaTrgt, iv_rank, + MemMark newChipMark( trgt, iv_rank, i_badChipCount.symList[0].symbol ); - o_rc = MarkStore::writeChipMark<TYPE_MCA>( iv_chip, iv_rank, - newChipMark ); + o_rc = MarkStore::writeChipMark<T>( iv_chip, iv_rank, + newChipMark ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "writeChipMark(0x%08x,0x%02x) " @@ -708,7 +739,7 @@ uint32_t TpsEvent<TYPE_MCA>::analyzeCeSymbolCounts( CeCount i_badDqCount, io_sc.service_data->setServiceCall(); // Permanently mask mainline NCEs and TCEs - getMcaDataBundle(iv_chip)->iv_maskMainlineNceTce = true; + __maskMainlineNceTces<T>( iv_chip ); } } else @@ -731,7 +762,7 @@ uint32_t TpsEvent<TYPE_MCA>::analyzeCeSymbolCounts( CeCount i_badDqCount, io_sc.service_data->setServiceCall(); // Permanently mask mainline NCEs and TCEs - getMcaDataBundle(iv_chip)->iv_maskMainlineNceTce = true; + __maskMainlineNceTces<T>( iv_chip ); } // If the chip mark is available. if ( !chipMark.isValid() ) @@ -742,10 +773,10 @@ uint32_t TpsEvent<TYPE_MCA>::analyzeCeSymbolCounts( CeCount i_badDqCount, // This means we have no more potential bad DQ or bad chips // since we can't correct those after chip mark is placed. // Place a chip mark on the bad chip. - MemMark newChipMark( mcaTrgt, iv_rank, + MemMark newChipMark( trgt, iv_rank, i_badChipCount.symList[0].symbol ); - o_rc = MarkStore::writeChipMark<TYPE_MCA>( iv_chip, iv_rank, - newChipMark ); + o_rc = MarkStore::writeChipMark<T>( iv_chip, iv_rank, + newChipMark ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "writeChipMark(0x%08x,0x%02x) " @@ -763,8 +794,8 @@ uint32_t TpsEvent<TYPE_MCA>::analyzeCeSymbolCounts( CeCount i_badDqCount, // this chip mark, we need to clear the symbol mark now // instead of at the end of the function to make room // for the additional symbol mark. - o_rc = MarkStore::clearSymbolMark<TYPE_MCA>( iv_chip, - iv_rank ); + o_rc = MarkStore::clearSymbolMark<T>( iv_chip, + iv_rank ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "MarkStore::clearSymbolMark(" @@ -810,7 +841,7 @@ uint32_t TpsEvent<TYPE_MCA>::analyzeCeSymbolCounts( CeCount i_badDqCount, io_sc.service_data->setServiceCall(); // Permanently mask mainline NCEs and TCEs. - getMcaDataBundle(iv_chip)->iv_maskMainlineNceTce = true; + __maskMainlineNceTces<T>( iv_chip ); } } // If the symbol mark is available. @@ -822,9 +853,9 @@ uint32_t TpsEvent<TYPE_MCA>::analyzeCeSymbolCounts( CeCount i_badDqCount, // This means we have no more potential bad DQ or bad chips // since we can't correct those after symbol mark is placed. // Place a symbol mark on this bad DQ. - MemMark newSymMark( mcaTrgt, iv_rank, + MemMark newSymMark( trgt, iv_rank, i_badDqCount.symList[0].symbol ); - o_rc = MarkStore::writeSymbolMark<TYPE_MCA>( iv_chip, + o_rc = MarkStore::writeSymbolMark<T>( iv_chip, iv_rank, newSymMark ); if ( SUCCESS != o_rc ) { @@ -865,7 +896,7 @@ uint32_t TpsEvent<TYPE_MCA>::analyzeCeSymbolCounts( CeCount i_badDqCount, io_sc.service_data->setServiceCall(); // Permanently mask mainline NCEs and TCEs. - getMcaDataBundle(iv_chip)->iv_maskMainlineNceTce = true; + __maskMainlineNceTces<T>( iv_chip ); } } @@ -888,7 +919,7 @@ uint32_t TpsEvent<TYPE_MCA>::analyzeCeSymbolCounts( CeCount i_badDqCount, io_sc.service_data->setServiceCall(); // Permanently mask mainline NCEs and TCEs. - getMcaDataBundle(iv_chip)->iv_maskMainlineNceTce = true; + __maskMainlineNceTces<T>( iv_chip ); } // If analysis resulted in a false alarm. @@ -903,18 +934,18 @@ uint32_t TpsEvent<TYPE_MCA>::analyzeCeSymbolCounts( CeCount i_badDqCount, } // Write any updates to VPD. - o_rc = setBadDqBitmap( mcaTrgt, iv_rank, dqBitmap ); + o_rc = setBadDqBitmap( trgt, iv_rank, dqBitmap ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "setBadDqBitmap(0x%08x, 0x%02x) failed", - getHuid(mcaTrgt), iv_rank.getKey() ); + getHuid(trgt), iv_rank.getKey() ); break; } // We may have placed a chip mark so do any necessary cleanup. This must // be called after writing the bad DQ bitmap because the this function // will also write it if necessary. - o_rc = MarkStore::chipMarkCleanup<TYPE_MCA>( iv_chip, iv_rank, io_sc ); + o_rc = MarkStore::chipMarkCleanup<T>( iv_chip, iv_rank, io_sc ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "MarkStore::chipMarkCleanup(0x%08x,0x%02x) " @@ -929,6 +960,15 @@ uint32_t TpsEvent<TYPE_MCA>::analyzeCeSymbolCounts( CeCount i_badDqCount, #undef PRDF_FUNC } +template +uint32_t TpsEvent<TYPE_MCA>::analyzeCeSymbolCounts( CeCount i_badDqCount, + CeCount i_badChipCount, CeCount i_sumAboveOneCount, + CeCount i_singleSymCount, STEP_CODE_DATA_STRUCT & io_sc ); +template +uint32_t TpsEvent<TYPE_OCMB_CHIP>::analyzeCeSymbolCounts( CeCount i_badDqCount, + CeCount i_badChipCount, CeCount i_sumAboveOneCount, + CeCount i_singleSymCount, STEP_CODE_DATA_STRUCT & io_sc ); + //------------------------------------------------------------------------------ template<> @@ -1031,11 +1071,110 @@ uint32_t TpsEvent<TYPE_MCA>::getSymbolCeCounts( CeCount & io_badDqCount, //------------------------------------------------------------------------------ -template <> -uint32_t TpsEvent<TYPE_MCA>::analyzeCeStats( STEP_CODE_DATA_STRUCT & io_sc, - bool & o_done ) +template<> +uint32_t TpsEvent<TYPE_OCMB_CHIP>::getSymbolCeCounts( CeCount & io_badDqCount, + CeCount & io_badChipCount, CeCount & io_sumAboveOneCount, + CeCount & io_singleSymCount, STEP_CODE_DATA_STRUCT & io_sc ) +{ + #define PRDF_FUNC "[TpsEvent<TYPE_OCMB_CHIP>::getSymbolCeCounts] " + + uint32_t o_rc = SUCCESS; + + do + { + // Get the Bad DQ Bitmap. + TargetHandle_t ocmbTrgt = iv_chip->getTrgt(); + MemDqBitmap dqBitmap; + + o_rc = getBadDqBitmap( ocmbTrgt, iv_rank, dqBitmap ); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "getBadDqBitmap(0x%08x,%d) failed", + getHuid(ocmbTrgt), iv_rank.getMaster() ); + break; + } + std::vector<MemSymbol> bmSymList = dqBitmap.getSymbolList(); + + const char * reg_str = nullptr; + SCAN_COMM_REGISTER_CLASS * reg = nullptr; + + for ( uint8_t regIdx = 0; regIdx < CE_REGS_PER_PORT; regIdx++ ) + { + reg_str = ocmbCeStatReg[regIdx]; + reg = iv_chip->getRegister( reg_str ); + + o_rc = reg->Read(); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "Read() failed on %s.", reg_str ); + break; + } + uint8_t baseSymbol = SYMBOLS_PER_CE_REG * regIdx; + + for ( uint8_t i = 0; i < SYMBOLS_PER_CE_REG; + i += MEM_SYMBOLS_PER_NIBBLE ) + { + MemUtils::MaintSymbols nibbleStats; + + // Get a nibble's worth of symbols. + for ( uint8_t n = 0; n < MEM_SYMBOLS_PER_NIBBLE; n++ ) + { + uint8_t sym = baseSymbol + (i+n); + PRDF_ASSERT( sym < SYMBOLS_PER_RANK ); + + MemUtils::SymbolData symData; + symData.symbol = MemSymbol::fromSymbol( ocmbTrgt, iv_rank, + sym, CEN_SYMBOL::ODD_SYMBOL_DQ ); + if ( !symData.symbol.isValid() ) + { + PRDF_ERR( PRDF_FUNC "MemSymbol() failed: symbol=%d", + sym ); + o_rc = FAIL; + break; + } + + // Any symbol set in the DRAM repairs VPD will have an + // automatic CE count of 0xFF + if ( std::find( bmSymList.begin(), bmSymList.end(), + symData.symbol ) != bmSymList.end() ) + symData.count = 0xFF; + else + symData.count = reg->GetBitFieldJustified(((i+n)*8), 8); + + nibbleStats.push_back( symData ); + + // Add all symbols with non-zero counts to the callout list. + if ( symData.count != 0 ) + { + MemoryMru mm { ocmbTrgt, iv_rank, symData.symbol }; + io_sc.service_data->SetCallout( mm ); + } + } + if ( SUCCESS != o_rc ) break; + + // Analyze the nibble of symbols. + __analyzeNibbleSyms<TYPE_OCMB_CHIP>( nibbleStats, io_badDqCount, + io_badChipCount, io_sumAboveOneCount, io_singleSymCount ); + + } + if ( SUCCESS != o_rc ) break; + } + + }while(0); + + return o_rc; + + #undef PRDF_FUNC + +} + +//------------------------------------------------------------------------------ + +template <TARGETING::TYPE T> +uint32_t TpsEvent<T>::analyzeCeStats( STEP_CODE_DATA_STRUCT & io_sc, + bool & o_done ) { - #define PRDF_FUNC "[TpsEvent<TYPE_MCA>::analyzeCeStats] " + #define PRDF_FUNC "[TpsEvent<T>::analyzeCeStats] " uint32_t o_rc = SUCCESS; @@ -1086,11 +1225,18 @@ uint32_t TpsEvent<TYPE_MCA>::analyzeCeStats( STEP_CODE_DATA_STRUCT & io_sc, } +template +uint32_t TpsEvent<TYPE_MCA>::analyzeCeStats( STEP_CODE_DATA_STRUCT & io_sc, + bool & o_done ); +template +uint32_t TpsEvent<TYPE_OCMB_CHIP>::analyzeCeStats(STEP_CODE_DATA_STRUCT & io_sc, + bool & o_done); + //------------------------------------------------------------------------------ -template<> -uint32_t TpsEvent<TYPE_MCA>::analyzePhase( STEP_CODE_DATA_STRUCT & io_sc, - bool & o_done ) +template<TARGETING::TYPE T> +uint32_t TpsEvent<T>::analyzePhase( STEP_CODE_DATA_STRUCT & io_sc, + bool & o_done ) { #define PRDF_FUNC "[TpsEvent::analyzePhase] " @@ -1102,11 +1248,11 @@ uint32_t TpsEvent<TYPE_MCA>::analyzePhase( STEP_CODE_DATA_STRUCT & io_sc, // Analyze Ecc Attentions uint32_t eccAttns; - o_rc = checkEccFirs<TYPE_MCA>( iv_chip, eccAttns ); + o_rc = checkEccFirs<T>( iv_chip, eccAttns ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "checkEccFirs(0x%08x) failed", - iv_chip->getHuid() ); + iv_chip->getHuid() ); break; } @@ -1135,7 +1281,7 @@ uint32_t TpsEvent<TYPE_MCA>::analyzePhase( STEP_CODE_DATA_STRUCT & io_sc, if ( (SUCCESS == o_rc) && o_done ) { // Clear the ECC FFDC for this master rank. - MemDbUtils::resetEccFfdc<TYPE_MCA>( iv_chip, iv_rank, SLAVE_RANK ); + MemDbUtils::resetEccFfdc<T>( iv_chip, iv_rank, SLAVE_RANK ); } return o_rc; @@ -1143,6 +1289,36 @@ uint32_t TpsEvent<TYPE_MCA>::analyzePhase( STEP_CODE_DATA_STRUCT & io_sc, #undef PRDF_FUNC } +template +uint32_t TpsEvent<TYPE_MCA>::analyzePhase( STEP_CODE_DATA_STRUCT & io_sc, + bool & o_done ); +template +uint32_t TpsEvent<TYPE_OCMB_CHIP>::analyzePhase( STEP_CODE_DATA_STRUCT & io_sc, + bool & o_done ); + +//------------------------------------------------------------------------------ + +template<TARGETING::TYPE T> +uint32_t TpsEvent<T>::startNextPhase( STEP_CODE_DATA_STRUCT & io_sc ) +{ + uint32_t signature = 0; + + __getNextPhase<T>( iv_chip, iv_rank, io_sc, iv_phase, signature ); + + PRDF_TRAC( "[TpsEvent] Starting TPS Phase %d: 0x%08x,0x%02x", + iv_phase, iv_chip->getHuid(), getKey() ); + + io_sc.service_data->AddSignatureList( iv_chip->getTrgt(), signature ); + + return startCmd(); +} + +template +uint32_t TpsEvent<TYPE_MCA>::startNextPhase( STEP_CODE_DATA_STRUCT & io_sc ); +template +uint32_t TpsEvent<TYPE_OCMB_CHIP>::startNextPhase( + STEP_CODE_DATA_STRUCT & io_sc ); + //############################################################################## // // Specializations for MCA @@ -1156,13 +1332,15 @@ uint32_t TpsEvent<TYPE_MCA>::startCmd() uint32_t o_rc = SUCCESS; + #ifndef CONFIG_AXONE + // We don't need to set any stop-on-error conditions or thresholds for // soft/inter/hard CEs at runtime. The design is to let the command continue // to the end of the rank and we do diagnostics on the CE counts found in // the per-symbol counters. Therefore, all we need to do is tell the // hardware which CE types to count. - mss::mcbist::stop_conditions stopCond; + mss::mcbist::stop_conditions<mss::mc_type::NIMBUS> stopCond; switch ( iv_phase ) { @@ -1190,26 +1368,67 @@ uint32_t TpsEvent<TYPE_MCA>::startCmd() iv_chip->getHuid(), getKey() ); } + #endif + return o_rc; #undef PRDF_FUNC } -//------------------------------------------------------------------------------ +//############################################################################## +// +// Specializations for OCMB +// +//############################################################################## template<> -uint32_t TpsEvent<TYPE_MCA>::startNextPhase( STEP_CODE_DATA_STRUCT & io_sc ) +uint32_t TpsEvent<TYPE_OCMB_CHIP>::startCmd() { - uint32_t signature = 0; + #define PRDF_FUNC "[TpsEvent::startCmd] " - __getNextPhase<TYPE_MCA>( iv_chip, iv_rank, io_sc, iv_phase, signature ); + uint32_t o_rc = SUCCESS; - PRDF_TRAC( "[TpsEvent] Starting TPS Phase %d: 0x%08x,0x%02x", - iv_phase, iv_chip->getHuid(), getKey() ); + #ifdef CONFIG_AXONE - io_sc.service_data->AddSignatureList( iv_chip->getTrgt(), signature ); + // We don't need to set any stop-on-error conditions or thresholds for + // soft/inter/hard CEs at runtime. The design is to let the command continue + // to the end of the rank and we do diagnostics on the CE counts found in + // the per-symbol counters. Therefore, all we need to do is tell the + // hardware which CE types to count. - return startCmd(); + mss::mcbist::stop_conditions<mss::mc_type::EXPLORER> stopCond; + + switch ( iv_phase ) + { + case TD_PHASE_1: + // Set the per symbol counters to count only hard CEs. + stopCond.set_nce_hard_symbol_count_enable(mss::ON); + break; + + case TD_PHASE_2: + // Since there are not enough hard CEs to trigger a symbol mark, set + // the per symbol counters to count all CE types. + stopCond.set_nce_soft_symbol_count_enable( mss::ON); + stopCond.set_nce_inter_symbol_count_enable(mss::ON); + stopCond.set_nce_hard_symbol_count_enable( mss::ON); + break; + + default: PRDF_ASSERT( false ); // invalid phase + } + + // Start the time based scrub procedure on this slave rank. + o_rc = startTdScrub<TYPE_OCMB_CHIP>(iv_chip, iv_rank, SLAVE_RANK, stopCond); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "startTdScrub(0x%08x,0x%2x) failed", + iv_chip->getHuid(), getKey() ); + } + + #endif + + return o_rc; + + #undef PRDF_FUNC } //############################################################################## diff --git a/src/usr/diag/prdf/plat/mem/prdfMemVcm.C b/src/usr/diag/prdf/plat/mem/prdfMemVcm.C index 8c3c4480a..784306baf 100644 --- a/src/usr/diag/prdf/plat/mem/prdfMemVcm.C +++ b/src/usr/diag/prdf/plat/mem/prdfMemVcm.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -30,6 +30,8 @@ // Platform includes #include <prdfCenMbaExtraSig.H> +#include <hwp_wrappers.H> + using namespace TARGETING; namespace PRDF @@ -39,41 +41,16 @@ using namespace PlatServices; //############################################################################## // -// Specializations for MCA +// Generic Specializations // //############################################################################## -template<> -uint32_t VcmEvent<TYPE_MCA>::startCmd() +template<TARGETING::TYPE T> +uint32_t VcmEvent<T>::handlePhaseComplete( const uint32_t & i_eccAttns, + STEP_CODE_DATA_STRUCT & io_sc, + bool & o_done ) { - #define PRDF_FUNC "[VcmEvent::startCmd] " - - uint32_t o_rc = SUCCESS; - - // No stop conditions. - mss::mcbist::stop_conditions stopCond; - - // Start the time based scrub procedure on this master rank. - o_rc = startTdScrub<TYPE_MCA>( iv_chip, iv_rank, MASTER_RANK, stopCond ); - if ( SUCCESS != o_rc ) - { - PRDF_ERR( PRDF_FUNC "startTdScrub(0x%08x,0x%2x) failed", - iv_chip->getHuid(), getKey() ); - } - - return o_rc; - - #undef PRDF_FUNC -} - -//------------------------------------------------------------------------------ - -template<> -uint32_t VcmEvent<TYPE_MCA>::handlePhaseComplete( const uint32_t & i_eccAttns, - STEP_CODE_DATA_STRUCT & io_sc, - bool & o_done ) -{ - #define PRDF_FUNC "[VcmEvent<TYPE_MCA>::handlePhaseComplete] " + #define PRDF_FUNC "[VcmEvent<T>::handlePhaseComplete] " uint32_t o_rc = SUCCESS; @@ -100,6 +77,49 @@ uint32_t VcmEvent<TYPE_MCA>::handlePhaseComplete( const uint32_t & i_eccAttns, #undef PRDF_FUNC } +template +uint32_t VcmEvent<TYPE_MCA>::handlePhaseComplete( const uint32_t & i_eccAttns, + STEP_CODE_DATA_STRUCT & io_sc, + bool & o_done ); +template +uint32_t VcmEvent<TYPE_OCMB_CHIP>::handlePhaseComplete( + const uint32_t & i_eccAttns, + STEP_CODE_DATA_STRUCT & io_sc, + bool & o_done ); + +//############################################################################## +// +// Specializations for MCA +// +//############################################################################## + +template<> +uint32_t VcmEvent<TYPE_MCA>::startCmd() +{ + #define PRDF_FUNC "[VcmEvent::startCmd] " + + uint32_t o_rc = SUCCESS; + + #ifndef CONFIG_AXONE + + // No stop conditions. + mss::mcbist::stop_conditions<mss::mc_type::NIMBUS> stopCond; + + // Start the time based scrub procedure on this master rank. + o_rc = startTdScrub<TYPE_MCA>( iv_chip, iv_rank, MASTER_RANK, stopCond ); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "startTdScrub(0x%08x,0x%2x) failed", + iv_chip->getHuid(), getKey() ); + } + + #endif + + return o_rc; + + #undef PRDF_FUNC +} + //############################################################################## // // Specializations for MBA @@ -448,6 +468,40 @@ uint32_t VcmEvent<TYPE_MBA>::handlePhaseComplete( const uint32_t & i_eccAttns, #undef PRDF_FUNC } +//############################################################################## +// +// Specializations for OCMB +// +//############################################################################## + +template<> +uint32_t VcmEvent<TYPE_OCMB_CHIP>::startCmd() +{ + #define PRDF_FUNC "[VcmEvent::startCmd] " + + uint32_t o_rc = SUCCESS; + + #ifdef CONFIG_AXONE + + // No stop conditions. + mss::mcbist::stop_conditions<mss::mc_type::EXPLORER> stopCond; + + // Start the time based scrub procedure on this master rank. + o_rc = startTdScrub<TYPE_OCMB_CHIP>( iv_chip, iv_rank, MASTER_RANK, + stopCond ); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "startTdScrub(0x%08x,0x%2x) failed", + iv_chip->getHuid(), getKey() ); + } + + #endif + + return o_rc; + + #undef PRDF_FUNC +} + //------------------------------------------------------------------------------ } // end namespace PRDF diff --git a/src/usr/diag/prdf/plat/mem/prdfMemVcm.H b/src/usr/diag/prdf/plat/mem/prdfMemVcm.H index b319f910b..c712d6aa3 100644 --- a/src/usr/diag/prdf/plat/mem/prdfMemVcm.H +++ b/src/usr/diag/prdf/plat/mem/prdfMemVcm.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -342,6 +342,9 @@ class VcmEvent : public TdEntry #ifdef __HOSTBOOT_RUNTIME template<> uint32_t VcmEvent<TARGETING::TYPE_MCA>::cleanup(STEP_CODE_DATA_STRUCT & io_sc); +template<> +uint32_t VcmEvent<TARGETING::TYPE_OCMB_CHIP>::cleanup( + STEP_CODE_DATA_STRUCT & io_sc); #endif template<> diff --git a/src/usr/diag/prdf/plat/mem/prdfMemVcm_ipl.C b/src/usr/diag/prdf/plat/mem/prdfMemVcm_ipl.C index 26ef1d727..5ffa9a84b 100644 --- a/src/usr/diag/prdf/plat/mem/prdfMemVcm_ipl.C +++ b/src/usr/diag/prdf/plat/mem/prdfMemVcm_ipl.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -92,6 +92,12 @@ bool __iueCheck<TYPE_MCA>( uint32_t i_eccAttns ) } template<> inline +bool __iueCheck<TYPE_OCMB_CHIP>( uint32_t i_eccAttns ) +{ + return ( 0 != (i_eccAttns & MAINT_IUE) ); +} + +template<> inline bool __iueCheck<TYPE_MBA>( uint32_t i_eccAttns ) { // IUES are reported via RCE ETE on Centaur @@ -218,6 +224,7 @@ uint32_t VcmEvent<TYPE_MBA>::startCmd() // Avoid linker errors with the template. template class VcmEvent<TYPE_MCA>; template class VcmEvent<TYPE_MBA>; +template class VcmEvent<TYPE_OCMB_CHIP>; } // end namespace PRDF diff --git a/src/usr/diag/prdf/plat/mem/prdfMemVcm_rt.C b/src/usr/diag/prdf/plat/mem/prdfMemVcm_rt.C index ca4de8e5a..e64227996 100644 --- a/src/usr/diag/prdf/plat/mem/prdfMemVcm_rt.C +++ b/src/usr/diag/prdf/plat/mem/prdfMemVcm_rt.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -55,6 +55,12 @@ VcmFalseAlarm * __getFalseAlarmCounter<TYPE_MCA>( ExtensibleChip * i_chip ) } template<> +VcmFalseAlarm * __getFalseAlarmCounter<TYPE_OCMB_CHIP>(ExtensibleChip * i_chip) +{ + return getOcmbDataBundle(i_chip)->getVcmFalseAlarmCounter(); +} + +template<> VcmFalseAlarm * __getFalseAlarmCounter<TYPE_MBA>( ExtensibleChip * i_chip ) { return getMbaDataBundle(i_chip)->getVcmFalseAlarmCounter(); @@ -62,16 +68,16 @@ VcmFalseAlarm * __getFalseAlarmCounter<TYPE_MBA>( ExtensibleChip * i_chip ) //############################################################################## // -// Specializations for MCA +// Generic Specializations // //############################################################################## -template<> -uint32_t VcmEvent<TYPE_MCA>::checkEcc( const uint32_t & i_eccAttns, - STEP_CODE_DATA_STRUCT & io_sc, - bool & o_done ) +template<TARGETING::TYPE T> +uint32_t VcmEvent<T>::checkEcc( const uint32_t & i_eccAttns, + STEP_CODE_DATA_STRUCT & io_sc, + bool & o_done ) { - #define PRDF_FUNC "[VcmEvent<TYPE_MCA>::checkEcc] " + #define PRDF_FUNC "[VcmEvent<T>::checkEcc] " uint32_t o_rc = SUCCESS; @@ -88,7 +94,7 @@ uint32_t VcmEvent<TYPE_MCA>::checkEcc( const uint32_t & i_eccAttns, // At this point we don't actually have an address for the UE. The // best we can do is get the address in which the command stopped. MemAddr addr; - o_rc = getMemMaintAddr<TYPE_MCA>( iv_chip, addr ); + o_rc = getMemMaintAddr<T>( iv_chip, addr ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "getMemMaintAddr(0x%08x) failed", @@ -96,7 +102,7 @@ uint32_t VcmEvent<TYPE_MCA>::checkEcc( const uint32_t & i_eccAttns, break; } - o_rc = MemEcc::handleMemUe<TYPE_MCA>( iv_chip, addr, + o_rc = MemEcc::handleMemUe<T>( iv_chip, addr, UE_TABLE::SCRUB_UE, io_sc ); if ( SUCCESS != o_rc ) { @@ -107,7 +113,7 @@ uint32_t VcmEvent<TYPE_MCA>::checkEcc( const uint32_t & i_eccAttns, // Because of the UE, any further TPS requests will likely have no // effect. So ban all subsequent requests. - MemDbUtils::banTps<TYPE_MCA>( iv_chip, addr.getRank() ); + MemDbUtils::banTps<T>( iv_chip, addr.getRank() ); // Leave the mark in place and abort this procedure. o_done = true; break; @@ -118,7 +124,7 @@ uint32_t VcmEvent<TYPE_MCA>::checkEcc( const uint32_t & i_eccAttns, io_sc.service_data->setSignature( iv_chip->getHuid(), PRDFSIG_MaintIUE ); - o_rc = MemEcc::handleMemIue<TYPE_MCA>( iv_chip, iv_rank, io_sc ); + o_rc = MemEcc::handleMemIue<T>( iv_chip, iv_rank, io_sc ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "handleMemIue(0x%08x,0x%02x) failed", @@ -143,6 +149,14 @@ uint32_t VcmEvent<TYPE_MCA>::checkEcc( const uint32_t & i_eccAttns, #undef PRDF_FUNC } +template +uint32_t VcmEvent<TYPE_MCA>::checkEcc( const uint32_t & i_eccAttns, + STEP_CODE_DATA_STRUCT & io_sc, + bool & o_done ); +template +uint32_t VcmEvent<TYPE_OCMB_CHIP>::checkEcc( const uint32_t & i_eccAttns, + STEP_CODE_DATA_STRUCT & io_sc, + bool & o_done ); //------------------------------------------------------------------------------ @@ -180,6 +194,41 @@ uint32_t VcmEvent<TYPE_MCA>::cleanup( STEP_CODE_DATA_STRUCT & io_sc ) #undef PRDF_FUNC } +template<> +uint32_t VcmEvent<TYPE_OCMB_CHIP>::cleanup( STEP_CODE_DATA_STRUCT & io_sc ) +{ + #define PRDF_FUNC "[VcmEvent::cleanup] " + + uint32_t o_rc = SUCCESS; + + do + { + o_rc = MarkStore::chipMarkCleanup<TYPE_OCMB_CHIP>( iv_chip, iv_rank, + io_sc ); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "chipMarkCleanup(0x%08x,0x%02x) failed", + iv_chip->getHuid(), iv_rank.getKey() ); + break; + } + + // The cleanup() function is called by both verified() and falseAlarm(). + // In either case, the error log should be predictive if there has been + // a least one false alarm on any DRAM on this rank other than this + // DRAM. This is required on Nimbus because of two symbol correction, + // which does not exist on Centaur. + VcmFalseAlarm * faCntr =__getFalseAlarmCounter<TYPE_OCMB_CHIP>(iv_chip); + uint8_t dram = iv_mark.getSymbol().getDram(); + if ( faCntr->queryDrams(iv_rank, dram, io_sc) ) + io_sc.service_data->setServiceCall(); + + } while (0); + + return o_rc; + + #undef PRDF_FUNC +} + //############################################################################## // // Specializations for MBA @@ -386,6 +435,7 @@ uint32_t VcmEvent<T>::falseAlarm( STEP_CODE_DATA_STRUCT & io_sc ) // Avoid linker errors with the template. template class VcmEvent<TYPE_MCA>; template class VcmEvent<TYPE_MBA>; +template class VcmEvent<TYPE_OCMB_CHIP>; //------------------------------------------------------------------------------ diff --git a/src/usr/diag/prdf/plat/mem/prdfP9Mca.C b/src/usr/diag/prdf/plat/mem/prdfP9Mca.C index 5f7efa274..fac29fce3 100644 --- a/src/usr/diag/prdf/plat/mem/prdfP9Mca.C +++ b/src/usr/diag/prdf/plat/mem/prdfP9Mca.C @@ -27,7 +27,6 @@ #include <iipServiceDataCollector.h> #include <prdfExtensibleChip.H> #include <prdfPluginMap.H> -#include <isteps/nvdimm/nvdimm.H> // Platform includes #include <prdfMemDbUtils.H> @@ -38,6 +37,10 @@ #include <prdfMemTps.H> #endif +#ifdef CONFIG_NVDIMM + #include <nvdimm.H> +#endif + using namespace TARGETING; namespace PRDF @@ -296,18 +299,9 @@ PRDF_PLUGIN_DEFINE( nimbus_mca, MemPortFailure ); // //############################################################################## +#ifdef CONFIG_NVDIMM #ifdef __HOSTBOOT_RUNTIME -enum nvdimmRegOffset -{ - NVDIMM_MGT_CMD1 = 0x041, - MODULE_HEALTH = 0x0A0, - MODULE_HEALTH_STATUS0 = 0x0A1, - MODULE_HEALTH_STATUS1 = 0x0A2, - ERROR_THRESHOLD_STATUS = 0x0A5, - WARNING_THRESHOLD_STATUS = 0x0A7, -}; - /** * @brief Gets a map list of which bits are set from a uint8_t bit list (7:0) * @param i_data uint8_t bit list (7:0) @@ -349,6 +343,7 @@ uint32_t __addBpmCallout( TargetHandle_t i_dimm, break; } + // addPartCallout will default to GARD_NULL, NO_DECONFIG mainErrl->addPartCallout( i_dimm, HWAS::BPM_PART_TYPE, i_priority ); @@ -362,10 +357,12 @@ uint32_t __addBpmCallout( TargetHandle_t i_dimm, /** * @brief Adds a callout of the cable connecting an NVDIMM to its * backup power module (BPM) + * @param i_dimm The target dimm. * @param i_priority The callout priority. * @return FAIL if unable to get the global error log, else SUCCESS */ -uint32_t __addNvdimmCableCallout( HWAS::callOutPriority i_priority ) +uint32_t __addNvdimmCableCallout( TargetHandle_t i_dimm, + HWAS::callOutPriority i_priority ) { #define PRDF_FUNC "[__addNvdimmCableCallout] " @@ -382,7 +379,9 @@ uint32_t __addNvdimmCableCallout( HWAS::callOutPriority i_priority ) break; } - mainErrl->addProcedureCallout( HWAS::EPUB_PRC_NVDIMM_ERR, i_priority ); + // addPartCallout will default to GARD_NULL, NO_DECONFIG + mainErrl->addPartCallout( i_dimm, HWAS::BPM_CABLE_PART_TYPE, + i_priority ); }while(0); @@ -391,21 +390,45 @@ uint32_t __addNvdimmCableCallout( HWAS::callOutPriority i_priority ) #undef PRDF_FUNC } +/** + * @brief If a previous error has been found, add a signature to the + * multi-signature list, else set the primary signature. + * @param io_sc The step code data struct. + * @param i_trgt The target. + * @param i_errFound Whether an error has already been found or not. + * @param i_sig The signature to be set. + */ +void __addSignature( STEP_CODE_DATA_STRUCT & io_sc, TargetHandle_t i_trgt, + bool i_errFound, uint32_t i_sig ) +{ + if ( i_errFound ) + { + io_sc.service_data->AddSignatureList( i_trgt, i_sig ); + } + else + { + io_sc.service_data->setSignature( getHuid(i_trgt), i_sig ); + } +} /** * @brief Analyze NVDIMM Health Status0 Register for errors - * @param io_sc The step code data struct. - * @param i_dimm The target dimm. + * @param io_sc The step code data struct. + * @param i_dimm The target dimm. + * @param io_errFound Whether an error has already been found or not. * @return FAIL if unable to read register, else SUCCESS */ -uint32_t __analyzeHealthStatus0Reg( STEP_CODE_DATA_STRUCT & io_sc, - TargetHandle_t i_dimm ) +uint32_t __analyzeHealthStatus0Reg(STEP_CODE_DATA_STRUCT & io_sc, + TargetHandle_t i_dimm, bool & io_errFound) { #define PRDF_FUNC "[__analyzeHealthStatus0Reg] " uint32_t o_rc = SUCCESS; uint8_t data = 0; + // Get MCA, for signatures + TargetHandle_t mca = getConnectedParent( i_dimm, TYPE_MCA ); + do { // NVDIMM health status registers size = 1 byte @@ -413,7 +436,7 @@ uint32_t __analyzeHealthStatus0Reg( STEP_CODE_DATA_STRUCT & io_sc, // Read the Health Status0 Register (0xA1) 7:0 errlHndl_t errl = deviceRead( i_dimm, &data, NVDIMM_SIZE, - DEVICE_NVDIMM_ADDRESS(MODULE_HEALTH_STATUS0) ); + DEVICE_NVDIMM_ADDRESS(NVDIMM::i2cReg::MODULE_HEALTH_STATUS0) ); if ( errl ) { PRDF_ERR( PRDF_FUNC "Failed to read Health Status0 Register. " @@ -427,58 +450,66 @@ uint32_t __analyzeHealthStatus0Reg( STEP_CODE_DATA_STRUCT & io_sc, // BIT 0: Voltage Regulator Fail if ( bitList.count(0) ) { - io_sc.service_data->AddSignatureList( i_dimm, PRDFSIG_VoltRegFail ); + __addSignature( io_sc, mca, io_errFound, PRDFSIG_VoltRegFail ); // Callout NVDIMM on 1st, no gard - io_sc.service_data->SetCallout( i_dimm, MRU_HIGH, NO_GARD ); + io_sc.service_data->SetCallout( i_dimm, MRU_MED, NO_GARD ); + io_errFound = true; } // BIT 1: VDD Lost if ( bitList.count(1) ) { - io_sc.service_data->AddSignatureList( i_dimm, PRDFSIG_VddLost ); + __addSignature( io_sc, mca, io_errFound, PRDFSIG_VddLost ); // Callout NVDIMM on 1st, no gard - io_sc.service_data->SetCallout( i_dimm, MRU_HIGH, NO_GARD ); + io_sc.service_data->SetCallout( i_dimm, MRU_MED, NO_GARD ); + io_errFound = true; } // BIT 2: VPP Lost if ( bitList.count(2) ) { - io_sc.service_data->AddSignatureList( i_dimm, PRDFSIG_VppLost ); + __addSignature( io_sc, mca, io_errFound, PRDFSIG_VppLost ); // Callout NVDIMM on 1st, no gard - io_sc.service_data->SetCallout( i_dimm, MRU_HIGH, NO_GARD ); + io_sc.service_data->SetCallout( i_dimm, MRU_MED, NO_GARD ); + io_errFound = true; } // BIT 3: VTT Lost if ( bitList.count(3) ) { - io_sc.service_data->AddSignatureList( i_dimm, PRDFSIG_VttLost ); + __addSignature( io_sc, mca, io_errFound, PRDFSIG_VttLost ); // Callout NVDIMM on 1st, no gard - io_sc.service_data->SetCallout( i_dimm, MRU_HIGH, NO_GARD ); + io_sc.service_data->SetCallout( i_dimm, MRU_MED, NO_GARD ); + io_errFound = true; } // BIT 4: DRAM not Self Refresh if ( bitList.count(4) ) { - io_sc.service_data->AddSignatureList( i_dimm, PRDFSIG_NotSelfRefr ); + __addSignature( io_sc, mca, io_errFound, PRDFSIG_NotSelfRefr ); // Callout NVDIMM on 1st, no gard - io_sc.service_data->SetCallout( i_dimm, MRU_HIGH, NO_GARD ); + io_sc.service_data->SetCallout( i_dimm, MRU_MED, NO_GARD ); + io_errFound = true; } // BIT 5: Controller HW Error if ( bitList.count(5) ) { - io_sc.service_data->AddSignatureList( i_dimm, PRDFSIG_CtrlHwErr ); + __addSignature( io_sc, mca, io_errFound, PRDFSIG_CtrlHwErr ); // Callout NVDIMM on 1st, no gard - io_sc.service_data->SetCallout( i_dimm, MRU_HIGH, NO_GARD ); + io_sc.service_data->SetCallout( i_dimm, MRU_MED, NO_GARD ); + io_errFound = true; } // BIT 6: NVM Controller Error if ( bitList.count(6) ) { - io_sc.service_data->AddSignatureList( i_dimm, PRDFSIG_NvmCtrlErr ); + __addSignature( io_sc, mca, io_errFound, PRDFSIG_NvmCtrlErr ); // Callout NVDIMM on 1st, no gard - io_sc.service_data->SetCallout( i_dimm, MRU_HIGH, NO_GARD ); + io_sc.service_data->SetCallout( i_dimm, MRU_MED, NO_GARD ); + io_errFound = true; } // BIT 7: NVM Lifetime Error if ( bitList.count(7) ) { - io_sc.service_data->AddSignatureList( i_dimm, PRDFSIG_NvmLifeErr ); + __addSignature( io_sc, mca, io_errFound, PRDFSIG_NvmLifeErr ); // Callout NVDIMM on 1st, no gard - io_sc.service_data->SetCallout( i_dimm, MRU_HIGH, NO_GARD ); + io_sc.service_data->SetCallout( i_dimm, MRU_MED, NO_GARD ); + io_errFound = true; } }while(0); @@ -491,18 +522,22 @@ uint32_t __analyzeHealthStatus0Reg( STEP_CODE_DATA_STRUCT & io_sc, /** * @brief Analyze NVDIMM Health Status1 Register for errors - * @param io_sc The step code data struct. - * @param i_dimm The target dimm. + * @param io_sc The step code data struct. + * @param i_dimm The target dimm. + * @param io_errFound Whether an error has already been found or not. * @return FAIL if unable to read register, else SUCCESS */ uint32_t __analyzeHealthStatus1Reg( STEP_CODE_DATA_STRUCT & io_sc, - TargetHandle_t i_dimm ) + TargetHandle_t i_dimm, bool & io_errFound ) { #define PRDF_FUNC "[__analyzeHealthStatus1Reg] " uint32_t o_rc = SUCCESS; uint8_t data = 0; + // Get MCA, for signatures + TargetHandle_t mca = getConnectedParent( i_dimm, TYPE_MCA ); + do { // NVDIMM health status registers size = 1 byte @@ -510,7 +545,7 @@ uint32_t __analyzeHealthStatus1Reg( STEP_CODE_DATA_STRUCT & io_sc, // Read the Health Status1 Register (0xA2) 7:0 errlHndl_t errl = deviceRead( i_dimm, &data, NVDIMM_SIZE, - DEVICE_NVDIMM_ADDRESS(MODULE_HEALTH_STATUS1) ); + DEVICE_NVDIMM_ADDRESS(NVDIMM::i2cReg::MODULE_HEALTH_STATUS1) ); if ( errl ) { PRDF_ERR( PRDF_FUNC "Failed to read Health Status1 Register. " @@ -524,83 +559,90 @@ uint32_t __analyzeHealthStatus1Reg( STEP_CODE_DATA_STRUCT & io_sc, // BIT 0: Insufficient Energy if ( bitList.count(0) ) { - io_sc.service_data->AddSignatureList(i_dimm, PRDFSIG_InsuffEnergy); + __addSignature( io_sc, mca, io_errFound, PRDFSIG_InsuffEnergy ); // Callout BPM (backup power module) high, cable high o_rc = __addBpmCallout( i_dimm, HWAS::SRCI_PRIORITY_HIGH ); if ( SUCCESS != o_rc ) break; - o_rc = __addNvdimmCableCallout( HWAS::SRCI_PRIORITY_HIGH ); + o_rc = __addNvdimmCableCallout( i_dimm, HWAS::SRCI_PRIORITY_HIGH ); if ( SUCCESS != o_rc ) break; // Callout NVDIMM low, no gard io_sc.service_data->SetCallout( i_dimm, MRU_LOW, NO_GARD ); + io_errFound = true; } // BIT 1: Invalid Firmware if ( bitList.count(1) ) { - io_sc.service_data->AddSignatureList( i_dimm, PRDFSIG_InvFwErr ); + __addSignature( io_sc, mca, io_errFound, PRDFSIG_InvFwErr ); // Callout NVDIMM on 1st, no gard - io_sc.service_data->SetCallout( i_dimm, MRU_HIGH, NO_GARD ); + io_sc.service_data->SetCallout( i_dimm, MRU_MED, NO_GARD ); + io_errFound = true; } // BIT 2: Configuration Data Error if ( bitList.count(2) ) { - io_sc.service_data->AddSignatureList( i_dimm, PRDFSIG_CnfgDataErr ); + __addSignature( io_sc, mca, io_errFound, PRDFSIG_CnfgDataErr ); // Callout NVDIMM on 1st, no gard - io_sc.service_data->SetCallout( i_dimm, MRU_HIGH, NO_GARD ); + io_sc.service_data->SetCallout( i_dimm, MRU_MED, NO_GARD ); + io_errFound = true; } // BIT 3: No Energy Source if ( bitList.count(3) ) { - io_sc.service_data->AddSignatureList(i_dimm, PRDFSIG_NoEsPres); + __addSignature( io_sc, mca, io_errFound, PRDFSIG_NoEsPres ); // Callout BPM (backup power module) high, cable high o_rc = __addBpmCallout( i_dimm, HWAS::SRCI_PRIORITY_HIGH ); if ( SUCCESS != o_rc ) break; - o_rc = __addNvdimmCableCallout( HWAS::SRCI_PRIORITY_HIGH ); + o_rc = __addNvdimmCableCallout( i_dimm, HWAS::SRCI_PRIORITY_HIGH ); if ( SUCCESS != o_rc ) break; // Callout NVDIMM low, no gard io_sc.service_data->SetCallout( i_dimm, MRU_LOW, NO_GARD ); + io_errFound = true; } // BIT 4: Energy Policy Not Set if ( bitList.count(4) ) { - io_sc.service_data->AddSignatureList( i_dimm, PRDFSIG_EsPolNotSet ); + __addSignature( io_sc, mca, io_errFound, PRDFSIG_EsPolNotSet ); // Callout FW (Level2 Support) High io_sc.service_data->SetCallout( LEVEL2_SUPPORT, MRU_HIGH, NO_GARD ); // Callout NVDIMM low on 1st, no gard io_sc.service_data->SetCallout( i_dimm, MRU_LOW, NO_GARD ); + io_errFound = true; } // BIT 5: Energy Source HW Error if ( bitList.count(5) ) { - io_sc.service_data->AddSignatureList ( i_dimm, PRDFSIG_EsHwFail ); + __addSignature( io_sc, mca, io_errFound, PRDFSIG_EsHwFail ); // Callout BPM (backup power module) high, cable high o_rc = __addBpmCallout( i_dimm, HWAS::SRCI_PRIORITY_HIGH ); if ( SUCCESS != o_rc ) break; - o_rc = __addNvdimmCableCallout( HWAS::SRCI_PRIORITY_HIGH ); + o_rc = __addNvdimmCableCallout( i_dimm, HWAS::SRCI_PRIORITY_HIGH ); if ( SUCCESS != o_rc ) break; // Callout NVDIMM low, no gard io_sc.service_data->SetCallout( i_dimm, MRU_LOW, NO_GARD ); + io_errFound = true; } // BIT 6: Energy Source Health Assessment Error if ( bitList.count(6) ) { - io_sc.service_data->AddSignatureList(i_dimm, PRDFSIG_EsHlthAssess); + __addSignature( io_sc, mca, io_errFound, PRDFSIG_EsHlthAssess); // Callout BPM (backup power module) high, cable high o_rc = __addBpmCallout( i_dimm, HWAS::SRCI_PRIORITY_HIGH ); if ( SUCCESS != o_rc ) break; - o_rc = __addNvdimmCableCallout( HWAS::SRCI_PRIORITY_HIGH ); + o_rc = __addNvdimmCableCallout( i_dimm, HWAS::SRCI_PRIORITY_HIGH ); if ( SUCCESS != o_rc ) break; // Callout NVDIMM low, no gard io_sc.service_data->SetCallout( i_dimm, MRU_LOW, NO_GARD ); + io_errFound = true; } // BIT 7: Reserved @@ -613,18 +655,105 @@ uint32_t __analyzeHealthStatus1Reg( STEP_CODE_DATA_STRUCT & io_sc, } /** + * @brief Reads and merges the data from two ES_TEMP registers to get the + * correct temperature format. + * @param i_dimm The target nvdimm. + * @param i_tempMsbReg The address of the register that contains the most + * significant byte of the temperature data. + * @param i_tempLsbReg The address of the register that contains the least + * significant byte of the temperature data. + * @param o_tempData The 16 bit temperature data. + * @return FAIL if unable to read register, else SUCCESS + */ +uint32_t __readTemp( TargetHandle_t i_dimm, uint16_t i_tempMsbReg, + uint16_t i_tempLsbReg, uint16_t & o_tempData ) +{ + #define PRDF_FUNC "[__readTemp] " + + /* + * -NOTE: Example showing how to read the temperature format: + * ES_TEMP1 = 0x03 (MSB: bits 15-8) + * ES_TEMP0 = 0x48 (LSB: bits 7-0) + * + * 0x0348 = 0000 0011 0100 1000 = 52.5 C + * + * -NOTE: bit definition: + * [15:13]Reserved + * [12]Sign 0 = positive, 1 = negative; 0°C should be expressed as positive + * [11] 128°C + * [10] 64°C + * [9] 32°C + * [8] 16°C + * [7] 8°C + * [6] 4°C + * [5] 2°C + * [4] 1°C + * [3] 0.5°C + * [2] 0.25°C + * [1] 0.125°C Optional for temp fields; not used for temp th fields + * [0]0.0625°C Optional for temp fields; not used for temp th fields + */ + uint32_t o_rc = SUCCESS; + + do + { + // NVDIMM health status registers size = 1 byte + size_t NVDIMM_SIZE = 1; + uint8_t msbData = 0; + uint8_t lsbData = 0; + + // Read the two inputted temperature registers. + errlHndl_t errl = deviceRead( i_dimm, &msbData, NVDIMM_SIZE, + DEVICE_NVDIMM_ADDRESS(i_tempMsbReg) ); + if ( errl ) + { + PRDF_ERR( PRDF_FUNC "Failed to read ES Temperature MSB Register. " + "HUID: 0x%08x", getHuid(i_dimm) ); + PRDF_COMMIT_ERRL( errl, ERRL_ACTION_REPORT ); + o_rc = FAIL; + break; + } + + errl = deviceRead( i_dimm, &lsbData, NVDIMM_SIZE, + DEVICE_NVDIMM_ADDRESS(i_tempLsbReg) ); + if ( errl ) + { + PRDF_ERR( PRDF_FUNC "Failed to read ES Temperature LSB Register. " + "HUID: 0x%08x", getHuid(i_dimm) ); + PRDF_COMMIT_ERRL( errl, ERRL_ACTION_REPORT ); + o_rc = FAIL; + break; + } + + o_tempData = ((uint16_t)msbData << 8) | lsbData; + + }while(0); + + return o_rc; + + #undef PRDF_FUNC +} + +/** * @brief Analyze NVDIMM Error Threshold Status Register for errors - * @param io_sc The step code data struct. - * @param i_dimm The target dimm. + * @param io_sc The step code data struct. + * @param i_dimm The target dimm. + * @param io_errFound Whether an error has already been found or not. + * @param o_esTempErr A flag for whether we hit an ES TEMP error or not. * @return FAIL if unable to read register, else SUCCESS */ uint32_t __analyzeErrorThrStatusReg( STEP_CODE_DATA_STRUCT & io_sc, - TargetHandle_t i_dimm ) + TargetHandle_t i_dimm, bool & io_errFound, + bool & o_esTempErr ) { #define PRDF_FUNC "[__analyzeErrorThrStatusReg] " uint32_t o_rc = SUCCESS; uint8_t data = 0; + o_esTempErr = false; + + // Get MCA, for signatures + TargetHandle_t mca = getConnectedParent( i_dimm, TYPE_MCA ); do { @@ -633,7 +762,7 @@ uint32_t __analyzeErrorThrStatusReg( STEP_CODE_DATA_STRUCT & io_sc, // Read the Error Threshold Status Register (0xA5) 7:0 errlHndl_t errl = deviceRead( i_dimm, &data, NVDIMM_SIZE, - DEVICE_NVDIMM_ADDRESS(ERROR_THRESHOLD_STATUS) ); + DEVICE_NVDIMM_ADDRESS(NVDIMM::i2cReg::ERROR_THRESHOLD_STATUS) ); if ( errl ) { PRDF_ERR( PRDF_FUNC "Failed to read Error Threshold Status Reg. " @@ -648,7 +777,7 @@ uint32_t __analyzeErrorThrStatusReg( STEP_CODE_DATA_STRUCT & io_sc, // BIT 1: ES Lifetime Error if ( bitList.count(1) ) { - io_sc.service_data->AddSignatureList ( i_dimm, PRDFSIG_EsLifeErr ); + __addSignature( io_sc, mca, io_errFound, PRDFSIG_EsLifeErr ); // Callout BPM (backup power module) high o_rc = __addBpmCallout( i_dimm, HWAS::SRCI_PRIORITY_HIGH ); @@ -656,11 +785,60 @@ uint32_t __analyzeErrorThrStatusReg( STEP_CODE_DATA_STRUCT & io_sc, // Callout NVDIMM low, no gard io_sc.service_data->SetCallout( i_dimm, MRU_LOW, NO_GARD ); + io_errFound = true; } // BIT 2: ES Temperature Error if ( bitList.count(2) ) { - io_sc.service_data->AddSignatureList( i_dimm, PRDFSIG_EsTmpErr ); + // Sleep two seconds to avoid exiting PRD analysis faster than the + // ES_TEMP sample rate. + PlatServices::milliSleep( 2, 0 ); + + // Read the ES_TEMP and ES_TEMP_ERROR_HIGH_THRESHOLD values + uint16_t msbEsTempReg = NVDIMM::i2cReg::ES_TEMP1; + uint16_t lsbEsTempReg = NVDIMM::i2cReg::ES_TEMP0; + uint16_t esTemp = 0; + o_rc = __readTemp( i_dimm, msbEsTempReg, lsbEsTempReg, esTemp ); + if ( SUCCESS != o_rc ) break; + + uint16_t msbThReg = NVDIMM::i2cReg::ES_TEMP_ERROR_HIGH_THRESHOLD1; + uint16_t lsbThReg = NVDIMM::i2cReg::ES_TEMP_ERROR_HIGH_THRESHOLD0; + uint16_t esTempHighTh = 0; + o_rc = __readTemp( i_dimm, msbThReg, lsbThReg, esTempHighTh ); + if ( SUCCESS != o_rc ) break; + + msbThReg = NVDIMM::i2cReg::ES_TEMP_ERROR_LOW_THRESHOLD1; + lsbThReg = NVDIMM::i2cReg::ES_TEMP_ERROR_LOW_THRESHOLD0; + uint16_t esTempLowTh = 0; + o_rc = __readTemp( i_dimm, msbThReg, lsbThReg, esTempLowTh ); + if ( SUCCESS != o_rc ) break; + + // Check to see if the ES_TEMP is negative (bit 12) + bool esTempNeg = false; + if ( esTemp & 0x1000 ) esTempNeg = true; + + // If ES_TEMP is equal or above ES_TEMP_ERROR_HIGH_THRESHOLD + // Just in case ES_TEMP has moved before we read it out, we'll add + // a 2°C margin when comparing to the threshold. + if ( (esTemp >= (esTempHighTh - 0x0020)) && !esTempNeg ) + { + __addSignature( io_sc, mca, io_errFound, + PRDFSIG_EsTmpErrHigh ); + } + // Else check if the error hit the low threshold, again with the + // same 2°C margin. + else if ( (esTemp <= (esTempLowTh + 0x0020)) || esTempNeg ) + { + __addSignature( io_sc, mca, io_errFound, + PRDFSIG_EsTmpErrLow ); + } + // Else the temperature must have gone back to a normal value, so + // we will label this as a false alarm case. + else + { + __addSignature( io_sc, mca, io_errFound, + PRDFSIG_EsTmpErrFa ); + } // Callout BPM (backup power module) high o_rc = __addBpmCallout( i_dimm, HWAS::SRCI_PRIORITY_HIGH ); @@ -668,6 +846,9 @@ uint32_t __analyzeErrorThrStatusReg( STEP_CODE_DATA_STRUCT & io_sc, // Callout NVDIMM low, no gard io_sc.service_data->SetCallout( i_dimm, MRU_LOW, NO_GARD ); + + o_esTempErr = true; + io_errFound = true; } // BIT 3:7: Reserved @@ -680,6 +861,419 @@ uint32_t __analyzeErrorThrStatusReg( STEP_CODE_DATA_STRUCT & io_sc, } /** + * @brief Adjusts the warning threshold so that future warnings are allowed + * to report. + * @param io_sc The step code data struct. + * @param i_dimm The target nvdimm. + * @param i_warnThReg The address of the relevant warning threshold register. + * @param i_errThReg The address of the relevant error threshold register. + * @param o_firstWarn Flag if this is the first warning of this type. + * @param o_statusErr Flag to tell if we found an error from checking the + * notification status register. + * @return FAIL if unable to read register, else SUCCESS + */ +uint32_t __adjustThreshold( STEP_CODE_DATA_STRUCT & io_sc, + TargetHandle_t i_dimm, uint16_t i_warnThReg, + uint16_t i_errThReg, bool & o_firstWarn, + bool & o_statusErr ) +{ + #define PRDF_FUNC "[__adjustThreshold] " + + uint32_t o_rc = SUCCESS; + uint16_t notifCmdReg = NVDIMM::i2cReg::SET_EVENT_NOTIFICATION_CMD; + uint16_t notifStatusReg = NVDIMM::i2cReg::SET_EVENT_NOTIFICATION_STATUS; + o_firstWarn = false; + o_statusErr = false; + + do + { + // NVDIMM health status registers size = 1 byte + size_t NVDIMM_SIZE = 1; + + // Read the corresponding warning threshold + uint8_t warnTh = 0; + errlHndl_t errl = deviceRead( i_dimm, &warnTh, NVDIMM_SIZE, + DEVICE_NVDIMM_ADDRESS(i_warnThReg) ); + if ( errl ) + { + PRDF_ERR( PRDF_FUNC "Failed to read Warning Threshold Reg. HUID: " + "0x%08x", getHuid(i_dimm) ); + PRDF_COMMIT_ERRL( errl, ERRL_ACTION_REPORT ); + o_rc = FAIL; + break; + } + + // Read the corresponding error threshold + uint8_t errTh = 0; + errl = deviceRead( i_dimm, &errTh, NVDIMM_SIZE, + DEVICE_NVDIMM_ADDRESS(i_errThReg) ); + if ( errl ) + { + PRDF_ERR( PRDF_FUNC "Failed to read Error Threshold Reg. HUID: " + "0x%08x", getHuid(i_dimm) ); + PRDF_COMMIT_ERRL( errl, ERRL_ACTION_REPORT ); + o_rc = FAIL; + break; + } + + // If the warning threshold is not set to the error threshold+1, + // move the threshold. + if ( warnTh != (errTh+1) ) + { + o_firstWarn = true; + + // SET_EVENT_NOTIFICATION_CMD is a write only register that is + // used to change the SET_EVENT_NOTIFICATION_STATUS register. + // The only bits within it that are used are bits 0 and 1, as such + // we can safely set the rest to 0. It is defined as: + // [0]: Persistency Notification + // [1]: Warning Threshold Notification + // [2]: Obsolete + // [3]: Firmware Activation Notification (Not Used) + // [4:7]: Reserved + + // Clear SET_EVENT_NOTIFICATION_CMD bit 1 and keep bit 0 set + uint8_t notifCmd = 0x01; + errl = deviceWrite( i_dimm, ¬ifCmd, NVDIMM_SIZE, + DEVICE_NVDIMM_ADDRESS(notifCmdReg) ); + if ( errl ) + { + PRDF_ERR( PRDF_FUNC "Failed to clear Set Event Notification " + "Cmd Reg. HUID: 0x%08x", getHuid(i_dimm) ); + PRDF_COMMIT_ERRL( errl, ERRL_ACTION_REPORT ); + o_rc = FAIL; + break; + } + + // Check SET_EVENT_NOTIFICATION_STATUS to ensure everything is set + // as we expect and we don't see any errors. + uint8_t notifStat = 0; + errl = deviceRead( i_dimm, ¬ifStat, NVDIMM_SIZE, + DEVICE_NVDIMM_ADDRESS(notifStatusReg) ); + if ( errl ) + { + PRDF_ERR( PRDF_FUNC "Failed to read Set Event Notification " + "Status Reg. HUID: 0x%08x", getHuid(i_dimm) ); + PRDF_COMMIT_ERRL( errl, ERRL_ACTION_REPORT ); + o_rc = FAIL; + break; + } + std::map<uint8_t,bool> bitList = __nvdimmGetActiveBits( notifStat ); + + // if Bit [1]: SET_EVENT_NOTIFICATION_ERROR = 1 + // or Bit [2]: PERSISTENCY_ENABLED = 0 + // or Bit [3]: WARNING_THRESHOLD_ENABLED = 1 + if ( bitList.count(1) || !bitList.count(2) || bitList.count(3) ) + { + o_statusErr = true; + + // Make the log predictive and mask the fir + io_sc.service_data->SetThresholdMaskId(0); + + // Callout the NVDIMM, no gard + io_sc.service_data->SetCallout( i_dimm, MRU_MED, NO_GARD ); + + // Send message to PHYP that save/restore may work + o_rc = PlatServices::nvdimmNotifyProtChange( i_dimm, + NVDIMM::NVDIMM_RISKY_HW_ERROR ); + if ( SUCCESS != o_rc ) break; + + break; + } + + + // Set the warning threshold to error threshold + 1 + warnTh = errTh+1; + errl = deviceWrite( i_dimm, &warnTh, NVDIMM_SIZE, + DEVICE_NVDIMM_ADDRESS(i_warnThReg) ); + if ( errl ) + { + PRDF_ERR( PRDF_FUNC "Failed to write Warning Threshold Reg. " + "HUID: 0x%08x", getHuid(i_dimm) ); + PRDF_COMMIT_ERRL( errl, ERRL_ACTION_REPORT ); + o_rc = FAIL; + break; + } + + // Set SET_EVENT_NOTIFICATION_CMD bit 1 and keep bit 0 set + notifCmd = 0x03; + errl = deviceWrite( i_dimm, ¬ifCmd, NVDIMM_SIZE, + DEVICE_NVDIMM_ADDRESS(notifCmdReg) ); + if ( errl ) + { + PRDF_ERR( PRDF_FUNC "Failed to write Set Event Notification " + "Cmd Reg. HUID: 0x%08x", getHuid(i_dimm) ); + PRDF_COMMIT_ERRL( errl, ERRL_ACTION_REPORT ); + o_rc = FAIL; + break; + } + + // Recheck SET_EVENT_NOTIFICATION_STATUS to ensure everything is set + // as we expect and we don't see any errors. + errl = deviceRead( i_dimm, ¬ifStat, NVDIMM_SIZE, + DEVICE_NVDIMM_ADDRESS(notifStatusReg) ); + if ( errl ) + { + PRDF_ERR( PRDF_FUNC "Failed to read Set Event Notification " + "Status Reg. HUID: 0x%08x", getHuid(i_dimm) ); + PRDF_COMMIT_ERRL( errl, ERRL_ACTION_REPORT ); + o_rc = FAIL; + break; + } + bitList = __nvdimmGetActiveBits( notifStat ); + + // if Bit [1]: SET_EVENT_NOTIFICATION_ERROR = 1 + // or Bit [2]: PERSISTENCY_ENABLED = 0 + // or Bit [3]: WARNING_THRESHOLD_ENABLED = 0 + if ( bitList.count(1) || !bitList.count(2) || !bitList.count(3) ) + { + o_statusErr = true; + + // Make the log predictive and mask the fir + io_sc.service_data->SetThresholdMaskId(0); + + // Callout the NVDIMM, no gard + io_sc.service_data->SetCallout( i_dimm, MRU_MED, NO_GARD ); + + // Send message to PHYP that save/restore may work + o_rc = PlatServices::nvdimmNotifyProtChange( i_dimm, + NVDIMM::NVDIMM_RISKY_HW_ERROR ); + if ( SUCCESS != o_rc ) break; + + break; + } + } + // Note: moving the threshold should clear the warning from + // WARNING_THRESHOLD_STATUS, which allows future warnings to report. + + }while(0); + + return o_rc; + + #undef PRDF_FUNC +} + +/** + * @brief Analyze NVDIMM Warning Threshold Status Register for errors + * @param io_sc The step code data struct. + * @param i_dimm The target dimm. + * @param io_errFound Whether an error has already been found or not. + * @return FAIL if unable to read register, else SUCCESS + */ +uint32_t __analyzeWarningThrStatusReg(STEP_CODE_DATA_STRUCT & io_sc, + TargetHandle_t i_dimm, bool & io_errFound) +{ + #define PRDF_FUNC "[__analyzeWarningThrStatusReg] " + + uint32_t o_rc = SUCCESS; + uint8_t data = 0; + + // Get MCA, for signatures + TargetHandle_t mca = getConnectedParent( i_dimm, TYPE_MCA ); + + do + { + // NVDIMM health status registers size = 1 byte + size_t NVDIMM_SIZE = 1; + + // Read the Warning Threshold Status Register (0xA7) 7:0 + errlHndl_t errl = deviceRead( i_dimm, &data, NVDIMM_SIZE, + DEVICE_NVDIMM_ADDRESS(NVDIMM::i2cReg::WARNING_THRESHOLD_STATUS) ); + if ( errl ) + { + PRDF_ERR( PRDF_FUNC "Failed to read Warning Threshold Status Reg. " + "HUID: 0x%08x", getHuid(i_dimm) ); + PRDF_COMMIT_ERRL( errl, ERRL_ACTION_REPORT ); + o_rc = FAIL; + break; + } + std::map<uint8_t,bool> bitList = __nvdimmGetActiveBits( data ); + + // Analyze Bit 2 First + // BIT 2: ES_TEMP_WARNING + if ( bitList.count(2) ) + { + // Sleep two seconds to avoid exiting PRD analysis faster than the + // ES_TEMP sample rate. + PlatServices::milliSleep( 2, 0 ); + + // Read the ES_TEMP and ES_TEMP_WARNING_HIGH_THRESHOLD values + uint16_t msbEsTempReg = NVDIMM::i2cReg::ES_TEMP1; + uint16_t lsbEsTempReg = NVDIMM::i2cReg::ES_TEMP0; + uint16_t esTemp = 0; + o_rc = __readTemp( i_dimm, msbEsTempReg, lsbEsTempReg, esTemp ); + if ( SUCCESS != o_rc ) break; + + uint16_t msbThReg = NVDIMM::i2cReg::ES_TEMP_WARNING_HIGH_THRESHOLD1; + uint16_t lsbThReg = NVDIMM::i2cReg::ES_TEMP_WARNING_HIGH_THRESHOLD0; + uint16_t esTempHighTh = 0; + o_rc = __readTemp( i_dimm, msbThReg, lsbThReg, esTempHighTh ); + if ( SUCCESS != o_rc ) break; + + msbThReg = NVDIMM::i2cReg::ES_TEMP_WARNING_LOW_THRESHOLD1; + lsbThReg = NVDIMM::i2cReg::ES_TEMP_WARNING_LOW_THRESHOLD0; + uint16_t esTempLowTh = 0; + o_rc = __readTemp( i_dimm, msbThReg, lsbThReg, esTempLowTh ); + if ( SUCCESS != o_rc ) break; + + // Check to see if the ES_TEMP is negative (bit 12) + bool esTempNeg = false; + if ( esTemp & 0x1000 ) esTempNeg = true; + + // If ES_TEMP is equal or above ES_TEMP_WARNING_HIGH_THRESHOLD + // Just in case ES_TEMP has moved before we read it out, we'll add + // a 2°C margin when comparing to the threshold. + if ( (esTemp >= (esTempHighTh - 0x0020)) && !esTempNeg ) + { + __addSignature( io_sc, mca, io_errFound, + PRDFSIG_EsTmpWarnHigh ); + } + // Else check if the warning hit the low threshold, again with the + // same 2°C margin. + else if ( (esTemp <= (esTempLowTh + 0x0020)) || esTempNeg ) + { + __addSignature( io_sc, mca, io_errFound, + PRDFSIG_EsTmpWarnLow ); + } + // Else the temperature must have gone back to a normal value, so + // we will label this as a false alarm case. + else + { + __addSignature( io_sc, mca, io_errFound, + PRDFSIG_EsTmpWarnFa ); + } + + // Callout BPM (backup power module) high + o_rc = __addBpmCallout( i_dimm, HWAS::SRCI_PRIORITY_HIGH ); + if ( SUCCESS != o_rc ) break; + + // Callout NVDIMM low, no gard + io_sc.service_data->SetCallout( i_dimm, MRU_LOW, NO_GARD ); + + // Because of the possibility of intermittent ES temperature + // false alarm readings, we will keep the log hidden. If there is + // an actual ES temperature problem, we assume we will continue + // to be called to handle the temperature warning and hit threshold. + + // Only send the save/restore message to PHYP if we hit threshold. + if ( io_sc.service_data->IsAtThreshold() ) + { + // Send message to PHYP that save/restore may work + o_rc = PlatServices::nvdimmNotifyProtChange( i_dimm, + NVDIMM::NVDIMM_RISKY_HW_ERROR ); + if ( SUCCESS != o_rc ) break; + } + + io_errFound = true; + } + // BIT 0: NVM_LIFETIME_WARNING + if ( bitList.count(0) ) + { + // Adjust warning threshold. + uint16_t warnThReg = NVDIMM::i2cReg::NVM_LIFETIME_WARNING_THRESHOLD; + uint16_t errThReg = NVDIMM::i2cReg::NVM_LIFETIME_ERROR_THRESHOLD; + bool firstWarn = false; + bool statusErr = false; + o_rc = __adjustThreshold( io_sc, i_dimm, warnThReg, errThReg, + firstWarn, statusErr ); + if ( SUCCESS != o_rc ) break; + + // Make the log predictive, but do not mask the FIR + io_sc.service_data->setServiceCall(); + + // If we got a set event notification status error, add the + // signature for that before adding the signature for the warning. + // Also do not take our normal callout action since we already will + // have called out the NVDIMM because of the status error. + if ( statusErr ) + { + __addSignature( io_sc, mca, io_errFound, PRDFSIG_NotifStatErr ); + + // Need to set io_errFound here so the warning signature is + // added to the multi-signature list instead of as the primary + // signature. + io_errFound = true; + } + else + { + // Callout NVDIMM on 1st, no gard + io_sc.service_data->SetCallout( i_dimm, MRU_MED, NO_GARD ); + } + + // Update signature depending on whether this is the first or second + // warning of this type. + if ( firstWarn ) + { + __addSignature( io_sc, mca, io_errFound, PRDFSIG_NvmLifeWarn1 ); + } + else + { + __addSignature( io_sc, mca, io_errFound, PRDFSIG_NvmLifeWarn2 ); + } + + + io_errFound = true; + } + // BIT 1: ES_LIFETIME_WARNING + if ( bitList.count(1) ) + { + // Adjust warning threshold. + uint16_t warnThReg = NVDIMM::i2cReg::ES_LIFETIME_WARNING_THRESHOLD; + uint16_t errThReg = NVDIMM::i2cReg::ES_LIFETIME_ERROR_THRESHOLD; + bool firstWarn = false; + bool statusErr = false; + o_rc = __adjustThreshold( io_sc, i_dimm, warnThReg, errThReg, + firstWarn, statusErr ); + if ( SUCCESS != o_rc ) break; + + // Make the log predictive, but do not mask the FIR + io_sc.service_data->setServiceCall(); + + // If we got a set event notification status error, add the + // signature for that before adding the signature for the warning. + // Also do not take our normal callout action since we already will + // have called out the NVDIMM because of the status error. + if ( statusErr ) + { + __addSignature( io_sc, mca, io_errFound, PRDFSIG_NotifStatErr ); + + // Need to set io_errFound here so the warning signature is + // added to the multi-signature list instead of as the primary + // signature. + io_errFound = true; + } + else + { + // Callout BPM (backup power module) high + o_rc = __addBpmCallout( i_dimm, HWAS::SRCI_PRIORITY_HIGH ); + if ( SUCCESS != o_rc ) break; + + // Callout NVDIMM low, no gard + io_sc.service_data->SetCallout( i_dimm, MRU_LOW, NO_GARD ); + } + + // Update signature depending on whether this is the first or second + // warning of this type. + if ( firstWarn ) + { + __addSignature(io_sc, mca, io_errFound, PRDFSIG_EsLifeWarn1); + } + else + { + __addSignature(io_sc, mca, io_errFound, PRDFSIG_EsLifeWarn2); + } + + io_errFound = true; + } + + }while(0); + + return o_rc; + + #undef PRDF_FUNC +} + +/** * @brief De-assert the EVENT_N pin by setting bit 2 in NVDIMM_MGT_CMD1 (0x41) * @param i_dimm The target dimm. * @return FAIL if unable to read/write register, else SUCCESS @@ -698,7 +1292,7 @@ uint32_t __deassertEventN( TargetHandle_t i_dimm ) // Read the NVDIMM_MGT_CMD1 register (0x41) 7:0 errlHndl_t errl = deviceRead( i_dimm, &data, NVDIMM_SIZE, - DEVICE_NVDIMM_ADDRESS(NVDIMM_MGT_CMD1) ); + DEVICE_NVDIMM_ADDRESS(NVDIMM::i2cReg::NVDIMM_MGT_CMD1) ); if ( errl ) { PRDF_ERR( PRDF_FUNC "Failed to read NVDIMM_MGT_CMD1. " @@ -713,7 +1307,7 @@ uint32_t __deassertEventN( TargetHandle_t i_dimm ) // Write the updated data back to NVDIMM_MGT_CMD1 errl = deviceWrite( i_dimm, &data, NVDIMM_SIZE, - DEVICE_NVDIMM_ADDRESS(NVDIMM_MGT_CMD1) ); + DEVICE_NVDIMM_ADDRESS(NVDIMM::i2cReg::NVDIMM_MGT_CMD1) ); if ( errl ) { PRDF_ERR( PRDF_FUNC "Failed to write NVDIMM_MGT_CMD1. " @@ -732,6 +1326,7 @@ uint32_t __deassertEventN( TargetHandle_t i_dimm ) } #endif // HOSTBOOT_RUNTIME +#endif // CONFIG_NVDIMM /** * @brief MCACALFIR[8] - Error from NVDIMM health status registers @@ -744,13 +1339,28 @@ int32_t AnalyzeNvdimmHealthStatRegs( ExtensibleChip * i_chip, { #define PRDF_FUNC "[nimbus_mca::AnalyzeNvdimmHealthStatRegs] " + #ifdef CONFIG_NVDIMM #ifdef __HOSTBOOT_RUNTIME uint32_t l_rc = SUCCESS; + bool errFound = false; // We need to check both dimms for errors for ( auto & dimm : getConnected(i_chip->getTrgt(), TYPE_DIMM) ) { + // Skip any non-NVDIMMs + if ( !isNVDIMM(dimm) ) continue; + + // Add SMART-specific, page 4 registers to FFDC + errlHndl_t mainErrl = nullptr; + mainErrl = ServiceGeneratorClass::ThisServiceGenerator().getErrl(); + if ( nullptr == mainErrl ) + { + PRDF_ERR( PRDF_FUNC "Failed to get the global error log." ); + continue; + } + PlatServices::nvdimmAddFfdc( dimm, mainErrl ); + // De-assert the EVENT_N pin by setting bit 2 in NVDIMM_MGT_CMD1 l_rc = __deassertEventN( dimm ); if ( SUCCESS != l_rc ) continue; @@ -762,7 +1372,7 @@ int32_t AnalyzeNvdimmHealthStatRegs( ExtensibleChip * i_chip, // Read the Module Health Register (0xA0) 7:0 errlHndl_t errl = deviceRead( dimm, &data, NVDIMM_SIZE, - DEVICE_NVDIMM_ADDRESS(MODULE_HEALTH) ); + DEVICE_NVDIMM_ADDRESS(NVDIMM::i2cReg::MODULE_HEALTH) ); if ( errl ) { PRDF_ERR( PRDF_FUNC "Failed to read Module Health Register. " @@ -775,6 +1385,30 @@ int32_t AnalyzeNvdimmHealthStatRegs( ExtensibleChip * i_chip, // BIT 0: Persistency Lost if ( bitList.count(0) ) { + // Analyze Health Status0 Reg, Health Status1 Reg, + // and Error Theshold Status Reg + l_rc = __analyzeHealthStatus0Reg( io_sc, dimm, errFound ); + if ( SUCCESS != l_rc ) continue; + l_rc = __analyzeHealthStatus1Reg( io_sc, dimm, errFound ); + if ( SUCCESS != l_rc ) continue; + bool esTempErr = false; + l_rc = __analyzeErrorThrStatusReg(io_sc, dimm, errFound, esTempErr); + if ( SUCCESS != l_rc ) continue; + + // If we hit an ES temperature error and have not yet hit threshold, + // then keep the log hidden. + if ( esTempErr && !io_sc.service_data->IsAtThreshold() ) continue; + + // If we didn't find any error, then keep the log hidden. + if ( !errFound ) + { + io_sc.service_data->setSignature( i_chip->getHuid(), + PRDFSIG_FirEvntGone ); + // Callout NVDIMM + io_sc.service_data->SetCallout( dimm, MRU_MED, NO_GARD ); + continue; + } + // EVENT_N cannot be retriggered on a new PERSISTENCY_LOST_ERROR // if a previous PERSISTENCY_LOST_ERROR still exists. Meaning, we // cannot detect/report multiple errors that happen at different @@ -782,43 +1416,77 @@ int32_t AnalyzeNvdimmHealthStatRegs( ExtensibleChip * i_chip, // and make the log predictive. io_sc.service_data->SetThresholdMaskId(0); - // Send persistency lost message to PHYP - l_rc = PlatServices::nvdimmNotifyPhypProtChange( dimm, - NVDIMM::UNPROTECTED_BECAUSE_ERROR ); + // Send message to PHYP that save/restore may work + l_rc = PlatServices::nvdimmNotifyProtChange( dimm, + NVDIMM::NVDIMM_RISKY_HW_ERROR ); if ( SUCCESS != l_rc ) continue; - // Analyze Health Status0 Reg, Health Status1 Reg, - // and Error Theshold Status Reg - l_rc = __analyzeHealthStatus0Reg( io_sc, dimm ); - if ( SUCCESS != l_rc ) continue; - l_rc = __analyzeHealthStatus1Reg( io_sc, dimm ); - if ( SUCCESS != l_rc ) continue; - l_rc = __analyzeErrorThrStatusReg( io_sc, dimm ); + } + // BIT 1: Warning Threshold Exceeded + else if ( bitList.count(1) ) + { + l_rc = __analyzeWarningThrStatusReg( io_sc, dimm, errFound ); if ( SUCCESS != l_rc ) continue; + + if ( !errFound ) + { + io_sc.service_data->setSignature( i_chip->getHuid(), + PRDFSIG_FirEvntGone ); + // Callout NVDIMM + io_sc.service_data->SetCallout( dimm, MRU_MED, NO_GARD ); + continue; + } } - // BIT 1: Warning Threshold Exceeded -- ignore // BIT 2: Persistency Restored - if ( bitList.count(2) ) + else if ( bitList.count(2) ) { // It would be rare to have an intermittent error that comes and // goes so fast we only see PERSISTENCY_RESTORED and not // PERSISTENCY_LOST_ERROR. Set predictive on threshold of 32 // per day (rule code handles the thresholding), else just keep // as a hidden log. - io_sc.service_data->AddSignatureList( dimm, PRDFSIG_NvdimmPersRes ); + __addSignature( io_sc, i_chip->getTrgt(), errFound, + PRDFSIG_NvdimmPersRes ); + + // Callout NVDIMM + io_sc.service_data->SetCallout( dimm, MRU_MED, NO_GARD ); + } + // BIT 3: Below Warning Threshold + else if ( bitList.count(3) ) + { + // Much like the persistency restored bit above, we don't expect + // to see this, so just make a hidden log. + __addSignature( io_sc, i_chip->getTrgt(), errFound, + PRDFSIG_BelowWarnTh ); + + // Callout NVDIMM + io_sc.service_data->SetCallout( dimm, MRU_MED, NO_GARD ); + } + // BIT 4: Hardware Failure -- ignore - no logic feeding this + // BIT 5: EVENT_N_LOW -- ignore + // BIT 6:7: Unused + + // If we reach a threshold on MCACALFIR[8] of 32 per day, we assume + // some intermittent error must be triggering the FIR that isn't a + // persistency lost error which would cause us to mask. The rule code + // handles the actual thresholding here. + if ( io_sc.service_data->IsAtThreshold() && !errFound ) + { + io_sc.service_data->setSignature( i_chip->getHuid(), + PRDFSIG_IntNvdimmErr ); // callout NVDIMM high, cable high, BPM high, no gard io_sc.service_data->SetCallout( dimm, MRU_HIGH, NO_GARD ); l_rc = __addBpmCallout( dimm, HWAS::SRCI_PRIORITY_HIGH ); if ( SUCCESS != l_rc ) continue; - l_rc = __addNvdimmCableCallout( HWAS::SRCI_PRIORITY_HIGH ); + l_rc = __addNvdimmCableCallout( dimm, HWAS::SRCI_PRIORITY_HIGH ); if ( SUCCESS != l_rc ) continue; - } - // BIT 3: Below Warning Threshold -- ignore - // BIT 4: Hardware Failure -- ignore - // BIT 5: EVENT_N_LOW -- ignore - // BIT 6:7: Unused + // Send message to PHYP that save/restore may work + l_rc = PlatServices::nvdimmNotifyProtChange( dimm, + NVDIMM::NVDIMM_RISKY_HW_ERROR ); + if ( SUCCESS != l_rc ) continue; + } } #else // IPL only @@ -826,7 +1494,14 @@ int32_t AnalyzeNvdimmHealthStatRegs( ExtensibleChip * i_chip, PRDF_ERR( PRDF_FUNC "Unexpected call to analyze NVDIMMs at IPL." ); io_sc.service_data->SetCallout( LEVEL2_SUPPORT, MRU_HIGH, NO_GARD ); - #endif + #endif // end runtime vs IPL check + + #else // CONFIG_NVDIMM not defined + + PRDF_ERR( PRDF_FUNC "CONFIG_NVDIMM not defined." ); + io_sc.service_data->SetCallout( LEVEL2_SUPPORT, MRU_HIGH, NO_GARD ); + + #endif // end CONFIG_NVDIMM check return SUCCESS; // nothing to return to rule code diff --git a/src/usr/diag/prdf/plat/mem/prdfP9Mcbist.C b/src/usr/diag/prdf/plat/mem/prdfP9Mcbist.C index 4a4391c0c..0e11b1a86 100644 --- a/src/usr/diag/prdf/plat/mem/prdfP9Mcbist.C +++ b/src/usr/diag/prdf/plat/mem/prdfP9Mcbist.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -301,9 +301,9 @@ int32_t commandAddrTimeout( ExtensibleChip * i_chip, // was executed. Restarting the command will likely fail with the same // issue. Callout and gard all MCAs in which the command was executed. - std::vector<ExtensibleChip *> mcaList; + ExtensibleChipList mcaList; - if ( SUCCESS != getMcbistMaintPort(i_chip, mcaList) ) + if ( SUCCESS != getMcbistMaintPort<TYPE_MCBIST>(i_chip, mcaList) ) { PRDF_ERR( PRDF_FUNC "getMcbistMaintPort(0x%08x) failed", i_chip->getHuid() ); diff --git a/src/usr/diag/prdf/plat/mem/prdfP9McbistDataBundle.H b/src/usr/diag/prdf/plat/mem/prdfP9McbistDataBundle.H index 4a284253a..44ef77ec7 100644 --- a/src/usr/diag/prdf/plat/mem/prdfP9McbistDataBundle.H +++ b/src/usr/diag/prdf/plat/mem/prdfP9McbistDataBundle.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -36,6 +36,7 @@ // Platform includes #include <prdfMemTdCtlr.H> #include <prdfPlatServices.H> +#include <prdfThresholdUtils.H> namespace PRDF { @@ -81,6 +82,24 @@ class McbistDataBundle : public DataBundle /** The Targeted Diagnostics controller. */ MemTdCtlr<TARGETING::TYPE_MCBIST> * iv_tdCtlr = nullptr; + + public: // instance variables + #ifdef __HOSTBOOT_RUNTIME + + // These are used to limit the number of times a scrub command will stop + // on a UE or CE on a rank. This is to prevent potential flooding of + // maintenance UEs or CEs. The threshold will be 16 per rank for each. + TimeBasedThreshold iv_ueStopCounter = + TimeBasedThreshold( 16, ThresholdResolution::TEN_HOURS ); + TimeBasedThreshold iv_ceStopCounter = + TimeBasedThreshold( 16, ThresholdResolution::TEN_HOURS ); + + // If we stop on a UE or a CE, we will need to store the rank that the + // error is on so that we can clear our respective thresholds if the + // next error we stop on is on a different rank. + MemRank iv_ceUeRank; + + #endif }; /** diff --git a/src/usr/diag/prdf/plat/mem/prdfRestoreDramRepairs.C b/src/usr/diag/prdf/plat/mem/prdfRestoreDramRepairs.C index ef3a143eb..fc389000a 100644 --- a/src/usr/diag/prdf/plat/mem/prdfRestoreDramRepairs.C +++ b/src/usr/diag/prdf/plat/mem/prdfRestoreDramRepairs.C @@ -99,7 +99,7 @@ void commitErrl( errlHndl_t i_errl, TargetHandle_t i_trgt ) template<TARGETING::TYPE T> void __calloutDimm( errlHndl_t & io_errl, TargetHandle_t i_portTrgt, - TargetHandle_t i_dimmTrgt ) + TargetHandle_t i_dimmTrgt, bool i_nvdimmNoGard = false ) { #define PRDF_FUNC "[RDR::__calloutDimm] " @@ -109,9 +109,31 @@ void __calloutDimm( errlHndl_t & io_errl, TargetHandle_t i_portTrgt, PRDF_ASSERT( nullptr != i_dimmTrgt ); PRDF_ASSERT( TYPE_DIMM == getTargetType(i_dimmTrgt) ); - // Callout the DIMM. + HWAS::DeconfigEnum deconfigPolicy = HWAS::DELAYED_DECONFIG; + HWAS::GARD_ErrorType gardPolicy = HWAS::GARD_Predictive; + + #ifdef CONFIG_NVDIMM + // For the "RDR: All repairs used" case, If the DIMM is an NVDIMM, change + // the gard and deconfig options to no gard/deconfig and call + // nvdimmNotifyProtChange to indicate a save/restore may work. + if ( i_nvdimmNoGard ) + { + deconfigPolicy = HWAS::NO_DECONFIG; + gardPolicy = HWAS::GARD_NULL; + + uint32_t l_rc = PlatServices::nvdimmNotifyProtChange( i_dimmTrgt, + NVDIMM::NVDIMM_RISKY_HW_ERROR ); + if ( SUCCESS != l_rc ) + { + PRDF_TRAC( PRDF_FUNC "nvdimmNotifyProtChange(0x%08x) " + "failed.", PlatServices::getHuid(i_dimmTrgt) ); + } + } + #endif + io_errl->addHwCallout( i_dimmTrgt, HWAS::SRCI_PRIORITY_HIGH, - HWAS::DELAYED_DECONFIG, HWAS::GARD_Predictive ); + deconfigPolicy, gardPolicy ); + // Clear the VPD on this DIMM. The DIMM has been garded, but it is possible // the customer will want to ungard the DIMM. Without clearing the VPD, the @@ -120,16 +142,20 @@ void __calloutDimm( errlHndl_t & io_errl, TargetHandle_t i_portTrgt, // customer takes the risk of ungarding the DIMM (that they should replace), // the repairs will need to be rediscovered. - std::vector<MemRank> ranks; - getMasterRanks<T>( i_portTrgt, ranks, getDimmSlct(i_dimmTrgt) ); - - for ( auto & rank : ranks ) + // Do not clear the VPD if we had an NVDIMM that we avoided garding. + if ( !i_nvdimmNoGard ) { - if ( SUCCESS != clearBadDqBitmap(i_portTrgt, rank) ) + std::vector<MemRank> ranks; + getMasterRanks<T>( i_portTrgt, ranks, getDimmSlct(i_dimmTrgt) ); + + for ( auto & rank : ranks ) { - PRDF_ERR( PRDF_FUNC "clearBadDqBitmap(0x%08x,0x%02x) failed", - getHuid(i_portTrgt), rank.getKey() ); - continue; + if ( SUCCESS != clearBadDqBitmap(i_portTrgt, rank) ) + { + PRDF_ERR( PRDF_FUNC "clearBadDqBitmap(0x%08x,0x%02x) failed", + getHuid(i_portTrgt), rank.getKey() ); + continue; + } } } @@ -156,11 +182,7 @@ void commitSoftError( uint32_t i_reasonCode, TargetHandle_t i_trgt, //------------------------------------------------------------------------------ template<TARGETING::TYPE T> -bool processRepairedRanks( TargetHandle_t i_trgt, uint8_t i_repairedRankMask ); - -template<> -bool processRepairedRanks<TYPE_MCA>( TargetHandle_t i_trgt, - uint8_t i_repairedRankMask ) +bool processRepairedRanks( TargetHandle_t i_trgt, uint8_t i_repairedRankMask ) { #define PRDF_FUNC "[processRepairedRanks] " @@ -179,7 +201,7 @@ bool processRepairedRanks<TYPE_MCA>( TargetHandle_t i_trgt, // map value has no significance. std::map<TargetHandle_t, uint32_t> calloutList; - ExtensibleChip * mcaChip = (ExtensibleChip *)systemPtr->GetChip(i_trgt); + ExtensibleChip * chip = (ExtensibleChip *)systemPtr->GetChip(i_trgt); for ( uint8_t r = 0; r < MASTER_RANKS_PER_PORT; ++r ) { @@ -191,20 +213,18 @@ bool processRepairedRanks<TYPE_MCA>( TargetHandle_t i_trgt, MemRank rank ( r ); MemMark cm; - if ( SUCCESS != MarkStore::readChipMark<TYPE_MCA>( mcaChip, rank, - cm ) ) + if ( SUCCESS != MarkStore::readChipMark<T>( chip, rank, cm ) ) { - PRDF_ERR( PRDF_FUNC "readChipMark<TYPE_MCA>(0x%08x,0x%02x) " - "failed", mcaChip->getHuid(), rank.getKey() ); + PRDF_ERR( PRDF_FUNC "readChipMark<T>(0x%08x,0x%02x) " + "failed", chip->getHuid(), rank.getKey() ); continue; // skip this rank } MemMark sm; - if ( SUCCESS != MarkStore::readSymbolMark<TYPE_MCA>( mcaChip, rank, - sm ) ) + if ( SUCCESS != MarkStore::readSymbolMark<T>( chip, rank, sm ) ) { - PRDF_ERR( PRDF_FUNC "readSymbolMark<TYPE_MCA>(0x%08x,0x%02x) " - "failed", mcaChip->getHuid(), rank.getKey() ); + PRDF_ERR( PRDF_FUNC "readSymbolMark<T>(0x%08x,0x%02x) " + "failed", chip->getHuid(), rank.getKey() ); continue; // skip this rank } @@ -214,9 +234,8 @@ bool processRepairedRanks<TYPE_MCA>( TargetHandle_t i_trgt, if ( NULL == errl ) { - errl = createErrl<TYPE_MCA>( PRDF_DETECTED_FAIL_HARDWARE, - i_trgt, - PRDFSIG_RdrRepairsUsed ); + errl = createErrl<T>( PRDF_DETECTED_FAIL_HARDWARE, + i_trgt, PRDFSIG_RdrRepairsUsed ); } std::vector<MemSymbol> symList; @@ -246,16 +265,21 @@ bool processRepairedRanks<TYPE_MCA>( TargetHandle_t i_trgt, // Callout all DIMMs in the map. for ( auto const & dimm : calloutList ) { - __calloutDimm<TYPE_MCA>( errl, i_trgt, dimm.first ); + bool nvdimmNoGard = false; + #ifdef CONFIG_NVDIMM + if ( isNVDIMM(dimm.first) ) nvdimmNoGard = true; + #endif + + __calloutDimm<T>( errl, i_trgt, dimm.first, nvdimmNoGard ); } // Commit the error log, if needed. - commitErrl<TYPE_MCA>( errl, i_trgt ); + commitErrl<T>( errl, i_trgt ); // Commit an additional error log indicating something failed in the // analysis, if needed. - commitSoftError<TYPE_MCA>( PRDF_DETECTED_FAIL_SOFTWARE, i_trgt, - PRDFSIG_RdrInternalFail, analysisErrors ); + commitSoftError<T>( PRDF_DETECTED_FAIL_SOFTWARE, i_trgt, + PRDFSIG_RdrInternalFail, analysisErrors ); }while(0); return o_calloutMade; @@ -263,6 +287,14 @@ bool processRepairedRanks<TYPE_MCA>( TargetHandle_t i_trgt, #undef PRDF_FUNC } + +template +bool processRepairedRanks<TYPE_MCA>( TargetHandle_t i_trgt, + uint8_t i_repairedRankMask ); +template +bool processRepairedRanks<TYPE_OCMB_CHIP>( TargetHandle_t i_trgt, + uint8_t i_repairedRankMask ); + //------------------------------------------------------------------------------ template<> @@ -368,7 +400,12 @@ bool processRepairedRanks<TYPE_MBA>( TargetHandle_t i_trgt, // Callout all DIMMs in the map. for ( auto const & dimm : calloutList ) { - __calloutDimm<TYPE_MBA>( errl, i_trgt, dimm.first ); + bool nvdimmNoGard = false; + #ifdef CONFIG_NVDIMM + if ( isNVDIMM(dimm.first) ) nvdimmNoGard = true; + #endif + + __calloutDimm<TYPE_MBA>(errl, i_trgt, dimm.first, nvdimmNoGard); } o_calloutMade = true; @@ -392,10 +429,7 @@ bool processRepairedRanks<TYPE_MBA>( TargetHandle_t i_trgt, template<TARGETING::TYPE T> -bool processBadDimms( TargetHandle_t i_trgt, uint8_t i_badDimmMask ); - -template<> -bool processBadDimms<TYPE_MCA>( TargetHandle_t i_trgt, uint8_t i_badDimmMask ) +bool processBadDimms( TargetHandle_t i_trgt, uint8_t i_badDimmMask ) { #define PRDF_FUNC "[processBadDimms] " @@ -421,29 +455,35 @@ bool processBadDimms<TYPE_MCA>( TargetHandle_t i_trgt, uint8_t i_badDimmMask ) { if ( NULL == errl ) { - errl = createErrl<TYPE_MCA>( PRDF_DETECTED_FAIL_HARDWARE, - i_trgt, PRDFSIG_RdrRepairUnavail ); + errl = createErrl<T>( PRDF_DETECTED_FAIL_HARDWARE, + i_trgt, PRDFSIG_RdrRepairUnavail ); } - __calloutDimm<TYPE_MCA>( errl, i_trgt, dimm ); + __calloutDimm<T>( errl, i_trgt, dimm ); o_calloutMade = true; } } // Commit the error log, if needed. - commitErrl<TYPE_MCA>( errl, i_trgt ); + commitErrl<T>( errl, i_trgt ); // Commit an additional error log indicating something failed in the // analysis, if needed. - commitSoftError<TYPE_MCA>( PRDF_DETECTED_FAIL_SOFTWARE, i_trgt, - PRDFSIG_RdrInternalFail, analysisErrors ); + commitSoftError<T>( PRDF_DETECTED_FAIL_SOFTWARE, i_trgt, + PRDFSIG_RdrInternalFail, analysisErrors ); return o_calloutMade; #undef PRDF_FUNC } +template +bool processBadDimms<TYPE_MCA>( TargetHandle_t i_trgt, uint8_t i_badDimmMask ); +template +bool processBadDimms<TYPE_OCMB_CHIP>( TargetHandle_t i_trgt, + uint8_t i_badDimmMask ); + //------------------------------------------------------------------------------ template<> @@ -580,6 +620,25 @@ void deployDramSpares<TYPE_MBA>( TargetHandle_t i_trgt, } } +template<> +void deployDramSpares<TYPE_OCMB_CHIP>( TargetHandle_t i_trgt, + const std::vector<MemRank> & i_ranks ) +{ + for ( auto & rank : i_ranks ) + { + MemSymbol sym = MemSymbol::fromSymbol( i_trgt, rank, 71 ); + + int32_t l_rc = mssSetSteerMux<TYPE_OCMB_CHIP>(i_trgt, rank, sym, false); + if ( SUCCESS != l_rc ) + { + // mssSetSteerMux() will print a trace and commit the error log, + // however, we need to handle the return code or we get a compile + // warning in Hostboot. + continue; + } + } +} + } // end namespace RDR //------------------------------------------------------------------------------ @@ -680,6 +739,8 @@ template uint32_t restoreDramRepairs<TYPE_MCA>( TargetHandle_t i_trgt ); template uint32_t restoreDramRepairs<TYPE_MBA>( TargetHandle_t i_trgt ); +template +uint32_t restoreDramRepairs<TYPE_OCMB_CHIP>( TargetHandle_t i_trgt ); //------------------------------------------------------------------------------ diff --git a/src/usr/diag/prdf/plat/prdfPlatServices.C b/src/usr/diag/prdf/plat/prdfPlatServices.C index 8c17c2fd9..0ad247134 100644 --- a/src/usr/diag/prdf/plat/prdfPlatServices.C +++ b/src/usr/diag/prdf/plat/prdfPlatServices.C @@ -40,6 +40,8 @@ #include <prdfRegisterCache.H> #include <prdfCenMbaDataBundle.H> +#include <prdfP9McbistDataBundle.H> +#include <prdfOcmbDataBundle.H> #include <prdfMemScrubUtils.H> #include <iipServiceDataCollector.h> @@ -50,7 +52,7 @@ #include <time.h> #include <initservice/initserviceif.H> #include <devicefw/userif.H> -#include <iipMopRegisterAccess.h> +#include <prdfHomRegisterAccess.H> #include <ibscomreasoncodes.H> #include <scom/scomreasoncodes.H> #include <p9_proc_gettracearray.H> @@ -58,6 +60,13 @@ #include <p9c_mss_maint_cmds.H> #include <prdfParserUtils.H> #include <p9c_mss_rowRepairFuncs.H> +#include <errl/errludlogregister.H> + +#include <hwp_wrappers.H> + +#ifdef CONFIG_NVDIMM +#include <nvdimm.H> +#endif using namespace TARGETING; @@ -387,31 +396,31 @@ uint32_t getMemAddrRange<TYPE_MCA>( ExtensibleChip * i_chip, //------------------------------------------------------------------------------ template<> -uint32_t getMemAddrRange<TYPE_MEM_PORT>( ExtensibleChip * i_chip, - const MemRank & i_rank, - mss::mcbist::address & o_startAddr, - mss::mcbist::address & o_endAddr, - AddrRangeType i_rangeType ) +uint32_t getMemAddrRange<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + const MemRank & i_rank, + mss::mcbist::address & o_startAddr, + mss::mcbist::address & o_endAddr, + AddrRangeType i_rangeType ) { - #define PRDF_FUNC "[PlatServices::getMemAddrRange<TYPE_MEM_PORT>] " + #define PRDF_FUNC "[PlatServices::getMemAddrRange<TYPE_OCMB_CHIP>] " - PRDF_ASSERT( nullptr != i_chip ); - PRDF_ASSERT( TYPE_MEM_PORT == i_chip->getType() ); + #ifdef CONFIG_AXONE - /* TODO RTC 207273 - no HWP support yet - uint32_t port = i_chip->getPos() % MAX_PORT_PER_OCMB; + PRDF_ASSERT( nullptr != i_chip ); + PRDF_ASSERT( TYPE_OCMB_CHIP == i_chip->getType() ); + // TODO RTC 210072 - support for multiple ports if ( SLAVE_RANK == i_rangeType ) { FAPI_CALL_HWP_NORETURN( mss::mcbist::address::get_srank_range, - port, i_rank.getDimmSlct(), + 0, i_rank.getDimmSlct(), i_rank.getRankSlct(), i_rank.getSlave(), o_startAddr, o_endAddr ); } else if ( MASTER_RANK == i_rangeType ) { FAPI_CALL_HWP_NORETURN( mss::mcbist::address::get_mrank_range, - port, i_rank.getDimmSlct(), + 0, i_rank.getDimmSlct(), i_rank.getRankSlct(), o_startAddr, o_endAddr ); } else @@ -419,7 +428,8 @@ uint32_t getMemAddrRange<TYPE_MEM_PORT>( ExtensibleChip * i_chip, PRDF_ERR( PRDF_FUNC "unsupported range type %d", i_rangeType ); PRDF_ASSERT(false); } - */ + + #endif return SUCCESS; @@ -520,15 +530,15 @@ uint32_t getMemAddrRange<TYPE_MCA>( ExtensibleChip * i_chip, //------------------------------------------------------------------------------ template<> -uint32_t getMemAddrRange<TYPE_MEM_PORT>( ExtensibleChip * i_chip, - const MemRank & i_rank, - MemAddr & o_startAddr, - MemAddr & o_endAddr, - AddrRangeType i_rangeType ) +uint32_t getMemAddrRange<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + const MemRank & i_rank, + MemAddr & o_startAddr, + MemAddr & o_endAddr, + AddrRangeType i_rangeType ) { mss::mcbist::address saddr, eaddr; - uint32_t o_rc = getMemAddrRange<TYPE_MEM_PORT>( i_chip, i_rank, saddr, - eaddr, i_rangeType ); + uint32_t o_rc = getMemAddrRange<TYPE_OCMB_CHIP>( i_chip, i_rank, saddr, + eaddr, i_rangeType ); if ( SUCCESS == o_rc ) { o_startAddr = __convertMssMcbistAddr( saddr ); @@ -630,16 +640,16 @@ uint32_t getMemAddrRange<TYPE_MCA>( ExtensibleChip * i_chip, uint8_t i_dimmSlct ); template -uint32_t getMemAddrRange<TYPE_MEM_PORT>( ExtensibleChip * i_chip, - mss::mcbist::address & o_startAddr, - mss::mcbist::address & o_endAddr, - uint8_t i_dimmSlct ); +uint32_t getMemAddrRange<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + mss::mcbist::address & o_startAddr, + mss::mcbist::address & o_endAddr, + uint8_t i_dimmSlct ); template -uint32_t getMemAddrRange<TYPE_MEM_PORT>( ExtensibleChip * i_chip, - MemAddr & o_startAddr, - MemAddr & o_endAddr, - uint8_t i_dimmSlct ); +uint32_t getMemAddrRange<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + MemAddr & o_startAddr, + MemAddr & o_endAddr, + uint8_t i_dimmSlct ); //------------------------------------------------------------------------------ @@ -696,17 +706,16 @@ bool isRowRepairEnabled<TYPE_MCA>( ExtensibleChip * i_chip, } template<> -bool isRowRepairEnabled<TYPE_MEM_PORT>( ExtensibleChip * i_chip, - const MemRank & i_rank ) +bool isRowRepairEnabled<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + const MemRank & i_rank ) { - #define PRDF_FUNC "[PlatServices::isRowRepairEnabled<TYPE_MEM_PORT>] " + #define PRDF_FUNC "[PlatServices::isRowRepairEnabled<TYPE_OCMB_CHIP>] " PRDF_ASSERT( nullptr != i_chip ); - PRDF_ASSERT( TYPE_MEM_PORT == i_chip->getType() ); + PRDF_ASSERT( TYPE_OCMB_CHIP == i_chip->getType() ); bool o_isEnabled = false; - /* TODO RTC 207273 - no HWP support yet do { // Don't do row repair if DRAM repairs is disabled. @@ -732,13 +741,110 @@ bool isRowRepairEnabled<TYPE_MEM_PORT>( ExtensibleChip * i_chip, } }while(0); - */ return o_isEnabled; #undef PRDF_FUNC } +//------------------------------------------------------------------------------ + +#ifdef CONFIG_NVDIMM +uint32_t nvdimmNotifyProtChange( TARGETING::TargetHandle_t i_target, + const NVDIMM::nvdimm_protection_t i_state ) +{ + #define PRDF_FUNC "[PlatServices::nvdimmNotifyProtChange] " + + uint32_t o_rc = SUCCESS; + + errlHndl_t errl = NVDIMM::notifyNvdimmProtectionChange( i_target, i_state ); + if ( nullptr != errl ) + { + PRDF_ERR( PRDF_FUNC "NVDIMM::notifyNvdimmProtectionChange(0x%08x) " + "failed.", getHuid(i_target) ); + PRDF_COMMIT_ERRL( errl, ERRL_ACTION_REPORT ); + o_rc = FAIL; + } + + return o_rc; + + #undef PRDF_FUNC + +} + +void nvdimmAddFfdc( TARGETING::TargetHandle_t i_nvdimm, errlHndl_t & io_errl ) +{ + #define PRDF_FUNC "[PlatServices::nvdimmAddFfdc] " + // Add Page 4 Regs and Vendor Log using external Hostboot interfaces. + NVDIMM::nvdimmAddPage4Regs( i_nvdimm, io_errl ); + NVDIMM::nvdimmAddVendorLog( i_nvdimm, io_errl ); + + // Add PRD specific registers relevant to runtime NVDIMM analysis. + const uint16_t regList[] = + { + // Module health registers + NVDIMM::i2cReg::MODULE_HEALTH, + NVDIMM::i2cReg::MODULE_HEALTH_STATUS0, + NVDIMM::i2cReg::MODULE_HEALTH_STATUS1, + + // Threshold status registers + NVDIMM::i2cReg::ERROR_THRESHOLD_STATUS, + NVDIMM::i2cReg::WARNING_THRESHOLD_STATUS, + + // ES_TEMP registers + NVDIMM::i2cReg::ES_TEMP0, + NVDIMM::i2cReg::ES_TEMP1, + NVDIMM::i2cReg::ES_TEMP_WARNING_HIGH_THRESHOLD0, + NVDIMM::i2cReg::ES_TEMP_WARNING_HIGH_THRESHOLD1, + NVDIMM::i2cReg::ES_TEMP_WARNING_LOW_THRESHOLD0, + NVDIMM::i2cReg::ES_TEMP_WARNING_LOW_THRESHOLD1, + + // NVM Lifetime registers + NVDIMM::i2cReg::NVM_LIFETIME, + NVDIMM::i2cReg::NVM_LIFETIME_ERROR_THRESHOLD, + NVDIMM::i2cReg::NVM_LIFETIME_WARNING_THRESHOLD, + + // ES Lifetime registers + NVDIMM::i2cReg::ES_LIFETIME, + NVDIMM::i2cReg::ES_LIFETIME_ERROR_THRESHOLD, + NVDIMM::i2cReg::ES_LIFETIME_WARNING_THRESHOLD, + + // Status registers + NVDIMM::i2cReg::ERASE_STATUS, + NVDIMM::i2cReg::ARM_STATUS, + NVDIMM::i2cReg::SET_EVENT_NOTIFICATION_STATUS, + }; + + ERRORLOG::ErrlUserDetailsLogRegister regUd( i_nvdimm ); + for ( auto const & reg : regList ) + { + // NVDIMM register size = 1 byte + size_t NVDIMM_SIZE = 1; + + uint8_t data = 0; + errlHndl_t errl = deviceRead( i_nvdimm, &data, NVDIMM_SIZE, + DEVICE_NVDIMM_ADDRESS(reg) ); + if ( errl ) + { + PRDF_ERR( PRDF_FUNC "Failed to read register 0x%X on " + "NVDIMM HUID: 0x%08x", reg, getHuid(i_nvdimm) ); + // Don't commit, just delete the error and continue + delete errl; errl = nullptr; + continue; + } + // Only add registers that have non-zero data. + if ( 0 == data ) continue; + + regUd.addDataBuffer( &data, sizeof(data), DEVICE_NVDIMM_ADDRESS(reg) ); + } + + regUd.addToLog( io_errl ); + + #undef PRDF_FUNC +} + +#endif + //############################################################################## //## Nimbus Maintenance Command wrappers //############################################################################## @@ -758,10 +864,16 @@ uint32_t startBgScrub<TYPE_MCA>( ExtensibleChip * i_mcaChip, ExtensibleChip * mcbChip = getConnectedParent( i_mcaChip, TYPE_MCBIST ); fapi2::Target<fapi2::TARGET_TYPE_MCBIST> fapiTrgt ( mcbChip->getTrgt() ); + #ifdef __HOSTBOOT_RUNTIME + // Starting a new command. Clear the UE and CE scrub stop counters + getMcbistDataBundle( mcbChip )->iv_ueStopCounter.reset(); + getMcbistDataBundle( mcbChip )->iv_ceStopCounter.reset(); + #endif + // Get the stop conditions. // NOTE: If HBRT_PRD is not configured, we want to use the defaults so that // background scrubbing never stops. - mss::mcbist::stop_conditions stopCond; + mss::mcbist::stop_conditions<> stopCond; // AUEs are checkstop attentions. Unfortunately, MCBIST commands do not stop // when the system checkstops. Therefore, we must set the stop condition for @@ -851,11 +963,11 @@ uint32_t startBgScrub<TYPE_MCBIST>( ExtensibleChip * i_mcaChip, //------------------------------------------------------------------------------ +#ifndef CONFIG_AXONE template<> uint32_t startTdScrub<TYPE_MCA>( ExtensibleChip * i_chip, - const MemRank & i_rank, - AddrRangeType i_rangeType, - mss::mcbist::stop_conditions i_stopCond ) + const MemRank & i_rank, AddrRangeType i_rangeType, + mss::mcbist::stop_conditions<mss::mc_type::NIMBUS> i_stopCond ) { #define PRDF_FUNC "[PlatServices::startTdScrub<TYPE_MCA>] " @@ -912,6 +1024,7 @@ uint32_t startTdScrub<TYPE_MCA>( ExtensibleChip * i_chip, #undef PRDF_FUNC } +#endif //############################################################################## //## Centaur Maintenance Command wrappers @@ -1316,25 +1429,31 @@ uint32_t incMaintAddr<TYPE_MBA>( ExtensibleChip * i_chip, //############################################################################## template<> -uint32_t startBgScrub<TYPE_MEM_PORT>( ExtensibleChip * i_memPort, - const MemRank & i_rank ) +uint32_t startBgScrub<TYPE_OCMB_CHIP>( ExtensibleChip * i_ocmb, + const MemRank & i_rank ) { - #define PRDF_FUNC "[PlatServices::startBgScrub<TYPE_MEM_PORT>] " + #define PRDF_FUNC "[PlatServices::startBgScrub<TYPE_OCMB_CHIP>] " - PRDF_ASSERT( nullptr != i_memPort ); - PRDF_ASSERT( TYPE_MEM_PORT == i_memPort->getType() ); + PRDF_ASSERT( nullptr != i_ocmb ); + PRDF_ASSERT( TYPE_OCMB_CHIP == i_ocmb->getType() ); uint32_t o_rc = SUCCESS; - /* TODO RTC 207273 - no HWP support yet + #ifdef CONFIG_AXONE + // Get the OCMB fapi target - ExtensibleChip * ocmbChip = getConnectedParent( i_memPort, TYPE_OCMB_CHIP ); - fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> fapiTrgt (ocmbChip->getTrgt()); + fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> fapiTrgt (i_ocmb->getTrgt()); + + #ifdef __HOSTBOOT_RUNTIME + // Starting a new command. Clear the UE and CE scrub stop counters + getOcmbDataBundle( i_ocmb )->iv_ueStopCounter.reset(); + getOcmbDataBundle( i_ocmb )->iv_ceStopCounter.reset(); + #endif // Get the stop conditions. // NOTE: If HBRT_PRD is not configured, we want to use the defaults so that // background scrubbing never stops. - mss::mcbist::stop_conditions stopCond; + mss::mcbist::stop_conditions<mss::mc_type::EXPLORER> stopCond; // AUEs are checkstop attentions. Unfortunately, MCBIST commands do not stop // when the system checkstops. Therefore, we must set the stop condition for @@ -1373,40 +1492,40 @@ uint32_t startBgScrub<TYPE_MEM_PORT>( ExtensibleChip * i_memPort, { // Get the first address of the given rank. mss::mcbist::address saddr, eaddr; - o_rc = getMemAddrRange<TYPE_MEM_PORT>( i_memPort, i_rank, saddr, eaddr, - SLAVE_RANK ); + o_rc = getMemAddrRange<TYPE_OCMB_CHIP>( i_ocmb, i_rank, saddr, eaddr, + SLAVE_RANK ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "getMemAddrRange(0x%08x,0x%2x) failed", - i_memPort->getHuid(), i_rank.getKey() ); + i_ocmb->getHuid(), i_rank.getKey() ); break; } // Clear all of the counters and maintenance ECC attentions. - o_rc = prepareNextCmd<TYPE_OCMB_CHIP>( ocmbChip ); + o_rc = prepareNextCmd<TYPE_OCMB_CHIP>( i_ocmb ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "prepareNextCmd(0x%08x) failed", - ocmbChip->getHuid() ); + i_ocmb->getHuid() ); break; } // Start the background scrub command. errlHndl_t errl = nullptr; - FAPI_INVOKE_HWP( errl, mss::memdiags::background_scrub, fapiTrgt, + FAPI_INVOKE_HWP( errl, exp_background_scrub, fapiTrgt, stopCond, scrubSpeed, saddr ); if ( nullptr != errl ) { - PRDF_ERR( PRDF_FUNC "mss::memdiags::background_scrub(0x%08x,%d) " - "failed", ocmbChip->getHuid(), i_rank.getMaster() ); + PRDF_ERR( PRDF_FUNC "exp_background_scrub(0x%08x,%d) " + "failed", i_ocmb->getHuid(), i_rank.getMaster() ); PRDF_COMMIT_ERRL( errl, ERRL_ACTION_REPORT ); o_rc = FAIL; break; } } while (0); + #endif - */ return o_rc; #undef PRDF_FUNC @@ -1414,31 +1533,19 @@ uint32_t startBgScrub<TYPE_MEM_PORT>( ExtensibleChip * i_memPort, //------------------------------------------------------------------------------ -// This specialization only exists to avoid a lot of extra code in some classes. -// The input chip must still be a MEM_PORT. -template<> -uint32_t startBgScrub<TYPE_OCMB_CHIP>( ExtensibleChip * i_memPort, - const MemRank & i_rank ) -{ - return startBgScrub<TYPE_MEM_PORT>( i_memPort, i_rank ); -} - -//------------------------------------------------------------------------------ - +#ifdef CONFIG_AXONE template<> -uint32_t startTdScrub<TYPE_MEM_PORT>( ExtensibleChip * i_chip, - const MemRank & i_rank, - AddrRangeType i_rangeType, - mss::mcbist::stop_conditions i_stopCond ) +uint32_t startTdScrub<TYPE_OCMB_CHIP>(ExtensibleChip * i_chip, + const MemRank & i_rank, AddrRangeType i_rangeType, + mss::mcbist::stop_conditions<mss::mc_type::EXPLORER> i_stopCond) { - #define PRDF_FUNC "[PlatServices::startTdScrub<TYPE_MEM_PORT>] " + #define PRDF_FUNC "[PlatServices::startTdScrub<TYPE_OCMB_CHIP>] " PRDF_ASSERT( nullptr != i_chip ); - PRDF_ASSERT( TYPE_MEM_PORT == i_chip->getType() ); + PRDF_ASSERT( TYPE_OCMB_CHIP == i_chip->getType() ); uint32_t o_rc = SUCCESS; - /* TODO RTC 207273 - no HWP support yet // Set stop-on-AUE for all target scrubs. See explanation in startBgScrub() // for the reasons why. i_stopCond.set_pause_on_aue(mss::ON); @@ -1447,8 +1554,8 @@ uint32_t startTdScrub<TYPE_MEM_PORT>( ExtensibleChip * i_chip, { // Get the address range of the given rank. mss::mcbist::address saddr, eaddr; - o_rc = getMemAddrRange<TYPE_MEM_PORT>( i_chip, i_rank, saddr, eaddr, - i_rangeType ); + o_rc = getMemAddrRange<TYPE_OCMB_CHIP>( i_chip, i_rank, saddr, eaddr, + i_rangeType ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "getMemAddrRange(0x%08x,0x%2x) failed", @@ -1457,12 +1564,10 @@ uint32_t startTdScrub<TYPE_MEM_PORT>( ExtensibleChip * i_chip, } // Get the OCMB_CHIP fapi target. - ExtensibleChip * ocmbChip = getConnectedParent(i_chip, TYPE_OCMB_CHIP); - fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> - fapiTrgt(ocmbChip->getTrgt()); + fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> fapiTrgt(i_chip->getTrgt()); // Clear all of the counters and maintenance ECC attentions. - o_rc = prepareNextCmd<TYPE_OCMB_CHIP>( ocmbChip ); + o_rc = prepareNextCmd<TYPE_OCMB_CHIP>( i_chip ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "prepareNextCmd(0x%08x) failed", @@ -1472,23 +1577,23 @@ uint32_t startTdScrub<TYPE_MEM_PORT>( ExtensibleChip * i_chip, // Start targeted scrub command. errlHndl_t errl = nullptr; - FAPI_INVOKE_HWP( errl, mss::memdiags::targeted_scrub, fapiTrgt, + FAPI_INVOKE_HWP( errl, exp_targeted_scrub, fapiTrgt, i_stopCond, saddr, eaddr, mss::mcbist::NONE ); if ( nullptr != errl ) { - PRDF_ERR( PRDF_FUNC "mss::memdiags::targeted_scrub(0x%08x,0x%02x) " - "failed", ocmbChip->getHuid(), i_rank.getKey() ); + PRDF_ERR( PRDF_FUNC "exp_targeted_scrub(0x%08x,0x%02x) " + "failed", i_chip->getHuid(), i_rank.getKey() ); PRDF_COMMIT_ERRL( errl, ERRL_ACTION_REPORT ); o_rc = FAIL; break; } } while (0); - */ return o_rc; #undef PRDF_FUNC } +#endif //############################################################################## //## Core/cache trace array functions diff --git a/src/usr/diag/prdf/plat/prdfPlatServices.H b/src/usr/diag/prdf/plat/prdfPlatServices.H index e1710119c..b99c20bed 100644 --- a/src/usr/diag/prdf/plat/prdfPlatServices.H +++ b/src/usr/diag/prdf/plat/prdfPlatServices.H @@ -53,6 +53,10 @@ #include <prdfBitString.H> #include <mem/prdfMemRank.H> +#ifdef CONFIG_NVDIMM +#include <isteps/nvdimm/nvdimm.H> +#endif + //------------------------------------------------------------------------------ namespace PRDF @@ -169,6 +173,26 @@ uint32_t getMemAddrRange( ExtensibleChip * i_chip, template<TARGETING::TYPE T> bool isRowRepairEnabled( ExtensibleChip * i_chip, const MemRank & i_rank ); +#ifdef CONFIG_NVDIMM +/** + * @brief Notify PHYP/Hostboot of NVDIMM protection status + * + * @param i_target Processor with NVDIMM + * @param i_state Protection state of NVDIMM + */ +uint32_t nvdimmNotifyProtChange( TARGETING::TargetHandle_t i_target, + const NVDIMM::nvdimm_protection_t i_state ); + +/** + * @brief Add SMART-specific, page 4 NVDIMM registers to the FFDC + * + * @param i_nvdimm An nvdimm target + * @param io_errl Error log to add the FFDC to + */ +void nvdimmAddFfdc( TARGETING::TargetHandle_t i_nvdimm, errlHndl_t & io_errl ); + +#endif + //############################################################################## //## Nimbus/Centaur Maintenance Command wrappers //############################################################################## diff --git a/src/usr/diag/prdf/plat/prdfPlatServices_ipl.C b/src/usr/diag/prdf/plat/prdfPlatServices_ipl.C index 21cea0c85..14d1c26ba 100644 --- a/src/usr/diag/prdf/plat/prdfPlatServices_ipl.C +++ b/src/usr/diag/prdf/plat/prdfPlatServices_ipl.C @@ -43,7 +43,8 @@ #include <prdfMfgThresholdMgr.H> #include <diag/mdia/mdia.H> -#include <config.h> + +#include <hwp_wrappers.H> using namespace TARGETING; @@ -211,19 +212,19 @@ uint32_t mssRestoreDramRepairs<TYPE_MBA>( TargetHandle_t i_target, //------------------------------------------------------------------------------ template<> -uint32_t mssRestoreDramRepairs<TYPE_MEM_PORT>( TargetHandle_t i_target, - uint8_t & o_repairedRankMask, - uint8_t & o_badDimmMask ) +uint32_t mssRestoreDramRepairs<TYPE_OCMB_CHIP>( TargetHandle_t i_target, + uint8_t & o_repairedRankMask, + uint8_t & o_badDimmMask ) { uint32_t o_rc = SUCCESS; - /* TODO RTC 207273 - no HWP support yet + /* TODO RTC 199032 - no HWP support yet errlHndl_t errl = NULL; fapi2::buffer<uint8_t> tmpRepairedRankMask, tmpBadDimmMask; FAPI_INVOKE_HWP( errl, mss::restore_repairs, - fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>( i_target ), + fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>( i_target ), tmpRepairedRankMask, tmpBadDimmMask ); if ( NULL != errl ) @@ -315,7 +316,7 @@ uint32_t startSfRead<TYPE_MCA>( ExtensibleChip * i_mcaChip, fapi2::Target<fapi2::TARGET_TYPE_MCBIST> fapiTrgt ( mcbChip->getTrgt() ); // Get the stop conditions. - mss::mcbist::stop_conditions stopCond; + mss::mcbist::stop_conditions<> stopCond; stopCond.set_pause_on_mpe(mss::ON) .set_pause_on_ue(mss::ON) .set_pause_on_aue(mss::ON) @@ -843,41 +844,43 @@ uint32_t resumeTdSteerCleanup<TYPE_MBA>( ExtensibleChip * i_chip, template<> bool isBroadcastModeCapable<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip ) { - /* TODO RTC 207273 - no HWP support yet PRDF_ASSERT( nullptr != i_chip ); PRDF_ASSERT( TYPE_OCMB_CHIP == i_chip->getType() ); + mss::states l_ret = mss::states::NO; + + #ifdef CONFIG_AXONE + fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> fapiTrgt ( i_chip->getTrgt() ); + FAPI_CALL_HWP( l_ret, exp_is_broadcast_capable, fapiTrgt ); + + #endif - mss::states l_ret = mss::states::NO; - FAPI_CALL_HWP( l_ret, mss::mcbist::is_broadcast_capable, fapiTrgt ); return ( mss::states::YES == l_ret ); - */ - return false; } //------------------------------------------------------------------------------ template<> -uint32_t startSfRead<TYPE_MEM_PORT>( ExtensibleChip * i_memPort, - const MemRank & i_rank ) +uint32_t startSfRead<TYPE_OCMB_CHIP>( ExtensibleChip * i_ocmb, + const MemRank & i_rank ) { - #define PRDF_FUNC "[PlatServices::startSfRead<TYPE_MCA>] " + #define PRDF_FUNC "[PlatServices::startSfRead<TYPE_OCMB_CHIP>] " PRDF_ASSERT( isInMdiaMode() ); // MDIA must be running. - PRDF_ASSERT( nullptr != i_memPort ); - PRDF_ASSERT( TYPE_MEM_PORT == i_memPort->getType() ); + PRDF_ASSERT( nullptr != i_ocmb ); + PRDF_ASSERT( TYPE_OCMB_CHIP == i_ocmb->getType() ); uint32_t o_rc = SUCCESS; - /* TODO RTC 207273 - no HWP support yet + #ifdef CONFIG_AXONE + // Get the OCMB_CHIP fapi target - ExtensibleChip * ocmbChip = getConnectedParent( i_memPort, TYPE_OCMB_CHIP ); - fapi2::Target<fapi2::TYPE_OCMB_CHIP> fapiTrgt ( ocmbChip->getTrgt() ); + fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> fapiTrgt ( i_ocmb->getTrgt() ); // Get the stop conditions. - mss::mcbist::stop_conditions stopCond; + mss::mcbist::stop_conditions<mss::mc_type::EXPLORER> stopCond; stopCond.set_pause_on_mpe(mss::ON) .set_pause_on_ue(mss::ON) .set_pause_on_aue(mss::ON) @@ -892,39 +895,39 @@ uint32_t startSfRead<TYPE_MEM_PORT>( ExtensibleChip * i_memPort, { // Get the first address of the given rank. mss::mcbist::address saddr, eaddr; - o_rc = getMemAddrRange<TYPE_MEM_PORT>( i_memPort, i_rank, saddr, eaddr, - SLAVE_RANK ); + o_rc = getMemAddrRange<TYPE_OCMB_CHIP>( i_ocmb, i_rank, saddr, eaddr, + SLAVE_RANK ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "getMemAddrRange(0x%08x,0x%2x) failed", - i_memPort->getHuid(), i_rank.getKey() ); + i_ocmb->getHuid(), i_rank.getKey() ); break; } // Clear all of the counters and maintenance ECC attentions. - o_rc = prepareNextCmd<TYPE_OCMB_CHIP>( ocmbChip ); + o_rc = prepareNextCmd<TYPE_OCMB_CHIP>( i_ocmb ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "prepareNextCmd(0x%08x) failed", - ocmbChip->getHuid() ); + i_ocmb->getHuid() ); break; } // Start the super fast read command. errlHndl_t errl; - FAPI_INVOKE_HWP( errl, mss::memdiags::sf_read, fapiTrgt, stopCond, + FAPI_INVOKE_HWP( errl, exp_sf_read, fapiTrgt, stopCond, saddr ); if ( nullptr != errl ) { - PRDF_ERR( PRDF_FUNC "mss::memdiags::sf_read(0x%08x,%d) failed", - ocmbChip->getHuid(), i_rank.getMaster() ); + PRDF_ERR( PRDF_FUNC "exp_sf_read(0x%08x,%d) failed", + i_ocmb->getHuid(), i_rank.getMaster() ); PRDF_COMMIT_ERRL( errl, ERRL_ACTION_REPORT ); o_rc = FAIL; break; } } while (0); - */ + #endif return o_rc; @@ -933,22 +936,154 @@ uint32_t startSfRead<TYPE_MEM_PORT>( ExtensibleChip * i_memPort, //------------------------------------------------------------------------------ -// This specialization only exists to avoid a lot of extra code in some classes. -// The input chip must still be an MEM_PORT chip. template<> -uint32_t startSfRead<TYPE_OCMB_CHIP>( ExtensibleChip * i_memPort, - const MemRank & i_rank ) +uint32_t cleanupSfRead<TYPE_OCMB_CHIP>( ExtensibleChip * i_ocmbChip ) { - return startSfRead<TYPE_MEM_PORT>( i_memPort, i_rank ); + return SUCCESS; // Not needed for MCBIST commands. } //------------------------------------------------------------------------------ +#ifdef CONFIG_AXONE + template<> -uint32_t cleanupSfRead<TYPE_OCMB_CHIP>( ExtensibleChip * i_ocmbChip ) +uint32_t startTdSteerCleanup<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + const MemRank & i_rank, AddrRangeType i_rangeType, + mss::mcbist::stop_conditions<mss::mc_type::EXPLORER> i_stopCond ) { - return SUCCESS; // Not needed for MCBIST commands. + #define PRDF_FUNC "[PlatServices::startTdSteerCleanup<TYPE_OCMB_CHIP>] " + + PRDF_ASSERT( isInMdiaMode() ); // MDIA must be running. + + PRDF_ASSERT( nullptr != i_chip ); + PRDF_ASSERT( TYPE_OCMB_CHIP == i_chip->getType() ); + + uint32_t o_rc = SUCCESS; + + // Default speed is to run as fast as possible. + //mss_MaintCmd::TimeBaseSpeed cmdSpeed = mss_MaintCmd::FAST_MAX_BW_IMPACT; + + // Set stop-on-AUE for all target scrubs. See explanation in startBgScrub() + // for the reasons why. + i_stopCond.set_pause_on_aue(mss::ON); + + do + { + // Get the address range of the given rank. + mss::mcbist::address saddr, eaddr; + o_rc = getMemAddrRange<TYPE_OCMB_CHIP>( i_chip, i_rank, saddr, eaddr, + i_rangeType ); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "getMemAddrRange(0x%08x,0x%2x) failed", + i_chip->getHuid(), i_rank.getKey() ); + break; + } + + // Clear all of the counters and maintenance ECC attentions. + o_rc = prepareNextCmd<TYPE_OCMB_CHIP>( i_chip ); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "prepareNextCmd(0x%08x) failed", + i_chip->getHuid() ); + break; + } + + /* TODO RTC 199032 - sparing support + // Get the MBA fapi target. + fapi2::Target<fapi2::TARGET_TYPE_MBA> fapiTrgt ( i_chip->getTrgt() ); + + // Start the steer cleanup command. + mss_TimeBaseSteerCleanup cmd { fapiTrgt, saddr, eaddr, cmdSpeed, + i_stopCond, false }; + errlHndl_t errl = nullptr; + FAPI_INVOKE_HWP( errl, cmd.setupAndExecuteCmd ); + if ( nullptr != errl ) + { + PRDF_ERR( PRDF_FUNC "setupAndExecuteCmd() on 0x%08x,0x%02x failed", + i_chip->getHuid(), i_rank.getKey() ); + PRDF_COMMIT_ERRL( errl, ERRL_ACTION_REPORT ); + o_rc = FAIL; break; + } + */ + + } while (0); + + return o_rc; + + #undef PRDF_FUNC } + +#endif + +//------------------------------------------------------------------------------ + +#ifdef CONFIG_AXONE + +template<> +uint32_t startTdSfRead<TYPE_OCMB_CHIP>(ExtensibleChip * i_chip, + const MemRank & i_rank, AddrRangeType i_rangeType, + mss::mcbist::stop_conditions<mss::mc_type::EXPLORER> i_stopCond) +{ + #define PRDF_FUNC "[PlatServices::startTdSfRead<TYPE_OCMB_CHIP>] " + + PRDF_ASSERT( isInMdiaMode() ); // MDIA must be running. + + PRDF_ASSERT( nullptr != i_chip ); + PRDF_ASSERT( TYPE_OCMB_CHIP == i_chip->getType() ); + + uint32_t o_rc = SUCCESS; + + // Set stop-on-AUE for all target scrubs. See explanation in startBgScrub() + // for the reasons why. + i_stopCond.set_pause_on_aue(mss::ON); + + do + { + // Get the address range of the given rank. + mss::mcbist::address saddr, eaddr; + o_rc = getMemAddrRange<TYPE_OCMB_CHIP>( i_chip, i_rank, saddr, eaddr, + i_rangeType ); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "getMemAddrRange(0x%08x,0x%2x) failed", + i_chip->getHuid(), i_rank.getKey() ); + break; + } + + // Clear all of the counters and maintenance ECC attentions. + o_rc = prepareNextCmd<TYPE_OCMB_CHIP>( i_chip ); + if ( SUCCESS != o_rc ) + { + PRDF_ERR( PRDF_FUNC "prepareNextCmd(0x%08x) failed", + i_chip->getHuid() ); + break; + } + + // Get the OCMB fapi target. + fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> + fapiTrgt( i_chip->getTrgt() ); + + // Start the super fast read command. + errlHndl_t errl; + FAPI_INVOKE_HWP( errl, exp_sf_read, fapiTrgt, i_stopCond, saddr ); + if ( nullptr != errl ) + { + PRDF_ERR( PRDF_FUNC "exp_sf_read(0x%08x,%d) failed", + i_chip->getHuid(), i_rank.getMaster() ); + PRDF_COMMIT_ERRL( errl, ERRL_ACTION_REPORT ); + o_rc = FAIL; break; + } + + } while (0); + + return o_rc; + + #undef PRDF_FUNC +} + +#endif + //------------------------------------------------------------------------------ } // end namespace PlatServices diff --git a/src/usr/diag/prdf/plat/prdfPlatServices_ipl.H b/src/usr/diag/prdf/plat/prdfPlatServices_ipl.H index a27f1b92e..c12cf5a51 100644 --- a/src/usr/diag/prdf/plat/prdfPlatServices_ipl.H +++ b/src/usr/diag/prdf/plat/prdfPlatServices_ipl.H @@ -66,7 +66,7 @@ int32_t mdiaSendEventMsg( TARGETING::TargetHandle_t i_trgt, /** * @brief Initiates a reconfig loop due to an RCD parity error. - * @param i_trgt An MCA or MEM_PORT target. + * @param i_trgt An MCA target. * @return True if the number of allowed reconfig loops has been exceeded. * False otherwise. */ @@ -113,7 +113,7 @@ bool isBroadcastModeCapable( ExtensibleChip * i_chip ); /** * @brief Starts a super fast read command from the first address of the given * rank to the end of memory. - * @param i_chip MCBIST/MCA, MBA, or MEM_PORT chip. + * @param i_chip MCBIST/MCA, MBA, or OCMB chip. * @param i_rank Will start the command on the first address of this slave * rank. To ensure the command is started on a master rank boundary, * make sure the slave rank value is 0. diff --git a/src/usr/diag/prdf/plat/prdfPlatServices_rt.C b/src/usr/diag/prdf/plat/prdfPlatServices_rt.C index 25a470f8d..0fbe5b969 100644 --- a/src/usr/diag/prdf/plat/prdfPlatServices_rt.C +++ b/src/usr/diag/prdf/plat/prdfPlatServices_rt.C @@ -37,6 +37,8 @@ // Platform includes #include <prdfCenMbaDataBundle.H> +#include <prdfP9McbistDataBundle.H> +#include <prdfOcmbDataBundle.H> #include <prdfMemScrubUtils.H> #include <prdfPlatServices.H> @@ -51,6 +53,8 @@ #include <p9_stop_api.H> #include <rt_todintf.H> +#include <hwp_wrappers.H> + //------------------------------------------------------------------------------ using namespace TARGETING; @@ -105,28 +109,6 @@ void sendPredDeallocRequest( uint64_t i_saddr, uint64_t i_eaddr ) __dyndealloc( i_saddr, i_eaddr, MEMORY_ERROR_PREDICTIVE ); } -uint32_t nvdimmNotifyPhypProtChange( TARGETING::TargetHandle_t i_target, - const NVDIMM::nvdimm_protection_t i_state ) -{ - #define PRDF_FUNC "[PlatServices::nvdimmNotifyPhypProtChange] " - - uint32_t o_rc = SUCCESS; - - errlHndl_t errl = NVDIMM::notifyNvdimmProtectionChange( i_target, i_state ); - if ( nullptr != errl ) - { - PRDF_ERR( PRDF_FUNC "NVDIMM::notifyNvdimmProtectionChange(0x%08x) " - "failed.", getHuid(i_target) ); - PRDF_COMMIT_ERRL( errl, ERRL_ACTION_REPORT ); - o_rc = FAIL; - } - - return o_rc; - - #undef PRDF_FUNC - -} - //############################################################################## //## Nimbus Maintenance Command wrappers //############################################################################## @@ -172,7 +154,8 @@ uint32_t stopBgScrub<TYPE_MCA>( ExtensibleChip * i_chip ) //------------------------------------------------------------------------------ template<> -uint32_t resumeBgScrub<TYPE_MCBIST>( ExtensibleChip * i_chip ) +uint32_t resumeBgScrub<TYPE_MCBIST>( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ) { #define PRDF_FUNC "[PlatServices::resumeBgScrub<TYPE_MCBIST>] " @@ -195,9 +178,42 @@ uint32_t resumeBgScrub<TYPE_MCBIST>( ExtensibleChip * i_chip ) break; } + // Check UE and CE stop counters to determine stop conditions + mss::mcbist::stop_conditions<> stopCond; + if ( getMcbistDataBundle(i_chip)->iv_ueStopCounter.thReached(io_sc) ) + { + // If we've reached the limit of UEs we're allowed to stop on + // per rank, only set the stop on mpe stop condition. + stopCond.set_pause_on_mpe(mss::ON); + } + else if (getMcbistDataBundle(i_chip)->iv_ceStopCounter.thReached(io_sc)) + { + // If we've reached the limit of CEs we're allowed to stop on + // per rank, set all the normal stop conditions except stop on CE + stopCond.set_pause_on_aue(mss::ON); + + #ifdef CONFIG_HBRT_PRD + + stopCond.set_pause_on_mpe(mss::ON) + .set_pause_on_ue(mss::ON); + + // In MNFG mode, stop on RCE_ETE to get an accurate callout for IUEs + if ( mfgMode() ) stopCond.set_thresh_rce(1); + + #endif + } + else + { + // If we haven't reached threshold on the number of UEs or CEs we + // have stopped on, do not change the stop conditions. + stopCond = mss::mcbist::stop_conditions<>( + mss::mcbist::stop_conditions<>::DONT_CHANGE ); + } + // Resume the command on the next address. errlHndl_t errl; - FAPI_INVOKE_HWP( errl, mss::memdiags::continue_cmd, fapiTrgt ); + FAPI_INVOKE_HWP( errl, mss::memdiags::continue_cmd, fapiTrgt, + mss::mcbist::end_boundary::DONT_CHANGE, stopCond ); if ( nullptr != errl ) { @@ -217,12 +233,14 @@ uint32_t resumeBgScrub<TYPE_MCBIST>( ExtensibleChip * i_chip ) //------------------------------------------------------------------------------ template<> -uint32_t resumeBgScrub<TYPE_MCA>( ExtensibleChip * i_chip ) +uint32_t resumeBgScrub<TYPE_MCA>( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ) { PRDF_ASSERT( nullptr != i_chip ); PRDF_ASSERT( TYPE_MCA == i_chip->getType() ); - return resumeBgScrub<TYPE_MCBIST>(getConnectedParent(i_chip, TYPE_MCBIST)); + return resumeBgScrub<TYPE_MCBIST>(getConnectedParent(i_chip, TYPE_MCBIST), + io_sc); } //############################################################################## @@ -362,7 +380,8 @@ uint32_t __resumeScrub<TYPE_MBA>( ExtensibleChip * i_chip, //------------------------------------------------------------------------------ template<> -uint32_t resumeBgScrub<TYPE_MBA>( ExtensibleChip * i_chip ) +uint32_t resumeBgScrub<TYPE_MBA>( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ) { PRDF_ASSERT( nullptr != i_chip ); PRDF_ASSERT( TYPE_MBA == i_chip->getType() ); @@ -418,19 +437,21 @@ uint32_t stopBgScrub<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip ) uint32_t rc = SUCCESS; - /* TODO RTC 207273 - no HWP support yet + #ifdef CONFIG_AXONE + fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> fapiTrgt ( i_chip->getTrgt() ); errlHndl_t errl; - FAPI_INVOKE_HWP( errl, mss::memdiags::stop, fapiTrgt ); + FAPI_INVOKE_HWP( errl, exp_stop, fapiTrgt ); if ( nullptr != errl ) { - PRDF_ERR( PRDF_FUNC "mss::memdiags::stop(0x%08x) failed", i_chip->getHuid()); + PRDF_ERR( PRDF_FUNC "exp_stop(0x%08x) failed", i_chip->getHuid()); PRDF_COMMIT_ERRL( errl, ERRL_ACTION_REPORT ); rc = FAIL; } - */ + + #endif return rc; @@ -440,19 +461,8 @@ uint32_t stopBgScrub<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip ) //------------------------------------------------------------------------------ template<> -uint32_t stopBgScrub<TYPE_MEM_PORT>( ExtensibleChip * i_chip ) -{ - PRDF_ASSERT( nullptr != i_chip ); - PRDF_ASSERT( TYPE_MEM_PORT == i_chip->getType() ); - - ExtensibleChip* ocmbChip = getConnectedParent( i_chip, TYPE_OCMB_CHIP ); - return stopBgScrub<TYPE_OCMB_CHIP>( ocmbChip ); -} - -//------------------------------------------------------------------------------ - -template<> -uint32_t resumeBgScrub<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip ) +uint32_t resumeBgScrub<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ) { #define PRDF_FUNC "[PlatServices::resumeBgScrub<TYPE_OCMB_CHIP>] " @@ -461,9 +471,9 @@ uint32_t resumeBgScrub<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip ) uint32_t o_rc = SUCCESS; - /* TODO RTC 207273 - no hwp support yet + #ifdef CONFIG_AXONE - // Get the OCMB_CHIP fapi target + // Get the OCMB fapi target fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> fapiTrgt ( i_chip->getTrgt() ); do @@ -477,13 +487,45 @@ uint32_t resumeBgScrub<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip ) break; } + // Check UE and CE stop counters to determine stop conditions + mss::mcbist::stop_conditions<mss::mc_type::EXPLORER> stopCond; + if ( getOcmbDataBundle(i_chip)->iv_ueStopCounter.thReached(io_sc) ) + { + // If we've reached the limit of UEs we're allowed to stop on + // per rank, only set the stop on mpe stop condition. + stopCond.set_pause_on_mpe(mss::ON); + } + else if ( getOcmbDataBundle(i_chip)->iv_ceStopCounter.thReached(io_sc) ) + { + // If we've reached the limit of CEs we're allowed to stop on + // per rank, set all the normal stop conditions except stop on CE + stopCond.set_pause_on_aue(mss::ON); + + #ifdef CONFIG_HBRT_PRD + + stopCond.set_pause_on_mpe(mss::ON) + .set_pause_on_ue(mss::ON); + + // In MNFG mode, stop on RCE_ETE to get an accurate callout for IUEs + if ( mfgMode() ) stopCond.set_thresh_rce(1); + + #endif + } + else + { + // If we haven't reached threshold on the number of UEs or CEs we + // have stopped on, do not change the stop conditions. + stopCond = mss::mcbist::stop_conditions<mss::mc_type::EXPLORER>( + mss::mcbist::stop_conditions<mss::mc_type::EXPLORER>::DONT_CHANGE ); + } + // Resume the command on the next address. errlHndl_t errl; - FAPI_INVOKE_HWP( errl, mss::memdiags::continue_cmd, fapiTrgt ); - + FAPI_INVOKE_HWP( errl, exp_continue_cmd, fapiTrgt, + mss::mcbist::end_boundary::DONT_CHANGE, stopCond ); if ( nullptr != errl ) { - PRDF_ERR( PRDF_FUNC "mss::memdiags::continue_cmd(0x%08x) failed", + PRDF_ERR( PRDF_FUNC "exp_continue_cmd(0x%08x) failed", i_chip->getHuid() ); PRDF_COMMIT_ERRL( errl, ERRL_ACTION_REPORT ); o_rc = FAIL; break; @@ -491,25 +533,13 @@ uint32_t resumeBgScrub<TYPE_OCMB_CHIP>( ExtensibleChip * i_chip ) } while (0); - */ + #endif return o_rc; #undef PRDF_FUNC } -//------------------------------------------------------------------------------ - -template<> -uint32_t resumeBgScrub<TYPE_MEM_PORT>( ExtensibleChip * i_chip ) -{ - PRDF_ASSERT( nullptr != i_chip ); - PRDF_ASSERT( TYPE_MEM_PORT == i_chip->getType() ); - - ExtensibleChip* ocmbChip = getConnectedParent( i_chip, TYPE_OCMB_CHIP ); - return resumeBgScrub<TYPE_OCMB_CHIP>( ocmbChip ); -} - //############################################################################## //## Line Delete Functions //############################################################################## diff --git a/src/usr/diag/prdf/plat/prdfPlatServices_rt.H b/src/usr/diag/prdf/plat/prdfPlatServices_rt.H index 5407c94ad..49d4c0a73 100644 --- a/src/usr/diag/prdf/plat/prdfPlatServices_rt.H +++ b/src/usr/diag/prdf/plat/prdfPlatServices_rt.H @@ -30,7 +30,6 @@ #include <p9_l2err_extract.H> #include <p9_pm_callout.H> #include <prdfMemAddress.H> -#include <isteps/nvdimm/nvdimm.H> namespace PRDF { @@ -65,22 +64,13 @@ void sendDynMemDeallocRequest( uint64_t i_saddr, uint64_t i_eaddr ); */ void sendPredDeallocRequest( uint64_t i_saddr, uint64_t i_eaddr ); -/** - * @brief Notify PHYP of NVDIMM protection status - * - * @param i_target Processor with NVDIMM - * @param i_state Protection state of NVDIMM - */ -uint32_t nvdimmNotifyPhypProtChange( TARGETING::Target * i_target, - const NVDIMM::nvdimm_protection_t i_state ); - //############################################################################## //## Nimbus/Centaur Maintenance Command wrappers //############################################################################## /** * @brief Stops Background Scrubbing. - * @param i_chip MCBIST, MCA, MBA, MEM_PORT, or OCMB chip. + * @param i_chip MCBIST, MCA, MBA, or OCMB chip. * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. */ template<TARGETING::TYPE T> @@ -99,11 +89,13 @@ uint32_t stopBgScrub( ExtensibleChip * i_chip ); * due to an error. It should not be called after executing a Targeted * Diagnotics procedure. * - * @param i_chip MCBIST, MCA, MBA, MEM_PORT, or OCMB chip. + * @param i_chip MCBIST, MCA, MBA, or OCMB chip. + * @param io_sc The step code data struct. * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. */ template<TARGETING::TYPE T> -uint32_t resumeBgScrub( ExtensibleChip * i_chip ); +uint32_t resumeBgScrub( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ); /** * @brief Resumes TD scrubbing after it has paused on error. diff --git a/src/usr/diag/prdf/prdfMain_ipl.C b/src/usr/diag/prdf/prdfMain_ipl.C index b73356575..755206b1e 100644 --- a/src/usr/diag/prdf/prdfMain_ipl.C +++ b/src/usr/diag/prdf/prdfMain_ipl.C @@ -42,10 +42,10 @@ #include <prdfCenMbaDataBundle.H> #include <prdfPlatServices.H> #include <prdfP9McaDataBundle.H> +#include <prdfOcmbDataBundle.H> #include <prdfMemBgScrub.H> // Custom compile configs -#include <config.h> #ifdef CONFIG_ENABLE_CHECKSTOP_ANALYSIS #include <prdfFileRegisterAccess.H> @@ -98,6 +98,11 @@ int32_t analyzeIplCEStats( TargetHandle_t i_trgt, bool &o_calloutMade ) MbaDataBundle * db = getMbaDataBundle( chip ); o_calloutMade = db->getIplCeStats()->analyzeStats(); } + else if ( TYPE_OCMB_CHIP == type ) + { + OcmbDataBundle * db = getOcmbDataBundle( chip ); + o_calloutMade = db->getIplCeStats()->analyzeStats(); + } else { PRDF_ERR( PRDF_FUNC "Unsupported target type %d", type ); @@ -155,6 +160,8 @@ errlHndl_t startScrub( const TargetHandle_t i_trgt ) { case TYPE_MBA: startInitialBgScrub<TYPE_MBA>( chip); break; case TYPE_MCBIST: startInitialBgScrub<TYPE_MCBIST>(chip); break; + case TYPE_OCMB_CHIP: + startInitialBgScrub<TYPE_OCMB_CHIP>(chip); break; default: PRDF_ERR( PRDF_FUNC "Unsupported maintenance target type " "0x%02x", chip->getType() ); diff --git a/src/usr/diag/prdf/prdf_hb_only.mk b/src/usr/diag/prdf/prdf_hb_only.mk index 72ef8880d..6217c6b40 100644 --- a/src/usr/diag/prdf/prdf_hb_only.mk +++ b/src/usr/diag/prdf/prdf_hb_only.mk @@ -75,10 +75,20 @@ prd_incpath += ${ROOTPATH}/src/import/chips/p9/procedures/hwp/pm/ prd_incpath += ${ROOTPATH}/src/import/chips/p9/procedures/hwp/lib/ prd_incpath += ${ROOTPATH}/src/import/generic/memory/lib/utils/ prd_incpath += ${ROOTPATH}/src/import/chips/p9/utils/imageProcs/ +prd_incpath += ${ROOTPATH}/src/import/chips/common/utils/ prd_incpath += ${ROOTPATH}/src/import/chips/common/utils/imageProcs/ prd_incpath += ${ROOTPATH}/src/import/hwpf/fapi2/include prd_incpath += ${ROOTPATH}/src/import/ prd_incpath += ${ROOTPATH}/src/import/chips/centaur/procedures/hwp/io/ +prd_incpath += ${ROOTPATH}/src/usr/isteps/nvdimm + +# For including hwp_wrappers.H +prd_incpath += ${ROOTPATH}/src/import/generic/memory/lib/prd/ +prd_incpath += ${ROOTPATH}/src/import/generic/memory/lib/utils/mcbist/ +prd_incpath += ${ROOTPATH}/src/import/chips/ocmb/explorer/common/include/ +prd_incpath += ${ROOTPATH}/src/import/chips/ocmb/explorer/procedures/hwp/memory/ +prd_incpath += ${ROOTPATH}/obj/genfiles/chips/ocmb/explorer/procedures/hwp/memory/lib/ +prd_incpath += ${ROOTPATH}/obj/genfiles/generic/memory/lib/ ################################################################################ # Hostboot only object files common to both IPL and runtime @@ -130,12 +140,6 @@ ifeq (${HOSTBOOT_RUNTIME},1) # plat/ prd_obj += prdfPlatServices_rt.o -# nvdimm -prd_vpath += ${ROOTPATH}/src/usr/isteps/nvdimm/ -prd_vpath += ${ROOTPATH}/src/usr/isteps/nvdimm/runtime -prd_obj_no_sim += nvdimm.o -prd_obj_no_sim += nvdimm_rt.o - endif ################################################################################ @@ -190,6 +194,19 @@ prd_obj_no_sim += p9c_dimmBadDqBitmapFuncs.o prd_obj_no_sim += p9c_query_channel_failure.o prd_obj_no_sim += p9c_mss_rowRepairFuncs.o +prd_vpath += ${ROOTPATH}/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ +prd_vpath += ${ROOTPATH}/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/ +prd_vpath += ${ROOTPATH}/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/ +prd_vpath += ${ROOTPATH}/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/utils +prd_vpath += ${ROOTPATH}/src/import/chips/p9/procedures/hwp/memory/lib/utils/ +prd_obj_no_sim += hwp_wrappers_nim.o +prd_obj_no_sim += hwp_wrappers_exp.o +prd_obj_no_sim += nimbus_pos.o +prd_obj_no_sim += explorer_pos.o +prd_obj_no_sim += exp_mcbist.o +prd_obj_no_sim += exp_memdiags.o +prd_obj_no_sim += explorer_memory_size.o + ################################################################################ # The following are hardware procedure utilities that we are pulling into the # PRD library (only needed here for HBRT). This code is already compiled in diff --git a/src/usr/diag/prdf/runtime/makefile b/src/usr/diag/prdf/runtime/makefile index 8f7338756..970ce9333 100644 --- a/src/usr/diag/prdf/runtime/makefile +++ b/src/usr/diag/prdf/runtime/makefile @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2014,2018 +# Contributors Listed Below - COPYRIGHT 2014,2019 # [+] International Business Machines Corp. # # @@ -38,13 +38,16 @@ include ../prdf_hb_only.mk # Will define PRD_SRC_PATH and PRD_INC_PATH include ../common/prdf_common_fsp_and_hb.mk include ../common/framework/prdf_framework.mk include ../common/plat/p9/prdf_plat_p9.mk +include ../common/plat/axone/prdf_plat_axone.mk include ../common/plat/cen/prdf_plat_cen.mk include ../common/plat/mem/prdf_plat_mem.mk include ../common/plat/centaur/prdf_plat_centaur.mk include ../common/plat/cumulus/prdf_plat_cumulus.mk include ../common/plat/nimbus/prdf_plat_nimbus.mk +include ../common/plat/explorer/prdf_plat_explorer.mk include ../plat/cen/prdf_plat_cen_hb_only.mk include ../plat/mem/prdf_plat_mem_hb_only.mk +include ../plat/explorer/prdf_plat_explorer_hb_only.mk include ../plat/p9/prdf_plat_p9_hb_only.mk VPATH += ${prd_vpath} diff --git a/src/usr/diag/prdf/test/prdfTest_BadDqBitmap.H b/src/usr/diag/prdf/test/prdfTest_BadDqBitmap.H new file mode 100644 index 000000000..4b4fa8fea --- /dev/null +++ b/src/usr/diag/prdf/test/prdfTest_BadDqBitmap.H @@ -0,0 +1,227 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/diag/prdf/test/prdfTest_BadDqBitmap.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +#ifndef __TEST_PRDFBADDQBITMAP_H +#define __TEST_PRDFBADDQBITMAP_H + +/** + * @file prdfTest_BadDqBitmap.H + * + * @brief prdf testing reading and writing the BAD_DQ_BITMAP attribute + */ + +#ifdef __HOSTBOOT_MODULE + #include <cxxtest/TestSuite.H> + #include <errl/errlentry.H> + #include <errl/errlmanager.H> +#else + #include <cxxtest/TestSuite.h> + #include <fsp/FipsGlobalFixture.H> + #include <errlentry.H> +#endif + +#include <prdfTrace.H> +#include <prdfMain.H> +#include "prdfsimMacros.H" +#include <prdfMemDqBitmap.H> +#include <prdfPlatServices.H> +#include <prdfTargetServices.H> + +class WriteBadDqBitmap: public CxxTest::TestSuite +{ + +public: + + void TestNimbusReadWriteBadDqBitmap(void) + { + using namespace PRDF; + using namespace TARGETING; + using namespace PlatServices; + + TargetHandle_t masterProc = nullptr; + targetService().masterProcChipTargetHandle(masterProc); + + // Nimbus only test + if ( MODEL_NIMBUS == masterProc->getAttr<ATTR_MODEL>() ) + { + TS_INFO("- TestNimbusReadWriteBadDqBitmap - Start -"); + + uint32_t rc = SUCCESS; + + // Get an MCBIST + TargetHandle_t mcb = getConnectedChild(masterProc, TYPE_MCBIST, 0); + if ( nullptr == mcb ) + { + TS_FAIL( "ERROR: Failed to get MCBIST" ); + } + // Get an MCA + TargetHandle_t mca = getConnectedChild( mcb, TYPE_MCA, 0 ); + if ( nullptr == mca ) + { + TS_FAIL( "ERROR: Failed to get MCA" ); + } + + // Make arbitrary initial data + MemRank rank( 0, 0 ); + const uint8_t initialBitmap[DQ_BITMAP::BITMAP_SIZE] = + { 0xdb, 0xdb, 0xdb, 0xdb, 0xdb, 0xdb, 0xdb, 0xdb, 0xdb, 0x00 }; + BitmapData initialData; + memcpy( initialData[0].bitmap, initialBitmap, + sizeof(initialData[0].bitmap) ); + + // Set with the initial data + MemDqBitmap setBitmap( mca, rank, initialData ); + rc = setBadDqBitmap( mca, rank, setBitmap ); + if ( SUCCESS != rc ) + { + TS_FAIL( "ERROR: setBadDqBitmap failed " ); + } + + // Read the data back + MemDqBitmap getBitmap; + rc = getBadDqBitmap( mca, rank, getBitmap ); + if ( SUCCESS != rc ) + { + TS_FAIL( "ERROR: getBadDqBitmap failed" ); + } + + BitmapData newData = getBitmap.getData(); + + // Compare the read data to the initial data. The last byte (byte 9) + // is for spares so we won't worry about comparing that. + for ( uint8_t n = 0; n < (DQ_BITMAP::BITMAP_SIZE-1); n++ ) + { + if ( newData.at(0).bitmap[n] != initialBitmap[n] ) + { + TS_FAIL( "TestNimbusReadWriteBadDqBitmap: Incorrect data " + "found. newData[%d]=0x%x initialBitmap[%d]=0x%x", + n, newData.at(0).bitmap[n], n, initialBitmap[n] ); + } + } + + // Clear the vpd just in case + rc = clearBadDqBitmap( mca, rank ); + if ( SUCCESS != rc ) + { + TS_FAIL( "ERROR: clearBadDqBitmap failed" ); + } + + TS_INFO("- TestNimbusReadWriteBadDqBitmap - End -"); + } + + } + + void TestAxoneReadWriteBadDqBitmap(void) + { + using namespace PRDF; + using namespace TARGETING; + using namespace PlatServices; + + TargetHandle_t masterProc = nullptr; + targetService().masterProcChipTargetHandle(masterProc); + + // Axone only test + if ( MODEL_AXONE == masterProc->getAttr<ATTR_MODEL>() ) + { + TS_INFO("- TestAxoneReadWriteBadDqBitmap - Start -"); + + uint32_t rc = SUCCESS; + + // Get an OCMB + TargetHandle_t mc = getConnectedChild( masterProc, TYPE_MC, 0 ); + if ( nullptr == mc ) + { + TS_FAIL( "ERROR: Failed to get MC" ); + } + TargetHandle_t omic = getConnectedChild( mc, TYPE_OMIC, 0 ); + if ( nullptr == omic ) + { + TS_FAIL( "ERROR: Failed to get OMIC" ); + } + TargetHandle_t omi = getConnectedChild( omic, TYPE_OMI, 0 ); + if ( nullptr == omi ) + { + TS_FAIL( "ERROR: Failed to get OMI" ); + } + TargetHandle_t ocmb = getConnectedChild( omi, TYPE_OCMB_CHIP, 0 ); + if ( nullptr == ocmb ) + { + TS_FAIL( "ERROR: Failed to get OCMB" ); + } + // Make arbitrary initial data + MemRank rank( 0 ); + const uint8_t initialBitmap[DQ_BITMAP::BITMAP_SIZE] = + { 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0x00 }; + BitmapData initialData; + memcpy( initialData[0].bitmap, initialBitmap, + sizeof(initialData[0].bitmap) ); + + // Set with the initial data + MemDqBitmap setBitmap( ocmb, rank, initialData ); + rc = setBadDqBitmap( ocmb, rank, setBitmap ); + if ( SUCCESS != rc ) + { + TS_FAIL( "ERROR: setBadDqBitmap failed " ); + } + + // Read the data back + MemDqBitmap getBitmap; + rc = getBadDqBitmap( ocmb, rank, getBitmap ); + if ( SUCCESS != rc ) + { + TS_FAIL( "ERROR: getBadDqBitmap failed" ); + } + + BitmapData newData = getBitmap.getData(); + + // Compare the read data to the initial data. The last byte (byte 9) + // is for spares so we won't worry about comparing that. + for ( uint8_t n = 0; n < (DQ_BITMAP::BITMAP_SIZE-1); n++ ) + { + if ( newData.at(0).bitmap[n] != initialBitmap[n] ) + { + TS_FAIL( "TestAxoneReadWriteBadDqBitmap: Incorrect data " + "found. newData[%d]=0x%x initialBitmap[%d]=0x%x", + n, newData.at(0).bitmap[n], n, initialBitmap[n] ); + } + } + + // Clear the vpd just in case + rc = clearBadDqBitmap( ocmb, rank ); + if ( SUCCESS != rc ) + { + TS_FAIL( "ERROR: clearBadDqBitmap failed" ); + } + + TS_INFO("- TestAxoneReadWriteBadDqBitmap - End -"); + + } + + } + +//------------------------------------------------------------------------------ + +}; +#endif diff --git a/src/usr/diag/prdf/test/prdf_hb_common_test.mk b/src/usr/diag/prdf/test/prdf_hb_common_test.mk index a148e0c24..5d1e7ea36 100755 --- a/src/usr/diag/prdf/test/prdf_hb_common_test.mk +++ b/src/usr/diag/prdf/test/prdf_hb_common_test.mk @@ -70,6 +70,7 @@ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/procedures/hwp/cache/ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/procedures/hwp/pm/ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/procedures/hwp/lib/ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/utils/imageProcs +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/utils EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/utils/imageProcs EXTRAINCDIR += ${ROOTPATH}/src/import/hwpf/fapi2/include EXTRAINCDIR += ${ROOTPATH}/src/import/ @@ -91,8 +92,9 @@ TESTS += ${PRD_USR_TEST_PATH}/prdfTest.H TESTS += ${PRD_USR_TEST_PATH}/prdfTest_XBus.H TESTS += ${PRD_USR_TEST_PATH}/prdfTest_ABus.H TESTS += ${PRD_USR_TEST_PATH}/prdfTest_ProcCentFir.H +TESTS += ${PRD_USR_TEST_PATH}/prdfTest_BadDqBitmap.H TESTS += ${PRD_USR_TEST_PATH}/prdfTest_Ex.H -TESTS += $(if $(CONFIG_AXONE_BRING_UP),,${PRD_USR_TEST_PATH}/prdfTest_NimbusTpLFir.H) +TESTS += ${PRD_USR_TEST_PATH}/prdfTest_NimbusTpLFir.H #@TODO RTC:178802 #TESTS += ${PRD_USR_TEST_PATH}/prdfTest_Mcs.H diff --git a/src/usr/diag/prdf/test/prdfsimHomRegisterAccess.C b/src/usr/diag/prdf/test/prdfsimHomRegisterAccess.C index 3e3079883..d6b02b5ee 100755 --- a/src/usr/diag/prdf/test/prdfsimHomRegisterAccess.C +++ b/src/usr/diag/prdf/test/prdfsimHomRegisterAccess.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2017 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -43,7 +43,7 @@ SimScomAccessor::~SimScomAccessor() uint32_t SimScomAccessor::Access(TARGETING::TargetHandle_t i_target, BitString & bs, uint64_t registerId, - MopRegisterAccess::Operation operation) const + RegisterAccess::Operation operation) const { PRDF_DENTER("SimScomAccessor::Access()"); uint32_t rc = SUCCESS; @@ -53,8 +53,8 @@ uint32_t SimScomAccessor::Access(TARGETING::TargetHandle_t i_target, { switch (operation) { - case MopRegisterAccess::WRITE: l_op = ScrDB::WRITE; break; - case MopRegisterAccess::READ: l_op = ScrDB::READ; break; + case RegisterAccess::WRITE: l_op = ScrDB::WRITE; break; + case RegisterAccess::READ: l_op = ScrDB::READ; break; default: PRDF_ERR( "SimScomAccessor::Access() unsupported operation: 0x%X", operation ); rc = PRD_SCANCOM_FAILURE; diff --git a/src/usr/diag/prdf/test/prdfsimHomRegisterAccess.H b/src/usr/diag/prdf/test/prdfsimHomRegisterAccess.H index b8a610f75..f5566eb54 100755 --- a/src/usr/diag/prdf/test/prdfsimHomRegisterAccess.H +++ b/src/usr/diag/prdf/test/prdfsimHomRegisterAccess.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2017 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -73,7 +73,7 @@ class SimScomAccessor : public ScomAccessor virtual uint32_t Access(TARGETING::TargetHandle_t i_target, BitString & bs, uint64_t registerId, - MopRegisterAccess::Operation operation) const; + RegisterAccess::Operation operation) const; private: diff --git a/src/usr/diag/prdf/test/prdfsimScrDB.C b/src/usr/diag/prdf/test/prdfsimScrDB.C index 6308ba423..a6a67bd9c 100755 --- a/src/usr/diag/prdf/test/prdfsimScrDB.C +++ b/src/usr/diag/prdf/test/prdfsimScrDB.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2017 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -24,7 +24,7 @@ /* IBM_PROLOG_END_TAG */ #include "prdfsimScrDB.H" -#include <iipMopRegisterAccess.h> +#include <prdfHomRegisterAccess.H> #include <prdfTrace.H> #include <prdfPlatServices.H> #include "prdfsimServices.H" diff --git a/src/usr/dump/dumpCollect.C b/src/usr/dump/dumpCollect.C index 6b95a2c2d..b85bcd28b 100644 --- a/src/usr/dump/dumpCollect.C +++ b/src/usr/dump/dumpCollect.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2019 */ +/* Contributors Listed Below - COPYRIGHT 2012,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -41,6 +41,8 @@ #include <dump/dumpif.H> #include <util/utiltce.H> #include <isteps/mem_utils.H> +#include <string.h> +#include <stdio.h> #include <sys/msg.h> // message Q's #include <mbox/mbox_queues.H> // @@ -54,7 +56,163 @@ TRAC_INIT(&g_trac_dump, "DUMP", 4*KILOBYTE); namespace DUMP { - +//////////// +// Define an SPR number to name str map. Note that this inverse of how +// the HWP uses it... so use the same mechanism/data - just inverse +std::map<uint32_t, const char*> SPRNUM_MAP; +typedef std::map<uint32_t, const char*>::iterator SPRNUM_MAP_IT; + +#define LIST_SPR_NAME_REG(_op_)\ + _op_(XER ,1 )\ + _op_(DSCR_RU ,3 )\ + _op_(LR ,8 )\ + _op_(CTR ,9 )\ + _op_(UAMR ,13 )\ + _op_(DSCR ,17 )\ + _op_(DSISR ,18 )\ + _op_(DAR ,19 )\ + _op_(DEC ,22 )\ + _op_(SDR1 ,25 )\ + _op_(SRR0 ,26 )\ + _op_(SRR1 ,27 )\ + _op_(CFAR ,28 )\ + _op_(AMR ,29 )\ + _op_(PIDR ,48 )\ + _op_(IAMR ,61 )\ + _op_(TFHAR ,128 )\ + _op_(TFIAR ,129 )\ + _op_(TEXASR ,130 )\ + _op_(TEXASRU ,131 )\ + _op_(CTRL_RU ,136 )\ + _op_(TIDR ,144 )\ + _op_(CTRL ,152 )\ + _op_(FSCR ,153 )\ + _op_(UAMOR ,157 )\ + _op_(GSR ,158 )\ + _op_(PSPB ,159 )\ + _op_(DPDES ,176 )\ + _op_(DAWR0 ,180 )\ + _op_(RPR ,186 )\ + _op_(CIABR ,187 )\ + _op_(DAWRX0 ,188 )\ + _op_(HFSCR ,190 )\ + _op_(VRSAVE ,256 )\ + _op_(SPRG3_RU ,259 )\ + _op_(TB ,268 )\ + _op_(TBU_RU ,269 )\ + _op_(SPRG0 ,272 )\ + _op_(SPRG1 ,273 )\ + _op_(SPRG2 ,274 )\ + _op_(SPRG3 ,275 )\ + _op_(SPRC ,276 )\ + _op_(SPRD ,277 )\ + _op_(CIR ,283 )\ + _op_(TBL ,284 )\ + _op_(TBU ,285 )\ + _op_(TBU40 ,286 )\ + _op_(PVR ,287 )\ + _op_(HSPRG0 ,304 )\ + _op_(HSPRG1 ,305 )\ + _op_(HDSISR ,306 )\ + _op_(HDAR ,307 )\ + _op_(SPURR ,308 )\ + _op_(PURR ,309 )\ + _op_(HDEC ,310 )\ + _op_(HRMOR ,313 )\ + _op_(HSRR0 ,314 )\ + _op_(HSRR1 ,315 )\ + _op_(TFMR ,317 )\ + _op_(LPCR ,318 )\ + _op_(LPIDR ,319 )\ + _op_(HMER ,336 )\ + _op_(HMEER ,337 )\ + _op_(PCR ,338 )\ + _op_(HEIR ,339 )\ + _op_(AMOR ,349 )\ + _op_(TIR ,446 )\ + _op_(PTCR ,464 )\ + _op_(USPRG0 ,496 )\ + _op_(USPRG1 ,497 )\ + _op_(UDAR ,499 )\ + _op_(SEIDR ,504 )\ + _op_(URMOR ,505 )\ + _op_(USRR0 ,506 )\ + _op_(USRR1 ,507 )\ + _op_(UEIR ,509 )\ + _op_(ACMCR ,510 )\ + _op_(SMFCTRL ,511 )\ + _op_(SIER_RU ,768 )\ + _op_(MMCR2_RU ,769 )\ + _op_(MMCRA_RU ,770 )\ + _op_(PMC1_RU ,771 )\ + _op_(PMC2_RU ,772 )\ + _op_(PMC3_RU ,773 )\ + _op_(PMC4_RU ,774 )\ + _op_(PMC5_RU ,775 )\ + _op_(PMC6_RU ,776 )\ + _op_(MMCR0_RU ,779 )\ + _op_(SIAR_RU ,780 )\ + _op_(SDAR_RU ,781 )\ + _op_(MMCR1_RU ,782 )\ + _op_(SIER ,784 )\ + _op_(MMCR2 ,785 )\ + _op_(MMCRA ,786 )\ + _op_(PMC1 ,787 )\ + _op_(PMC2 ,788 )\ + _op_(PMC3 ,789 )\ + _op_(PMC4 ,790 )\ + _op_(PMC5 ,791 )\ + _op_(PMC6 ,792 )\ + _op_(MMCR0 ,795 )\ + _op_(SIAR ,796 )\ + _op_(SDAR ,797 )\ + _op_(MMCR1 ,798 )\ + _op_(IMC ,799 )\ + _op_(BESCRS ,800 )\ + _op_(BESCRSU ,801 )\ + _op_(BESCRR ,802 )\ + _op_(BESCRRU ,803 )\ + _op_(EBBHR ,804 )\ + _op_(EBBRR ,805 )\ + _op_(BESCR ,806 )\ + _op_(LMRR ,813 )\ + _op_(LMSER ,814 )\ + _op_(TAR ,815 )\ + _op_(ASDR ,816 )\ + _op_(PSSCR_SU ,823 )\ + _op_(IC ,848 )\ + _op_(VTB ,849 )\ + _op_(LDBAR ,850 )\ + _op_(MMCRC ,851 )\ + _op_(PMSR ,853 )\ + _op_(PMMAR ,854 )\ + _op_(PSSCR ,855 )\ + _op_(L2QOSR ,861 )\ + _op_(WORC ,863 )\ + _op_(TRIG0 ,880 )\ + _op_(TRIG1 ,881 )\ + _op_(TRIG2 ,882 )\ + _op_(PMCR ,884 )\ + _op_(RWMR ,885 )\ + _op_(WORT ,895 )\ + _op_(PPR ,896 )\ + _op_(PPR32 ,898 )\ + _op_(TSCR ,921 )\ + _op_(TTR ,922 )\ + _op_(TRACE ,1006)\ + _op_(HID ,1008)\ + _op_(PIR ,1023)\ + _op_(NIA ,2000)\ + _op_(MSR ,2001)\ + _op_(CR ,2002)\ + _op_(FPSCR ,2003)\ + _op_(VSCR ,2004)\ + _op_(SLBE ,2005)\ + _op_(SLBV ,2006) + + +#define DO_SPRNUM_MAP(in_name, in_number)\ + SPRNUM_MAP[in_number] = #in_name; /////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////// @@ -107,6 +265,31 @@ errlHndl_t doDumpCollect(void) /////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////// +// Replace reg num with name +void replaceRegNumWithName( hostArchRegDataEntry *hostRegData ) +{ + char str[sizeof(reg_t)]; + + if(hostRegData->reg.type == DUMP_ARCH_REG_TYPE_GPR) + { + snprintf(str,sizeof(reg_t), "GPR%d\0", hostRegData->reg.num); + strncpy(hostRegData->reg.name, str, sizeof(reg_t)); + } + else if (hostRegData->reg.type == DUMP_ARCH_REG_TYPE_SPR) + { + if(SPRNUM_MAP.find(hostRegData->reg.num) != SPRNUM_MAP.end()) + { + strncpy(hostRegData->reg.name, SPRNUM_MAP[hostRegData->reg.num], sizeof(reg_t)); + } + //else unknown... leave as number for debug + } + //else unknown type... leave as number for debug + +} + + +/////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////// // Returns the physical address corresponding to a PHYP MDST/MDRT entry void* getPhysAddr( uint64_t i_phypAddr ) { @@ -153,6 +336,9 @@ errlHndl_t copyArchitectedRegs(void) // Architected Reg Dump table struct pointers procDumpAreaEntry *procTableEntry = nullptr; + //Setup SPR num to string mapping + LIST_SPR_NAME_REG(DO_SPRNUM_MAP) + do { // Get the PROC_DUMP_AREA_TBL address from SPIRAH @@ -196,16 +382,30 @@ errlHndl_t copyArchitectedRegs(void) procTableEntry = reinterpret_cast<procDumpAreaEntry *>(procTableAddr); pDstAddrBase = getPhysAddr(procTableEntry->dstArrayAddr); vMapDstAddrBase = mm_block_map(pDstAddrBase, - procTableEntry->dstArraySize); + (ALIGN_PAGE(procTableEntry->dstArraySize) + PAGESIZE)); + + //Need to adjust actual virtual address due to mm_block_map only + //mapping on page boundary to account for non page aligned addresses + //from PHYP/OPAL + uint64_t tmpAddr = reinterpret_cast<uint64_t>(vMapDstAddrBase); + vMapDstAddrBase = reinterpret_cast<void*>(tmpAddr + + (procTableEntry->dstArrayAddr & (PAGESIZE-1))); // Map architected register reserved memory to VA addresses - uint64_t srcAddr = ISTEP::get_top_homer_mem_addr() - - VMM_ARCH_REG_DATA_SIZE_ALL_PROC - - VMM_ALL_HOMER_OCC_MEMORY_SIZE; + TARGETING::Target * l_sys = NULL; + TARGETING::targetService().getTopLevelTarget( l_sys ); + assert(l_sys != NULL); + auto srcAddr = + l_sys->getAttr<TARGETING::ATTR_SBE_ARCH_DUMP_ADDR>(); + pSrcAddrBase = reinterpret_cast<void * const>(srcAddr); vMapSrcAddrBase = mm_block_map(pSrcAddrBase, VMM_ARCH_REG_DATA_SIZE_ALL_PROC); + TRACDCOMP(g_trac_dump, "src address [0x%X] [%p], destArrayaddr" + " [%X] dest[%p] [%p]", srcAddr, vMapSrcAddrBase, + procTableEntry->dstArrayAddr, pDstAddrBase, vMapDstAddrBase); + // Get list of functional processor chips, in MPIPL path we // don't expect any deconfiguration TARGETING::TargetHandleList procChips; @@ -214,13 +414,13 @@ errlHndl_t copyArchitectedRegs(void) uint64_t dstTempAddr = reinterpret_cast<uint64_t>(vMapDstAddrBase); procTableEntry->capArraySize = 0; - for (const auto & procChip: procChips) + for (uint32_t procNum = 0; procNum < procChips.size(); procNum++) { - uint8_t procNum = procChip->getAttr<TARGETING::ATTR_POSITION>(); // Base addresses w.r.t PROC positions. This is static here // and used for reference below to calculate all other addresses uint64_t procSrcAddr = (reinterpret_cast<uint64_t>(vMapSrcAddrBase)+ procNum * VMM_ARCH_REG_DATA_PER_PROC_SIZE); + TRACDCOMP(g_trac_dump, "SBE Proc[%d] [%p]", procNum, procSrcAddr); sbeArchRegDumpProcHdr_t *sbeProcHdr = reinterpret_cast<sbeArchRegDumpProcHdr_t *>(procSrcAddr); @@ -294,7 +494,11 @@ errlHndl_t copyArchitectedRegs(void) hostArchRegDataHdr *hostHdr = reinterpret_cast<hostArchRegDataHdr *>(dstTempAddr); + TRACDCOMP(g_trac_dump, " Thread[%d] src[%p] dest[%p]", + idx, procSrcAddr, dstTempAddr); + // Fill thread header info + memset(hostHdr, 0x0, sizeof(hostHdr)); hostHdr->pir = sbeTdHdr->pir; hostHdr->coreState = sbeTdHdr->coreState; hostHdr->iv_regArrayHdr.hdatOffset = @@ -330,10 +534,16 @@ errlHndl_t copyArchitectedRegs(void) hostArchRegDataEntry *hostRegData = reinterpret_cast<hostArchRegDataEntry *>(dstTempAddr); - hostRegData->regType = sbeRegData->regType; - hostRegData->regNum = sbeRegData->regNum; + hostRegData->reg.type = sbeRegData->regType; + hostRegData->reg.num = sbeRegData->regNum; hostRegData->regVal = sbeRegData->regVal; + // If HOST type is PHYP replace register number with strings + if (TARGETING::is_phyp_load()) + { + replaceRegNumWithName(hostRegData); + } + dstTempAddr = reinterpret_cast<uint64_t>(dstTempAddr + sizeof(hostArchRegDataEntry)); //Update the SBE data source address to point to the @@ -367,9 +577,6 @@ errlHndl_t copyArchitectedRegs(void) procTableEntry->capArrayAddr = procTableEntry->dstArrayAddr; // Update the PDA Table Entries to Attribute to be fetched in istep 21 - TARGETING::TargetService& targetService = TARGETING::targetService(); - TARGETING::Target* l_sys = NULL; - targetService.getTopLevelTarget(l_sys); l_sys->setAttr<TARGETING::ATTR_PDA_THREAD_REG_STATE_ENTRY_FORMAT>( procTableEntry->threadRegVersion); l_sys->setAttr<TARGETING::ATTR_PDA_THREAD_REG_ENTRY_SIZE>( diff --git a/src/usr/errl/errl.mk b/src/usr/errl/errl.mk index 8cab37324..8caf92216 100644 --- a/src/usr/errl/errl.mk +++ b/src/usr/errl/errl.mk @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2015,2018 +# Contributors Listed Below - COPYRIGHT 2015,2019 # [+] International Business Machines Corp. # # @@ -41,3 +41,4 @@ OBJS += errludsensor.o OBJS += errludstate.o OBJS += errlmanager_common.o OBJS += errli2c.o +OBJS += errludattribute.o diff --git a/src/usr/errl/errlentry.C b/src/usr/errl/errlentry.C index 61eeb15f2..78e1f9bc6 100644 --- a/src/usr/errl/errlentry.C +++ b/src/usr/errl/errlentry.C @@ -49,7 +49,6 @@ #include <errl/errludstate.H> #include <errl/errli2c.H> #include <trace/interface.H> -#include <config.h> #include "../trace/entry.H" #include <util/align.H> @@ -60,7 +59,6 @@ #include <targeting/common/targetservice.H> #include <targeting/common/utilFilter.H> #include <targeting/common/commontargeting.H> -#include <config.h> #include <initservice/initserviceif.H> #include <attributeenums.H> #include "errlentry_consts.H" @@ -405,18 +403,6 @@ void ErrlEntry::addPartCallout(const TARGETING::Target *i_target, i_target, i_partType, i_priority, i_deconfigState, i_gardErrorType); - // Need targeting for nvdimm check - if(Util::isTargetingLoaded() && TARGETING::targetService().isInitialized()) - { - // Add procedure callout to replace the cable to the NVDIMM - if( (i_target->getAttr<TARGETING::ATTR_TYPE>() == TARGETING::TYPE_DIMM) - && ( isNVDIMM(i_target) ) ) - { - addProcedureCallout( HWAS::EPUB_PRC_NVDIMM_ERR, - HWAS::SRCI_PRIORITY_HIGH ); - } - } - const void* pData = nullptr; uint32_t size = 0; TARGETING::EntityPath* ep = nullptr; @@ -599,42 +585,7 @@ void ErrlEntry::addHwCallout(const TARGETING::Target *i_target, i_deconfigState, i_gardErrorType); #endif - // Add procedure callout to replace the cable to the NVDIMM - if( isNVDIMM(i_target) ) - { - addProcedureCallout( HWAS::EPUB_PRC_NVDIMM_ERR, - HWAS::SRCI_PRIORITY_HIGH ); - } - TARGETING::EntityPath ep; - TARGETING::TYPE l_type = i_target->getAttr<TARGETING::ATTR_TYPE>(); - - TARGETING::TYPE l_type_ecid = l_type; - const TARGETING::Target* l_parentTarget = i_target; - if((l_type_ecid != TARGETING::TYPE_MEMBUF) && - (l_type_ecid != TARGETING::TYPE_PROC) && - (l_type_ecid != TARGETING::TYPE_NODE) - ) - { - //since this returns NULL if the parent is not found, - // we need a placeholder - const TARGETING::Target* l_tempParentTarget = - getParentChip(l_parentTarget); - if(l_tempParentTarget != NULL) - { - l_parentTarget = l_tempParentTarget; - l_type_ecid = l_parentTarget->getAttr<TARGETING::ATTR_TYPE>(); - } - } - //if we have found a type_membuf or type_proc, store the ecid - //otherwise, (type_node), do nothing. - if(l_type_ecid == TARGETING::TYPE_MEMBUF || - l_type_ecid == TARGETING::TYPE_PROC) - { - ErrlUserDetailsAttribute(l_parentTarget, - TARGETING::ATTR_ECID).addToLog(this); - } - ep = i_target->getAttr<TARGETING::ATTR_PHYS_PATH>(); // size is total EntityPath size minus unused path elements @@ -704,99 +655,24 @@ void ErrlEntry::addVersionInfo() if ( !INITSERVICE::spBaseServicesEnabled() && PNOR::isSectionAvailable(PNOR::VERSION)) { - -// Setting variables only used in config secureboot -#ifdef CONFIG_SECUREBOOT - bool l_secureSectionLoaded = false; - errlHndl_t l_errl_loadSecureSection = nullptr; -#endif - - errlHndl_t l_errl = nullptr; - do { - -#ifdef CONFIG_SECUREBOOT - l_errl_loadSecureSection = PNOR::loadSecureSection(PNOR::VERSION); - if (l_errl_loadSecureSection) - { - TRACFCOMP( g_trac_errl, - "addVersionInfo: Failed to load secure VERSION"); - // Since an error occurred while attempting to add version info - // to another error log there is nothing that can be done with - // this error since attempting to commit it will lead to an - // infinite loop of committing the error and then recalling this - // function. If this error occurred then the VERSION partition - // is not added and the error log commit continues. - delete l_errl_loadSecureSection; - l_errl_loadSecureSection = nullptr; - break; - } - else - { - l_secureSectionLoaded = true; - } -#endif - - // Get PNOR Version - PNOR::SectionInfo_t l_pnorVersionInfo; - l_errl = getSectionInfo(PNOR::VERSION, l_pnorVersionInfo); - - if (l_errl) - { - TRACFCOMP( g_trac_errl, - "addVersionInfo: Failed to getSectionInfo"); - // Since an error occurred while attempting to add version info - // to another error log there is nothing that can be done with - // this error since attempting to commit it will lead to an - // infinite loop of committing the error and then recalling this - // function. If this error occurred then the VERSION partition - // is not added and the error log commit continues. - delete l_errl; - l_errl = nullptr; - break; - } - const uint8_t* l_versionData = - reinterpret_cast<uint8_t*>(l_pnorVersionInfo.vaddr); - - size_t l_numberOfBytes = 0; + ERRORLOG::getCachedVersionPartition(); + size_t l_versionSize = + ERRORLOG::getCachedVersionPartitionSize(); - // Determine the size of the version data. The max size is the given - // size in the SectionInfo but can be less. - while ((static_cast<char>(l_versionData[l_numberOfBytes]) != '\0') - && l_numberOfBytes < l_pnorVersionInfo.size) + if(!l_versionData || !l_versionSize) { - ++l_numberOfBytes; + break; } - char l_pVersionString[l_numberOfBytes + 1]={0}; + char l_pVersionString[l_versionSize + 1]={0}; - memcpy(l_pVersionString, l_versionData, l_numberOfBytes); + memcpy(l_pVersionString, l_versionData, l_versionSize); ErrlUserDetailsString(l_pVersionString).addToLog(this); } while(0); - -#ifdef CONFIG_SECUREBOOT - if (l_secureSectionLoaded) - { - l_errl_loadSecureSection = PNOR::unloadSecureSection(PNOR::VERSION); - if(l_errl_loadSecureSection) - { - TRACFCOMP( g_trac_errl, - "addVersionInfo: Failed to unload secure VERSION"); - // Since an error occurred while attempting to add version info - // to another error log there is nothing that can be done with - // this error since attempting to commit it will lead to an - // infinite loop of committing the error and then recalling this - // function. If this error occurred then the VERSION partition - // is not added and the error log commit continues. - delete l_errl_loadSecureSection; - l_errl_loadSecureSection = nullptr; - } - } -#endif - } // End of IPL only block @@ -947,75 +823,142 @@ void ErrlEntry::checkHiddenLogsEnable( ) } /////////////////////////////////////////////////////////////////////////////// -// Called by addHwCallout to get the part and serial numbers from the current -// target so that it can be appended to the error log -#ifdef CONFIG_BMC_IPMI - void ErrlEntry::addPartAndSerialNumbersToErrLog -(const TARGETING::Target * i_target) +// Called by addHwCallout to retrieve various pieces of card +// and/or chip data, e.g. part number, serial number, ecid. +void ErrlEntry::addPartIdInfoToErrLog + (const TARGETING::Target * i_target) { - TRACDCOMP(g_trac_errl, ENTER_MRK"ErrlEntry::addPartAndSerialNumbersToErrLog()"); + TRACDCOMP(g_trac_errl, ENTER_MRK"ErrlEntry::addPartIdInfoToErrLog()"); - - // Get the type of the target const TARGETING::Target * l_target = i_target; - TARGETING::TYPE l_type = l_target->getAttr<TARGETING::ATTR_TYPE>(); + const TARGETING::Target * l_targetPrev = nullptr; + ErrlUserDetailsAttribute* l_attrdata = nullptr; - do + //Add the part number to the error log. + TARGETING::TargetHandleList l_parentList; + TARGETING::ATTR_PART_NUMBER_type l_PN = {}; + while( !l_target->tryGetAttr<TARGETING::ATTR_PART_NUMBER>(l_PN) ) { - if((l_type != TARGETING::TYPE_PROC ) && - (l_type != TARGETING::TYPE_DIMM ) && - (l_type != TARGETING::TYPE_MEMBUF )) + // Get immediate parent + TARGETING::targetService().getAssociated( + l_parentList, + l_target, + TARGETING::TargetService::PARENT, + TARGETING::TargetService::IMMEDIATE); + + // never found a match... + if (l_parentList.size() != 1) { - TARGETING::PredicatePostfixExpr l_procDimmMembuf; - TARGETING::TargetHandleList l_pList; + l_target = nullptr; + break; + } - TARGETING::PredicateCTM l_procs(TARGETING::CLASS_CHIP, - TARGETING::TYPE_PROC); + l_target = l_parentList[0]; + l_parentList.clear(); // clear out old entry + } // end while + if( l_target ) + { + l_attrdata = new ErrlUserDetailsAttribute(l_target); + l_attrdata->addData(TARGETING::ATTR_PART_NUMBER); + l_targetPrev = l_target; + } - TARGETING::PredicateCTM l_dimms(TARGETING::CLASS_CARD, - TARGETING::TYPE_DIMM); + // Note - it is extremely likely that we will end up with the same + // target for PN and SN, but since this is error path only we're + // opting for thoroughness over efficiency. - TARGETING::PredicateCTM l_membufs(TARGETING::CLASS_CHIP, - TARGETING::TYPE_MEMBUF); + //Add the serial number to the error log. + l_target = i_target; + TARGETING::ATTR_SERIAL_NUMBER_type l_SN = {}; + while( !l_target->tryGetAttr<TARGETING::ATTR_SERIAL_NUMBER>(l_SN) ) + { + // Get immediate parent + TARGETING::targetService().getAssociated( + l_parentList, + l_target, + TARGETING::TargetService::PARENT, + TARGETING::TargetService::IMMEDIATE); - l_procDimmMembuf.push(&l_procs).push(&l_dimms).Or() - .push(&l_membufs).Or(); + // never found a match... + if (l_parentList.size() != 1) + { + l_target = nullptr; + break; + } - // Search for any parents with TYPE_PROC, TYPE_DIMM, or TYPE_MEMBUF - TARGETING::targetService().getAssociated( l_pList, l_target, - TARGETING::TargetService::PARENT, - TARGETING::TargetService::ALL, - &l_procDimmMembuf); - // If no parent of desired type is present, break - if(!l_pList.size()) - { - TRACFCOMP(g_trac_errl, "Error! errlentry.C::addPartAndSerialNumbersToErrLog - No parent containing Serial/Part numbers found."); - break; - } - else - { - // We have found the parent - l_target = l_pList[0]; - } + l_target = l_parentList[0]; + l_parentList.clear(); // clear out old entry + } // end while + if( l_target ) + { + // not likely to happen, but just in case... + if( l_attrdata && (l_targetPrev != l_target) ) + { + // got a new target, commit the previous data and start over + l_attrdata->addToLog(this); + delete l_attrdata; + l_attrdata = nullptr; + } + if( !l_attrdata ) + { + l_attrdata = new ErrlUserDetailsAttribute(l_target); + } + + l_attrdata->addData(TARGETING::ATTR_SERIAL_NUMBER); + l_targetPrev = l_target; + } + + //Add the ECID to the error log. + l_target = i_target; + TARGETING::ATTR_ECID_type l_ECID = {}; + while( !l_target->tryGetAttr<TARGETING::ATTR_ECID>(l_ECID) ) + { + // Get immediate parent + TARGETING::targetService().getAssociated( + l_parentList, + l_target, + TARGETING::TargetService::PARENT, + TARGETING::TargetService::IMMEDIATE); + // never found a match... + if (l_parentList.size() != 1) + { + l_target = nullptr; + break; } - // We have made it here so we have found a target that contains - // ATTR_SERIAL_NUMBER and ATTR_PART_NUMBER - //Add the part number to the error log. - ErrlUserDetailsAttribute( l_target, - TARGETING::ATTR_PART_NUMBER).addToLog(this); - //Add the serial number to the error log. - ErrlUserDetailsAttribute( l_target, - TARGETING::ATTR_SERIAL_NUMBER).addToLog(this); + l_target = l_parentList[0]; + l_parentList.clear(); // clear out old entry + } // end while + if( l_target ) + { + // not likely to happen, but just in case... + if( l_attrdata && (l_targetPrev != l_target) ) + { + // got a new target, commit the previous data and start over + l_attrdata->addToLog(this); + delete l_attrdata; + l_attrdata = nullptr; + } + if( !l_attrdata ) + { + l_attrdata = new ErrlUserDetailsAttribute(l_target); + } + l_attrdata->addData(TARGETING::ATTR_ECID); + l_targetPrev = l_target; + } - }while( 0 ); + if( l_attrdata ) + { + l_attrdata->addToLog(this); + delete l_attrdata; + } - TRACDCOMP(g_trac_errl, EXIT_MRK"ErrlEntry::addPartAndSerialNumbersToErrLog()"); + TRACDCOMP(g_trac_errl, EXIT_MRK"ErrlEntry::addPartIdInfoToErrLog()"); } - +#ifdef CONFIG_BMC_IPMI // Find the FRU ID associated with target. // Returns first FRU ID found as it navigates the target's parent hierarchy TARGETING::ATTR_FRU_ID_type getFRU_ID(TARGETING::Target * i_target) @@ -1154,8 +1097,8 @@ void ErrlEntry::commit( compId_t i_committerComponent ) this); if(!l_err) { + addPartIdInfoToErrLog( l_target ); #ifdef CONFIG_BMC_IPMI - addPartAndSerialNumbersToErrLog( l_target ); addSensorDataToErrLog( l_target, l_ud->priority); #endif } diff --git a/src/usr/errl/errlentry_consts.H b/src/usr/errl/errlentry_consts.H index e6784c217..816738010 100644 --- a/src/usr/errl/errlentry_consts.H +++ b/src/usr/errl/errlentry_consts.H @@ -66,7 +66,6 @@ const epubProcToSub_t PROCEDURE_TO_SUBSYS_TABLE[] = { EPUB_PRC_COOLING_SYSTEM_ERR , EPUB_MISC_SUBSYS }, { EPUB_PRC_FW_VERIFICATION_ERR , EPUB_FIRMWARE_SUBSYS }, { EPUB_PRC_GPU_ISOLATION_PROCEDURE, EPUB_CEC_HDW_SUBSYS }, - { EPUB_PRC_NVDIMM_ERR , EPUB_MEMORY_SUBSYS }, }; struct epubTargetTypeToSub_t @@ -103,6 +102,13 @@ const epubTargetTypeToSub_t TARGET_TO_SUBSYS_TABLE[] = { TARGETING::TYPE_TPM , EPUB_CEC_HDW_SUBSYS }, { TARGETING::TYPE_MC , EPUB_MEMORY_SUBSYS }, { TARGETING::TYPE_SMPGROUP , EPUB_CEC_HDW_SUBSYS }, + { TARGETING::TYPE_OMI , EPUB_MEMORY_SUBSYS }, + { TARGETING::TYPE_MCC , EPUB_MEMORY_SUBSYS }, + { TARGETING::TYPE_OMIC , EPUB_MEMORY_SUBSYS }, + { TARGETING::TYPE_OCMB_CHIP , EPUB_MEMORY_SUBSYS }, + { TARGETING::TYPE_MEM_PORT , EPUB_MEMORY_SUBSYS }, + { TARGETING::TYPE_I2C_MUX , EPUB_CEC_HDW_SUBSYS }, + { TARGETING::TYPE_PMIC , EPUB_MEMORY_SUBSYS }, }; struct epubBusTypeToSub_t @@ -120,6 +126,7 @@ const epubBusTypeToSub_t BUS_TO_SUBSYS_TABLE[] = { HWAS::I2C_BUS_TYPE , EPUB_CEC_HDW_I2C_DEVS }, { HWAS::PSI_BUS_TYPE , EPUB_CEC_HDW_SP_PHYP_INTF }, { HWAS::O_BUS_TYPE , EPUB_PROCESSOR_BUS_CTL }, + { HWAS::OMI_BUS_TYPE , EPUB_MEMORY_BUS }, }; struct epubClockTypeToSub_t @@ -159,6 +166,9 @@ const epubPartTypeToSub_t PART_TO_SUBSYS_TABLE[] = { HWAS::PROC_REF_CLOCK , EPUB_CEC_HDW_CLK_CTL }, { HWAS::PCI_REF_CLOCK , EPUB_CEC_HDW_CLK_CTL }, { HWAS::SMP_CABLE , EPUB_CEC_HDW_SUBSYS }, + { HWAS::BPM_CABLE_PART_TYPE , EPUB_MEMORY_SUBSYS }, + { HWAS::NV_CONTROLLER_PART_TYPE , EPUB_MEMORY_SUBSYS }, + { HWAS::BPM_PART_TYPE , EPUB_MEMORY_SUBSYS }, }; struct epubSensorTypeToSub_t diff --git a/src/usr/errl/errli2c.C b/src/usr/errl/errli2c.C index b3838a866..2c814ca58 100644 --- a/src/usr/errl/errli2c.C +++ b/src/usr/errl/errli2c.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -33,7 +33,6 @@ #include <hwas/common/deconfigGard.H> #include <targeting/common/targetservice.H> #include <targeting/common/utilFilter.H> -#include <config.h> #include <attributeenums.H> #include <i2c/eepromif.H> diff --git a/src/usr/errl/errlmanager.C b/src/usr/errl/errlmanager.C index c32c2b2b7..2e787d2e0 100644 --- a/src/usr/errl/errlmanager.C +++ b/src/usr/errl/errlmanager.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2018 */ +/* Contributors Listed Below - COPYRIGHT 2011,2019 */ /* [+] Google Inc. */ /* [+] International Business Machines Corp. */ /* */ @@ -50,15 +50,18 @@ #include <arch/pirformat.H> #include <errldisplay/errldisplay.H> #include <console/consoleif.H> -#include <config.h> #include <functional> #include <hwas/common/deconfigGard.H> #include <kernel/terminate.H> #include <debugpointers.H> +#include <sys/sync.h> namespace ERRORLOG { +// Used in VERSION partition caching +mutex_t g_errlMutex = MUTEX_INITIALIZER; + extern trace_desc_t* g_trac_errl; #ifdef STORE_ERRL_IN_L3 @@ -103,6 +106,20 @@ bool compareEidToPlid(const uint32_t i_plid, return (i_pair.first->eid() == i_plid); } +const uint8_t* getCachedVersionPartition() +{ + return Singleton<ErrlManager>::instance().getCachedVersionPartition(); +} + +size_t getCachedVersionPartitionSize() +{ + return Singleton<ErrlManager>::instance().getCachedVersionPartitionSize(); +} + +errlHndl_t cacheVersionPartition() +{ + return Singleton<ErrlManager>::instance().cacheVersionPartition(); +} class AtLoadFunctions { @@ -120,6 +137,7 @@ AtLoadFunctions atLoadFunction; /////////////////////////////////////////////////////////////////////////////// ErrlManager::ErrlManager() : iv_pnorReadyForErrorLogs(false), + iv_recvdShutdownEvent(false), iv_hwasProcessCalloutFn(NULL), iv_msgQ(NULL), iv_pnorAddr(NULL), @@ -129,7 +147,9 @@ ErrlManager::ErrlManager() : iv_isMboxEnabled(false), // assume mbox isn't ready yet.. iv_isIpmiEnabled(false), // assume ipmi isn't ready yet.. iv_nonInfoCommitted(false), - iv_isErrlDisplayEnabled(false) + iv_isErrlDisplayEnabled(false), + iv_versionPartitionCache(nullptr), + iv_versionPartitionCacheSize(0) { TRACFCOMP( g_trac_errl, ENTER_MRK "ErrlManager::ErrlManager constructor" ); @@ -270,6 +290,30 @@ void ErrlManager::errlogMsgHndlr () msg_t * theMsg = msg_wait( iv_msgQ ); TRACFCOMP( g_trac_errl, INFO_MRK"Got an error log Msg - Type: 0x%08x", theMsg->type ); + + // if we've been shut down then do nothing except delete the msg or send + // a response depending on the message type. + if(iv_recvdShutdownEvent) + { + TRACFCOMP( g_trac_errl, INFO_MRK "Error log service is shutdown. " + "Message will be ignored."); + switch( theMsg->type ) + { + // Shutdown and flush message types expect a response + case ERRLOG_SHUTDOWN_TYPE: + case ERRLOG_FLUSH_TYPE: + msg_respond ( iv_msgQ, theMsg ); + break; + + // All other messages just need to be freed + default: + msg_free(theMsg); + break; + } + // wait for next message + continue; + } + //Process message just received switch( theMsg->type ) { @@ -1009,6 +1053,9 @@ void ErrlManager::errlogShutdown() // prior to the PNOR resource provider shutting down. PNOR::flush(PNOR::HB_ERRLOGS); + // Remember that we have recieved the shutdown event + iv_recvdShutdownEvent = true; + return; } @@ -1031,4 +1078,118 @@ bool ErrlManager::_updateErrlListIter(ErrlListItr_t & io_it) return l_removed; } +const uint8_t* ErrlManager::getCachedVersionPartition() const +{ + mutex_lock(&g_errlMutex); + const uint8_t* l_versionPtr = iv_versionPartitionCache; + mutex_unlock(&g_errlMutex); + return l_versionPtr; +} + +size_t ErrlManager::getCachedVersionPartitionSize() const +{ + mutex_lock(&g_errlMutex); + size_t l_versionSize = iv_versionPartitionCacheSize; + mutex_unlock(&g_errlMutex); + return l_versionSize; +} + +errlHndl_t ErrlManager::cacheVersionPartition() +{ + errlHndl_t l_errl = nullptr; + bool l_versionPartitionLoaded = false; + + do { + + if(iv_isVersionPartitionCached || + !PNOR::isSectionAvailable(PNOR::VERSION)) + { + // No need to try to cache more than once or if + // there is no VERSION partition + break; + } + +#ifdef CONFIG_SECUREBOOT + l_errl = PNOR::loadSecureSection(PNOR::VERSION); + if(l_errl) + { + TRACFCOMP(g_trac_errl, ERR_MRK"ErrlManager::cacheVersionPartition() - could not load VERSION partition"); + break; + } + + l_versionPartitionLoaded = true; +#endif + + PNOR::SectionInfo_t l_pnorVersionSectionInfo; + l_errl = getSectionInfo(PNOR::VERSION, l_pnorVersionSectionInfo); + if(l_errl) + { + TRACFCOMP(g_trac_errl, ERR_MRK"ErrlManager::cacheVersionPartition() - could not get VERSION section info"); + break; + } + + // Since multiple errls may be at different stages of commit at the same + // time, lock the mutex to prevent atomicity issues + mutex_lock(&g_errlMutex); + + iv_versionPartitionCacheSize = 0; + + const char* l_versionSectionPtr = + reinterpret_cast<char*>(l_pnorVersionSectionInfo.vaddr); + + // The actual size of the text in the VERSION partition is likely to be less + // than the declared size. Calculate the actual size here. + while((l_versionSectionPtr[iv_versionPartitionCacheSize] != '\0') && + (iv_versionPartitionCacheSize < l_pnorVersionSectionInfo.size)) + { + ++iv_versionPartitionCacheSize; + } + iv_versionPartitionCache = new uint8_t[iv_versionPartitionCacheSize]; + + memcpy(const_cast<uint8_t*>(iv_versionPartitionCache), + reinterpret_cast<uint8_t*>(l_pnorVersionSectionInfo.vaddr), + iv_versionPartitionCacheSize); + + mutex_unlock(&g_errlMutex); + + } while(0); + + if(l_versionPartitionLoaded) + { +#ifdef CONFIG_SECUREBOOT + errlHndl_t l_unloadSecErr = PNOR::unloadSecureSection(PNOR::VERSION); + if(l_unloadSecErr) + { + TRACFCOMP(g_trac_errl, ERR_MRK"ErrlManager::cacheVersionPartition() - could not unload VERSION partition"); + if(l_errl) + { + l_unloadSecErr->plid(l_errl->plid()); + errlCommit(l_unloadSecErr, ERRL_COMP_ID); + } + else + { + l_errl = l_unloadSecErr; + l_unloadSecErr = nullptr; + } + } +#endif + } + + if(l_errl) + { + if(iv_versionPartitionCache) + { + delete[] iv_versionPartitionCache; + iv_versionPartitionCache = nullptr; + } + iv_versionPartitionCacheSize = 0; + } + + // Set the cache attrmpted flag regardless of whether we actually + // were able to cache the partition + iv_isVersionPartitionCached = true; + + return l_errl; +} + } // End namespace diff --git a/src/usr/errl/errlmanager_common.C b/src/usr/errl/errlmanager_common.C index e1e965e5a..bd84f2828 100644 --- a/src/usr/errl/errlmanager_common.C +++ b/src/usr/errl/errlmanager_common.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -23,7 +23,6 @@ /* */ /* IBM_PROLOG_END_TAG */ #include <errl/errlmanager.H> -#include <config.h> #include <hwas/common/hwasCallout.H> #include <errl/errlreasoncodes.H> #ifdef CONFIG_BMC_IPMI diff --git a/src/usr/diag/prdf/common/framework/register/iipMopRegisterAccessScanComm.inl b/src/usr/errl/errludattribute.C index ad08084d6..5d031545f 100755..100644 --- a/src/usr/diag/prdf/common/framework/register/iipMopRegisterAccessScanComm.inl +++ b/src/usr/errl/errludattribute.C @@ -1,11 +1,13 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/usr/diag/prdf/common/framework/register/iipMopRegisterAccessScanComm.inl $ */ +/* $Source: src/usr/errl/errludattribute.C $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 1996,2014 */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ @@ -20,48 +22,63 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ +#include <stdint.h> +#include <stdio.h> +#include <string.h> +#include <errl/errludattribute.H> +#include <errl/errlreasoncodes.H> +#include <targeting/common/targetservice.H> +#include <targeting/common/trace.H> -// Module Description ************************************************** -// -// Description: This module provides the inline implementation for the -// PRD MOP Register Access Scan Comm class. -// -// End Module Description ********************************************** - -namespace PRDF +namespace ERRORLOG { +using namespace TARGETING; +extern TARG_TD_t g_trac_errl; -//---------------------------------------------------------------------- -// Includes -//---------------------------------------------------------------------- - -//---------------------------------------------------------------------- -// User Types -//---------------------------------------------------------------------- -//---------------------------------------------------------------------- -// Constants -//---------------------------------------------------------------------- +//------------------------------------------------------------------------------ +ErrlUserDetailsAttribute::ErrlUserDetailsAttribute( + const Target * i_pTarget, uint32_t i_attr) + : iv_pTarget(i_pTarget), iv_dataSize(0) +{ + // Set up ErrlUserDetails instance variables + iv_CompId = ERRL_COMP_ID; + iv_Version = 1; + iv_SubSection = ERRL_UDT_ATTRIBUTE; + // override the default of false + iv_merge = true; -//---------------------------------------------------------------------- -// Macros -//---------------------------------------------------------------------- + // first, write out the HUID + addData(ATTR_HUID); + if (i_attr != ATTR_HUID) { + addData(i_attr); + } +} -//---------------------------------------------------------------------- -// Internal Function Prototypes -//---------------------------------------------------------------------- +//------------------------------------------------------------------------------ +ErrlUserDetailsAttribute::ErrlUserDetailsAttribute( + const Target * i_pTarget) + : iv_pTarget(i_pTarget), iv_dataSize(0) +{ + // Set up ErrlUserDetails instance variables + iv_CompId = ERRL_COMP_ID; + iv_Version = 1; + iv_SubSection = ERRL_UDT_ATTRIBUTE; + // override the default of false + iv_merge = true; -//---------------------------------------------------------------------- -// Global Variables -//---------------------------------------------------------------------- + // first, write out the HUID + addData(ATTR_HUID); +} -//--------------------------------------------------------------------- -// Member Function Specifications -//--------------------------------------------------------------------- +//------------------------------------------------------------------------------ +ErrlUserDetailsAttribute::~ErrlUserDetailsAttribute() +{ } +} // namespace -inline -MopRegisterAccessScanComm::MopRegisterAccessScanComm(void) - { - } +// Pull in the auto-generated portion +// ::addData +// ::dumpAll +// Generated by xmltohb.pl +#include <errludattribute_gen.C> -} // end namespace PRDF diff --git a/src/usr/errl/errludlogregister.C b/src/usr/errl/errludlogregister.C index 0db5aaca9..e908b0d4d 100644 --- a/src/usr/errl/errludlogregister.C +++ b/src/usr/errl/errludlogregister.C @@ -223,6 +223,7 @@ void ErrlUserDetailsLogRegister::copyRegisterData( case DeviceFW::SCOM: // userif.H case DeviceFW::FSI: // userif.H case DeviceFW::SPD: // userif.H + case DeviceFW::NVDIMM: // userif.H case DeviceFW::XSCOM: // driverif.H case DeviceFW::FSISCOM: // driverif.H case DeviceFW::IBSCOM: // driverif.H diff --git a/src/usr/errl/parser/genErrlParsers.pl b/src/usr/errl/parser/genErrlParsers.pl index 19be84266..2ae0282e5 100755 --- a/src/usr/errl/parser/genErrlParsers.pl +++ b/src/usr/errl/parser/genErrlParsers.pl @@ -996,9 +996,9 @@ close(SUBSYSTEM_TYPES_FILE); # Generate a list of all possible SRCs and their descriptions # ------------------------------------------------------------------ open(OFILE, ">", $srcFileName) or die ("Cannot open: $srcFileName: $!"); -foreach my $sub (sort keys %subsysList) +foreach my $rcVal (sort keys %srcList) { - foreach my $rcVal (sort keys %srcList) + foreach my $sub (sort keys %subsysList) { my $src = "BC$sub$rcVal"; print OFILE "//////////////////////////////////////////////////////\n"; diff --git a/src/usr/errl/parser/makefile b/src/usr/errl/parser/makefile index 905e4e6fd..8db2fc0fc 100644 --- a/src/usr/errl/parser/makefile +++ b/src/usr/errl/parser/makefile @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2011,2016 +# Contributors Listed Below - COPYRIGHT 2011,2019 # [+] Google Inc. # [+] International Business Machines Corp. # diff --git a/src/usr/errl/plugins/errludattributeP.H b/src/usr/errl/plugins/errludattributeP.H new file mode 100644 index 000000000..d097ad9e7 --- /dev/null +++ b/src/usr/errl/plugins/errludattributeP.H @@ -0,0 +1,41 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/errl/plugins/errludattributeP.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef ERRL_UDATTRIBUTEP_H +#define ERRL_UDATTRIBUTEP_H + +/** + * Defines the classes that allow you to parse attribute data + * that was previously saved to an error log with + * ERRORLOG::ErrlUserDetailsAttribute. + */ + +#include "errluserdetails.H" + +// Pull in the auto-generated portion for the parser +// Created by xmltohb.pl +#include <errludattributeP_gen.H> + + +#endif // ERRL_UDATTRIBUTEP_H diff --git a/src/usr/errl/plugins/errludbacktrace.H b/src/usr/errl/plugins/errludbacktrace.H index 898ea8faa..9ecc11511 100644 --- a/src/usr/errl/plugins/errludbacktrace.H +++ b/src/usr/errl/plugins/errludbacktrace.H @@ -5,7 +5,10 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ +/* [+] International Business Machines Corp. */ +/* [+] YADRO */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ @@ -113,7 +116,7 @@ public: for( int i = 0; i < l_count; i++ ) { // endian convert the stack address - uint64_t l_addr = ntohll(*p64); + uint64_t l_addr = ntohll(UINT64_FROM_PTR(p64)); // get nearest symbol const char * l_pSymbol = symTab.nearestSymbol( l_addr ); diff --git a/src/usr/errl/plugins/errludcallout.H b/src/usr/errl/plugins/errludcallout.H index fc45e5590..47cbfd9fd 100644 --- a/src/usr/errl/plugins/errludcallout.H +++ b/src/usr/errl/plugins/errludcallout.H @@ -210,6 +210,7 @@ case HWAS::_type: i_parser.PrintString( "Bus Type", #_type); break; case_BUS_TYPE(I2C_BUS_TYPE) case_BUS_TYPE(PSI_BUS_TYPE) case_BUS_TYPE(O_BUS_TYPE) + case_BUS_TYPE(OMI_BUS_TYPE) default: i_parser.PrintNumber( "Bus Type", "UNKNOWN: 0x%X", ntohl(pData->busType) ); diff --git a/src/usr/errl/plugins/errludlogregister.H b/src/usr/errl/plugins/errludlogregister.H index f795a9643..221458022 100644 --- a/src/usr/errl/plugins/errludlogregister.H +++ b/src/usr/errl/plugins/errludlogregister.H @@ -5,9 +5,10 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2014 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] Google Inc. */ /* [+] International Business Machines Corp. */ +/* [+] YADRO */ /* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ @@ -79,7 +80,7 @@ public: { // first is the HUID uint32_t *pData = reinterpret_cast<uint32_t *>(pBuf); - if (ntohl(*pData) == 0xFFFFFFFF) + if (ntohl(UINT32_FROM_PTR(pData)) == 0xFFFFFFFF) { i_parser.PrintString("LogRegister", "Target: MASTER_PROCESSOR_CHIP_TARGET_SENTINEL"); @@ -87,7 +88,7 @@ public: else { i_parser.PrintNumber( "LogRegister", - "Target: HUID = 0x%08X", ntohl(*pData) ); + "Target: HUID = 0x%08X", ntohl(UINT32_FROM_PTR(pData)) ); } pData++; pBuf += sizeof(*pData); @@ -122,6 +123,11 @@ public: numArgs = 1; addrParams.push_back(" SPD keyword enumaration"); break; + case DeviceFW::NVDIMM: // userif.H + i_parser.PrintString("AccessType", "DeviceFW::NVDIMM"); + numArgs = 1; + addrParams.push_back(" NVDIMM address"); + break; case DeviceFW::XSCOM: // driverif.H i_parser.PrintString("AccessType", "DeviceFW::XSCOM"); numArgs = 1; @@ -199,7 +205,7 @@ public: for (int32_t i = 0;i < numArgs;i++) { std::vector<char> l_traceEntry(20); - sprintf(&(l_traceEntry[0]),"0x%016llX", ntohll(*pData64)); + sprintf(&(l_traceEntry[0]),"0x%016llX", ntohll(UINT64_FROM_PTR(pData64))); i_parser.PrintString(addrParams[i], &(l_traceEntry[0])); pData64++; diff --git a/src/usr/errl/plugins/errludparser.H b/src/usr/errl/plugins/errludparser.H index ddaadade7..6957d4632 100755 --- a/src/usr/errl/plugins/errludparser.H +++ b/src/usr/errl/plugins/errludparser.H @@ -5,8 +5,9 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2018 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ +/* [+] YADRO */ /* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ @@ -84,6 +85,7 @@ static bool myDataParse(\ {\ l_rc = true;\ l_pParser->parse(i_ver, i_parser, i_buffer, i_buflen);\ + delete l_pParser;\ }\ return l_rc;\ }\ diff --git a/src/usr/errl/plugins/errludparserfactoryerrl.H b/src/usr/errl/plugins/errludparserfactoryerrl.H index fbefe231f..d5999c807 100644 --- a/src/usr/errl/plugins/errludparserfactoryerrl.H +++ b/src/usr/errl/plugins/errludparserfactoryerrl.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2018 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -34,7 +34,7 @@ #include "errludstring.H" #include "errludtarget.H" #include "errludbacktrace.H" -#include "errludattribute.H" +#include "errludattributeP.H" #include "errludlogregister.H" #include "errludcallout.H" #include "errludsensor.H" diff --git a/src/usr/errl/plugins/errludwofdata.H b/src/usr/errl/plugins/errludwofdata.H index f792c5485..203a4a14e 100644 --- a/src/usr/errl/plugins/errludwofdata.H +++ b/src/usr/errl/plugins/errludwofdata.H @@ -5,8 +5,9 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017,2018 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ +/* [+] YADRO */ /* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ @@ -98,7 +99,7 @@ public: // addWofCompareDataToErrl() in plat_wof_access.C if ((NULL != i_pBuffer) && (i_buflen >= sizeof(tableEntries))) { - tableEntries = ntohs(*(reinterpret_cast<uint16_t*>(i_pBuffer))); + tableEntries = ntohs(UINT16_FROM_PTR(i_pBuffer)); } // How many entries are really present in this buffer? diff --git a/src/usr/errl/plugins/errluserdetails.H b/src/usr/errl/plugins/errluserdetails.H index 917dcf266..eac453505 100755 --- a/src/usr/errl/plugins/errluserdetails.H +++ b/src/usr/errl/plugins/errluserdetails.H @@ -5,8 +5,9 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2018 */ +/* Contributors Listed Below - COPYRIGHT 2011,2019 */ /* [+] International Business Machines Corp. */ +/* [+] YADRO */ /* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ @@ -39,6 +40,88 @@ namespace ERRORLOG { /** + * @struct UnalignedData + * @brief Structure used for safe assigment from unaligned pointer, it forces + * the compiler to generate extra instructions and satisfy architectural + * alignment requirements. + */ +template<typename T> struct UnalignedData { + T value; +} __attribute__ ((packed)); + +/** + * @brief Read integral value from unaligned pointer. + * + * @param[in] i_pUint64 - Pointer to uint64_t value + * + * @return uint64_t value from specified pointer + */ +inline uint64_t UINT64_FROM_PTR(const void* i_pUint64) +{ + return reinterpret_cast<const UnalignedData<uint64_t>*>(i_pUint64)->value; +} + +/** + * @brief Read integral value from unaligned pointer. + * + * @param[in] i_pUint32 - Pointer to uint32_t value + * + * @return uint32_t value from specified pointer + */ +inline uint32_t UINT32_FROM_PTR(const void* i_pUint32) +{ + return reinterpret_cast<const UnalignedData<uint32_t>*>(i_pUint32)->value; +} + +/** + * @brief Read integral value from unaligned pointer. + * + * @param[in] i_pUint16 - Pointer to uint16_t value + * + * @return uint16_t value from specified pointer + */ +inline uint16_t UINT16_FROM_PTR(const void* i_pUint16) +{ + return reinterpret_cast<const UnalignedData<uint16_t>*>(i_pUint16)->value; +} + +/** + * @brief Read integral value from unaligned pointer. + * + * @param[in] i_pInt64 - Pointer to int64_t value + * + * @return int64_t value from specified pointer + */ +inline int64_t INT64_FROM_PTR(const void* i_pInt64) +{ + return reinterpret_cast<const UnalignedData<int64_t>*>(i_pInt64)->value; +} + +/** + * @brief Read integral value from unaligned pointer. + * + * @param[in] i_pInt32 - Pointer to int32_t value + * + * @return int32_t value from specified pointer + */ +inline int32_t INT32_FROM_PTR(const void* i_pInt32) +{ + return reinterpret_cast<const UnalignedData<int32_t>*>(i_pInt32)->value; +} + +/** + * @brief Read integral value from unaligned pointer. + * + * @param[in] i_pInt16 - Pointer to int16_t value + * + * @return int16_t value from specified pointer + */ +inline int16_t INT16_FROM_PTR(const void* i_pInt16) +{ + return reinterpret_cast<const UnalignedData<int16_t>*>(i_pInt16)->value; +} + +/** * @brief Returns the uint64_t at the pointed to location in host byte order * * @param[in] i_pUint64 Pointer to a uint64_t in network byte order @@ -47,7 +130,7 @@ namespace ERRORLOG */ inline uint64_t NTH_UINT64(const void* i_pUint64) { - return (ntohll(*(reinterpret_cast<const uint64_t*>(i_pUint64)))); + return (ntohll(UINT64_FROM_PTR(i_pUint64))); } /** @@ -59,7 +142,7 @@ inline uint64_t NTH_UINT64(const void* i_pUint64) */ inline uint32_t NTH_UINT32(const void* i_pUint32) { - return (ntohl(*(reinterpret_cast<const uint32_t*>(i_pUint32)))); + return (ntohl(UINT32_FROM_PTR(i_pUint32))); } /** @@ -71,7 +154,7 @@ inline uint32_t NTH_UINT32(const void* i_pUint32) */ inline uint16_t NTH_UINT16(const void* i_pUint16) { - return (ntohs(*(reinterpret_cast<const uint16_t*>(i_pUint16)))); + return (ntohs(UINT16_FROM_PTR(i_pUint16))); } /** diff --git a/src/usr/errl/runtime/rt_errlmanager.C b/src/usr/errl/runtime/rt_errlmanager.C index 9fb624608..e545641bb 100644 --- a/src/usr/errl/runtime/rt_errlmanager.C +++ b/src/usr/errl/runtime/rt_errlmanager.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2018 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -47,6 +47,8 @@ uint8_t ErrlManager::iv_hiddenErrLogsEnable = extern trace_desc_t* g_trac_errl; +// Maximum size of error log that can be sent to the host +const uint32_t MAX_FSP_ERROR_LOG_LENGTH = 4096; ////////////////////////////////////////////////////////////////////////////// @@ -188,10 +190,14 @@ void ErrlManager::sendMboxMsg ( errlHndl_t& io_err ) if(g_hostInterfaces) { uint32_t l_msgSize = io_err->flattenedSize(); + if (l_msgSize > MAX_FSP_ERROR_LOG_LENGTH) + { + l_msgSize = MAX_FSP_ERROR_LOG_LENGTH; + } if (g_hostInterfaces->sendErrorLog) { uint8_t * temp_buff = new uint8_t [l_msgSize ]; - io_err->flatten ( temp_buff, l_msgSize ); + io_err->flatten ( temp_buff, l_msgSize, true /* truncate */ ); size_t rc = g_hostInterfaces->sendErrorLog(io_err->plid(), l_msgSize, diff --git a/src/usr/errl/runtime/test/test_runtimeDeconfig.H b/src/usr/errl/runtime/test/test_runtimeDeconfig.H index 2f5d37259..0cf1a0a52 100644 --- a/src/usr/errl/runtime/test/test_runtimeDeconfig.H +++ b/src/usr/errl/runtime/test/test_runtimeDeconfig.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -51,8 +51,8 @@ class deconfigureTargetAtRuntimeTest : public CxxTest::TestSuite // pass in a null target pointer TARGETING::Target * l_target = nullptr; - errlHndl_t l_errl = - HWAS::theDeconfigGard().deconfigureTargetAtRuntime( + errlHndl_t l_errl = nullptr; + l_errl = HWAS::theDeconfigGard().deconfigureTargetAtRuntime( l_target, HWAS::DeconfigGard::FULLY_AT_RUNTIME, l_errl); @@ -118,8 +118,8 @@ class deconfigureTargetAtRuntimeTest : public CxxTest::TestSuite l_target = l_cores.at(0); - errlHndl_t l_errl = - HWAS::theDeconfigGard().deconfigureTargetAtRuntime( + errlHndl_t l_errl = nullptr; + l_errl = HWAS::theDeconfigGard().deconfigureTargetAtRuntime( l_target, HWAS::DeconfigGard::SPEC_DECONFIG, l_errl); @@ -179,8 +179,8 @@ class deconfigureTargetAtRuntimeTest : public CxxTest::TestSuite TARGETING::Target * l_target = l_proc.at(0); - errlHndl_t l_errl = - HWAS::theDeconfigGard().deconfigureTargetAtRuntime( + errlHndl_t l_errl = nullptr; + l_errl = HWAS::theDeconfigGard().deconfigureTargetAtRuntime( l_target, HWAS::DeconfigGard::FULLY_AT_RUNTIME, l_errl); diff --git a/src/usr/errl/test/errltest.H b/src/usr/errl/test/errltest.H index ff5df6b65..32e798ac4 100644 --- a/src/usr/errl/test/errltest.H +++ b/src/usr/errl/test/errltest.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2018 */ +/* Contributors Listed Below - COPYRIGHT 2011,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -1214,6 +1214,57 @@ public: l_err = NULL; } + /** + * @brief Ensure all callouts have a SUBSYS mapping + * + */ + void testErrl_ensureSubsystemMapping(void) + { + // dummy log to call non-static methods with + errlHndl_t l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_INFORMATIONAL, + ERRORLOG::ERRL_TEST_MOD_ID, + ERRORLOG::ERRL_TEST_REASON_CODE, + 0x494E464F, //INFO + 0); + + // Walk through every BUS_TYPE + for( busTypeEnum bus = (busTypeEnum)(NO_BUS_TYPE+1); + bus < LAST_BUS_TYPE; + bus = (busTypeEnum)(bus+1) ) + { + if( l_err->getSubSystem(bus) == EPUB_MISC_UNKNOWN ) + { + TS_FAIL( "No subsystem returned for BUS_TYPE %d", bus ); + } + } + + // Walk through every PART_TYPE + for( partTypeEnum part = (partTypeEnum)(NO_PART_TYPE+1); + part < LAST_PART_TYPE; + part = (partTypeEnum)(part+1) ) + { + if( l_err->getSubSystem(part) == EPUB_MISC_UNKNOWN ) + { + TS_FAIL( "No subsystem returned for PART_TYPE %d", part ); + } + } + + // Walk through every SENSOR_TYPE + for( sensorTypeEnum sensor = (sensorTypeEnum)(UNKNOWN_SENSOR+1); + sensor < LAST_SENSOR_TYPE; + sensor = (sensorTypeEnum)(sensor+1) ) + { + if( l_err->getSubSystem(sensor) == EPUB_MISC_UNKNOWN ) + { + TS_FAIL( "No subsystem returned for SENSOR_TYPE %d", sensor ); + } + } + + // Note - Can't loop over epubProcedureID because the values are + // sparsely populated + + } }; diff --git a/src/usr/errldisplay/errldisplay.C b/src/usr/errldisplay/errldisplay.C index b8c26614e..3f04618cd 100644 --- a/src/usr/errldisplay/errldisplay.C +++ b/src/usr/errldisplay/errldisplay.C @@ -67,6 +67,7 @@ #include <targeting/common/targetservice.H> #include <targeting/common/iterators/targetiterator.H> #include <targeting/common/target.H> +#include <arch/ppc.H> #ifdef CONFIG_CONSOLE_OUTPUT_FFDCDISPLAY //Generated hearder files for HWP parsing @@ -325,6 +326,7 @@ case HWAS::_type: CONSOLE::displayf(NULL, " Bus Type : %s", #_t case_BUS_TYPE(I2C_BUS_TYPE) case_BUS_TYPE(PSI_BUS_TYPE) case_BUS_TYPE(O_BUS_TYPE) + case_BUS_TYPE(OMI_BUS_TYPE) default: CONSOLE::displayf(NULL, " Bus Type : UNKNOWN 0x%X", callout->busType); @@ -338,7 +340,6 @@ case HWAS::_type: CONSOLE::displayf(NULL, " Bus Type : %s", #_t case HWAS::HW_CALLOUT: CONSOLE::displayf(NULL, " Callout type : Hardware Callout"); - CONSOLE::displayf(NULL, " CPU id : %d", callout->cpuid); displayGard = true; l_gard = callout->gardErrorType; @@ -675,9 +676,9 @@ void ErrLogDisplay::msgDisplay (const errlHndl_t &i_err, CONSOLE::displayf(NULL, "================================================"); - CONSOLE::displayf(NULL, "Error reported by %s (0x%04X) PLID 0x%08X", + CONSOLE::displayf(NULL, "Error reported by %s (0x%04X) EID 0x%08X", findComponentName( i_committerComp ), - i_committerComp, i_err->plid() ); + i_committerComp, i_err->eid() ); //PRD doesn't follow the rest of the HB conventions // Handle them special @@ -709,7 +710,7 @@ void ErrLogDisplay::msgDisplay (const errlHndl_t &i_err, displayHwpf( user_data->iv_pData, user_data->iv_Size, user_data->iv_header.iv_sst); } - else + else if(user_data->iv_header.iv_compId == ERRL_COMP_ID) { switch ( user_data->iv_header.iv_sst ) { diff --git a/src/usr/errldisplay/makefile b/src/usr/errldisplay/makefile index b094bfc63..a2fe4c9e4 100644 --- a/src/usr/errldisplay/makefile +++ b/src/usr/errldisplay/makefile @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2013,2017 +# Contributors Listed Below - COPYRIGHT 2013,2019 # [+] Google Inc. # [+] International Business Machines Corp. # @@ -48,3 +48,4 @@ EXTRAINCDIR += ${GENDIR}/plugins/prdf/ EXTRAINCDIR += ${ROOTPATH}/src/usr/diag/prdf/plugins/ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/common/include/ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/centaur/common/include/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/explorer/common/include/ diff --git a/src/usr/expaccess/errlud_expscom.C b/src/usr/expaccess/errlud_expscom.C new file mode 100644 index 000000000..7480b9887 --- /dev/null +++ b/src/usr/expaccess/errlud_expscom.C @@ -0,0 +1,216 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/expaccess/errlud_expscom.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/** + * @file errlud_expscom.C + * @brief Utility to add Explorer logs to your hostboot error + */ +#include "errlud_expscom.H" +#include "expscom_trace.H" +#include <errl/hberrltypes.H> // pelSectionHeader_t +#include <exp_fw_log_data.H> // explorer log gathering tools +#include <fapi2/plat_hwp_invoker.H> // FAPI_INVOKE_HWP +#include <expscom/expscom_reasoncodes.H> // user-detail subsections +#include <errl/errlmanager.H> // errlCommit + +using namespace EXPSCOM; + +// Main function to add Explorer logs to a HB error log +bool EXPSCOM::expAddLog( const exp_log_type i_type, + TARGETING::Target * i_ocmb, + errlHndl_t & io_errl ) +{ + bool l_logsAdded = false; + explog_section_header_t l_header; // use 0 defaults + + // Meta data included with each section + const uint32_t META_SECTION_SIZE = sizeof(l_header) + + sizeof(ERRORLOG::pelSectionHeader_t); + + // @todo RTC 214628 + // Hopefully create a way to tell how much room is left in io_errl + uint32_t l_bytesAvailableInLog = 4 * KILOBYTE; + + if (l_bytesAvailableInLog > META_SECTION_SIZE) + { + errlHndl_t l_errl = nullptr; + std::vector<uint8_t>l_error_log_data; // explorer error entry data + fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> l_fapi_ocmb_target(i_ocmb); + + // Make HWP call to grab explorer error log data + if (i_type == EXPSCOM::ACTIVE_LOG) + { + TRACFCOMP( g_trac_expscom, INFO_MRK "FAPI_INVOKE_HWP exp_active_error_log"); + FAPI_INVOKE_HWP( l_errl, exp_active_log, + l_fapi_ocmb_target, l_error_log_data ); + } + else + { + TRACFCOMP( g_trac_expscom, INFO_MRK "FAPI_INVOKE_HWP exp_saved_error_log"); + FAPI_INVOKE_HWP( l_errl, exp_saved_log, + l_fapi_ocmb_target, l_error_log_data ); + } + + if (l_errl) + { + // Unable to grab explorer error log data + TRACFCOMP( g_trac_expscom, ERR_MRK "Unable to grab explorer error log data"); + l_errl->collectTrace(EXPSCOM_COMP_NAME); + + // This error is not a system critical failure, should be just noted + l_errl->setSev(ERRORLOG::ERRL_SEV_INFORMATIONAL); + + // Associate this error with the original explorer failure log + l_errl->plid(io_errl->plid()); + errlCommit(l_errl, EXPSCOM_COMP_ID); + } + else + { + // Cycle through data and add sections to io_errl + // Most recent error log entries are at the end of the data returned + // so need to work backwards from the end + l_header.error_data_size = FIRST_EXPLORER_DATA_SECTION_SIZE; + uint32_t l_explorer_bytes_left = l_error_log_data.size(); + uint8_t * l_end_ptr = l_error_log_data.data() + l_explorer_bytes_left; + + // while explorer data to append + while (l_explorer_bytes_left && l_bytesAvailableInLog) + { + // Can we add a full packet size of error data? + if (l_bytesAvailableInLog > (l_header.error_data_size + META_SECTION_SIZE)) + { + // Check if we don't have full packet of explorer error data + if (l_explorer_bytes_left < l_header.error_data_size) + { + // Reduce the packet size to include the last of explorer error data + l_header.error_data_size = l_explorer_bytes_left; + } + } + else if ( l_bytesAvailableInLog > META_SECTION_SIZE ) // Any room left for another section? + { + // Is there enough explorer error data for room available? + if ( l_explorer_bytes_left >= + (l_bytesAvailableInLog - META_SECTION_SIZE) ) + { + // Not enough room is available for all the remaining explorer error data + // Use up the rest of the space available + l_header.error_data_size = l_bytesAvailableInLog - META_SECTION_SIZE; + } + else + { + // Room is available but not enough explorer data for full packet size + // Reduce the packet size to include the last of explorer error data + l_header.error_data_size = l_explorer_bytes_left; + } + } + else + { + // No more space available in hostboot error log + break; + } + + // Offset into explorer error log data returned + l_header.offset_exp_log = l_explorer_bytes_left - + l_header.error_data_size; + + // Add the section entry to the HWP error log + if ( i_type == EXPSCOM::ACTIVE_LOG ) + { + ExpscomActiveLogUD(l_header, (l_end_ptr - l_header.error_data_size)). + addToLog(io_errl); + } + else + { + ExpscomSavedLogUD(l_header, (l_end_ptr - l_header.error_data_size)). + addToLog(io_errl); + } + l_logsAdded = true; + + // Update to next packet of Explorer error log data + l_end_ptr -= l_header.error_data_size; // update to always be the tail of data to add + l_header.packet_num++; + l_explorer_bytes_left -= l_header.error_data_size; + l_bytesAvailableInLog -= (META_SECTION_SIZE + l_header.error_data_size); + l_header.error_data_size = FOLLOWING_EXPLORER_DATA_SECTION_SIZE; + } + } + } + else + { + TRACFCOMP( g_trac_expscom, INFO_MRK + "expAddErrorLog: Unable to add any %d type error logs," + " only have %d bytes available in log", i_type, l_bytesAvailableInLog ); + } + return l_logsAdded; +} + +//------------------------------------------------------------------------------ +// Expscom Active Log User Details +//------------------------------------------------------------------------------ +ExpscomActiveLogUD::ExpscomActiveLogUD( + const explog_section_header_t & i_header_info, + const uint8_t * i_data_portion ) +{ + // Set up Ud instance variables + iv_CompId = EXPSCOM_COMP_ID; + iv_Version = 1; + iv_SubSection = EXPSCOM_UDT_ACTIVE_LOG; + + uint8_t * l_pBuf = reallocUsrBuf( sizeof(i_header_info) + + i_header_info.error_data_size ); + + memcpy(l_pBuf, &i_header_info, sizeof(i_header_info)); + l_pBuf += sizeof(i_header_info); + memcpy(l_pBuf, i_data_portion, i_header_info.error_data_size); + l_pBuf += i_header_info.error_data_size; +} + +ExpscomActiveLogUD::~ExpscomActiveLogUD() +{ +} + +//------------------------------------------------------------------------------ +// Expscom Saved Log User Details +//------------------------------------------------------------------------------ +ExpscomSavedLogUD::ExpscomSavedLogUD( + const explog_section_header_t & i_header_info, + const uint8_t * i_data_portion ) +{ + // Set up Ud instance variables + iv_CompId = EXPSCOM_COMP_ID; + iv_Version = 1; + iv_SubSection = EXPSCOM_UDT_SAVED_LOG; + + uint8_t * l_pBuf = reallocUsrBuf( sizeof(i_header_info) + + i_header_info.error_data_size ); + + memcpy(l_pBuf, &i_header_info, sizeof(i_header_info)); + l_pBuf += sizeof(i_header_info); + memcpy(l_pBuf, i_data_portion, i_header_info.error_data_size); + l_pBuf += i_header_info.error_data_size; +} + +ExpscomSavedLogUD::~ExpscomSavedLogUD() +{ +} diff --git a/src/usr/expaccess/errlud_expscom.H b/src/usr/expaccess/errlud_expscom.H new file mode 100644 index 000000000..acb17bc2c --- /dev/null +++ b/src/usr/expaccess/errlud_expscom.H @@ -0,0 +1,160 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/expaccess/errlud_expscom.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +#ifndef __ERRLUD_EXPSCOM_H +#define __ERRLUD_EXPSCOM_H + +/** + * @file errlud_expscom.H + * @brief Utility functions to add Explorer logs to your hostboot error + */ +#include <stdint.h> + +#include <errl/errluserdetails.H> + +// targeting support +#include <targeting/common/commontargeting.H> +#include <targeting/common/utilFilter.H> + +namespace EXPSCOM +{ +/** + * @brief Enum for what kind of Explorer log + */ +enum exp_log_type : uint8_t +{ + ACTIVE_LOG = 1, // RAM error section + SAVED_LOG = 2 // SPI flash error section +}; + +/** + * @brief Adds Explorer log data to platform log + * Grabs explorer error log based on type and then breaks that data + * into smaller user-data sections adding them to the platform log. + * Note: First section will be the smallest and contain the most recent + * trace data. Probably contains most relevent traces, so try to make + * always fit in the error log. + * @param i_type - what kind of explorer error log to add + * @param i_ocmb - Explorer target + * @param io_errl - Platform error log to add logs into + * @return true if explorer error data added, else false + */ +bool expAddLog( const exp_log_type i_type, + TARGETING::Target * i_ocmb, + errlHndl_t & io_errl ); + + + +/** + * @brief Header data of every explorer error log user-data section + */ +struct explog_section_header_t +{ + uint16_t packet_num; // ordering byte (0 = first packet) + uint32_t offset_exp_log; // offset where data portion started in full explorer log + uint16_t error_data_size; // size of data portion following header + + explog_section_header_t() + : packet_num(0), + offset_exp_log(0), + error_data_size(0) + {} +} __attribute__((__packed__)); + +// Break large explorer log data into smaller error sections +// to avoid dropping important debug data. +// Make most important first section smaller so this won't get dropped +const uint16_t FIRST_EXPLORER_DATA_SECTION_SIZE = 0x0100; +const uint16_t FOLLOWING_EXPLORER_DATA_SECTION_SIZE = 0x0200; + + +/** + * @class ExpscomActiveLogUD + * + * Adds Explorer Active log information to an error log as user detail + * Data is from Explorer RAM + * + */ +class ExpscomActiveLogUD : public ERRORLOG::ErrlUserDetails +{ + public: + /** + * @brief Constructor + * + * @param i_header_info Meta information added to beginning of section + * @param i_data_portion Pointer to portion of Active log data + * + */ + ExpscomActiveLogUD( const explog_section_header_t & i_header_info, + const uint8_t * i_data_portion ); + + /** + * @brief Destructor + */ + virtual ~ExpscomActiveLogUD(); + + // Disabled + ExpscomActiveLogUD() = delete; + ExpscomActiveLogUD(ExpscomActiveLogUD &) = delete; + ExpscomActiveLogUD & operator=(ExpscomActiveLogUD &) = delete; +}; + + + + +/** + * @class ExpscomSavedLogUD + * + * Adds Explorer Saved log information to an error log as user detail + * Data is from Explorer SPI flash + * + */ +class ExpscomSavedLogUD : public ERRORLOG::ErrlUserDetails +{ + public: + /** + * @brief Constructor + * + * @param i_header_info Meta information added to beginning of section + * @param i_data_portion Pointer to portion of Saved error data + * + */ + ExpscomSavedLogUD( const explog_section_header_t & i_header_info, + const uint8_t * i_data_portion ); + + /** + * @brief Destructor + */ + virtual ~ExpscomSavedLogUD(); + + // Disabled + ExpscomSavedLogUD() = delete; + ExpscomSavedLogUD(ExpscomSavedLogUD &) = delete; + ExpscomSavedLogUD & operator=(ExpscomSavedLogUD &) = delete; +}; + +} + +#endif diff --git a/src/usr/expaccess/expaccess.mk b/src/usr/expaccess/expaccess.mk index 84835c522..d4431e0cd 100644 --- a/src/usr/expaccess/expaccess.mk +++ b/src/usr/expaccess/expaccess.mk @@ -25,14 +25,20 @@ EXTRAINCDIR += ${ROOTPATH}/src/import EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/explorer/common/include/ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/explorer/procedures/hwp/memory/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/inband/ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/utils/imageProcs EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/procedures/hwp/ffdc/ EXTRAINCDIR += ${ROOTPATH}/src/import/hwpf/fapi2/include EXTRAINCDIR += ${ROOTPATH}/src/include/usr/fapi2 -# Need to build exp_indband to use EKB's getMMIO/putMMIO/getCMD/getRSP +VPATH += ${ROOTPATH}/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/inband/ + +# Need to build exp_inband to use EKB's getMMIO/putMMIO/getCMD/getRSP OBJS += exp_inband.o OBJS += expscom_trace.o OBJS += expscom_utils.o OBJS += i2cscomdd.o -OBJS += mmioscomdd.o
\ No newline at end of file +OBJS += mmioscomdd.o +OBJS += exp_fw_log.o +OBJS += exp_fw_log_data.o +OBJS += errlud_expscom.o diff --git a/src/usr/expaccess/expscom_utils.C b/src/usr/expaccess/expscom_utils.C index 5ea7eeeb2..c4818379c 100644 --- a/src/usr/expaccess/expscom_utils.C +++ b/src/usr/expaccess/expscom_utils.C @@ -55,20 +55,21 @@ errlHndl_t validateInputs(DeviceFW::OperationType i_opType, errlHndl_t l_err = nullptr; uint32_t l_commonPlid = 0; // If there are multiple issues found link logs with first - TARGETING::ATTR_MODEL_type l_targetModel = - i_target->getAttr<TARGETING::ATTR_MODEL>(); + // Verify that the target is of type OCMB_CHIP + TARGETING::ATTR_TYPE_type l_targetType = + i_target->getAttr<TARGETING::ATTR_TYPE>(); - // Only target we can perform ocmb scoms on are explorer OCMB chip targets - if( l_targetModel != TARGETING::MODEL_EXPLORER ) + // Only target we can perform ocmb scoms on are OCMB chip targets + if( l_targetType != TARGETING::TYPE_OCMB_CHIP ) { - TRACFCOMP( g_trac_expscom, ERR_MRK "validateInputs> Invalid target type : l_targetModel=%d", l_targetModel ); + TRACFCOMP( g_trac_expscom, ERR_MRK "validateInputs> Invalid target type : l_targetType=0x%X", l_targetType ); /*@ * @errortype * @moduleid EXPSCOM::MOD_OCMB_UTILS * @reasoncode EXPSCOM::RC_INVALID_MODEL_TYPE * @userdata1 SCOM Address * @userdata2 Model Type - * @devdesc validateInputs> Invalid target type (!= OCMB_CHP) + * @devdesc validateInputs> Invalid target type (!= OCMB_CHIP) * @custdesc A problem occurred during the IPL of the system: * Invalid target type for a SCOM operation. */ @@ -76,7 +77,7 @@ errlHndl_t validateInputs(DeviceFW::OperationType i_opType, EXPSCOM::MOD_OCMB_UTILS, EXPSCOM::RC_INVALID_MODEL_TYPE, i_scomAddr, - l_targetModel, + l_targetType, ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); l_err->collectTrace(EXPSCOM_COMP_NAME); diff --git a/src/usr/expaccess/mmioscomdd.C b/src/usr/expaccess/mmioscomdd.C index bf4513158..00feb38d4 100644 --- a/src/usr/expaccess/mmioscomdd.C +++ b/src/usr/expaccess/mmioscomdd.C @@ -31,7 +31,7 @@ /*****************************************************************************/ // I n c l u d e s /*****************************************************************************/ -#include <exp_inband.H> // mmio_get_scom +#include <lib/inband/exp_inband.H> // mmio_get_scom #include <lib/shared/exp_consts.H> // IBM_SCOM_INDICATOR #include <hwpf/fapi2/include/fapi2_hwp_executor.H>// FAPI_EXEC_HWP #include "mmioscomdd.H" //mmioScomPerformOp diff --git a/src/usr/diag/prdf/common/util/iipbits.h b/src/usr/expaccess/plugins/EXPSCOM_COMP_ID_Parse.C index 7b02e52f3..54bf595b6 100755..100644 --- a/src/usr/diag/prdf/common/util/iipbits.h +++ b/src/usr/expaccess/plugins/EXPSCOM_COMP_ID_Parse.C @@ -1,11 +1,13 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/usr/diag/prdf/common/util/iipbits.h $ */ +/* $Source: src/usr/expaccess/plugins/EXPSCOM_COMP_ID_Parse.C $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 1993,2014 */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ @@ -20,5 +22,11 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ +/** + * @file EXPSCOM_COMP_ID_Parse.C + * @brief Build the Explorer User Details parser factory + */ +#include "errludparser.H" +#include "expscomUdParserFactory.H" -#include<prdfBitString.H> +ERRL_MAKE_UD_PARSER(EXPSCOM::UserDetailsParserFactory, hbfw::EXPSCOM_COMP_ID) diff --git a/src/usr/expaccess/plugins/errludP_expscom.H b/src/usr/expaccess/plugins/errludP_expscom.H new file mode 100644 index 000000000..73d449ba4 --- /dev/null +++ b/src/usr/expaccess/plugins/errludP_expscom.H @@ -0,0 +1,168 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/expaccess/plugins/errludP_expscom.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef ERRL_UDP_EXPSCOM_H +#define ERRL_UDP_EXPSCOM_H + +/** + * @file errludP_expscom.H + * Defines the ErrlUserDetailsParser classes that parse EXPSCOM FFDC + */ + +#include "errluserdetails.H" +#include <string.h> + +#define TO_UINT16(ptr) (ntohs(*(reinterpret_cast<uint16_t*>(ptr)))) +#define TO_UINT32(ptr) (ntohl(*(reinterpret_cast<uint32_t*>(ptr)))) + +namespace EXPSCOM +{ + +/** + * @brief Header data of every explorer error log section + */ +typedef struct __attribute__((packed)) +{ + uint16_t packet_num; // ordering byte (0 = first packet) + uint32_t offset_exp_log; // offset where data portion started in full explorer log + uint16_t error_data_size; // size of data portion following header +} explog_section_header_t; + +/** + * @class UdParserExpActiveErrorLog + * + * Parses user-data sections for Explorer's Active logs + */ +class UdParserExpActiveLog : public ERRORLOG::ErrlUserDetailsParser +{ +public: + /** + * @brief Constructor + */ + UdParserExpActiveLog() {} + + /** + * @brief Destructor + */ + virtual ~UdParserExpActiveLog() {} + + /** + * @brief Parses string user detail data from an error log + * + * @param i_version Version of the data + * @param i_parse ErrlUsrParser object for outputting information + * @param i_pBuffer Pointer to buffer containing detail data + * @param i_buflen Length of the buffer + */ + virtual void parse(errlver_t i_version, + ErrlUsrParser & i_parser, + void * i_pBuffer, + const uint32_t i_buflen) const + { + explog_section_header_t * pHeader = reinterpret_cast<explog_section_header_t *>(i_pBuffer); + i_parser.PrintHeading("Explorer Active (RAM) Log Data"); + i_parser.PrintNumber("Order packet", "%d", TO_UINT16(&(pHeader->packet_num))); + i_parser.PrintNumber("Data starting offset", "0x%.8lX", TO_UINT32(&(pHeader->offset_exp_log))); + i_parser.PrintNumber("Size of data section", "0x%.4lX", TO_UINT16(&(pHeader->error_data_size))); + i_parser.PrintBlank(); + uint16_t errorDataSize = TO_UINT16(&(pHeader->error_data_size)); + if (errorDataSize <= (i_buflen - sizeof(explog_section_header_t))) + { + char * l_trace_error_data = static_cast<char*>(i_pBuffer) + sizeof(explog_section_header_t); + i_parser.PrintHexDump(l_trace_error_data, errorDataSize); + } + else + { + i_parser.PrintHeading("ERROR DATA MISSING -- printing entire section in hex"); + i_parser.PrintNumber("Expected data size", "0x%.4lX", i_buflen - sizeof(explog_section_header_t)); + i_parser.PrintHexDump(i_pBuffer, i_buflen); + } + + } + + // Disabled + UdParserExpActiveLog(const UdParserExpActiveLog&) = delete; + UdParserExpActiveLog & operator=(const UdParserExpActiveLog&) = delete; +}; + +/** + * @class UdParserExpSavedErrorLog + * + * Parses user-data sections for Explorer's Saved logs + */ +class UdParserExpSavedLog : public ERRORLOG::ErrlUserDetailsParser +{ +public: + /** + * @brief Constructor + */ + UdParserExpSavedLog() {} + + /** + * @brief Destructor + */ + virtual ~UdParserExpSavedLog() {} + + /** + * @brief Parses string user detail data from an error log + * + * @param i_version Version of the data + * @param i_parse ErrlUsrParser object for outputting information + * @param i_pBuffer Pointer to buffer containing detail data + * @param i_buflen Length of the buffer + */ + virtual void parse(errlver_t i_version, + ErrlUsrParser & i_parser, + void * i_pBuffer, + const uint32_t i_buflen) const + { + explog_section_header_t * pHeader = reinterpret_cast<explog_section_header_t *>(i_pBuffer); + i_parser.PrintHeading("Explorer Saved (SPI flash) Log Data"); + i_parser.PrintNumber("Order packet", "%d", TO_UINT16(&(pHeader->packet_num))); + i_parser.PrintNumber("Data starting offset", "0x%.8lX", TO_UINT32(&(pHeader->offset_exp_log))); + i_parser.PrintNumber("Size of data section", "0x%.4lX", TO_UINT16(&(pHeader->error_data_size))); + i_parser.PrintBlank(); + uint16_t errorDataSize = TO_UINT16(&pHeader->error_data_size); + if (errorDataSize <= (i_buflen - sizeof(explog_section_header_t))) + { + char * l_trace_error_data = static_cast<char*>(i_pBuffer) + sizeof(explog_section_header_t); + i_parser.PrintHexDump(l_trace_error_data, errorDataSize); + } + else + { + i_parser.PrintHeading("ERROR DATA MISSING -- printing entire section in hex"); + i_parser.PrintNumber("Expected data size", "0x%.4lX", i_buflen - sizeof(explog_section_header_t)); + i_parser.PrintHexDump(i_pBuffer, i_buflen); + } + + } + + // Disabled + UdParserExpSavedLog(const UdParserExpSavedLog&) = delete; + UdParserExpSavedLog & operator=(const UdParserExpSavedLog&) = delete; +}; + +} // end EXPSCOM namespace + +#endif diff --git a/src/usr/expaccess/plugins/expscomUdParserFactory.H b/src/usr/expaccess/plugins/expscomUdParserFactory.H new file mode 100644 index 000000000..6a006e308 --- /dev/null +++ b/src/usr/expaccess/plugins/expscomUdParserFactory.H @@ -0,0 +1,58 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/expaccess/plugins/expscomUdParserFactory.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/** + * @file expscomUdParserFactory.H + * @brief Registers Explorer User Detail parsers + */ +#if !defined(_EXPSCOMUDPARSERFACTORY_H) +#define _EXPSCOMUDPARSERFACTORY_H + +#include "errludparserfactory.H" +#include "errludP_expscom.H" + +namespace EXPSCOM +{ + class UserDetailsParserFactory + : public ERRORLOG::ErrlUserDetailsParserFactory + { + public: + UserDetailsParserFactory() + { + registerParser<UdParserExpActiveLog> + (EXPSCOM_UDT_ACTIVE_LOG); + + registerParser<UdParserExpSavedLog> + (EXPSCOM_UDT_SAVED_LOG); + } + + private: + + UserDetailsParserFactory(const UserDetailsParserFactory &); + UserDetailsParserFactory & operator= + (const UserDetailsParserFactory &); + }; +}; + +#endif diff --git a/src/usr/expaccess/runtime/makefile b/src/usr/expaccess/runtime/makefile index ed744eab2..722d966e6 100644 --- a/src/usr/expaccess/runtime/makefile +++ b/src/usr/expaccess/runtime/makefile @@ -22,6 +22,7 @@ # permissions and limitations under the License. # # IBM_PROLOG_END_TAG +HOSTBOOT_RUNTIME = 1 ROOTPATH = ../../../.. MODULE = expaccess_rt @@ -30,7 +31,9 @@ SUBDIRS += test.d include ../expaccess.mk +EXTRAINCDIR += ../ + VPATH += ${ROOTPATH}/src/import/chips/ocmb/explorer/procedures/hwp/memory/ VPATH += ${ROOTPATH}/src/usr/expaccess/ -include ${ROOTPATH}/config.mk
\ No newline at end of file +include ${ROOTPATH}/config.mk diff --git a/src/usr/expaccess/runtime/test/makefile b/src/usr/expaccess/runtime/test/makefile index 442fc0953..3359dc760 100644 --- a/src/usr/expaccess/runtime/test/makefile +++ b/src/usr/expaccess/runtime/test/makefile @@ -30,9 +30,6 @@ MODULE = testexpaccess_rt include ../../test/test.mk -#TODO RTC:196806 re-enable mmio communication tests when mmio works TESTS = ../../test/expscomtest.H include ${ROOTPATH}/config.mk - - diff --git a/src/usr/expaccess/test/expErrlTest.C b/src/usr/expaccess/test/expErrlTest.C new file mode 100644 index 000000000..10f3b1189 --- /dev/null +++ b/src/usr/expaccess/test/expErrlTest.C @@ -0,0 +1,158 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/expaccess/test/expErrlTest.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/** + * @file expErrlTest.C + * @brief Tests the various ways to grab/add explorer error log data + */ +#include <rcExpLog.H> // RC error log side +#include <fapi2.H> +#include <fapi2/plat_hwp_invoker.H> // FAPI_INVOKE_HWP +#include <errl/errlmanager.H> +#include "../errlud_expscom.H" // HB error log side + + +fapi2::ReturnCode get_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_address, + fapi2::buffer<uint64_t>& o_data) +{ + return fapi2::getScom(i_target,i_address,o_data); +} + +uint32_t expErrorLogHb() +{ + uint32_t numTests = 0; + uint32_t numFails = 0; + errlHndl_t l_err = nullptr; + + // Create a vector of TARGETING::Target pointers + TARGETING::TargetHandleList l_chipList; + + // Get a list of all of the functioning ocmb chips + TARGETING::getAllChips(l_chipList, TARGETING::TYPE_OCMB_CHIP, true); + + //Verify at least one ocmb found, some systems do not have ocmb chips + if(l_chipList.size() == 0 ) + { + FAPI_INF("expErrorLogHb: No OCMB targets found, skipping test"); + } + + // create an error for each OCMB and grab the trace data + for ( auto & l_ocmb : l_chipList ) + { + // Get a scom error with bad address + FAPI_INF("expErrorLogHb - Get a scom error with bad address for ocmb 0x%.8X", + TARGETING::get_huid(l_ocmb)); + numTests++; + fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> fapi2_ocmbTarget(l_ocmb); + fapi2::buffer<uint64_t> l_scom_buffer; + FAPI_INVOKE_HWP( l_err, get_scom, fapi2_ocmbTarget, + 0xFFFFFFFF, l_scom_buffer ); + if (l_err) + { + FAPI_INF("expErrorLogHb - created error log 0x%04X, now adding explorer errors", l_err->plid()); + + // Add explorer error logs to this and commit + bool logAdded = false; + numTests++; + logAdded = EXPSCOM::expAddLog(EXPSCOM::ACTIVE_LOG, l_ocmb, l_err); + if (!logAdded) + { + TS_FAIL("expErrorLogHb: No ACTIVE explorer logs added to 0x%04X", l_err->plid()); + numFails++; + } + + numTests++; + logAdded = EXPSCOM::expAddLog(EXPSCOM::SAVED_LOG, l_ocmb, l_err); + if (!logAdded) + { + TS_FAIL("expErrorLogHb: No SAVED explorer logs added to 0x%04X", l_err->plid()); + numFails++; + } + errlCommit(l_err, CXXTEST_COMP_ID); + } + else + { + TS_FAIL("expErrorLogHb: getScom(0xFFFFFFFF) worked on 0x%.8X", + TARGETING::get_huid(l_ocmb)); + numFails++; + } + } + + FAPI_INF("expErrorLogHb Test Complete. %d/%d fails", numFails, numTests); + + return numFails; +} + +uint32_t expErrorLogRc() +{ + uint32_t numTests = 0; + uint32_t numFails = 0; + errlHndl_t l_errl = nullptr; + FAPI_INF("expErrorLogRc() running"); + do + { + // Create a vector of TARGETING::Target pointers + TARGETING::TargetHandleList l_chipList; + + // Get a list of all of the functioning ocmb chips + TARGETING::getAllChips(l_chipList, TARGETING::TYPE_OCMB_CHIP, true); + TARGETING::Target * l_ocmb = nullptr; + + //Take the first ocmb and use it + if (l_chipList.size() > 0) + { + l_ocmb = l_chipList[0]; + } + else + { + FAPI_INF("expErrorLogRc: No OCMB targets found, skipping test"); + break; + } + + numTests++; + fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> fapi2_ocmbTarget(l_ocmb); + // This procedure creates an RC error and then adds Explorer log data + // to that error + // (0x500 bytes of ACTIVE log data, 0x450 bytes of SAVED log data) + FAPI_INVOKE_HWP(l_errl, exp_error_rc, fapi2_ocmbTarget, 0x500, 0x450); + if(l_errl != nullptr) + { + // Commit this error log so it can be examined for Explorer log data + FAPI_INF("exp_errorFfdc_fail returned expected errl"); + errlCommit(l_errl,CXXTEST_COMP_ID); + l_errl = nullptr; + } + else + { + TS_FAIL("expErrorLogRc: No error from exp_errorFfdc_fail !!"); + numFails++; + } + } while (0); + + FAPI_INF("expErrorLogRc Test Complete. %d/%d fails", + numFails , numTests); + + return numFails; +} diff --git a/src/usr/expaccess/test/expErrlTest.H b/src/usr/expaccess/test/expErrlTest.H new file mode 100644 index 000000000..77b44452d --- /dev/null +++ b/src/usr/expaccess/test/expErrlTest.H @@ -0,0 +1,129 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/expaccess/test/expErrlTest.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef __expErrlTest_H +#define __expErrlTest_H + +/** + * @file ExpErrorLogTest.H + * + * @brief Test case for explorer error log grabbing/adding +*/ + +#include <cxxtest/TestSuite.H> +#include <fapi2.H> +#include "expErrlTest.C" +#include <exptest_utils.H> + +using namespace fapi2; + +class test_expErrorLog: public CxxTest::TestSuite +{ +public: + + /** + * @brief Test adding Explorer error logs via RC + */ + void testExpErrorLogRc(void) + { + // @todo RTC 214629 - disabled until simics implements exp_error_log + return; + + if (!iv_serializeTestMutex) + { + TS_FAIL("iv_serializedTestMutex is not setup, unable to continue"); + } + else + { + // Inband operations can't be run at the same time + // atomic section >> + mutex_lock(iv_serializeTestMutex); + uint32_t l_res = expErrorLogRc(); + if (l_res != 0) + { + TS_FAIL("rcTestExpErrorLogRc. Fail l_res=%d", l_res); + } + // atomic section << + mutex_unlock(iv_serializeTestMutex); + } + } + + /** + * @brief Test hostboot side of adding Explorer error log to errl + */ + void testExpErrorLogHb(void) + { + // @todo RTC 214629 - disabled until simics implements exp_error_log + return; + + if (!iv_serializeTestMutex) + { + TS_FAIL("iv_serializedTestMutex is not setup, unable to continue"); + } + else + { + // Inband operations can't be run at the same time + // atomic section >> + mutex_lock(iv_serializeTestMutex); + uint32_t l_res = expErrorLogHb(); + + if (l_res != 0) + { + TS_FAIL("testExpErrorLogHb. Fail l_res=%d", l_res); + } + // atomic section << + mutex_unlock(iv_serializeTestMutex); + } + } + + /** + * @brief Constructor + */ + test_expErrorLog() : CxxTest::TestSuite() + { + // All modules are loaded by runtime, + // so testcase loading of modules is not required +#ifndef __HOSTBOOT_RUNTIME + errlHndl_t err = nullptr; + + // For testing, just load the library needed and don't bother with + // unloading to avoid pulling the rug from under other tests that need + // the loaded library + err = exptest::loadModule(exptest::MSS_LIBRARY_NAME); + if(err) + { + TS_FAIL("OCMBCommTest() - Constuctor: failed to load MSS module"); + errlCommit( err, TARG_COMP_ID ); + } +#endif + iv_serializeTestMutex = exptest::getTestMutex(); + }; + + private: + // This is used for tests that need to not run operations at the same time + TARGETING::HB_MUTEX_SERIALIZE_TEST_LOCK_ATTR iv_serializeTestMutex; + +}; + +#endif diff --git a/src/usr/expaccess/test/expscomtest.H b/src/usr/expaccess/test/expscomtest.H index c943ca7ba..5f5583287 100644 --- a/src/usr/expaccess/test/expscomtest.H +++ b/src/usr/expaccess/test/expscomtest.H @@ -41,8 +41,9 @@ #include <fapi2_hwp_executor.H> #include <fapi2/hw_access.H> #include <lib/shared/exp_consts.H> +#include "exptest_utils.H" +#include "../expscom_trace.H" -extern trace_desc_t* g_trac_expscom; using namespace TARGETING; using namespace ERRORLOG; @@ -57,10 +58,11 @@ struct testExpscomAddrData // Test table values const testExpscomAddrData g_expscomAddrTable[] = { - {0x501C, 0x00000000DEADBEEF}, - {0x209004, 0x00000000C0DEDEAD}, - {0x8010002, 0xDEADC0DEC0DEBEEF} + {0x501C, 0x00000000DEADBEEF}, // UART scratch register + {0x209004, 0x00000000C0DEDEAD}, // PVT_CTRL - TM_SCRATCH register + {0x8010002, 0xDEADC0DEC0DEBEEF} // PSCOM_ERROR_MASK register }; + const uint32_t g_expscomAddrTableSz = sizeof(g_expscomAddrTable)/sizeof(testExpscomAddrData); @@ -80,7 +82,7 @@ TS_FAIL(STRING , \ l_testEntry.addr, \ get_huid(TARGET)); \ l_err = fapi2::rcToErrl(l_rc); \ -errlCommit(l_err, 0x10); +errlCommit(l_err, CXXTEST_COMP_ID); #define FAIL_TEST_ERRL(TARGET, STRING) \ l_fails++; \ @@ -88,7 +90,7 @@ TS_FAIL(STRING , \ l_testEntry.data, \ l_testEntry.addr, \ get_huid(TARGET)); \ -errlCommit(l_err, 0x10); +errlCommit(l_err, CXXTEST_COMP_ID); class expscomTest: public CxxTest::TestSuite { @@ -107,14 +109,33 @@ private: return fapi2::getScom(i_target,i_address,o_data); } + fapi2::ReturnCode put_scom(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + const uint64_t i_address, + const fapi2::buffer<uint64_t> i_data) + { + return fapi2::putScom(i_target,i_address,i_data); + } + + fapi2::ReturnCode get_scom(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + const uint64_t i_address, + fapi2::buffer<uint64_t>& o_data) + { + return fapi2::getScom(i_target,i_address,o_data); + } + + // This is used for tests that need to not run operations at the same time + HB_MUTEX_SERIALIZE_TEST_LOCK_ATTR iv_serializeTestMutex; + public: /** - * @brief EXPSCOM test I2C Path + * @brief EXPSCOM test I2C Path of FAPI HWP interfaces * Write value and read back to verify i2c scoms to OCMBs */ void testExpscomI2c(void) { +// Only MMIO supported at runtime +#ifndef __HOSTBOOT_RUNTIME TRACFCOMP( g_trac_expscom, ">> Enter testExpscomI2c"); // Keep trace of pass/fails uint32_t l_tests = 0; @@ -125,15 +146,16 @@ public: // will be used to hold error from fapi calls fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS; fapi2::buffer<uint64_t> l_scom_buffer; - TargetHandleList l_explorerList; do{ -// Causing a data storage exception in c_str... -#ifdef CONFIG_AXONE_BRING_UP -TRACFCOMP( g_trac_expscom,"skipping testExpscomI2c"); -break; -#endif + if (!iv_serializeTestMutex) + { + TS_FAIL("iv_serializedTestMutex is not setup"); + break; + } + // Get the system's OCMB chips, we will use these as test targets + TargetHandleList l_explorerList; getAllChips( l_explorerList, TYPE_OCMB_CHIP, true ); // true: return functional OCMBs @@ -144,23 +166,44 @@ break; break; } + // Get the system's MEM_PORT units, we will use these as test targets + TargetHandleList l_memportList; + getAllChiplets( l_memportList, + TYPE_MEM_PORT, + true ); // true: return functional OCMBs + + if(l_explorerList.size() != l_memportList.size() ) + { + TS_FAIL( "Wrong number of MEM_PORTs (%d) compared to OCMB_CHIPs (%d)", l_memportList.size(), l_explorerList.size() ); + break; + } // We will use the first and last targets for these scom tests auto l_firstExpChip = l_explorerList.front(); auto l_lastExpChip = l_explorerList.back(); + auto l_firstMemPort = l_memportList.front(); + auto l_lastMemPort = l_memportList.back(); // Cast the TARGETING::Targets into fapi2::Targets fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> l_firstExpChip_fapi(l_firstExpChip); fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> l_lastExpChip_fapi(l_lastExpChip); + fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT> l_firstMemPort_fapi(l_firstMemPort); + fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT> l_lastMemPort_fapi(l_lastMemPort); // Save away original scom switch info so we can restore it at the end of the test - auto first_ocmb_info = l_firstExpChip->getAttr<TARGETING::ATTR_SCOM_SWITCHES>(); - auto last_ocmb_info = l_lastExpChip->getAttr<TARGETING::ATTR_SCOM_SWITCHES>(); + auto first_ocmb_info = + l_firstExpChip->getAttr<ATTR_SCOM_SWITCHES>(); + auto last_ocmb_info = + l_lastExpChip->getAttr<ATTR_SCOM_SWITCHES>(); - // This goal of this tests is to make sure I2C scom to OCMB is working so force - // scom to go over I2C path for these targets - l_firstExpChip->setAttr<TARGETING::ATTR_SCOM_SWITCHES>(forceI2CScom); - l_lastExpChip->setAttr<TARGETING::ATTR_SCOM_SWITCHES>(forceI2CScom); + // Inband operations can't be run at the same time + // atomic section >> + mutex_lock(iv_serializeTestMutex); + + // The goal of these tests is to make sure I2C scom to OCMB is + // working so force scom to go over I2C path for these targets + l_firstExpChip->setAttr<ATTR_SCOM_SWITCHES>(forceI2CScom); + l_lastExpChip->setAttr<ATTR_SCOM_SWITCHES>(forceI2CScom); // Loop through table for first and last OCMB targets for( uint32_t l_num=0; l_num < g_expscomAddrTableSz; l_num++) @@ -216,7 +259,7 @@ break; if(l_err) { FAIL_TEST_ERRL(l_firstExpChip, - "testExpscomI2c>> Failed getScom reading 0x%.16X to 0x%.8X on target w/ huid 0x%.8X") + "testExpscomI2c>> Failed getScom reading 0x%.16X to 0x%.8X on target w/ huid 0x%.8X"); } l_tests++; @@ -241,7 +284,7 @@ break; if(l_err) { FAIL_TEST_ERRL(l_lastExpChip, - "testExpscomI2c>> Failed getScom reading 0x%.16X to 0x%.8X on target w/ huid 0x%.8X") + "testExpscomI2c>> Failed getScom reading 0x%.16X to 0x%.8X on target w/ huid 0x%.8X"); } l_tests++; @@ -253,20 +296,118 @@ break; l_scom_buffer(), get_huid(l_lastExpChip)); } + + /// Repeat everything on the MEM_PORT targets + + // Read the test entry info from the global table at the top of this file + l_testEntry = g_expscomAddrTable[l_num]; + + if(l_testEntry.addr & mss::exp::i2c::IBM_SCOM_INDICATOR) + { + // If this is an IBM address then we expect 64 bits of data + l_scom_buffer.insert<0,64,0,uint64_t>(l_testEntry.data); + } + else + { + // Otherwise we know this is a native OCMB address and it is only 32 bits + l_scom_buffer.insert<32,32,0,uint32_t>(l_testEntry.data); + } + + FAPI_INVOKE_HWP(l_err, put_scom, + l_firstMemPort_fapi, + l_testEntry.addr, + l_scom_buffer ); + l_tests++; + if(l_err) + { + FAIL_TEST_ERRL(l_firstMemPort, + "testExpscomI2c>> Failed putScom writing 0x%.16X to 0x%.8X on target w/ huid 0x%.8X"); + + } + + // putScom to last MEM_PORT over i2c + FAPI_INVOKE_HWP(l_err, put_scom, + l_lastMemPort_fapi, + l_testEntry.addr, + l_scom_buffer ); + l_tests++; + if(l_err) + { + FAIL_TEST_ERRL(l_lastMemPort, + "testExpscomI2c>> Failed putScom writing 0x%.16X to 0x%.8X on target w/ huid 0x%.8X"); + } + + + // Flush scom buffers so it doesnt mess up next test + l_scom_buffer.flush<0>(); + + // getScom to first MEM_PORT over i2c + FAPI_INVOKE_HWP(l_err, get_scom, + l_firstMemPort_fapi, + l_testEntry.addr, + l_scom_buffer ); + l_tests++; + if(l_err) + { + FAIL_TEST_ERRL(l_firstMemPort, + "testExpscomI2c>> Failed getScom reading 0x%.16X to 0x%.8X on target w/ huid 0x%.8X"); + } + + l_tests++; + if(l_scom_buffer() != l_testEntry.data) + { + l_fails++; + TS_FAIL("testExpscomI2c>> Expected 0x%.16X but got 0x%.16X on target w/ huid 0x%.8X", + l_testEntry.data, + l_scom_buffer(), + get_huid(l_firstMemPort)); + } + + // Flush scom buffers so it doesnt mess up next test + l_scom_buffer.flush<0>(); + + // getScom to last MEM_PORT over i2c + FAPI_INVOKE_HWP(l_err, get_scom, + l_lastMemPort_fapi, + l_testEntry.addr, + l_scom_buffer ); + l_tests++; + if(l_err) + { + FAIL_TEST_ERRL(l_lastMemPort, + "testExpscomI2c>> Failed getScom reading 0x%.16X to 0x%.8X on target w/ huid 0x%.8X"); + } + + l_tests++; + if(l_scom_buffer() != l_testEntry.data) + { + l_fails++; + TS_FAIL("testExpscomI2c>> Expected 0x%.16X but got 0x%.16X on target w/ huid 0x%.8X", + l_testEntry.data, + l_scom_buffer(), + get_huid(l_lastMemPort)); + } } // Set ATTR_SCOM_SWITCHES back to their original values - l_firstExpChip->setAttr<TARGETING::ATTR_SCOM_SWITCHES>(first_ocmb_info); - l_lastExpChip->setAttr<TARGETING::ATTR_SCOM_SWITCHES>(last_ocmb_info); - }while(0); + l_firstExpChip->setAttr<ATTR_SCOM_SWITCHES>(first_ocmb_info); + l_lastExpChip->setAttr<ATTR_SCOM_SWITCHES>(last_ocmb_info); + // << atomic section + mutex_unlock(iv_serializeTestMutex); + }while(0); TRACFCOMP( g_trac_expscom, "<< Exit testExpscomI2c"); +#endif return; } + /** + * @brief Test platform level interfaces over I2C + */ void testExpscomI2cPlatform(void) { - +// Only mmio supported at runtime +#ifndef __HOSTBOOT_RUNTIME TRACFCOMP( g_trac_expscom, ">> Enter testExpscomI2cPlatform"); // Keep trace of pass/fails uint32_t l_tests = 0; @@ -283,12 +424,11 @@ break; TargetHandleList l_explorerList; do{ -// Causing a data storage exception in c_str... -#ifdef CONFIG_AXONE_BRING_UP -TRACFCOMP( g_trac_expscom,"skipping testExpscomI2cPlatformPlatform"); -break; -#endif - + if (!iv_serializeTestMutex) + { + TS_FAIL("iv_serializedTestMutex is not setup"); + break; + } getAllChips( l_explorerList, TYPE_OCMB_CHIP, true ); // true: return functional OCMBs @@ -296,7 +436,7 @@ break; if(l_explorerList.size() == 0 ) { - TRACFCOMP( g_trac_expscom, "No OCMB targets found, skipping testExpscomI2cPlatformPlatform"); + TRACFCOMP( g_trac_expscom, "No OCMB targets found, skipping testExpscomI2cPlatform"); break; } @@ -305,412 +445,517 @@ break; auto l_lastExpChip = l_explorerList.back(); // Save away original scom switch info so we can restore it at the end of the test - auto first_ocmb_info = l_firstExpChip->getAttr<TARGETING::ATTR_SCOM_SWITCHES>(); - auto last_ocmb_info = l_lastExpChip->getAttr<TARGETING::ATTR_SCOM_SWITCHES>(); + auto first_ocmb_info = + l_firstExpChip->getAttr<ATTR_SCOM_SWITCHES>(); + auto last_ocmb_info = + l_lastExpChip->getAttr<ATTR_SCOM_SWITCHES>(); + + // Inband operations can't be run at the same time + // atomic section >> + mutex_lock(iv_serializeTestMutex); // This goal of this tests is to make sure I2C scom to OCMB is working so force // scom to go over I2C path for these targets - l_firstExpChip->setAttr<TARGETING::ATTR_SCOM_SWITCHES>(forceI2CScom); - l_lastExpChip->setAttr<TARGETING::ATTR_SCOM_SWITCHES>(forceI2CScom); + l_firstExpChip->setAttr<ATTR_SCOM_SWITCHES>(forceI2CScom); + l_lastExpChip->setAttr<ATTR_SCOM_SWITCHES>(forceI2CScom); // Loop through table for first and last OCMB targets for( uint32_t l_num=0; l_num < g_expscomAddrTableSz; l_num++) { - // Read the test entry info from the global table at the top of this file - testExpscomAddrData l_testEntry = g_expscomAddrTable[l_num]; - - if(l_testEntry.addr & mss::exp::i2c::IBM_SCOM_INDICATOR) - { - // If this is an IBM address then we expect 64 bits of data - l_scom_buffer.insert<0,64,0,uint64_t>(l_testEntry.data); - } - else - { - // Otherwise we know this is a native OCMB address and it is only 32 bits - l_scom_buffer.insert<32,32,0,uint32_t>(l_testEntry.data); - } - l_err = deviceWrite(l_firstExpChip, - &l_scom_buffer, - l_scomSize, - DEVICE_SCOM_ADDRESS( l_testEntry.addr)); - l_tests++; - if(l_err) - { - FAIL_TEST_ERRL(l_firstExpChip, + // Read the test entry info from the global table at the top of this file + testExpscomAddrData l_testEntry = g_expscomAddrTable[l_num]; + + if(l_testEntry.addr & mss::exp::i2c::IBM_SCOM_INDICATOR) + { + // If this is an IBM address then we expect 64 bits of data + l_scom_buffer.insert<0,64,0,uint64_t>(l_testEntry.data); + } + else + { + // Otherwise we know this is a native OCMB address and it is only 32 bits + l_scom_buffer.insert<32,32,0,uint32_t>(l_testEntry.data); + } + l_err = deviceWrite(l_firstExpChip, + &l_scom_buffer, + l_scomSize, + DEVICE_SCOM_ADDRESS( l_testEntry.addr)); + l_tests++; + if(l_err) + { + FAIL_TEST_ERRL(l_firstExpChip, + "testExpscomI2cPlatform>> Failed putScom writing 0x%.16X to 0x%.8X on target w/ huid 0x%.8X"); + + } + + l_err = deviceWrite(l_lastExpChip, + &l_scom_buffer, + l_scomSize, + DEVICE_SCOM_ADDRESS( l_testEntry.addr)); + l_tests++; + if(l_err) + { + FAIL_TEST_ERRL(l_firstExpChip, "testExpscomI2cPlatform>> Failed putScom writing 0x%.16X to 0x%.8X on target w/ huid 0x%.8X"); - } - - l_err = deviceWrite(l_lastExpChip, - &l_scom_buffer, - l_scomSize, - DEVICE_SCOM_ADDRESS( l_testEntry.addr)); - l_tests++; - if(l_err) - { - FAIL_TEST_ERRL(l_firstExpChip, - "testExpscomI2cPlatform>> Failed putScom writing 0x%.16X to 0x%.8X on target w/ huid 0x%.8X"); - - } - // Flush scom buffers so it doesnt mess up next test - l_scom_buffer.flush<0>(); - - // getScom to first OCMB over i2c - l_err = deviceRead(l_firstExpChip, - &l_scom_buffer(), - l_scomSize, - DEVICE_SCOM_ADDRESS( l_testEntry.addr)); - l_tests++; - if(l_err) - { - FAIL_TEST_ERRL(l_firstExpChip, - "testExpscomI2cPlatform>> Failed getScom reading 0x%.16X to 0x%.8X on target w/ huid 0x%.8X") - } - - l_tests++; - if(l_scom_buffer() != l_testEntry.data) - { - l_fails++; - TS_FAIL("testExpscomI2cPlatform>> Expected 0x%.16X but got 0x%.16X on target w/ huid 0x%.8X", - l_testEntry.data, - l_scom_buffer(), - get_huid(l_firstExpChip)); - } - - - // Flush scom buffers so it doesnt mess up next test - l_scom_buffer.flush<0>(); - - // getScom to last OCMB over i2c - l_err = deviceRead(l_lastExpChip, - &l_scom_buffer(), - l_scomSize, - DEVICE_SCOM_ADDRESS( l_testEntry.addr)); - l_tests++; - if(l_err) - { - FAIL_TEST_ERRL(l_firstExpChip, - "testExpscomI2cPlatform>> Failed getScom reading 0x%.16X to 0x%.8X on target w/ huid 0x%.8X") - } - - l_tests++; - if(l_scom_buffer() != l_testEntry.data) - { - l_fails++; - TS_FAIL("testExpscomI2cPlatform>> Expected 0x%.16X but got 0x%.16X on target w/ huid 0x%.8X", - l_testEntry.data, - l_scom_buffer(), - get_huid(l_firstExpChip)); - } + } + // Flush scom buffers so it doesnt mess up next test + l_scom_buffer.flush<0>(); + + // getScom to first OCMB over i2c + l_err = deviceRead(l_firstExpChip, + &l_scom_buffer(), + l_scomSize, + DEVICE_SCOM_ADDRESS( l_testEntry.addr)); + l_tests++; + if(l_err) + { + FAIL_TEST_ERRL(l_firstExpChip, + "testExpscomI2cPlatform>> Failed getScom reading 0x%.16X to 0x%.8X on target w/ huid 0x%.8X") + } + + l_tests++; + if(l_scom_buffer() != l_testEntry.data) + { + l_fails++; + TS_FAIL("testExpscomI2cPlatform>> Expected 0x%.16X but got 0x%.16X on target w/ huid 0x%.8X", + l_testEntry.data, + l_scom_buffer(), + get_huid(l_firstExpChip)); + } + + + // Flush scom buffers so it doesnt mess up next test + l_scom_buffer.flush<0>(); + + // getScom to last OCMB over i2c + l_err = deviceRead(l_lastExpChip, + &l_scom_buffer(), + l_scomSize, + DEVICE_SCOM_ADDRESS( l_testEntry.addr)); + l_tests++; + if(l_err) + { + FAIL_TEST_ERRL(l_firstExpChip, + "testExpscomI2cPlatform>> Failed getScom reading 0x%.16X to 0x%.8X on target w/ huid 0x%.8X") + } + + l_tests++; + if(l_scom_buffer() != l_testEntry.data) + { + l_fails++; + TS_FAIL("testExpscomI2cPlatform>> Expected 0x%.16X but got 0x%.16X on target w/ huid 0x%.8X", + l_testEntry.data, + l_scom_buffer(), + get_huid(l_firstExpChip)); + } } // Set ATTR_SCOM_SWITCHES back to their original values - l_firstExpChip->setAttr<TARGETING::ATTR_SCOM_SWITCHES>(first_ocmb_info); - l_lastExpChip->setAttr<TARGETING::ATTR_SCOM_SWITCHES>(last_ocmb_info); + l_firstExpChip->setAttr<ATTR_SCOM_SWITCHES>(first_ocmb_info); + l_lastExpChip->setAttr<ATTR_SCOM_SWITCHES>(last_ocmb_info); + + // << atomic section + mutex_unlock(iv_serializeTestMutex); + }while(0); TRACFCOMP( g_trac_expscom, "<< Exit testExpscomI2cPlatform"); +#endif return; } -// TODO RTC: 189447 Enable MMIO tests when MMIO drivers avail - /** + /** * @brief EXPSCOM test MMIO * Write value and read back to verify MMIO scoms to OCMBs + * using fapi HWPs. */ -// void testExpscomMmio(void) -// { -// TargetHandleList l_explorerList; -// uint32_t l_tests = 0; -// uint32_t l_fails = 0; -// errlHndl_t l_err = nullptr; -// fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS; -// fapi2::buffer<uint64_t> l_scom_buffer; -// -// // Get the system's procs -// getAllChips( l_explorerList, -// TYPE_OCMB_CHIP, -// true ); // true: return functional OCMBs -// -// auto l_firstExpChip = l_explorerList.front(); -// auto l_lastExpChip = l_explorerList.back(); -// -// fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> l_firstExpChip_fapi(l_firstExpChip); -// fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> l_lastExpChip_fapi(l_lastExpChip); -// -// auto first_ocmb_info = l_firstExpChip->getAttr<TARGETING::ATTR_SCOM_SWITCHES>(); -// auto last_ocmb_info = l_lastExpChip->getAttr<TARGETING::ATTR_SCOM_SWITCHES>(); -// -// -// // Loop through table for first and last OCMB, perform i2c write, then -// // mmio read, and mmio write followed by i2c read. -// for( uint32_t l_num=0; l_num < g_expscomAddrTableSz; l_num++) -// { -// testExpscomAddrData l_testEntry = g_expscomAddrTable[l_num]; -// if(l_testEntry.addr & mss::exp::i2c::IBM_SCOM_INDICATOR) -// { -// l_scom_buffer.insert<0,64,0,uint64_t>(l_testEntry.data); -// } -// else -// { -// l_scom_buffer.insert<0,32,0,uint32_t>(l_testEntry.data); -// } -// -// // putScom to first OCMB over mmio -// l_rc = put_scom(l_firstExpChip_fapi, -// l_testEntry.addr, -// l_scom_buffer); -// l_tests++; -// if(l_rc) -// { -// l_fails++; -// TS_FAIL("testExpscomMmio>> Failed putScom writing 0x%.16X to 0x%.8X on target w/ huid 0x%.8X", -// l_testEntry.data, -// l_testEntry.addr, -// get_huid(l_firstExpChip)); -// l_err = fapi2::rcToErrl(l_rc); -// errlCommit(l_err, 0x10); -// } -// -// // putScom to last OCMB over mmio -// l_rc = put_scom(l_lastExpChip_fapi, -// l_testEntry.addr, -// l_scom_buffer); -// l_tests++; -// if(l_rc) -// { -// l_fails++; -// TS_FAIL("testExpscomMmio>> Failed putScom writing 0x%.16X to 0x%.8X on target w/ huid 0x%.8X", -// l_testEntry.data, -// l_testEntry.addr, -// get_huid(l_lastExpChip)); -// l_err = fapi2::rcToErrl(l_rc); -// errlCommit(l_err, 0x10); -// } -// -// // Flush scom buffer so it doesnt mess up next test -// l_scom_buffer.flush<0>(); -// -// -// // getScom to first OCMB over mmio -// l_rc = get_scom(l_firstExpChip_fapi, -// l_testEntry.addr, -// l_scom_buffer); -// l_tests++; -// if(l_rc) -// { -// l_fails++; -// TS_FAIL("testExpscomMmio>> Failed getScom reading 0x%.16X to 0x%.8X on target w/ huid 0x%.8X", -// l_testEntry.data, -// l_testEntry.addr, -// get_huid(l_firstExpChip)); -// l_err = fapi2::rcToErrl(l_rc); -// errlCommit(l_err, 0x10); -// } -// -// l_tests++; -// if(l_scom_buffer() != l_testEntry.data) -// { -// l_fails++; -// TS_FAIL("testExpscomMmio>> Expected 0x%.16X but got 0x%.16X on target w/ huid 0x%.8X", -// l_testEntry.data, -// l_scom_buffer(), -// get_huid(l_firstExpChip)); -// l_err = fapi2::rcToErrl(l_rc); -// errlCommit(l_err, 0x10); -// } -// -// // Flush scom buffer so it doesnt mess up next test -// l_scom_buffer.flush<0>(); -// -// // getScom to last OCMB over mmio -// l_rc = get_scom(l_lastExpChip_fapi, -// l_testEntry.addr, -// l_scom_buffer); -// l_tests++; -// if(l_rc) -// { -// l_fails++; -// TS_FAIL("testExpscomMmio>> Failed getScom reading 0x%.16X to 0x%.8X on target w/ huid 0x%.8X", -// l_testEntry.data, -// l_testEntry.addr, -// get_huid(l_lastExpChip)); -// l_err = fapi2::rcToErrl(l_rc); -// errlCommit(l_err, 0x10); -// } -// -// l_tests++; -// if(l_scom_buffer() != l_testEntry.data) -// { -// l_fails++; -// TS_FAIL("testExpscomMmio>> Expected 0x%.16X but got 0x%.16X on target w/ huid 0x%.8X", -// l_testEntry.data, -// l_scom_buffer(), -// get_huid(l_lastExpChip)); -// l_err = fapi2::rcToErrl(l_rc); -// errlCommit(l_err, 0x10); -// } -// } -// // Set ATTR_SCOM_SWITCHES back to their original values -// l_firstExpChip->setAttr<TARGETING::ATTR_SCOM_SWITCHES>(first_ocmb_info); -// l_lastExpChip->setAttr<TARGETING::ATTR_SCOM_SWITCHES>(last_ocmb_info); -// return; -// } - - /** - * @brief EXPSCOM test MMIO - * Write value and read back to verify MMIO - */ -// void testExpscomCombined(void) -// { -// TargetHandleList l_explorerList; -// uint32_t l_tests = 0; -// uint32_t l_fails = 0; -// fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS; -// fapi2::buffer<uint64_t> l_scom_buffer; -// -// // Get the system's procs -// getAllChips( l_explorerList, -// TYPE_OCMB_CHIP, -// true ); // true: return functional OCMBs -// -// auto l_firstExpChip = l_explorerList.front(); -// auto l_lastExpChip = l_explorerList.back(); -// -// fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> l_firstExpChip_fapi(l_firstExpChip); -// fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> l_lastExpChip_fapi(l_lastExpChip); -// -// auto first_ocmb_info = l_firstExpChip->getAttr<TARGETING::ATTR_SCOM_SWITCHES>(); -// auto last_ocmb_info = l_lastExpChip->getAttr<TARGETING::ATTR_SCOM_SWITCHES>(); -// -// // Loop through table for first and last OCMB -// for( uint32_t l_num=0; l_num < g_expscomAddrTableSz; l_num++) -// { -// testExpscomAddrData l_testEntry = g_expscomAddrTable[l_num]; -// -// if(l_testEntry.addr & mss::exp::i2c::IBM_SCOM_INDICATOR) -// { -// l_scom_buffer.insert<0,64,0,uint64_t>(l_testEntry.data); -// } -// else -// { -// l_scom_buffer.insert<0,32,0,uint32_t>(l_testEntry.data); -// } -// -// // ODD tests : first target writes MMIO, last target writes I2C -// // EVEN tests : first target writes I2C, last target writes MMIO -// if(l_num % 2) -// { -// l_firstExpChip->setAttr<TARGETING::ATTR_SCOM_SWITCHES>(forceMMIOScom); -// l_lastExpChip->setAttr<TARGETING::ATTR_SCOM_SWITCHES>(forceI2CScom); -// } -// else -// { -// l_firstExpChip->setAttr<TARGETING::ATTR_SCOM_SWITCHES>(forceI2CScom); -// l_lastExpChip->setAttr<TARGETING::ATTR_SCOM_SWITCHES>(forceMMIOScom); -// } -// -// // putScom to first OCMB over mmio -// l_rc = put_scom(l_firstExpChip_fapi, -// l_testEntry.addr, -// l_scom_buffer); -// l_tests++; -// if(l_rc) -// { -// l_fails++; -// TS_FAIL("testExpscomMmio>> Failed putScom writing 0x%.16X to 0x%.8X on target w/ huid 0x%.8X", -// l_testEntry.data, -// l_testEntry.addr, -// get_huid(l_firstExpChip)); -// } -// -// // putScom to last OCMB over mmio -// l_rc = put_scom(l_lastExpChip_fapi, -// l_testEntry.addr, -// l_scom_buffer); -// l_tests++; -// if(l_rc) -// { -// l_fails++; -// TS_FAIL("testExpscomMmio>> Failed putScom writing 0x%.16X to 0x%.8X on target w/ huid 0x%.8X", -// l_testEntry.data, -// l_testEntry.addr, -// get_huid(l_lastExpChip)); -// } -// -// // Flush scom buffer so it doesnt mess up next test -// l_scom_buffer.flush<0>(); -// -// // getScom to first OCMB over mmio -// l_rc = get_scom(l_firstExpChip_fapi, -// l_testEntry.addr, -// l_scom_buffer); -// l_tests++; -// if(l_rc) -// { -// l_fails++; -// TS_FAIL("testExpscomMmio>> Failed getScom reading 0x%.16X to 0x%.8X on target w/ huid 0x%.8X", -// l_testEntry.data, -// l_testEntry.addr, -// get_huid(l_firstExpChip)); -// } -// -// l_tests++; -// if(l_scom_buffer() != l_testEntry.data) -// { -// l_fails++; -// TS_FAIL("testExpscomMmio>> Expected 0x%.16X but got 0x%.16X on target w/ huid 0x%.8X", -// l_testEntry.data, -// l_scom_buffer(), -// get_huid(l_firstExpChip)); -// } -// -// // ODD tests : first target reads I2C, last target reads MMIO -// // EVEN tests : first target reads MMIO, last target reads I2C -// if(l_num % 2) -// { -// l_firstExpChip->setAttr<TARGETING::ATTR_SCOM_SWITCHES>(forceI2CScom); -// l_lastExpChip->setAttr<TARGETING::ATTR_SCOM_SWITCHES>(forceMMIOScom); -// } -// else -// { -// l_firstExpChip->setAttr<TARGETING::ATTR_SCOM_SWITCHES>(forceMMIOScom); -// l_lastExpChip->setAttr<TARGETING::ATTR_SCOM_SWITCHES>(forceI2CScom); -// } -// -// // Flush scom buffer so it doesnt mess up next test -// l_scom_buffer.flush<0>(); -// -// // getScom to last OCMB over mmio -// l_rc = get_scom(l_lastExpChip_fapi, -// l_testEntry.addr, -// l_scom_buffer); -// l_tests++; -// if(l_rc) -// { -// l_fails++; -// TS_FAIL("testExpscomMmio>> Failed getScom reading 0x%.16X to 0x%.8X on target w/ huid 0x%.8X", -// l_testEntry.data, -// l_testEntry.addr, -// get_huid(l_lastExpChip)); -// } -// -// l_tests++; -// if(l_scom_buffer() != l_testEntry.data) -// { -// l_fails++; -// TS_FAIL("testExpscomMmio>> Expected 0x%.16X but got 0x%.16X on target w/ huid 0x%.8X", -// l_testEntry.data, -// l_scom_buffer(), -// get_huid(l_lastExpChip)); -// } -// } -// // Set ATTR_SCOM_SWITCHES back to their original values -// l_firstExpChip->setAttr<TARGETING::ATTR_SCOM_SWITCHES>(first_ocmb_info); -// l_lastExpChip->setAttr<TARGETING::ATTR_SCOM_SWITCHES>(last_ocmb_info); -// return; -// } + void testExpscomMmio(void) + { + TargetHandleList l_explorerList; + uint32_t l_tests = 0; + uint32_t l_fails = 0; + errlHndl_t l_err = nullptr; + fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS; + fapi2::buffer<uint64_t> l_scom_buffer; + + TRACFCOMP(g_trac_expscom, ">> Enter testExpscomMmio"); + + do{ + if (!iv_serializeTestMutex) + { + TS_FAIL("iv_serializedTestMutex is not setup"); + break; + } + + // Get the system's procs + getAllChips( l_explorerList, + TYPE_OCMB_CHIP, + true ); // true: return functional OCMBs + + if(l_explorerList.size() == 0 ) + { + TRACFCOMP(g_trac_expscom, "No OCMB targets found, skipping testExpscomMmio"); + break; + } + + auto l_firstExpChip = l_explorerList.front(); + auto l_lastExpChip = l_explorerList.back(); + + fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> + l_firstExpChip_fapi(l_firstExpChip); + fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> + l_lastExpChip_fapi(l_lastExpChip); + + auto first_ocmb_info = + l_firstExpChip->getAttr<ATTR_SCOM_SWITCHES>(); + auto last_ocmb_info = + l_lastExpChip->getAttr<ATTR_SCOM_SWITCHES>(); + + // Inband operations can't be run at the same time + // atomic section >> + mutex_lock(iv_serializeTestMutex); + + // Force use of MMIO + l_firstExpChip->setAttr<ATTR_SCOM_SWITCHES>(forceMMIOScom); + l_lastExpChip->setAttr<ATTR_SCOM_SWITCHES>(forceMMIOScom); + + // Loop through table for first and last OCMB, perform i2c write, + // then read it back + for( uint32_t l_num=0; l_num < g_expscomAddrTableSz; l_num++) + { + testExpscomAddrData l_testEntry = g_expscomAddrTable[l_num]; + if(l_testEntry.addr & mss::exp::i2c::IBM_SCOM_INDICATOR) + { + l_scom_buffer.insert<0,64,0,uint64_t>(l_testEntry.data); + } + else + { + l_scom_buffer.insert<32,32,0,uint32_t>(l_testEntry.data); + } + + // putScom to first OCMB over mmio + l_rc = put_scom(l_firstExpChip_fapi, + l_testEntry.addr, + l_scom_buffer); + l_tests++; + if(l_rc) + { + l_fails++; + TS_FAIL("testExpscomMmio>> Failed putScom writing 0x%.16X to 0x%.8X on target w/ huid 0x%.8X", + l_testEntry.data, + l_testEntry.addr, + get_huid(l_firstExpChip)); + l_err = fapi2::rcToErrl(l_rc); + errlCommit(l_err, CXXTEST_COMP_ID); + } + + // putScom to last OCMB over mmio + l_rc = put_scom(l_lastExpChip_fapi, + l_testEntry.addr, + l_scom_buffer); + l_tests++; + if(l_rc) + { + l_fails++; + TS_FAIL("testExpscomMmio>> Failed putScom writing 0x%.16X to 0x%.8X on target w/ huid 0x%.8X", + l_testEntry.data, + l_testEntry.addr, + get_huid(l_lastExpChip)); + l_err = fapi2::rcToErrl(l_rc); + errlCommit(l_err, CXXTEST_COMP_ID); + } + + // Flush scom buffer so it doesnt mess up next test + l_scom_buffer.flush<0>(); + + // getScom to first OCMB over mmio + l_rc = get_scom(l_firstExpChip_fapi, + l_testEntry.addr, + l_scom_buffer); + l_tests++; + if(l_rc) + { + l_fails++; + TS_FAIL("testExpscomMmio>> Failed getScom reading 0x%.16X to 0x%.8X on target w/ huid 0x%.8X", + l_testEntry.data, + l_testEntry.addr, + get_huid(l_firstExpChip)); + l_err = fapi2::rcToErrl(l_rc); + errlCommit(l_err, CXXTEST_COMP_ID); + } + + l_tests++; + if(l_scom_buffer() != l_testEntry.data) + { + l_fails++; + TS_FAIL("testExpscomMmio>> Expected 0x%.16X but got 0x%.16X on target w/ huid 0x%.8X", + l_testEntry.data, + l_scom_buffer(), + get_huid(l_firstExpChip)); + l_err = fapi2::rcToErrl(l_rc); + errlCommit(l_err, CXXTEST_COMP_ID); + } + + // Flush scom buffer so it doesnt mess up next test + l_scom_buffer.flush<0>(); + + // getScom to last OCMB over mmio + l_rc = get_scom(l_lastExpChip_fapi, + l_testEntry.addr, + l_scom_buffer); + l_tests++; + if(l_rc) + { + l_fails++; + TS_FAIL("testExpscomMmio>> Failed getScom reading 0x%.16X to 0x%.8X on target w/ huid 0x%.8X", + l_testEntry.data, + l_testEntry.addr, + get_huid(l_lastExpChip)); + l_err = fapi2::rcToErrl(l_rc); + errlCommit(l_err, CXXTEST_COMP_ID); + } + + l_tests++; + if(l_scom_buffer() != l_testEntry.data) + { + l_fails++; + TS_FAIL("testExpscomMmio>> Expected 0x%.16X but got 0x%.16X on target w/ huid 0x%.8X", + l_testEntry.data, + l_scom_buffer(), + get_huid(l_lastExpChip)); + l_err = fapi2::rcToErrl(l_rc); + errlCommit(l_err, CXXTEST_COMP_ID); + } + } + // Set ATTR_SCOM_SWITCHES back to their original values + l_firstExpChip->setAttr<ATTR_SCOM_SWITCHES>(first_ocmb_info); + l_lastExpChip->setAttr<ATTR_SCOM_SWITCHES>(last_ocmb_info); + + // << atomic section + mutex_unlock(iv_serializeTestMutex); + }while(0); + + + TRACFCOMP(g_trac_expscom, "<< Exit testExpscomMmio"); + return; + } + + /** + * @brief EXPSCOM test MMIO + * Combine I2C and MMIO reads/writes to verify that we + * get consistent results using FAPI HWPs. + */ + void testExpscomCombined(void) + { +// Only MMIO scoms supported at runtime, i2c not supported +#ifndef __HOSTBOOT_RUNTIME + TargetHandleList l_explorerList; + uint32_t l_tests = 0; + uint32_t l_fails = 0; + fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS; + fapi2::buffer<uint64_t> l_scom_buffer; + + TRACFCOMP(g_trac_expscom, ">> Enter testExpscomCombined"); + + do{ + if (!iv_serializeTestMutex) + { + TS_FAIL("iv_serializedTestMutex is not setup"); + break; + } + + // Get the system's procs + getAllChips( l_explorerList, + TYPE_OCMB_CHIP, + true ); // true: return functional OCMBs + + if(l_explorerList.size() == 0 ) + { + TRACFCOMP(g_trac_expscom, "No OCMB targets found, skipping testExpscomCombined"); + break; + } + + auto l_firstExpChip = l_explorerList.front(); + auto l_lastExpChip = l_explorerList.back(); + + fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> + l_firstExpChip_fapi(l_firstExpChip); + fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> + l_lastExpChip_fapi(l_lastExpChip); + + auto first_ocmb_info = + l_firstExpChip->getAttr<ATTR_SCOM_SWITCHES>(); + auto last_ocmb_info = + l_lastExpChip->getAttr<ATTR_SCOM_SWITCHES>(); + // Inband operations can't be run at the same time + // atomic section >> + mutex_lock(iv_serializeTestMutex); + + // Loop through table for first and last OCMB, perform i2c write, + // then mmio read, and mmio write followed by i2c read. + for( uint32_t l_num=0; l_num < g_expscomAddrTableSz; l_num++) + { + testExpscomAddrData l_testEntry = g_expscomAddrTable[l_num]; + + if(l_testEntry.addr & mss::exp::i2c::IBM_SCOM_INDICATOR) + { + l_scom_buffer.insert<0,64,0,uint64_t>(l_testEntry.data); + } + else + { + l_scom_buffer.insert<32,32,0,uint32_t>(l_testEntry.data); + } + + // ODD tests : first target writes MMIO, last target writes I2C + // EVEN tests : first target writes I2C, last target writes MMIO + if(l_num % 2) + { + l_firstExpChip->setAttr<ATTR_SCOM_SWITCHES>(forceMMIOScom); + l_lastExpChip->setAttr<ATTR_SCOM_SWITCHES>(forceI2CScom); + } + else + { + l_firstExpChip->setAttr<ATTR_SCOM_SWITCHES>(forceI2CScom); + l_lastExpChip->setAttr<ATTR_SCOM_SWITCHES>(forceMMIOScom); + } + + // putScom to first OCMB + l_rc = put_scom(l_firstExpChip_fapi, + l_testEntry.addr, + l_scom_buffer); + l_tests++; + if(l_rc) + { + l_fails++; + TS_FAIL("testExpscomCombined>> Failed putScom writing 0x%.16X to 0x%.8X on target w/ huid 0x%.8X", + l_testEntry.data, + l_testEntry.addr, + get_huid(l_firstExpChip)); + } + + // putScom to last OCMB + l_rc = put_scom(l_lastExpChip_fapi, + l_testEntry.addr, + l_scom_buffer); + l_tests++; + if(l_rc) + { + l_fails++; + TS_FAIL("testExpscomCombined>> Failed putScom writing 0x%.16X to 0x%.8X on target w/ huid 0x%.8X", + l_testEntry.data, + l_testEntry.addr, + get_huid(l_lastExpChip)); + } + + // Flush scom buffer so it doesnt mess up next test + l_scom_buffer.flush<0>(); + + // getScom to first OCMB + l_rc = get_scom(l_firstExpChip_fapi, + l_testEntry.addr, + l_scom_buffer); + l_tests++; + if(l_rc) + { + l_fails++; + TS_FAIL("testExpscomCombined>> Failed getScom reading 0x%.16X to 0x%.8X on target w/ huid 0x%.8X", + l_testEntry.data, + l_testEntry.addr, + get_huid(l_firstExpChip)); + } + + l_tests++; + if(l_scom_buffer() != l_testEntry.data) + { + l_fails++; + TS_FAIL("testExpscomCombined>> Expected 0x%.16X but got 0x%.16X on target w/ huid 0x%.8X", + l_testEntry.data, + l_scom_buffer(), + get_huid(l_firstExpChip)); + } + + // ODD tests : first target reads I2C, last target reads MMIO + // EVEN tests : first target reads MMIO, last target reads I2C + if(l_num % 2) + { + l_firstExpChip->setAttr<ATTR_SCOM_SWITCHES>(forceI2CScom); + l_lastExpChip->setAttr<ATTR_SCOM_SWITCHES>(forceMMIOScom); + } + else + { + l_firstExpChip->setAttr<ATTR_SCOM_SWITCHES>(forceMMIOScom); + l_lastExpChip->setAttr<ATTR_SCOM_SWITCHES>(forceI2CScom); + } + + // Flush scom buffer so it doesnt mess up next test + l_scom_buffer.flush<0>(); + + // getScom to last OCMB + l_rc = get_scom(l_lastExpChip_fapi, + l_testEntry.addr, + l_scom_buffer); + l_tests++; + if(l_rc) + { + l_fails++; + TS_FAIL("testExpscomCombined>> Failed getScom reading 0x%.16X to 0x%.8X on target w/ huid 0x%.8X", + l_testEntry.data, + l_testEntry.addr, + get_huid(l_lastExpChip)); + } + + l_tests++; + if(l_scom_buffer() != l_testEntry.data) + { + l_fails++; + TS_FAIL("testExpscomCombined>> Expected 0x%.16X but got 0x%.16X on target w/ huid 0x%.8X", + l_testEntry.data, + l_scom_buffer(), + get_huid(l_lastExpChip)); + } + } + + // Set ATTR_SCOM_SWITCHES back to their original values + l_firstExpChip->setAttr<ATTR_SCOM_SWITCHES>(first_ocmb_info); + l_lastExpChip->setAttr<ATTR_SCOM_SWITCHES>(last_ocmb_info); + + // << atomic section + mutex_unlock(iv_serializeTestMutex); + }while(0); + + TRACFCOMP(g_trac_expscom, "<< Exit testExpscomCombined"); +#endif + return; + } + + /** + * @brief Constructor + */ + expscomTest() : CxxTest::TestSuite() + { + // All modules are loaded by runtime, + // so testcase loading of modules is not required +#ifndef __HOSTBOOT_RUNTIME + errlHndl_t err = nullptr; + + err = exptest::loadModule(exptest::MSS_LIBRARY_NAME); + if(err) + { + TS_FAIL("expscomTest() - Constuctor: failed to load MSS module"); + errlCommit( err, CXXTEST_COMP_ID ); + } +#endif + iv_serializeTestMutex = exptest::getTestMutex(); + }; + + + /** + * @brief Destructor + */ + ~expscomTest() + { + }; }; diff --git a/src/usr/expaccess/test/exptest_utils.C b/src/usr/expaccess/test/exptest_utils.C new file mode 100644 index 000000000..01096716f --- /dev/null +++ b/src/usr/expaccess/test/exptest_utils.C @@ -0,0 +1,136 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/expaccess/test/exptest_utils.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#include <fapi2.H> +#include <cxxtest/TestSuite.H> +#include "exptest_utils.H" + +namespace exptest +{ + errlHndl_t loadModule(const char * i_modName) + { + errlHndl_t err = NULL; + + // VFS functions only compilable in non-runtime environment + #ifndef __HOSTBOOT_RUNTIME + if(!VFS::module_is_loaded(i_modName)) + { + err = VFS::module_load(i_modName); + if(err) + { + TS_FAIL("loadModule() - %s load failed", i_modName ); + } + else + { + FAPI_INF("loadModule: %s loaded", i_modName); + } + } + #endif + return err; + } + + TARGETING::HB_MUTEX_SERIALIZE_TEST_LOCK_ATTR getTestMutex(void) + { + TARGETING::HB_MUTEX_SERIALIZE_TEST_LOCK_ATTR pMutex = nullptr; + + // Get a reference to the target service + TARGETING::TargetService& l_targetService = TARGETING::targetService(); + + // Get the system target containing the test mutex + TARGETING::Target* l_pTarget = NULL; + (void) l_targetService.getTopLevelTarget(l_pTarget); + if (l_pTarget == nullptr) + { + TS_INFO("getTestMutex: Top level target handle is NULL"); + } + else + { + // use the chip-specific mutex attribute + pMutex = l_pTarget->getHbMutexAttr + <TARGETING::ATTR_HB_MUTEX_SERIALIZE_TEST_LOCK>(); + } + return pMutex; + } + + void enableInbandScomsOcmb(const TARGETING::TargetHandle_t i_ocmbTarget) + { + mutex_t* l_mutex = nullptr; + + assert((i_ocmbTarget != nullptr), + "enableInbandScomsOcmb: target is NULL!"); + + // Verify that the target is of type OCMB_CHIP + TARGETING::ATTR_TYPE_type l_targetType = + i_ocmbTarget->getAttr<TARGETING::ATTR_TYPE>(); + assert((l_targetType == TARGETING::TYPE_OCMB_CHIP), + "enableInbandScomsOcmb: target is not an OCMB chip!"); + + TS_INFO("enableInbandScomsOcmb: switching to use MMIO on OCMB 0x%08x", + TARGETING::get_huid(i_ocmbTarget)); + + //don't mess with attributes without the mutex (just to be safe) + l_mutex = i_ocmbTarget->getHbMutexAttr<TARGETING::ATTR_IBSCOM_MUTEX>(); + mutex_lock(l_mutex); + + TARGETING::ScomSwitches l_switches = + i_ocmbTarget->getAttr<TARGETING::ATTR_SCOM_SWITCHES>(); + l_switches.useInbandScom = 1; + l_switches.useI2cScom = 0; + + // Modify attribute + i_ocmbTarget->setAttr<TARGETING::ATTR_SCOM_SWITCHES>(l_switches); + mutex_unlock(l_mutex); + }; + + void disableInbandScomsOcmb(const TARGETING::TargetHandle_t i_ocmbTarget) + { + mutex_t* l_mutex = nullptr; + + assert((i_ocmbTarget != nullptr), + "disableInbandScomsOcmb: target is NULL!"); + + // Verify that the target is of type OCMB_CHIP + TARGETING::ATTR_TYPE_type l_targetType = + i_ocmbTarget->getAttr<TARGETING::ATTR_TYPE>(); + assert((l_targetType == TARGETING::TYPE_OCMB_CHIP), + "disableInbandScomsOcmb: target is not an OCMB chip!"); + + TS_INFO("disableInbandScomsOcmb: switching to use i2c on OCMB 0x%08x", + TARGETING::get_huid(i_ocmbTarget)); + + //don't mess with attributes without the mutex (just to be safe) + l_mutex = i_ocmbTarget->getHbMutexAttr<TARGETING::ATTR_IBSCOM_MUTEX>(); + mutex_lock(l_mutex); + + TARGETING::ScomSwitches l_switches = + i_ocmbTarget->getAttr<TARGETING::ATTR_SCOM_SWITCHES>(); + l_switches.useInbandScom = 0; + l_switches.useI2cScom = 1; + + // Modify attribute + i_ocmbTarget->setAttr<TARGETING::ATTR_SCOM_SWITCHES>(l_switches); + mutex_unlock(l_mutex); + }; + +} diff --git a/src/usr/expaccess/test/exptest_utils.H b/src/usr/expaccess/test/exptest_utils.H new file mode 100644 index 000000000..babba0fcf --- /dev/null +++ b/src/usr/expaccess/test/exptest_utils.H @@ -0,0 +1,64 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/expaccess/test/exptest_utils.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef EXPTEST_UTILS_H_ +#define EXPTEST_UTILS_H_ + +#ifndef __HOSTBOOT_RUNTIME +#include <vfs/vfs.H> // module_is_loaded & module_load +#endif + +namespace exptest +{ + +// Need this module for mss::c_str call in HWP failure path traces +const char MSS_LIBRARY_NAME[17] = "libisteps_mss.so"; + +/** + * @brief Generic function to load a module + * @param i_modName - module name to load + * @return error handle if module_load call fails + */ +errlHndl_t loadModule(const char * i_modName); + +/** + * @brief Get the mutex pointer for syncronizing tests + * @return pointer to mutex, nullptr if not found + */ +TARGETING::HB_MUTEX_SERIALIZE_TEST_LOCK_ATTR getTestMutex(void); + +/** + * @brief Enable inband scoms on an OCMB target + * @param[in] i_ocmbTarget The target OCMB chip + */ +void enableInbandScomsOcmb(const TARGETING::TargetHandle_t i_ocmbTarget); + +/** + * @brief Disable inband scoms on an OCMB target (use i2c instead) + * @param[in] i_ocmbTarget The target OCMB chip + */ +void disableInbandScomsOcmb(const TARGETING::TargetHandle_t i_ocmbTarget); +} + +#endif diff --git a/src/usr/expaccess/test/makefile b/src/usr/expaccess/test/makefile index 461a908c8..0e4f0e2e5 100644 --- a/src/usr/expaccess/test/makefile +++ b/src/usr/expaccess/test/makefile @@ -28,7 +28,6 @@ MODULE = testexpaccess include test.mk -#TODO RTC:196806 re-enable mmio communication tests when mmio works -TESTS = expscomtest.H +TESTS = *.H -include ${ROOTPATH}/config.mk
\ No newline at end of file +include ${ROOTPATH}/config.mk diff --git a/src/usr/expaccess/test/ocmbcommtest.H b/src/usr/expaccess/test/ocmbcommtest.H index 94d298032..3c5486a1b 100644 --- a/src/usr/expaccess/test/ocmbcommtest.H +++ b/src/usr/expaccess/test/ocmbcommtest.H @@ -33,13 +33,13 @@ #include <errl/errlmanager.H> #include <errl/errlentry.H> #include <fapi2.H> -#ifndef __HOSTBOOT_RUNTIME -#include <vfs/vfs.H> // module_is_loaded & module_load -#endif + #include <plat_hwp_invoker.H> -#include <exp_inband.H> +#include <lib/inband/exp_inband.H> #include <exp_data_structs.H> #include <generic/memory/lib/utils/endian_utils.H> +#include "exptest_utils.H" + // EXP_FW_ADAPTER_PROPERTIES_GET data response format #define FW_ADAPTER_MAX_FW_IMAGE 4 @@ -67,64 +67,6 @@ typedef struct } FW_ADAPTER_PROPERTIES_type; -// Need this module for mss::c_str call in HWP failure path traces -const char MSS_LIBRARY_NAME[17] = "libisteps_mss.so"; - -/** - * @brief Generic function to load a module - * @param o_module_loaded - returns true if module is loaded by this function - * @param i_modName - module name to load - * @return error handle if module_load call fails - */ -errlHndl_t loadModule(bool & o_module_loaded, const char * i_modName) -{ - errlHndl_t err = NULL; - o_module_loaded = false; - -// VFS functions only compilable in non-runtime environment -#ifndef __HOSTBOOT_RUNTIME - if(!VFS::module_is_loaded(i_modName)) - { - err = VFS::module_load(i_modName); - if(err) - { - TS_FAIL("loadModule() - %s load failed", i_modName ); - } - else - { - o_module_loaded = true; - FAPI_INF("loadModule: %s loaded", i_modName); - } - } -#endif - return err; -} - -/** - * @brief Generic function to unload a module - * @param i_modName - module name to load - * @return error handle if module_unload call fails - */ -errlHndl_t unloadModule(const char * i_modName) -{ - errlHndl_t err = NULL; - -// VFS function only compilable in non-runtime environment -#ifndef __HOSTBOOT_RUNTIME - err = VFS::module_unload(i_modName); - if(err) - { - TS_FAIL("unloadExplorerModule() - %s unload failed", i_modName ); - } - else - { - FAPI_INF("unloadModule: %s unloaded", i_modName); - } -#endif - return err; -} - - class OCMBCommTest: public CxxTest::TestSuite { public: @@ -189,11 +131,13 @@ class OCMBCommTest: public CxxTest::TestSuite } /** - * @brief Test the Explorer inband command/response path + * @brief Send and check get_properties Explorer inband command + * @return Number of failures */ - void testOcmbInbandCmdRsp( void ) + int sendOcmbInbandCmdRsp(bool setScomI2c) { errlHndl_t l_errl = nullptr; + uint8_t failures = 0; // Create a vector of TARGETING::Target pointers TARGETING::TargetHandleList l_chipList; @@ -210,102 +154,217 @@ class OCMBCommTest: public CxxTest::TestSuite for (auto & l_ocmb: l_chipList) { - FAPI_INF("testOcmbInbandCmdRsp: testing 0x%.8X OCMB", TARGETING::get_huid(l_ocmb)); - - fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>l_fapi2_target( l_ocmb ); + do + { + if (setScomI2c) + { + FAPI_INF("sendOcmbInbandCmdRsp: testing 0x%.8X OCMB using I2C", TARGETING::get_huid(l_ocmb)); + // disable inband and use i2c when possible + exptest::disableInbandScomsOcmb(l_ocmb); + } + else + { + FAPI_INF("sendOcmbInbandCmdRsp: testing 0x%.8X OCMB using MMIO", TARGETING::get_huid(l_ocmb)); + // just incase some other test disabled inband scoms + exptest::enableInbandScomsOcmb(l_ocmb); + } + + fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>l_fapi2_target( l_ocmb ); + + TRACFBIN(g_trac_expscom, "l_cmd: ", &l_cmd, sizeof(host_fw_command_struct)); + + // send the command + FAPI_INVOKE_HWP(l_errl, mss::exp::ib::putCMD, l_fapi2_target, + l_cmd); + if (l_errl) + { + TS_FAIL("Error from putCMD for 0x%.8X target", + TARGETING::get_huid(l_ocmb)); + failures++; + break; + } + + FAPI_INF("sendOcmbInbandCmdRsp: reading response"); + + // grab the response + FAPI_INVOKE_HWP(l_errl, mss::exp::ib::getRSP, l_fapi2_target, + l_rsp, l_rsp_data); + if (l_errl) + { + TS_FAIL("Error from getRSP for 0x%.8X target, plid=0x%X rc=0x%X", + TARGETING::get_huid(l_ocmb), + ERRL_GETPLID_SAFE(l_errl), ERRL_GETRC_SAFE(l_errl)); + failures++; + break; + } + + TRACFBIN(g_trac_expscom, "l_rsp: ", &l_rsp, sizeof(host_fw_response_struct)); + TRACFBIN(g_trac_expscom, "l_rsp_data: ", l_rsp_data.data(), l_rsp_data.size()); + + // Check for a valid data response length + if (l_rsp.response_length != sizeof(FW_ADAPTER_PROPERTIES_type)) + { + TS_FAIL("Unexpected response length 0x%.8X (expected 0x%.8X)", + l_rsp.response_length, sizeof(FW_ADAPTER_PROPERTIES_type)); + failures++; + break; + } + + // Now convert the little endian response data into big endian + FW_ADAPTER_PROPERTIES_type l_fw_adapter_data; + fw_adapter_properties_struct_from_little_endian(l_fw_adapter_data, + l_rsp_data); + + // Check for some expected response values + // Simics should return 0x88 as the first byte of chip_version + if (l_fw_adapter_data.chip_version[0] != 0x88 ) + { + TS_FAIL("Expected chip_version to start with 0x88, found 0x%02X", + l_fw_adapter_data.chip_version[0]); + failures++; + } + } while (0); - // send the command - FAPI_INVOKE_HWP(l_errl, mss::exp::ib::putCMD, l_fapi2_target, - l_cmd); if (l_errl) { - TS_FAIL("Error from putCMD for 0x%.8X target", - TARGETING::get_huid(l_ocmb)); - break; + // Commit the error as this is NOT expected and + // needs to be investigated + errlCommit( l_errl, TARG_COMP_ID ); } - // grab the response - FAPI_INVOKE_HWP(l_errl, mss::exp::ib::getRSP, l_fapi2_target, - l_rsp, l_rsp_data); - if (l_errl) + if (setScomI2c) { - TS_FAIL("Error from getRSP for 0x%.8X target", - TARGETING::get_huid(l_ocmb)); - break; + // Default the ocmb back to inband communication + exptest::enableInbandScomsOcmb(l_ocmb); } + } + + FAPI_INF("sendOcmbInbandCmdRsp: exiting"); + return failures; + }; + + /** + * @brief Test the Explorer inband command/response path over MMIO + */ + void testOcmbInbandCmdRspOverMMIO( void ) + { + if (!iv_serializeTestMutex) + { + TS_FAIL("iv_serializedTestMutex is not setup, unable to continue"); + } + else + { + // Inband operations can't be run at the same time + // atomic section >> + mutex_lock(iv_serializeTestMutex); - // Check for a valid data response length - if (l_rsp.response_length != sizeof(FW_ADAPTER_PROPERTIES_type)) + int failures = sendOcmbInbandCmdRsp(false); + if (failures) { - TS_FAIL("Unexpected response length 0x%.8X (expected 0x%.8X)", - l_rsp.response_length, sizeof(FW_ADAPTER_PROPERTIES_type)); - break; + TS_FAIL("testOcmbInbandCmdRspOverMMIO() failed: %d", failures); } + mutex_unlock(iv_serializeTestMutex); + } + } + + /** + * @brief Test the Explorer inband command/response path over I2C + * using ATTR_FORCE_SRAM_MMIO_OVER_I2C + */ + void testOcmbInbandCmdRspOverI2c_via_force( void ) + { + FAPI_INF("testOcmbInbandCmdRspOverI2c_via_force: entering"); + if (!iv_serializeTestMutex) + { + TS_FAIL("iv_serializedTestMutex is not setup, unable to continue"); + } + else + { + // Inband operations can't be run at the same time + // atomic section >> + mutex_lock(iv_serializeTestMutex); + + // Set FORCE_SRAM_MMIO_OVER_I2C to change to use I2C instead of MMIO + TARGETING::Target * l_sys = nullptr; + TARGETING::targetService().getTopLevelTarget(l_sys); + crit_assert(l_sys != nullptr); - // Now convert the little endian response data into big endian - FW_ADAPTER_PROPERTIES_type l_fw_adapter_data; - fw_adapter_properties_struct_from_little_endian(l_fw_adapter_data, - l_rsp_data); + l_sys->setAttr<TARGETING::ATTR_FORCE_SRAM_MMIO_OVER_I2C>(0x01); - // Check for some expected response values - // Simics should return 0x10 as the first byte of chip_version - if (l_fw_adapter_data.chip_version[0] != 0x10 ) + int failures = sendOcmbInbandCmdRsp(false); + if (failures) { - TS_FAIL("Expected chip_version to start with 0x10, found 0x%02X", - l_fw_adapter_data.chip_version[0]); + TS_FAIL("testOcmbInbandCmdRspOverI2c_via_force() failed: %d", failures); } + + // Restore using MMIO instead of I2C + l_sys->setAttr<TARGETING::ATTR_FORCE_SRAM_MMIO_OVER_I2C>(0x00); + + mutex_unlock(iv_serializeTestMutex); } + FAPI_INF("testOcmbInbandCmdRspOverI2c_via_force: exiting"); + } - if (l_errl) + /** + * @brief Test the Explorer inband command/response path over I2C + * using scom setting to i2c + */ + void testOcmbInbandCmdRspOverI2c_via_scom_switch( void ) + { + FAPI_INF("testOcmbInbandCmdRspOverI2c_via_scom_switch: entering"); + if (!iv_serializeTestMutex) { - errlCommit( l_errl, TARG_COMP_ID ); + TS_FAIL("iv_serializedTestMutex is not setup, unable to continue"); } - FAPI_INF("testOcmbInbandCmdRsp: exiting"); - }; + else + { + // Inband operations can't be run at the same time + // atomic section >> + mutex_lock(iv_serializeTestMutex); + + // Set SCOM_SWITCHES to use i2c instead of MMMIO when + // running the inband cmd/rsp operations + int failures = sendOcmbInbandCmdRsp(true); + if (failures) + { + TS_FAIL("testOcmbInbandCmdRspOverI2c_via_scom_switch() failed: %d", failures); + } + + mutex_unlock(iv_serializeTestMutex); + } + FAPI_INF("testOcmbInbandCmdRspOverI2c_via_scom_switch: exiting"); + } /** * @brief Constructor */ OCMBCommTest() : CxxTest::TestSuite() { - mss_module_loaded = false; - // All modules are loaded by runtime, // so testcase loading of modules is not required #ifndef __HOSTBOOT_RUNTIME errlHndl_t err = nullptr; - err = loadModule(mss_module_loaded, MSS_LIBRARY_NAME); + err = exptest::loadModule(exptest::MSS_LIBRARY_NAME); if(err) { TS_FAIL("OCMBCommTest() - Constuctor: failed to load MSS module"); errlCommit( err, TARG_COMP_ID ); } #endif + iv_serializeTestMutex = exptest::getTestMutex(); }; - /** * @brief Destructor */ ~OCMBCommTest() { - errlHndl_t err = nullptr; - if (mss_module_loaded) - { - err = unloadModule(MSS_LIBRARY_NAME); - if(err) - { - TS_FAIL("~OCMBCommTest() - Destructor: failed to unload MSS module"); - errlCommit( err, TARG_COMP_ID ); - } - } }; private: - // use this to keep track of if we need to unload any - // modules loaded by this testcase - bool mss_module_loaded; + // This is used for tests that need to not run operations at the same time + TARGETING::HB_MUTEX_SERIALIZE_TEST_LOCK_ATTR iv_serializeTestMutex; }; diff --git a/src/usr/expaccess/test/rcExpLog.C b/src/usr/expaccess/test/rcExpLog.C new file mode 100644 index 000000000..53e61cd5d --- /dev/null +++ b/src/usr/expaccess/test/rcExpLog.C @@ -0,0 +1,55 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/expaccess/test/rcExpLog.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/** + * @file rcExpLog.C + * @brief Call fapi2::ReturnCode functions for explorer logs + */ +#include <cxxtest/TestSuite.H> +#include <fapi2.H> +#include <plat_hwp_invoker.H> +#include <hwp_error_info.H> +#include <hwp_ffdc_classes.H> + +#include <rcExpLog.H> + +fapi2::ReturnCode exp_error_rc( + fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_ocmb_target, + const uint32_t i_active_log_size, + const uint32_t i_saved_log_size) +{ + FAPI_INF("Enter exp_error_rc (active %d, saved %d)...", + i_active_log_size, i_saved_log_size); + + FAPI_ASSERT(0, fapi2::COLLECT_EXPLORER_ERROR() + .set_OCMB_CHIP_TARGET(i_ocmb_target) + .set_EXP_ACTIVE_LOG_SIZE(i_active_log_size) + .set_EXP_SAVED_LOG_SIZE(i_saved_log_size), + "Testcase exp_error_rc assert"); + +fapi_try_exit: + + FAPI_INF("Exiting exp_error_rc..."); + return fapi2::current_err; +} diff --git a/src/usr/expaccess/test/rcExpLog.H b/src/usr/expaccess/test/rcExpLog.H new file mode 100644 index 000000000..c3193bef9 --- /dev/null +++ b/src/usr/expaccess/test/rcExpLog.H @@ -0,0 +1,49 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/expaccess/test/rcExpLog.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/** + * @file rcExpLog.H + * + * @brief These procedures provide fapi2 return codes with desired data to + * support testing from expErrlTest + */ +#ifndef _RC_EXPLOG_H_ +#define _RC_EXPLOG_H_ + +#include <fapi2.H> + + +/** + * @brief Creates a test RC with added Explorer log trace data + * @param i_ocmb_target - Explorer target + * @param i_active_log_size - maximum size of active (RAM) data to add + * @param i_saved_log_size - maximum size of saved (SPI flash) data to add + * @return ReturnCode with added error log data + */ +fapi2::ReturnCode exp_error_rc( + fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_ocmb_target, + const uint32_t i_active_log_size, + const uint32_t i_saved_log_size ); + +#endif diff --git a/src/usr/expaccess/test/test.mk b/src/usr/expaccess/test/test.mk index 059efe27d..9dd8237df 100644 --- a/src/usr/expaccess/test/test.mk +++ b/src/usr/expaccess/test/test.mk @@ -22,14 +22,23 @@ # permissions and limitations under the License. # # IBM_PROLOG_END_TAG -EXTRAINCDIR += ${ROOTPATH}/src/include/usr/fapi2 -EXTRAINCDIR += ${ROOTPATH}/src/import/hwpf/fapi2/include -EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/utils/imageProcs -EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/procedures/hwp/ffdc -EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared +EXTRAINCDIR += ${ROOTPATH}/src/include/usr/fapi2/ +EXTRAINCDIR += ${ROOTPATH}/src/import/hwpf/fapi2/include/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/utils/imageProcs/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/procedures/hwp/ffdc/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/explorer/procedures/hwp/memory/ -EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/explorer/common/include -EXTRAINCDIR += ${ROOTPATH}/src/import +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/explorer/common/include/ +EXTRAINCDIR += ${ROOTPATH}/src/import/ +EXTRAINCDIR += ${ROOTPATH}/src/usr/expaccess/ +EXTRAINCDIR += ${ROOTPATH}/src/usr/expaccess/test/ +VPATH += ${ROOTPATH}/src/usr/expaccess/test/ +VPATH += ${ROOTPATH}/src/usr/expaccess/ +VPATH += ${ROOTPATH}/src/import/chips/p9/procedures/hwp/ffdc/ + +OBJS += exptest_utils.o +OBJS += exp_collect_explorer_log.o +OBJS += rcExpLog.o include ${ROOTPATH}/config.mk diff --git a/src/usr/fapi2/attribute_service.C b/src/usr/fapi2/attribute_service.C index 0c7442fd9..4b994fe65 100644 --- a/src/usr/fapi2/attribute_service.C +++ b/src/usr/fapi2/attribute_service.C @@ -48,12 +48,14 @@ #include <target.H> #include <target_types.H> #include <hwpf_fapi2_reasoncodes.H> +#include <chipids.H> #include <devicefw/driverif.H> #include <plat_attr_override_sync.H> #include <vpd/spdenums.H> #include <p9_pm_get_poundv_bucket_attr.H> #include <p9_pm_get_poundw_bucket_attr.H> +#include <p9_frequency_buckets.H> #include <errl/errlmanager.H> #include <targeting/common/targetservice.H> @@ -178,11 +180,11 @@ errlHndl_t getTargetingTarget(const Target<TARGET_TYPE_ALL>& i_pFapiTarget, return l_errl; } -bool getTargetingAttrHelper(TARGETING::Target * l_pTargTarget, +bool getTargetingAttrHelper(TARGETING::Target * i_pTargTarget, const TARGETING::ATTRIBUTE_ID i_targAttrId, const uint32_t i_attrSize, void * o_pAttr) { - return l_pTargTarget->_tryGetAttr(i_targAttrId, i_attrSize, o_pAttr); + return i_pTargTarget->_tryGetAttr(i_targAttrId, i_attrSize, o_pAttr); } /// @@ -365,9 +367,52 @@ ReturnCode platGetTargetName(const Target<TARGET_TYPE_ALL>& i_pFapiTarget, { o_name = ENUM_ATTR_NAME_AXONE; } - else if (l_model == TARGETING::MODEL_EXPLORER) + else if (l_model == TARGETING::MODEL_OCMB) { - o_name = ENUM_ATTR_NAME_EXPLORER; + // For MODEL_OCMB the ATTR_CHIP_ID determines if it is a + // Gemini or an Explorer chip + uint32_t l_chipID = + l_pHbTarget->getAttr<TARGETING::ATTR_CHIP_ID>(); + + if (l_chipID == POWER_CHIPID::EXPLORER_16) + { + o_name = ENUM_ATTR_NAME_EXPLORER; + } + else if (l_chipID == POWER_CHIPID::GEMINI_16) + { + o_name = ENUM_ATTR_NAME_GEMINI; + } + else + { + FAPI_ERR("platGetTargetName. Unknown CHIP_ID 0x%x for MODEL_OCMB 0x%x", l_chipID, l_model); + + /*@ + * @errortype + * @moduleid fapi2::MOD_FAPI2_GET_TARGETING_TARGET + * @reasoncode RC_UNKNOWN_OCMB_CHIP_TYPE + * @userdata1[0:31] FAPI2 Type + * @userdata1[32:63] HB Target HUID + * @userdata2[0:31] HB Type + * @userdata2[32:63] HB Target CHIP_ID + * @devdesc HB OCMB_CHIP target found with unknown + * model based on ATTR_CHIP_ID + * @custdesc Firmware Error + */ + l_errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE, + MOD_FAPI2_GET_TARGETING_TARGET, + RC_UNKNOWN_OCMB_CHIP_TYPE, + TWO_UINT32_TO_UINT64( + i_pFapiTarget.getType(), + TARGETING::get_huid(l_pHbTarget) + ), + TWO_UINT32_TO_UINT64( + l_pHbTarget-> + getAttr<TARGETING::ATTR_TYPE>(), + l_chipID)); + + l_rc.setPlatDataPtr(reinterpret_cast<void *> (l_errl)); + break; + } } else { @@ -466,6 +511,40 @@ ReturnCode platGetTargetPos(const Target<TARGET_TYPE_ALL>& i_pFapiTarget, } //****************************************************************************** +// fapi::platAttrSvc::platErrorOnSet function +//****************************************************************************** +ReturnCode platErrorOnSet( TARGETING::Target * i_pTargTarget, + const fapi2::AttributeId i_fapiAttrId ) +{ + // Just create an error to return back + FAPI_ERR("platErrorOnSet: Set not valid for Attribute %X on Target %.8X", + i_fapiAttrId, TARGETING::get_huid(i_pTargTarget) ); + /*@ + * @errortype + * @moduleid fapi2::MOD_FAPI2_PLAT_ERROR_ON_SET + * @reasoncode fapi2::RC_SET_ATTR_NOT_VALID + * @userdata1 Target HUID + * @userdata2 FAPI Attribute Id + * @devdesc platErrorOnSet> Set operation not valid + * @custdesc Firmware error + */ + errlHndl_t l_errl = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + fapi2::MOD_FAPI2_PLAT_ERROR_ON_SET, + fapi2::RC_SET_ATTR_NOT_VALID, + TARGETING::get_huid(i_pTargTarget), + i_fapiAttrId, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + l_errl->collectTrace(FAPI_TRACE_NAME); + l_errl->collectTrace(FAPI_IMP_TRACE_NAME); + + // attach our log to the fapi RC and return it + ReturnCode l_rc; + l_rc.setPlatDataPtr(reinterpret_cast<void *> (l_errl)); + return l_rc; +} + +//****************************************************************************** // fapi::platAttrSvc::platGetFusedCoreMode function //****************************************************************************** ReturnCode platGetFusedCoreMode(uint8_t & o_isFused) @@ -2001,6 +2080,7 @@ ReturnCode platGetDQAttrISDIMM( } else { + mutex_lock(&l_C4DQmutex); auto l_huid = TARGETING::get_huid(l_pTarget); auto l_iterator = std::find ( l_cachedC4DQValues.begin(), l_cachedC4DQValues.end(), @@ -2013,14 +2093,13 @@ ReturnCode platGetDQAttrISDIMM( l_kvPair.huid = l_huid; rc = getDQAttrISDIMM(l_fapiTarget, l_kvPair.value); memcpy(o_vpdIsDimmTOC4DQVal, l_kvPair.value, sizeof(ATTR_CEN_VPD_ISDIMMTOC4DQ_Type)); - mutex_lock(&l_C4DQmutex); l_cachedC4DQValues.push_back(l_kvPair); - mutex_unlock(&l_C4DQmutex); } else { memcpy(o_vpdIsDimmTOC4DQVal, (*l_iterator).value, sizeof(ATTR_CEN_VPD_ISDIMMTOC4DQ_Type)); } + mutex_unlock(&l_C4DQmutex); } return rc; @@ -2052,6 +2131,7 @@ ReturnCode platGetDQSAttrISDIMM( } else { + mutex_lock(&l_C4DQSmutex); auto l_huid = TARGETING::get_huid(l_pTarget); auto l_iterator = std::find ( l_cachedC4DQSValues.begin(), l_cachedC4DQSValues.end(), @@ -2065,14 +2145,13 @@ ReturnCode platGetDQSAttrISDIMM( l_kvPair.huid = l_huid; rc = getDQSAttrISDIMM(l_fapiTarget, l_kvPair.value); memcpy(o_vpdIsDimmTOC4DQSVal, l_kvPair.value, sizeof(ATTR_CEN_VPD_ISDIMMTOC4DQS_Type)); - mutex_lock(&l_C4DQSmutex); l_cachedC4DQSValues.push_back(l_kvPair); - mutex_unlock(&l_C4DQSmutex); } else { memcpy(o_vpdIsDimmTOC4DQSVal, (*l_iterator).value, sizeof(ATTR_CEN_VPD_ISDIMMTOC4DQS_Type)); } + mutex_unlock(&l_C4DQSmutex); } return rc; @@ -2652,11 +2731,12 @@ ReturnCode platGetMBvpdSlopeInterceptData( return rc; } +#ifndef CONFIG_AXONE //****************************************************************************** // fapi::platAttrSvc::platGetFreqMcaMhz function //****************************************************************************** ReturnCode platGetFreqMcaMhz(const Target<TARGET_TYPE_ALL>& i_fapiTarget, - uint32_t & o_val) + ATTR_FREQ_MCA_MHZ_Type & o_val) { // The POR config for Cumulus is to run the MC/DMI clocks directly // off of the NEST PLL in 'sync' mode. To support 'sync' mode FW @@ -2679,7 +2759,350 @@ ReturnCode platGetFreqMcaMhz(const Target<TARGET_TYPE_ALL>& i_fapiTarget, return l_rc; } +#else + +/// @brief This function is called by the FAPI_ATTR_GET functions that lookup +/// values in the MEM_PLL_FREQ_BUCKETS tree. The key's used to lookup values in that +/// tree are the ATTR_FREQ_OMI_MHZ and ATTR_OMI_PLL_VCO attributes. These are on the +/// processor target but it is expected that all of the values match. +/// @param[out] o_omiFreq OMI Frequency of the system +/// @param[out] o_omiVco OMI VCO of the system +/// @return ReturnCode Zero on success, else platform specified error. +errlHndl_t getOmiFreqAndVco(TARGETING::ATTR_FREQ_OMI_MHZ_type & o_omiFreq, + TARGETING::ATTR_OMI_PLL_VCO_type & o_omiVco) +{ + errlHndl_t l_errl = nullptr; + + // Get all functional Proc targets + TARGETING::TargetHandleList l_procsList; + getAllChips(l_procsList, TARGETING::TYPE_PROC); + uint8_t l_firstValidProc = 0; + bool l_outValueSet = false; + + // Until we are told we need to support individual processor frequency + // assert that all of the processors have the same values + for(uint8_t i = 0; i < l_procsList.size(); i++) + { + // Get a list of functional OCMB targets under this processor + TARGETING::TargetHandleList l_childOcmbList; + TARGETING::getChildAffinityTargets(l_childOcmbList, l_procsList[i], + TARGETING::CLASS_CHIP, + TARGETING::TYPE_OCMB_CHIP); + // If there are no OCMB children for this processor then ignore it; + if(l_childOcmbList.size() == 0) + { + continue; + } + + // First valid processor's values will be used to compare against all other processors + if(!l_outValueSet) + { + o_omiFreq = l_procsList[i]->getAttr<TARGETING::ATTR_FREQ_OMI_MHZ>(); + o_omiVco = l_procsList[i]->getAttr<TARGETING::ATTR_OMI_PLL_VCO>(); + l_outValueSet = true; + l_firstValidProc = i; + continue; + } + + TARGETING::ATTR_FREQ_OMI_MHZ_type l_omiFreqToCmp = l_procsList[i]->getAttr<TARGETING::ATTR_FREQ_OMI_MHZ>(); + TARGETING::ATTR_OMI_PLL_VCO_type l_omiVcoToCmp = l_procsList[i]->getAttr<TARGETING::ATTR_OMI_PLL_VCO>(); + + // If this processors OMI freq is 0 then we have not determined this proc's OMI freq yet so we can ignore it. + // Otherwise, if we found that this processor's OMI freq / vco values do not match the first processor's values then + // return an error + if ((l_omiFreqToCmp != 0) && + (l_omiFreqToCmp != o_omiFreq || + l_omiVcoToCmp != o_omiVco )) + { + FAPI_ERR("platGetMcPllBucket: Detected two processors with difference OMI VCO / FREQ combinations." + " Proc 0x%.08X has OMI freq = %d and OMI vco = %d. " + " Proc 0x%.08X has OMI freq = %d and OMI vco = %d. " , + get_huid(l_procsList[l_firstValidProc]), o_omiFreq, o_omiVco, + get_huid(l_procsList[i]), l_omiFreqToCmp, l_omiVcoToCmp ); + /*@ + * @errortype + * @moduleid fapi2::MOD_GET_OMI_FREQ_AND_VCO + * @reasoncode fapi2::RC_PROC_FREQ_MISMATCH + * @userdata1[0:31] first ATTR_FREQ_OMI_MHZ found + * @userdata1[32:63] first ATTR_FREQ_PLL_VCO found + * @userdata2[0:31] ATTR_FREQ_OMI_MHZ mismatch found + * @userdata2[32:63] ATTR_FREQ_PLL_VCO mismatch found + * @devdesc Found mismatching processor attribute settings + * when we expect them to all be in sync + */ + l_errl = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + fapi2::MOD_GET_OMI_FREQ_AND_VCO, + fapi2::RC_NO_MATCHING_FREQ, + TWO_UINT32_TO_UINT64(o_omiFreq, o_omiVco), + TWO_UINT32_TO_UINT64(l_omiFreqToCmp, l_omiVcoToCmp), + ERRORLOG::ErrlEntry::NO_SW_CALLOUT); + l_errl->collectTrace(FAPI_IMP_TRACE_NAME, 256); + break; + } + } + + return l_errl; +} + +// OMI bucket descriptor +struct OmiFreqVcoBucketSelect_t +{ + uint32_t omifreq; // OMI Frequency in MHz + uint32_t vco; // VCO selector + uint8_t pll_bucket; // MCA Frequency in MHz +}; + + +//****************************************************************************** +// fapi::platAttrSvc::platGetMcPllBucket function +//****************************************************************************** +ReturnCode platGetMcPllBucket(const Target<TARGET_TYPE_ALL>& i_fapiTarget, + ATTR_MC_PLL_BUCKET_Type & o_val) +{ + fapi2::ReturnCode l_rc; + errlHndl_t l_errl = nullptr; + TARGETING::Target * l_sysTarget = nullptr; + TARGETING::ATTR_FREQ_OMI_MHZ_type l_omiFreq = 0; + TARGETING::ATTR_OMI_PLL_VCO_type l_omiVco = 0; + bool l_matchFound = false; + + // There can be up to 2 matches for OMI frequencies. If only 1 match is found + // then we ignore the VCO attribute + std::vector<OmiFreqVcoBucketSelect_t> l_omiFreqMatches; + + do{ + // Convert to platform-style target + l_errl = getTargetingTarget(i_fapiTarget, l_sysTarget); + + if(l_errl) + { + FAPI_ERR("platGetMcPllBucket: Error from getTargetingTarget"); + l_rc.setPlatDataPtr(reinterpret_cast<void *> (l_errl)); + break; + } + + // Use helper function to lookup omi frequency and omi vco for this system + l_errl = getOmiFreqAndVco(l_omiFreq, l_omiVco); + + if(l_errl) + { + l_rc.setPlatDataPtr(reinterpret_cast<void *> (l_errl)); + break; + } + + // Loop through the MEM_PLL frequency buckets to see if we can find a bucket that + // matches what we have found for omi freq and vco + for(uint8_t i = 0; i < MEM_PLL_FREQ_BUCKETS; i++) + { + if(OMI_PLL_FREQ_LIST[i].omifreq == l_omiFreq) + { + OmiFreqVcoBucketSelect_t l_tmpBucketSelect = {OMI_PLL_FREQ_LIST[i].omifreq, OMI_PLL_FREQ_LIST[i].vco, i}; + l_omiFreqMatches.push_back(l_tmpBucketSelect); + } + } + + if(l_omiFreqMatches.size() > 1) + { + for(uint8_t i = 0; i < l_omiFreqMatches.size(); i++) + { + if(l_omiFreqMatches[i].vco == l_omiVco) + { + FAPI_INF("Found match to be bucket %d for freq %d, vco %d", + l_omiFreqMatches[i].pll_bucket, + OMI_PLL_FREQ_LIST[i].omifreq, + OMI_PLL_FREQ_LIST[i].vco); + l_matchFound = true; + // Value returned in this case is the bucket number that had the matching values + // MC_PLL_BUCKET attribute is 1-based so increment bucket ID by 1 + o_val = l_omiFreqMatches[i].pll_bucket + 1; + break; + } + } + } + else if (l_omiFreqMatches.size() == 1) + { + FAPI_INF("Single match for OMI freq %d found in OMI_PLL_FREQ_LIST, ignoring VCO attribute. PLL Bucket = %d", + l_omiFreq, + l_omiFreqMatches[0].pll_bucket); + l_matchFound = true; + // MC_PLL_BUCKET attribute is 1-based so increment bucket ID by 1 + o_val = l_omiFreqMatches[0].pll_bucket + 1; + } + + // If not match is found return an error + if(!l_matchFound) + { + FAPI_ERR("platGetMcPllBucket: Could not find matching bucket for omiFreq = %d and vco = %d", + l_omiFreq, l_omiVco); + + /*@ + * @errortype + * @moduleid fapi2::MOD_FAPI2_PLAT_GET_MC_PLL_BUCKET + * @reasoncode fapi2::RC_NO_MATCHING_FREQ + * @userdata1[0:31] ATTR_FREQ_OMI_MHZ + * @userdata1[32:63] ATTR_FREQ_PLL_VCO + * @userdata2 Target HUID + * @devdesc Invalid omi frequence and omi vco settings + */ + l_errl = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + fapi2::MOD_FAPI2_PLAT_GET_MC_PLL_BUCKET, + fapi2::RC_NO_MATCHING_FREQ, + TWO_UINT32_TO_UINT64(l_omiFreq, l_omiVco), + TARGETING::get_huid(l_sysTarget), + ERRORLOG::ErrlEntry::NO_SW_CALLOUT); + l_errl->collectTrace(FAPI_IMP_TRACE_NAME, 256); + l_rc.setPlatDataPtr(reinterpret_cast<void *> (l_errl)); + break; + } + + }while(0); + return l_rc; +} + +//****************************************************************************** +// fapi::platAttrSvc::platGetFreqMcaMhz function +//****************************************************************************** +ReturnCode platGetFreqMcaMhz(const Target<TARGET_TYPE_ALL>& i_fapiTarget, + ATTR_FREQ_MCA_MHZ_Type & o_val) +{ + fapi2::ReturnCode l_rc; + errlHndl_t l_errl = nullptr; + TARGETING::Target * l_sysTarget = nullptr; + TARGETING::ATTR_FREQ_OMI_MHZ_type l_omiFreq = 0; + TARGETING::ATTR_OMI_PLL_VCO_type l_omiVco = 0; + bool l_matchFound = false; + + // There can be up to 2 matches for OMI frequencies. If only 1 match is found + // then we ignore the VCO attribute + std::vector<OmiBucketDescriptor_t> l_matchingOmiBucketDescriptors; + + do{ + // Convert to platform-style target + l_errl = getTargetingTarget(i_fapiTarget, l_sysTarget); + + if(l_errl) + { + FAPI_ERR("platGetFreqMcaMhz: Error from getTargetingTarget"); + l_rc.setPlatDataPtr(reinterpret_cast<void *> (l_errl)); + break; + } + + // Use helper function to lookup omi frequency and omi vco for this system + l_errl = getOmiFreqAndVco(l_omiFreq, l_omiVco); + + if(l_errl) + { + l_rc.setPlatDataPtr(reinterpret_cast<void *> (l_errl)); + break; + } + + // Loop through the MEM_PLL frequency buckets to see if we can find a bucket that + // matches what we have found for omi freq and vco + for(uint8_t i = 0; i < MEM_PLL_FREQ_BUCKETS; i++) + { + if(OMI_PLL_FREQ_LIST[i].omifreq == l_omiFreq) + { + l_matchingOmiBucketDescriptors.push_back(OMI_PLL_FREQ_LIST[i]); + } + } + + if(l_matchingOmiBucketDescriptors.size() > 1) + { + for(uint8_t i = 0; i < l_matchingOmiBucketDescriptors.size(); i++) + { + if(l_matchingOmiBucketDescriptors[i].vco == l_omiVco) + { + FAPI_INF("found match for freq %d, vco %d. Mca freq = %d", + OMI_PLL_FREQ_LIST[i].omifreq, OMI_PLL_FREQ_LIST[i].vco); + l_matchFound = true; + // Value returned in this case is the bucket number that had the matching values + o_val = l_matchingOmiBucketDescriptors[i].mcafreq; + break; + } + } + } + else if (l_matchingOmiBucketDescriptors.size() == 1) + { + FAPI_INF("Single match for OMI freq %d found in OMI_PLL_FREQ_LIST, MCA freq found = %d, ignoring VCO attribute", + l_omiFreq, + l_matchingOmiBucketDescriptors[0].mcafreq); + l_matchFound = true; + o_val = l_matchingOmiBucketDescriptors[0].mcafreq; + } + + if(!l_matchFound) + { + FAPI_ERR("platGetFreqMcaMhz: Could not find matching bucket for omiFreq = %d and vco = %d", + l_omiFreq, l_omiVco); + + /*@ + * @errortype + * @moduleid fapi2::MOD_FAPI2_PLAT_GET_FREQ_MCA_MHZ + * @reasoncode fapi2::RC_NO_MATCHING_FREQ + * @userdata1[0:31] ATTR_FREQ_OMI_MHZ + * @userdata1[32:63] ATTR_FREQ_PLL_VCO + * @userdata2 Target HUID + * @devdesc Invalid omi frequence and omi vco settings + */ + l_errl = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + fapi2::MOD_FAPI2_PLAT_GET_FREQ_MCA_MHZ, + fapi2::RC_NO_MATCHING_FREQ, + TWO_UINT32_TO_UINT64(l_omiFreq, l_omiVco), + TARGETING::get_huid(l_sysTarget), + ERRORLOG::ErrlEntry::NO_SW_CALLOUT); + l_rc.setPlatDataPtr(reinterpret_cast<void *> (l_errl)); + break; + } + + }while(0); + return l_rc; +} + + + +#endif + +//****************************************************************************** +// fapi::platAttrSvc::platIncrementCounter function +//****************************************************************************** +ReturnCode platIncrementOcmbCounter(const Target<TARGET_TYPE_ALL>& i_fapiTarget, + uint32_t & o_val) +{ + fapi2::ReturnCode rc; + errlHndl_t l_errl = nullptr; + + TARGETING::Target * l_chipTarget = nullptr; + static mutex_t l_counter_mutex = MUTEX_INITIALIZER; + l_errl = getTargetingTarget(i_fapiTarget, l_chipTarget); + if (l_errl) + { + FAPI_ERR("platIncrementOcmbCounter: Error from getTargetingTarget"); + rc.setPlatDataPtr(reinterpret_cast<void *> (l_errl)); + } + else + { + mutex_lock(&l_counter_mutex); + o_val = l_chipTarget->getAttr<TARGETING::ATTR_OCMB_COUNTER_HB>(); + if( o_val == 0 ) + { + // seed each target with a unique number to make messages more + // distinct across operations + o_val = (l_chipTarget->getAttr<TARGETING::ATTR_HUID>() + && 0x0000FFFF) << 16; + } + else + { + ++o_val; + } + l_chipTarget->setAttr<TARGETING::ATTR_OCMB_COUNTER_HB>(o_val); + mutex_unlock(&l_counter_mutex); + } + return rc; +} } // End platAttrSvc namespace } // End fapi2 namespace diff --git a/src/usr/fapi2/dimmBadDqBitmapFuncs.C b/src/usr/fapi2/dimmBadDqBitmapFuncs.C index 8fb4b9fe0..170c022c5 100644 --- a/src/usr/fapi2/dimmBadDqBitmapFuncs.C +++ b/src/usr/fapi2/dimmBadDqBitmapFuncs.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017,2018 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -38,8 +38,8 @@ extern "C" // Utility function to check parameters and get the Bad DQ bitmap //------------------------------------------------------------------------------ fapi2::ReturnCode dimmBadDqCheckParamGetBitmap( const fapi2::Target - <fapi2::TARGET_TYPE_MCA|fapi2::TARGET_TYPE_MBA|fapi2::TARGET_TYPE_MEM_PORT> - & i_fapiTrgt, + <fapi2::TARGET_TYPE_MCA|fapi2::TARGET_TYPE_MBA| + fapi2::TARGET_TYPE_MEM_PORT|fapi2::TARGET_TYPE_OCMB_CHIP> & i_fapiTrgt, const uint8_t i_port, const uint8_t i_dimm, const uint8_t i_rank, @@ -115,8 +115,8 @@ fapi2::ReturnCode dimmBadDqCheckParamGetBitmap( const fapi2::Target //------------------------------------------------------------------------------ fapi2::ReturnCode p9DimmGetBadDqBitmap( const fapi2::Target - <fapi2::TARGET_TYPE_MCA|fapi2::TARGET_TYPE_MBA|fapi2::TARGET_TYPE_MEM_PORT> - & i_fapiTrgt, + <fapi2::TARGET_TYPE_MCA|fapi2::TARGET_TYPE_MBA| + fapi2::TARGET_TYPE_MEM_PORT|fapi2::TARGET_TYPE_OCMB_CHIP> & i_fapiTrgt, const uint8_t i_dimm, const uint8_t i_rank, uint8_t (&o_data)[mss::BAD_DQ_BYTE_COUNT], @@ -151,8 +151,8 @@ fapi2::ReturnCode p9DimmGetBadDqBitmap( const fapi2::Target //------------------------------------------------------------------------------ fapi2::ReturnCode p9DimmSetBadDqBitmap( const fapi2::Target - <fapi2::TARGET_TYPE_MCA|fapi2::TARGET_TYPE_MBA|fapi2::TARGET_TYPE_MEM_PORT> - & i_fapiTrgt, + <fapi2::TARGET_TYPE_MCA|fapi2::TARGET_TYPE_MBA| + fapi2::TARGET_TYPE_MEM_PORT|fapi2::TARGET_TYPE_OCMB_CHIP> & i_fapiTrgt, const uint8_t i_dimm, const uint8_t i_rank, const uint8_t (&i_data)[mss::BAD_DQ_BYTE_COUNT], @@ -179,17 +179,8 @@ fapi2::ReturnCode p9DimmSetBadDqBitmap( const fapi2::Target // Add the rank bitmap to the DIMM bitmap and write the bitmap. memcpy( l_dqBitmap[i_rank], i_data, mss::BAD_DQ_BYTE_COUNT ); - errlHndl_t l_errl = nullptr; - TARGETING::TargetHandle_t l_trgt = nullptr; - l_errl = fapi2::platAttrSvc::getTargetingTarget(i_fapiTrgt, l_trgt); - if ( l_errl ) - { - FAPI_ERR( "p9DimmSetBadDqBitmap: Error from getTargetingTarget" ); - break; - } - l_rc = FAPI_ATTR_SET( fapi2::ATTR_BAD_DQ_BITMAP, l_dimmTrgt, - l_dqBitmap ); + l_dqBitmap ); if ( l_rc ) { diff --git a/src/usr/fapi2/fapi2.mk b/src/usr/fapi2/fapi2.mk index c69d77c92..713e3e80b 100755 --- a/src/usr/fapi2/fapi2.mk +++ b/src/usr/fapi2/fapi2.mk @@ -59,6 +59,10 @@ EXTRAINCDIR += ${HWP_PATH_2}/hwp/memory/lib/shared/ EXTRAINCDIR += ${HWP_PATH_2}/hwp/memory/lib/utils/ EXTRAINCDIR += ${HWP_PATH_2}/vpd_accessors/ EXTRAINCDIR += ${ROOTPATH}/src/usr/scom/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/explorer/common/include/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/utils/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/common/include/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/explorer/procedures/hwp/memory/ include ${ROOTPATH}/src/build/mkrules/verbose.rules.mk define __CLEAN_TARGET @@ -128,6 +132,10 @@ FAPI2_ERROR_XML += $(wildcard \ $(ROOTPATH)/src/import/chips/ocmb/explorer/procedures/xml/error_info/*.xml) FAPI2_ERROR_XML += $(wildcard \ $(ROOTPATH)/src/import/chips/p9a/procedures/xml/error_info/*.xml) +FAPI2_ERROR_XML += $(wildcard \ + $(ROOTPATH)/src/import/chips/ocmb/gemini/procedures/xml/error_info/*.xml) +FAPI2_ERROR_XML += $(wildcard \ + $(ROOTPATH)/src/import/chips/ocmb/common/procedures/xml/error_info/*.xml) # Attribute XML files. FAPI2_ATTR_XML += $(wildcard \ @@ -140,6 +148,10 @@ FAPI2_ATTR_XML += $(wildcard \ $(ROOTPATH)/src/import/generic/procedures/xml/attribute_info/*.xml) FAPI2_ATTR_XML += $(wildcard \ $(ROOTPATH)/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/*.xml) +FAPI2_ATTR_XML += $(wildcard \ + $(ROOTPATH)/src/import/chips/ocmb/gemini/procedures/xml/attribute_info/*.xml) +FAPI2_ATTR_XML += $(wildcard \ + $(ROOTPATH)/src/import/chips/ocmb/common/procedures/xml/attribute_info/*.xml) # Filter out Temp defaults XML file from Attribute XML files. # NOTE: The hb_temp_defaults.xml file is not a normal attribute file with the diff --git a/src/usr/fapi2/platCreateHwpErrParser.pl b/src/usr/fapi2/platCreateHwpErrParser.pl index 618459e30..84fc84316 100755 --- a/src/usr/fapi2/platCreateHwpErrParser.pl +++ b/src/usr/fapi2/platCreateHwpErrParser.pl @@ -6,9 +6,10 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2015,2018 +# Contributors Listed Below - COPYRIGHT 2015,2019 # [+] Google Inc. # [+] International Business Machines Corp. +# [+] YADRO # # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -78,13 +79,14 @@ print TGFILE "// This file is generated by perl script platCreateHwpErrParser.pl print TGFILE "#ifndef HBFWPLATHWPERRPARSER_H_\n"; print TGFILE "#define HBFWPLATHWPERRPARSER_H_\n\n"; print TGFILE "#if defined(PARSER) || defined(LOGPARSER)\n\n"; +print TGFILE "#include \"errluserdetails.H\"\n\n"; print TGFILE "namespace fapi2\n"; print TGFILE "{\n\n"; print TGFILE "void hbfwParseHwpRc(ErrlUsrParser & i_parser,\n"; print TGFILE " void * i_pBuffer,\n"; print TGFILE " const uint32_t i_buflen)\n"; print TGFILE "{\n"; -print TGFILE " uint32_t l_rc = ntohl(*(static_cast<uint32_t *>(i_pBuffer)));\n"; +print TGFILE " uint32_t l_rc = ntohl(ERRORLOG::UINT32_FROM_PTR(i_pBuffer));\n"; print TGFILE " switch(l_rc)\n"; print TGFILE " {\n"; @@ -225,6 +227,7 @@ print EDISFILE "#include <p9_perv_scom_addresses.H>\n"; print EDISFILE "#include <p9_quad_scom_addresses.H>\n"; print EDISFILE "#include <p9_xbus_scom_addresses.H>\n"; print EDISFILE "#include <cen_gen_scom_addresses.H>\n"; +print EDISFILE "#include <explorer_scom_addresses.H>\n"; print EDISFILE "#include <centaur_misc_constants.H>\n"; print EDISFILE "namespace fapi2\n"; print EDISFILE "{\n\n"; @@ -243,7 +246,7 @@ print TGFILE " uint8_t * l_pBuffer = static_cast<uint8_t *>(i_pBuffer);\n"; print TGFILE " uint32_t l_buflen = i_buflen;\n\n"; print TGFILE " // The first uint32_t is the FFDC ID\n"; print TGFILE " uint32_t * l_pFfdcId = static_cast<uint32_t *>(i_pBuffer);\n"; -print TGFILE " uint32_t l_ffdcId = ntohl(*l_pFfdcId);\n"; +print TGFILE " uint32_t l_ffdcId = ntohl(ERRORLOG::UINT32_FROM_PTR(l_pFfdcId));\n"; print TGFILE " l_pBuffer += sizeof(l_ffdcId);\n"; print TGFILE " l_buflen -= sizeof(l_ffdcId);\n"; print TGFILE " switch(l_ffdcId)\n"; @@ -364,7 +367,7 @@ foreach my $argnum (1 .. $#ARGV) print TGFILE " if (l_buflen >= POS_LEN)\n"; print TGFILE " {\n"; print TGFILE " uint32_t * l_pBufferTemp = reinterpret_cast<uint32_t *>(l_pBuffer);\n"; - print TGFILE " i_parser.PrintNumber(\"Chip Position:\",\"%X\",ntohl(*l_pBufferTemp));\n"; + print TGFILE " i_parser.PrintNumber(\"Chip Position:\",\"%X\",ntohl(ERRORLOG::UINT32_FROM_PTR(l_pBufferTemp)));\n"; print TGFILE " l_pBufferTemp = NULL;\n"; print TGFILE " l_pBuffer+= POS_LEN;\n"; print TGFILE " l_buflen -= POS_LEN;\n"; diff --git a/src/usr/fapi2/plat_mmio_access.C b/src/usr/fapi2/plat_mmio_access.C index 60526761b..365aa1f22 100644 --- a/src/usr/fapi2/plat_mmio_access.C +++ b/src/usr/fapi2/plat_mmio_access.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -39,9 +39,272 @@ #include <hwpf_fapi2_reasoncodes.H> #include <fapi2/plat_mmio_access.H> - namespace fapi2 { +// Address bit that designates it as an Explorer MMIO address +static const uint64_t EXPLR_IB_MMIO_OFFSET = 0x0000000100000000ull; + +// Valid I2C access to 256MB SRAM space, starts at offset 0x01000000 +static const uint64_t MIN_I2C_SRAM_SPACE_ADDRESS = 0x0000000001000000ull; +static const uint64_t MAX_I2C_SRAM_SPACE_ADDRESS = 0x0000000001030000ull; + +// byte transaction sizes for i2c +static const size_t I2C_TRANSACTION_SIZE = 4; // actual size sent +static const size_t SCOM_I2C_TRANSACTION_SIZE = 8; + +// Convert MMIO to I2C address (need these bits set) +static const uint64_t EXPLR_MMIO_TO_I2C_ADDRESS_MASK = 0xA0000000; + + +/** + * @brief Explorer Inband read via i2c + * @param[in] i_target - OCMB target + * @param[in/out] io_data_read - buffer to be filled with read data + * @param[in/out] io_get_size - size of buffer (returns read size) + * @param[in] i_i2c_addr - i2c scom address + * @return errlHndl_t indicating success or failure + */ +errlHndl_t explrIbI2cRead(TARGETING::Target * i_target, + uint8_t * io_data_read, + size_t io_get_size, + const uint64_t i_i2c_addr) +{ + errlHndl_t l_err = nullptr; + + if ( io_get_size % I2C_TRANSACTION_SIZE ) + { + // invalid size expected (needs to be a multiple of I2C_TRANSACTION_SIZE) + FAPI_ERR("explrIbI2cRead: read size %d is not a multiple of %d", + io_get_size, I2C_TRANSACTION_SIZE); + /*@ + * @errortype + * @moduleid fapi2::MOD_FAPI2_EXPLR_IB_I2C_READ + * @reasoncode fapi2::RC_INVALID_BUFFER_SIZE + * @userdata1[0:31] Buffer size + * @userdata1[32:63] Transaction size + * @userdata2[0:31] HUID of input target + * @userdata2[32:63] i2c_address + * @devdesc Invalid read buffer size, needs to be divisible by transaction size + * @custdesc Internal firmware error + */ + l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE, + fapi2::MOD_FAPI2_EXPLR_IB_I2C_READ, + fapi2::RC_INVALID_BUFFER_SIZE, + TWO_UINT32_TO_UINT64(io_get_size, + I2C_TRANSACTION_SIZE), + TWO_UINT32_TO_UINT64( + TARGETING::get_huid(i_target), + i_i2c_addr), + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + l_err->collectTrace(FAPI_TRACE_NAME); + io_get_size = 0; // no data being read + } + else + { + FAPI_INF("explrIbI2cRead: deviceRead() starting at i2cscom address " + "0x%08X for %d bytes", i_i2c_addr, io_get_size); + + // keep track of total bytes read + size_t total_bytes_read = 0; + + // Increment this address after each read transaction + uint64_t i2cAddr = i_i2c_addr; + + // scom transaction variables + size_t scomTransSize = SCOM_I2C_TRANSACTION_SIZE; + uint8_t scomReadData[SCOM_I2C_TRANSACTION_SIZE]; + + // Only able to read 4 bytes at a time with i2c, so + // need to break into multiple i2c read transactions + while( total_bytes_read < io_get_size ) + { + FAPI_DBG("explrIbI2cRead: deviceRead() at i2cscom address 0x%08X", i2cAddr); + l_err = deviceOp( DeviceFW::READ, + i_target, + scomReadData, + scomTransSize, + DEVICE_I2CSCOM_ADDRESS(i2cAddr) ); + if (l_err) + { + FAPI_ERR("explrIbI2cRead: target 0x%08X deviceRead() at address 0x%08X failed", + TARGETING::get_huid(i_target), i2cAddr); + l_err->collectTrace(FAPI_TRACE_NAME); + break; + } + else + { + FAPI_DBG("explrIbI2cRead: read %02X%02X%02X%02X", + scomReadData[4], scomReadData[5], scomReadData[6], scomReadData[7]); + } + + // The MMIO hardware does this byteswap for us, since we are + // running this over i2c we must reorder the bytes here + io_data_read[total_bytes_read] = scomReadData[7]; + io_data_read[total_bytes_read+1] = scomReadData[6]; + io_data_read[total_bytes_read+2] = scomReadData[5]; + io_data_read[total_bytes_read+3] = scomReadData[4]; + + // Only able to read 4 bytes at a time + total_bytes_read += I2C_TRANSACTION_SIZE; + i2cAddr += I2C_TRANSACTION_SIZE; + + // make sure this value is correct for next op + scomTransSize = SCOM_I2C_TRANSACTION_SIZE; + } + } + return l_err; +} + + +/** + * @brief Explorer Inband write via i2c + * @param[in] i_target - OCMB target + * @param[in] i_write_data - data to write out + * @param[in/out] io_write_size - how much data to write (returns how much written) + * @param[in] i_i2c_addr - i2c scom address + * @return errlHndl_t indicating success or failure + */ +errlHndl_t explrIbI2cWrite(TARGETING::Target * i_target, + const uint8_t * i_write_data, + size_t io_write_size, + const uint64_t i_i2c_addr) +{ + errlHndl_t l_err = nullptr; + + // Verify write can be divide up evenly + if ( io_write_size % I2C_TRANSACTION_SIZE ) + { + // invalid size expected (needs to be a multiple of I2C_TRANSACTION_SIZE) + FAPI_ERR("explrIbI2cWrite: write size %d is not a multiple of %d", + io_write_size, I2C_TRANSACTION_SIZE); + /*@ + * @errortype + * @moduleid fapi2::MOD_FAPI2_EXPLR_IB_I2C_WRITE + * @reasoncode fapi2::RC_INVALID_BUFFER_SIZE + * @userdata1[0:31] Buffer size + * @userdata1[32:63] Transaction size + * @userdata2[0:31] HUID of input target + * @userdata2[32:63] i2c_address + * @devdesc Invalid write buffer size, needs to be divisible by transaction size + * @custdesc Internal firmware error + */ + l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE, + fapi2::MOD_FAPI2_EXPLR_IB_I2C_READ, + fapi2::RC_INVALID_BUFFER_SIZE, + TWO_UINT32_TO_UINT64(io_write_size, + I2C_TRANSACTION_SIZE), + TWO_UINT32_TO_UINT64( + TARGETING::get_huid(i_target), + i_i2c_addr), + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + l_err->collectTrace(FAPI_TRACE_NAME); + } + else + { + // counter for bytes written out to SRAM space + size_t total_bytes_written = 0; + + // going to alter this address to cycle through write data + uint64_t i2cAddr = i_i2c_addr; + + // scom transaction variables + size_t scomTransSize = SCOM_I2C_TRANSACTION_SIZE; + uint8_t scomWriteData[SCOM_I2C_TRANSACTION_SIZE]; + + FAPI_INF("explrIbI2cWrite: deviceWrite() starting at i2cscom address " + "0x%08X for %d bytes", i_i2c_addr, io_write_size); + + // Only able to write 4 bytes at a time with i2c, + // so need to break into multiple i2c write transactions + while( total_bytes_written < io_write_size ) + { + memset(scomWriteData, 0x00, SCOM_I2C_TRANSACTION_SIZE); + + // Only last four bytes are actually written out + // NOTE: MMIO hardware does this byteswap for us, but since we + // are running this over i2c we must reorder the bytes here + scomWriteData[7] = i_write_data[total_bytes_written]; + scomWriteData[6] = i_write_data[total_bytes_written+1]; + scomWriteData[5] = i_write_data[total_bytes_written+2]; + scomWriteData[4] = i_write_data[total_bytes_written+3]; + + l_err = deviceOp( DeviceFW::WRITE, + i_target, + scomWriteData, + scomTransSize, + DEVICE_I2CSCOM_ADDRESS(i2cAddr) ); + if (l_err) + { + FAPI_ERR("explrIbI2cWrite: i2cscom write(0x%02X%02X%02X%02X) at address 0x%08X failed", + scomWriteData[4], scomWriteData[5], scomWriteData[6], scomWriteData[7], i2cAddr); + l_err->collectTrace(FAPI_TRACE_NAME); + break; + } + // Really only doing 4-byte transactions + i2cAddr += I2C_TRANSACTION_SIZE; + total_bytes_written += I2C_TRANSACTION_SIZE; + + // Update for next scom operation + scomTransSize = SCOM_I2C_TRANSACTION_SIZE; + } + } + return l_err; +} + +/** + * @brief Checks if all the conditions are met to allow i2c + * operation instead of MMIO. + * @param[in] i_ocmb - OCMB target + * @param[in] i_mmioAddress - address passed into get/putMMIO + * @return true if i2c should be used instead of MMIO + */ +bool useI2cInsteadOfMmio( const TARGETING::Target * i_ocmb, + const uint64_t i_mmioAddress ) +{ + bool useI2c = false; // default to use MMIO + + uint8_t attrAllowedI2c = 0; + + // Check force i2c attribute first + TARGETING::Target* l_sys = nullptr; + TARGETING::targetService().getTopLevelTarget(l_sys); + crit_assert(l_sys != nullptr); + attrAllowedI2c = l_sys->getAttr<TARGETING::ATTR_FORCE_SRAM_MMIO_OVER_I2C>(); + + // If not forced to use i2c, then check if that is the current scom setting + if (!attrAllowedI2c) + { + // The SCOM_SWITCHES attribute will keep track of when it is safe + // to access the ocmb via inband vs when we should do accesses over + // i2c. Use this attribute to decide which we want to use. + auto ocmb_info = i_ocmb->getAttr<TARGETING::ATTR_SCOM_SWITCHES>(); + if (!ocmb_info.useInbandScom) + { + attrAllowedI2c = 1; + } + } + + // Attribute settings must allow i2c operation before checking + // for a valid address range + if (attrAllowedI2c) + { + // Verify address is within valid SRAM range + if ( ((i_mmioAddress & 0x0F00000000) == EXPLR_IB_MMIO_OFFSET) && + ((i_mmioAddress & 0x0FFFFFFFF) >= MIN_I2C_SRAM_SPACE_ADDRESS) && + ((i_mmioAddress & 0x0FFFFFFFF) <= MAX_I2C_SRAM_SPACE_ADDRESS) ) + { + useI2c = true; + } + else + { + FAPI_INF("0x%08X OCMB address 0x%.8X is outside of SRAM range so using mmio", + TARGETING::get_huid(i_ocmb), i_mmioAddress); + } + } + + return useI2c; +} + //------------------------------------------------------------------------------ // HW Communication Functions to be implemented at the platform layer. //------------------------------------------------------------------------------ @@ -83,12 +346,22 @@ ReturnCode platGetMMIO( const Target<TARGET_TYPE_ALL>& i_target, break; //return with error } - // call MMIO driver - l_err = DeviceFW::deviceRead(l_target, - l_data_read, - l_get_size, - DEVICE_MMIO_ADDRESS(i_mmioAddr, i_transSize)); - + // Run mmio if inband i2c isn't enabled or address is outside of SRAM range + if ( !useI2cInsteadOfMmio(l_target, i_mmioAddr) ) + { + // call MMIO driver + l_err = DeviceFW::deviceRead(l_target, + l_data_read, + l_get_size, + DEVICE_MMIO_ADDRESS(i_mmioAddr, i_transSize)); + } + else + { + // Use i2c instead of MMMIO + // Explorer i2c addresses are actually 32-bit and need 0xA at the beginning + uint64_t i2cAddr = (i_mmioAddr & 0x00000000FFFFFFFF) | EXPLR_MMIO_TO_I2C_ADDRESS_MASK; + l_err = explrIbI2cRead(l_target, l_data_read, l_get_size, i2cAddr); + } if (l_traceit) { // Only trace the first 8 bytes of data read @@ -167,11 +440,22 @@ ReturnCode platPutMMIO( const Target<TARGET_TYPE_ALL>& i_target, std::copy(i_data.begin(), i_data.end(), l_writeDataPtr); size_t l_dataSize = i_data.size(); - // call MMIO driver - l_err = DeviceFW::deviceWrite(l_target, - l_writeDataPtr, - l_dataSize, - DEVICE_MMIO_ADDRESS(i_mmioAddr, i_transSize)); + // Run mmio if inband i2c isn't enabled or address is outside of SRAM range + if ( !useI2cInsteadOfMmio(l_target, i_mmioAddr) ) + { + // call MMIO driver + l_err = DeviceFW::deviceWrite(l_target, + l_writeDataPtr, + l_dataSize, + DEVICE_MMIO_ADDRESS(i_mmioAddr, i_transSize)); + } + else + { + // Address is an Explorer SRAM address, so I2C will work + // Explorer i2c addresses are actually 32-bit and need 0xA at the beginning + uint64_t i2cAddr = (i_mmioAddr & 0x00000000FFFFFFFF) | EXPLR_MMIO_TO_I2C_ADDRESS_MASK; + l_err = explrIbI2cWrite(l_target, l_writeDataPtr, l_dataSize, i2cAddr); + } if (l_traceit) { // trace the first 8 bytes of written data diff --git a/src/usr/fapi2/plat_spd_access.C b/src/usr/fapi2/plat_spd_access.C index c8466f5da..6f3107f0c 100644 --- a/src/usr/fapi2/plat_spd_access.C +++ b/src/usr/fapi2/plat_spd_access.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -34,6 +34,8 @@ #include <errl/errlentry.H> #include <errl/errlmanager.H> #include <fapi2_spd_access.H> +#include <vpd/spdenums.H> +#include <hwas/common/hwasCallout.H> namespace fapi2 { @@ -49,14 +51,9 @@ fapi2::ReturnCode getSPD( { FAPI_DBG(ENTER_MRK "getSPD"); - const uint8_t MEM_DDR3 = 0xB; - const uint8_t MEM_DDR4 = 0xC; - const uint32_t DDR3_KEYWORD_SIZE = 256; - const uint32_t DDR4_KEYWORD_SIZE = 512; - - errlHndl_t l_errl = NULL; + errlHndl_t l_errl = nullptr; fapi2::ReturnCode l_rc; - TARGETING::Target* l_pTarget = NULL; + TARGETING::Target* l_pTarget = nullptr; do { @@ -65,49 +62,104 @@ fapi2::ReturnCode getSPD( TARGETING::TYPE_DIMM); if (l_errl) { - FAPI_ERR("getSPD: Error from getTargetingTarget"); + FAPI_ERR("getSPD: Error from getTargetingTarget for TYPE_DIMM"); break; } // If the caller passed a nullptr for blob then // return size of the SPD - if ( o_blob == NULL ) + if ( o_blob == nullptr ) { - // Get the DDR device type from SPD - uint8_t l_memType = 0x0; - size_t l_memSize = sizeof(l_memType); + // Get the DRAM generation from SPD + uint8_t l_memGen = 0x0; + size_t l_memSize = sizeof(l_memGen); l_errl = deviceRead(l_pTarget, - (void *)&l_memType, - l_memSize, - DEVICE_SPD_ADDRESS(SPD::BASIC_MEMORY_TYPE)); + static_cast<void *>(&l_memGen), + l_memSize, + DEVICE_SPD_ADDRESS(SPD::BASIC_MEMORY_TYPE)); + + if ( l_errl ) + { + FAPI_ERR("getSPD: Error from deviceRead for BASIC_MEMORY_TYPE") + break; + } - if ( !l_errl ) + switch(l_memGen) { - if ( l_memType == MEM_DDR3 ) + case SPD::MEM_DDR3: + o_size = SPD::DDR3_SPD_SIZE; + break; + + case SPD::MEM_DDR4: { - o_size = DDR3_KEYWORD_SIZE; - } - else if ( l_memType == MEM_DDR4 ) + uint8_t l_memModule = 0x0; + + l_errl = deviceRead(l_pTarget, + static_cast<void *>(&l_memModule), + l_memSize, + DEVICE_SPD_ADDRESS(SPD::MODULE_TYPE)); + + if( l_errl ) + { + FAPI_ERR("getSPD: Error on deviceRead for MODULE_TYPE"); + break; + } + + if( l_memModule == SPD::MEM_DDIMM ) + { + // currently getSPD only supports the ENTIRE_SPD + // keyword. In the DDIMM case this include the EFD + // data so be sure to reflect that in the size we return. + o_size = SPD::OCMB_SPD_EFD_COMBINED_SIZE; + } + else + { + o_size = SPD::DDR4_SPD_SIZE; + } + }// case MEM_DDR4 + break; + + default: { - o_size = DDR4_KEYWORD_SIZE; - } - else - { - FAPI_ERR("getSPD: Invalid DIMM DDR Type"); - break; + FAPI_ERR("getSPD: Unsupported DIMM DDR Generation"); + + /*@ + * @errortype + * @moduleid MOD_FAPI2_SPD_ACCESS + * @reasoncode RC_INVALID_SPD_DRAM_GEN + * @userdata1 DDR generation + * @userdata2 HUID of input target + * @devdesc Bad SPD or unsupported DIMM + * @custdesc Unsupported DIMM generation + */ + l_errl = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + MOD_FAPI2_SPD_ACCESS, + RC_INVALID_SPD_DRAM_GEN, + TARGETING::get_huid(l_pTarget), + l_memGen ); + + l_errl->addHwCallout( l_pTarget, + HWAS::SRCI_PRIORITY_HIGH, + HWAS::DELAYED_DECONFIG, + HWAS::GARD_NULL ); } + break; - FAPI_DBG("getSPD: Returning the size of the SPD :%d ", o_size); - } - } + }// switch + + FAPI_DBG("getSPD: Returning the size of the SPD :%d ", o_size); + + }// endif else { + // Return the entire SPD blob l_errl = deviceRead(l_pTarget, - o_blob, - o_size, - DEVICE_SPD_ADDRESS(SPD::ENTIRE_SPD)); - } + o_blob, + o_size, + DEVICE_SPD_ADDRESS(SPD::ENTIRE_SPD)); + }// end else break; @@ -118,7 +170,7 @@ fapi2::ReturnCode getSPD( FAPI_ERR("getSPD: Error getting SPD data for HUID=0x%.8X Size %d", TARGETING::get_huid(l_pTarget),o_size); - l_rc.setPlatDataPtr(reinterpret_cast<void *> (l_errl)); + l_rc.setPlatDataPtr(reinterpret_cast<void *>(l_errl)); } FAPI_DBG("getSPD: SPD data for HUID=0x%.8X Size %d Blob %d", diff --git a/src/usr/fapi2/plat_utils.C b/src/usr/fapi2/plat_utils.C index 01eacb645..bcea30664 100644 --- a/src/usr/fapi2/plat_utils.C +++ b/src/usr/fapi2/plat_utils.C @@ -48,6 +48,7 @@ #include <p9_scan_compression.H> #include <cen_ringId.H> #include <scom/wakeup.H> +#include <util/misc.H> //****************************************************************************** // Trace descriptors @@ -941,6 +942,13 @@ void processEIBusCallouts(const ErrorInfo & i_errInfo, { l_busType = HWAS::DMI_BUS_TYPE; } + else if ( ((l_type1 == TARGETING::TYPE_DMI) && + (l_type2 == TARGETING::TYPE_MEMBUF)) || + ((l_type1 == TARGETING::TYPE_MEMBUF) && + (l_type2 == TARGETING::TYPE_DMI)) ) + { + l_busType = HWAS::DMI_BUS_TYPE; + } else if ((l_type1 == TARGETING::TYPE_ABUS) && (l_type2 == TARGETING::TYPE_ABUS)) { @@ -956,6 +964,13 @@ void processEIBusCallouts(const ErrorInfo & i_errInfo, { l_busType = HWAS::O_BUS_TYPE; } + else if ( ((l_type1 == TARGETING::TYPE_OMI) && + (l_type2 == TARGETING::TYPE_OCMB_CHIP)) || + ((l_type1 == TARGETING::TYPE_OCMB_CHIP) && + (l_type2 == TARGETING::TYPE_OMI)) ) + { + l_busType = HWAS::OMI_BUS_TYPE; + } else { FAPI_ERR("processEIBusCallouts: Bus between target types not known (0x%08x:0x%08x)", @@ -1468,7 +1483,12 @@ ReturnCode delay(uint64_t i_nanoSeconds, bool i_fixed) { //Note: i_fixed is deliberately ignored - nanosleep( 0, i_nanoSeconds ); + + // We don't need to waste time for hardware delays if we're running in Simics + if( !Util::isSimicsRunning() ) + { + nanosleep( 0, i_nanoSeconds ); + } return FAPI2_RC_SUCCESS; } diff --git a/src/usr/fapi2/rowRepairsFuncs.C b/src/usr/fapi2/rowRepairsFuncs.C index 6548e31ed..67796ad20 100644 --- a/src/usr/fapi2/rowRepairsFuncs.C +++ b/src/usr/fapi2/rowRepairsFuncs.C @@ -34,8 +34,8 @@ extern "C" { fapi2::ReturnCode __getDimmRepairData( const fapi2::Target - <fapi2::TARGET_TYPE_MCA|fapi2::TARGET_TYPE_MBA|fapi2::TARGET_TYPE_MEM_PORT> - & i_fapiTrgt, + <fapi2::TARGET_TYPE_MCA|fapi2::TARGET_TYPE_MBA| + fapi2::TARGET_TYPE_MEM_PORT|fapi2::TARGET_TYPE_OCMB_CHIP> & i_fapiTrgt, const uint8_t i_dimm, const uint8_t i_rank, TARGETING::TargetHandle_t & o_dimmTrgt, @@ -109,8 +109,8 @@ fapi2::ReturnCode __getDimmRepairData( const fapi2::Target //------------------------------------------------------------------------------ fapi2::ReturnCode getRowRepair( const fapi2::Target - <fapi2::TARGET_TYPE_MCA|fapi2::TARGET_TYPE_MBA|fapi2::TARGET_TYPE_MEM_PORT> - & i_fapiTrgt, + <fapi2::TARGET_TYPE_MCA|fapi2::TARGET_TYPE_MBA| + fapi2::TARGET_TYPE_MEM_PORT|fapi2::TARGET_TYPE_OCMB_CHIP> & i_fapiTrgt, const uint8_t i_dimm, const uint8_t i_rank, uint8_t (&o_data)[mss::ROW_REPAIR_BYTE_COUNT], @@ -147,8 +147,8 @@ fapi2::ReturnCode getRowRepair( const fapi2::Target //------------------------------------------------------------------------------ fapi2::ReturnCode setRowRepair( const fapi2::Target - <fapi2::TARGET_TYPE_MCA|fapi2::TARGET_TYPE_MBA|fapi2::TARGET_TYPE_MEM_PORT> - & i_fapiTrgt, + <fapi2::TARGET_TYPE_MCA|fapi2::TARGET_TYPE_MBA| + fapi2::TARGET_TYPE_MEM_PORT|fapi2::TARGET_TYPE_OCMB_CHIP> & i_fapiTrgt, const uint8_t i_dimm, const uint8_t i_rank, uint8_t (&i_data)[mss::ROW_REPAIR_BYTE_COUNT], diff --git a/src/usr/fapi2/test/fapi2DdimmGetEfdTest.C b/src/usr/fapi2/test/fapi2DdimmGetEfdTest.C index 13f0ed87b..400ca2a59 100644 --- a/src/usr/fapi2/test/fapi2DdimmGetEfdTest.C +++ b/src/usr/fapi2/test/fapi2DdimmGetEfdTest.C @@ -111,7 +111,8 @@ fapi2DdimmGetEfdTest::fapi2DdimmGetEfdTest() { FAPI_INF(">> fapi2DdimmGetEfdTest"); - if(TARGETING::MODEL_AXONE != TARGETING::targetService().getProcessorModel()) + iv_attrModel = TARGETING::targetService().getProcessorModel(); + if(TARGETING::MODEL_AXONE != iv_attrModel) { FAPI_INF("<< fapi2DdimmGetEfdTest: This is not AXONE. " "Skipping AXONE tests."); diff --git a/src/usr/fapi2/test/fapi2GetChildrenTest.H b/src/usr/fapi2/test/fapi2GetChildrenTest.H index 3971c1270..961579e1f 100644 --- a/src/usr/fapi2/test/fapi2GetChildrenTest.H +++ b/src/usr/fapi2/test/fapi2GetChildrenTest.H @@ -32,7 +32,6 @@ #include <functional> #include <plat_utils.H> #include <error_scope.H> -#include <config.h> namespace fapi2 { @@ -66,7 +65,6 @@ void test_fapi2GetChildren() uint32_t l_targetHuid = 0xFFFFFFFF; uint32_t l_actualSize = 0; uint32_t l_expectedSize = 0; - errlHndl_t l_err = nullptr; int numTests = 0; int numFails = 0; @@ -225,7 +223,7 @@ void test_fapi2GetChildren() numTests++; if(l_actualSize != l_expectedSize) { - TS_FAIL("test_fapi2GetChildren:: OMIs per proc mismatch"); + TS_FAIL("test_fapi2GetChildren:: OMIs per proc mismatch. Actual size: %d, Expected size: %d", l_actualSize, l_expectedSize); numFails++; break; } @@ -611,17 +609,25 @@ void test_fapi2GetChildren() TARGET_STATE_PRESENT).size(); } }, // CAPP pervasive has 1 CAPP child - {PERV_CAPP_CUMULUS_CHILDREN, + {PERV_CAPP_AXONE_CHILDREN, [](TARGETING::ATTR_CHIP_UNIT_type i_unit) { return ((i_unit == CAPP0_RANGE) || (i_unit == CAPP1_RANGE));}, [](Target<fapi2::TARGET_TYPE_PERV>& i_perv) { return i_perv.getChildren<fapi2::TARGET_TYPE_CAPP>( TARGET_STATE_PRESENT).size(); } }, - // OBUS pervasive has 3 OBUS BRICK children - {PERV_OBUS_BRICK_CHILDREN, + // OBUS0,3 pervasive has 2 OBUS BRICK children + {PERV_OBUS_BRICK03_AXONE_CHILDREN, [](TARGETING::ATTR_CHIP_UNIT_type i_unit) - { return ((i_unit >= OBUS_LOW) && (i_unit <= OBUS_HIGH)); }, + { return ((i_unit == OBUS_LOW+0) || (i_unit == OBUS_LOW+3)); }, + [](Target<fapi2::TARGET_TYPE_PERV>& i_perv) + { return i_perv.getChildren<fapi2::TARGET_TYPE_OBUS_BRICK>( + TARGET_STATE_PRESENT).size(); } }, + + // OBUS1,2 pervasive has 1 OBUS BRICK child + {PERV_OBUS_BRICK12_AXONE_CHILDREN, + [](TARGETING::ATTR_CHIP_UNIT_type i_unit) + { return ((i_unit == OBUS_LOW+1) || (i_unit == OBUS_LOW+2)); }, [](Target<fapi2::TARGET_TYPE_PERV>& i_perv) { return i_perv.getChildren<fapi2::TARGET_TYPE_OBUS_BRICK>( TARGET_STATE_PRESENT).size(); } }, @@ -699,7 +705,7 @@ void test_fapi2GetChildren() TARGET_STATE_PRESENT).size(); } }, }; - pervasiveChildTestRec* ptr; + pervasiveChildTestRec* ptr = nullptr; int numPervTests = 0; TARGETING::ATTR_MODEL_type l_model = l_proc->getAttr<TARGETING::ATTR_MODEL>(); if (l_model == TARGETING::MODEL_NIMBUS) @@ -750,9 +756,9 @@ void test_fapi2GetChildren() if(candidateTarget == nullptr) { - TS_FAIL("test_fapi2GetChildren:: candidateTarget not found"); + TS_FAIL("test_fapi2GetChildren:: candidateTarget not found - test %d", i); numFails++; - break; + continue; } l_targetHuid = TARGETING::get_huid(candidateTarget); @@ -764,9 +770,9 @@ void test_fapi2GetChildren() if(l_actualSize != l_expectedSize) { - TS_FAIL("test_fapi2GetChildren:: children of pervasive mismatch"); + TS_FAIL("test_fapi2GetChildren:: children of pervasive mismatch for %.8X (exp=%d,act=%d)", + l_targetHuid,l_expectedSize,l_actualSize); numFails++; - break; } } @@ -780,31 +786,6 @@ void test_fapi2GetChildren() }while(0); - if(l_actualSize != l_expectedSize) - { - /*@ - * @errortype ERRORLOG::ERRL_SEV_UNRECOVERABLE - * @moduleid fapi2::MOD_FAPI2_PLAT_GET_CHILDREN_TEST - * @reasoncode fapi2::RC_INVALID_CHILD_COUNT - * @userdata1[0:31] Expected Child Count - * @userdata1[32:63] Actual Child Count - * @userdata2 Parent HUID - * @devdesc Invalid amount of child cores found - * on a proc - */ - l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE, - fapi2::MOD_FAPI2_PLAT_GET_CHILDREN_TEST, - fapi2::RC_INVALID_CHILD_COUNT, - TWO_UINT32_TO_UINT64( - TO_UINT32( - l_expectedSize), - TO_UINT32( - l_actualSize)), - l_targetHuid, - true/*SW Error*/); - errlCommit(l_err,HWPF_COMP_ID); - TS_FAIL("test_fapi2GetChildren Fail, for HUID: %d , expected %d children , found %d ", l_targetHuid,l_expectedSize,l_actualSize ); - } FAPI_INF("fapi2GetChildrenTest:: Test Complete. %d/%d fails", numFails , numTests); } @@ -818,7 +799,6 @@ void test_fapi2GetChildrenFilter() uint32_t l_targetHuid = 0xFFFFFFFF; uint32_t l_actualSize = 0; uint32_t l_expectedSize = 0; - errlHndl_t l_err = nullptr; TARGETING::Target * l_proc = nullptr; TARGETING::TargetHandleList l_chipList; do @@ -835,7 +815,7 @@ void test_fapi2GetChildrenFilter() } else { - TS_FAIL("test_fapi2GetChildren Fail: could not find any proc, skipping tests"); + TS_FAIL("test_fapi2GetChildrenFilter Fail: could not find any proc, skipping tests"); numFails++; break; } @@ -876,7 +856,7 @@ void test_fapi2GetChildrenFilter() if(l_actualSize != l_expectedSize) { numFails++; - break; + TS_FAIL("test_fapi2GetChildrenFilter Fail on PERV/ALL_CORES, for HUID: 0x%.8X , expected %d children , found %d ", l_targetHuid,l_expectedSize,l_actualSize ); } // PERV - TARGET_FILTER_CORE1 @@ -890,7 +870,7 @@ void test_fapi2GetChildrenFilter() if(l_actualSize != l_expectedSize) { numFails++; - break; + TS_FAIL("test_fapi2GetChildrenFilter Fail on PERV/CORE1, for HUID: 0x%.8X , expected %d children , found %d ", l_targetHuid,l_expectedSize,l_actualSize ); } if (isHwValid(l_proc, MY_MC)) @@ -906,13 +886,26 @@ void test_fapi2GetChildrenFilter() if(l_actualSize != l_expectedSize) { numFails++; - break; + TS_FAIL("test_fapi2GetChildrenFilter Fail on PERV/ALL_MC, for HUID: 0x%.8X , expected %d children , found %d ", l_targetHuid,l_expectedSize,l_actualSize ); } } // PERV - SYNC_MODE_ALL_IO_EXCEPT_NEST - // NOTE: 2 of 4 OBUS are Cumulus only, so expect 8 instead of 10 returned - l_expectedSize = 8; + l_expectedSize = 0; + TARGETING::ATTR_MODEL_type l_model = l_proc->getAttr<TARGETING::ATTR_MODEL>(); + if (l_model == TARGETING::MODEL_NIMBUS) + { + // NOTE: 2 of 4 OBUS are Cumulus only, so expect 8 instead of 10 returned + l_expectedSize = 8; + } + else if (l_model == TARGETING::MODEL_CUMULUS) + { + l_expectedSize = 10; + } + else if (l_model == TARGETING::MODEL_AXONE) + { + l_expectedSize = 10; + } l_childPERVs = fapi2_procTarget.getChildren<fapi2::TARGET_TYPE_PERV>( TARGET_FILTER_SYNC_MODE_ALL_IO_EXCEPT_NEST, TARGET_STATE_PRESENT); @@ -922,37 +915,11 @@ void test_fapi2GetChildrenFilter() if(l_actualSize != l_expectedSize) { numFails++; - break; + TS_FAIL("test_fapi2GetChildrenFilter Fail on PERV/ALL_IO_EXCEPT_NEST, for HUID: 0x%.8X , expected %d children , found %d ", l_targetHuid,l_expectedSize,l_actualSize ); } }while(0); - if(l_actualSize != l_expectedSize) - { - /*@ - * @errortype ERRORLOG::ERRL_SEV_UNRECOVERABLE - * @moduleid fapi2::MOD_FAPI2_PLAT_GET_CHILDREN_FILTER_TEST - * @reasoncode fapi2::RC_INVALID_CHILD_COUNT - * @userdata1[0:31] Expected Child Count - * @userdata1[32:63] Actual Child Count - * @userdata2 Parent HUID - * @devdesc Invalid amount of child cores found - * on a proc - */ - l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE, - fapi2::MOD_FAPI2_PLAT_GET_CHILDREN_FILTER_TEST, - fapi2::RC_INVALID_CHILD_COUNT, - TWO_UINT32_TO_UINT64( - TO_UINT32( - l_expectedSize), - TO_UINT32( - l_actualSize)), - l_targetHuid, - true/*SW Error*/); - errlCommit(l_err,HWPF_COMP_ID); - TS_FAIL("test_fapi2GetChildrenFilter Fail, for HUID: 0x%X , expected %d children , found %d ", l_targetHuid,l_expectedSize,l_actualSize ); - } - FAPI_INF("test_fapi2GetChildrenFilter: Test Complete. %d/%d fails", numFails , numTests); } @@ -966,10 +933,12 @@ void test_fapi2getChildTargetsForCDG() int numFails = 0; TARGETING::Target * l_proc = nullptr; size_t l_expectedDimms = 0; + TARGETING::TargetHandleList l_chipList; +// These port and socket arguments are not valid for Axone targets +#ifndef CONFIG_AXONE size_t l_expectedDimmsUnderPort0 = 0; size_t l_expectedDimmsUnderPort1 = 0; - TARGETING::TargetHandleList l_chipList; - +#endif do { FAPI_DBG("start of test_fapi2getChildTargetsForCDG()"); @@ -992,20 +961,24 @@ void test_fapi2getChildTargetsForCDG() if (l_proc->getAttr<TARGETING::ATTR_MODEL>() == TARGETING::MODEL_NIMBUS) { l_expectedDimms = 16; +// These port and socket arguments are not valid for Axone targets +#ifndef CONFIG_AXONE l_expectedDimmsUnderPort0 = l_expectedDimms; l_expectedDimmsUnderPort1 = 0; +#endif } else if (l_proc->getAttr<TARGETING::ATTR_MODEL>() == TARGETING::MODEL_CUMULUS) { l_expectedDimms = 8; +// These port and socket arguments are not valid for Axone targets +#ifndef CONFIG_AXONE l_expectedDimmsUnderPort0 = l_expectedDimms/2; l_expectedDimmsUnderPort1 = l_expectedDimms/2; +#endif } else if (l_proc->getAttr<TARGETING::ATTR_MODEL>() == TARGETING::MODEL_AXONE) { l_expectedDimms = 9; - l_expectedDimmsUnderPort0 = 0xFF; //wrong - l_expectedDimmsUnderPort1 = 0xFF; //wrong } else //both are nullptr { @@ -1035,6 +1008,9 @@ void test_fapi2getChildTargetsForCDG() numFails++; } +// These port and socket arguments are not valid for Axone targets +// so skip testing them +#ifndef CONFIG_AXONE // All dimms under port 0 fapi2::getChildTargetsForCDG(fapi2_procTarget, fapi2::TARGET_TYPE_DIMM, @@ -1047,11 +1023,9 @@ void test_fapi2getChildTargetsForCDG() if(l_dimmList.size() != l_expectedDimmsUnderPort0) { -#ifndef CONFIG_AXONE_BRING_UP TS_FAIL("test_fapi2getChildTargetsForCDG: Dimm count %d under port 0 not equal expected %d", l_dimmList.size(),l_expectedDimmsUnderPort0); numFails++; -#endif } // All dimms under port 1 @@ -1066,11 +1040,9 @@ void test_fapi2getChildTargetsForCDG() if(l_dimmList.size() != l_expectedDimmsUnderPort1) { -#ifndef CONFIG_AXONE_BRING_UP TS_FAIL("test_fapi2getChildTargetsForCDG: Dimm count %d under port 1 not equal expected %d", l_dimmList.size(),l_expectedDimmsUnderPort1); numFails++; -#endif } // All dimms under socket 0 @@ -1084,11 +1056,9 @@ void test_fapi2getChildTargetsForCDG() numTests++; if(l_dimmList.size() != l_expectedDimms) { -#ifndef CONFIG_AXONE_BRING_UP - TS_FAIL("test_fapi2getChildTargetsForCDG: Dimm count %d under socket 0 not equal expected %d", + TS_FAIL("test_fapi2getChildTargetsForCDG: Dimm count %d under socket 0x0, all ports, not equal expected %d", l_dimmList.size(),l_expectedDimms); numFails++; -#endif } // All dimms under socket 1 @@ -1106,6 +1076,7 @@ void test_fapi2getChildTargetsForCDG() l_dimmList.size(),0); numFails++; } +#endif }while(0); diff --git a/src/usr/fapi2/test/fapi2GetVpdTest.H b/src/usr/fapi2/test/fapi2GetVpdTest.H index 8a8dc0849..8f86430a0 100644 --- a/src/usr/fapi2/test/fapi2GetVpdTest.H +++ b/src/usr/fapi2/test/fapi2GetVpdTest.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -46,7 +46,7 @@ public: void testGetVPD(void) { -#ifdef CONFIG_SECUREBOOT +#if (defined CONFIG_SECUREBOOT && ! defined CONFIG_AXONE) errlHndl_t pError=NULL; do { @@ -71,7 +71,7 @@ void testGetVPD(void) testGetVPD_DQ(); testGetVPD_CK(); -#ifdef CONFIG_SECUREBOOT +#if (defined CONFIG_SECUREBOOT && ! defined CONFIG_AXONE) pError = PNOR::unloadSecureSection(PNOR::MEMD); if(pError) { diff --git a/src/usr/fapi2/test/fapi2MmioAccessTest.H b/src/usr/fapi2/test/fapi2MmioAccessTest.H index 3ba0f31c0..fffec22e8 100644 --- a/src/usr/fapi2/test/fapi2MmioAccessTest.H +++ b/src/usr/fapi2/test/fapi2MmioAccessTest.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -38,7 +38,7 @@ #include <fapi2TestUtils.H> #include <p9_mmiotests.H> #include <plat_hwp_invoker.H> -#include <config.h> +#include <test/exptest_utils.H> using namespace fapi2; @@ -110,10 +110,22 @@ void test_fapi2MmioInvalidSizes() // Get a list of all of the OCMB chips TARGETING::getAllChips(l_ocmbTargetList, TARGETING::TYPE_OCMB_CHIP, true); + if (!iv_serializeTestMutex) + { + TS_FAIL("test_fapi2MmioInvalidSizes(): unable to get test mutex"); + return; + } + mutex_lock(iv_serializeTestMutex); + for (auto & l_ocmb: l_ocmbTargetList) { Target<fapi2::TARGET_TYPE_OCMB_CHIP> fapi2_ocmbTarget( l_ocmb ); - + auto first_ocmb_info = l_ocmb->getAttr<TARGETING::ATTR_SCOM_SWITCHES>(); + if (!first_ocmb_info.useInbandScom) + { + TS_FAIL("test_fapi2MmioInvalidSizes() - scom access is not using inband"); + continue; + } numTests++; FAPI_INVOKE_HWP(l_errl, p9_mmiotest_indivisible_by_section_size, fapi2_ocmbTarget); if(l_errl != nullptr) @@ -126,6 +138,12 @@ void test_fapi2MmioInvalidSizes() TS_FAIL("No error from p9_mmiotest_indivisible_by_section_size !!"); numFails++; } + auto second_ocmb_info = l_ocmb->getAttr<TARGETING::ATTR_SCOM_SWITCHES>(); + if (!second_ocmb_info.useInbandScom) + { + TS_FAIL("p9_mmiotest_indivisible_by_section_size turned off mmio operations"); + l_ocmb->setAttr<TARGETING::ATTR_SCOM_SWITCHES>(first_ocmb_info); + } numTests++; FAPI_INVOKE_HWP(l_errl, p9_mmiotest_invalid_section_size, fapi2_ocmbTarget); @@ -139,7 +157,14 @@ void test_fapi2MmioInvalidSizes() TS_FAIL("No error from p9_mmiotest_invalid_section_size !!"); numFails++; } + auto third_ocmb_info = l_ocmb->getAttr<TARGETING::ATTR_SCOM_SWITCHES>(); + if (!third_ocmb_info.useInbandScom) + { + TS_FAIL("p9_mmiotest_invalid_section_size turned off mmio operations"); + l_ocmb->setAttr<TARGETING::ATTR_SCOM_SWITCHES>(first_ocmb_info); + } } + mutex_unlock(iv_serializeTestMutex); FAPI_INF("test_fapi2MmioInvalidSizes Test Complete. %d/%d fails", numFails, numTests); } @@ -152,7 +177,6 @@ void test_fapi2MmioAccess() int numTests = 0; int numFails = 0; -#ifndef CONFIG_AXONE_BRING_UP errlHndl_t l_errl = nullptr; // Create a vector of TARGETING::Target pointers @@ -161,6 +185,12 @@ void test_fapi2MmioAccess() // Get a list of all of the OCMB chips TARGETING::getAllChips(l_chipList, TARGETING::TYPE_OCMB_CHIP, true); + if (!iv_serializeTestMutex) + { + TS_FAIL("test_fapi2MmioAccess(): unable to get test mutex"); + return; + } + mutex_lock(iv_serializeTestMutex); for (auto & l_ocmb: l_chipList) { Target<fapi2::TARGET_TYPE_OCMB_CHIP> l_fapi2_target( l_ocmb ); @@ -213,11 +243,41 @@ void test_fapi2MmioAccess() l_errl = nullptr; } } -#endif + mutex_unlock(iv_serializeTestMutex); FAPI_INF("fapi2MmioAccessTest Test Complete. %d/%d fails", numFails, numTests); } +/** + * @brief Constructor + */ +Fapi2MmioAccessTest() : CxxTest::TestSuite() +{ + // All modules are loaded by runtime, + // so testcase loading of modules is not required +#ifndef __HOSTBOOT_RUNTIME + errlHndl_t err = nullptr; + err = exptest::loadModule(exptest::MSS_LIBRARY_NAME); + if(err) + { + TS_FAIL("Fapi2MmioAccessTest() - Constuctor: failed to load MSS module"); + errlCommit( err, TARG_COMP_ID ); + } +#endif + iv_serializeTestMutex = exptest::getTestMutex(); +}; + +/** + * @brief Deconstructor + */ +~Fapi2MmioAccessTest() +{ +} + + +private: + // This is used for tests that need to not run operations at the same time + TARGETING::HB_MUTEX_SERIALIZE_TEST_LOCK_ATTR iv_serializeTestMutex; }; diff --git a/src/usr/fapi2/test/fapi2MvpdTestCxx.H b/src/usr/fapi2/test/fapi2MvpdTestCxx.H index 224879070..92d791908 100644 --- a/src/usr/fapi2/test/fapi2MvpdTestCxx.H +++ b/src/usr/fapi2/test/fapi2MvpdTestCxx.H @@ -326,7 +326,8 @@ public: #ifdef CONFIG_EARLY_TESTCASES // Requires some prereqs of step7 - FAPI_INF("Skipping poundv tests"); + FAPI_INF("Skipping poundv tests due to CONFIG_EARLY_TESTCASES"); + #else fapi2::ReturnCode l_rc; @@ -421,7 +422,8 @@ public: #ifdef CONFIG_EARLY_TESTCASES // Requires some prereqs of step7 - FAPI_INF("Skipping poundv tests"); + FAPI_INF("Skipping poundw tests due to CONFIG_EARLY_TESTCASES"); + #else fapi2::ReturnCode l_rc; diff --git a/src/usr/fapi2/test/fapi2SpdTestCxx.H b/src/usr/fapi2/test/fapi2SpdTestCxx.H index 2ccd457dc..d033401e8 100644 --- a/src/usr/fapi2/test/fapi2SpdTestCxx.H +++ b/src/usr/fapi2/test/fapi2SpdTestCxx.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -37,6 +37,7 @@ #include <errl/errlentry.H> #include <devicefw/driverif.H> #include <fapi2_spd_access.H> +#include <vpd/spdenums.H> using namespace TARGETING; @@ -52,76 +53,127 @@ class SPDTest: public CxxTest::TestSuite { public: - /** - * @brief Test SPD get Interface DIMMs. - */ - void testGetSPD ( void ) - { - fapi2::ReturnCode l_rc; - size_t l_size = 0; - uint8_t * l_blobData = NULL; - - FAPI_INF( "testGetSPD - Enter" ); - - do - { - TARGETING::Target * i_pTarget = NULL; - - // Get DIMM Targets - TargetHandleList dimmList; - getDIMMTargets( dimmList ); - - // Should get atleast one - if( ( 0 == dimmList.size() ) || - ( NULL == dimmList[0] ) ) - { - FAPI_INF( "testGetSPD- No DIMMs found!"); - break; - } - - // Work on the first DIMM target - i_pTarget = dimmList[0]; - - // convert to fapi2 target - fapi2::Target<fapi2::TARGET_TYPE_DIMM> fapi2_Target(i_pTarget); - - // SPD interface call with NULL blob to get size data - l_rc = fapi2::getSPD(fapi2_Target, NULL, l_size); - - // Expect to return the size or non failure - if( !l_size || (l_rc != fapi2::FAPI2_RC_SUCCESS) ) - { - TS_FAIL("testGetSPD: Failed getting the size of the mem buffer"); - break; - } - - // allocate the blob data of mem size length to hold data - l_blobData = reinterpret_cast<uint8_t *>(malloc(l_size)); - memset(l_blobData,0,l_size); - - l_rc = fapi2::getSPD(fapi2_Target,l_blobData, l_size); - if ( l_rc != fapi2::FAPI2_RC_SUCCESS ) - { - TS_FAIL( "testGetSPD- Failed to read data from DIMM with HUID= 0x%x", - TARGETING::get_huid(i_pTarget)); - break; - } - - FAPI_DBG("getSPD: SPD data for DIMM with HUID=0x%.8X Size %d Blob %d", - TARGETING::get_huid(i_pTarget), - l_size, - l_blobData); - - } while(0); - - if( NULL != l_blobData ) - { - free( l_blobData ); - l_blobData = NULL; - } - - FAPI_INF( "testGetSPD - Exit" ); - } + /** + * @brief Test SPD get Interface DIMMs. + */ + void testGetSPD ( void ) + { + fapi2::ReturnCode l_rc; + size_t l_spdSize = 0; + uint8_t * l_blobData = NULL; + + FAPI_INF( "testGetSPD - Enter" ); + + // Get DIMM Targets + TargetHandleList dimmList; + getDIMMTargets( dimmList ); + + // Should get atleast one + if( ( 0 == dimmList.size() ) || + ( NULL == dimmList[0] ) ) + { + TS_FAIL( "testGetSPD- No DIMMs found!"); + } + + for( auto l_tDimm : dimmList ) + { + + // convert to fapi2 target + fapi2::Target<fapi2::TARGET_TYPE_DIMM> l_fDimm(l_tDimm); + + // SPD interface call with NULL blob to get size data + l_rc = fapi2::getSPD(l_fDimm, NULL, l_spdSize); + + // Expect to return the size or non failure + if( !l_spdSize || (l_rc != fapi2::FAPI2_RC_SUCCESS) ) + { + TS_FAIL("testGetSPD: Failed getting the size of the mem buffer - Dimm %.8X", TARGETING::get_huid(l_tDimm)); + continue; + } + + // allocate the blob data of mem size length to hold data + l_blobData = reinterpret_cast<uint8_t *>(malloc(l_spdSize)); + memset(l_blobData,0,l_spdSize); + + l_rc = fapi2::getSPD(l_fDimm,l_blobData, l_spdSize); + if ( l_rc != fapi2::FAPI2_RC_SUCCESS ) + { + TS_FAIL( "testGetSPD- Failed to read data from DIMM with HUID= 0x%x", + TARGETING::get_huid(l_tDimm)); + continue; + } + + uint8_t l_memModule = 0x0; + size_t l_memSize = sizeof(uint8_t); + + auto l_errl = deviceRead(l_tDimm, + (void *)&l_memModule, + l_memSize, + DEVICE_SPD_ADDRESS(SPD::MODULE_TYPE)); + + if ( l_errl ) + { + TS_FAIL( "testGetSPD- Failed to deviceRead with HUID= 0x%x", + TARGETING::get_huid(l_tDimm)); + continue; + } + + uint8_t l_memGen = 0x0; + l_errl = deviceRead(l_tDimm, + (void *)&l_memGen, + l_memSize, + DEVICE_SPD_ADDRESS(SPD::BASIC_MEMORY_TYPE)); + + if ( l_errl ) + { + TS_FAIL( "testGetSPD- Failed to deviceRead with HUID= 0x%x", + TARGETING::get_huid(l_tDimm)); + continue; + } + + // figure out the expected size based on the memory type + size_t l_compareSize = 0; + if( (l_memModule == SPD::MEM_DDIMM) && (l_memGen == SPD::MEM_DDR4) ) + { + l_compareSize = SPD::OCMB_SPD_EFD_COMBINED_SIZE; + } + else if( (l_memModule != SPD::MEM_DDIMM) && (l_memGen == SPD::MEM_DDR4) ) + { + l_compareSize = SPD::DDR4_SPD_SIZE; + } + else if( l_memGen == SPD::MEM_DDR3 ) + { + l_compareSize = SPD::DDR3_SPD_SIZE; + } + else + { + TS_FAIL( "testGetSPD - Unknown memory type for %.8X : module=0x%X, gen=0x%X", + TARGETING::get_huid(l_tDimm), l_memModule, l_memGen ); + continue; + } + + if( l_compareSize != l_spdSize ) + { + TS_FAIL( "testGetSPD - Wrong SPD size for %.8X : module=0x%X, gen=0x%X, exp=%d, act=%d", + TARGETING::get_huid(l_tDimm), l_memModule, l_memGen, + l_compareSize, l_spdSize); + continue; + } + + FAPI_DBG("getSPD: SPD data for DIMM with HUID=0x%.8X Size %d Blob %d", + TARGETING::get_huid(l_tDimm), + l_spdSize, + l_blobData); + } + + if( NULL != l_blobData ) + { + free( l_blobData ); + l_blobData = NULL; + } + + FAPI_INF( "testGetSPD - Exit" ); + } }; diff --git a/src/usr/fapi2/test/fapi2Test.mk b/src/usr/fapi2/test/fapi2Test.mk index f7dc4d002..074e4e45d 100644 --- a/src/usr/fapi2/test/fapi2Test.mk +++ b/src/usr/fapi2/test/fapi2Test.mk @@ -72,6 +72,8 @@ else ## All hostboot IPL time tests TESTS += ${shell ls ${ROOTPATH}/src/usr/fapi2/test/*Test.H | \ sort | xargs} +EXTRAINCDIR += ${ROOTPATH}/src/usr/expaccess/ + OBJS += p9_i2ctests.o OBJS += p9_mmiotests.o diff --git a/src/usr/fapi2/test/fapi2TestUtils.H b/src/usr/fapi2/test/fapi2TestUtils.H index 7b724a094..011538c63 100644 --- a/src/usr/fapi2/test/fapi2TestUtils.H +++ b/src/usr/fapi2/test/fapi2TestUtils.H @@ -225,7 +225,10 @@ enum PERVASIVE_CHILDREN { PERV_OBUS_CHILDREN = 1, PERV_CAPP_NIMBUS_CHILDREN = 1, PERV_CAPP_CUMULUS_CHILDREN = 2, + PERV_CAPP_AXONE_CHILDREN = 1, PERV_OBUS_BRICK_CHILDREN = 3, + PERV_OBUS_BRICK03_AXONE_CHILDREN = 2, + PERV_OBUS_BRICK12_AXONE_CHILDREN = 1, PERV_MCBIST_CHILDREN = 1, PERV_MCS_CHILDREN = 2, PERV_MCA_CHILDREN = 4, diff --git a/src/usr/fapi2/test/p9_mmiotests.C b/src/usr/fapi2/test/p9_mmiotests.C index 264e88117..1214e20fb 100644 --- a/src/usr/fapi2/test/p9_mmiotests.C +++ b/src/usr/fapi2/test/p9_mmiotests.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -37,6 +37,13 @@ #include <sbe/sbe_common.H> +// Write/Read from the inband response address (shouldn't hurt anything) +// Constants from #include <lib/inband/exp_inband.H> +static const uint64_t EXPLR_IB_MMIO_OFFSET = 0x0000000100000000ull; // 4GB +static const uint64_t EXPLR_IB_SRAM_BASE = 0x01000000; // MSCCRNGE 01000000 020FFFFF +static const uint64_t EXPLR_IB_RSP_SRAM_ADDR = EXPLR_IB_SRAM_BASE | 0x03FF00; +static const uint64_t EXPLR_IB_RSP_ADDR = EXPLR_IB_MMIO_OFFSET | EXPLR_IB_RSP_SRAM_ADDR; + fapi2::ReturnCode p9_mmiotest_getmmio_invalid_target( fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) { @@ -48,7 +55,7 @@ fapi2::ReturnCode p9_mmiotest_getmmio_invalid_target( FAPI_INF("Do getMMIO on a proc target for 8 bytes"); FAPI_TRY(fapi2::getMMIO(i_target, - 0x1000, // mmio address relative to target + EXPLR_IB_RSP_ADDR, // mmio address relative to target 8, // mmio transaction size l_mmiodata)); fapi_try_exit: @@ -75,7 +82,7 @@ fapi2::ReturnCode p9_mmiotest_putmmio_invalid_target( FAPI_INF( "Do putMMIO on proc target" ); FAPI_TRY(fapi2::putMMIO(i_target, - 0x1000, + EXPLR_IB_RSP_ADDR, 4, l_mmiodata)); @@ -100,7 +107,7 @@ fapi2::ReturnCode p9_mmiotest_indivisible_by_section_size( FAPI_INF("Do getMMIO on a target for 10 bytes"); FAPI_TRY(fapi2::getMMIO(i_target, - 0x1000, // mmio address relative to target + EXPLR_IB_RSP_ADDR, // mmio address relative to target 8, // mmio transaction size l_mmiodata)); fapi_try_exit: @@ -123,7 +130,7 @@ fapi2::ReturnCode p9_mmiotest_invalid_section_size( FAPI_INF("Do getMMIO on a target for 12 bytes"); FAPI_TRY(fapi2::getMMIO(i_target, - 0x1000, // mmio address relative to target + EXPLR_IB_RSP_ADDR, // mmio address relative to target 12, // mmio transaction size l_mmiodata)); fapi_try_exit: @@ -149,7 +156,7 @@ fapi2::ReturnCode p9_mmiotest_getmmio_pass( FAPI_INF("Do single-read transaction getMMIO on an OCMB target"); FAPI_TRY(fapi2::getMMIO(i_target, - 0x1000, + EXPLR_IB_RSP_ADDR, l_mmiodataSize, l_mmiodata) ); @@ -157,7 +164,7 @@ fapi2::ReturnCode p9_mmiotest_getmmio_pass( l_mmiodata.resize(l_mmiodataSize*2); // do a double mmio transaction FAPI_INF("Do double-read transaction getMMIO on an OCMB target"); FAPI_TRY(fapi2::getMMIO(i_target, - 0x1000, + EXPLR_IB_RSP_ADDR, l_mmiodataSize, l_mmiodata) ); @@ -183,7 +190,7 @@ fapi2::ReturnCode p9_mmiotest_double_read_pass( FAPI_INF("Do first getMMIO on an ocmb target"); FAPI_TRY(fapi2::getMMIO(i_target, - 0x1000, + EXPLR_IB_RSP_ADDR, l_mmioTransactionSize, l_1st_read) ); @@ -195,7 +202,7 @@ fapi2::ReturnCode p9_mmiotest_double_read_pass( FAPI_INF("Do second getMMIO on an ocmb target"); FAPI_TRY(fapi2::getMMIO(i_target, - 0x1000, + EXPLR_IB_RSP_ADDR, l_mmioTransactionSize, l_2nd_read) ); @@ -237,7 +244,7 @@ fapi2::ReturnCode p9_mmiotest_putmmio_pass( FAPI_INF("Do putMMIO on OCMB target"); FAPI_TRY(fapi2::putMMIO(i_target, - 0x1000, + EXPLR_IB_RSP_ADDR, 4, l_mmiodata)); fapi_try_exit: @@ -266,14 +273,14 @@ fapi2::ReturnCode p9_mmiotest_write_read_pass( // Write out a known value (name of this test) FAPI_INF("Calling putMMIO on the target (size: %d)", l_data_size); - FAPI_TRY(fapi2::putMMIO(i_target, 0x1000, + FAPI_TRY(fapi2::putMMIO(i_target, EXPLR_IB_RSP_ADDR, l_mmioTransactionSize, l_mmio_data)); // now read it out and verify it was written correctly FAPI_INF("Now read the just written data"); l_read_mmio_data.resize(l_data_size); FAPI_TRY(fapi2::getMMIO(i_target, - 0x1000, + EXPLR_IB_RSP_ADDR, l_mmioTransactionSize, l_read_mmio_data)); diff --git a/src/usr/fapiwrap/fapiWrap.C b/src/usr/fapiwrap/fapiWrap.C new file mode 100644 index 000000000..8950e0a92 --- /dev/null +++ b/src/usr/fapiwrap/fapiWrap.C @@ -0,0 +1,106 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/fapiwrap/fapiWrap.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +// Platform includes +#include <fapiwrap/fapiWrapif.H> // interface definitions +#include <fapi2/plat_hwp_invoker.H> // FAPI_INVOKE_HWP +#include <trace/interface.H> // tracing includes +#include <vpd/spdenums.H> // DDIMM_DDR4_SPD_SIZE +#include <devicefw/driverif.H> // deviceRead + +// Imported Includes +#include <exp_getidec.H> // exp_getidec +#include <pmic_i2c_addr_get.H> // get_pmic_i2c_addr +#include <chipids.H> // for GEMINI ID + + +trace_desc_t* g_trac_fapiwrap; +TRAC_INIT(&g_trac_fapiwrap, FAPIWRAP_COMP_NAME, 6*KILOBYTE, TRACE::BUFFER_SLOW); + + +namespace FAPIWRAP +{ + errlHndl_t explorer_getidec( TARGETING::Target * i_ocmbChip, + uint16_t& o_chipId, + uint8_t& o_ec) + { + errlHndl_t l_errl = nullptr; + + //assert type of i_ocmbChip == TARGETING::TYPE_OCMB_CHIP + assert(i_ocmbChip->getAttr<TARGETING::ATTR_TYPE>() == TARGETING::TYPE_OCMB_CHIP, + "exp_getidec_wrap: error expected type OCMB_CHIP"); + + fapi2::Target <fapi2::TARGET_TYPE_OCMB_CHIP> l_fapi_ocmb_target(i_ocmbChip); + + FAPI_INVOKE_HWP(l_errl, + exp_getidec, + l_fapi_ocmb_target, + o_chipId, + o_ec); + + return l_errl; + } + + errlHndl_t get_pmic_dev_addr( TARGETING::Target * i_ocmbChip, + const uint8_t i_pmic_id, + uint8_t& o_pmic_devAddr) + { + errlHndl_t l_errl = nullptr; + + do{ + + auto l_chipId = i_ocmbChip->getAttr< TARGETING::ATTR_CHIP_ID>(); + + if( l_chipId == POWER_CHIPID::GEMINI_16) + { + // If this is a Gemini OCMB then there are no PMIC targets + // so just set the out parm to NO_PMIC_DEV_ADDR and break + o_pmic_devAddr = NO_PMIC_DEV_ADDR; + break; + } + + uint8_t l_spdBlob[SPD::DDIMM_DDR4_SPD_SIZE]; + size_t l_spdSize = SPD::DDIMM_DDR4_SPD_SIZE; + + l_errl = deviceRead(i_ocmbChip, + l_spdBlob, + l_spdSize, + DEVICE_SPD_ADDRESS(SPD::ENTIRE_SPD_WITHOUT_EFD)); + + if(l_errl) + { + TRACFCOMP( g_trac_fapiwrap, ERR_MRK"get_pmic_dev_addr() " + "Error reading SPD associated with OCMB 0x%.08X", + TARGETING::get_huid(i_ocmbChip)); + break; + } + + o_pmic_devAddr = get_pmic_i2c_addr(reinterpret_cast<char *>(l_spdBlob), + i_pmic_id); + + }while(0); + return l_errl; + } +}
\ No newline at end of file diff --git a/src/usr/fapiwrap/makefile b/src/usr/fapiwrap/makefile new file mode 100644 index 000000000..1916630db --- /dev/null +++ b/src/usr/fapiwrap/makefile @@ -0,0 +1,53 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/fapiwrap/makefile $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2019 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +ROOTPATH = ../../.. +MODULE = fapiwrap + +# Add the import path to the include path +EXTRAINCDIR += ${ROOTPATH}/src/import +# to get fapi2.H +EXTRAINCDIR += ${ROOTPATH}/src/import/hwpf/fapi2/include/ +# to get target.H +EXTRAINCDIR += ${ROOTPATH}/src/include/usr/fapi2/ +# to get common_ringId.H +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/utils/imageProcs/ +# to get ffdc_includes.H +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/procedures/hwp/ffdc/ +# to get chipids.H +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/utils + +# HWP include directories : +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/explorer/procedures/hwp/memory/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/common/spd_access/ + +# HWP objects +OBJS += exp_getidec.o + +OBJS += fapiWrap.o + +# Add HWP src directories to VPATH +VPATH += ${ROOTPATH}/src/import/chips/ocmb/explorer/procedures/hwp/memory/ + +include ${ROOTPATH}/config.mk
\ No newline at end of file diff --git a/src/usr/fsi/fsipres.C b/src/usr/fsi/fsipres.C index 873b58af4..f0a8f7c3a 100644 --- a/src/usr/fsi/fsipres.C +++ b/src/usr/fsi/fsipres.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2018 */ +/* Contributors Listed Below - COPYRIGHT 2011,2019 */ /* [+] Google Inc. */ /* [+] International Business Machines Corp. */ /* */ @@ -33,7 +33,6 @@ #include <errl/errlmanager.H> #include <hwas/common/hwasCallout.H> #include <targeting/common/predicates/predicatectm.H> -#include <config.h> #include <initservice/initserviceif.H> extern trace_desc_t* g_trac_fsi; diff --git a/src/usr/fsi/runtime/rt_fsi.C b/src/usr/fsi/runtime/rt_fsi.C index 75103cc4b..551ef7b4e 100644 --- a/src/usr/fsi/runtime/rt_fsi.C +++ b/src/usr/fsi/runtime/rt_fsi.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -24,7 +24,7 @@ /* IBM_PROLOG_END_TAG */ #include <stdlib.h> -#include <runtime/rt_targeting.H> +#include <targeting/runtime/rt_targeting.H> #include <runtime/interface.h> #include <targeting/common/targetservice.H> diff --git a/src/usr/gpio/HBconfig b/src/usr/gpio/HBconfig index e5f650eb9..20ed72dd0 100644 --- a/src/usr/gpio/HBconfig +++ b/src/usr/gpio/HBconfig @@ -1,4 +1,4 @@ config GPIODD - default n + default y help Enable GPIO device driver support diff --git a/src/usr/gpio/gpio_pca9551.C b/src/usr/gpio/gpio_pca9551.C new file mode 100644 index 000000000..6edbd1a9a --- /dev/null +++ b/src/usr/gpio/gpio_pca9551.C @@ -0,0 +1,343 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/gpio/gpio_pca9551.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/** + * @file gpio_pca9551.C + * + * @brief Implements Interfaces Specific to the PCA9551 GPIO Devices + * + * @note Reference: https://www.nxp.com/docs/en/data-sheet/PCA9551.pdf + * + */ + + +#include <trace/interface.H> +#include <errl/errlentry.H> +#include <errl/errlmanager.H> +#include <errl/errludtarget.H> +#include <errl/errludstring.H> +#include <targeting/common/targetservice.H> +#include <targeting/common/commontargeting.H> +#include <devicefw/driverif.H> +#include "gpiodd.H" +#include <gpio/gpioddreasoncodes.H> +#include <gpio/gpioif.H> +#include <config.h> + +extern trace_desc_t* g_trac_gpio; + +// Set to TRACFCOMP to enable unit trace +#define TRACUCOMP(args...) TRACDCOMP(args) + +using namespace DeviceFW; +using namespace TARGETING; + +namespace GPIO +{ + + +void gpioPca9551SetReigsterHelper(const PCA9551_LEDS_t i_led, + const PCA9551_LED_Output_Settings_t i_setting, + uint8_t & io_led_register_data) +{ + uint8_t l_led = i_led; + uint8_t l_mask = PCA9551_LED_SETTINGS_MASK; // 2-bit mask shifted over to + // match i_led's value + uint8_t l_setting = i_setting; // will be shifted with 2-bit mask before it is applied + + // Adjust values for LEDs 4 to 7 to match calculations below for LEDs 0 to 3 + if (i_led > PCA9551_LED3) + { + l_led = l_led / PCA9551_LED_SETTINGS_DIVISOR; + } + TRACUCOMP(g_trac_gpio, "gpioPca9551SetReigsterHelper: " + "i_led=0x%.2X, l_led=0x%.2X, l_mask=0x%.2X, " + "l_setting=0x%.2X, data0=0x%.2X", + i_led, l_led, l_mask, l_setting,io_led_register_data); + + // Move 2-bit mask and setting to cover the correct values + // Setting register is uint8_t broken into 4 2-bit setting sections: + // [LED3 Setting][LED2 Setting][LED1 Setting][LED0 Setting] + // --OR-- + // [LED7 Setting][LED6 Setting][LED5 Setting][LED4 Setting] + + const uint8_t match = 0x01; // shift values until l_led == match + + // l_led must be >= match or following loop won't work + assert(l_led >= match, "gpioPca9551SetReigsterHelper: l_led %d is < match %d", l_led, match); + + TRACUCOMP(g_trac_gpio,"gpioPca9551SetReigsterHelper: Pre-loop: " + "l_led=0x%.2X, match=0x%.2X", + l_led, match); + while ( match != l_led ) + { + l_led = l_led >> PCA9551_LED_SHIFT_AMOUNT; + l_mask = l_mask << PCA9551_LED_SETTINGS_MASK_SHIFT_AMOUNT; + l_setting = l_setting << PCA9551_LED_SETTINGS_MASK_SHIFT_AMOUNT; + TRACUCOMP(g_trac_gpio,"gpioPca9551SetReigsterHelper: inside-loop: " + "l_led=0x%.2X, l_mask=0x%.2X, l_setting=0x%.2X", + l_led, l_mask, l_setting); + } + TRACUCOMP(g_trac_gpio, "gpioPca9551SetReigsterHelper: Post-loop: " + "l_mask=0x%.2X, l_setting=0x%.2X", + l_mask, l_setting); + + // Apply Mask to Register data and then OR-in setting bits + io_led_register_data = (io_led_register_data & ~l_mask) | l_setting; + TRACUCOMP(g_trac_gpio, "gpioPca9551SetReigsterHelper: " + "io_led_register_data=0x%.2X", + io_led_register_data); + + return; +} + + +errlHndl_t gpioPca9551GetLeds(TARGETING::Target * i_target, + uint8_t & o_led_data) +{ + errlHndl_t err = nullptr; + + TRACUCOMP(g_trac_gpio, ENTER_MRK"gpioPca9551GetLeds: " + "i_target 0x%.08X", + get_huid(i_target)); + + do + { + + // Read PCA9551 INPUT Register to get Pin (aka LED) Values + uint8_t data = 0; + size_t data_len = sizeof(data); + const size_t exp_data_len = data_len; + uint64_t device_type = PCA9551_GPIO_PHYS_PRES; + uint64_t register_addr = PCA9551_REGISTER_INPUT; + + err = DeviceFW::deviceOp + ( DeviceFW::READ, + i_target, + &data, + data_len, + DEVICE_GPIO_ADDRESS(device_type, register_addr) + ); + if(err) + { + TRACFCOMP(g_trac_gpio, ERR_MRK"gpioPca9551GetLeds: " + "Reading INPUT register failed"); + break; + } + else + { + o_led_data = data; + TRACUCOMP(g_trac_gpio, INFO_MRK"gpioPca9551GetLeds: " + "register_addr=0x%X, o_led_data=0x%.2X", + register_addr, o_led_data); + } + assert(data_len==exp_data_len, "gpioPca9551GetLeds: expected %d size of data but got %d", exp_data_len, data_len); + + } while (0); + + if (err) + { + err->collectTrace( GPIO_COMP_NAME ); + } + + return err; +} + +errlHndl_t gpioPca9551SetLed(TARGETING::Target * i_target, + const PCA9551_LEDS_t i_led, + const PCA9551_LED_Output_Settings_t i_setting, + uint8_t & o_led_data) +{ + errlHndl_t err = nullptr; + + TRACUCOMP(g_trac_gpio, ENTER_MRK"gpioPca9551SetLed: " + "i_target 0x%.8X, i_led=0x%.2X, i_setting=0x%.2X", + get_huid(i_target), i_led, i_setting); + + do + { + uint64_t deviceType = PCA9551_GPIO_PHYS_PRES; + + // First Read Select Register - either LS0 (LEDs 0-3) or LS1 (LEDs 4-7) + uint64_t register_addr = PCA9551_REGISTER_LS0; + if (i_led > PCA9551_LED3) + { + register_addr = PCA9551_REGISTER_LS1; + } + uint8_t data = 0; + size_t data_len = sizeof(data); + const size_t exp_data_len = data_len; + + err = DeviceFW::deviceOp + ( DeviceFW::READ, + i_target, + &data, + data_len, + DEVICE_GPIO_ADDRESS(deviceType, register_addr) + ); + if(err) + { + TRACFCOMP(g_trac_gpio, ERR_MRK"gpioPca9551SetLed: " + "Reading LED Select register 0x%X failed", + register_addr); + break; + } + else + { + TRACUCOMP(g_trac_gpio, INFO_MRK"gpioPca9551SetLed: " + "LED Select register_addr=0x%X, data=0x%.2X", + register_addr, data); + } + assert(data_len==exp_data_len, "gpioPca9551SetLed: expected %d size of data but got %d", exp_data_len, data_len); + + + // Create Setting Register to Write Back: + uint8_t write_data = data; + gpioPca9551SetReigsterHelper(i_led, i_setting, write_data); + + // Write LED Select Register + data = write_data; + + err = DeviceFW::deviceOp + ( DeviceFW::WRITE, + i_target, + &data, + data_len, + DEVICE_GPIO_ADDRESS(deviceType, register_addr) + ); + if(err) + { + TRACFCOMP(g_trac_gpio, ERR_MRK"gpioPca9551SetLed: " + "Writing LED Select register 0x%X failed", + register_addr); + break; + } + else + { + TRACUCOMP(g_trac_gpio, INFO_MRK"gpioPca9551SetLed: " + "Writing LED Select register_addr=0x%X, data=0x%.2X", + register_addr, data); + } + assert(data_len==exp_data_len, "gpioPca9551SetLed: expected %d size of data but got %d", exp_data_len, data_len); + + + // Read Back LED Select Register + data = 0; + err = DeviceFW::deviceOp + ( DeviceFW::READ, + i_target, + &data, + data_len, + DEVICE_GPIO_ADDRESS(deviceType, register_addr) + ); + if(err) + { + TRACFCOMP(g_trac_gpio, ERR_MRK"gpioPca9551SetLed: " + "Reading LED Select register 0x%X failed", + register_addr); + break; + } + else + { + TRACUCOMP(g_trac_gpio, INFO_MRK"gpioPca9551SetLed: " + "LED Select register_addr=0x%X, data=0x%.2X", + register_addr, data); + } + assert(data_len==exp_data_len, "gpioPca9551SetLed: expected %d size of data but got %d", exp_data_len, data_len); + + // Compare data written and data read back + if (data != write_data) + { + TRACFCOMP(g_trac_gpio, ERR_MRK"gpioPca9551SetLed: " + "Reading Back LED Select register 0x%X had unexpected data=", + "0x%.2X. Expected 0x%.2X", + register_addr, data, write_data); + + /*@ + * @errortype + * @reasoncode GPIO_PCA9551_DATA_MISMATCH + * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE + * @moduleid GPIO_PCA9551_SET_LED + * @userdata1[0:31] HUID of Master Processor Target + * @userdata1[32:63] Input LED to Set + * @userdata2[0:31] Expected Data (aka data written) + * @userdata2[32:63] Data Read Back + * @devdesc Setting of LED value did not appear to work + * @custdesc A problem occurred during the IPL + * of the system. + */ + err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE, + GPIO_PCA9551_SET_LED, + GPIO_PCA9551_DATA_MISMATCH, + TWO_UINT32_TO_UINT64( + get_huid(i_target), + i_led), + TWO_UINT32_TO_UINT64( + write_data, + data), + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + + break; + } + + // Read PCA9551 INPUT Register to get Pin (aka LED) Values + data = 0; + data_len = sizeof(data); + register_addr = PCA9551_REGISTER_INPUT; + + err = DeviceFW::deviceOp + ( DeviceFW::READ, + i_target, + &data, + data_len, + DEVICE_GPIO_ADDRESS(deviceType, register_addr) + ); + if(err) + { + TRACFCOMP(g_trac_gpio, ERR_MRK"gpioPca9551SetLed: " + "Reading INPUT register failed"); + break; + } + else + { + o_led_data = data; + TRACUCOMP(g_trac_gpio, INFO_MRK"gpioPca9551SetLed: " + "INPUT register_addr=0x%X, o_led_data=0x%.2X", + register_addr, o_led_data); + } + assert(data_len==exp_data_len, "gpioPca9551SetLed: expected %d size of data but got %d", exp_data_len, data_len); + + } while (0); + + if (err) + { + err->collectTrace( GPIO_COMP_NAME ); + } + + return err; + +} + +}; // end namespace GPIO + diff --git a/src/usr/gpio/gpiodd.C b/src/usr/gpio/gpiodd.C index 559dab79e..50fa193c5 100644 --- a/src/usr/gpio/gpiodd.C +++ b/src/usr/gpio/gpiodd.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014,2018 */ +/* Contributors Listed Below - COPYRIGHT 2014,2019 */ /* [+] Google Inc. */ /* [+] International Business Machines Corp. */ /* */ @@ -34,6 +34,8 @@ #include <devicefw/driverif.H> #include "gpiodd.H" #include <gpio/gpioddreasoncodes.H> +#include <gpio/gpioif.H> +#include <config.h> trace_desc_t * g_trac_gpio = NULL; TRAC_INIT( & g_trac_gpio, GPIO_COMP_NAME, KILOBYTE ); @@ -57,6 +59,11 @@ DEVICE_REGISTER_ROUTE( DeviceFW::WILDCARD, TARGETING::TYPE_MEMBUF, gpioPerformOp); +DEVICE_REGISTER_ROUTE( DeviceFW::WILDCARD, + DeviceFW::GPIO, + TARGETING::TYPE_PROC, + gpioPerformOp); + errlHndl_t gpioPerformOp(DeviceFW::OperationType i_opType, TARGETING::Target * i_target, void * io_buffer, @@ -237,20 +244,51 @@ errlHndl_t gpioReadAttributes ( TARGETING::Target * i_target, { errlHndl_t err = NULL; - TARGETING::GpioInfo gpioData; - bool attrReadErr = false; +#ifndef CONFIG_FSP_BUILD + TARGETING::GpioInfo gpioData; +#endif + TARGETING::GpioInfoPhysPres gpioDataPhysPres; switch(io_gpioInfo.deviceType) { +#ifndef CONFIG_FSP_BUILD case PCA95X_GPIO: if( !( i_target-> tryGetAttr<TARGETING::ATTR_GPIO_INFO>( gpioData ) ) ) { attrReadErr = true; } + else + { + io_gpioInfo.i2cMasterPath = gpioData.i2cMasterPath; + io_gpioInfo.engine = gpioData.engine; + io_gpioInfo.i2cPort = gpioData.port; + io_gpioInfo.i2cDeviceAddr = gpioData.devAddr; + io_gpioInfo.i2cMuxBusSelector = gpioData.i2cMuxBusSelector; + io_gpioInfo.i2cMuxPath = gpioData.i2cMuxPath; + } break; +#endif + case PCA9551_GPIO_PHYS_PRES: + + if( !( i_target-> + tryGetAttr<TARGETING::ATTR_GPIO_INFO_PHYS_PRES>(gpioDataPhysPres))) + { + attrReadErr = true; + } + else + { + io_gpioInfo.i2cMasterPath = gpioDataPhysPres.i2cMasterPath; + io_gpioInfo.engine = gpioDataPhysPres.engine; + io_gpioInfo.i2cPort = gpioDataPhysPres.port; + io_gpioInfo.i2cDeviceAddr = gpioDataPhysPres.devAddr; + io_gpioInfo.i2cMuxBusSelector = gpioDataPhysPres.i2cMuxBusSelector; + io_gpioInfo.i2cMuxPath = gpioDataPhysPres.i2cMuxPath; + } + break; + default: TRACFCOMP( g_trac_gpio,ERR_MRK"gpioReadAttributes() - " @@ -309,16 +347,6 @@ errlHndl_t gpioReadAttributes ( TARGETING::Target * i_target, err->collectTrace( GPIO_COMP_NAME ); } - if( !err ) - { - io_gpioInfo.i2cMasterPath = gpioData.i2cMasterPath; - io_gpioInfo.engine = gpioData.engine; - io_gpioInfo.i2cPort = gpioData.port; - io_gpioInfo.i2cDeviceAddr = gpioData.devAddr; - io_gpioInfo.i2cMuxBusSelector = gpioData.i2cMuxBusSelector; - io_gpioInfo.i2cMuxPath = gpioData.i2cMuxPath; - } - return err; } diff --git a/src/usr/gpio/makefile b/src/usr/gpio/makefile index d40eaa130..fd42e2d1d 100644 --- a/src/usr/gpio/makefile +++ b/src/usr/gpio/makefile @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2014 +# Contributors Listed Below - COPYRIGHT 2014,2019 # [+] Google Inc. # [+] International Business Machines Corp. # @@ -27,6 +27,8 @@ ROOTPATH = ../../.. MODULE = gpio OBJS += $(if $(CONFIG_GPIODD),gpiodd.o,) +OBJS += $(if $(CONFIG_GPIODD),gpio_pca9551.o,) + # no way to test this at the moment TODO RTC 111415 #SUBDIRS = test.d diff --git a/src/usr/hdat/hdatiohub.C b/src/usr/hdat/hdatiohub.C index c2f5d7eea..c9be567ff 100644 --- a/src/usr/hdat/hdatiohub.C +++ b/src/usr/hdat/hdatiohub.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -54,7 +54,6 @@ vpdData mvpdData[] = { PVPD::VINI, PVPD::B4 }, { PVPD::VINI, PVPD::B7 }, { PVPD::VINI, PVPD::PF }, - { PVPD::VINI, PVPD::LX }, }; const HdatKeywordInfo l_pvpdKeywords[] = @@ -74,7 +73,18 @@ const HdatKeywordInfo l_pvpdKeywords[] = { PVPD::B4, "B4" }, { PVPD::B7, "B7" }, { PVPD::PF, "PF" }, - { PVPD::LX, "LX" }, +}; + +vpdData pvpdDataAxone[] = +{ + { PVPD::OPFR, PVPD::VP }, + { PVPD::OPFR, PVPD::VS }, +}; + +const HdatKeywordInfo l_pvpdKeywordsAxone[] = +{ + { PVPD::VP, "VP" }, + { PVPD::VS, "VS" }, }; extern trace_desc_t *g_trac_hdat; @@ -653,13 +663,28 @@ errlHndl_t HdatIoHubFru::addDaughterCard(uint32_t i_resourceId, // told to allow for on the constructor if (iv_actDaughterCnt < iv_maxDaughters) { + //Get the processor model + auto l_model = TARGETING::targetService().getProcessorModel(); + if ( l_vpdType == FRU_BP ) { - - uint32_t i_num = sizeof(mvpdData)/sizeof(mvpdData[0]); - l_vpdObj = new HdatVpd(l_errlHndl, i_resourceId,i_target, - HDAT_KID_STRUCT_NAME,i_index,BP, - mvpdData,i_num,l_pvpdKeywords); + //@TODO:RTC 213229(Remove HDAT hack or Axone) + //Check whether the code can be more fault tolerant by avoiding + //model check + if(l_model == TARGETING::MODEL_NIMBUS) + { + uint32_t i_num = sizeof(mvpdData)/sizeof(mvpdData[0]); + l_vpdObj = new HdatVpd(l_errlHndl, i_resourceId,i_target, + HDAT_KID_STRUCT_NAME,i_index,BP, + mvpdData,i_num,l_pvpdKeywords); + } + else if(l_model == TARGETING::MODEL_AXONE) + { + uint32_t i_num = sizeof(pvpdDataAxone)/sizeof(pvpdDataAxone[0]); + l_vpdObj = new HdatVpd(l_errlHndl, i_resourceId,i_target, + HDAT_KID_STRUCT_NAME,i_index,BP, + pvpdDataAxone,i_num,l_pvpdKeywordsAxone); + } } //@TODO: RTC 148660 pci slots and cards @@ -900,6 +925,10 @@ errlHndl_t hdatLoadIoData(const hdatMsAddr_t &i_msAddr, { l_hub->hdatModuleId = HDAT_MODULE_TYPE_ID_NIMBUS_LAGRANGE; } + else if(l_model == TARGETING::MODEL_AXONE) + { + l_hub->hdatModuleId = HDAT_MODULE_TYPE_ID_AXONE_HOPPER; + } else if(l_model == TARGETING::MODEL_CUMULUS) { l_hub->hdatModuleId = HDAT_MODULE_TYPE_ID_CUMULUS_DUOMO; diff --git a/src/usr/hdat/hdatiohub.H b/src/usr/hdat/hdatiohub.H index 14c3a8524..9823c9146 100755 --- a/src/usr/hdat/hdatiohub.H +++ b/src/usr/hdat/hdatiohub.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -273,6 +273,7 @@ enum hdatHubStatus //@TODO:RTC 166789: Need to access the module type from HB targeting model #define HDAT_MODULE_TYPE_ID_NIMBUS_LAGRANGE 0x0022 #define HDAT_MODULE_TYPE_ID_CUMULUS_DUOMO 0x0030 +#define HDAT_MODULE_TYPE_ID_AXONE_HOPPER 0x0040 diff --git a/src/usr/hdat/hdatiplparms.C b/src/usr/hdat/hdatiplparms.C index a22dfbbe2..c0b24e49d 100755 --- a/src/usr/hdat/hdatiplparms.C +++ b/src/usr/hdat/hdatiplparms.C @@ -564,10 +564,7 @@ static void hdatGetFeatureFlagInfo( l_ddLevel = l_pvr.getDDLevel(); // Default to Nimbus DD2.3 - uint8_t l_ddLvlIdx = 2; - l_featFlagArr = hdatIplpFeatureFlagSettingsArray[l_riskLvl][l_ddLvlIdx]; - l_featFlagArrSize = - sizeof(hdatIplpFeatureFlagSettingsArray[l_riskLvl][l_ddLvlIdx]); + uint8_t l_ddLvlIdx = HDAT_NIMBUS_DD_23_IDX; // Set the value based on DD level and risk level if (l_pvr.chipType == PVR_t::NIMBUS_CHIP) @@ -586,12 +583,17 @@ static void hdatGetFeatureFlagInfo( { l_ddLvlIdx = HDAT_NIMBUS_DD_23_IDX; } - - l_featFlagArr = hdatIplpFeatureFlagSettingsArray[l_riskLvl][l_ddLvlIdx]; - l_featFlagArrSize = - sizeof(hdatIplpFeatureFlagSettingsArray[l_riskLvl][l_ddLvlIdx]); } - + else if (l_pvr.chipFamily == PVR_t::P9_AXONE) + { + // Axone follows the Nimbus DD2.3 settings + l_ddLvlIdx = HDAT_NIMBUS_DD_23_IDX; + } + + l_featFlagArr = hdatIplpFeatureFlagSettingsArray[l_riskLvl][l_ddLvlIdx]; + l_featFlagArrSize = + sizeof(hdatIplpFeatureFlagSettingsArray[l_riskLvl][l_ddLvlIdx]); + HDAT_DBG("Feature flag array size:0x%x, Model:0x%x, DD Level:0x%x " "Risk Level:0x%x", l_featFlagArrSize, l_pvr.chipType, l_ddLevel, l_riskLvl); @@ -705,8 +707,16 @@ void HdatIplParms::hdatGetSystemParamters() HDAT_ERR(" Error in getting attribute PAYLOAD_IN_MIRROR_MEM"); } - this->iv_hdatIPLParams->iv_sysParms.hdatSystemAttributes |= - l_pSysTarget->getAttr<ATTR_RISK_LEVEL>() ? HDAT_RISK_LEVEL_ELEVATED : 0 ; + // Check both compat and native mode for relevant risk levels + ATTR_RISK_LEVEL_type l_risk = l_pSysTarget->getAttr<ATTR_RISK_LEVEL>(); + if( !((l_risk == UTIL::P9N22_P9C12_RUGBY_FAVOR_SECURITY) + || (l_risk == UTIL::P9N23_P9C13_NATIVE_SMF_RUGBY_FAVOR_SECURITY)) ) + { + // running in a mode that doesn't favor security, set elevated risk + this->iv_hdatIPLParams->iv_sysParms.hdatSystemAttributes |= + HDAT_RISK_LEVEL_ELEVATED; + } + this->iv_hdatIPLParams->iv_sysParms.hdatSystemAttributes |= l_pSysTarget->getAttr<ATTR_IS_MPIPL_SUPPORTED>() ? HDAT_MPIPL_SUPPORTED : 0 ; diff --git a/src/usr/hdat/hdatiplparms.H b/src/usr/hdat/hdatiplparms.H index 86eb4ad5f..7e7380e93 100755 --- a/src/usr/hdat/hdatiplparms.H +++ b/src/usr/hdat/hdatiplparms.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2019 */ +/* Contributors Listed Below - COPYRIGHT 2016,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -593,7 +593,7 @@ const hdatIplpFeatureFlagSetting_t hdatIplpFeatureFlagSettingsArray[NUM_RISK_LEV #define HDAT_SMM_ENABLED 0x40000000 #define HDAT_CRYPTO_DISABLED_BIT 0x20000000 #define HDAT_RISK_LEVEL_ELEVATED 0x10000000 -#define HDAT_MPIPL_SUPPORTED 0x08000000 +#define HDAT_MPIPL_SUPPORTED 0x04000000 #define HDAT_ECO_ENABLED 0x80000000 #define HDAT_ECO_CAPABLE 0x40000000 diff --git a/src/usr/hdat/hdatmsarea.C b/src/usr/hdat/hdatmsarea.C index 78c3633e8..336428644 100755 --- a/src/usr/hdat/hdatmsarea.C +++ b/src/usr/hdat/hdatmsarea.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -309,7 +309,8 @@ errlHndl_t HdatMsArea::addAddrRange(hdatMsAddr_t &i_start, bool i_rangeIsMirrorable, uint8_t i_mirroringAlgorithm, hdatMsAddr_t &i_startMirrAddr, - uint32_t i_memcntlrId) + uint32_t i_memcntlrId, + bool i_hdatSmf) { HDAT_ENTER(); errlHndl_t l_errlHndl = NULL; @@ -324,9 +325,10 @@ errlHndl_t HdatMsArea::addAddrRange(hdatMsAddr_t &i_start, l_addr->hdatMsAreaStrAddr = i_start; l_addr->hdatMsAreaEndAddr = i_end; l_addr->hatMsAreaProcChipId = i_procChipId; - l_addr->hdatSMMAttributes.hdatRangeIsMirrorable = - i_rangeIsMirrorable ? 1 : 0; + l_addr->hdatSMMAttributes.hdatRangeIsMirrorable = + i_rangeIsMirrorable ? 1 : 0; l_addr->hdatSMMAttributes.hdatMirroringAlgorithm = i_mirroringAlgorithm; + l_addr->hdatSMMAttributes.hdatIsSMFmemory = i_hdatSmf; l_addr->hdatStartMirrAddr = i_startMirrAddr; l_addr->hdatMsAreaMemCntId = i_memcntlrId; iv_addrRngArrayHdr.hdatArrayCnt++; @@ -343,7 +345,7 @@ errlHndl_t HdatMsArea::addAddrRange(hdatMsAddr_t &i_start, * @userdata2 maximum number of array entries * @userdata3 ID number of mainstore area * @userdata4 none - * @devdesc Failed trying to add another entry to a mainstore area + * @devdesc Failed trying to add another entry to a mainstore area * address range array */ hdatBldErrLog(l_errlHndl, diff --git a/src/usr/hdat/hdatmsarea.H b/src/usr/hdat/hdatmsarea.H index f39ad3737..83236d134 100755 --- a/src/usr/hdat/hdatmsarea.H +++ b/src/usr/hdat/hdatmsarea.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -51,7 +51,7 @@ namespace HDAT /* Constants */ /*----------------------------------------------------------------------------*/ -const uint16_t HDAT_MS_AREA_VERSION = 0x30; +const uint16_t HDAT_MS_AREA_VERSION = 0x50; const char HDAT_MSAREA_STRUCT_NAME[] = "MSAREA"; /** @brief Since the size of each MS Area must the same as all others, the @@ -119,10 +119,11 @@ struct hdatMsAreaSize_t */ struct hdatSMMAttributes_t { - uint8_t hdatRangeIsMirrorable; // 0x0000 Memory range is mirrorable - uint8_t hdatMirroringAlgorithm; // 0x0001 Hardware mirroring algorithm to + uint8_t hdatRangeIsMirrorable; // 0x0000 Memory range is mirrorable + uint8_t hdatMirroringAlgorithm; // 0x0001 Hardware mirroring algorithm to // use - uint16_t hdatReserved; // 0x0002 + uint8_t hdatIsSMFmemory; // 0x0002 SMF memory region + uint8_t hdatReserved; // 0x0003 } __attribute__ ((packed)); @@ -418,6 +419,7 @@ public: * @param[in] i_startMirrAddr - Specifies the starting mirrorable * address for range * @param[in] i_memcntlrId - Memory Controller ID + * @param[in] i_hdatSmf - Whether the range is in SMF memory * * @return A null error log handle if successful, else the return code pointed * to by o_errlHndl contains one of: @@ -427,10 +429,11 @@ public: errlHndl_t addAddrRange(hdatMsAddr_t &i_start, hdatMsAddr_t &i_end, uint32_t i_procChipId, - bool i_rangeIsMirrorable, - uint8_t i_mirroringAlgorithm, - hdatMsAddr_t &i_startMirrAddr, - uint32_t i_memcntlrId); + bool i_rangeIsMirrorable, + uint8_t i_mirroringAlgorithm, + hdatMsAddr_t &i_startMirrAddr, + uint32_t i_memcntlrId, + bool i_hdatSmf); /** diff --git a/src/usr/hdat/hdatmsvpd.C b/src/usr/hdat/hdatmsvpd.C index e5593db3d..5b67903f7 100755 --- a/src/usr/hdat/hdatmsvpd.C +++ b/src/usr/hdat/hdatmsvpd.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -609,7 +609,8 @@ errlHndl_t HdatMsVpd::addMsAreaAddr(uint16_t i_msAreaId, bool i_rangeIsMirrorable, uint8_t i_mirroringAlgorithm, uint64_t i_startMirrAddr, - uint32_t i_hdatMemCntrlID) + uint32_t i_hdatMemCntrlID, + bool i_hdatSmf) { errlHndl_t l_errlHndl = NULL; HdatMsArea *l_obj; @@ -620,8 +621,14 @@ errlHndl_t HdatMsVpd::addMsAreaAddr(uint16_t i_msAreaId, if (i_msAreaId < iv_actMsAreaCnt) { l_obj = HDAT_MS_AREA(i_msAreaId); - l_errlHndl = l_obj->addAddrRange(i_start, i_end, i_procChipId, - i_rangeIsMirrorable, i_mirroringAlgorithm, l_startMirrAddr, i_hdatMemCntrlID); + l_errlHndl = l_obj->addAddrRange(i_start, + i_end, + i_procChipId, + i_rangeIsMirrorable, + i_mirroringAlgorithm, + l_startMirrAddr, + i_hdatMemCntrlID, + i_hdatSmf); } else { @@ -926,6 +933,8 @@ void HdatMsVpd::prt() iv_mover.hdatMoverAddr.lo); HDAT_INF(" hdatBSRAddr = 0X %08X %08X ", iv_mover.hdatBSRAddr.hi, iv_mover.hdatBSRAddr.lo); + HDAT_INF(" hdatXSCOMAddr = 0X %08X %08X", iv_mover.hdatXSCOMAddr.hi, + iv_mover.hdatXSCOMAddr.lo); HDAT_INF(" **hdatMsVpdImtAddrRange_t**"); hdatPrintHdrs(NULL, NULL, &iv_IMTaddrRngArrayHdr, NULL); @@ -1013,8 +1022,13 @@ errlHndl_t HdatMsVpd::hdatLoadMsData(uint32_t &o_size, uint32_t &o_count) l_addr_range.lo = 0x0; l_end = l_addr_range; + //Get the processor model + auto l_model = TARGETING::targetService().getProcessorModel(); + uint32_t l_sizeConfigured = 0; - uint64_t l_maxMsAddr = hdatGetMaxMemConfiguredAddress(); + + uint64_t l_maxMsAddr = + hdatGetMaxMemConfiguredAddress(l_model); hdatMsAddr_t l_tmpMaxMsAddr; l_tmpMaxMsAddr.hi = (l_maxMsAddr & 0xFFFFFFFF00000000ull) >> 32; @@ -1037,10 +1051,19 @@ errlHndl_t HdatMsVpd::hdatLoadMsData(uint32_t &o_size, uint32_t &o_count) TARGETING::ATTR_MAX_MCS_PER_SYSTEM_type l_maxMsAreas = l_pSysTarget->getAttr<TARGETING::ATTR_MAX_MCS_PER_SYSTEM>(); + if (l_model == TARGETING::MODEL_NIMBUS) + { + l_maxMsAreas *= 2; + } + else + { + l_maxMsAreas = HDAT_MAX_MSAREA_AXONE; + } + // Initialize the MS vpd class // TODO : RTC Story 166994 to set the maximum number of Ms Area entries // from new attribute - hdatInit(l_tmpMaxMsAddr,l_tmpMaxMsAddr,l_sizeConfigured,l_maxMsAreas*2, + hdatInit(l_tmpMaxMsAddr,l_tmpMaxMsAddr,l_sizeConfigured,l_maxMsAreas, l_mostSigAffinityDomain_x,l_ueCount,l_mirroringBaseAddress_x); TARGETING::ATTR_XSCOM_BASE_ADDRESS_type l_xscomAddr = @@ -1056,7 +1079,9 @@ errlHndl_t HdatMsVpd::hdatLoadMsData(uint32_t &o_size, uint32_t &o_count) setXSCOM(l_hdatXscomAddr); } + // This contains the MS Area Index uint32_t l_index = 0; + //for each proc/ memory controller in the system TARGETING::PredicateCTM l_procPred(TARGETING::CLASS_CHIP, TARGETING::TYPE_PROC); @@ -1076,77 +1101,12 @@ errlHndl_t HdatMsVpd::hdatLoadMsData(uint32_t &o_size, uint32_t &o_count) for(;l_procs;++l_procs) { + bool l_smfAdded = false; + TARGETING::Target *l_pProcTarget = *(l_procs); TARGETING::ATTR_ORDINAL_ID_type l_procChipId = l_pProcTarget->getAttr<TARGETING::ATTR_ORDINAL_ID>(); - - //For each MCA - TARGETING::PredicateCTM l_allMca(TARGETING::CLASS_UNIT, - TARGETING::TYPE_MCA); - TARGETING::PredicateHwas l_funcMca; - l_funcMca.functional(true); - TARGETING::PredicatePostfixExpr l_allFuncMca; - l_allFuncMca.push(&l_allMca).push(&l_funcMca).And(); - - TARGETING::TargetHandleList l_mcaList; - - TARGETING::targetService(). - getAssociated(l_mcaList, l_pProcTarget, - TARGETING::TargetService::CHILD, - TARGETING::TargetService::ALL, &l_allFuncMca); - - TARGETING::ATTR_PROC_MEM_BASES_type l_procMemBases = {0}; - assert(l_pProcTarget-> - tryGetAttr<TARGETING::ATTR_PROC_MEM_BASES>(l_procMemBases)); - - //Sharing count for each group - TARGETING::ATTR_MSS_MEM_MC_IN_GROUP_type l_mcaSharingCount = {0}; - - //Group ID for each group, group id will be assigned only - //if the group is shared - TARGETING::ATTR_MSS_MEM_MC_IN_GROUP_type l_mcsSharingGrpIds = {0}; - - //Size configured under each group - TARGETING::ATTR_PROC_MEM_SIZES_type l_procMemSizesBytes = {0}; - - assert(l_pProcTarget->tryGetAttr<TARGETING::ATTR_PROC_MEM_SIZES> - (l_procMemSizesBytes)); - - - - for(uint32_t l_mcaIdx = 0; l_mcaIdx<l_mcaList.size(); - ++l_mcaIdx) - { - uint32_t l_mcaInGrp = 0; - TARGETING::Target *l_pMcaTarget = - l_mcaList[l_mcaIdx]; - if(!hdatFindGroupForMc(l_pProcTarget, - l_pMcaTarget, - l_mcaInGrp)) - { - //Skip this MCA is not in any group - continue; - } - - //Increment sharing count if mem configured under group. - if(l_procMemSizesBytes[l_mcaInGrp] > 0) - { - l_mcaSharingCount[l_mcaInGrp]++; - - //Assign sharing group id only if shared - //And only when first instance of sharing is found - if(l_mcaSharingCount[l_mcaInGrp] == - HDAT_MIN_NUM_FOR_SHARING) - { - l_mcsSharingGrpIds[l_mcaInGrp] = - l_nxtSharingGroupId; - l_nxtSharingGroupId++; - } - } - } - - // TODO : RTC Story 159682 // Further CHTM support needs to be added which contains the trace // array for 24 cores @@ -1154,14 +1114,14 @@ errlHndl_t HdatMsVpd::hdatLoadMsData(uint32_t &o_size, uint32_t &o_count) hdatMsAddr_t l_hdatNhtmEndAddr; TARGETING::ATTR_PROC_NHTM_BAR_BASE_ADDR_type l_nhtmStartAddr = - l_pProcTarget->getAttr<TARGETING::ATTR_PROC_NHTM_BAR_BASE_ADDR>(); + l_pProcTarget->getAttr<TARGETING::ATTR_PROC_NHTM_BAR_BASE_ADDR>(); TARGETING::ATTR_PROC_NHTM_BAR_SIZE_type l_nhtmSize = l_pProcTarget->getAttr<TARGETING::ATTR_PROC_NHTM_BAR_SIZE>(); if( 0 != l_nhtmSize ) { l_hdatNhtmStartAddr.hi = - (l_nhtmStartAddr & 0xFFFFFFFF00000000ull) >> 32; + (l_nhtmStartAddr & 0xFFFFFFFF00000000ull) >> 32; l_hdatNhtmStartAddr.lo = l_nhtmStartAddr & 0x00000000FFFFFFFFull; l_hdatNhtmStartAddr.hi |= HDAT_REAL_ADDRESS_MASK; @@ -1185,433 +1145,1236 @@ errlHndl_t HdatMsVpd::hdatLoadMsData(uint32_t &o_size, uint32_t &o_count) l_nhtmSize); } + TARGETING::ATTR_PROC_MEM_BASES_type l_procMemBases = {0}; + assert(l_pProcTarget-> + tryGetAttr<TARGETING::ATTR_PROC_MEM_BASES>(l_procMemBases)); + + TARGETING::ATTR_PROC_MIRROR_BASES_type l_MirrorAddr = {0}; + assert(l_pProcTarget->tryGetAttr< + TARGETING::ATTR_PROC_MIRROR_BASES>(l_MirrorAddr)); + + TARGETING::ATTR_PROC_MIRROR_SIZES_type l_MirrorSize = {0}; + assert(l_pProcTarget->tryGetAttr< + TARGETING::ATTR_PROC_MIRROR_SIZES>(l_MirrorSize)); - TARGETING::PredicateCTM l_mcbistPredicate(TARGETING::CLASS_UNIT, + TARGETING::ATTR_PAYLOAD_IN_MIRROR_MEM_type l_payLoadMirrorMem = + l_pSysTarget->getAttr<TARGETING::ATTR_PAYLOAD_IN_MIRROR_MEM>(); + + if(l_model == TARGETING::MODEL_NIMBUS) + { + //Sharing count for each group + TARGETING::ATTR_MSS_MEM_MC_IN_GROUP_type l_mcaSharingCount + = {0}; + + //Group ID for each group, group id will be assigned only + //if the group is shared + TARGETING::ATTR_MSS_MEM_MC_IN_GROUP_type l_mcsSharingGrpIds + = {0}; + + //Size configured under each group + TARGETING::ATTR_PROC_MEM_SIZES_type l_procMemSizesBytes = {0}; + + assert(l_pProcTarget->tryGetAttr<TARGETING::ATTR_PROC_MEM_SIZES> + (l_procMemSizesBytes)); + + //For each MCA + TARGETING::PredicateCTM l_allMca(TARGETING::CLASS_UNIT, + TARGETING::TYPE_MCA); + TARGETING::PredicateHwas l_funcMca; + l_funcMca.functional(true); + TARGETING::PredicatePostfixExpr l_allFuncMca; + l_allFuncMca.push(&l_allMca).push(&l_funcMca).And(); + + TARGETING::TargetHandleList l_mcaList; + + TARGETING::targetService(). + getAssociated(l_mcaList, l_pProcTarget, + TARGETING::TargetService::CHILD, + TARGETING::TargetService::ALL, &l_allFuncMca); + + for(uint32_t l_mcaIdx = 0; l_mcaIdx<l_mcaList.size(); + ++l_mcaIdx) + { + uint32_t l_mcaInGrp = 0; + TARGETING::Target *l_pMcaTarget = + l_mcaList[l_mcaIdx]; + if(!hdatFindGroupForMc(l_pProcTarget, + l_pMcaTarget, + l_mcaInGrp)) + { + //Skip this MCA is not in any group + continue; + } + + //Increment sharing count if mem configured under group. + if(l_procMemSizesBytes[l_mcaInGrp] > 0) + { + l_mcaSharingCount[l_mcaInGrp]++; + + //Assign sharing group id only if shared + //And only when first instance of sharing is found + if(l_mcaSharingCount[l_mcaInGrp] == + HDAT_MIN_NUM_FOR_SHARING) + { + l_mcsSharingGrpIds[l_mcaInGrp] = + l_nxtSharingGroupId; + l_nxtSharingGroupId++; + } + } + } + + TARGETING::PredicateCTM l_mcbistPredicate(TARGETING::CLASS_UNIT, TARGETING::TYPE_MCBIST); - TARGETING::PredicatePostfixExpr l_presentMcbist; + TARGETING::PredicatePostfixExpr l_presentMcbist; l_presentMcbist.push(&l_mcbistPredicate). push(&l_predHwasFunc).And(); - TARGETING::TargetHandleList l_mcbistList; + TARGETING::TargetHandleList l_mcbistList; - // Find Associated MCBIST list - TARGETING::targetService().getAssociated(l_mcbistList, + // Find Associated MCBIST list + TARGETING::targetService().getAssociated(l_mcbistList, l_pProcTarget, TARGETING::TargetService::CHILD_BY_AFFINITY, TARGETING::TargetService::ALL, &l_presentMcbist); - //scan all mcbist in this proc - for(uint32_t l_mcbistIdx =0; - l_mcbistIdx < l_mcbistList.size(); - ++l_mcbistIdx) - { - TARGETING::Target *l_pMcbistTarget = l_mcbistList[l_mcbistIdx]; - - TARGETING::PredicateCTM l_mcsPredicate(TARGETING::CLASS_UNIT, - TARGETING::TYPE_MCS); + //scan all mcbist in this proc + for(uint32_t l_mcbistIdx =0; + l_mcbistIdx < l_mcbistList.size(); + ++l_mcbistIdx) + { + TARGETING::Target *l_pMcbistTarget = + l_mcbistList[l_mcbistIdx]; + + TARGETING::PredicateCTM l_mcsPredicate( + TARGETING::CLASS_UNIT, + TARGETING::TYPE_MCS); - TARGETING::PredicatePostfixExpr l_funcMcs; + TARGETING::PredicatePostfixExpr l_funcMcs; l_funcMcs.push(&l_mcsPredicate).push(&l_predHwasFunc).And(); - TARGETING::TargetHandleList l_mcsList; + TARGETING::TargetHandleList l_mcsList; - // Find Associated memory controllers - TARGETING::targetService().getAssociated(l_mcsList, + // Find Associated memory controllers + TARGETING::targetService().getAssociated(l_mcsList, l_pMcbistTarget, TARGETING::TargetService::CHILD, TARGETING::TargetService::ALL, &l_funcMcs); - uint32_t l_memBusFreq = getMemBusFreq(l_pMcbistTarget); + uint32_t l_memBusFreq = getMemBusFreq(l_pMcbistTarget); - //scan all mcs in this proc to get sharing counit - for(uint32_t l_mcsIdx = 0;l_mcsIdx<l_mcsList.size(); ++l_mcsIdx) - { - TARGETING::Target *l_pMcsTarget = l_mcsList[l_mcsIdx]; + //scan all mcs in this proc to get sharing counit + for(uint32_t l_mcsIdx = 0;l_mcsIdx<l_mcsList.size(); + ++l_mcsIdx) + { + TARGETING::Target *l_pMcsTarget = l_mcsList[l_mcsIdx]; - //for each MCA connected to this this MCS - TARGETING::PredicateCTM l_mcaPredicate( - TARGETING::CLASS_UNIT, TARGETING::TYPE_MCA); + //for each MCA connected to this this MCS + TARGETING::PredicateCTM l_mcaPredicate( + TARGETING::CLASS_UNIT, TARGETING::TYPE_MCA); - TARGETING::PredicateHwas l_predMca; - l_predMca.present(true); - TARGETING::PredicatePostfixExpr l_presentMca; - l_presentMca.push(&l_mcaPredicate).push(&l_predMca).And(); - TARGETING::TargetHandleList l_mcaList; + TARGETING::PredicateHwas l_predMca; + l_predMca.present(true); + TARGETING::PredicatePostfixExpr l_presentMca; + l_presentMca.push(&l_mcaPredicate). + push(&l_predMca).And(); + TARGETING::TargetHandleList l_mcaList; - // Get associated MCAs - TARGETING::targetService(). - getAssociated(l_mcaList, l_pMcsTarget, - TARGETING::TargetService::CHILD_BY_AFFINITY, - TARGETING::TargetService::ALL, &l_presentMca); + // Get associated MCAs + TARGETING::targetService(). + getAssociated(l_mcaList, l_pMcsTarget, + TARGETING::TargetService::CHILD_BY_AFFINITY, + TARGETING::TargetService::ALL, &l_presentMca); - for(uint32_t l_mcaIdx = 0; l_mcaIdx<l_mcaList.size(); - ++l_mcaIdx) - { - TARGETING::Target *l_pMcaTarget = - l_mcaList[l_mcaIdx]; + for(uint32_t l_mcaIdx = 0; l_mcaIdx<l_mcaList.size(); + ++l_mcaIdx) + { + TARGETING::Target *l_pMcaTarget = + l_mcaList[l_mcaIdx]; - //Group which this MCA is belonging - uint32_t l_mcaInGrp = 0; + //Group which this MCA is belonging + uint32_t l_mcaInGrp = 0; - if(!hdatFindGroupForMc(l_pProcTarget, - l_pMcaTarget, - l_mcaInGrp)) - { - HDAT_INF("No group found for MCA"); - //Skip this MCS is not under any group - continue; - } - uint32_t l_mcaFruId = 0; - hdatMemParentType l_parentType= HDAT_MEM_PARENT_CEC_FRU; - - std::list<hdatRamArea> l_areas; - l_areas.clear(); - uint32_t l_areaSizeInMB = 0; - bool l_areaFunctional = false; - uint32_t l_numDimms =0; - - l_err = hdatScanDimms(l_pMcaTarget, - l_pMcsTarget, - l_mcaFruId, - l_areas, - l_areaSizeInMB, - l_numDimms, - l_areaFunctional, - l_parentType); - - if(NULL != l_err) - { - HDAT_ERR("Error in calling Scan Dimms"); - break; - } + if(!hdatFindGroupForMc(l_pProcTarget, + l_pMcaTarget, + l_mcaInGrp)) + { + HDAT_INF("No group found for MCA"); + //Skip this MCS is not under any group + continue; + } + uint32_t l_mcaFruId = 0; + hdatMemParentType l_parentType = + HDAT_MEM_PARENT_CEC_FRU; + + std::list<hdatRamArea> l_areas; + l_areas.clear(); + uint32_t l_areaSizeInMB = 0; + bool l_areaFunctional = false; + uint32_t l_numDimms =0; + + l_err = hdatScanDimms(l_pMcaTarget, + l_pMcsTarget, + l_mcaFruId, + l_areas, + l_areaSizeInMB, + l_numDimms, + l_areaFunctional, + l_parentType); + + if(NULL != l_err) + { + HDAT_ERR("Error in calling Scan Dimms"); + break; + } - HDAT_INF("l_areaSizeInMB:0x%.8X l_numDimms:0x%.8X " - "l_areas.size():0x%.8X", l_areaSizeInMB, l_numDimms, - l_areas.size()); + HDAT_INF("l_areaSizeInMB:0x%.8X l_numDimms:0x%.8X " + "l_areas.size():0x%.8X", l_areaSizeInMB, + l_numDimms, l_areas.size()); - //Skip if no memory configured under this MCS - if(l_areaSizeInMB == 0) - { - continue; - } + //Skip if no memory configured under this MCS + if(l_areaSizeInMB == 0) + { + continue; + } - uint32_t l_maxMemBlocks = 0; - l_err = + uint32_t l_maxMemBlocks = 0; + l_err = hdatGetMaxMemoryBlocks(l_pMcsTarget,l_maxMemBlocks); - if(NULL != l_err) - { - HDAT_ERR("Error error in get max blocks"); - break; - } + if(NULL != l_err) + { + HDAT_ERR("Error error in get max blocks"); + break; + } - TARGETING::ATTR_SLCA_RID_type l_procRid = + TARGETING::ATTR_SLCA_RID_type l_procRid = l_pProcTarget->getAttr<TARGETING::ATTR_SLCA_RID>(); - TARGETING::ATTR_SLCA_INDEX_type l_procSlcaIndex = - l_pProcTarget->getAttr<TARGETING::ATTR_SLCA_INDEX>(); - + TARGETING::ATTR_SLCA_INDEX_type l_procSlcaIndex = + l_pProcTarget->getAttr + <TARGETING::ATTR_SLCA_INDEX>(); - l_err = addMsAreaFru(l_procRid, - l_procSlcaIndex, - l_pProcTarget, - l_index, - l_numDimms, - MAX_CHIP_EC_CNT_PER_MSAREA, - l_maxMemBlocks); + l_err = addMsAreaFru(l_procRid, + l_procSlcaIndex, + l_pProcTarget, + l_index, + l_numDimms, + MAX_CHIP_EC_CNT_PER_MSAREA, + l_maxMemBlocks); - if(NULL != l_err) - { - HDAT_ERR("Error adding MSArea %d" - "Number of Dimms: %d Max Blocks: %d", - l_index, - l_numDimms,l_maxMemBlocks); - break; - } + if(NULL != l_err) + { + HDAT_ERR("Error adding MSArea %d" + "Number of Dimms: %d Max Blocks: %d", + l_index, + l_numDimms,l_maxMemBlocks); + break; + } - uint32_t l_memStatus = 0; - //If group is shared with more than one area - if(l_mcaSharingCount[l_mcaInGrp] >= - HDAT_MIN_NUM_FOR_SHARING) - { - l_memStatus = HDAT_MEM_SHARED; - setMsAreaInterleavedId(l_index, - l_mcsSharingGrpIds[l_mcaInGrp]); - } + uint32_t l_memStatus = 0; + //If group is shared with more than one area + if(l_mcaSharingCount[l_mcaInGrp] >= + HDAT_MIN_NUM_FOR_SHARING) + { + l_memStatus = HDAT_MEM_SHARED; + setMsAreaInterleavedId(l_index, + l_mcsSharingGrpIds[l_mcaInGrp]); + } - setMsAreaType(l_index,l_parentType); - setMsAreaSize(l_index,l_areaSizeInMB); + setMsAreaType(l_index,l_parentType); + setMsAreaSize(l_index,l_areaSizeInMB); - iv_maxSize.hdatTotSize += l_areaSizeInMB; + iv_maxSize.hdatTotSize += l_areaSizeInMB; - l_memStatus |= l_areaFunctional ? - (HDAT_MEM_INSTALLED | HDAT_MEM_FUNCTIONAL) : - HDAT_MEM_INSTALLED; + l_memStatus |= l_areaFunctional ? + (HDAT_MEM_INSTALLED | HDAT_MEM_FUNCTIONAL) : + HDAT_MEM_INSTALLED; - setMsAreaStat(l_index, l_memStatus); + setMsAreaStat(l_index, l_memStatus); - //Add MCS ec level - uint32_t l_mcsEcLevel = 0; - uint32_t l_mcsChipId = 0; - l_err = hdatGetIdEc(l_pMcsTarget, - l_mcsEcLevel, - l_mcsChipId); - if(NULL != l_err) - { - HDAT_ERR("Error in getting MCS ID " + //Add MCS ec level + uint32_t l_mcsEcLevel = 0; + uint32_t l_mcsChipId = 0; + l_err = hdatGetIdEc(l_pMcsTarget, + l_mcsEcLevel, + l_mcsChipId); + if(NULL != l_err) + { + HDAT_ERR("Error in getting MCS ID " "and EC HUID:[0x%08X]", l_pMcsTarget->getAttr<TARGETING::ATTR_HUID>()); - break; - } + break; + } - l_err = addEcEntry(l_index, - l_mcsChipId, - l_mcsEcLevel); - if(NULL != l_err) - { - HDAT_ERR("Error in adding" + l_err = addEcEntry(l_index, + l_mcsChipId, + l_mcsEcLevel); + if(NULL != l_err) + { + HDAT_ERR("Error in adding" " ID[0x%08X] and EC[0x%08X] to ms area" " HUID:[0x%08X]",l_mcsChipId, l_mcsEcLevel, l_pMcsTarget->getAttr<TARGETING::ATTR_HUID>()); - break; - } + break; + } - // Need to get i2c Master data correctly - std::vector<hdatI2cData_t> l_i2cDevEntries; + // Need to get i2c Master data correctly + std::vector<hdatI2cData_t> l_i2cDevEntries; - TARGETING::PredicateCTM l_membufPredicate( - TARGETING::CLASS_CHIP, TARGETING::TYPE_MEMBUF); + TARGETING::PredicateCTM l_membufPredicate( + TARGETING::CLASS_CHIP, TARGETING::TYPE_MEMBUF); - TARGETING::PredicatePostfixExpr l_presentMemBuf; - l_presentMemBuf.push(&l_membufPredicate). + TARGETING::PredicatePostfixExpr l_presentMemBuf; + l_presentMemBuf.push(&l_membufPredicate). push(&l_predHwasPresent).And(); - TARGETING::TargetHandleList l_membufList; + TARGETING::TargetHandleList l_membufList; - // Find Associated membuf - TARGETING::targetService().getAssociated(l_membufList, - l_pMcsTarget, - TARGETING::TargetService::CHILD_BY_AFFINITY, - TARGETING::TargetService::ALL, - &l_presentMemBuf); - //Skip is there is no Membuf attached to this MCS - if(l_membufList.size() > 0) - { - TARGETING::Target *l_pMembufTarget = - l_membufList[0]; - if (l_pMembufTarget != NULL) + // Find Associated membuf + TARGETING::targetService().getAssociated( + l_membufList, + l_pMcsTarget, + TARGETING::TargetService::CHILD_BY_AFFINITY, + TARGETING::TargetService::ALL, + &l_presentMemBuf); + //Skip is there is no Membuf attached to this MCS + if(l_membufList.size() > 0) { - hdatGetI2cDeviceInfo(l_pMembufTarget, - l_i2cDevEntries); + TARGETING::Target *l_pMembufTarget = + l_membufList[0]; + if (l_pMembufTarget != NULL) + { + hdatGetI2cDeviceInfo(l_pMembufTarget, + l_model, + l_i2cDevEntries); + } } - } - setMsaI2cInfo(l_index, l_i2cDevEntries); + setMsaI2cInfo(l_index, l_i2cDevEntries); - std::list<hdatRamArea>::iterator l_area = - l_areas.begin(); + std::list<hdatRamArea>::iterator l_area = + l_areas.begin(); - for (uint32_t l_ramId = 0; - l_area != l_areas.end(); - ++l_ramId, ++l_area) - { - uint32_t l_status = (l_area)->ivFunctional ? + for (uint32_t l_ramId = 0; + l_area != l_areas.end(); + ++l_ramId, ++l_area) + { + uint32_t l_status = (l_area)->ivFunctional ? (HDAT_RAM_INSTALLED | HDAT_RAM_FUNCTIONAL) : HDAT_RAM_INSTALLED; - TARGETING::Target *l_pDimmTarget = - TARGETING::Target::getTargetFromHuid(l_area->ivHuid); - - TARGETING::ATTR_SLCA_RID_type l_dimmRid = - l_pDimmTarget->getAttr<TARGETING::ATTR_SLCA_RID>(); - - TARGETING::ATTR_SLCA_INDEX_type l_dimmSlcaIndex = - l_pDimmTarget->getAttr<TARGETING::ATTR_SLCA_INDEX>(); - - uint32_t l_dimmId = - 1 << (31 - (l_pDimmTarget->getAttr<TARGETING::ATTR_FAPI_POS>() % MAX_DIMMS_PER_MCBIST)); - l_err = addRamFru(l_index, - l_pDimmTarget, - l_dimmRid, - l_dimmSlcaIndex, - l_ramId, - l_status, - (l_area)->ivSize, - l_dimmId, - l_memBusFreq); - - if (l_err) // Failed to add ram fru information - { - HDAT_ERR("Error in adding RAM FRU" - "Index:%d Rid:[0x%08X] status:[0x%08X]" - "Size:[0x%08X] RamID:[0x%08X]", - l_index,(l_area)->ivHuid, - l_status,(l_area)->ivSize,l_ramId); - ERRORLOG::errlCommit(l_err,HDAT_COMP_ID); - - delete l_err; - l_err = NULL; - continue; - } - }//end of RAM list + TARGETING::Target *l_pDimmTarget = + TARGETING::Target::getTargetFromHuid( + l_area->ivHuid); + + TARGETING::ATTR_SLCA_RID_type l_dimmRid = + l_pDimmTarget->getAttr + <TARGETING::ATTR_SLCA_RID>(); + + TARGETING::ATTR_SLCA_INDEX_type l_dimmSlcaIndex= + l_pDimmTarget->getAttr + <TARGETING::ATTR_SLCA_INDEX>(); + + uint32_t l_dimmId = + 1 << (31 - (l_pDimmTarget->getAttr + <TARGETING::ATTR_FAPI_POS>() % + MAX_DIMMS_PER_MCBIST)); + l_err = addRamFru(l_index, + l_pDimmTarget, + l_dimmRid, + l_dimmSlcaIndex, + l_ramId, + l_status, + (l_area)->ivSize, + l_dimmId, + l_memBusFreq); + + if (l_err) // Failed to add ram fru information + { + HDAT_ERR("Error in adding RAM FRU" + "Index:%d Rid:[0x%08X] status:[0x%08X]" + "Size:[0x%08X] RamID:[0x%08X]", + l_index,(l_area)->ivHuid, + l_status,(l_area)->ivSize,l_ramId); + ERRORLOG::errlCommit(l_err,HDAT_COMP_ID); + + delete l_err; + l_err = NULL; + continue; + } + }//end of RAM list - l_addr_range.hi = (l_procMemBases[l_mcaInGrp] & + l_addr_range.hi = (l_procMemBases[l_mcaInGrp] & 0xFFFFFFFF00000000ull) >> 32; - l_addr_range.lo = l_procMemBases[l_mcaInGrp] & + l_addr_range.lo = l_procMemBases[l_mcaInGrp] & 0x00000000FFFFFFFFull; - l_end = l_addr_range; + l_end = l_addr_range; - //Update the range - l_end.hi += (l_procMemSizesBytes[l_mcaInGrp] & + //Update the range + l_end.hi += (l_procMemSizesBytes[l_mcaInGrp] & 0xFFFFFFFF00000000ull) >> 32; - l_end.lo += l_procMemSizesBytes[l_mcaInGrp] & + l_end.lo += l_procMemSizesBytes[l_mcaInGrp] & 0x00000000FFFFFFFFull; - HDAT_INF("MCS:0x%08X l_addr_range:0x%08X 0x%08X" - " l_end:0x%08X 0x%08X", - l_pMcsTarget->getAttr<TARGETING::ATTR_HUID>(), - l_addr_range.hi, l_addr_range.lo, - l_end.hi,l_end.lo); - - uint64_t l_hdatMirrorAddr_x = 0x0ull; - uint64_t l_hdatMirrorAddr = 0x0ull; - uint32_t l_hdatMemcntrlID = 0x0 ; - uint8_t l_hdatMirrorAlogrithm = 0xFF; - bool l_rangeIsMirrorable = false; - - TARGETING::ATTR_PROC_MIRROR_BASES_type - l_MirrorAddr = {0}; - assert(l_pProcTarget->tryGetAttr< - TARGETING::ATTR_PROC_MIRROR_BASES>(l_MirrorAddr)); - - TARGETING::ATTR_PROC_MIRROR_SIZES_type - l_MirrorSize = {0}; - assert(l_pProcTarget->tryGetAttr< - TARGETING::ATTR_PROC_MIRROR_SIZES>(l_MirrorSize)); - - uint64_t l_startAddr = + HDAT_INF("MCS:0x%08X l_addr_range:0x%08X 0x%08X" + " l_end:0x%08X 0x%08X", + l_pMcsTarget->getAttr<TARGETING::ATTR_HUID>(), + l_addr_range.hi, l_addr_range.lo, + l_end.hi,l_end.lo); + + uint64_t l_hdatMirrorAddr_x = 0x0ull; + uint64_t l_hdatMirrorAddr = 0x0ull; + uint32_t l_hdatMemcntrlID = 0x0 ; + uint8_t l_hdatMirrorAlogrithm = 0xFF; + bool l_rangeIsMirrorable = false; + + //Calculate the mirror address and related data + uint64_t l_startAddr = (((uint64_t)(l_addr_range.hi) << 32 ) | (uint64_t)(l_addr_range.lo)); - l_hdatMirrorAddr_x = - (l_startAddr / 2) + l_mirrorBaseAddress_x; - - TARGETING::ATTR_PAYLOAD_IN_MIRROR_MEM_type - l_payLoadMirrorMem = - l_pSysTarget->getAttr< - TARGETING::ATTR_PAYLOAD_IN_MIRROR_MEM>(); + l_hdatMirrorAddr_x = + (l_startAddr / 2) + l_mirrorBaseAddress_x; - HDAT_INF( - "Start add : 0x%016llX MirrorBase : 0x%016llX" - " MirrorAddr : 0x%016llX PayLoadMirrorMem : 0x%X", - l_startAddr, l_mirrorBaseAddress_x, - l_hdatMirrorAddr_x, l_payLoadMirrorMem); + HDAT_INF( + "Start add : 0x%016llX MirrorBase : 0x%016llX" + " MirrorAddr : 0x%016llX PayLoadMirrorMem : 0x%X", + l_startAddr, l_mirrorBaseAddress_x, + l_hdatMirrorAddr_x, l_payLoadMirrorMem); - if ( 0 != l_payLoadMirrorMem ) - { - for ( int idx=0 ; idx < - (int)(sizeof(TARGETING::ATTR_PROC_MIRROR_SIZES_type) - / sizeof(uint64_t)) ; idx++ ) + if ( 0 != l_payLoadMirrorMem ) { - HDAT_INF("Mirror size : 0x%016llX" - " MirrorAddr[idx] : 0x%016llX" - " hdatMirrorAddr_x : 0x%016llX", - l_MirrorSize[idx], l_MirrorAddr[idx], - l_hdatMirrorAddr_x); + for ( int idx=0 ; idx < + (int) + (sizeof(TARGETING::ATTR_PROC_MIRROR_SIZES_type) + / sizeof(uint64_t)) ; idx++ ) + { + HDAT_INF("Mirror size : 0x%016llX" + " MirrorAddr : 0x%016llX" + " hdatMirrorAddr_x : 0x%016llX", + l_MirrorSize[idx], l_MirrorAddr[idx], + l_hdatMirrorAddr_x); - if( (0 != l_MirrorSize[idx]) && + if( (0 != l_MirrorSize[idx]) && (l_MirrorAddr[idx] == l_hdatMirrorAddr_x) ) - { - l_rangeIsMirrorable = true; - l_hdatMirrorAddr = l_MirrorAddr[idx] + { + l_rangeIsMirrorable = true; + l_hdatMirrorAddr = l_MirrorAddr[idx] | HDAT_REAL_ADDRESS_MASK64; - break; + break; + } } } - } - if(l_pProcTarget->getAttr<TARGETING::ATTR_MODEL>() == TARGETING::MODEL_NIMBUS) - { + // Set the memory controller ID - l_hdatMemcntrlID |= 1 << (31 - l_pMcbistTarget->getAttr<TARGETING::ATTR_CHIP_UNIT>()); - l_hdatMemcntrlID |= 1 << (31 - (l_pMcsTarget->getAttr<TARGETING::ATTR_CHIP_UNIT>() + 4)); - l_hdatMemcntrlID |= 1 << (31 - (l_pMcaTarget->getAttr<TARGETING::ATTR_CHIP_UNIT>() + 8)); - } - else if(l_pProcTarget->getAttr<TARGETING::ATTR_MODEL>() == TARGETING::MODEL_CUMULUS) - { - //TODO : MEmory controller ID for cumulus need to be defined. - HDAT_INF("Memory controller ID : 0 since this is Cumulus proc"); - } - l_err = addMsAreaAddr(l_index, - l_addr_range, - l_end, - l_procChipId, - l_rangeIsMirrorable, - l_hdatMirrorAlogrithm, - l_hdatMirrorAddr, - l_hdatMemcntrlID); - if(NULL != l_err) + l_hdatMemcntrlID |= + 1 << (31 - l_pMcbistTarget->getAttr + <TARGETING::ATTR_CHIP_UNIT>()); + l_hdatMemcntrlID |= + 1 << (31 - (l_pMcsTarget->getAttr + <TARGETING::ATTR_CHIP_UNIT>() + 4)); + l_hdatMemcntrlID |= + 1 << (31 - (l_pMcaTarget->getAttr + <TARGETING::ATTR_CHIP_UNIT>() + 8)); + + l_err = addMsAreaAddr(l_index, + l_addr_range, + l_end, + l_procChipId, + l_rangeIsMirrorable, + l_hdatMirrorAlogrithm, + l_hdatMirrorAddr, + l_hdatMemcntrlID); + if(NULL != l_err) + { + HDAT_ERR("Error in adding addMsAreaAddr" + " to ms area index[%d]", + l_index); + break; + } + + // TODO : RTC Story 159682 + // Further CHTM support needs to be added which + // contains the trace array for 24 cores + // Reinitializing the NHTM size + + // Don't re-init NHTM size -- only one HTM region + // per proc + uint64_t l_end_hi = l_end.hi; + uint64_t l_end_lo = l_end.lo; + uint64_t l_end_addr = + ((l_end_hi << 32 ) | l_end_lo); + + + uint64_t l_addr_range_hi = l_addr_range.hi; + uint64_t l_addr_range_lo = l_addr_range.lo; + uint64_t l_start_addr = + ((l_addr_range_hi << 32 )| l_addr_range_lo); + + uint64_t l_size_bytes = ((uint64_t)l_areaSizeInMB) * + l_mcaSharingCount[l_mcaInGrp] * 1024 * 1024; + + if((0 != l_nhtmSize) && + (l_size_bytes != (l_end_addr - l_start_addr))) + { + HDAT_INF("NHTM Bar size = 0x%016llX " + " MS area size = 0x%016llX" + " l_end_addr = 0x%016llX" + " l_start_addr = 0x%016llX", + l_nhtmSize,l_size_bytes, l_end_addr, + l_start_addr); + + l_addr_range.lo = l_hdatNhtmStartAddr.lo; + l_addr_range.hi = l_hdatNhtmStartAddr.hi; + + l_end.lo = l_hdatNhtmEndAddr.lo; + l_end.hi = l_hdatNhtmEndAddr.hi; + + l_err = addMsAreaAddr(l_index, + l_addr_range, + l_end, + l_procChipId, + false, 0, 0); + if(NULL != l_err) + { + HDAT_ERR("Error in adding " + " addMsAreaAddr to ms area index[%d]", + l_index); + break; + } + l_nhtmSize=0; //only add 1 entry + } + l_addr_range = l_end; + + auto l_smfStartAddr = l_pProcTarget-> + getAttr<TARGETING::ATTR_PROC_SMF_BAR_BASE_ADDR>(); + auto l_smfSize = l_pProcTarget-> + getAttr<TARGETING::ATTR_PROC_SMF_BAR_SIZE>(); + + if(l_smfSize && !l_smfAdded) + { + hdatMsAddr_t l_hdatSmfStartAddr{}; + hdatMsAddr_t l_hdatSmfEndAddr{}; + l_hdatSmfStartAddr.hi = + (l_smfStartAddr & 0xFFFFFFFF00000000ull) >> 32; + l_hdatSmfStartAddr.lo = + l_smfStartAddr & 0x00000000FFFFFFFFull; + l_hdatSmfStartAddr.hi |= HDAT_REAL_ADDRESS_MASK; + + l_hdatSmfEndAddr.hi = + ((l_smfStartAddr + l_smfSize) & + 0xFFFFFFFF00000000ull) >>32; + l_hdatSmfEndAddr.lo = + (l_smfStartAddr + l_smfSize) & + 0x00000000FFFFFFFFull; + l_hdatSmfEndAddr.hi |= HDAT_REAL_ADDRESS_MASK; + + l_err = addMsAreaAddr(l_index, + l_hdatSmfStartAddr, + l_hdatSmfEndAddr, + l_procChipId, + false, //rangeIsMirrorable + 0, // i_mirroringAlgorithm + 0, // i_startMirrAddr + l_hdatMemcntrlID, + true); // i_hdatsmf + l_smfAdded = true; + } + + if(l_err) + { + HDAT_ERR("Could not add SMF memory range to " + "HDAT at index[%d]", l_index); + break; + } + else + { + HDAT_INF("Added SMF memory range to HDAT at " + "index[%d]; start addr: 0x%08x; end addr: 0x%08x" + "; size: 0x%08x", + l_smfStartAddr, + l_smfStartAddr + l_smfSize, + l_smfSize); + } + + l_index++; + } //end of mca list + if(l_err) { - HDAT_ERR("Error in adding addMsAreaAddr" - " to ms area index[%d]", - l_index); break; } + } //end of MCS list + if(l_err) + { + break; + } + } //end of MCBIST list + } + else //if model is Axone + { + //Sharing count for each group + TARGETING::ATTR_MSS_MEM_MC_IN_GROUP_type l_mccSharingCount + = {0}; + + //Size configured under each group + TARGETING::ATTR_PROC_MEM_SIZES_type l_procMemSizesBytes = {0}; + + assert(l_pProcTarget->tryGetAttr<TARGETING::ATTR_PROC_MEM_SIZES> + (l_procMemSizesBytes)); + + //For each MCC + TARGETING::PredicateCTM l_allMcc(TARGETING::CLASS_UNIT, + TARGETING::TYPE_MCC); + TARGETING::PredicateHwas l_funcMcc; + l_funcMcc.functional(true); + TARGETING::PredicatePostfixExpr l_allFuncMcc; + l_allFuncMcc.push(&l_allMcc).push(&l_funcMcc).And(); + + TARGETING::TargetHandleList l_mccList; + + TARGETING::targetService(). + getAssociated(l_mccList, l_pProcTarget, + TARGETING::TargetService::CHILD, + TARGETING::TargetService::ALL, &l_allFuncMcc); + + for(uint32_t l_mccIdx = 0; l_mccIdx<l_mccList.size(); + ++l_mccIdx) + { + uint32_t l_mccInGrp = 0; + + TARGETING::Target *l_pMccTarget = + l_mccList[l_mccIdx]; + if(!hdatFindGroupForMcc(l_pProcTarget, + l_pMccTarget, + l_mccInGrp)) + { + //Skip this MCC is not in any group + continue; + } + + //Increment sharing count if mem configured under group. + if(l_procMemSizesBytes[l_mccInGrp] > 0) + { + l_mccSharingCount[l_mccInGrp]++; + } + } + + TARGETING::PredicateCTM l_mcPredicate(TARGETING::CLASS_UNIT, + TARGETING::TYPE_MC); + + TARGETING::PredicatePostfixExpr l_presentMc; + l_presentMc.push(&l_mcPredicate). + push(&l_predHwasFunc).And(); + + TARGETING::TargetHandleList l_mcList; + + // Find Associated MC list + TARGETING::targetService().getAssociated(l_mcList, + l_pProcTarget, + TARGETING::TargetService::CHILD_BY_AFFINITY, + TARGETING::TargetService::ALL, + &l_presentMc); - // TODO : RTC Story 159682 - // Further CHTM support needs to be added which contains - // the trace array for 24 cores - // Reinitializing the NHTM size + //scan all mc in this proc + for(uint32_t l_mcIdx =0; + l_mcIdx < l_mcList.size(); + ++l_mcIdx) + { + TARGETING::Target *l_pMcTarget = l_mcList[l_mcIdx]; - //Don't re-init NHTM size -- only one HTM region per proc - uint64_t l_end_hi = l_end.hi; - uint64_t l_end_lo = l_end.lo; - uint64_t l_end_addr = ((l_end_hi << 32 ) | l_end_lo); + TARGETING::PredicateCTM l_miPredicate( + TARGETING::CLASS_UNIT, + TARGETING::TYPE_MI); + TARGETING::PredicatePostfixExpr l_funcMi; + l_funcMi.push(&l_miPredicate).push(&l_predHwasFunc).And(); - uint64_t l_addr_range_hi = l_addr_range.hi; - uint64_t l_addr_range_lo = l_addr_range.lo; - uint64_t l_start_addr =((l_addr_range_hi << 32 )| l_addr_range_lo); + TARGETING::TargetHandleList l_miList; - uint64_t l_size_bytes = ((uint64_t)l_areaSizeInMB) * l_mcaSharingCount[l_mcaInGrp] * 1024 * 1024; + // Find Associated mi list + TARGETING::targetService().getAssociated(l_miList, + l_pMcTarget, + TARGETING::TargetService::CHILD, + TARGETING::TargetService::ALL, + &l_funcMi); - if((0 != l_nhtmSize) && - (l_size_bytes != (l_end_addr - l_start_addr))) + //for each MI connected to this this MC + for(uint32_t l_miIdx = 0;l_miIdx<l_miList.size(); + ++l_miIdx) + { + TARGETING::Target *l_pMiTarget = l_miList[l_miIdx]; + + //for each MCC connected to this this MI + TARGETING::PredicateCTM l_mccPredicate( + TARGETING::CLASS_UNIT, TARGETING::TYPE_MCC); + + TARGETING::PredicateHwas l_predMcc; + l_predMcc.present(true); + TARGETING::PredicatePostfixExpr l_presentMcc; + l_presentMcc.push(&l_mccPredicate). + push(&l_predMcc).And(); + TARGETING::TargetHandleList l_mccList; + + // Get associated MCCs + TARGETING::targetService(). + getAssociated(l_mccList, l_pMiTarget, + TARGETING::TargetService::CHILD_BY_AFFINITY, + TARGETING::TargetService::ALL, &l_presentMcc); + + for(uint32_t l_mccIdx = 0; l_mccIdx<l_mccList.size(); + ++l_mccIdx) { - HDAT_INF("NHTM Bar size = 0x%016llX " - " MS area size = 0x%016llX" - " l_end_addr = 0x%016llX" - " l_start_addr = 0x%016llX", - l_nhtmSize,l_size_bytes, l_end_addr, - l_start_addr); + TARGETING::Target *l_pMccTarget = + l_mccList[l_mccIdx]; - l_addr_range.lo = l_hdatNhtmStartAddr.lo; - l_addr_range.hi = l_hdatNhtmStartAddr.hi; + //Group which this MCC is belonging + uint32_t l_mccInGrp = 0; - l_end.lo = l_hdatNhtmEndAddr.lo; - l_end.hi = l_hdatNhtmEndAddr.hi; + if(!hdatFindGroupForMcc(l_pProcTarget, + l_pMccTarget, + l_mccInGrp)) + { + HDAT_INF("No group found for MCC"); + //Skip this MCC as it is not under any group + continue; + } - l_err = addMsAreaAddr(l_index, - l_addr_range, - l_end, - l_procChipId, - false, 0, 0); - if(NULL != l_err) + //for each OMI connected to this this MCC + TARGETING::PredicateCTM l_omiPredicate( + TARGETING::CLASS_UNIT, TARGETING::TYPE_OMI); + + TARGETING::PredicateHwas l_predOmi; + l_predOmi.present(true); + TARGETING::PredicatePostfixExpr l_presentOmi; + l_presentOmi.push(&l_omiPredicate). + push(&l_predOmi).And(); + TARGETING::TargetHandleList l_omiList; + + // Get associated OMIs + TARGETING::targetService(). + getAssociated(l_omiList, l_pMccTarget, + TARGETING::TargetService::CHILD_BY_AFFINITY, + TARGETING::TargetService::ALL, &l_presentOmi); + + for(uint32_t l_omiIdx = 0; + l_omiIdx<l_omiList.size(); + ++l_omiIdx) + { + TARGETING::Target *l_pOmiTarget = + l_omiList[l_omiIdx]; + + //for each OCMB CHIP connected to this this OMI + TARGETING::PredicateCTM l_ocmbPredicate( + TARGETING::CLASS_CHIP, + TARGETING::TYPE_OCMB_CHIP); + + TARGETING::PredicateHwas l_predOcmb; + l_predOcmb.present(true); + TARGETING::PredicatePostfixExpr l_presentOcmb; + l_presentOcmb.push(&l_ocmbPredicate). + push(&l_predOcmb).And(); + TARGETING::TargetHandleList l_ocmbList; + + // Get associated OCMB CHIP's + TARGETING::targetService(). + getAssociated(l_ocmbList, l_pOmiTarget, + TARGETING::TargetService::CHILD_BY_AFFINITY, + TARGETING::TargetService::ALL, &l_presentOcmb); + + for(uint32_t l_ocmbIdx = 0; + l_ocmbIdx<l_ocmbList.size(); + ++l_ocmbIdx) + { + TARGETING::Target *l_pOcmbTarget = + l_ocmbList[l_ocmbIdx]; + + // Swift uses a DDIMM. It is a single FRU + // that includes 1 OCMB chip and some dram + hdatMemParentType l_parentType = + HDAT_MEM_PARENT_RISER; + + std::list<hdatRamArea> l_areas; + l_areas.clear(); + uint32_t l_areaSizeInMB = 0; + bool l_areaFunctional = false; + uint32_t l_numDimms =0; + + l_err = hdatScanDimmsAxone(l_pOcmbTarget, + l_areas, + l_areaSizeInMB, + l_numDimms, + l_areaFunctional, + l_parentType); + if(NULL != l_err) + { + HDAT_ERR("Error in calling Scan Dimms"); + break; + } + + HDAT_INF("l_areaSizeInMB:0x%.8X " + "l_numDimms:0x%.8X " + "l_areas.size():0x%.8X", l_areaSizeInMB, + l_numDimms, l_areas.size()); + + // Skip if no memory configured under + // OCMB_CHIP + if(l_areaSizeInMB == 0) + { + continue; + } + + uint32_t l_maxMemBlocks = 0; + l_err = hdatGetMaxMemoryBlocks + (l_pOcmbTarget,l_maxMemBlocks); + if(NULL != l_err) + { + HDAT_ERR("Error to get max blocks"); + break; + } + + TARGETING::ATTR_SLCA_RID_type l_procRid = + l_pProcTarget->getAttr + <TARGETING::ATTR_SLCA_RID>(); + + TARGETING::ATTR_SLCA_INDEX_type + l_procSlcaIndex = l_pProcTarget->getAttr + <TARGETING::ATTR_SLCA_INDEX>(); + + l_err = addMsAreaFru(l_procRid, + l_procSlcaIndex, + l_pProcTarget, + l_index, + l_numDimms, + MAX_CHIP_EC_CNT_PER_MSAREA, + l_maxMemBlocks); + + if(NULL != l_err) + { + HDAT_ERR("Error adding MSArea %d" + "Number of Dimms: %d " + "Max Blocks: %d", + l_index, + l_numDimms,l_maxMemBlocks); + break; + } + + uint32_t l_memStatus = 0; + + //If group is shared with more than one area + if(l_mccSharingCount[l_mccInGrp] >= + HDAT_MIN_NUM_FOR_SHARING) + { + l_memStatus = HDAT_MEM_SHARED; + setMsAreaInterleavedId(l_index, + l_mccInGrp); + } + //The memory channel is defined as a single + // MCC, and all of the memory on that + // channel is part of a single address + // space. That means that both OCMBs on + // the same MCC share an address space. + // While this isn't the same mechanism as + // true interleaving, it looks the same to + // the code consuming HDAT, so we need to + // set the sharing flags appropriately. + else if( l_omiList.size() > 1 ) + { + l_memStatus = HDAT_MEM_SHARED; + setMsAreaInterleavedId(l_index, + l_mccInGrp); + } + + setMsAreaType(l_index,l_parentType); + setMsAreaSize(l_index,l_areaSizeInMB); + + iv_maxSize.hdatTotSize += l_areaSizeInMB; + + l_memStatus |= l_areaFunctional ? + (HDAT_MEM_INSTALLED | + HDAT_MEM_FUNCTIONAL) : + HDAT_MEM_INSTALLED; + + setMsAreaStat(l_index, l_memStatus); + + //Add OMI ec level + uint32_t l_omiEcLevel = 0; + uint32_t l_omiChipId = 0; + l_err = hdatGetIdEc(l_pOmiTarget, + l_omiEcLevel, + l_omiChipId); + if(NULL != l_err) + { + HDAT_ERR("Error in getting OMI ID " + "and EC HUID:[0x%08X]", + l_pOmiTarget->getAttr + <TARGETING::ATTR_HUID>()); + break; + } + + l_err = addEcEntry(l_index, + l_omiChipId, + l_omiEcLevel); + if(NULL != l_err) + { + HDAT_ERR("Error in adding" + " ID[0x%08X] and " + "EC[0x%08X] to ms area" + " HUID:[0x%08X]",l_omiChipId, + l_omiEcLevel, + l_pOmiTarget->getAttr + <TARGETING::ATTR_HUID>()); + break; + } + + // Get the i2c Master data + std::vector<hdatI2cData_t> l_i2cDevEntries; + + if (l_pOcmbTarget != NULL) + { + hdatGetI2cDeviceInfo(l_pOcmbTarget, + l_model, + l_i2cDevEntries); + } + + setMsaI2cInfo(l_index, l_i2cDevEntries); + + //for each mem-port connected to this this + //ocmb_chip + TARGETING::PredicateCTM l_allMemPort( + TARGETING::CLASS_UNIT, + TARGETING::TYPE_MEM_PORT); + TARGETING::PredicateHwas l_funcMemPort; + l_funcMemPort.functional(true); + TARGETING::PredicatePostfixExpr + l_allFuncMemPort; + l_allFuncMemPort.push(&l_allMemPort). + push(&l_funcMemPort).And(); + + TARGETING::TargetHandleList l_memPortList; + + TARGETING::targetService(). + getAssociated(l_memPortList, + l_pOcmbTarget, + TARGETING::TargetService::CHILD, + TARGETING::TargetService::ALL, + &l_allFuncMemPort); + + TARGETING::Target *l_pmemPortTarget; + + l_pmemPortTarget = l_memPortList[0]; + + uint32_t l_memBusFreq = 0; + l_memBusFreq = + getMemBusFreqAxone(l_pmemPortTarget); + + std::list<hdatRamArea>::iterator l_area = + l_areas.begin(); + + for (uint32_t l_ramId = 0; + l_area != l_areas.end(); + ++l_ramId, ++l_area) + { + uint32_t l_status = + (l_area)->ivFunctional ? + (HDAT_RAM_INSTALLED | + HDAT_RAM_FUNCTIONAL) + : HDAT_RAM_INSTALLED; + + TARGETING::Target *l_pDimmTarget = + TARGETING::Target::getTargetFromHuid( + l_area->ivHuid); + + TARGETING::ATTR_SLCA_RID_type l_dimmRid + = 0; + TARGETING::ATTR_SLCA_INDEX_type + l_dimmSlcaIndex = 0; + l_dimmRid + = l_pDimmTarget->getAttr + <TARGETING::ATTR_SLCA_RID>(); + + l_dimmSlcaIndex = + l_pDimmTarget->getAttr + <TARGETING::ATTR_SLCA_INDEX>(); + + uint32_t l_dimmId = 0; + l_dimmId |= + 1 << (31 - l_pOmiTarget->getAttr + <TARGETING::ATTR_CHIP_UNIT>()); + l_dimmId |= + 1 << (31 - (l_pmemPortTarget->getAttr + <TARGETING::ATTR_CHIP_UNIT>()+16)); + l_dimmId |= + 1 << (31 - (l_pDimmTarget->getAttr + <TARGETING::ATTR_REL_POS>()+20)); + + l_err = addRamFru(l_index, + l_pDimmTarget, + l_dimmRid, + l_dimmSlcaIndex, + l_ramId, + l_status, + (l_area)->ivSize, + l_dimmId, + l_memBusFreq); + + if (l_err) // Failed to add ram fru + { + HDAT_ERR("Error in adding RAM FRU" + "Index:%d Rid:[0x%08X] " + "status:[0x%08X]" + "Size:[0x%08X] RamID:[0x%08X]", + l_index,(l_area)->ivHuid, + l_status,(l_area)->ivSize, + l_ramId); + ERRORLOG::errlCommit(l_err, + HDAT_COMP_ID); + + delete l_err; + l_err = NULL; + continue; + } + }//end of RAM list + + l_addr_range.hi = + (l_procMemBases[l_mccInGrp] & + 0xFFFFFFFF00000000ull) >> 32; + l_addr_range.lo = + l_procMemBases[l_mccInGrp] & + 0x00000000FFFFFFFFull; + + l_end = l_addr_range; + + //Update the range + l_end.hi += + (l_procMemSizesBytes[l_mccInGrp] & + 0xFFFFFFFF00000000ull) >> 32; + l_end.lo += + l_procMemSizesBytes[l_mccInGrp] & + 0x00000000FFFFFFFFull; + + HDAT_INF("MI:0x%08X l_addr_range:0x%08X " + "0x%08X" + " l_end:0x%08X 0x%08X", + l_pMiTarget->getAttr + <TARGETING::ATTR_HUID>(), + l_addr_range.hi, l_addr_range.lo, + l_end.hi,l_end.lo); + + uint64_t l_hdatMirrorAddr_x = 0x0ull; + uint64_t l_hdatMirrorAddr = 0x0ull; + uint32_t l_hdatMemcntrlID = 0x0 ; + uint8_t l_hdatMirrorAlogrithm = 0xFF; + bool l_rangeIsMirrorable = false; + + //Calculate the mirror address and + //related data + uint64_t l_startAddr = + (((uint64_t)(l_addr_range.hi) << 32 ) + | (uint64_t)(l_addr_range.lo)); + l_hdatMirrorAddr_x = (l_startAddr / 2) + + l_mirrorBaseAddress_x; + + HDAT_INF("Start add : 0x%016llX " + "MirrorBase : 0x%016llX" + " MirrorAddr : 0x%016llX" + " PayLoadMirrorMem : 0x%X", + l_startAddr, l_mirrorBaseAddress_x, + l_hdatMirrorAddr_x, l_payLoadMirrorMem); + + if ( 0 != l_payLoadMirrorMem ) + { + for ( int idx=0 ; idx < + (int)(sizeof + (TARGETING::ATTR_PROC_MIRROR_SIZES_type) + / sizeof(uint64_t)) ; idx++ ) + { + HDAT_INF("Mirror size : 0x%016llX" + " MirrorAddr : 0x%016llX" + " hdatMirrorAddr_x : 0x%016llX", + l_MirrorSize[idx], + l_MirrorAddr[idx], + l_hdatMirrorAddr_x); + + if( (0 != l_MirrorSize[idx]) && + (l_MirrorAddr[idx] == + l_hdatMirrorAddr_x) ) + { + l_rangeIsMirrorable = true; + l_hdatMirrorAddr = + l_MirrorAddr[idx] | + HDAT_REAL_ADDRESS_MASK64; + break; + } + } + } + + // Set the memory controller ID + l_hdatMemcntrlID |= + 1 << (31 - l_pMcTarget->getAttr + <TARGETING::ATTR_CHIP_UNIT>()); + l_hdatMemcntrlID |= + 1 << (31 - (l_pMiTarget->getAttr + <TARGETING::ATTR_CHIP_UNIT>() + 4)); + l_hdatMemcntrlID |= + 1 << (31 - (l_pMccTarget->getAttr + <TARGETING::ATTR_CHIP_UNIT>() + 8)); + l_hdatMemcntrlID |= + 1 << (31 - (l_pOmiTarget->getAttr + <TARGETING::ATTR_CHIP_UNIT>() + 16)); + + l_err = addMsAreaAddr(l_index, + l_addr_range, + l_end, + l_procChipId, + l_rangeIsMirrorable, + l_hdatMirrorAlogrithm, + l_hdatMirrorAddr, + l_hdatMemcntrlID); + if(NULL != l_err) + { + HDAT_ERR("Error in adding addMsAreaAddr" + " to ms area index[%d]", + l_index); + break; + } + + // TODO : RTC Story 159682 + // Further CHTM support needs to be added + // which contains the trace array for + // 24 cores + // Reinitializing the NHTM size + + // Don't re-init NHTM size -- only one HTM + // region per proc + uint64_t l_end_hi = l_end.hi; + uint64_t l_end_lo = l_end.lo; + uint64_t l_end_addr = + ((l_end_hi << 32 ) | l_end_lo); + + + uint64_t l_addr_range_hi = l_addr_range.hi; + uint64_t l_addr_range_lo = l_addr_range.lo; + uint64_t l_start_addr = + ((l_addr_range_hi << 32 )| l_addr_range_lo); + + uint64_t l_size_bytes = + ((uint64_t)l_areaSizeInMB) * + l_mccSharingCount[l_mccInGrp] * 1024 * 1024; + + if((0 != l_nhtmSize) && + (l_size_bytes != + (l_end_addr - l_start_addr))) + { + HDAT_INF("NHTM Bar size = 0x%016llX " + " MS area size = 0x%016llX" + " l_end_addr = 0x%016llX" + " l_start_addr = 0x%016llX", + l_nhtmSize,l_size_bytes, + l_end_addr, + l_start_addr); + + l_addr_range.lo = + l_hdatNhtmStartAddr.lo; + l_addr_range.hi = + l_hdatNhtmStartAddr.hi; + + l_end.lo = l_hdatNhtmEndAddr.lo; + l_end.hi = l_hdatNhtmEndAddr.hi; + + l_err = addMsAreaAddr(l_index, + l_addr_range, + l_end, + l_procChipId, + false, 0, 0); + if(NULL != l_err) + { + HDAT_ERR("Error in adding " + " addMsAreaAddr to ms area " + "index[%d]", + l_index); + break; + } + l_nhtmSize=0; //only add 1 entry + } + l_addr_range = l_end; + + // Add SMF memory addr range + auto l_smfStartAddr = l_pProcTarget-> + getAttr<TARGETING::ATTR_PROC_SMF_BAR_BASE_ADDR>(); + auto l_smfSize = l_pProcTarget-> + getAttr<TARGETING::ATTR_PROC_SMF_BAR_SIZE>(); + + if(l_smfSize && !l_smfAdded) + { + hdatMsAddr_t l_hdatSmfStartAddr{}; + hdatMsAddr_t l_hdatSmfEndAddr{}; + l_hdatSmfStartAddr.hi = + (l_smfStartAddr & 0xFFFFFFFF00000000ull) >> 32; + l_hdatSmfStartAddr.lo = + l_smfStartAddr & 0x00000000FFFFFFFFull; + l_hdatSmfStartAddr.hi |= HDAT_REAL_ADDRESS_MASK; + + l_hdatSmfEndAddr.hi = + ((l_smfStartAddr + l_smfSize) & + 0xFFFFFFFF00000000ull) >>32; + l_hdatSmfEndAddr.lo = + (l_smfStartAddr + l_smfSize) & + 0x00000000FFFFFFFFull; + l_hdatSmfEndAddr.hi |= HDAT_REAL_ADDRESS_MASK; + + l_err = addMsAreaAddr(l_index, + l_hdatSmfStartAddr, + l_hdatSmfEndAddr, + l_procChipId, + false, //rangeIsMirrorable + 0, // i_mirroringAlgorithm + 0, // i_startMirrAddr + l_hdatMemcntrlID, + true); // i_hdatsmf + l_smfAdded = true; + } + + if(l_err) + { + HDAT_ERR("Could not add SMF memory range to " + "HDAT at index[%d]", l_index); + break; + } + else + { + HDAT_INF("Added SMF memory range to HDAT at " + "index[%d]; start addr: 0x%08x; end addr: 0x%08x" + "; size: 0x%08x", + l_smfStartAddr, + l_smfStartAddr + l_smfSize, + l_smfSize); + } + l_index++; + } // end of OCMB_CHIP list + if(l_err) + { + break; + } + } //end of OMI list + if(l_err) { - HDAT_ERR("Error in adding " - " addMsAreaAddr to ms area index[%d]", - l_index); break; } - l_nhtmSize=0; //only add 1 entry + } //end of MCC list + if(l_err) + { + break; } - l_addr_range = l_end; - l_index++; - } //end of mca list - } //end of MCS list - } //end of MCBIST list + } //end of MI list + if(l_err) + { + break; + } + } //end of MC list + } if(l_err) { // Error message recorded above @@ -1823,7 +2586,8 @@ void HdatMsVpd::commit(void * i_addr, /******************************************************************************* * hdatGetMaxMemConfiguredAddress *******************************************************************************/ -uint64_t HdatMsVpd::hdatGetMaxMemConfiguredAddress() +uint64_t HdatMsVpd::hdatGetMaxMemConfiguredAddress( + TARGETING::ATTR_MODEL_type i_model) { //For each processor in the system TARGETING::PredicateCTM l_procChipPred(TARGETING::CLASS_CHIP, @@ -1856,49 +2620,101 @@ uint64_t HdatMsVpd::hdatGetMaxMemConfiguredAddress() assert(l_pProcTarget-> tryGetAttr<TARGETING::ATTR_PROC_MEM_BASES>(l_procMemBases)); + if (i_model == TARGETING::MODEL_NIMBUS) + { + //For each MCA + TARGETING::PredicateCTM l_allMca(TARGETING::CLASS_UNIT, + TARGETING::TYPE_MCA); + TARGETING::PredicateHwas l_funcMca; + l_funcMca.functional(true); + TARGETING::PredicatePostfixExpr l_allFuncMca; + l_allFuncMca.push(&l_allMca).push(&l_funcMca).And(); - //For each MCA - TARGETING::PredicateCTM l_allMca(TARGETING::CLASS_UNIT, - TARGETING::TYPE_MCA); - TARGETING::PredicateHwas l_funcMca; - l_funcMca.functional(true); - TARGETING::PredicatePostfixExpr l_allFuncMca; - l_allFuncMca.push(&l_allMca).push(&l_funcMca).And(); - - TARGETING::TargetHandleList l_mcaList; + TARGETING::TargetHandleList l_mcaList; - TARGETING::targetService(). + TARGETING::targetService(). getAssociated(l_mcaList, l_pProcTarget, TARGETING::TargetService::CHILD, TARGETING::TargetService::ALL, &l_allFuncMca); - for(uint32_t i=0; i < l_mcaList.size(); i++) - { + for(uint32_t i=0; i < l_mcaList.size(); i++) + { - TARGETING::Target *l_pMcaTarget = l_mcaList[i]; + TARGETING::Target *l_pMcaTarget = l_mcaList[i]; - uint32_t l_mcaInGroup = 0; - if(!hdatFindGroupForMc(l_pProcTarget, - l_pMcaTarget, - l_mcaInGroup)) - { - HDAT_INF("Input target is not in group," - " MCA HUID:[0x%08X]", - l_pMcaTarget->getAttr<TARGETING::ATTR_HUID>()); - //Skip this MC not part of any group - continue; + uint32_t l_mcaInGroup = 0; + if(!hdatFindGroupForMc(l_pProcTarget, + l_pMcaTarget, + l_mcaInGroup)) + { + HDAT_INF("Input target is not in group," + " MCA HUID:[0x%08X]", + l_pMcaTarget->getAttr<TARGETING::ATTR_HUID>()); + //Skip this MC not part of any group + continue; + } + + if(!l_processedAnyGroup || + (l_procMemBases[l_mcaInGroup] > l_maxBase)) + { + l_maxBase = l_procMemBases[l_mcaInGroup]; + l_processedAnyGroup = true; + l_maxMsAddress = + l_maxBase + l_procMemSizesBytes[l_mcaInGroup]; + HDAT_INF("Max MS Addr l_maxMsAddress: = 0x%016llX," + "l_maxBase= 0x%016llX," + "l_procMemSizesBytes[l_mcaInGroup]= 0x%016llX", + l_maxMsAddress, l_maxBase, + l_procMemSizesBytes[l_mcaInGroup]); + } } + } + else + { + //For each MCC + TARGETING::PredicateCTM l_allMcc(TARGETING::CLASS_UNIT, + TARGETING::TYPE_MCC); + TARGETING::PredicateHwas l_funcMcc; + l_funcMcc.functional(true); + TARGETING::PredicatePostfixExpr l_allFuncMcc; + l_allFuncMcc.push(&l_allMcc).push(&l_funcMcc).And(); - if(!l_processedAnyGroup || - (l_procMemBases[l_mcaInGroup] > l_maxBase)) + TARGETING::TargetHandleList l_mccList; + + TARGETING::targetService(). + getAssociated(l_mccList, l_pProcTarget, + TARGETING::TargetService::CHILD, + TARGETING::TargetService::ALL, &l_allFuncMcc); + + for(uint32_t i=0; i < l_mccList.size(); i++) { - l_maxBase = l_procMemBases[l_mcaInGroup]; - l_processedAnyGroup = true; - l_maxMsAddress = l_maxBase + l_procMemSizesBytes[l_mcaInGroup]; - HDAT_INF("Max MS Addr l_maxMsAddress: = 0x%016llX," - "l_maxBase= 0x%016llX," - "l_procMemSizesBytes[l_mcaInGroup]= 0x%016llX", - l_maxMsAddress, l_maxBase, l_procMemSizesBytes[l_mcaInGroup]); + TARGETING::Target *l_pMccTarget = l_mccList[i]; + + uint32_t l_mccInGroup = 0; + if(!hdatFindGroupForMcc(l_pProcTarget, + l_pMccTarget, + l_mccInGroup)) + { + HDAT_INF("Input target is not in group," + " MCC HUID:[0x%08X]", + l_pMccTarget->getAttr<TARGETING::ATTR_HUID>()); + //Skip this MCC as its not part of any group + continue; + } + + if(!l_processedAnyGroup || + (l_procMemBases[l_mccInGroup] > l_maxBase)) + { + l_maxBase = l_procMemBases[l_mccInGroup]; + l_processedAnyGroup = true; + l_maxMsAddress = + l_maxBase + l_procMemSizesBytes[l_mccInGroup]; + HDAT_INF("Max MS Addr l_maxMsAddress: = 0x%016llX," + "l_maxBase= 0x%016llX," + "l_procMemSizesBytes[l_omiInGroup]= 0x%016llX", + l_maxMsAddress, l_maxBase, + l_procMemSizesBytes[l_mccInGroup]); + } } } @@ -2004,6 +2820,56 @@ bool HdatMsVpd::hdatFindGroupForMc(const TARGETING::Target *i_pProcTarget, return l_foundGroup; } + +//****************************************************************************** +//* hdatFindGroupForMcc +//****************************************************************************** +bool HdatMsVpd::hdatFindGroupForMcc(const TARGETING::Target *i_pProcTarget, + const TARGETING::Target *i_pMccTarget, + uint32_t& o_groupOfMcc) +{ + bool l_foundGroup = false; + TARGETING::ATTR_MSS_MEM_MC_IN_GROUP_type l_mccGroups = {0}; + assert(i_pProcTarget != NULL || i_pMccTarget != NULL); + + assert(!(i_pProcTarget->getAttr<TARGETING::ATTR_TYPE>() + != TARGETING::TYPE_PROC)|| + !(i_pProcTarget->getAttr<TARGETING::ATTR_CLASS>() + != TARGETING::CLASS_CHIP)); + + assert(i_pProcTarget-> + tryGetAttr<TARGETING::ATTR_MSS_MEM_MC_IN_GROUP>(l_mccGroups)); + + assert(!(i_pMccTarget->getAttr<TARGETING::ATTR_TYPE>() + != TARGETING::TYPE_MCC)|| + !(i_pMccTarget->getAttr<TARGETING::ATTR_CLASS>() + != TARGETING::CLASS_UNIT)); + TARGETING::ATTR_CHIP_UNIT_type l_chipUnit = + i_pMccTarget->getAttr<TARGETING::ATTR_CHIP_UNIT>(); + uint32_t l_sizeOfArray = sizeof(l_mccGroups)/sizeof(l_mccGroups[0]); + + assert(!(sizeof( l_mccGroups[0] ) != sizeof(uint8_t))); + + assert(!( l_chipUnit >= ( sizeof( l_mccGroups[0] ) * HDAT_BITS_PER_BYTE ))); + + const uint8_t MC_IN_GROUP_MCC_0 = 0x80; + for(uint32_t l_idx =0; l_idx < l_sizeOfArray;++l_idx) + { + //Attribute ATTR_MSS_MEM_MC_IN_GROUP is an array of bitmask + //bit 0 of bitmask corresponds to mcc 0, bit 7 to mcc 7 + if((l_mccGroups[l_idx] & (MC_IN_GROUP_MCC_0 >> l_chipUnit)) == + (MC_IN_GROUP_MCC_0 >> l_chipUnit)) + { + HDAT_INF("hdatFindGroupForMcc::: Found group : %d",l_idx); + o_groupOfMcc = l_idx; + l_foundGroup = true; + break; + } + } + + return l_foundGroup; +} + /******************************************************************************* * hdatScanDimms *******************************************************************************/ @@ -2148,6 +3014,145 @@ errlHndl_t HdatMsVpd::hdatScanDimms(const TARGETING::Target *i_pTarget, while(0); return l_err; } + +/******************************************************************************* +* hdatScanDimmsAxone +*******************************************************************************/ +errlHndl_t HdatMsVpd::hdatScanDimmsAxone(const TARGETING::Target *i_pOcmbTarget, + std::list<hdatRamArea>& o_areas, + uint32_t& o_areaSize, + uint32_t& o_dimmNum, + bool& o_areaFunctional, + hdatMemParentType& o_parentType) +{ + errlHndl_t l_err = NULL; + + do + { + if(i_pOcmbTarget->getAttr<TARGETING::ATTR_TYPE>() != + TARGETING::TYPE_OCMB_CHIP) + { + HDAT_ERR("Input Target is type not OCMB_CHIP"); + break; + } + + //for each mem-port connected to this this ocmb_chip + TARGETING::PredicateCTM l_allMemPort(TARGETING::CLASS_UNIT, + TARGETING::TYPE_MEM_PORT); + TARGETING::PredicateHwas l_funcMemPort; + l_funcMemPort.functional(true); + TARGETING::PredicatePostfixExpr l_allFuncMemPort; + l_allFuncMemPort.push(&l_allMemPort).push(&l_funcMemPort).And(); + + TARGETING::TargetHandleList l_memPortList; + + TARGETING::targetService(). + getAssociated(l_memPortList, i_pOcmbTarget, + TARGETING::TargetService::CHILD, + TARGETING::TargetService::ALL, &l_allFuncMemPort); + + for(uint32_t i=0; i < l_memPortList.size(); i++) + { + TARGETING::Target *l_pmemPortTarget = l_memPortList[i]; + + TARGETING::ATTR_MEM_EFF_DIMM_SIZE_type l_dimSizes = {0}; + //Get configured memory size + if(!l_pmemPortTarget-> + tryGetAttr<TARGETING::ATTR_MEM_EFF_DIMM_SIZE>(l_dimSizes)) + { + HDAT_ERR("DIMM size should be available with MEM_PORT"); + } + + //for each DIMM connected to this this MCA + TARGETING::PredicateCTM l_dimmPredicate(TARGETING:: + CLASS_LOGICAL_CARD, + TARGETING::TYPE_DIMM); + TARGETING::PredicateHwas l_predDimm; + l_predDimm.present(true); + TARGETING::PredicatePostfixExpr l_presentDimm; + l_presentDimm.push(&l_dimmPredicate).push(&l_predDimm).And(); + + TARGETING::TargetHandleList l_dimmList; + + // Get associated dimms + TARGETING::targetService(). + getAssociated(l_dimmList, l_pmemPortTarget, + TARGETING::TargetService::CHILD_BY_AFFINITY, + TARGETING::TargetService::ALL, &l_presentDimm); + + for(uint32_t j=0; j < l_dimmList.size(); ++j) + { + //fetch each dimm + TARGETING::Target *l_pDimmTarget = l_dimmList[j]; + + uint32_t l_dimmfru = 0; + l_dimmfru = l_pDimmTarget->getAttr<TARGETING::ATTR_FRU_ID>(); + + TARGETING::ATTR_MEM_PORT_type l_dimmMemPort = 0; + + if(!l_pDimmTarget-> + tryGetAttr<TARGETING::ATTR_MEM_PORT>(l_dimmMemPort)) + { + HDAT_ERR("DIMM size should be available with MEM_PORT"); + } + + //Convert GB to MB + uint32_t l_dimmSizeInMB = l_dimSizes[l_dimmMemPort] * + HDAT_MB_PER_GB; + uint32_t l_huid = TARGETING::get_huid(l_pDimmTarget); + + bool foundArea = false; + for (std::list<hdatRamArea>::iterator l_area = o_areas.begin(); + l_area != o_areas.end(); + ++l_area) + { + //we do not need to compare each dimm fru id with mca fru id + //to create ram area, by the below logic + //dimms with same fruid will fall into same ram area + //even if they have fru id same with mca + if (l_area->ivfruId == l_dimmfru)//this means soldered dimms + { + foundArea = true; + l_area->ivFunctional = (l_area)->ivFunctional || + isFunctional(l_pDimmTarget); + (l_area)->ivFunctional = true; + (l_area)->ivSize += l_dimmSizeInMB; + break; + } + } + + //Search in the list of RAM Areas if not + //present create a new ram area + if (!foundArea) + { + o_dimmNum++; + o_areas.push_back(hdatRamArea(l_huid, + isFunctional(l_pDimmTarget), + l_dimmSizeInMB,l_dimmfru)); + } + o_areaSize += l_dimmSizeInMB; + o_areaFunctional = o_areaFunctional || + isFunctional(l_pDimmTarget); + } //end of dimm list + + o_parentType = HDAT_MEM_PARENT_CEC_FRU; + + if(l_err != NULL) + { + //break if error + break; + } + } // end of mem_port list + if(l_err != NULL) + { + //break if error + break; + } + } + while(0); + return l_err; +} + /******************************************************************************* * hdatGetMaxMemoryBlocks *******************************************************************************/ diff --git a/src/usr/hdat/hdatmsvpd.H b/src/usr/hdat/hdatmsvpd.H index 0778e3e9a..93955ba39 100755 --- a/src/usr/hdat/hdatmsvpd.H +++ b/src/usr/hdat/hdatmsvpd.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -63,6 +63,10 @@ const uint32_t HDAT_START_INSTANCE = 0; const uint32_t HDAT_RHB_MAX_RANGE_ENTRIES = 20; const uint32_t MAX_DIMMS_PER_MCBIST = 8; +//@TODO:RTC 213230(HDAT Axone additional support) +//Need to revisit the number if needed +const uint32_t HDAT_MAX_MSAREA_AXONE = 32; + /** @brief Structure version number */ const uint16_t HDAT_MS_VPD_VERSION = 0x24; @@ -632,6 +636,7 @@ class HdatMsVpd : public HdatHdif * @param[in] i_startMirrAddr - Specifies the starting mirrorable * address for range * @param[in] i_hdatMemCntlID - Memory Controller ID + * @param[in] i_hdatSmf - Whether the range is in SMF memory * * @return A null error log handle if successful, else the return code * pointed to by errlHndl_t contains one of: @@ -645,7 +650,8 @@ class HdatMsVpd : public HdatHdif bool i_rangeIsMirrorable = false, uint8_t i_mirroringAlgorithm = 0, uint64_t i_startMirrAddr = 0, - uint32_t i_hdatMemCntlID = 0); + uint32_t i_hdatMemCntlID = 0, + bool i_hdatSmf = false); /** @@ -809,10 +815,12 @@ class HdatMsVpd : public HdatHdif /** * @brief Gets maximum configured memory address * + * @param[in] i_model Target model * * @return value of ms address */ - uint64_t hdatGetMaxMemConfiguredAddress(); + uint64_t hdatGetMaxMemConfiguredAddress( + TARGETING::ATTR_MODEL_type i_model); /** * @brief Fetches the group of MC @@ -828,6 +836,19 @@ class HdatMsVpd : public HdatHdif uint32_t& o_groupOfMc); /** + * @brief Fetches the group of MCC + * + * @param[in] i_pTarget Proc target + * @param[in] i_pMccTarget MCC target + * @param[out] o_groupOfMcc MCC group value + * + * @return Success or failure + */ + bool hdatFindGroupForMcc(const TARGETING::Target *i_pProcTarget, + const TARGETING::Target *i_pMccTarget, + uint32_t& o_groupOfMcc); + + /** * @brief Get the DIMMS list present on the system * * @param[in] i_pTarget Mca target @@ -854,6 +875,28 @@ class HdatMsVpd : public HdatHdif hdatMemParentType& i_parentType); /** + * @brief Get the DIMMS list present on the axone system + * + * @param[in] i_pTarget OCMB Chip target + * @param[out] o_areas list of ram area structure based on the DIMM + * present. + * @param[out] o_areaSize - Total DIMM size + * @param[out] o_dimmNum - Total DIMM number + * @param[out] o_areaFunctional - DIMM functional status + * @param[out] o_parentType - memory parent type based on whether + * the dimms are pluggable or soldered + * + * @return A null error log handle if successful, else the return the + * error handle + */ + errlHndl_t hdatScanDimmsAxone(const TARGETING::Target *i_pOcmbTarget, + std::list<hdatRamArea>& o_areas, + uint32_t& o_areaSize, + uint32_t& o_dimmNum, + bool& o_areaFunctional, + hdatMemParentType& i_parentType); + + /** * @brief Get max memory blocks connected to membuf * * @param[in] i_pTarget Mcs target diff --git a/src/usr/hdat/hdatpcrd.C b/src/usr/hdat/hdatpcrd.C index b052afb5d..c813b010f 100644 --- a/src/usr/hdat/hdatpcrd.C +++ b/src/usr/hdat/hdatpcrd.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] Google Inc. */ /* [+] International Business Machines Corp. */ /* */ @@ -446,8 +446,10 @@ errlHndl_t HdatPcrd::hdatLoadPcrd(uint32_t &o_size, uint32_t &o_count) // Need to get i2c Master data correctly std::vector<hdatI2cData_t> l_i2cDevEntries; + TARGETING::ATTR_MODEL_type l_model = TARGETING::MODEL_NIMBUS; + l_model = l_pProcTarget->getAttr<TARGETING::ATTR_MODEL>(); - hdatGetI2cDeviceInfo(l_pProcTarget, l_i2cDevEntries); + hdatGetI2cDeviceInfo(l_pProcTarget, l_model, l_i2cDevEntries); l_pcrdHI2cTotalSize = sizeof(*l_hostI2cFullPcrdHdrPtr) + (sizeof(hdatI2cData_t) * l_i2cDevEntries.size()); diff --git a/src/usr/hdat/hdatutil.C b/src/usr/hdat/hdatutil.C index d0b3edca1..83deff106 100644 --- a/src/usr/hdat/hdatutil.C +++ b/src/usr/hdat/hdatutil.C @@ -772,7 +772,10 @@ errlHndl_t hdatGetPvpdFullRecord(TARGETING::Target * i_target, theRecord,0,0,0, ERRORLOG::ERRL_SEV_INFORMATIONAL, HDAT_VERSION1, - true); + false); + //@TODO:RTC 213229(Remove HDAT hack or Axone) + //There are known differences where not all records will be + //present. So changing now from true to false. continue; } @@ -1738,6 +1741,7 @@ bool byNodeProcAffinity( * * @param[in] i_pTarget * The i2c master target handle, or nullptr for all i2c masters + * @param[in] i_model Target model * @param[out] o_i2cDevEntries * The host i2c dev entries * @@ -1746,6 +1750,7 @@ bool byNodeProcAffinity( *******************************************************************************/ void hdatGetI2cDeviceInfo( TARGETING::Target* i_pTarget, + TARGETING::ATTR_MODEL_type i_model, std::vector<hdatI2cData_t>& o_i2cDevEntries) { HDAT_ENTER(); @@ -1825,11 +1830,13 @@ void hdatGetI2cDeviceInfo( "detected"); ++linkId.instance; - if( (i_pTarget == nullptr) - || (i_pTarget == i2cDevice.masterChip)) + if( (i_pTarget == nullptr) || + (i_pTarget == i2cDevice.masterChip) + ) { o_i2cDevEntries.push_back(l_hostI2cObj); } + } } @@ -2144,60 +2151,77 @@ errlHndl_t hdatUpdateSMPLinkInfoData(hdatHDIFDataArray_t * i_SMPInfoFullPcrdHdrP uint32_t getMemBusFreq(const TARGETING::Target* i_pTarget) { - HDAT_ENTER(); - TARGETING::ATTR_MSS_FREQ_type l_MemBusFreqInMHz = 0; + TARGETING::ATTR_MSS_FREQ_type l_MemBusFreqInMHz = 0; TARGETING::ATTR_CLASS_type l_class = GETCLASS(i_pTarget); TARGETING::ATTR_TYPE_type l_type = GETTYPE(i_pTarget); - if((l_class == TARGETING::CLASS_CHIP) && (l_type == TARGETING::TYPE_PROC)) + if((l_class == TARGETING::CLASS_CHIP) && + (l_type == TARGETING::TYPE_PROC)) { TARGETING::PredicateCTM l_mcbistPredicate(TARGETING::CLASS_UNIT, TARGETING::TYPE_MCBIST); TARGETING::PredicateHwas l_predHwasFunc; TARGETING::PredicatePostfixExpr l_presentMcbist; l_presentMcbist.push(&l_mcbistPredicate). - push(&l_predHwasFunc).And(); + push(&l_predHwasFunc).And(); TARGETING::TargetHandleList l_mcbistList; // Find Associated MCBIST list TARGETING::targetService().getAssociated(l_mcbistList, - i_pTarget, - TARGETING::TargetService::CHILD_BY_AFFINITY, - TARGETING::TargetService::ALL, - &l_presentMcbist); + i_pTarget, + TARGETING::TargetService::CHILD_BY_AFFINITY, + TARGETING::TargetService::ALL, + &l_presentMcbist); if(l_mcbistList.size() == 0) { HDAT_ERR("Didn't find any mcbist for a proc with huid [0x%08X]", - i_pTarget->getAttr<TARGETING::ATTR_HUID>()); + i_pTarget->getAttr<TARGETING::ATTR_HUID>()); } else { TARGETING::Target *l_pMcbistTarget = l_mcbistList[0]; if( l_pMcbistTarget->tryGetAttr<TARGETING::ATTR_MSS_FREQ> - (l_MemBusFreqInMHz) == false ) + (l_MemBusFreqInMHz) == false ) { - HDAT_ERR(" MSS_FREQ not present for MCBIST with huid [0x%08X]", - l_pMcbistTarget->getAttr<TARGETING::ATTR_HUID>()); + HDAT_ERR("MSS_FREQ not present for MCBIST with " + "huid [0x%08X]", + l_pMcbistTarget->getAttr<TARGETING::ATTR_HUID>()); } } - } - else if((l_class == TARGETING::CLASS_UNIT) && (l_type == TARGETING::TYPE_MCBIST)) + } + else if((l_class == TARGETING::CLASS_UNIT) && + (l_type == TARGETING::TYPE_MCBIST)) { - if(i_pTarget->tryGetAttr<TARGETING::ATTR_MSS_FREQ> - (l_MemBusFreqInMHz) == false ) - { - HDAT_ERR(" MSS_FREQ not present for MCBIST with huid [0x%08X]", - i_pTarget->getAttr<TARGETING::ATTR_HUID>()); - } + if(i_pTarget->tryGetAttr<TARGETING::ATTR_MSS_FREQ> + (l_MemBusFreqInMHz) == false ) + { + HDAT_ERR(" MSS_FREQ not present for MCBIST with huid [0x%08X]", + i_pTarget->getAttr<TARGETING::ATTR_HUID>()); + } } else { - HDAT_ERR(" Input target with HUID [0x%08X] is not of proc/mcbist target type", - i_pTarget->getAttr<TARGETING::ATTR_HUID>()); + HDAT_ERR(" Input target with HUID [0x%08X] is not of " + "proc/mcbist target type", + i_pTarget->getAttr<TARGETING::ATTR_HUID>()); + } + HDAT_EXIT(); + return l_MemBusFreqInMHz; +} + +uint32_t getMemBusFreqAxone(const TARGETING::Target* i_pTarget) +{ + HDAT_ENTER(); + TARGETING::ATTR_MEM_EFF_FREQ_type l_MemBusFreqInMHz = {0}; + if( i_pTarget->tryGetAttr<TARGETING::ATTR_MEM_EFF_FREQ> + (l_MemBusFreqInMHz) == false ) + { + HDAT_ERR("MSS_EFF_FREQ not present for MEM PORT with " + "huid [0x%08X]", + i_pTarget->getAttr<TARGETING::ATTR_HUID>()); } - HDAT_EXIT(); return l_MemBusFreqInMHz; } diff --git a/src/usr/hdat/hdatutil.H b/src/usr/hdat/hdatutil.H index 893852482..942549467 100755 --- a/src/usr/hdat/hdatutil.H +++ b/src/usr/hdat/hdatutil.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -572,6 +572,7 @@ errlHndl_t hdatGetFullEepromVpd ( TARGETING::Target * i_target, * * @param[in] i_pTarget * The i2c master target handle + * @param[in] i_model Target model * @param[out] o_i2cDevEntries * The host i2c dev entries * @@ -579,6 +580,7 @@ errlHndl_t hdatGetFullEepromVpd ( TARGETING::Target * i_target, * *******************************************************************************/ void hdatGetI2cDeviceInfo(TARGETING::Target* i_pTarget, + TARGETING::ATTR_MODEL_type i_model, std::vector<hdatI2cData_t>&o_i2cDevEntries); /******************************************************************************* @@ -620,6 +622,13 @@ errlHndl_t hdatUpdateSMPLinkInfoData(hdatHDIFDataArray_t * i_SMPInfoFullPcrdHdrP * @return Memory bus frequency. upon any error conditions it returns 0. *******************************************************************************/ uint32_t getMemBusFreq(const TARGETING::Target* i_pTarget); + +/****************************************************************************** + * @brief get Memory bus frequency of given target. + * @param[in] i_pTarget : input target handle + * @return Memory bus frequency. upon any error conditions it returns 0. +*******************************************************************************/ +uint32_t getMemBusFreqAxone(const TARGETING::Target* i_pTarget); };// end namespace #endif // HDATUTILITY_H diff --git a/src/usr/hdat/hdatvpd.C b/src/usr/hdat/hdatvpd.C index a07996921..9c72c020c 100755 --- a/src/usr/hdat/hdatvpd.C +++ b/src/usr/hdat/hdatvpd.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -58,6 +58,13 @@ extern trace_desc_t * g_hdatTraceDesc; /*----------------------------------------------------------------------------*/ const uint16_t HDAT_VPD_VERSION = 0x0020; +const uint8_t LX_RECORD_TEMPLATE[] = +{0x84, 0x1C, 0x00, 0x52, 0x54, 0x04, 0x4C, 0x58, + 0x52, 0x30, 0x56, 0x5A, 0x02, 0x30, 0x31, 0x4C, + 0x58, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x50, 0x46, 0x02, 0x00, 0x00, 0x78}; +const uint16_t LX_RECORD_SIZE = 32; +const uint16_t LX_KEYWORD_OFFSET= 18; /** @brief See the prologue in hdatvpd.H */ @@ -118,6 +125,19 @@ iv_kwdSize(0), iv_kwd(NULL) HDAT_DBG("hdatGetAsciiKwd returned kwd size =%d",iv_kwdSize); + char *o_fmtKwd; + uint32_t o_fmtkwdSize; + o_errlHndl = hdatformatAsciiKwd(i_fetchVpd, i_num, theSize, iv_kwd, + iv_kwdSize, o_fmtKwd, o_fmtkwdSize, i_pvpdKeywords); + if( o_fmtKwd != NULL ) + { + delete[] iv_kwd; + iv_kwd = new char [o_fmtkwdSize]; + memcpy(iv_kwd,o_fmtKwd,o_fmtkwdSize); + iv_kwdSize = o_fmtkwdSize; + delete[] o_fmtKwd; + } + if(strcmp(i_eyeCatcher,"IO KID")==0) { using namespace TARGETING; @@ -130,30 +150,23 @@ iv_kwdSize(0), iv_kwd(NULL) //fetching lx data uint64_t l_LXvalue = l_sysTarget->getAttr<ATTR_ASCII_VPD_LX_KEYWORD>(); - char *temp_kwd = new char [iv_kwdSize]; - uint32_t temp_kwdSize = iv_kwdSize; - memcpy(temp_kwd, iv_kwd,iv_kwdSize); - delete[] iv_kwd; - iv_kwdSize +=sizeof(uint64_t); - iv_kwd = new char [iv_kwdSize]; - memcpy(iv_kwd,temp_kwd,temp_kwdSize); - memcpy((void *)(iv_kwd+temp_kwdSize),&l_LXvalue,sizeof(uint64_t)); - theSize[i_num-1] = sizeof(uint64_t); - delete[] temp_kwd; - } - char *o_fmtKwd; - uint32_t o_fmtkwdSize; - o_errlHndl = hdatformatAsciiKwd(i_fetchVpd, i_num, theSize, iv_kwd, - iv_kwdSize, o_fmtKwd, o_fmtkwdSize, i_pvpdKeywords); - if( o_fmtKwd != NULL ) - { + char *temp_lx = new char[LX_RECORD_SIZE]; + memcpy(temp_lx, LX_RECORD_TEMPLATE, LX_RECORD_SIZE); + memcpy((void*)(temp_lx + LX_KEYWORD_OFFSET), &l_LXvalue, sizeof(uint64_t)); + + //append LXR0 record to VINI record + size_t combined_size = iv_kwdSize + LX_RECORD_SIZE; + char * temp_buf = new char[combined_size]; + memcpy(temp_buf,iv_kwd,iv_kwdSize); + memcpy((void *)(temp_buf+iv_kwdSize),temp_lx, LX_RECORD_SIZE); + + delete[] temp_lx; delete[] iv_kwd; - iv_kwd = new char [o_fmtkwdSize]; - memcpy(iv_kwd,o_fmtKwd,o_fmtkwdSize); - iv_kwdSize = o_fmtkwdSize; - delete[] o_fmtKwd; + iv_kwd = temp_buf; + iv_kwdSize = combined_size; } + if (NULL == o_errlHndl) { iv_fru.hdatSlcaIdx = l_slcaIdx; @@ -194,7 +207,10 @@ iv_kwdSize(0), iv_kwd(NULL) TARGETING::TargetHandleList l_targList; PredicateCTM predNode(TARGETING::CLASS_ENC, TARGETING::TYPE_NODE); PredicateHwas predFunctional; - predFunctional.functional(true); + //@TODO:RTC 213229(Remove HDAT hack or Axone) + //crashes below at l_target because the node got deconfigured + //changed from functional to present + predFunctional.present(true); PredicatePostfixExpr nodeCheckExpr; nodeCheckExpr.push(&predNode).push(&predFunctional).And(); @@ -238,16 +254,20 @@ iv_kwdSize(0), iv_kwd(NULL) //fetching lx data uint64_t l_LXvalue = l_sysTarget->getAttr<ATTR_ASCII_VPD_LX_KEYWORD>(); - char *temp_kwd = new char [iv_kwdSize]; - uint32_t temp_kwdSize = iv_kwdSize; - memcpy(temp_kwd, iv_kwd,iv_kwdSize); + char *temp_lx = new char[LX_RECORD_SIZE]; + memcpy(temp_lx, LX_RECORD_TEMPLATE, LX_RECORD_SIZE); + memcpy((void*)(temp_lx + LX_KEYWORD_OFFSET), &l_LXvalue, sizeof(uint64_t)); + + //append LXR0 record to VINI record + size_t combined_size = iv_kwdSize + LX_RECORD_SIZE; + char * temp_buf = new char[combined_size]; + memcpy(temp_buf,iv_kwd,iv_kwdSize); + memcpy((void *)(temp_buf+iv_kwdSize),temp_lx, LX_RECORD_SIZE); + + delete[] temp_lx; delete[] iv_kwd; - iv_kwdSize +=sizeof(uint64_t); - iv_kwd = new char [iv_kwdSize]; - memcpy(iv_kwd,temp_kwd,temp_kwdSize); - memcpy((void *)(iv_kwd+temp_kwdSize),&l_LXvalue,sizeof(uint64_t)); - theSize[i_num-1] = sizeof(uint64_t); - delete[] temp_kwd; + iv_kwd = temp_buf; + iv_kwdSize = combined_size; } if (NULL == o_errlHndl) { diff --git a/src/usr/htmgt/htmgt.C b/src/usr/htmgt/htmgt.C index f83cf65a8..db34411d5 100644 --- a/src/usr/htmgt/htmgt.C +++ b/src/usr/htmgt/htmgt.C @@ -31,7 +31,6 @@ #include "htmgt_memthrottles.H" #include "htmgt_poll.H" #include <devicefw/userif.H> -#include <config.h> #include <console/consoleif.H> // Targeting support diff --git a/src/usr/htmgt/htmgt_occ.H b/src/usr/htmgt/htmgt_occ.H index e53d78fe6..21079c2ad 100644 --- a/src/usr/htmgt/htmgt_occ.H +++ b/src/usr/htmgt/htmgt_occ.H @@ -99,6 +99,16 @@ namespace HTMGT } __attribute__ ((__packed__)); typedef struct occErrlCallout occErrlCallout_t; + // PGPE Callout Structure + struct pgpeErrlCallout + { + uint64_t calloutValue; + uint8_t type; + uint8_t priority; + uint8_t reserved[6]; + } __attribute__ ((__packed__)); + typedef struct pgpeErrlCallout pgpeErrlCallout_t; + /** * @class Occ @@ -382,6 +392,21 @@ namespace HTMGT /** + * @brief Add specified PGEP callout to the error log + * + * @param[in,out] io_errlHndl elog to add callout + * @param[in] i_priority priority for callout + * @param[in] i_callout callout from PGPE + * @param[in,out] io_numCallouts number of callouts in elog, + * incremented if new callout added + * */ + bool elogAddPgpeCallout(errlHndl_t & io_errlHndl, + HWAS::callOutPriority & i_priority, + const pgpeErrlCallout_t i_callout, + uint8_t & io_callout_num); + + + /** * @brief Update the GPU presence sensors in the system */ void updateGpuPresence(); diff --git a/src/usr/htmgt/occError.C b/src/usr/htmgt/occError.C index 492d047ce..690a86c54 100644 --- a/src/usr/htmgt/occError.C +++ b/src/usr/htmgt/occError.C @@ -128,11 +128,23 @@ namespace HTMGT const occErrlEntry_t * l_occElog = reinterpret_cast<occErrlEntry_t*> (l_buffer.pointer()); - TMGT_BIN("OCC ELOG", l_occElog, 256); + TMGT_BIN("OCC ELOG", l_occElog, 320); - // Get user details section + unsigned int l_elog_header_len = OCC_ELOG_HEADER_LENGTH; + unsigned int l_max_callout = l_occElog->occ_data.maxCallouts; + unsigned int l_callout_size = sizeof(occErrlCallout_t); + if (i_source != OCC_ERRSRC_405) + { + // PGPE logs require different memory alignment/structures + l_elog_header_len = PGPE_ELOG_HEADER_LENGTH; + l_max_callout = l_occElog->pgpe_data.maxCallouts; + l_callout_size = sizeof(pgpeErrlCallout_t); + } + + // Get user details section (after callouts) const occErrlUsrDtls_t *l_usrDtls_ptr = (occErrlUsrDtls_t *) - ((uint8_t*)l_occElog + sizeof(occErrlEntry_t)); + ( (uint8_t*)l_occElog + + l_elog_header_len + (l_max_callout * l_callout_size) ); const uint32_t l_occSrc = l_comp_id | l_occElog->reasonCode; ERRORLOG::errlSeverity_t severity = @@ -166,6 +178,16 @@ namespace HTMGT severity, l_call_home_event); + uint16_t l_extendedRC = l_usrDtls_ptr->modId << 16; + if (i_source == OCC_ERRSRC_405) + { + l_extendedRC |= l_occElog->occ_data.extendedRC; + } + else + { + l_extendedRC |= l_occElog->pgpe_data.extendedRC; + } + // Create OCC error log // NOTE: word 4 (used by extended reason code) to save off OCC // sub component value which is needed to correctly parse @@ -178,8 +200,7 @@ namespace HTMGT l_usrDtls_ptr->userData1, l_usrDtls_ptr->userData2, l_usrDtls_ptr->userData3, - (l_usrDtls_ptr->modId << 16 ) | - l_occElog->extendedRC, // extended reason code + l_extendedRC, severity); if (l_call_home_event) @@ -190,26 +211,36 @@ namespace HTMGT } // Add callout information - const uint8_t l_max_callouts = l_occElog->maxCallouts; bool l_bad_fru_data = false; uint8_t numCallouts = 0; uint8_t calloutIndex = 0; - while (calloutIndex < l_max_callouts) + while (calloutIndex < l_max_callout) { - const occErrlCallout_t callout = - l_occElog->callout[calloutIndex]; - if (callout.type != 0) + const occErrlCallout_t *callout = (occErrlCallout_t*) + ( (uint8_t*)l_occElog + l_elog_header_len + + (calloutIndex*l_callout_size) ); + if (callout->type != 0) { HWAS::callOutPriority priority; bool l_success = true; - l_success = elogXlateSrciPriority(callout.priority, + l_success = elogXlateSrciPriority(callout->priority, priority); if (l_success == true) { - l_success = elogAddCallout(l_errlHndl, - priority, - callout, - numCallouts); + if (i_source == OCC_ERRSRC_405) + { + l_success = elogAddCallout(l_errlHndl, + priority, + *callout, + numCallouts); + } + else + { + l_success = elogAddPgpeCallout(l_errlHndl, + priority, + *((pgpeErrlCallout_t*)callout), + numCallouts); + } if (l_success == false) { l_bad_fru_data = true; @@ -220,24 +251,26 @@ namespace HTMGT l_bad_fru_data = true; TMGT_ERR("occProcessElog: Priority translate" " failure (priority = 0x%02X)", - callout.priority); + callout->priority); } } else { // make sure all the remaining callout data are zeros, // otherwise mark bad fru data - const occErrlCallout_t zeros = { 0 }; - while (calloutIndex < l_max_callouts) + uint8_t *l_ptr = (uint8_t*)callout; + unsigned int l_len = + (l_max_callout-calloutIndex) * l_callout_size; + while (l_len != 0) { - if (memcmp(&l_occElog->callout[calloutIndex], - &zeros, sizeof(occErrlCallout_t))) + if (*l_ptr != 0x00) { TMGT_ERR("occProcessElog: The remaining" " callout data should be all zeros"); l_bad_fru_data = true; break; } - ++calloutIndex; + l_len--; + l_ptr++; } break; } @@ -248,8 +281,10 @@ namespace HTMGT errlHndl_t err2 = nullptr; if (l_bad_fru_data == true) { - TMGT_BIN("Callout Data", &l_occElog->callout[0], - sizeof(occErrlCallout)*ERRL_MAX_CALLOUTS); + const uint8_t *callout_ptr = (uint8_t*)l_occElog + + l_elog_header_len; + TMGT_BIN("Callout Data", callout_ptr, + l_callout_size * ERRL_MAX_CALLOUTS); /*@ * @errortype * @refcode LIC_REFCODE @@ -516,6 +551,65 @@ namespace HTMGT } // end Occ::elogAddCallout() + // Add callout to specified elog + bool Occ::elogAddPgpeCallout(errlHndl_t & io_errlHndl, + HWAS::callOutPriority & i_priority, + const pgpeErrlCallout_t i_callout, + uint8_t & io_callout_num) + { + bool l_success = true; + + TMGT_INF("elogAddPgpeCallout: Add callout type:0x%02X, value:0x%016llX," + " priority:0x%02X", + i_callout.type,i_callout.calloutValue, i_priority); + + if (i_callout.type == OCC_CALLOUT_TYPE_COMPONENT_ID) + { + tmgtCompxlateType l_compDataType; + uint32_t l_compData = 0; + const uint8_t l_compId = (i_callout.calloutValue & 0xFF); + + if (elogGetTranslationData(l_compId, l_compDataType, l_compData)) + { + switch(l_compDataType) + { + case TMGT_COMP_DATA_SYMBOLIC_FRU: + TMGT_INF("elogAddPgpeCallout: symbolic callout: 0x%08X", + l_compData); + break; + case TMGT_COMP_DATA_PROCEDURE: + io_errlHndl->addProcedureCallout( + (HWAS::epubProcedureID)l_compData, + i_priority); + io_callout_num++; + break; + case TMGT_COMP_DATA_END_OF_TABLE: + break; + default: + TMGT_ERR("elogAddPgpeCallout: Invalid component id" + " 0x%02X", l_compId); + l_success = false; + } + } + else + { + TMGT_ERR("elogAddPgpeCallout: Component id translate failure" + " (id=0x%02X)", l_compId); + l_success = false; + } + } + else + { + TMGT_ERR("elogAddPgpeCallout: Invalid callout type (type=%d)", + i_callout.type); + l_success = false; + } + + return l_success;; + + } // end Occ::elogAddPgpeCallout() + + void Occ::elogProcessActions(const uint8_t i_actions, const uint32_t i_src, uint32_t i_data, diff --git a/src/usr/htmgt/occError.H b/src/usr/htmgt/occError.H index ac98bf8bb..216c4b946 100644 --- a/src/usr/htmgt/occError.H +++ b/src/usr/htmgt/occError.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014,2018 */ +/* Contributors Listed Below - COPYRIGHT 2014,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -130,6 +130,8 @@ namespace HTMGT #define ERRL_MAX_CALLOUTS 6 // OCC Error Log Structure + const unsigned int OCC_ELOG_HEADER_LENGTH = 12; + const unsigned int PGPE_ELOG_HEADER_LENGTH = 16; struct occErrlEntry { // Log CheckSum @@ -144,14 +146,30 @@ namespace HTMGT uint8_t severity; // Actions to process the errors uint8_t actions; - // Reserved - uint16_t reserved; - // Extended Reason Code - uint16_t extendedRC; - // Log Callout Number - uint8_t maxCallouts; - // Callouts - occErrlCallout callout[ERRL_MAX_CALLOUTS]; + + union // PGPE has different alignment requirements, so structure differs + { + struct { + // Max Elog Size + uint16_t maxSize; + // Extended Reason Code + uint16_t extendedRC; + // Log Callout Number + uint8_t maxCallouts; + } occ_data __attribute__((packed)); + struct { + // Log Callout Number + uint8_t maxCallouts; + // Extended Reason Code + uint16_t extendedRC; + // Max Elog Size + uint16_t maxSize; + // Reserved + uint16_t reserved[2]; + } pgpe_data __attribute__ ((__packed__)); + }; + + // Callouts start } __attribute__ ((__packed__)); typedef struct occErrlEntry occErrlEntry_t; @@ -192,10 +210,13 @@ namespace HTMGT const tmgtCompXlate_t tmgt_compXlateTable[TMGT_MAX_COMP_IDS] = { - { 0x01, TMGT_COMP_DATA_PROCEDURE, HWAS::EPUB_PRC_HB_CODE}, // FW - { 0x04, TMGT_COMP_DATA_SYMBOLIC_FRU, OVERTMP}, // over temperature - { 0x05, TMGT_COMP_DATA_SYMBOLIC_FRU, TPMD_OV}, // oversub throttling - { 0xFF, TMGT_COMP_DATA_END_OF_TABLE, 0}, // none + { OCC_COMPONENT_ID_FIRMWARE, + TMGT_COMP_DATA_PROCEDURE,HWAS::EPUB_PRC_HB_CODE}, + { OCC_COMPONENT_ID_OVER_TEMPERATURE, TMGT_COMP_DATA_SYMBOLIC_FRU, + OVERTMP}, + { OCC_COMPONENT_ID_OVERSUBSCRIPTION, TMGT_COMP_DATA_SYMBOLIC_FRU, + TPMD_OV}, + { OCC_COMPONENT_ID_NONE, TMGT_COMP_DATA_END_OF_TABLE, 0} // END }; diff --git a/src/usr/htmgt/runtime/rt_occ.C b/src/usr/htmgt/runtime/rt_occ.C index 652e767ed..d25d12f96 100644 --- a/src/usr/htmgt/runtime/rt_occ.C +++ b/src/usr/htmgt/runtime/rt_occ.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014,2018 */ +/* Contributors Listed Below - COPYRIGHT 2014,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,7 +27,7 @@ #include <htmgt/htmgt.H> #include "../htmgt_utility.H" #include <targeting/common/commontargeting.H> -#include <runtime/rt_targeting.H> +#include <targeting/runtime/rt_targeting.H> using namespace TARGETING; diff --git a/src/usr/hwas/common/deconfigGard.C b/src/usr/hwas/common/deconfigGard.C index 727611eed..89df5b160 100644 --- a/src/usr/hwas/common/deconfigGard.C +++ b/src/usr/hwas/common/deconfigGard.C @@ -42,7 +42,6 @@ #include <targeting/common/targetservice.H> #ifdef __HOSTBOOT_MODULE -#include <config.h> #include <errl/errlmanager.H> #if (!defined(CONFIG_CONSOLE_OUTPUT_TRACE) && defined(CONFIG_CONSOLE)) #include <console/consoleif.H> @@ -174,6 +173,17 @@ errlHndl_t DeconfigGard::applyGardRecord(Target *i_pTarget, // all ok - do the work HWAS_MUTEX_LOCK(iv_mutex); +#if (!defined(CONFIG_CONSOLE_OUTPUT_TRACE) && defined(CONFIG_CONSOLE)) + const char* l_tmpstring = + i_pTarget->getAttr<TARGETING::ATTR_PHYS_PATH>().toString(); + CONSOLE::displayf("HWAS", "Applying GARD record for HUID=0x%08X (%s) due to 0x%.8X", + get_huid(i_pTarget), + l_tmpstring, + l_errlogEid); + free((void*)(l_tmpstring)); + l_tmpstring = nullptr; +#endif + // Deconfigure the Target // don't need to check ATTR_DECONFIG_GARDABLE -- if we get // here, it's because of a gard record on this target @@ -643,9 +653,13 @@ errlHndl_t DeconfigGard::deconfigureTargetsFromGardRecordsForIpl( } #if (!defined(CONFIG_CONSOLE_OUTPUT_TRACE) && defined(CONFIG_CONSOLE)) + const char* l_tmpstring = + l_pTarget->getAttr<TARGETING::ATTR_PHYS_PATH>().toString(); CONSOLE::displayf("HWAS", "Deconfig HUID 0x%08X, %s", get_huid(l_pTarget), - l_pTarget->getAttr<TARGETING::ATTR_PHYS_PATH>().toString()); + l_tmpstring); + free((void*)(l_tmpstring)); + l_tmpstring = nullptr; #endif } // for @@ -912,9 +926,13 @@ errlHndl_t DeconfigGard::deconfigureTargetsFromGardRecordsForIpl( } #if (!defined(CONFIG_CONSOLE_OUTPUT_TRACE) && defined(CONFIG_CONSOLE)) + const char* l_tmpstring = + l_pTarget->getAttr<TARGETING::ATTR_PHYS_PATH>().toString(); CONSOLE::displayf("HWAS", "Deconfig HUID 0x%08X, %s", get_huid(l_pTarget), - l_pTarget->getAttr<TARGETING::ATTR_PHYS_PATH>().toString()); + l_tmpstring); + free((void*)(l_tmpstring)); + l_tmpstring = nullptr; #endif l_specDeconfigVector.erase(l_specDeconfigVector.begin()); diff --git a/src/usr/hwas/common/hwas.C b/src/usr/hwas/common/hwas.C index 45a88cf85..94d947dad 100644 --- a/src/usr/hwas/common/hwas.C +++ b/src/usr/hwas/common/hwas.C @@ -41,7 +41,6 @@ #include <stdio.h> // sprintf #ifdef __HOSTBOOT_MODULE -#include <config.h> #include <initservice/initserviceif.H> #endif @@ -569,6 +568,59 @@ errlHndl_t discoverMuxTargetsAndEnable(const Target &i_sysTarget) return l_err; } +/** + * @brief Do presence detect on only PMIC targets and enable HWAS state + * + * @param[in] i_sysTarget the top level target (CLASS_SYS) + * @return errlHndl_t return nullptr if no error, + * else return a handle to an error entry + * + */ +errlHndl_t discoverPmicTargetsAndEnable(const Target &i_sysTarget) +{ + HWAS_INF(ENTER_MRK"discoverPmicTargetsAndEnable"); + + errlHndl_t l_err{nullptr}; + + do + { + // Only get PMIC targets + const PredicateCTM l_pmicPred(CLASS_ASIC, TYPE_PMIC); + TARGETING::PredicatePostfixExpr l_asicPredExpr; + l_asicPredExpr.push(&l_pmicPred); + TargetHandleList l_pPmicCheckPres; + targetService().getAssociated( l_pPmicCheckPres, (&i_sysTarget), + TargetService::CHILD, TargetService::ALL, &l_asicPredExpr); + + // Do the presence detect on only PMIC targets + // NOTE: this function will remove any non-functional targets + // from pPmicCheckPres + l_err = platPresenceDetect(l_pPmicCheckPres); + + // If an issue with platPresenceDetect, then exit, returning + // error back to caller + if (nullptr != l_err) + { + break; + } + + // Enable the HWAS State for the PMICs + const bool l_present(true); + const bool l_functional(true); + const uint32_t l_errlEid(0); + for (TargetHandle_t pTarget : l_pPmicCheckPres) + { + // set HWAS state to show PMIC is present and functional + enableHwasState(pTarget, l_present, l_functional, l_errlEid); + } + } while (0); + + HWAS_INF(EXIT_MRK"discoverPmicTargetsAndEnable exit with %s", + (nullptr == l_err ? "no error" : "error")); + + return l_err; +} + errlHndl_t discoverTargets() { HWAS_DBG("discoverTargets entry"); @@ -643,11 +695,13 @@ errlHndl_t discoverTargets() PredicateCTM predPmic(CLASS_ASIC, TYPE_PMIC); // We can ignore chips of TYPE_I2C_MUX because they // were already detected above in discoverMuxTargetsAndEnable + // Also we can ignore chips of type PMIC because they will be processed + // below. PredicateCTM predMux(CLASS_CHIP, TYPE_I2C_MUX); PredicatePostfixExpr checkExpr; checkExpr.push(&predChip).push(&predDimm).Or().push(&predEnc).Or(). - push(&predMcs).Or().push(&predPmic).Or(). - push(&predMux).Not().And(); + push(&predMcs).Or().push(&predMux).Not().And(). + push(&predPmic).Not().And(); TargetHandleList pCheckPres; targetService().getAssociated( pCheckPres, pSys, @@ -728,19 +782,22 @@ errlHndl_t discoverTargets() MOD_DISCOVER_TARGETS, RC_PARTIAL_GOOD_INFORMATION); - if( (pTarget->getAttr<ATTR_CLASS>() == CLASS_CHIP) && - (l_targetType != TYPE_TPM) && - (l_targetType != TYPE_SP) && - (l_targetType != TYPE_BMC) && - (l_targetType != TYPE_I2C_MUX)) + if( (pTarget->getAttr<ATTR_CLASS>() == CLASS_CHIP) + && (l_targetType != TYPE_TPM) + && (l_targetType != TYPE_SP) + && (l_targetType != TYPE_BMC) + && (l_targetType != TYPE_I2C_MUX)) { // read Chip ID/EC data from these physical chips errl = platReadIDEC(pTarget); if (errl) - { // read of ID/EC failed even tho we THOUGHT we were present. - HWAS_INF("pTarget %.8X - read IDEC failed (eid 0x%X) - bad", - errl->eid(), pTarget->getAttr<ATTR_HUID>()); + { + // read of ID/EC failed even tho we THOUGHT we were present. + HWAS_INF("pTarget 0x%.8X - read IDEC failed " + "(eid 0x%X) - bad", + get_huid(pTarget), errl->eid()); + // chip NOT present and NOT functional, so that FSP doesn't // include this for HB to process chipPresent = false; @@ -758,8 +815,9 @@ errlHndl_t discoverTargets() if (errl) { // read of PG failed even tho we were present.. - HWAS_INF("pTarget %.8X - read PG failed (eid 0x%X)- bad", - errl->eid(), pTarget->getAttr<ATTR_HUID>()); + HWAS_INF("pTarget 0x%.8X - read PG failed " + "(eid 0x%X) - bad", + get_huid(pTarget), errl->eid()); chipFunctional = false; errlEid = errl->eid(); @@ -861,6 +919,16 @@ errlHndl_t discoverTargets() } // for pTarget_it + // After processing all other targets look at the pmics, + // we must wait because we need the SPD cached from the OCMBs + // which occurs when OCMBs go through presence detection above + errl = discoverPmicTargetsAndEnable(*pSys); + + if (errl != NULL) + { + break; // break out of the do/while so that we can return + } + // Check for non-present Procs and if found, trigger // DeconfigGard::_invokeDeconfigureAssocProc() to run by setting // setXAOBusEndpointDeconfigured to true @@ -966,6 +1034,13 @@ bool isChipFunctional(const TARGETING::TargetHandle_t &i_target, uint16_t l_xbus = (l_model == MODEL_NIMBUS) ? VPD_CP00_PG_XBUS_GOOD_NIMBUS : VPD_CP00_PG_XBUS_GOOD_CUMULUS; + uint16_t l_perv = (l_model == MODEL_AXONE) ? + VPD_CP00_PG_PERVASIVE_GOOD_AXONE : VPD_CP00_PG_PERVASIVE_GOOD; + + uint16_t l_n2 = (l_model == MODEL_AXONE) ? + VPD_CP00_PG_N2_GOOD_AXONE : VPD_CP00_PG_N2_GOOD; + + // Check all bits in FSI entry if (i_pgData[VPD_CP00_PG_FSI_INDEX] != VPD_CP00_PG_FSI_GOOD) @@ -981,14 +1056,14 @@ bool isChipFunctional(const TARGETING::TargetHandle_t &i_target, else // Check all bits in PRV entry if (i_pgData[VPD_CP00_PG_PERVASIVE_INDEX] != - VPD_CP00_PG_PERVASIVE_GOOD) + l_perv) { HWAS_INF("pTarget %.8X - Pervasive pgData[%d]: " "actual 0x%04X, expected 0x%04X - bad", i_target->getAttr<ATTR_HUID>(), VPD_CP00_PG_PERVASIVE_INDEX, i_pgData[VPD_CP00_PG_PERVASIVE_INDEX], - VPD_CP00_PG_PERVASIVE_GOOD); + l_perv); l_chipFunctional = false; } else @@ -1018,14 +1093,14 @@ bool isChipFunctional(const TARGETING::TargetHandle_t &i_target, } else // Check all bits in N2 entry - if (i_pgData[VPD_CP00_PG_N2_INDEX] != VPD_CP00_PG_N2_GOOD) + if (i_pgData[VPD_CP00_PG_N2_INDEX] != l_n2) { HWAS_INF("pTarget %.8X - N2 pgData[%d]: " "actual 0x%04X, expected 0x%04X - bad", i_target->getAttr<ATTR_HUID>(), VPD_CP00_PG_N2_INDEX, i_pgData[VPD_CP00_PG_N2_INDEX], - VPD_CP00_PG_N2_GOOD); + l_n2); l_chipFunctional = false; } else @@ -3839,7 +3914,7 @@ errlHndl_t updateProcCompatibilityRiskLevel() "force compatibility of invalid MRW risk level %d", l_risk); - /* + /*@ * @errortype * @severity ERRL_SEV_UNRECOVERABLE * @moduleid MOD_UPDATE_PROC_COMPAT_RISK_LEVEL @@ -3906,7 +3981,7 @@ errlHndl_t updateProcCompatibilityRiskLevel() "force native compatibility of mixed processor levels", " (0x%02X and 0x%02X)", l_firstEc, l_lastEc ); - /* + /*@ * @errortype * @severity ERRL_SEV_UNRECOVERABLE * @moduleid MOD_UPDATE_PROC_COMPAT_RISK_LEVEL @@ -3977,7 +4052,7 @@ errlHndl_t updateProcCompatibilityRiskLevel() "force native compatibility of DD2.3 for risk level %d", l_risk); - /* + /*@ * @errortype * @severity ERRL_SEV_UNRECOVERABLE * @moduleid MOD_UPDATE_PROC_COMPAT_RISK_LEVEL @@ -4064,6 +4139,33 @@ errlHndl_t updateProcCompatibilityRiskLevel() return l_err; } +/** + * @brief Normalize the RISK_LEVEL for Axone to use the upper range + */ +void normalizeRiskLevelForAxone( void ) +{ + // Axone follows Nimbus DD2.3 settings except it can use + // the low or high numbers. Let's normalize it to the + // high range to make things less confusing. + Target* pSys; + targetService().getTopLevelTarget(pSys); + auto l_risk = pSys->getAttr<TARGETING::ATTR_RISK_LEVEL>(); + if( TARGETING::UTIL::P9A_RUGBY_FAVOR_SECURITY_LOWER == l_risk ) + { + l_risk = TARGETING::UTIL::P9A_RUGBY_FAVOR_SECURITY; + } + else if( TARGETING::UTIL::P9A_RUGBY_FAVOR_PERFORMANCE_LOWER == l_risk ) + { + l_risk = TARGETING::UTIL::P9A_RUGBY_FAVOR_PERFORMANCE; + } + else + { + // Nothing to change, just leave + return; + } + pSys->setAttr<TARGETING::ATTR_RISK_LEVEL>(l_risk); +} + errlHndl_t validateProcessorEcLevels() { HWAS_INF("validateProcessorEcLevels entry"); @@ -4109,6 +4211,12 @@ errlHndl_t validateProcessorEcLevels() break; } } + else if(TARGETING::MODEL_AXONE == l_model) + { + // Axone follows Nimbus DD2.3 settings except it can use + // the low or high numbers, going to force one way. + normalizeRiskLevelForAxone(); + } //Loop through all functional procs and create error logs //for any processors whose EC does not match the master diff --git a/src/usr/hwas/common/pgLogic.C b/src/usr/hwas/common/pgLogic.C index 2cc30944f..cd0aa9b19 100644 --- a/src/usr/hwas/common/pgLogic.C +++ b/src/usr/hwas/common/pgLogic.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -31,6 +31,7 @@ #include <hwas/common/hwasError.H> using namespace HWAS::COMMON; +using namespace HWAS; //needed for trace macros namespace PARTIAL_GOOD { @@ -134,6 +135,7 @@ namespace PARTIAL_GOOD // MC // PG/AG Masks const uint16_t MC_R1_AG_MASK = 0xE0FD; + const uint16_t MC_R1_AG_MASK_AXONE = 0xE03D; const uint16_t MC_R2_PG_MASK = 0x0040; const uint16_t MC_R3_PG_MASK = 0x0020; @@ -257,6 +259,9 @@ namespace PARTIAL_GOOD if (rulesIterator == pgRules_map.end()) { + HWAS_ERR( "No rules found for type %d", + i_target->getAttr<TARGETING::ATTR_TYPE>() ); + // Target is missing from the table. This is an error, so break // out of this section of code and return the appropriate error // below. @@ -344,6 +349,12 @@ namespace PARTIAL_GOOD // the following error if applicable. if ((l_errl == nullptr) && (o_targetPgLogic.size() == 0)) { + HWAS_ERR( "No rule found for Target %.8X of type %d", + get_huid(i_target), + i_target->getAttr<TARGETING::ATTR_TYPE>() ); + uint64_t userdata1 = static_cast<uint64_t>(i_target->getAttr<TARGETING::ATTR_TYPE>()); + userdata1 <<= 32; + userdata1 |= static_cast<uint64_t>(get_huid(i_target)); /*@ * @errortype * @severity ERRL_SEV_UNRECOVERABLE @@ -358,15 +369,16 @@ namespace PARTIAL_GOOD * * @custdesc A problem occured during IPL of the system: * Internal Firmware Error - * @userdata1 target type attribute - * @userdata2 HUID of the target + * @userdata1[00:31] target type attribute + * @userdata1[32:63] HUID of the target + * @userdata2 Number of rules for this target type */ l_errl = hwasError( ERRL_SEV_UNRECOVERABLE, HWAS::MOD_FIND_RULES_FOR_TARGET, HWAS::RC_NO_PG_LOGIC, - i_target->getAttr<TARGETING::ATTR_TYPE>(), - get_huid(i_target)); + userdata1, + pgRules_map.size()); } return l_errl; @@ -481,8 +493,7 @@ namespace PARTIAL_GOOD != TARGETING::OPTICS_CONFIG_MODE_SMP) && ((i_pgData[N3_PG_INDEX] & NPU_R1_PG_MASK) != ALL_OFF_AG_MASK)) { - TRACFCOMP(HWAS::g_trac_imp_hwas, - "pDesc 0x%.8X - OBUS_BRICK pgData[%d]: " + HWAS_INF( "pDesc 0x%.8X - OBUS_BRICK pgData[%d]: " "actual 0x%04X, expected 0x%04X - bad", i_desc->getAttr<TARGETING::ATTR_HUID>(), N3_PG_INDEX, diff --git a/src/usr/hwas/hwasPlat.C b/src/usr/hwas/hwasPlat.C index bea5b4d8f..1cea60415 100644 --- a/src/usr/hwas/hwasPlat.C +++ b/src/usr/hwas/hwasPlat.C @@ -43,13 +43,16 @@ #include <sys/misc.h> #include <pnor/pnorif.H> +#include <fapiwrap/fapiWrapif.H> #include <hwas/common/hwas_reasoncodes.H> #include <targeting/common/utilFilter.H> #include <fsi/fsiif.H> -#include <config.h> #include <targeting/common/targetservice.H> #include <chipids.H> +#include <vpd/spdenums.H> + +#include <map> #ifdef CONFIG_SUPPORT_EEPROM_CACHING #include <i2c/eepromif.H> @@ -85,13 +88,19 @@ errlHndl_t platReadIDEC(const TargetHandle_t &i_target) // Call over to the target-specific layer since every chip can have // unique registers size_t sz = 0; - errlHndl_t l_errl = - DeviceFW::deviceWrite(i_target, - nullptr, - sz, - DEVICE_IDEC_ADDRESS()); + errlHndl_t errl = nullptr; - return l_errl; + // Pass a 1 as va_arg to signal phase 1 of ocmbIDEC to execute. + // Other IDEC functions will ignore this argument. + const uint64_t Phase1 = 1; + errl = DeviceFW::deviceWrite(i_target, + nullptr, + sz, + DEVICE_IDEC_ADDRESS(), + Phase1); + + + return errl; } /** @@ -234,6 +243,70 @@ DEVICE_REGISTER_ROUTE(DeviceFW::WRITE, TARGETING::TYPE_MEMBUF, cfamIDEC); +/** + * @brief During early IPL the OCMB isn't able to be read from so this function, + * executed during discover targets, will read from the SPD and set the + * CHIP_ID, EC, and HDAT_EC attributes with what is found there. + * + * @param[in] i_target Presence detect target + * + * @return errlHndl_t An error log if reading from the SPD failed. + * Otherwise, other errors are predictive and + * committed. So nullptr will be returned in those + * cases and on success. + */ +errlHndl_t ocmbIdecPhase1(const TARGETING::TargetHandle_t& i_target); + +/** + * @brief Once the OCMB is able to be read from the second phase will execute + * and cross-check the data given from the SPD is consistent with what + * was read from the chip itself. If the data is not consistent then the + * CHIP_ID, EC, and HDAT_EC attributes will be updated with what was + * found from the OCMB read since that data would be correct. + * + * @param[in] i_target Presence detect target + * + * @return errlHndl_t An error log if reading from the OCMB ID/EC + * register failed. Otherwise, other errors are + * predictive and committed. So nullptr will be + * returned in those cases and on success. + */ +errlHndl_t ocmbIdecPhase2(const TARGETING::TargetHandle_t& i_target); + +/** + * @brief Read the chipid and EC/DD-level for OCMB chips and set the attributes. + * In this function there are two phases that are executed at different + * times during IPL. The OCMB is held in reset and unable to be read from + * during early IPL. So the first phase, executed during discover + * targets, will read from the SPD and set the attributes with what is + * found there. Once the OCMB is able to be read from the second phase + * will execute and cross-check the data given from the SPD is consistent + * with what was read from the chip itself. If the data is not consistent + * then the attributes will be updated with what was found from the OCMB + * read since that data would be correct. + * + * @param[in] i_opType Operation type, see DeviceFW::OperationType + * in driverif.H + * + * @param[in] i_target Presence detect target + * + * @param[in/out] io_buffer Unused by this function + * + * @param[in/out] io_buflen Unused by this function + * + * @param[in] i_accessType DeviceFW::AccessType enum (userif.H) + * + * @param[in] i_args This is an argument list for DD framework. + * In this function, there is one argument to + * signal which phase to execute. + * + * @return errlHndl_t If there is an issue while reading from the SPD + * or the OCMB chip, or an unexpected memory + * interface type then this function will return an + * error. Otherwise, all other errors are + * predictive and committed. So nullptr will be + * returned in that case or on success. + */ errlHndl_t ocmbIDEC(DeviceFW::OperationType i_opType, TARGETING::Target* i_target, void* io_buffer, @@ -241,16 +314,456 @@ errlHndl_t ocmbIDEC(DeviceFW::OperationType i_opType, int64_t i_accessType, va_list i_args) { - // for now just hardcode the answer to something explicitly invalid - uint8_t l_ec = INVALID__ATTR_EC; - i_target->setAttr<TARGETING::ATTR_EC>(l_ec); - i_target->setAttr<TARGETING::ATTR_HDAT_EC>(l_ec); + errlHndl_t error = nullptr; + + // Determine which phase of this function to run. + uint64_t phase = va_arg(i_args, uint64_t); + + // Execute the correct phase based on the va_arg given. + if (phase == 1) + { + error = ocmbIdecPhase1(i_target); + } + else + { + error = ocmbIdecPhase2(i_target); + } + + + return error; +} + +/** + * @brief This is a small helper function that the ocmb IDEC functions use to + * add all the proper callouts and commit errorlogs. + * + * @param[in] i_target Presence detect target + * + * @param[in] io_error The error log to be committed + * + */ +void ocmbErrlCommit(const TARGETING::TargetHandle_t& i_target, + errlHndl_t& io_error) +{ + io_error->addHwCallout(i_target, + SRCI_PRIORITY_HIGH, + NO_DECONFIG, + GARD_NULL); + + io_error->addPartCallout(i_target, + VPD_PART_TYPE, + SRCI_PRIORITY_MED, + NO_DECONFIG, + GARD_NULL); + + io_error->addProcedureCallout(EPUB_PRC_HB_CODE, + SRCI_PRIORITY_LOW); - // we can assume this is an Explorer chip though - uint32_t l_id = POWER_CHIPID::EXPLORER_16; - i_target->setAttr<TARGETING::ATTR_CHIP_ID>(l_id); + ERRORLOG::errlCommit(io_error, HWAS_COMP_ID); + +} + +/** + * @brief This helper function will lookup the chip id and ec levels of + * a given OCMB based on what is found in a provided SPD buffer. + * The target is passed along for trace information. + * + * @param[in] i_target OCMB target we are looking up IDEC for + * + * @param[in] i_spdBuffer Buffer of at least SPD::OCMB_SPD_EFD_COMBINED_SIZE + * bytes of the given OCMB's SPD + * + * @param[out] o_chipId Chip Id associated with the given OCMB + * (see src/import/chips/common/utils/chipids.H) + * + * @param[out] o_ec EC level associated with the given OCMB + * + * @return nullptr if success, error log otherwise + * + */ +errlHndl_t getOcmbIdecFromSpd(const TARGETING::TargetHandle_t& i_target, + uint8_t * i_spdBuffer, + uint16_t& o_chipId, + uint8_t& o_ec) +{ + errlHndl_t l_errl = nullptr; + // These bytes are used for FFDC and verification purposes. + const size_t SPD_REVISION_OFFSET = 1; + const size_t DRAM_INTERFACE_TYPE_OFFSET = 2; + const size_t MEMORY_MODULE_INTERFACE_TYPE_OFFSET = 3; + + // This is the value that signifies the SPD we read is for a DDIMM. + const uint8_t DDIMM_MEMORY_INTERFACE_TYPE = 0x0A; + + const uint8_t l_spdModuleRevision = + *(i_spdBuffer + SPD_REVISION_OFFSET); + + const uint8_t l_spdDRAMInterfaceType = + *(i_spdBuffer + DRAM_INTERFACE_TYPE_OFFSET); + + const uint8_t l_spdMemoryInterfaceType = + *(i_spdBuffer + MEMORY_MODULE_INTERFACE_TYPE_OFFSET); + + // Byte 1 SPD Module Revision + // Byte 2 DRAM Interface Type Presented or Emulated + // Byte 3 Memory Module Interface Type + const uint32_t SPD_FFDC_BYTES = TWO_UINT16_TO_UINT32( + TWO_UINT8_TO_UINT16(l_spdModuleRevision, l_spdDRAMInterfaceType), + TWO_UINT8_TO_UINT16(l_spdMemoryInterfaceType, 0)); + + do{ + + // Since the byte offsets used to get the IDEC info out of the SPD are + // specific to the DDIMM interface type we must first verify that we + // read from an SPD of that type. + if (DDIMM_MEMORY_INTERFACE_TYPE != l_spdMemoryInterfaceType) + { + HWAS_ERR("getOcmbIdecFromSpd> memory module interface type " + "didn't match the expected type. " + "Expected 0x%.2X, Actual 0x%.2X", + DDIMM_MEMORY_INTERFACE_TYPE, + l_spdMemoryInterfaceType); + + /*@ + * @errortype + * @severity ERRL_SEV_UNRECOVERABLE + * @moduleid MOD_OCMB_IDEC + * @reasoncode RC_OCMB_INTERFACE_TYPE_MISMATCH + * @userdata1[0:7] SPD Module Revision + * @userdata1[8:15] DRAM Interface Type Presented or Emulated + * @userdata1[16:23] Memory Module Interface Type + * @userdata1[24:31] Unused + * @userdata1[32:63] Expected memory interface type + * @userdata2 HUID of OCMB target + * @devdesc The memory interface type read from the SPD did + * not match the DDIMM value. Setting the + * appropriate IDEC values for this target cannot + * continue. + * @custdesc Invalid or unsupported memory card installed. + */ + l_errl = hwasError(ERRORLOG::ERRL_SEV_UNRECOVERABLE, + MOD_OCMB_IDEC, + RC_OCMB_INTERFACE_TYPE_MISMATCH, + TWO_UINT32_TO_UINT64(SPD_FFDC_BYTES, + DDIMM_MEMORY_INTERFACE_TYPE), + TARGETING::get_huid(i_target)); + + l_errl->addProcedureCallout(EPUB_PRC_HB_CODE, + SRCI_PRIORITY_LOW); + + l_errl->addHwCallout(i_target, + SRCI_PRIORITY_HIGH, + NO_DECONFIG, + GARD_NULL); + + + break; + } + + // SPD IDEC info is in the following three bytes + const size_t SPD_ID_LEAST_SIGNIFICANT_BYTE_OFFSET = 198; + const size_t SPD_ID_MOST_SIGNIFICANT_BYTE_OFFSET = 199; + const size_t DMB_REV_OFFSET = 200; + + // Get the ID from the SPD and verify that it matches what we read from + // the IDEC register. + uint16_t l_spdId = TWO_UINT8_TO_UINT16( + *(i_spdBuffer + SPD_ID_LEAST_SIGNIFICANT_BYTE_OFFSET), + *(i_spdBuffer + SPD_ID_MOST_SIGNIFICANT_BYTE_OFFSET)); + + // Bytes 200 of the SPD contains the DMB Revision, this is essentially the + // OCMB manufacture's version of the chip. The manufacture can define any + // format for this field and we must add special logic to convert the + // manufacture's DMB_REV to the EC level IBM is familiar with. + uint8_t l_spdDmbRev = *(i_spdBuffer + DMB_REV_OFFSET); + + HWAS_INF("getOcmbIdecFromSpd> OCMB 0x%.8x l_spdId = 0x%.4X l_spdDmbRev = 0x%.2x", + TARGETING::get_huid(i_target), l_spdId, l_spdDmbRev); + + if (DDIMM_DMB_ID::EXPLORER == l_spdId) + { + o_chipId = POWER_CHIPID::EXPLORER_16; + // Must convert Explorer's versioning into IBM-style EC levels. + // Explorer vendor has stated versioning will start at 0xA0 and increment + // 1st nibble for major revisions and 2nd nibble by 1 for minor revisions + // Examples : + // Version 0xA0 = EC 0x10 + // Version 0xA1 = EC 0x11 + // Version 0xB2 = EC 0x22 + + // Resulting formula from pattern in examples above is as follows: + o_ec = (l_spdDmbRev - 0x90); + } + else if (DDIMM_DMB_ID::GEMINI == l_spdId) + { + o_chipId = POWER_CHIPID::GEMINI_16; + + HWAS_ASSERT(l_spdDmbRev == 0x0, + "Invalid Gemini DMB Revision Number, expected to find 0x0 at byte 200 in Gemini SPD"); + + // 0x10 is the only valid EC level for Gemini cards. If we find 0x0 @ byte 200 in + // the Gemini SPD then we will return 0x10 as the EC level + o_ec = 0x10; + } + else + { + HWAS_ERR("getOcmbIdecFromSpd> Unknown OCMB chip type discovered in SPD " + "ID=0x%.4X OCMB HUID 0x%.8x", + l_spdId, + TARGETING::get_huid(i_target)); + + /*@ + * @errortype + * @severity ERRL_SEV_PREDICTIVE + * @moduleid MOD_OCMB_IDEC + * @reasoncode RC_OCMB_UNKNOWN_CHIP_TYPE + * @userdata1[0:7] SPD Module Revision + * @userdata1[8:15] DRAM Interface Type Presented or Emulated + * @userdata1[16:23] Memory Module Interface Type + * @userdata1[24:31] Unused + * @userdata1[32:63] SPD Chip Id + * @userdata2 HUID of OCMB target + * @devdesc The ID read from the SPD didn't match any known + * OCMB chip types. + * @custdesc Unsupported memory installed. + */ + l_errl = hwasError(ERRORLOG::ERRL_SEV_PREDICTIVE, + MOD_OCMB_IDEC_PHASE_1, + RC_OCMB_UNKNOWN_CHIP_TYPE, + TWO_UINT32_TO_UINT64(SPD_FFDC_BYTES, l_spdId), + TARGETING::get_huid(i_target)); + + break; + } + + }while(0); + + return l_errl; + +} + + +errlHndl_t ocmbIdecPhase1(const TARGETING::TargetHandle_t& i_target) +{ + errlHndl_t l_errl = nullptr; + + // Allocate buffer to hold SPD and init to 0 + size_t l_spdBufferSize = SPD::DDIMM_DDR4_SPD_SIZE; + uint8_t* l_spdBuffer = new uint8_t[l_spdBufferSize]; + memset(l_spdBuffer, 0, l_spdBufferSize); + uint16_t l_chipId = 0; + uint8_t l_chipEc = 0; + + do { + + // Read the SPD off the ocmb but skip reading the EFD to save time. + l_errl = deviceRead(i_target, + l_spdBuffer, + l_spdBufferSize, + DEVICE_SPD_ADDRESS(SPD::ENTIRE_SPD_WITHOUT_EFD)); + + // If unable to retrieve the SPD buffer then can't + // extract the IDEC data, so return error. + if (l_errl != nullptr) + { + HWAS_ERR("ocmbIdecPhase1> Error while trying to read " + "ENTIRE SPD from 0x%.08X ", + TARGETING::get_huid(i_target)); + break; + } + + // Make sure we got back the size we were expecting. + assert(l_spdBufferSize == SPD::DDIMM_DDR4_SPD_SIZE, + "ocmbIdecPhase1> OCMB SPD read size %d " + "doesn't match the expected size %d", + l_spdBufferSize, + SPD::DDIMM_DDR4_SPD_SIZE); + + l_errl = getOcmbIdecFromSpd(i_target, + l_spdBuffer, + l_chipId, + l_chipEc); + + // If we were unable to read the IDEC information from the SPD + // then break out early and do not set the associated attributes + if (l_errl != nullptr) + { + HWAS_ERR("ocmbIdecPhase1> Error while trying to parse " + "chip id and ec values from SPD read from OCMB 0x%.08X ", + TARGETING::get_huid(i_target)); + break; + } + + HWAS_INF("ocmbIdecPhase1> Read Chip ID = 0x%x Chip EC = 0x%x from target 0x%.08X", + l_chipId, l_chipEc, TARGETING::get_huid(i_target) ); + + // set the explorer chip EC attributes. + i_target->setAttr<TARGETING::ATTR_EC>(l_chipEc); + i_target->setAttr<TARGETING::ATTR_HDAT_EC>(l_chipEc); + + // set the explorer chip id attribute. + i_target->setAttr<TARGETING::ATTR_CHIP_ID>(l_chipId); + + } while(0); + + delete[] l_spdBuffer; + return l_errl; + +} + +errlHndl_t ocmbIdecPhase2(const TARGETING::TargetHandle_t& i_target) +{ + const uint32_t GEM_IDEC_SCOM_REGISTER = 0x0801240e; + const TARGETING::ATTR_CHIP_ID_type l_chipIdFromSpd = + i_target->getAttr<TARGETING::ATTR_CHIP_ID>(); + + errlHndl_t l_errl = nullptr; + uint64_t l_idec = 0; + size_t l_op_size = sizeof(l_idec); + uint8_t l_ec = 0; + uint16_t l_id = 0; + + do { + + if(l_chipIdFromSpd == POWER_CHIPID::EXPLORER_16) + { + // Call platform independent lookup for Explorer OCMBs + l_errl = FAPIWRAP::explorer_getidec(i_target, l_id, l_ec); + + if (l_errl != nullptr) + { + HWAS_ERR("ocmbIdecPhase2> explorer OCMB 0x%.8X - failed to read ID/EC", + TARGETING::get_huid(i_target)); + + break; + } + } + else + { + // read the register containing IDEC info on Gemini OCMBs + l_errl = DeviceFW::deviceRead(i_target, + &l_idec, + l_op_size, + DEVICE_SCOM_ADDRESS(GEM_IDEC_SCOM_REGISTER)); + + if (l_errl != nullptr) + { + HWAS_ERR("ocmbIdecPhase2> gemini OCMB 0x%.8X - failed to read ID/EC", + TARGETING::get_huid(i_target)); + + break; + } + + // Need to convert Gemini's IDEC register from MmL000CC + // to cfam standard format MLmCC000 + uint32_t l_major = 0xF0000000 & static_cast<uint32_t>(l_idec); + uint32_t l_minor = 0x0F000000 & static_cast<uint32_t>(l_idec); + uint32_t l_location = 0x00F00000 & static_cast<uint32_t>(l_idec); + l_idec = (l_major | (l_location << 4) | (l_minor >> 4) + | ((l_idec & 0x000000FF) << 12)); + // Parse out the information we need + l_ec = POWER_CHIPID::extract_ddlevel(l_idec); + l_id = POWER_CHIPID::extract_chipid16(l_idec); + } + + HWAS_INF("ocmbIdecPhase2> OCMB 0x%.8X - read ID/EC successful. " + "ID = 0x%.4X, EC = 0x%.2X, Full IDEC 0x%x", + TARGETING::get_huid(i_target), + l_id, + l_ec, + l_idec); + + if (l_id != l_chipIdFromSpd) + { + HWAS_ERR("ocmbIdecPhase2> OCMB Chip Id and associated SPD Chip Id " + "don't match: OCMB ID=0x%.4X; SPD ID=0x%.4X;", + l_id, + l_chipIdFromSpd); + + HWAS_ERR("ocmbIdecPhase2> Previous CHIP_ID 0x%.4X was set based on values from " + "SPD read will now be overwritten with values from OCMB IDEC register " + "ID=0x%.4X", + l_chipIdFromSpd, + l_id); + /*@ + * @errortype + * @severity ERRL_SEV_PREDICTIVE + * @moduleid MOD_OCMB_IDEC + * @reasoncode RC_OCMB_CHIP_ID_MISMATCH + * @userdata1[00:31] OCMB IDEC Register ID + * @userdata1[32:63] IDEC ID found in OCMB's SPD + * @userdata2[32:63] HUID of OCMB target + * @devdesc The IDEC info read from the OCMB and SPD + * did not match the expected values. + * @custdesc Firmware Error + */ + l_errl = hwasError(ERRORLOG::ERRL_SEV_PREDICTIVE, + MOD_OCMB_IDEC, + RC_OCMB_CHIP_ID_MISMATCH, + TWO_UINT32_TO_UINT64(l_id, l_chipIdFromSpd), + TARGETING::get_huid(i_target)); + + // Add callouts and commit + ocmbErrlCommit(i_target, l_errl); + + // Since there was an error then the ID values don't agree between + // the OCMB read and the SPD read. Since the OCMB has the correct + // answer, set the attributes to the values read from that instead + // of the SPD. + i_target->setAttr<TARGETING::ATTR_CHIP_ID>(l_id); + } + + const uint8_t l_ecFromSpd = i_target->getAttr<TARGETING::ATTR_EC>(); + + if (l_ec != l_ecFromSpd) + { + HWAS_ERR("ocmbIdecPhase2> OCMB Revision and associated SPD " + "Revision don't match: OCMB EC=0x%.2X; " + "SPD EC=0x%.2X; ", + l_ec, l_ecFromSpd); + + HWAS_ERR("ocmbIdecPhase2> Previous EC and HDAT_EC attributes 0x%.2X," + " which were set with values found in SPD will be overwritten" + " with value from OCMB IDEC register ID=0x%.2X", + l_ecFromSpd, + l_ec); + + /*@ + * @errortype + * @severity ERRL_SEV_PREDICTIVE + * @moduleid MOD_OCMB_IDEC + * @reasoncode RC_OCMB_SPD_REVISION_MISMATCH + * @userdata1[00:31] OCMB IDEC register EC + * @userdata1[32:63] EC found in OCMB's SPD + * @userdata2[00:31] OCMB Chip ID Attribute + * @userdata2[32:63] HUID of OCMB target + * @devdesc The EC (Revision) info read from the OCMB and + * SPD did not match the expected values. + * @custdesc Firmware Error + */ + l_errl = hwasError(ERRORLOG::ERRL_SEV_PREDICTIVE, + MOD_OCMB_IDEC, + RC_OCMB_SPD_REVISION_MISMATCH, + TWO_UINT32_TO_UINT64(l_ec, l_ecFromSpd), + TWO_UINT32_TO_UINT64( + i_target->getAttr<TARGETING::ATTR_CHIP_ID>(), + TARGETING::get_huid(i_target))); + + // Add callouts and commit + ocmbErrlCommit(i_target, l_errl); + + // Since there was an error then the EC values don't agree between + // the OCMB read and the SPD read. Since the OCMB has the correct + // answer, set the attributes to the values read from that instead + // of the SPD. + i_target->setAttr<TARGETING::ATTR_EC>(l_ec); + i_target->setAttr<TARGETING::ATTR_HDAT_EC>(l_ec); + } + + } while(0); + + return l_errl; - return nullptr; } // Register the presence detect function with the device framework @@ -628,7 +1141,10 @@ errlHndl_t platPresenceDetect(TargetHandleList &io_targets) DEVICE_CACHE_EEPROM_ADDRESS(present, EEPROM::VPD_PRIMARY)); errl = deviceRead(pTarget, &present, presentSize, DEVICE_CACHE_EEPROM_ADDRESS(present, EEPROM::VPD_PRIMARY)); - errlCommit(errl, HWAS_COMP_ID); + if( errl ) + { + errlCommit(errl, HWAS_COMP_ID); + } // errl is now null, move on to next target } #endif diff --git a/src/usr/hwas/hwasPlatDeconfigGard.C b/src/usr/hwas/hwasPlatDeconfigGard.C index 0bdbb4c24..3f5a461eb 100644 --- a/src/usr/hwas/hwasPlatDeconfigGard.C +++ b/src/usr/hwas/hwasPlatDeconfigGard.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2018 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] Google Inc. */ /* [+] International Business Machines Corp. */ /* */ @@ -41,7 +41,6 @@ #include <vpd/mvpdenums.H> #include <stdio.h> #include <sys/mm.h> -#include <config.h> #include <initservice/istepdispatcherif.H> #include <initservice/initserviceif.H> diff --git a/src/usr/hwas/test/hwas1test.H b/src/usr/hwas/test/hwas1test.H index 6784d4408..306fea006 100644 --- a/src/usr/hwas/test/hwas1test.H +++ b/src/usr/hwas/test/hwas1test.H @@ -48,8 +48,74 @@ #include <targeting/common/commontargeting.H> #include <targeting/common/utilFilter.H> +const uint16_t pgDataAllGoodAxone[HWAS::VPD_CP00_PG_DATA_ENTRIES] = + {(uint16_t)HWAS::VPD_CP00_PG_FSI_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_PERVASIVE_GOOD_AXONE, + (uint16_t)HWAS::VPD_CP00_PG_N0_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_N1_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_N2_GOOD_AXONE, + (uint16_t)HWAS::VPD_CP00_PG_N3_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_XBUS_GOOD_CUMULUS, + (uint16_t)HWAS::VPD_CP00_PG_MCxx_GOOD_AXONE, + (uint16_t)HWAS::VPD_CP00_PG_MCxx_GOOD_AXONE, + (uint16_t)HWAS::VPD_CP00_PG_OBUS_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_OBUS_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_OBUS_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_OBUS_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_PCIx_GOOD[0], + (uint16_t)HWAS::VPD_CP00_PG_PCIx_GOOD[1], + (uint16_t)HWAS::VPD_CP00_PG_PCIx_GOOD[2], + (uint16_t)HWAS::VPD_CP00_PG_EPx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_EPx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_EPx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_EPx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_EPx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_EPx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD}; + // Buffer with all good data (CUMULUS chip) -const uint16_t pgDataAllGood[HWAS::VPD_CP00_PG_DATA_ENTRIES] = +const uint16_t pgDataAllGoodCumulus[HWAS::VPD_CP00_PG_DATA_ENTRIES] = {(uint16_t)HWAS::VPD_CP00_PG_FSI_GOOD, (uint16_t)HWAS::VPD_CP00_PG_PERVASIVE_GOOD, (uint16_t)HWAS::VPD_CP00_PG_N0_GOOD, @@ -371,9 +437,20 @@ public: ? (uint16_t)VPD_CP00_PG_RESERVED_GOOD : (uint16_t)VPD_CP00_PG_OBUS_GOOD; uint16_t pgData[VPD_CP00_PG_DATA_ENTRIES]; - memcpy(pgData, - pgDataAllGood, - VPD_CP00_PG_DATA_LENGTH); + + if(MODEL_AXONE == l_model) + { + memcpy(pgData, + pgDataAllGoodAxone, + VPD_CP00_PG_DATA_LENGTH); + } + else + { + memcpy(pgData, + pgDataAllGoodCumulus, + VPD_CP00_PG_DATA_LENGTH); + } + pgData[VPD_CP00_PG_XBUS_INDEX] = l_xbus; pgData[VPD_CP00_PG_OB0_INDEX + 1] = l_obus12; pgData[VPD_CP00_PG_OB0_INDEX + 2] = l_obus12; @@ -460,9 +537,18 @@ public: l_mask); } - // Restore the "all good" data - pgData[VPD_CP00_PG_PERVASIVE_INDEX] = - (uint16_t)VPD_CP00_PG_PERVASIVE_GOOD; + if(MODEL_AXONE == l_model) + { + // Restore the "all good" data + pgData[VPD_CP00_PG_PERVASIVE_INDEX] = + (uint16_t)VPD_CP00_PG_PERVASIVE_GOOD_AXONE; + } + else + { + // Restore the "all good" data + pgData[VPD_CP00_PG_PERVASIVE_INDEX] = + (uint16_t)VPD_CP00_PG_PERVASIVE_GOOD; + } } TS_INFO( "testHWASisChipFunctional: N0 is not functional"); @@ -562,6 +648,19 @@ public: // Restore the "all good" data pgData[VPD_CP00_PG_N2_INDEX] = (uint16_t)VPD_CP00_PG_N2_GOOD; + + if(MODEL_AXONE == l_model) + { + // Restore the "all good" data + pgData[VPD_CP00_PG_N2_INDEX] = + (uint16_t)VPD_CP00_PG_N2_GOOD_AXONE; + } + else + { + // Restore the "all good" data + pgData[VPD_CP00_PG_N2_INDEX] = + (uint16_t)VPD_CP00_PG_N2_GOOD; + } } TS_INFO( "testHWASisChipFunctional: N3 is not functional"); @@ -686,9 +785,20 @@ public: ? (uint16_t)VPD_CP00_PG_RESERVED_GOOD : (uint16_t)VPD_CP00_PG_OBUS_GOOD; uint16_t pgData[VPD_CP00_PG_DATA_ENTRIES]; - memcpy(pgData, - pgDataAllGood, - VPD_CP00_PG_DATA_LENGTH); + + if(MODEL_AXONE == l_model) + { + memcpy(pgData, + pgDataAllGoodAxone, + VPD_CP00_PG_DATA_LENGTH); + } + else + { + memcpy(pgData, + pgDataAllGoodCumulus, + VPD_CP00_PG_DATA_LENGTH); + } + pgData[VPD_CP00_PG_XBUS_INDEX] = l_xbus; pgData[VPD_CP00_PG_OB0_INDEX + 1] = l_obus12; pgData[VPD_CP00_PG_OB0_INDEX + 2] = l_obus12; @@ -1107,9 +1217,19 @@ public: pDesc->getAttr<ATTR_HUID>()); } - // Restore the "all good" data - pgData[l_indexMC] = VPD_CP00_PG_MCxx_GOOD; + if(MODEL_AXONE == l_model) + { + // Restore the "all good" data + pgData[l_indexMC] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD_AXONE; + } + else + { + // Restore the "all good" data + pgData[l_indexMC] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD; + } } break; @@ -1208,8 +1328,18 @@ public: pDesc->getAttr<ATTR_HUID>()); } - // Restore the "all good" data - pgData[l_indexMC] = VPD_CP00_PG_MCxx_GOOD; + if(MODEL_AXONE == l_model) + { + // Restore the "all good" data + pgData[l_indexMC] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD_AXONE; + } + else + { + // Restore the "all good" data + pgData[l_indexMC] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD; + } } break; @@ -1307,8 +1437,18 @@ public: pDesc->getAttr<ATTR_HUID>()); } - // Restore the "all good" data - pgData[l_indexMC] = VPD_CP00_PG_MCxx_GOOD; + if(MODEL_AXONE == l_model) + { + // Restore the "all good" data + pgData[l_indexMC] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD_AXONE; + } + else + { + // Restore the "all good" data + pgData[l_indexMC] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD; + } } break; @@ -1406,8 +1546,18 @@ public: pDesc->getAttr<ATTR_HUID>()); } - // Restore the "all good" data - pgData[l_indexMC] = VPD_CP00_PG_MCxx_GOOD; + if(MODEL_AXONE == l_model) + { + // Restore the "all good" data + pgData[l_indexMC] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD_AXONE; + } + else + { + // Restore the "all good" data + pgData[l_indexMC] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD; + } } break; @@ -1506,8 +1656,18 @@ public: pDesc->getAttr<ATTR_HUID>()); } - // Restore the "all good" data - pgData[l_indexMC] = VPD_CP00_PG_MCxx_GOOD; + if(MODEL_AXONE == l_model) + { + // Restore the "all good" data + pgData[l_indexMC] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD_AXONE; + } + else + { + // Restore the "all good" data + pgData[l_indexMC] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD; + } } break; @@ -1871,9 +2031,18 @@ public: pDesc->getAttr<ATTR_HUID>()); } - // Restore the "all good" data - pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit * 2]] = - (uint16_t)VPD_CP00_PG_MCxx_GOOD; + if(MODEL_AXONE == l_model) + { + // Restore the "all good" data + pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit * 2]] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD_AXONE; + } + else + { + // Restore the "all good" data + pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit * 2]] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD; + } } @@ -1987,9 +2156,18 @@ public: pDesc->getAttr<ATTR_HUID>()); } - // Restore the "all good" data - pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit]] = - (uint16_t)VPD_CP00_PG_MCxx_GOOD; + if(MODEL_AXONE == l_model) + { + // Restore the "all good" data + pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit]] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD_AXONE; + } + else + { + // Restore the "all good" data + pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit]] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD; + } } // TEST WITH BAD MAGIC PORT (MCA0 or MCA4) @@ -2038,8 +2216,18 @@ public: pDesc->getAttr<ATTR_HUID>()); } - pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit / 2]] = - (uint16_t)VPD_CP00_PG_MCxx_GOOD; + if(MODEL_AXONE == l_model) + { + // Restore the "all good" data + pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit / 2]] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD_AXONE; + } + else + { + // Restore the "all good" data + pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit / 2]] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD; + } // Try bad MCA Port setting for MCA2/3 & MCA6/7 if ( VPD_CP00_PG_MCxx_IOMyy[l_chipUnit / 2] != @@ -2147,14 +2335,26 @@ public: } // Restore the "all good" data - pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit * 2]] = - (uint16_t)VPD_CP00_PG_MCxx_GOOD; + if(MODEL_AXONE == l_model) + { + // Restore the "all good" data + pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit * 2]] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD_AXONE; + } + else + { + // Restore the "all good" data + pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit * 2]] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD; + } + } break; case TYPE_OBUS_BRICK: { +#ifndef CONFIG_AXONE //@todo-RTC:208518 - Add Axone OBUS_BRICK rules //Two cases here: //OBUS==SMP --> Target should be present regardless // of PG @@ -2186,7 +2386,7 @@ public: TS_FAIL("testHWAS" "checkPartialGoodForDescendants> " "functional = 0x%x, should be true " - "because" + "because " "OBUS_BRICK is SMP: PG = 0x%04x. " "pDesc HUID 0x%.8x", checkPartialGoodForDescendants( @@ -2211,7 +2411,7 @@ public: TS_FAIL("testHWAS" "checkPartialGoodForDescendants> " "functional = 0x%x, should be " - "false because" + "false because " "OBUS_BRICK is NVLINK: PG = " "0x%04x. " "pDesc HUID 0x%.8x", @@ -2227,10 +2427,12 @@ public: pgData[VPD_CP00_PG_N3_INDEX] = (uint16_t)VPD_CP00_PG_N3_GOOD; +#endif break; } case TYPE_NPU: +#ifndef CONFIG_AXONE //@todo-RTC:208518 - Add Axone NPU rules TS_INFO( "testHWAScheckPartialGoodForDescendants: " "NPU is not functional"); pgData[VPD_CP00_PG_N3_INDEX] |= @@ -2250,6 +2452,7 @@ public: pgData[VPD_CP00_PG_N3_INDEX] = (uint16_t)VPD_CP00_PG_N3_GOOD; +#endif break; case TYPE_PERV: diff --git a/src/usr/hwas/test/hwasGardTest.H b/src/usr/hwas/test/hwasGardTest.H index 01c8d1735..1edc8a445 100644 --- a/src/usr/hwas/test/hwasGardTest.H +++ b/src/usr/hwas/test/hwasGardTest.H @@ -51,7 +51,7 @@ #define DISABLE_EX_UNIT_TESTS 1 //$$#define DISABLE_UNIT_TESTS 0 -#define DISABLE_OMI_UNIT_TESTS 0 +#define DISABLE_OMI_UNIT_TESTS 1 #if DISABLE_OMI_UNIT_TESTS #define ENABLE_OMI_UNIT_TEST_1 0 diff --git a/src/usr/hwplibs/nest/nestmemutils.mk b/src/usr/hwplibs/nest/nestmemutils.mk index 26b6a406c..9962f3b0e 100644 --- a/src/usr/hwplibs/nest/nestmemutils.mk +++ b/src/usr/hwplibs/nest/nestmemutils.mk @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2017,2018 +# Contributors Listed Below - COPYRIGHT 2017,2019 # [+] International Business Machines Corp. # # @@ -26,15 +26,26 @@ ROOTPATH=../../../.. +P9_PROCEDURE_PATH = ${ROOTPATH}/src/import/chips/p9/procedures/ HWP_NEST_MEM_UTILS_PATH := ${ROOTPATH}/src/import/chips/p9/procedures/hwp/nest/ +EXP_COMMON_PATH = ${ROOTPATH}/src/import/chips/ocmb/explorer/common +AXONE_PROCEDURE_PATH = ${ROOTPATH}/src/import/chips/p9a/procedures EXTRAINCDIR += ${HWP_NEST_MEM_UTILS_PATH} EXTRAINCDIR += ${ROOTPATH}/src/include/usr/fapi2/ EXTRAINCDIR += ${ROOTPATH}/src/import/hwpf/fapi2/include EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/utils/imageProcs +EXTRAINCDIR += ${EXP_COMMON_PATH}/include/ +EXTRAINCDIR += ${ROOTPATH}/obj/genfiles/ +EXTRAINCDIR += ${ROOTPATH}/src/import/ +EXTRAINCDIR += ${AXONE_PROCEDURE_PATH}/hwp/memory/ +EXTRAINCDIR += ${P9_PROCEDURE_PATH}/hwp/memory VPATH += ${HWP_NEST_MEM_UTILS_PATH} include ${ROOTPATH}/procedure.rules.mk include ${HWP_NEST_MEM_UTILS_PATH}/p9_putmemproc.mk +OBJS += $(if $(CONFIG_AXONE),p9a_throttle_sync.o,p9_throttle_sync.o) + +include ${ROOTPATH}/config.mk diff --git a/src/usr/i2c/eepromCache.C b/src/usr/i2c/eepromCache.C index ef906302c..bbdddf334 100644 --- a/src/usr/i2c/eepromCache.C +++ b/src/usr/i2c/eepromCache.C @@ -30,17 +30,18 @@ #include <devicefw/driverif.H> #include <errl/errlmanager.H> #include <fsi/fsiif.H> +#include <hwas/hwasPlat.H> #include "i2c.H" #include "eepromCache.H" #include <i2c/i2cif.H> -#include <i2c/eepromif.H> + #include <i2c/eepromddreasoncodes.H> #include <initservice/initserviceif.H> #include <initservice/initsvcreasoncodes.H> #include <pnor/pnorif.H> #include <vpd/vpd_if.H> + #include <errl/errludtarget.H> -#include <config.h> #ifdef CONFIG_CONSOLE #include <console/consoleif.H> #endif @@ -53,6 +54,10 @@ extern trace_desc_t* g_trac_eeprom; namespace EEPROM { +// Any time we access either any of the global variables defined below we want +// to wrap the call in this mutex to avoid multi-threading issues +mutex_t g_eecacheMutex = MUTEX_INITIALIZER; + // Global variable that will keep track of the virtual address which // points to the start of the EECACHE section, and the size of this section. // It is handy to keep these around so we do not need to look them up in the @@ -63,166 +68,10 @@ uint64_t g_eecachePnorSize = 0; // Global map which is used as a way to quickly look up the virtual address // of a given eeprom's cached data in EECACHE section // Key = eepromRecordHeader with unique info filled out -// Value = virtual address pointing to the cached eeprom data in pnor -std::map<eepromRecordHeader, uint64_t> g_cachedEeproms; - -// Any time we access either any of the global variables defined above we want -// to wrap the call in this mutex to avoid multi-threading issues -mutex_t g_eecacheMutex = MUTEX_INITIALIZER; - -uint64_t lookupEepromAddr(const eepromRecordHeader& i_eepromRecordHeader) -{ - uint64_t l_vaddr = 0; - std::map<eepromRecordHeader, uint64_t>::iterator l_it; - - // Wrap lookup in mutex because reads are not thread safe - mutex_lock(&g_eecacheMutex); - l_it = g_cachedEeproms.find(i_eepromRecordHeader); - mutex_unlock(&g_eecacheMutex); - - if(l_it != g_cachedEeproms.end()) - { - l_vaddr = l_it->second; - } - - if(l_vaddr == 0) - { - TRACSSCOMP( g_trac_eeprom, "lookupEepromAddr() failed to find I2CM Huid: 0x%.08X, Port: 0x%.02X, Engine: 0x%.02X, Dev Addr: 0x%.02X, Mux Select: 0x%.02X, Size: 0x%.08X in g_cachedEeproms", - i_eepromRecordHeader.completeRecord.i2c_master_huid, - i_eepromRecordHeader.completeRecord.port, - i_eepromRecordHeader.completeRecord.engine, - i_eepromRecordHeader.completeRecord.devAddr, - i_eepromRecordHeader.completeRecord.mux_select, - i_eepromRecordHeader.completeRecord.cache_copy_size); - } - return l_vaddr; -} - -errlHndl_t buildEepromRecordHeader(TARGETING::Target * i_target, - eeprom_addr_t & io_eepromInfo, - eepromRecordHeader & o_eepromRecordHeader) -{ - - TARGETING::Target * l_muxTarget = nullptr; - TARGETING::Target * l_i2cMasterTarget = nullptr; - TARGETING::TargetService& l_targetService = TARGETING::targetService(); - errlHndl_t l_errl = nullptr; - - do{ - - l_errl = eepromReadAttributes(i_target, io_eepromInfo); - if(l_errl) - { - TRACFCOMP( g_trac_eeprom, - "buildEepromRecordHeader() error occured reading eeprom attributes for eepromType %d, target 0x%.08X, returning!!", - io_eepromInfo.eepromRole, - TARGETING::get_huid(i_target)); - l_errl->collectTrace(EEPROM_COMP_NAME); - break; - } - - // Grab the I2C mux target so we can read the HUID, if the target is NULL we will not be able - // to lookup attribute to uniquely ID this eeprom so we will not cache it - l_muxTarget = l_targetService.toTarget( io_eepromInfo.i2cMuxPath); - if(l_muxTarget == nullptr) - { - TRACFCOMP( g_trac_eeprom, - "buildEepromRecordHeader() Mux target associated with target 0x%.08X resolved to a nullptr , check attribute for eepromType %d. Skipping Cache", - TARGETING::get_huid(i_target), - io_eepromInfo.eepromRole); - /*@ - * @errortype - * @moduleid EEPROM_CACHE_EEPROM - * @reasoncode EEPROM_I2C_MUX_PATH_ERROR - * @userdata1 HUID of target we want to cache - * @userdata2 Type of EEPROM we are caching - * @devdesc buildEepromRecordHeader invalid mux target - */ - l_errl = new ERRORLOG::ErrlEntry( - ERRORLOG::ERRL_SEV_UNRECOVERABLE, - EEPROM_CACHE_EEPROM, - EEPROM_I2C_MUX_PATH_ERROR, - TARGETING::get_huid(i_target), - io_eepromInfo.eepromRole, - ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); - l_errl->collectTrace(EEPROM_COMP_NAME); - break; - } - - // Grab the I2C master target so we can read the HUID, if the target is NULL we will not be able - // to lookup attribute to uniquely ID this eeprom so we will not cache it - l_i2cMasterTarget = l_targetService.toTarget( io_eepromInfo.i2cMasterPath ); - if(l_i2cMasterTarget == nullptr) - { - TRACFCOMP( g_trac_eeprom, - "buildEepromRecordHeader() I2C Master target associated with target 0x%.08X resolved to a nullptr , check attribute for eepromType %d. Skipping Cache ", - TARGETING::get_huid(i_target), - io_eepromInfo.eepromRole); - /*@ - * @errortype - * @moduleid EEPROM_CACHE_EEPROM - * @reasoncode EEPROM_I2C_MASTER_PATH_ERROR - * @userdata1 HUID of target we want to cache - * @userdata2 Type of EEPROM we are caching - * @devdesc buildEepromRecordHeader invalid master target - */ - l_errl = new ERRORLOG::ErrlEntry( - ERRORLOG::ERRL_SEV_UNRECOVERABLE, - EEPROM_CACHE_EEPROM, - EEPROM_I2C_MASTER_PATH_ERROR, - TARGETING::get_huid(i_target), - io_eepromInfo.eepromRole, - ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); - l_errl->collectTrace(EEPROM_COMP_NAME); - break; - } - - // This is what we will compare w/ when we are going through the existing - // caches in the eeprom to see if we have already cached something - // Or if no matches are found we will copy this into the header - o_eepromRecordHeader.completeRecord.i2c_master_huid = l_i2cMasterTarget->getAttr<TARGETING::ATTR_HUID>(); - o_eepromRecordHeader.completeRecord.port = static_cast<uint8_t>(io_eepromInfo.port); - o_eepromRecordHeader.completeRecord.engine = static_cast<uint8_t>(io_eepromInfo.engine); - o_eepromRecordHeader.completeRecord.devAddr = static_cast<uint8_t>(io_eepromInfo.devAddr); - o_eepromRecordHeader.completeRecord.mux_select = static_cast<uint8_t>(io_eepromInfo.i2cMuxBusSelector); - o_eepromRecordHeader.completeRecord.cache_copy_size = static_cast<uint32_t>(io_eepromInfo.devSize_KB); - - // Do not set valid bit nor internal offset here as we do not have - // enough information availible to determine - - }while(0); - - return l_errl; -} - -// Do NOT allow adding/removing eeproms to cache during RT -#ifndef __HOSTBOOT_RUNTIME - -bool addEepromToCachedList(const eepromRecordHeader & i_eepromRecordHeader) -{ - bool l_matchFound = true; - std::map<eepromRecordHeader, uint64_t>::iterator it; - - // Map accesses are not thread safe, make sure this is always wrapped in mutex - mutex_lock(&g_eecacheMutex); - - if(g_cachedEeproms.find(i_eepromRecordHeader) == g_cachedEeproms.end()) - { - g_cachedEeproms[i_eepromRecordHeader] = g_eecachePnorVaddr + i_eepromRecordHeader.completeRecord.internal_offset; - TRACSSCOMP( g_trac_eeprom, "addEepromToCachedList() Adding I2CM Huid: 0x%.08X, Port: 0x%.02X, Engine: 0x%.02X, Dev Addr: 0x%.02X, Mux Select: 0x%.02X, Size: 0x%.08X to g_cachedEeproms", - i_eepromRecordHeader.completeRecord.i2c_master_huid, - i_eepromRecordHeader.completeRecord.port, - i_eepromRecordHeader.completeRecord.engine, - i_eepromRecordHeader.completeRecord.devAddr, - i_eepromRecordHeader.completeRecord.mux_select, - i_eepromRecordHeader.completeRecord.cache_copy_size); - l_matchFound = false; - } - - mutex_unlock(&g_eecacheMutex); - - return l_matchFound; -} +// Value = A struct of 2 uint64_t virtual addresses ,one points to header address +// and other points to the location of the cache, and a byte indicating +// if this eeprom's hardware has changed this IPL +std::map<eepromRecordHeader, EeepromEntryMetaData_t> g_cachedEeproms; /** * @brief Lookup I2C information for given eeprom, check if eeprom exists in cache. @@ -252,13 +101,19 @@ errlHndl_t cacheEeprom(TARGETING::Target* i_target, bool l_updateHeader = true; bool l_updateContents = true; + // Initially assume this is a new eeprom cache entry + bool l_newEntryDetected = true; + do{ // eepromReadAttributes keys off the eepromRole value // to determine what attribute to lookup to get eeprom info l_eepromInfo.eepromRole = i_eepromType; // if the target is present, then this record is valid - l_eepromRecordHeader.completeRecord.cached_copy_valid = i_present; + if(i_present) + { + l_eepromRecordHeader.completeRecord.cached_copy_valid = 1; + } // buildEepromRecordHeader will call eepromReadAttributes to fill in l_eepromInfo // with info looked up in attributes and also fill in l_eepromRecordHeader @@ -271,7 +126,7 @@ errlHndl_t cacheEeprom(TARGETING::Target* i_target, if(l_errl) { // buildEepromRecordHeader should have traced any relavent information if - // is was needed, just break out and pass the error along + // it was needed, just break out and pass the error along break; } @@ -310,7 +165,7 @@ errlHndl_t cacheEeprom(TARGETING::Target* i_target, // if nothing has been cached before then version should // be set to be the latest version of the struct available l_eecacheSectionHeaderPtr->version = EECACHE_VERSION_LATEST; - TRACFCOMP( g_trac_eeprom, + TRACDCOMP( g_trac_eeprom, "cacheEeprom() Found Empty Cache, set version of cache structure to be 0x%.02x", EECACHE_VERSION_1); } @@ -322,7 +177,7 @@ errlHndl_t cacheEeprom(TARGETING::Target* i_target, // This means the start of first eeprom's cached data will be immediately // following the end of the EECACHE header. l_eecacheSectionHeaderPtr->end_of_cache = sizeof(eecacheSectionHeader); - TRACFCOMP( g_trac_eeprom, + TRACDCOMP( g_trac_eeprom, "cacheEeprom() Found Empty Cache, set end of cache to be 0x%.04x (End of ToC)", sizeof(eecacheSectionHeader)); } @@ -356,6 +211,9 @@ errlHndl_t cacheEeprom(TARGETING::Target* i_target, // to be the current "end of cache" offset in the toc. l_eepromRecordHeader.completeRecord.internal_offset = l_eecacheSectionHeaderPtr->end_of_cache; l_eecacheSectionHeaderPtr->end_of_cache += l_eepromLen; + + // Set cached_copy_valid to 0 until the cache contents actually gets loaded + l_recordHeaderToUpdate->completeRecord.cached_copy_valid = 0; l_updateContents = i_present; break; } @@ -366,6 +224,9 @@ errlHndl_t cacheEeprom(TARGETING::Target* i_target, if( memcmp(l_recordHeaderToUpdate, &l_eepromRecordHeader, NUM_BYTE_UNIQUE_ID ) == 0 ) { l_recordHeaderToUpdateIndex = i; + // We have matched with existing eeprom in the PNOR's EECACHE + // section. So we know this is not a new entry. + l_newEntryDetected = false; if( l_recordHeaderToUpdate->completeRecord.cache_copy_size != l_eepromRecordHeader.completeRecord.cache_copy_size) { @@ -410,81 +271,192 @@ errlHndl_t cacheEeprom(TARGETING::Target* i_target, #ifdef CONFIG_CONSOLE CONSOLE::displayf(EEPROM_COMP_NAME, - "New EEPROM size detected for an existing part, clearing EEPROM cache and performing reconfig loop"); + "New EEPROM size detected for an existing part," + "clearing EEPROM cache and performing reconfig loop"); #endif INITSERVICE::doShutdown(INITSERVICE::SHUTDOWN_DO_RECONFIG_LOOP); } - // - // At this point we have found a match in the PNOR but we need - // to decide what all needs an update - // - - // Stash the internal_offset of the section we found in so we can add - // this record to g_cachedEeproms for later use + // Stash the internal_offset of the section we found in so we + // can add this record to g_cachedEeproms for later use l_eepromRecordHeader.completeRecord.internal_offset = - l_recordHeaderToUpdate->completeRecord.internal_offset; + l_recordHeaderToUpdate->completeRecord.internal_offset; + TRACSSCOMP(g_trac_eeprom, + "cacheEeprom() already found copy for eeprom role %d " + "for target w/ HUID 0x.%08X in EECACHE table of contents", + i_eepromType , TARGETING::get_huid(i_target)); + break; + } + } - if(l_recordHeaderToUpdate->completeRecord.cached_copy_valid) - { - // If the existing eeprom record is valid, then only update the - // contents if the SN/PN for current HW do not match the eeprom - // record. (target must be present to cache) + // pass the record we have been building up (l_eepromRecordHeader) + // and the virtual address of this eeprom's record entry in the + // EECACHE table of contents as a uint64. + if(!addEepromToCachedList(l_eepromRecordHeader, + reinterpret_cast<uint64_t>(l_recordHeaderToUpdate))) + { + TRACSSCOMP( g_trac_eeprom, + "cacheEeprom() Eeprom w/ Role %d, HUID 0x.%08X added to the global map of cached eeproms", + i_eepromType , TARGETING::get_huid(i_target)); + } + else + { + // If this target's eeprom has already been cached in PNOR and our global map + // indicates the cache entry was updated this boot, then we must also + // mark this target associated with the cached eeprom as changed for hwas + if( hasEeepromChanged( l_eepromRecordHeader ) ) + { + HWAS::markTargetChanged(i_target); + } + TRACSSCOMP( g_trac_eeprom, + "cacheEeprom() Eeprom w/ Role %d, HUID 0x.%08X already in global map of cached eeproms", + i_eepromType , TARGETING::get_huid(i_target)); - // TODO RTC:203788 add lookup for PN and SN matches - //if( !i_present || PNandSNMatch ) - { - l_updateContents = false; - } + // Cache entry has already been updated via another target, just break out + break; + } - // If target is present there is nothing in the - // header to update - if( i_present ) - { - l_updateHeader = false; - } + // Only check if the cache is in sync with HARDWARE if there is an + // existing EECACHE section. Otherwise, the code after this logic will + // take care of adding a new eeprom cache section for the target. + if (l_recordHeaderToUpdate->completeRecord.cached_copy_valid) + { + // At this point we have found a match in the PNOR but we need + // to decide what all needs an update. + + // Create namespace alias for targeting to reduce number of + // new lines required to be within line character limit. + namespace T = TARGETING; + + // If the existing eeprom record is valid, then only update + // the contents if the SN/PN for current HW do not match the + // eeprom record. (target must be present to cache) + T::EEPROM_CONTENT_TYPE l_eepromContentType = + T::EEPROM_CONTENT_TYPE_RAW; + + if (i_eepromType == EEPROM::VPD_PRIMARY) + { + auto l_eepromVpd = + i_target->getAttr<T::ATTR_EEPROM_VPD_PRIMARY_INFO>(); + + l_eepromContentType = + static_cast<T::EEPROM_CONTENT_TYPE>( + l_eepromVpd.eepromContentType); + } + else + { + auto l_eepromVpd = + i_target->getAttr<T::ATTR_EEPROM_VPD_BACKUP_INFO>(); + + l_eepromContentType = + static_cast<T::EEPROM_CONTENT_TYPE>( + l_eepromVpd.eepromContentType); + } + + + bool l_isInSync = false; + + if (i_present) + { + l_errl = VPD::ensureEepromCacheIsInSync(i_target, + l_eepromContentType, + l_isInSync); + + if (l_errl != nullptr) + { + break; } - else if(!i_present) + + if(l_isInSync) { - // If the target is not present, then do not update contents or header l_updateContents = false; - l_updateHeader = false; } - TRACSSCOMP( g_trac_eeprom, "cacheEeprom() already found copy for eeprom role %d for target w/ HUID 0x.%08X", - i_eepromType , TARGETING::get_huid(i_target)); - break; } - } + else + { + // Clear out the contents of the cache for this eeprom if we have detected that it + // was once valid, indicating it was present at one time, and is now showing + // up as not present. We want to clear the contents of cache so we can achieve + // the replug behavior where a tester can remove the part, boot, then plug in the + // same part and boot again fresh. + void * l_internalSectionAddr = + reinterpret_cast<uint8_t *>(l_eecacheSectionHeaderPtr) + + l_eepromRecordHeader.completeRecord.internal_offset; + + memset( l_internalSectionAddr, 0xFF , + (l_recordHeaderToUpdate->completeRecord.cache_copy_size * KILOBYTE)); + + l_updateContents = false; + + setIsValidCacheEntry(l_eepromRecordHeader, false); + + TRACFCOMP( g_trac_eeprom, "Detected Master 0x%.08X" + " Engine 0x%.02X Port 0x%.02X" + " MuxSelect 0x%.02X DevAddr 0x%.02X" + " no longer present, clearing cache and marking cache as invalid", + l_recordHeaderToUpdate->completeRecord.i2c_master_huid, + l_recordHeaderToUpdate->completeRecord.engine, + l_recordHeaderToUpdate->completeRecord.port, + l_recordHeaderToUpdate->completeRecord.mux_select, + l_recordHeaderToUpdate->completeRecord.devAddr); + + setEeepromChanged(l_eepromRecordHeader); + // We have cleared the cache entry, this indicates we have found a part has been removed. + // Mark that the target is changed in hwas. + HWAS::markTargetChanged(i_target); + } - if(!addEepromToCachedList(l_eepromRecordHeader)) + // If target is present there is nothing in the + // header to update + if( i_present ) + { + l_updateHeader = false; + } + } + else if(!i_present) { - TRACSSCOMP( g_trac_eeprom, "cacheEeprom() Eeprom w/ Role %d, HUID 0x.%08X added to cached list", - i_eepromType , TARGETING::get_huid(i_target)); + // If the target is not present, then do not update contents + l_updateContents = false; + // Only update header if this is a new entry + l_updateHeader = l_newEntryDetected; } - else + // The check below makes sure that is isnt a new entry + // If there is a matching header entry in PNOR marked 'invalid' + // but we now see the target as present, this indicates a replacement + // part has been added where a part was removed + else if(!l_newEntryDetected) { - TRACSSCOMP( g_trac_eeprom, "cacheEeprom() Eeprom w/ Role %d, HUID 0x.%08X already in cached list", - i_eepromType , TARGETING::get_huid(i_target)); + TRACFCOMP(g_trac_eeprom, "cacheEeprom() Detected replacement of a part" + " Master 0x%.08X Engine 0x%.02X" + " Port 0x%.02X MuxSelect 0x%.02X DevAddr 0x%.02X" + " that was previously removed, we will update the cache with new part's eeproms contents", + l_recordHeaderToUpdate->completeRecord.i2c_master_huid, + l_recordHeaderToUpdate->completeRecord.engine, + l_recordHeaderToUpdate->completeRecord.port, + l_recordHeaderToUpdate->completeRecord.mux_select, + l_recordHeaderToUpdate->completeRecord.devAddr); } - // Above we have determined whether the contents of the eeprom at // hand need to have their contents updated. Only do the following // steps that update the eeprom's cached data if we were told to do so. - if(l_updateContents ) + if( l_updateContents ) { assert(l_recordHeaderToUpdateIndex != INVALID_EEPROM_INDEX, "More than MAX_EEPROMS_VERSION_1 in system XML"); + TRACFCOMP( g_trac_eeprom, "cacheEeprom() updating cache entry"); + void * l_tmpBuffer; l_tmpBuffer = malloc(l_eepromLen); void * l_internalSectionAddr = - reinterpret_cast<uint8_t *>(l_eecacheSectionHeaderPtr) + l_eepromRecordHeader.completeRecord.internal_offset; + reinterpret_cast<uint8_t *>(l_eecacheSectionHeaderPtr) + + l_eepromRecordHeader.completeRecord.internal_offset; TRACSSCOMP( g_trac_eeprom, "cacheEeprom() passing the following into deviceOp eeprom address : huid 0x%.08X length 0x%.08X vaddr %p" , get_huid(i_target), l_eepromLen, l_internalSectionAddr); @@ -543,6 +515,18 @@ errlHndl_t cacheEeprom(TARGETING::Target* i_target, break; } + // Set mark_target_changed and cached_copy_valid and update set updateHeader + // Since we have copied stuff in the cache is valid, and been updated. + // Even if this is a replacement ( cached_copy_valid was already 1) we + // must set mark_target_changed so just always update the header + setEeepromChanged(l_eepromRecordHeader); + // We will update header in PNOR below so no need to call + // setIsValidCacheEntry right here + l_eepromRecordHeader.completeRecord.cached_copy_valid = 1; + l_updateHeader = true; + // We have updated the cache entry, this indicates we have found a "new" part. + // Mark that the target is changed in hwas. + HWAS::markTargetChanged(i_target); } // Above we have determined whether the header entry for the eeprom at @@ -550,6 +534,7 @@ errlHndl_t cacheEeprom(TARGETING::Target* i_target, // the eeprom's header entry if we were told to do so. if(l_updateHeader) { + TRACFCOMP( g_trac_eeprom, "cacheEeprom() updating header entry"); TRACDBIN( g_trac_eeprom, "cacheEeprom: l_eecacheSectionHeaderPtr currently ", l_eecacheSectionHeaderPtr, sizeof(eecacheSectionHeader)); @@ -658,175 +643,318 @@ DEVICE_REGISTER_ROUTE( DeviceFW::READ, TARGETING::TYPE_DIMM, genericI2CEepromCache ); -#endif +DEVICE_REGISTER_ROUTE( DeviceFW::READ, + DeviceFW::EEPROM_CACHE, + TARGETING::TYPE_NODE, + genericI2CEepromCache ); -errlHndl_t eepromPerformOpCache(DeviceFW::OperationType i_opType, - TARGETING::Target * i_target, - void * io_buffer, - size_t& io_buflen, - eeprom_addr_t &i_eepromInfo) +errlHndl_t setIsValidCacheEntry(const TARGETING::Target * i_target, + const EEPROM_ROLE &i_eepromRole, + bool i_isValid) { errlHndl_t l_errl = nullptr; eepromRecordHeader l_eepromRecordHeader; + eeprom_addr_t l_eepromInfo; do{ - TRACSSCOMP( g_trac_eeprom, ENTER_MRK"eepromPerformOpCache() " - "Target HUID 0x%.08X Enter", TARGETING::get_huid(i_target)); + TRACDCOMP( g_trac_eeprom, ENTER_MRK"setIsValidCacheEntry() " + "Target HUID 0x%.08X Eeprom Role = %d Enter", + TARGETING::get_huid(i_target), l_eepromInfo.eepromRole); - l_errl = buildEepromRecordHeader(i_target, i_eepromInfo, l_eepromRecordHeader); + l_eepromInfo.eepromRole = i_eepromRole; + l_errl = buildEepromRecordHeader(const_cast<TARGETING::Target *>(i_target), l_eepromInfo, l_eepromRecordHeader); if(l_errl) { - // buildEepromRecordHeader should have traced any relavent information if - // it was needed, just break out and pass the error along break; } - uint64_t l_eepromCacheVaddr = lookupEepromAddr(l_eepromRecordHeader); + l_errl = setIsValidCacheEntry(l_eepromRecordHeader, i_isValid); - // Ensure that a copy of the eeprom exists in our map of cached eeproms - if(l_eepromCacheVaddr) - { - // First check if io_buffer is a nullptr, if so then assume user is - // requesting size back in io_bufferlen - if(io_buffer == nullptr) - { - io_buflen = l_eepromRecordHeader.completeRecord.cache_copy_size * KILOBYTE; - TRACSSCOMP( g_trac_eeprom, "eepromPerformOpCache() " - "io_buffer == nullptr , returning io_buflen as 0x%lx", - io_buflen); - break; - } + }while(0); - TRACSSCOMP( g_trac_eeprom, "eepromPerformOpCache() " - "Performing %s on target 0x%.08X offset 0x%lx length 0x%x vaddr 0x%lx", - (i_opType == DeviceFW::READ) ? "READ" : "WRITE", - TARGETING::get_huid(i_target), - i_eepromInfo.offset, io_buflen, l_eepromCacheVaddr); + return l_errl; +} - // Make sure that offset + buflen are less than the total size of the eeprom - if(i_eepromInfo.offset + io_buflen > (l_eepromRecordHeader.completeRecord.cache_copy_size * KILOBYTE)) - { - TRACFCOMP(g_trac_eeprom, - ERR_MRK"eepromPerformOpCache: i_eepromInfo.offset + i_offset is greater than size of eeprom (0x%x KB)", - l_eepromRecordHeader.completeRecord.cache_copy_size); - /*@ - * @errortype - * @moduleid EEPROM_CACHE_PERFORM_OP - * @reasoncode EEPROM_OVERFLOW_ERROR - * @userdata1 Length of Operation - * @userdata2 Offset we are attempting to read/write - * @custdesc Soft error in Firmware - * @devdesc cacheEeprom invalid op type - */ - l_errl = new ERRORLOG::ErrlEntry( - ERRORLOG::ERRL_SEV_UNRECOVERABLE, - EEPROM_CACHE_PERFORM_OP, - EEPROM_OVERFLOW_ERROR, - TO_UINT64(io_buflen), - TO_UINT64(i_eepromInfo.offset), - ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); - ERRORLOG::ErrlUserDetailsTarget(i_target).addToLog(l_errl); - l_errl->collectTrace( EEPROM_COMP_NAME ); +errlHndl_t setIsValidCacheEntry(const eepromRecordHeader& i_eepromRecordHeader, bool i_isValid) +{ + errlHndl_t l_errl = nullptr; + eepromRecordHeader * l_eepromRecordHeaderToUpdate; + std::map<eepromRecordHeader, EeepromEntryMetaData_t>::iterator l_headerMapIterator; - break; - } + do{ - if(i_opType == DeviceFW::READ) - { - memcpy(io_buffer, reinterpret_cast<void *>(l_eepromCacheVaddr + i_eepromInfo.offset), io_buflen); - } - else if(i_opType == DeviceFW::WRITE) - { - memcpy(reinterpret_cast<void *>(l_eepromCacheVaddr + i_eepromInfo.offset), io_buffer, io_buflen); + TRACDCOMP( g_trac_eeprom, ENTER_MRK"setIsValidCacheEntry() "); - #ifndef __HOSTBOOT_RUNTIME - // Perform flush to ensure pnor is updated - int rc = mm_remove_pages( FLUSH, - reinterpret_cast<void *>(l_eepromCacheVaddr + i_eepromInfo.offset), - io_buflen ); - if( rc ) - { - TRACFCOMP(g_trac_eeprom,ERR_MRK"eepromPerformOpCache: Error from mm_remove_pages trying for flush contents write to pnor! rc=%d",rc); - /*@ - * @errortype - * @moduleid EEPROM_CACHE_PERFORM_OP - * @reasoncode EEPROM_FAILED_TO_FLUSH_CONTENTS - * @userdata1 Requested Address - * @userdata2 rc from mm_remove_pages - * @devdesc cacheEeprom mm_remove_pages FLUSH failed - */ - l_errl = new ERRORLOG::ErrlEntry( - ERRORLOG::ERRL_SEV_UNRECOVERABLE, - EEPROM_CACHE_PERFORM_OP, - EEPROM_FAILED_TO_FLUSH_CONTENTS, - (l_eepromCacheVaddr + i_eepromInfo.offset), - TO_UINT64(rc), - ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); - l_errl->collectTrace( EEPROM_COMP_NAME ); - } - #endif //__HOSTBOOT_RUNTIME - } - else - { - TRACFCOMP(g_trac_eeprom,ERR_MRK"eepromPerformOpCache: Invalid OP_TYPE passed to function, i_opType=%d", i_opType); - /*@ - * @errortype - * @moduleid EEPROM_CACHE_PERFORM_OP - * @reasoncode EEPROM_INVALID_OPERATION - * @userdata1[0:31] Op Type that was invalid - * @userdata1[32:63] Eeprom Role - * @userdata2 Offset we are attempting to perfrom op on - * @custdesc Soft error in Firmware - * @devdesc cacheEeprom invalid op type - */ - l_errl = new ERRORLOG::ErrlEntry( - ERRORLOG::ERRL_SEV_UNRECOVERABLE, - EEPROM_CACHE_PERFORM_OP, - EEPROM_INVALID_OPERATION, - TWO_UINT32_TO_UINT64(i_opType, - i_eepromInfo.eepromRole), - TO_UINT64(i_eepromInfo.offset), - ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); - ERRORLOG::ErrlUserDetailsTarget(i_target).addToLog(l_errl); - l_errl->collectTrace( EEPROM_COMP_NAME ); - } + // Find the address of the header entry in the table of contents of the EECACHE pnor section + l_eepromRecordHeaderToUpdate = + reinterpret_cast<eepromRecordHeader *>(lookupEepromHeaderAddr(i_eepromRecordHeader)); + + if(l_eepromRecordHeaderToUpdate == 0) + { + TRACFCOMP(g_trac_eeprom, + ERR_MRK"setIsValidCacheEntry: Attempting to invalidate cache for an " + "eeprom but we could not find in global eecache map"); + /*@ + * @errortype + * @moduleid EEPROM_INVALIDATE_CACHE + * @reasoncode EEPROM_CACHE_NOT_FOUND_IN_MAP + * @userdata1[0:7] i2c_master_huid + * @userdata1[8:9] port on i2c master eeprom slave is on + * @userdata1[10:11] engine on i2c master eeprom slave is on + * @userdata1[12:13] devAddr of eeprom slave + * @userdata1[14:15] muxSelect of eeprom slave (0xFF is not valid) + * @userdata2[0:7] size of eeprom + * @devdesc invalidateCache failed to find cache in map + */ + l_errl = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + EEPROM_INVALIDATE_CACHE, + EEPROM_CACHE_NOT_FOUND_IN_MAP, + TWO_UINT32_TO_UINT64( + i_eepromRecordHeader.completeRecord.i2c_master_huid, + TWO_UINT16_TO_UINT32( + TWO_UINT8_TO_UINT16( + i_eepromRecordHeader.completeRecord.port, + i_eepromRecordHeader.completeRecord.engine), + TWO_UINT8_TO_UINT16( + i_eepromRecordHeader.completeRecord.devAddr, + i_eepromRecordHeader.completeRecord.mux_select))), + i_eepromRecordHeader.completeRecord.cache_copy_size, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + break; } - else + + // Ensure that information at the address we just looked up matches the record we built up + if( memcmp(&l_eepromRecordHeaderToUpdate->uniqueRecord.uniqueID, + &i_eepromRecordHeader.uniqueRecord.uniqueID, + NUM_BYTE_UNIQUE_ID ) != 0 ) + { + TRACFCOMP(g_trac_eeprom,ERR_MRK"setIsValidCacheEntry: Attempting to invalidate cache for an" + "eeprom but we could not find the entry in table of contents of EECACHE section of pnor"); + /*@ + * @errortype + * @moduleid EEPROM_INVALIDATE_CACHE + * @reasoncode EEPROM_CACHE_NOT_FOUND_IN_PNOR + * @userdata1[0:7] i2c_master_huid + * @userdata1[8:9] port on i2c master eeprom slave is on + * @userdata1[10:11] engine on i2c master eeprom slave is on + * @userdata1[12:13] devAddr of eeprom slave + * @userdata1[14:15] muxSelect of eeprom slave (0xFF is not valid) + * @userdata2[0:7] size of eeprom + * @devdesc invalidateCache failed to find cache in pnor + */ + l_errl = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + EEPROM_INVALIDATE_CACHE, + EEPROM_CACHE_NOT_FOUND_IN_PNOR, + TWO_UINT32_TO_UINT64( + i_eepromRecordHeader.completeRecord.i2c_master_huid, + TWO_UINT16_TO_UINT32( + TWO_UINT8_TO_UINT16( + i_eepromRecordHeader.completeRecord.port, + i_eepromRecordHeader.completeRecord.engine), + TWO_UINT8_TO_UINT16( + i_eepromRecordHeader.completeRecord.devAddr, + i_eepromRecordHeader.completeRecord.mux_select))), + i_eepromRecordHeader.completeRecord.cache_copy_size, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + break; + } + + // Update the header so that it state the entry is invalid + l_eepromRecordHeaderToUpdate->completeRecord.cached_copy_valid = i_isValid; + + // Flush the page to make sure it gets to the PNOR + int rc = mm_remove_pages( FLUSH, + l_eepromRecordHeaderToUpdate, + sizeof(eepromRecordHeader) ); + if( rc ) { - TRACFCOMP( g_trac_eeprom,"eepromPerformOpCache: Failed to find entry in cache for 0x%.08X, %s failed", - TARGETING::get_huid(i_target), - (i_opType == DeviceFW::READ) ? "READ" : "WRITE"); + TRACFCOMP(g_trac_eeprom, + ERR_MRK"setIsValidCacheEntry: Error from mm_remove_pages trying for flush header write to pnor, rc=%d",rc); /*@ * @errortype - * @moduleid EEPROM_CACHE_PERFORM_OP - * @reasoncode EEPROM_NOT_IN_CACHE - * @userdata1[0:31] Op Type - * @userdata1[32:63] Eeprom Role - * @userdata2 Offset we are attempting to read/write - * @custdesc Soft error in Firmware - * @devdesc Tried to lookup eeprom not in cache + * @moduleid EEPROM_INVALIDATE_CACHE + * @reasoncode EEPROM_FAILED_TO_FLUSH_HEADER + * @userdata1 Requested Address + * @userdata2 rc from mm_remove_pages + * @devdesc invalidateCache mm_remove_pages FLUSH failed */ l_errl = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_UNRECOVERABLE, - EEPROM_CACHE_PERFORM_OP, - EEPROM_NOT_IN_CACHE, - TWO_UINT32_TO_UINT64(i_opType, - i_eepromInfo.eepromRole), - TO_UINT64(i_eepromInfo.offset), + EEPROM_INVALIDATE_CACHE, + EEPROM_FAILED_TO_FLUSH_HEADER, + (uint64_t)l_eepromRecordHeaderToUpdate, + TO_UINT64(rc), ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); - ERRORLOG::ErrlUserDetailsTarget(i_target).addToLog(l_errl); - l_errl->collectTrace( EEPROM_COMP_NAME ); + break; } - TRACSSCOMP( g_trac_eeprom, EXIT_MRK"eepromPerformOpCache() " - "Target HUID 0x%.08X Exit", TARGETING::get_huid(i_target)); - }while(0); return l_errl; } +bool addEepromToCachedList(const eepromRecordHeader & i_eepromRecordHeader, + const uint64_t i_recordHeaderVaddr) +{ + bool l_matchFound = true; + + // Map accesses are not thread safe, make sure this is always wrapped in mutex + mutex_lock(&g_eecacheMutex); + + if(g_cachedEeproms.find(i_eepromRecordHeader) == g_cachedEeproms.end()) + { + g_cachedEeproms[i_eepromRecordHeader].cache_entry_address = + g_eecachePnorVaddr + i_eepromRecordHeader.completeRecord.internal_offset; + + g_cachedEeproms[i_eepromRecordHeader].header_entry_address = + i_recordHeaderVaddr; + + TRACSSCOMP( g_trac_eeprom, + "addEepromToCachedList() Adding I2CM Huid: 0x%.08X, Port: 0x%.02X," + " Engine: 0x%.02X, Dev Addr: 0x%.02X, Mux Select: 0x%.02X," + " Size: 0x%.08X to g_cachedEeproms", + i_eepromRecordHeader.completeRecord.i2c_master_huid, + i_eepromRecordHeader.completeRecord.port, + i_eepromRecordHeader.completeRecord.engine, + i_eepromRecordHeader.completeRecord.devAddr, + i_eepromRecordHeader.completeRecord.mux_select, + i_eepromRecordHeader.completeRecord.cache_copy_size); + + l_matchFound = false; + } + + mutex_unlock(&g_eecacheMutex); + + return l_matchFound; +} + +void printTableOfContents(void) +{ + eecacheSectionHeader * l_eecacheSectionHeaderPtr = + reinterpret_cast<eecacheSectionHeader*>(g_eecachePnorVaddr); + + TRACFCOMP( g_trac_eeprom, + "printTableOfContents(): Version = 0x%.02X" + " End of Cache = 0x.08X", + l_eecacheSectionHeaderPtr->version, + l_eecacheSectionHeaderPtr->end_of_cache); + + for(uint8_t i = 0; i < MAX_EEPROMS_VERSION_1; i++) + { + eepromRecordHeader l_currentRecordHeader = + l_eecacheSectionHeaderPtr->recordHeaders[i]; + + if( l_currentRecordHeader.completeRecord.internal_offset != + UNSET_INTERNAL_OFFSET_VALUE) + { + TRACFCOMP( g_trac_eeprom, + "printTableOfContents(): I2CM Huid: 0x%.08X, Port: 0x%.02X," + " Engine: 0x%.02X, Dev Addr: 0x%.02X," + " Mux Select: 0x%.02X, Size: 0x%.08X", + l_currentRecordHeader.completeRecord.i2c_master_huid, + l_currentRecordHeader.completeRecord.port, + l_currentRecordHeader.completeRecord.engine, + l_currentRecordHeader.completeRecord.devAddr, + l_currentRecordHeader.completeRecord.mux_select, + l_currentRecordHeader.completeRecord.cache_copy_size); + + TRACFCOMP( g_trac_eeprom, + " " + "Internal Offset: 0x%.08X, Cache Valid: 0x%.02X", + l_currentRecordHeader.completeRecord.internal_offset, + l_currentRecordHeader.completeRecord.cached_copy_valid); + } + } + } + +bool hasEeepromChanged(const eepromRecordHeader & i_eepromRecordHeader) +{ + bool l_eepromHasChanged = false; + + // Map accesses are not thread safe, make sure this is always wrapped in mutex + mutex_lock(&g_eecacheMutex); + + if(g_cachedEeproms.find(i_eepromRecordHeader) != g_cachedEeproms.end()) + { + l_eepromHasChanged = g_cachedEeproms[i_eepromRecordHeader].mark_target_changed; + } + + mutex_unlock(&g_eecacheMutex); + + return l_eepromHasChanged; +} + +void setEeepromChanged(const eepromRecordHeader & i_eepromRecordHeader) +{ + + // Map accesses are not thread safe, make sure this is always wrapped in mutex + mutex_lock(&g_eecacheMutex); + + if(g_cachedEeproms.find(i_eepromRecordHeader) != g_cachedEeproms.end()) + { + g_cachedEeproms[i_eepromRecordHeader].mark_target_changed = true; + } + + mutex_unlock(&g_eecacheMutex); + +} + +uint64_t lookupEepromCacheAddr(const eepromRecordHeader& i_eepromRecordHeader) +{ + uint64_t l_vaddr = 0; + std::map<eepromRecordHeader, EeepromEntryMetaData_t>::iterator l_it; + + // Wrap lookup in mutex because reads are not thread safe + mutex_lock(&g_eecacheMutex); + l_it = g_cachedEeproms.find(i_eepromRecordHeader); + + if(l_it != g_cachedEeproms.end()) + { + l_vaddr = l_it->second.cache_entry_address; + } + + mutex_unlock(&g_eecacheMutex); + + return l_vaddr; +} + +uint64_t lookupEepromHeaderAddr(const eepromRecordHeader& i_eepromRecordHeader) +{ + uint64_t l_vaddr = 0; + std::map<eepromRecordHeader, EeepromEntryMetaData_t>::iterator l_it; + + // Wrap lookup in mutex because reads are not thread safe + mutex_lock(&g_eecacheMutex); + l_it = g_cachedEeproms.find(i_eepromRecordHeader); + + if(l_it != g_cachedEeproms.end()) + { + l_vaddr = l_it->second.header_entry_address; + } + mutex_unlock(&g_eecacheMutex); + + if(l_vaddr == 0) + { + TRACFCOMP( g_trac_eeprom, + "lookupEepromHeaderAddr() failed to find" + " I2CM Huid: 0x%.08X, Port: 0x%.02X," + " Engine: 0x%.02X, Dev Addr: 0x%.02X," + " Mux Select: 0x%.02X, Size: 0x%.08X" + "in g_cachedEeproms", + i_eepromRecordHeader.completeRecord.i2c_master_huid, + i_eepromRecordHeader.completeRecord.port, + i_eepromRecordHeader.completeRecord.engine, + i_eepromRecordHeader.completeRecord.devAddr, + i_eepromRecordHeader.completeRecord.mux_select, + i_eepromRecordHeader.completeRecord.cache_copy_size); + } + return l_vaddr; +} + +}
\ No newline at end of file diff --git a/src/usr/i2c/eepromCache.H b/src/usr/i2c/eepromCache.H index 5cad475ba..253367b07 100644 --- a/src/usr/i2c/eepromCache.H +++ b/src/usr/i2c/eepromCache.H @@ -97,10 +97,44 @@ errlHndl_t buildEepromRecordHeader(TARGETING::Target * i_target, eeprom_addr_t & io_eepromInfo, eepromRecordHeader & o_eepromRecordHeader); + +#ifndef __HOSTBOOT_RUNTIME + +/** +* +* @brief Check if entry already exists in g_cachedEeproms, if a match is +* found then return true. If there is no match, add it to the list +* and return false; +* +* @param[in] i_eepromRecordHeader Header for record we want to add to map +* +* @param[in] i_recordHeaderVaddr Virtual address to PNOR copy of header information +* +* @return TRUE if entry is already in map FALSE if this is a new entry +* +*/ +bool addEepromToCachedList(const eepromRecordHeader & i_eepromRecordHeader, + const uint64_t i_recordHeaderVaddr); + +/** +* +* @brief Perform a lookup on the global map g_cachedEeproms to get a +* virtual address for a given EEPROM entry in the EECACHE table of contents +* +* @param[in] i_eepromRecordHeader +* +* @pre It is expected that i_eepromRecordHeader has valid information for +* the uniqueID (i2cm_huid, port, engine, devAddr, mux_select) +* +* @return uint64_t virtual address pointing to the cached eeprom data in pnor +* +*/ +uint64_t lookupEepromHeaderAddr(const eepromRecordHeader& i_eepromRecordHeader); + /** * * @brief Perform a lookup on the global map g_cachedEeproms to get a -* virtual address for a given EEPROM +* virtual address for a given EEPROM cache entry * * @param[in] i_eepromRecordHeader * @@ -110,8 +144,127 @@ errlHndl_t buildEepromRecordHeader(TARGETING::Target * i_target, * @return uint64_t virtual address pointing to the cached eeprom data in pnor * */ -uint64_t lookupEepromAddr(const eepromRecordHeader & i_eepromRecordHeader); +uint64_t lookupEepromCacheAddr(const eepromRecordHeader& i_eepromRecordHeader); + +/** +* +* @brief Print the info found in the Table of Contents of the EECACHE +* section of pnor to trace buffer +* +* @return void +* +*/ +void printTableOfContents(void); + + +/** +* +* @brief Update the record entry in the Table of Contents of the EECACHE +* section of pnor to either mark the contents of the cache to be +* valid or invalid +* +* @param[in] i_target Target associated with EEPROM +* +* @param[in] i_eepromRole Role of EEPROM associated with target (VPD_PRIMARY etc) +* +* @param[in] i_isValid Mark eeprom cache valid or invalid ? +* +* @return errlHndl_t - nullptr if successful, otherwise a pointer to the +* error log. +* +*/ +errlHndl_t setIsValidCacheEntry(const TARGETING::Target * i_target, + const EEPROM_ROLE &i_eepromRole, + bool i_isValid); + +/** +* +* @brief Update the record entry in the Table of Contents of the EECACHE +* section of pnor to either mark the contents of the cache to be +* valid or invalid +* +* @param[in] i_eepromRecordHeader eepromRecord oject already filled in (including eepromRole) +* +* @param[in] i_isValid Mark eeprom cache valid or invalid ? +* +* @return errlHndl_t - nullptr if successful, otherwise a pointer to the +* error log. +* +*/ +errlHndl_t setIsValidCacheEntry(const eepromRecordHeader& i_eepromRecordHeader, bool i_isValid); + +/** +* +* @brief Lookup a given i_eepromRecordHeader in the global map of eeprom +* caches and check if the eeprom has changed this IPL or not +* +* @param[in] i_eepromRecordHeader we want to look up +* +* @return bool Return TRUE if eeprom is found in map AND mark_target_changed + was set to true for the eeprom entry. Return FALSE otherwise. +* +*/ +bool hasEeepromChanged(const eepromRecordHeader & i_eepromRecordHeader); + +/** +* +* @brief Lookup a given i_eepromRecordHeader in the global map of eeprom +* caches and mark that it has changed this IPL +* +* @param[in] i_eepromRecordHeader we want to mark as changed +* +* @return void +*/ +void setEeepromChanged(const eepromRecordHeader & i_eepromRecordHeader); +#else +/** +* +* @brief Check if entry already exists in g_cachedEeproms, if a match is +* found then return true. If there is no match, add it to the list +* and return false; +* +* @param[in] i_eepromRecordHeader Header for record we want to add to map +* +* @param[in] i_recordHeaderVaddr Virtual address to PNOR copy of header information +* +* @param[in] i_instance Node ID that this eeprom is on +* +* @return TRUE if entry is already in map FALSE if this is a new entry +* +*/ +bool addEepromToCachedList(const eepromRecordHeader & i_eepromRecordHeader, + const uint64_t i_recordHeaderVaddr, + const uint8_t i_instance); + +/** +* +* @brief Perform a lookup on the global map g_cachedEeproms to get a +* virtual address for a given EEPROM cache entry +* +* @param[in] i_eepromRecordHeader Header for record we want to add to lookup address for +* +* @param[in] i_isntance Node ID that this eeprom is on +* +* @pre It is expected that i_eepromRecordHeader has valid information for +* the uniqueID (i2cm_huid, port, engine, devAddr, mux_select) +* +* @return uint64_t virtual address pointing to the cached eeprom data in pnor +* +*/ +uint64_t lookupEepromCacheAddr(const eepromRecordHeader& i_eepromRecordHeader, + const uint8_t i_instance); + +/** +* +* @brief Walk through g_cachedEeproms map and print information about +* the cached eeproms found +* +* @return void +* +*/ +void printCurrentCachedEepromMap(void); +#endif // __HOSTBOOT_RUNTIME } #endif
\ No newline at end of file diff --git a/src/usr/i2c/eepromCache_common.C b/src/usr/i2c/eepromCache_common.C new file mode 100644 index 000000000..72c982056 --- /dev/null +++ b/src/usr/i2c/eepromCache_common.C @@ -0,0 +1,325 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/i2c/eepromCache_common.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#include "eepromCache.H" +#include <errl/errlmanager.H> +#include <i2c/eepromif.H> +#include <i2c/eepromddreasoncodes.H> +#include <errl/errludtarget.H> + +#ifdef __HOSTBOOT_RUNTIME +#include <targeting/attrrp.H> +#else +#include <sys/mm.h> +#endif + +extern trace_desc_t* g_trac_eeprom; + +//#define TRACSSCOMP(args...) TRACFCOMP(args) +#define TRACSSCOMP(args...) + +namespace EEPROM +{ + +errlHndl_t buildEepromRecordHeader(TARGETING::Target * i_target, + eeprom_addr_t & io_eepromInfo, + eepromRecordHeader & o_eepromRecordHeader) +{ + + TARGETING::Target * l_muxTarget = nullptr; + TARGETING::Target * l_i2cMasterTarget = nullptr; + TARGETING::TargetService& l_targetService = TARGETING::targetService(); + errlHndl_t l_errl = nullptr; + + do{ + + l_errl = eepromReadAttributes(i_target, io_eepromInfo); + if(l_errl) + { + TRACFCOMP( g_trac_eeprom, + "buildEepromRecordHeader() error occurred reading eeprom attributes for eepromType %d, target 0x%.08X, returning!!", + io_eepromInfo.eepromRole, + TARGETING::get_huid(i_target)); + l_errl->collectTrace(EEPROM_COMP_NAME); + break; + } + + // Grab the I2C mux target so we can read the HUID, if the target is NULL we will not be able + // to lookup attribute to uniquely ID this eeprom so we will not cache it + l_muxTarget = l_targetService.toTarget( io_eepromInfo.i2cMuxPath); + if(l_muxTarget == nullptr) + { + TRACFCOMP( g_trac_eeprom, + "buildEepromRecordHeader() Mux target associated with target 0x%.08X resolved to a nullptr , check attribute for eepromType %d. Skipping Cache", + TARGETING::get_huid(i_target), + io_eepromInfo.eepromRole); + /*@ + * @errortype + * @moduleid EEPROM_CACHE_EEPROM + * @reasoncode EEPROM_I2C_MUX_PATH_ERROR + * @userdata1 HUID of target we want to cache + * @userdata2 Type of EEPROM we are caching + * @devdesc buildEepromRecordHeader invalid mux target + */ + l_errl = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + EEPROM_CACHE_EEPROM, + EEPROM_I2C_MUX_PATH_ERROR, + TARGETING::get_huid(i_target), + io_eepromInfo.eepromRole, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + l_errl->collectTrace(EEPROM_COMP_NAME); + break; + } + + // Grab the I2C master target so we can read the HUID, if the target is NULL we will not be able + // to lookup attribute to uniquely ID this eeprom so we will not cache it + l_i2cMasterTarget = l_targetService.toTarget( io_eepromInfo.i2cMasterPath ); + if(l_i2cMasterTarget == nullptr) + { + TRACFCOMP( g_trac_eeprom, + "buildEepromRecordHeader() I2C Master target associated with target 0x%.08X resolved to a nullptr , check attribute for eepromType %d. Skipping Cache ", + TARGETING::get_huid(i_target), + io_eepromInfo.eepromRole); + /*@ + * @errortype + * @moduleid EEPROM_CACHE_EEPROM + * @reasoncode EEPROM_I2C_MASTER_PATH_ERROR + * @userdata1 HUID of target we want to cache + * @userdata2 Type of EEPROM we are caching + * @devdesc buildEepromRecordHeader invalid master target + */ + l_errl = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + EEPROM_CACHE_EEPROM, + EEPROM_I2C_MASTER_PATH_ERROR, + TARGETING::get_huid(i_target), + io_eepromInfo.eepromRole, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + l_errl->collectTrace(EEPROM_COMP_NAME); + break; + } + + // This is what we will compare w/ when we are going through the existing + // caches in the eeprom to see if we have already cached something + // Or if no matches are found we will copy this into the header + o_eepromRecordHeader.completeRecord.i2c_master_huid = l_i2cMasterTarget->getAttr<TARGETING::ATTR_HUID>(); + o_eepromRecordHeader.completeRecord.port = static_cast<uint8_t>(io_eepromInfo.port); + o_eepromRecordHeader.completeRecord.engine = static_cast<uint8_t>(io_eepromInfo.engine); + o_eepromRecordHeader.completeRecord.devAddr = static_cast<uint8_t>(io_eepromInfo.devAddr); + o_eepromRecordHeader.completeRecord.mux_select = static_cast<uint8_t>(io_eepromInfo.i2cMuxBusSelector); + o_eepromRecordHeader.completeRecord.cache_copy_size = static_cast<uint32_t>(io_eepromInfo.devSize_KB); + + // Do not set valid bit nor internal offset here as we do not have + // enough information availible to determine + + }while(0); + + return l_errl; +} + +errlHndl_t eepromPerformOpCache(DeviceFW::OperationType i_opType, + TARGETING::Target * i_target, + void * io_buffer, + size_t& io_buflen, + eeprom_addr_t &i_eepromInfo) +{ + errlHndl_t l_errl = nullptr; + eepromRecordHeader l_eepromRecordHeader; + + do{ + + TRACSSCOMP( g_trac_eeprom, ENTER_MRK"eepromPerformOpCache() " + "Target HUID 0x%.08X Enter", TARGETING::get_huid(i_target)); + + l_errl = buildEepromRecordHeader(i_target, + i_eepromInfo, + l_eepromRecordHeader); + + if(l_errl) + { + // buildEepromRecordHeader should have traced any relavent information if + // it was needed, just break out and pass the error along + break; + } + +#ifndef __HOSTBOOT_RUNTIME + uint64_t l_eepromCacheVaddr = lookupEepromCacheAddr(l_eepromRecordHeader); +#else + uint8_t l_instance = TARGETING::AttrRP::getNodeId(i_target); + uint64_t l_eepromCacheVaddr = lookupEepromCacheAddr(l_eepromRecordHeader, l_instance); +#endif + + // Ensure that a copy of the eeprom exists in our map of cached eeproms + if(l_eepromCacheVaddr) + { + // First check if io_buffer is a nullptr, if so then assume user is + // requesting size back in io_bufferlen + if(io_buffer == nullptr) + { + io_buflen = l_eepromRecordHeader.completeRecord.cache_copy_size * KILOBYTE; + TRACSSCOMP( g_trac_eeprom, "eepromPerformOpCache() " + "io_buffer == nullptr , returning io_buflen as 0x%lx", + io_buflen); + break; + } + + TRACSSCOMP( g_trac_eeprom, "eepromPerformOpCache() " + "Performing %s on target 0x%.08X offset 0x%lx length 0x%x vaddr 0x%lx", + (i_opType == DeviceFW::READ) ? "READ" : "WRITE", + TARGETING::get_huid(i_target), + i_eepromInfo.offset, io_buflen, l_eepromCacheVaddr); + + // Make sure that offset + buflen are less than the total size of the eeprom + if(i_eepromInfo.offset + io_buflen > + (l_eepromRecordHeader.completeRecord.cache_copy_size * KILOBYTE)) + { + TRACFCOMP(g_trac_eeprom, + ERR_MRK"eepromPerformOpCache: i_eepromInfo.offset + i_offset is greater than size of eeprom (0x%x KB)", + l_eepromRecordHeader.completeRecord.cache_copy_size); + /*@ + * @errortype + * @moduleid EEPROM_CACHE_PERFORM_OP + * @reasoncode EEPROM_OVERFLOW_ERROR + * @userdata1 Length of Operation + * @userdata2 Offset we are attempting to read/write + * @custdesc Soft error in Firmware + * @devdesc cacheEeprom invalid op type + */ + l_errl = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + EEPROM_CACHE_PERFORM_OP, + EEPROM_OVERFLOW_ERROR, + TO_UINT64(io_buflen), + TO_UINT64(i_eepromInfo.offset), + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + ERRORLOG::ErrlUserDetailsTarget(i_target).addToLog(l_errl); + l_errl->collectTrace( EEPROM_COMP_NAME ); + + break; + } + + if(i_opType == DeviceFW::READ) + { + memcpy(io_buffer, + reinterpret_cast<void *>(l_eepromCacheVaddr + i_eepromInfo.offset), + io_buflen); + } + else if(i_opType == DeviceFW::WRITE) + { + memcpy(reinterpret_cast<void *>(l_eepromCacheVaddr + i_eepromInfo.offset), + io_buffer, + io_buflen); + +#ifndef __HOSTBOOT_RUNTIME + // Perform flush to ensure pnor is updated + int rc = mm_remove_pages( FLUSH, + reinterpret_cast<void *>(l_eepromCacheVaddr + i_eepromInfo.offset), + io_buflen ); + if( rc ) + { + TRACFCOMP(g_trac_eeprom, + ERR_MRK"eepromPerformOpCache: Error from mm_remove_pages trying for flush contents write to pnor! rc=%d", + rc); + /*@ + * @errortype + * @moduleid EEPROM_CACHE_PERFORM_OP + * @reasoncode EEPROM_FAILED_TO_FLUSH_CONTENTS + * @userdata1 Requested Address + * @userdata2 rc from mm_remove_pages + * @devdesc cacheEeprom mm_remove_pages FLUSH failed + */ + l_errl = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + EEPROM_CACHE_PERFORM_OP, + EEPROM_FAILED_TO_FLUSH_CONTENTS, + (l_eepromCacheVaddr + i_eepromInfo.offset), + TO_UINT64(rc), + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + l_errl->collectTrace( EEPROM_COMP_NAME ); + } +#endif + } + else + { + TRACFCOMP(g_trac_eeprom, + ERR_MRK"eepromPerformOpCache: Invalid OP_TYPE passed to function, i_opType=%d", + i_opType); + /*@ + * @errortype + * @moduleid EEPROM_CACHE_PERFORM_OP + * @reasoncode EEPROM_INVALID_OPERATION + * @userdata1[0:31] Op Type that was invalid + * @userdata1[32:63] Eeprom Role + * @userdata2 Offset we are attempting to perfrom op on + * @custdesc Soft error in Firmware + * @devdesc cacheEeprom invalid op type + */ + l_errl = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + EEPROM_CACHE_PERFORM_OP, + EEPROM_INVALID_OPERATION, + TWO_UINT32_TO_UINT64(i_opType, + i_eepromInfo.eepromRole), + TO_UINT64(i_eepromInfo.offset), + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + ERRORLOG::ErrlUserDetailsTarget(i_target).addToLog(l_errl); + l_errl->collectTrace( EEPROM_COMP_NAME ); + } + } + else + { + TRACFCOMP( g_trac_eeprom,"eepromPerformOpCache: Failed to find entry in cache for 0x%.08X, %s failed", + TARGETING::get_huid(i_target), + (i_opType == DeviceFW::READ) ? "READ" : "WRITE"); + /*@ + * @errortype + * @moduleid EEPROM_CACHE_PERFORM_OP + * @reasoncode EEPROM_NOT_IN_CACHE + * @userdata1[0:31] Op Type + * @userdata1[32:63] Eeprom Role + * @userdata2 Offset we are attempting to read/write + * @custdesc Soft error in Firmware + * @devdesc Tried to lookup eeprom not in cache + */ + l_errl = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + EEPROM_CACHE_PERFORM_OP, + EEPROM_NOT_IN_CACHE, + TWO_UINT32_TO_UINT64(i_opType, + i_eepromInfo.eepromRole), + TO_UINT64(i_eepromInfo.offset), + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + ERRORLOG::ErrlUserDetailsTarget(i_target).addToLog(l_errl); + l_errl->collectTrace( EEPROM_COMP_NAME ); + } + + TRACSSCOMP( g_trac_eeprom, EXIT_MRK"eepromPerformOpCache() " + "Target HUID 0x%.08X Exit", TARGETING::get_huid(i_target)); + + }while(0); + + return l_errl; +} +}
\ No newline at end of file diff --git a/src/usr/i2c/eeprom_utils.C b/src/usr/i2c/eeprom_utils.C index 806a0cf31..8333ebf49 100644 --- a/src/usr/i2c/eeprom_utils.C +++ b/src/usr/i2c/eeprom_utils.C @@ -87,6 +87,18 @@ bool eepromPresence ( TARGETING::Target * i_target ) break; } + // If the target has dynamic device address attribute, then use that instead of the + // read-only address found in ATTR_EEPROM_XX_INFO attrs. We use the dynamic address + // attribute because ATTR_EEPROM_XX_INFO attrs are not writable and its difficult + // to override complex attributes. + if(i_target->tryGetAttr<TARGETING::ATTR_DYNAMIC_I2C_DEVICE_ADDRESS>(i2cInfo.devAddr)) + { + TRACDCOMP(g_trac_eeprom, + "Using DYNAMIC_I2C_DEVICE_ADDRESS %.2x for HUID %.8x", + i2cInfo.devAddr, + TARGETING::get_huid(i_target)); + } + //Check for the target at the I2C level l_present = I2C::i2cPresence(i2cMasterTarget, i2cInfo.port, @@ -373,7 +385,7 @@ errlHndl_t eepromReadAttributes ( TARGETING::Target * i_target, // Printing mux info separately, if combined, nothing is displayed char* l_muxPath = o_i2cInfo.i2cMuxPath.toString(); - TRACFCOMP(g_trac_eeprom, "eepromReadAttributes(): " + TRACUCOMP(g_trac_eeprom, "eepromReadAttributes(): " "muxSelector=0x%X, muxPath=%s", o_i2cInfo.i2cMuxBusSelector, l_muxPath); diff --git a/src/usr/i2c/eepromdd.C b/src/usr/i2c/eepromdd.C index 74b6d3692..2243e9b38 100755 --- a/src/usr/i2c/eepromdd.C +++ b/src/usr/i2c/eepromdd.C @@ -41,6 +41,11 @@ // va_list #include "eepromCache.H" #include "eepromdd_hardware.H" +#include <i2c/eepromddreasoncodes.H> +#ifdef __HOSTBOOT_RUNTIME +// Need to be able to convert HB target id's to runtime target ids +#include <targeting/attrrp.H> +#endif extern trace_desc_t* g_trac_eeprom; @@ -87,19 +92,59 @@ errlHndl_t resolveSource(TARGETING::Target * i_target, err = buildEepromRecordHeader(i_target, io_i2cInfo, l_eepromRecordHeader); +#ifndef __HOSTBOOT_RUNTIME // if lookupEepromAddr returns non-zero address // then we know it exists in cache somewhere - if(lookupEepromAddr(l_eepromRecordHeader)) + if(lookupEepromCacheAddr(l_eepromRecordHeader)) { - TRACFCOMP(g_trac_eeprom,"Eeprom found in cache, looking at eecache"); + TRACDCOMP(g_trac_eeprom,"Eeprom found in cache, looking at eecache"); o_source = EEPROM::CACHE; } else { - TRACFCOMP(g_trac_eeprom,"Eeprom not found in cache, looking at hardware"); + TRACDCOMP(g_trac_eeprom,"Eeprom not found in cache, looking at hardware"); o_source = EEPROM::HARDWARE; } - +#else + uint8_t l_instance = TARGETING::AttrRP::getNodeId(i_target); + // if lookupEepromAddr returns non-zero address + // then we know it exists in cache somewhere + if(lookupEepromCacheAddr(l_eepromRecordHeader, l_instance)) + { + TRACDCOMP(g_trac_eeprom,"Eeprom found in cache, looking at eecache"); + o_source = EEPROM::CACHE; + } + else + { + /*@ + * @errortype + * @moduleid EEPROM_RESOLVE_SOURCE + * @reasoncode EEPROM_CACHE_NOT_FOUND_IN_MAP + * @userdata1[0:7] i2c_master_huid + * @userdata1[8:9] port on i2c master eeprom slave is on + * @userdata1[10:11] engine on i2c master eeprom slave is on + * @userdata1[12:13] devAddr of eeprom slave + * @userdata1[14:15] muxSelect of eeprom slave (0xFF is not valid) + * @userdata2[0:7] size of eeprom + * @devdesc resolveSource failed to find cache in map during runtime + */ + err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + EEPROM_RESOLVE_SOURCE, + EEPROM_CACHE_NOT_FOUND_IN_MAP, + TWO_UINT32_TO_UINT64( + l_eepromRecordHeader.completeRecord.i2c_master_huid, + TWO_UINT16_TO_UINT32( + TWO_UINT8_TO_UINT16( + l_eepromRecordHeader.completeRecord.port, + l_eepromRecordHeader.completeRecord.engine), + TWO_UINT8_TO_UINT16( + l_eepromRecordHeader.completeRecord.devAddr, + l_eepromRecordHeader.completeRecord.mux_select))), + l_eepromRecordHeader.completeRecord.cache_copy_size, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + } +#endif return err; } @@ -178,29 +223,35 @@ errlHndl_t eepromPerformOp( DeviceFW::OperationType i_opType, if(l_source == EEPROM::CACHE ) { // Read the copy of the EEPROM data we have cached in PNOR - err = eepromPerformOpCache(i_opType, i_target, io_buffer, io_buflen, i2cInfo); + err = eepromPerformOpCache(i_opType, i_target, + io_buffer, io_buflen, i2cInfo); if(err) { break; } - - // If the operation is a write we also need to "write through" to HW after - // we write cache + // TODO RTC:212469 Complete Work needed for Axone i2c runtime support + #ifndef __HOSTBOOT_RUNTIME if(i_opType == DeviceFW::WRITE) { - err = eepromPerformOpHW(i_opType, i_target, io_buffer, io_buflen, i2cInfo); + // If the operation is a write we also need to + // "write through" to HW after we write cache + err = eepromPerformOpHW(i_opType, i_target, + io_buffer, io_buflen, i2cInfo); } + #endif } else if(l_source == EEPROM::HARDWARE) { // Read from the actual physical EEPROM device - err = eepromPerformOpHW(i_opType, i_target, io_buffer, io_buflen, i2cInfo); + err = eepromPerformOpHW(i_opType, i_target, io_buffer, + io_buflen, i2cInfo); } #else // Read from the actual physical EEPROM device - err = eepromPerformOpHW(i_opType, i_target, io_buffer, io_buflen, i2cInfo); + err = eepromPerformOpHW(i_opType, i_target, io_buffer, + io_buflen, i2cInfo); #endif // CONFIG_SUPPORT_EEPROM_CACHING diff --git a/src/usr/i2c/eepromdd_hardware.C b/src/usr/i2c/eepromdd_hardware.C index 351ca549a..b48c3889e 100644 --- a/src/usr/i2c/eepromdd_hardware.C +++ b/src/usr/i2c/eepromdd_hardware.C @@ -109,7 +109,7 @@ errlHndl_t eepromPerformOpHW(DeviceFW::OperationType i_opType, ( io_i2cInfo.devSize_KB * KILOBYTE ) ) { TRACFCOMP( g_trac_eeprom, - ERR_MRK"eepromPerformOp(): Device Overflow! " + ERR_MRK"eepromPerformOpHW(): Device Overflow! " "C-e/p/dA=%d-%d/%d/0x%X, offset=0x%X, len=0x%X " "devSizeKB=0x%X", io_i2cInfo.eepromRole, io_i2cInfo.engine, io_i2cInfo.port, io_i2cInfo.devAddr, io_i2cInfo.offset, @@ -155,19 +155,19 @@ errlHndl_t eepromPerformOpHW(DeviceFW::OperationType i_opType, l_currentOpLen = l_snglChipSize - io_i2cInfo.offset; } - TRACFCOMP( g_trac_eeprom, - "eepromPerformOp(): i_opType=%d " + TRACDCOMP( g_trac_eeprom, + "eepromPerformOpHW(): i_opType=%d " "C-e/p/dA=%d-%d/%d/0x%X, offset=0x%X, len=0x%X, ", i_opType, io_i2cInfo.eepromRole, io_i2cInfo.engine, - io_i2cInfo.port, io_i2cInfo.devAddr, io_i2cInfo.offset, io_buflen) + io_i2cInfo.port, io_i2cInfo.devAddr, io_i2cInfo.offset, io_buflen); - TRACFCOMP (g_trac_eeprom, - "eepromPerformOp(): snglChipKB=0x%X, chipCount=0x%X, devSizeKB=0x%X", + TRACDCOMP (g_trac_eeprom, + "eepromPerformOpHW(): snglChipKB=0x%X, chipCount=0x%X, devSizeKB=0x%X", l_snglChipSize, io_i2cInfo.chipCount, io_i2cInfo.devSize_KB); // Printing mux info separately, if combined, nothing is displayed char* l_muxPath = io_i2cInfo.i2cMuxPath.toString(); - TRACFCOMP(g_trac_eeprom, "eepromPerformOp(): " + TRACDCOMP(g_trac_eeprom, "eepromPerformOpHW(): " "muxSelector=0x%X, muxPath=%s", io_i2cInfo.i2cMuxBusSelector, l_muxPath); @@ -207,7 +207,7 @@ errlHndl_t eepromPerformOpHW(DeviceFW::OperationType i_opType, else { TRACFCOMP( g_trac_eeprom, - ERR_MRK"eepromPerformOp(): " + ERR_MRK"eepromPerformOpHW(): " "Invalid EEPROM Operation!"); /*@ diff --git a/src/usr/i2c/fapi_i2c_dd.C b/src/usr/i2c/fapi_i2c_dd.C index bf1771865..35a838998 100644 --- a/src/usr/i2c/fapi_i2c_dd.C +++ b/src/usr/i2c/fapi_i2c_dd.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -41,6 +41,8 @@ #include <devicefw/driverif.H> #include <i2c/i2creasoncodes.H> #include "fapi_i2c_dd.H" +#include <time.h> +#include <stdio.h> extern trace_desc_t* g_trac_i2c; @@ -69,6 +71,11 @@ DEVICE_REGISTER_ROUTE( DeviceFW::WILDCARD, TARGETING::TYPE_OCMB_CHIP, fapiI2cPerformOp ); +DEVICE_REGISTER_ROUTE( DeviceFW::WILDCARD, + DeviceFW::FAPI_I2C, + TARGETING::TYPE_PMIC, + fapiI2cPerformOp ); + errlHndl_t fapiI2cPerformOp(DeviceFW::OperationType i_opType, TARGETING::Target * i_target, void * io_buffer, @@ -78,6 +85,7 @@ errlHndl_t fapiI2cPerformOp(DeviceFW::OperationType i_opType, { errlHndl_t l_err = nullptr; errlHndl_t l_err_retryable = nullptr; + bool l_non_retryable_err_hit = false; const uint8_t FAPI_I2C_MAX_RETRIES = 2; TARGETING::ATTR_FAPI_I2C_CONTROL_INFO_type l_i2cInfo; @@ -89,6 +97,10 @@ errlHndl_t fapiI2cPerformOp(DeviceFW::OperationType i_opType, l_cfgData = va_arg( i_args, uint8_t* ); } + timespec_t l_startTime; + timespec_t l_endTime; + clock_gettime(CLOCK_MONOTONIC, &l_startTime); + TRACUCOMP(g_trac_i2c, ENTER_MRK"fapiI2cPerformOp(): " "%s operation on target %.8X", (i_opType==DeviceFW::READ)?"READ":"WRITE", @@ -103,6 +115,18 @@ errlHndl_t fapiI2cPerformOp(DeviceFW::OperationType i_opType, break; } + // If the target has dynamic device address attribute, then use that instead of the + // read-only address found in ATTR_FAPI_I2C_CONTROL_INFO. We use the dynamic address + // attribute because ATTR_FAPI_I2C_CONTROL_INFO is not writable and its difficult + // to override complex attributes. + if(i_target->tryGetAttr<TARGETING::ATTR_DYNAMIC_I2C_DEVICE_ADDRESS>(l_i2cInfo.devAddr)) + { + TRACDCOMP(g_trac_i2c, + "Using DYNAMIC_I2C_DEVICE_ADDRESS %.2x for HUID %.8x", + l_i2cInfo.devAddr, + TARGETING::get_huid(i_target)); + } + // grab target pointer to master TARGETING::TargetService& ts = TARGETING::targetService(); TARGETING::Target * i2cm = ts.toTarget(l_i2cInfo.i2cMasterPath); @@ -136,8 +160,6 @@ errlHndl_t fapiI2cPerformOp(DeviceFW::OperationType i_opType, TARGETING::get_huid(i_target), 0, true /*Add HB SW Callout*/ ); - - l_err->collectTrace( I2C_COMP_NAME ); break; } @@ -164,8 +186,6 @@ errlHndl_t fapiI2cPerformOp(DeviceFW::OperationType i_opType, i_opType, TARGETING::get_huid(i_target), true /*Add HB SW Callout*/ ); - - l_err->collectTrace( I2C_COMP_NAME ); break; } @@ -204,8 +224,7 @@ errlHndl_t fapiI2cPerformOp(DeviceFW::OperationType i_opType, "Error: rc=0x%X, tgt=0x%X, No Retry (retry=%d)", l_err->reasonCode(), TARGETING::get_huid(i_target), retry); - l_err->collectTrace(I2C_COMP_NAME); - + l_non_retryable_err_hit = true; // break from retry loop break; } @@ -267,35 +286,54 @@ errlHndl_t fapiI2cPerformOp(DeviceFW::OperationType i_opType, } // end of retryable error loop + clock_gettime(CLOCK_MONOTONIC, &l_endTime); + char l_time_str[128]; + snprintf(l_time_str, sizeof(l_time_str), + "Start Time: %lu sec %lu ns End Time: %lu sec %lu ns", + l_startTime.tv_sec, l_startTime.tv_nsec, + l_endTime.tv_sec, l_endTime.tv_nsec); + // Handle saved retryable error, if any if (l_err_retryable) { - if (l_err) + // This is the case where we had 1 or more retryable errors and + // eventually hit a non retryable error. + if (l_err && l_non_retryable_err_hit) { // commit original retryable error with new err PLID l_err_retryable->plid(l_err->plid()); TRACFCOMP(g_trac_i2c, "fapiI2cPerformOp(): Committing saved " "retryable error eid=0x%X with plid of returned err 0x%X", l_err_retryable->eid(), l_err_retryable->plid()); - + ERRORLOG::ErrlUserDetailsString(l_time_str) + .addToLog(l_err_retryable); ERRORLOG::ErrlUserDetailsTarget(i_target) .addToLog(l_err_retryable); l_err_retryable->collectTrace(I2C_COMP_NAME); + l_err_retryable->setSev(ERRORLOG::ERRL_SEV_INFORMATIONAL); errlCommit(l_err_retryable, I2C_COMP_ID); } else { - // Since we eventually succeeded, - // delete original retryable error - TRACUCOMP(g_trac_i2c, "fapiI2cPerformOp(): Op successful, " - "deleting saved retryable err eid=0x%X, plid=0x%X", + // In this case we have either hit the max retryable errors and + // failed, or hit one or more retryable errors and eventually + // passed. Either way we do not need this l_err_retryable anymore. + TRACUCOMP(g_trac_i2c, "fapiI2cPerformOp(): Op successful, or we hit max Retries and" + " the caller is polling on this i2c op. Deleting saved retryable err eid=0x%X," + " plid=0x%X.", l_err_retryable->eid(), l_err_retryable->plid()); - delete l_err_retryable; l_err_retryable = nullptr; } } + if(l_err) + { + ERRORLOG::ErrlUserDetailsString(l_time_str) + .addToLog(l_err); + l_err->collectTrace(I2C_COMP_NAME); + } + } while (0); return l_err; @@ -376,10 +414,10 @@ errlHndl_t i2cWrite( TARGETING::Target * i_target, i_buffer, io_buffer_size, DEVICE_I2C_ADDRESS(i_i2cInfo->port, - i_i2cInfo->engine, - i_i2cInfo->devAddr, - i_i2cInfo->i2cMuxBusSelector, - &(i_i2cInfo->i2cMuxPath) ) ); + i_i2cInfo->engine, + i_i2cInfo->devAddr, + i_i2cInfo->i2cMuxBusSelector, + &(i_i2cInfo->i2cMuxPath) ) ); if( l_err ) { diff --git a/src/usr/i2c/i2c.C b/src/usr/i2c/i2c.C index 63b579202..2439f1eff 100755 --- a/src/usr/i2c/i2c.C +++ b/src/usr/i2c/i2c.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2019 */ +/* Contributors Listed Below - COPYRIGHT 2011,2020 */ /* [+] Google Inc. */ /* [+] International Business Machines Corp. */ /* */ @@ -94,6 +94,7 @@ TRAC_INIT( & g_trac_i2cr, "I2CR", KILOBYTE ); #define MAX_NACK_RETRIES 3 #define PAGE_OPERATION 0xffffffff // Special value use to determine type of op #define P9_ENGINE_SCOM_OFFSET 0x1000 +constexpr uint64_t FSI_BUS_SPEED_MHZ = 133; //FSI runs at 133MHz // Derived from ATTR_I2C_BUS_SPEED_ARRAY[engine][port] attribute const TARGETING::ATTR_I2C_BUS_SPEED_ARRAY_type g_var = {{NULL}}; @@ -447,14 +448,16 @@ errlHndl_t i2cPerformOp( DeviceFW::OperationType i_opType, // Else this is not a page operation, call the normal common function else { - if( (subop==DeviceFW::I2C_SMBUS_BLOCK) - || (subop==DeviceFW::I2C_SMBUS_BYTE) - || (subop==DeviceFW::I2C_SMBUS_WORD)) + if( (subop == DeviceFW::I2C_SMBUS_BLOCK) + || (subop == DeviceFW::I2C_SMBUS_BYTE) + || (subop == DeviceFW::I2C_SMBUS_WORD) + || (subop == DeviceFW::I2C_SMBUS_WORD_NO_PEC) + || (subop == DeviceFW::I2C_SMBUS_BLOCK_NO_BYTE_COUNT) ) { args.smbus.commandCode = static_cast<decltype(args.smbus.commandCode)>( va_arg(i_args,uint64_t)); - args.smbus.usePec = true; // All implementations use PEC + args.smbus.usePec = true; // Most implementations use PEC args.i2cMuxBusSelector = va_arg(i_args,uint64_t); args.i2cMuxPath = reinterpret_cast<const TARGETING::EntityPath*>( va_arg(i_args, uint64_t)); @@ -477,11 +480,23 @@ errlHndl_t i2cPerformOp( DeviceFW::OperationType i_opType, if ( args.offset_length != 0 ) { args.offset_buffer = temp; - } } - args.subop=subop; + if (subop == DeviceFW::I2C_SMBUS_WORD_NO_PEC) + { + args.smbus.usePec = false; + args.subop = DeviceFW::I2C_SMBUS_WORD; + } + else if (subop == DeviceFW::I2C_SMBUS_BLOCK_NO_BYTE_COUNT) + { + args.smbus.usePec = false; + args.subop=subop; + } + else + { + args.subop=subop; + } err = i2cCommonOp( i_opType, i_target, @@ -1284,11 +1299,22 @@ errlHndl_t i2cAccessMux( TARGETING::Target* i_masterTarget, if (! (l_i2cMuxTarget->tryGetAttr<TARGETING::ATTR_FAPI_I2C_CONTROL_INFO>(l_muxData)) ) { TRACFCOMP(g_trac_i2c, - "i2cAccessMux(): get attributes failed"); + "i2cAccessMux(): getting ATTR_FAPI_I2C_CONTROL_INFO failed"); break; } - uint8_t l_muxSelector = i_i2cMuxBusSelector; + TARGETING::ATTR_MODEL_type l_muxModel; + if (! (l_i2cMuxTarget->tryGetAttr<TARGETING::ATTR_MODEL>(l_muxModel)) ) + { + TRACFCOMP(g_trac_i2c, + "i2cAccessMux(): getting ATTR_MODEL failed"); + break; + } + + assert(l_muxModel == TARGETING::MODEL_PCA9847, "Invalid model of mux detected"); + const uint8_t PCA9847_ENABLE_BIT = 8; + + uint8_t l_muxSelector = i_i2cMuxBusSelector | PCA9847_ENABLE_BIT; uint8_t *l_ptrMuxSelector = &l_muxSelector; size_t l_muxSelectorSize = sizeof(l_muxSelector); @@ -1430,7 +1456,8 @@ errlHndl_t i2cCommonOp( DeviceFW::OperationType i_opType, /*******************************************************/ /* Perform the I2C Operation */ /*******************************************************/ - + TRACUCOMP( g_trac_i2c, INFO_MRK "i2cCommonOp() -- opType: %d, subOp: %d", + static_cast<uint64_t>(i_opType), i_args.subop); /***********************************************/ /* I2C SMBUS Send Byte */ /***********************************************/ @@ -1598,14 +1625,16 @@ errlHndl_t i2cCommonOp( DeviceFW::OperationType i_opType, /***********************************************/ /* I2C SMBUS Block Write */ /***********************************************/ - else if( (i_opType == DeviceFW::WRITE ) - && (i_args.subop == DeviceFW::I2C_SMBUS_BLOCK)) + else if( (i_opType == DeviceFW::WRITE ) && + ((i_args.subop == DeviceFW::I2C_SMBUS_BLOCK) || + (i_args.subop == DeviceFW::I2C_SMBUS_BLOCK_NO_BYTE_COUNT)) ) { TRACUCOMP(g_trac_i2c, INFO_MRK - "I2C SMBUS Block Write: Command code = 0x%02X, " - "Use PEC = %d. io_buflen = %lu", - i_args.smbus.commandCode, - i_args.smbus.usePec, io_buflen); + "I2C SMBUS Block Write: Command code = 0x%02X, SubCmd = 0x%02X " + "Use PEC = %d. io_buflen = %lu, io_buffer byte0: 0x%02X", + i_args.smbus.commandCode, i_args.subop, + i_args.smbus.usePec, io_buflen, + *reinterpret_cast<uint8_t*>(io_buffer)); // If requested length is for < 1 byte or > 255 bytes for a block // write transaction, throw an error. @@ -1649,12 +1678,29 @@ errlHndl_t i2cCommonOp( DeviceFW::OperationType i_opType, io_buflen, io_buffer, i_args.smbus.usePec); + void * writeStart = &blockWrite.commandCode; + + // byteCount might be altered into commandCode, so store its value + size_t dataByteCount = blockWrite.byteCount; + if (i_args.subop == DeviceFW::I2C_SMBUS_BLOCK_NO_BYTE_COUNT) + { + // Moving commandCode down a byte so it is followed + // immediately by dataBytes[] instead of byteCount + // (this removes byteCount from the block write) + writeStart = &blockWrite.byteCount; + blockWrite.byteCount = blockWrite.commandCode; + blockWrite.messageSize -= sizeof(blockWrite.commandCode); + TRACUCOMP(g_trac_i2c, INFO_MRK + "I2C SMBUS Block Write no-byte-count: removing byteCount," + " msgSize = %d", blockWrite.messageSize); + } + do { size_t writeSize = blockWrite.messageSize; const auto writeSizeExp = writeSize; err = i2cWrite(i_target, - &blockWrite.commandCode, + writeStart, writeSize, i_args); if(err) @@ -1666,7 +1712,8 @@ errlHndl_t i2cCommonOp( DeviceFW::OperationType i_opType, "Write size mismatch; expected %d but got %d", writeSizeExp,writeSize); - io_buflen = blockWrite.byteCount; + + io_buflen = dataByteCount; } while(0); @@ -4308,13 +4355,23 @@ errlHndl_t i2cSetBusVariables ( TARGETING::Target * i_target, if ( io_args.switches.useFsiI2C == 1 ) { - // @todo RTC 117560 - verify correct frequency - local_bus_MHZ = g_I2C_NEST_FREQ_MHZ; + // For FSI I2C we should use the FSI clock + local_bus_MHZ = FSI_BUS_SPEED_MHZ; } else { - // For Host I2C use Nest Frequency - local_bus_MHZ = g_I2C_NEST_FREQ_MHZ; + // For Host I2C use Nest Frequency as base + + // PIB_CLK = NEST_FREQ / 4 + uint64_t pib_clk = g_I2C_NEST_FREQ_MHZ / 4; + +#ifdef CONFIG_AXONE + // Axone has a by-2 internal divider + local_bus_MHZ = pib_clk / 2; +#else + // Nimbus/Cumulus have a by-4 internal divider + local_bus_MHZ = pib_clk / 4; +#endif } io_args.bit_rate_divisor = i2cGetBitRateDivisor(io_args.bus_speed, @@ -5148,8 +5205,13 @@ void getMasterInfo( const TARGETING::Target* i_chip, info.engine = engine; info.freq = i2cGetNestFreq()*FREQ_CONVERSION::HZ_PER_MHZ; // PIB_CLK = NEST_FREQ /4 - // Local Bus = PIB_CLK / 4 +#ifdef CONFIG_AXONE + // Local Bus = PIB_CLK / 2 [Axone] + info.freq = info.freq/8; //convert nest to local bus +#else + // Local Bus = PIB_CLK / 4 [Nimbus/Cumulus] info.freq = info.freq/16; //convert nest to local bus +#endif TRACFCOMP(g_trac_i2c,"getMasterInfo(%.8X): pushing back engine=%d, scomAddr=0x%X",TARGETING::get_huid(i_chip), engine, info.scomAddr); @@ -5447,6 +5509,7 @@ void getDeviceInfo( TARGETING::Target* i_i2cMaster, // Lookup i2c info for the TPM l_err = TPMDD::tpmReadAttributes(pTpm, tpmInfo, locality); + if( NULL != l_err ) { // Unable to get info, so we skip @@ -5474,11 +5537,34 @@ void getDeviceInfo( TARGETING::Target* i_i2cMaster, l_currentDI.slavePort = 0xFF; l_currentDI.busFreqKhz = (tpmInfo.busFreq) / FREQ_CONVERSION::HZ_PER_KHZ; - l_currentDI.deviceType = - TARGETING::HDAT_I2C_DEVICE_TYPE_NUVOTON_TPM; l_currentDI.devicePurpose = TARGETING::HDAT_I2C_DEVICE_PURPOSE_TPM; - strcpy(l_currentDI.deviceLabel,"?nuvoton,npct601,tpm,host"); + + // Read TPM Model attribute to determine some values + if (tpmInfo.model == TPMDD::TPM_MODEL_65x) + { + strcpy(l_currentDI.deviceLabel,"?nuvoton,npct601,tpm,host"); + l_currentDI.deviceType = + TARGETING::HDAT_I2C_DEVICE_TYPE_NUVOTON_TPM; + } + else if (tpmInfo.model == TPMDD::TPM_MODEL_75x) + { + strcpy(l_currentDI.deviceLabel,"?tcg,tpm_i2c_ptp,tpm,host"); + l_currentDI.deviceType = + TARGETING::HDAT_I2C_DEVICE_TYPE_TCG_I2C_TPM; + } + else + { + // Should never get here as tpmReadAttributes will fail if + // unknown TPM Model, but just in case do this: + strcpy(l_currentDI.deviceLabel, + "?unknwon,unknown,tpm,host"); + } + + TRACUCOMP(g_trac_i2c,"TPM 0x%X is Model %d using label %s", + TARGETING::get_huid(pTpm), + tpmInfo.model, + l_currentDI.deviceLabel); o_deviceInfo.push_back(l_currentDI); } //end of tpm iter diff --git a/src/usr/i2c/i2c.H b/src/usr/i2c/i2c.H index eca944479..6f230ac58 100755 --- a/src/usr/i2c/i2c.H +++ b/src/usr/i2c/i2c.H @@ -112,10 +112,10 @@ static uint64_t g_I2C_NEST_FREQ_MHZ = i2cGetNestFreq(); ALWAYS_INLINE inline uint16_t i2cGetBitRateDivisor(uint64_t i_bus_speed_khz, uint64_t i_local_bus_MHZ) { - // BRD = ( ( ( LocalBus_MHZ / 16 ) / i_bus_speed_khz ) - 1 ) / 4 + // BRD = ( ( LocalBus_MHZ) / i_bus_speed_khz ) - 1 ) / 4 // Use tmp variable to convert everything to KHZ safely - uint64_t tmp = ( i_local_bus_MHZ / 16 ) * 1000; + uint64_t tmp = i_local_bus_MHZ * 1000; return ( ( ( tmp / i_bus_speed_khz ) - 1 ) / 4 ); } diff --git a/src/usr/i2c/i2c.mk b/src/usr/i2c/i2c.mk index 6d4ef8935..0300d2c46 100644 --- a/src/usr/i2c/i2c.mk +++ b/src/usr/i2c/i2c.mk @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2015 +# Contributors Listed Below - COPYRIGHT 2015,2019 # [+] International Business Machines Corp. # # @@ -27,4 +27,4 @@ OBJS += eepromdd.o OBJS += eepromdd_hardware.o OBJS += eeprom_utils.o OBJS += errlud_i2c.o -OBJS += $(if $(CONFIG_SUPPORT_EEPROM_CACHING),eepromCache.o) +OBJS += $(if $(CONFIG_SUPPORT_EEPROM_CACHING),eepromCache_common.o) diff --git a/src/usr/i2c/i2cTargetPres.C b/src/usr/i2c/i2cTargetPres.C index c3809f099..c7c9421a3 100644 --- a/src/usr/i2c/i2cTargetPres.C +++ b/src/usr/i2c/i2cTargetPres.C @@ -32,7 +32,7 @@ #include <initservice/initserviceif.H> #include <errl/errlmanager.H> #include "i2c_common.H" - +#include <fapiwrap/fapiWrapif.H> extern trace_desc_t* g_trac_i2c; @@ -182,6 +182,18 @@ errlHndl_t genericI2CTargetPresenceDetect(TARGETING::Target* i_target, //* If we make it through all of the checks then we have verified master is present * //*********************************************************************************** + // If the target has dynamic device address attribute, then use that instead of the + // read-only address found in ATTR_FAPI_I2C_CONTROL_INFO. We use the dynamic address + // attribute because ATTR_FAPI_I2C_CONTROL_INFO is not writable and its difficult + // to override complex attributes. + if(i_target->tryGetAttr<TARGETING::ATTR_DYNAMIC_I2C_DEVICE_ADDRESS>(l_i2cInfo.devAddr)) + { + TRACDCOMP(g_trac_i2c, + "Using DYNAMIC_I2C_DEVICE_ADDRESS %.2x for HUID %.8x", + l_i2cInfo.devAddr, + TARGETING::get_huid(i_target)); + } + //Check for the target at the I2C level l_target_present = I2C::i2cPresence(l_i2cMasterTarget, l_i2cInfo.port, @@ -223,10 +235,6 @@ errlHndl_t ocmbI2CPresencePerformOp(DeviceFW::OperationType i_opType, { errlHndl_t l_invalidateErrl = nullptr; - // @TODO RTC 208696: Gemini vs Explorer Presence Detection via SPD - // This function will be updated to differentiate between Explorer and - // Gemini OCMB chips. For now, presense of an OCMB chip is inferred by - // the presense of the eeprom. bool l_ocmbPresent = EEPROM::eepromPresence(i_target); memcpy(io_buffer, &l_ocmbPresent, sizeof(l_ocmbPresent)); @@ -236,10 +244,97 @@ errlHndl_t ocmbI2CPresencePerformOp(DeviceFW::OperationType i_opType, } /** - * @brief Performs a presence detect operation on a Target that has the + * @brief Performs a presence detect operation on a PMIC Target + * + * @param[in] i_opType Operation type, see DeviceFW::OperationType + * in driverif.H + * @param[in] i_target Presence detect target + * @param[in/out] io_buffer Read: Pointer to output data storage + * Write: Pointer to input data storage + * @param[in/out] io_buflen Input: size of io_buffer (in bytes, always 1) + * Output: Success = 1, Failure = 0 + * @param[in] i_accessType DeviceFW::AccessType enum (userif.H) + * @param[in] i_args This is an argument list for DD framework. + * In this function, there are no arguments. + * @return errlHndl_t + */ +errlHndl_t pmicI2CPresencePerformOp(DeviceFW::OperationType i_opType, + TARGETING::Target* i_target, + void* io_buffer, + size_t& io_buflen, + int64_t i_accessType, + va_list i_args) +{ + + errlHndl_t l_errl = nullptr; + bool l_pmicPresent = 0; + uint8_t l_devAddr; + TARGETING::Target* l_parentOcmb = TARGETING::getImmediateParentByAffinity(i_target); + auto l_parentHwasState = l_parentOcmb->getAttr<TARGETING::ATTR_HWAS_STATE>(); + + do{ + + if(! l_parentHwasState.present) + { + // If the parent chip is not present, then neither is the pmic + // so just break out and return not present + break; + } + + TARGETING::ATTR_REL_POS_type l_relPos = i_target->getAttr<TARGETING::ATTR_REL_POS>(); + + // PMICs will have a different device address depending on the vendor. + // Prior to doing present detection on a pmic we must first query the + // device address from the parent OCMB's SPD + l_errl = FAPIWRAP::get_pmic_dev_addr(l_parentOcmb, + l_relPos, + l_devAddr); + if (l_errl) + { + TRACFCOMP( g_trac_i2c, ERR_MRK"pmicI2CPresencePerformOp() " + "Error attempting to read pmic device address on OCMB 0x%.08X", + TARGETING::get_huid(l_parentOcmb)); + break; + } + + assert(l_devAddr != 0, + "Found devAddr for PMIC 0x%.08x to be 0, this cannot be. Check SPD and REL_POS on target", + TARGETING::get_huid(i_target)); + + if(l_devAddr == FAPIWRAP::NO_PMIC_DEV_ADDR) + { + // There is no pmic device address for this rel position on this ocmb so + // break and return not present. + break; + } + + i_target->setAttr<TARGETING::ATTR_DYNAMIC_I2C_DEVICE_ADDRESS>(l_devAddr); + + l_errl = genericI2CTargetPresenceDetect(i_target, + io_buflen, + l_pmicPresent); + + if (l_errl) + { + TRACFCOMP( g_trac_i2c, ERR_MRK"pmicI2CPresencePerformOp() " + "Error detecting target 0x%.08X, io_buffer will not be set", + TARGETING::get_huid(i_target)); + break; + } + + // Copy variable describing if target is present or not to i/o buffer param + memcpy(io_buffer, &l_pmicPresent, sizeof(l_pmicPresent)); + io_buflen = sizeof(l_pmicPresent); + + }while(0); + + return l_errl; +} + +/** + * @brief Performs a presence detect operation on a Mux Target that has the * ATTR_FAPI_I2C_CONTROL_INFO and can be detected via that device * - * Currently used to detect I2C_MUTEX targets * * @param[in] i_opType Operation type, see DeviceFW::OperationType * in driverif.H @@ -253,7 +348,7 @@ errlHndl_t ocmbI2CPresencePerformOp(DeviceFW::OperationType i_opType, * In this function, there are no arguments. * @return errlHndl_t */ -errlHndl_t basicI2CPresencePerformOp(DeviceFW::OperationType i_opType, +errlHndl_t muxI2CPresencePerformOp(DeviceFW::OperationType i_opType, TARGETING::Target* i_target, void* io_buffer, size_t& io_buflen, @@ -261,13 +356,13 @@ errlHndl_t basicI2CPresencePerformOp(DeviceFW::OperationType i_opType, va_list i_args) { bool l_muxPresent = 0; - errlHndl_t l_returnedError = nullptr; + errlHndl_t l_errl = nullptr; - l_returnedError = genericI2CTargetPresenceDetect(i_target, - io_buflen, - l_muxPresent); + l_errl = genericI2CTargetPresenceDetect(i_target, + io_buflen, + l_muxPresent); - if (l_returnedError) + if (l_errl) { TRACFCOMP( g_trac_i2c, ERR_MRK"basicI2CTargetPresenceDetect() " "Error detecting target 0x%.08X, io_buffer will not be set", @@ -280,7 +375,7 @@ errlHndl_t basicI2CPresencePerformOp(DeviceFW::OperationType i_opType, io_buflen = sizeof(l_muxPresent); } - return l_returnedError; + return l_errl; } // Register the ocmb presence detect function with the device framework @@ -293,12 +388,12 @@ DEVICE_REGISTER_ROUTE(DeviceFW::READ, DEVICE_REGISTER_ROUTE( DeviceFW::READ, DeviceFW::PRESENT, TARGETING::TYPE_I2C_MUX, - basicI2CPresencePerformOp ); + muxI2CPresencePerformOp ); // Register the pmic vrm presence detect function with the device framework DEVICE_REGISTER_ROUTE( DeviceFW::READ, DeviceFW::PRESENT, TARGETING::TYPE_PMIC, - basicI2CPresencePerformOp ); + pmicI2CPresencePerformOp ); } diff --git a/src/usr/i2c/makefile b/src/usr/i2c/makefile index 535484752..10e55c9de 100644 --- a/src/usr/i2c/makefile +++ b/src/usr/i2c/makefile @@ -33,6 +33,7 @@ OBJS += i2c.o OBJS += $(if $(CONFIG_TPMDD),tpmdd.o,) OBJS += fapi_i2c_dd.o OBJS += i2cTargetPres.o +OBJS += $(if $(CONFIG_SUPPORT_EEPROM_CACHING),eepromCache.o) SUBDIRS += test.d SUBDIRS += runtime.d diff --git a/src/usr/i2c/runtime/makefile b/src/usr/i2c/runtime/makefile index e6bf9330b..73d3d464b 100644 --- a/src/usr/i2c/runtime/makefile +++ b/src/usr/i2c/runtime/makefile @@ -1,11 +1,11 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/usr/vpd/runtime/makefile $ +# $Source: src/usr/i2c/runtime/makefile $ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2013,2015 +# Contributors Listed Below - COPYRIGHT 2013,2019 # [+] International Business Machines Corp. # # @@ -32,7 +32,7 @@ include ../i2c.mk #add unique object modules OBJS += rt_i2c.o - +OBJS += $(if $(CONFIG_SUPPORT_EEPROM_CACHING),rt_eepromCache.o) VPATH += .. include $(ROOTPATH)/config.mk diff --git a/src/usr/i2c/runtime/rt_eepromCache.C b/src/usr/i2c/runtime/rt_eepromCache.C new file mode 100644 index 000000000..2b775ddb5 --- /dev/null +++ b/src/usr/i2c/runtime/rt_eepromCache.C @@ -0,0 +1,285 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/i2c/runtime/rt_eepromCache.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/** + * @file rt_eepromCache.C + * + * @brief Runtime functionality of the eeprom cache driver + * + */ + +// ---------------------------------------------- +// Includes +// ---------------------------------------------- + +#include <errl/errlentry.H> +#include <devicefw/driverif.H> +#include <i2c/eepromddreasoncodes.H> +#include <runtime/interface.h> +#include <targeting/runtime/rt_targeting.H> +#include <targeting/common/utilFilter.H> +#include <targeting/attrrp.H> +#include <trace/interface.H> +#include <util/runtime/util_rt.H> +#include <sys/internode.h> +#include <errl/errlentry.H> +#include <errl/errlmanager.H> + +#include "../eepromCache.H" + +// ---------------------------------------------- +// Trace definitions +// ---------------------------------------------- +extern trace_desc_t* g_trac_eeprom; + +//#define TRACSSCOMP(args...) TRACFCOMP(args) +#define TRACSSCOMP(args...) + +namespace EEPROM +{ + +// Any time we access either any of the global variables defined above we want +// to wrap the call in this mutex to avoid multi-threading issues +mutex_t g_eecacheMutex = MUTEX_INITIALIZER; + +uint64_t g_eecachePnorVaddr[MAX_NODES_PER_SYS] = {0,0,0,0,0,0,0,0}; +std::map<eepromRecordHeader, EeepromEntryMetaData_t> g_cachedEeproms[MAX_NODES_PER_SYS]; + +// ------------------------------------------------------------------ +// rtEecacheInit +// ------------------------------------------------------------------ +struct rtEecacheInit +{ + rtEecacheInit() + { + errlHndl_t l_errl = nullptr; + + // Add cache status for the node + TARGETING::TargetHandleList l_nodeList; + getEncResources(l_nodeList, + TARGETING::TYPE_NODE, + TARGETING::UTIL_FILTER_ALL); + // Find all the targets with VPD switches + for (auto & l_node : l_nodeList) + { + uint8_t l_instance = TARGETING::AttrRP::getNodeId(l_node); + uint64_t vpd_size = 0; + eecacheSectionHeader* l_sectionHeader = + reinterpret_cast<eecacheSectionHeader*>( + hb_get_rt_rsvd_mem(Util::HBRT_MEM_LABEL_VPD, + l_instance, vpd_size)); + + g_eecachePnorVaddr[l_instance] = reinterpret_cast<uint64_t>(l_sectionHeader); + + // Check if reserved memory does not exist for this instance + if ((NULL == l_sectionHeader) || (0 == vpd_size)) + { + TRACFCOMP(g_trac_eeprom, + "rtEecacheInit(): ERROR Could not find VPD section of reserved memory for Node %d, ", + l_instance); + /*@ + * @errortype ERRL_SEV_UNRECOVERABLE + * @moduleid EEPROM_CACHE_INIT_RT + * @reasoncode EEPROM_CACHE_NO_VPD_IN_RSV_MEM + * @userdata1 Node Id + * @userdata2 Unused + * + * @devdesc Attempted to lookup VPD in reserved memory + * and failed + * @custdesc A problem occurred during the IPL of the + * system. + */ + l_errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE, + EEPROM::EEPROM_CACHE_INIT_RT, + EEPROM::EEPROM_CACHE_NO_VPD_IN_RSV_MEM, + l_instance, + 0, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + + errlCommit (l_errl, EEPROM_COMP_ID); + break; + + } + + eepromRecordHeader * l_recordHeaderToCopy = nullptr; + uint8_t l_eepromCount = 0; + for(int8_t i = 0; i < MAX_EEPROMS_VERSION_1; i++) + { + // Keep track of current record so we can use outside for loop + l_recordHeaderToCopy = &l_sectionHeader->recordHeaders[i]; + + // If internal_offset is UNSET_INTERNAL_OFFSET_VALUE then we will assume this address not been filled + if(l_recordHeaderToCopy->completeRecord.internal_offset != UNSET_INTERNAL_OFFSET_VALUE) + { + l_eepromCount++; + // Will return true if already found an entry in the list + if(addEepromToCachedList(*l_recordHeaderToCopy, + reinterpret_cast<uint64_t>(l_recordHeaderToCopy), + l_instance)) + { + + TRACFCOMP(g_trac_eeprom, + "rtEecacheInit(): ERROR Duplicate cache entries found in VPD reserved memory section"); + /*@ + * @errortype ERRL_SEV_UNRECOVERABLE + * @moduleid EEPROM_CACHE_INIT_RT + * @reasoncode EEPROM_DUPLICATE_CACHE_ENTRY + * @userdata1[0:31] i2c_master_huid + * @userdata1[32:39] port on i2c master eeprom slave is on + * @userdata1[40:47] engine on i2c master eeprom slave is on + * @userdata1[48:55] devAddr of eeprom slave + * @userdata1[56:63] muxSelect of eeprom slave (0xFF is not valid) + * @userdata2[0:31] size of eeprom + * @userdata2[32:63] Node Id + * @devdesc Attempted to lookup VPD in reserved memory + * and failed + * @custdesc A problem occurred during the IPL of the + * system. + */ + l_errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE, + EEPROM::EEPROM_CACHE_INIT_RT, + EEPROM::EEPROM_DUPLICATE_CACHE_ENTRY, + TWO_UINT32_TO_UINT64( + l_recordHeaderToCopy->completeRecord.i2c_master_huid, + TWO_UINT16_TO_UINT32( + TWO_UINT8_TO_UINT16( + l_recordHeaderToCopy->completeRecord.port, + l_recordHeaderToCopy->completeRecord.engine), + TWO_UINT8_TO_UINT16( + l_recordHeaderToCopy->completeRecord.devAddr, + l_recordHeaderToCopy->completeRecord.mux_select))), + TWO_UINT32_TO_UINT64(l_recordHeaderToCopy->completeRecord.cache_copy_size, + TO_UINT32(l_instance)), + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + + errlCommit (l_errl, EEPROM_COMP_ID); + // Something is wrong so we have committed the unrecoverable + // but keep processing the eeproms because we want a full picture + // of what we understand the eeprom cache contents to be + continue; + } + } + } + + TRACFCOMP(g_trac_eeprom, "Found %d cached eeproms in reserved memory for node %d", + l_eepromCount, l_instance); + + printCurrentCachedEepromMap(); + + } + } + +}; +rtEecacheInit g_rtEecacheInit; + +void printCurrentCachedEepromMap(void) +{ + TRACFCOMP( g_trac_eeprom, + "printCurrentCachedEepromMap():"); + + mutex_lock(&g_eecacheMutex); + for(int8_t i = 0; i < MAX_NODES_PER_SYS; i++) + { + for(std::map<eepromRecordHeader, EeepromEntryMetaData_t>::iterator iter = g_cachedEeproms[i].begin(); + iter != g_cachedEeproms[i].end(); + ++iter) + { + TRACSSCOMP( g_trac_eeprom, + "printTableOfContents(): I2CM Huid: 0x%.08X, Port: 0x%.02X," + " Engine: 0x%.02X, Dev Addr: 0x%.02X," + " Mux Select: 0x%.02X, Size: 0x%.08X", + iter->first.completeRecord.i2c_master_huid, + iter->first.completeRecord.port, + iter->first.completeRecord.engine, + iter->first.completeRecord.devAddr, + iter->first.completeRecord.mux_select, + iter->first.completeRecord.cache_copy_size); + + TRACSSCOMP( g_trac_eeprom, + " " + "Internal Offset: 0x%.08X, Cache Valid: 0x%.02X", + iter->first.completeRecord.internal_offset, + iter->first.completeRecord.cached_copy_valid); + } + } + mutex_unlock(&g_eecacheMutex); + +} + +uint64_t lookupEepromCacheAddr(const eepromRecordHeader& i_eepromRecordHeader, + const uint8_t i_instance) +{ + uint64_t l_vaddr = 0; + std::map<eepromRecordHeader, EeepromEntryMetaData_t>::iterator l_it; + + // Wrap lookup in mutex because reads are not thread safe + mutex_lock(&g_eecacheMutex); + l_it = g_cachedEeproms[i_instance].find(i_eepromRecordHeader); + + if(l_it != g_cachedEeproms[i_instance].end()) + { + l_vaddr = l_it->second.cache_entry_address; + } + mutex_unlock(&g_eecacheMutex); + return l_vaddr; +} + +bool addEepromToCachedList(const eepromRecordHeader & i_eepromRecordHeader, + const uint64_t i_recordHeaderVaddr, + const uint8_t i_instance) +{ + bool l_matchFound = true; + + // Map accesses are not thread safe, make sure this is always wrapped in mutex + mutex_lock(&g_eecacheMutex); + + if(g_cachedEeproms[i_instance].find(i_eepromRecordHeader) == + g_cachedEeproms[i_instance].end()) + { + g_cachedEeproms[i_instance][i_eepromRecordHeader].cache_entry_address = + g_eecachePnorVaddr[i_instance] + i_eepromRecordHeader.completeRecord.internal_offset; + + g_cachedEeproms[i_instance][i_eepromRecordHeader].header_entry_address = + i_recordHeaderVaddr; + + TRACSSCOMP( g_trac_eeprom, + "addEepromToCachedList() Adding I2CM Huid: 0x%.08X, Port: 0x%.02X," + " Engine: 0x%.02X, Dev Addr: 0x%.02X, Mux Select: 0x%.02X," + " Size: 0x%.08X to g_cachedEeproms", + i_eepromRecordHeader.completeRecord.i2c_master_huid, + i_eepromRecordHeader.completeRecord.port, + i_eepromRecordHeader.completeRecord.engine, + i_eepromRecordHeader.completeRecord.devAddr, + i_eepromRecordHeader.completeRecord.mux_select, + i_eepromRecordHeader.completeRecord.cache_copy_size); + + l_matchFound = false; + } + + mutex_unlock(&g_eecacheMutex); + + return l_matchFound; +} + +} // end namespace EEPROM diff --git a/src/usr/i2c/runtime/rt_i2c.C b/src/usr/i2c/runtime/rt_i2c.C index 16f62c76e..d3f5537c6 100755 --- a/src/usr/i2c/runtime/rt_i2c.C +++ b/src/usr/i2c/runtime/rt_i2c.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2019 */ +/* Contributors Listed Below - COPYRIGHT 2015,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -41,7 +41,7 @@ #include <devicefw/driverif.H> #include <i2c/i2creasoncodes.H> #include <runtime/interface.h> -#include <runtime/rt_targeting.H> +#include <targeting/runtime/rt_targeting.H> #include "../errlud_i2c.H" // ---------------------------------------------- @@ -146,10 +146,10 @@ errlHndl_t i2cPerformOp( DeviceFW::OperationType i_opType, int rc = 0; bool l_host_if_enabled = true; - RT_TARG::rtChipId_t proc_id = 0; + TARGETING::rtChipId_t proc_id = 0; // Convert target to proc id - err = RT_TARG::getRtTarget( i_target, + err = TARGETING::getRtTarget( i_target, proc_id); if(err) { diff --git a/src/usr/i2c/test/eecachetest.H b/src/usr/i2c/test/eecachetest.H new file mode 100644 index 000000000..cc5233bf6 --- /dev/null +++ b/src/usr/i2c/test/eecachetest.H @@ -0,0 +1,121 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/i2c/test/eecachetest.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2011,2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef __EECACHETEST_H +#define __EECACHETEST_H + +/** + * @file eepromtest.H + * + * @brief Test cases for the eeprom cache code + */ + +#include <cxxtest/TestSuite.H> +#include "../eepromCache.H" + +extern trace_desc_t* g_trac_eeprom; + +using namespace TARGETING; +using namespace EEPROM; + +class EECACHETest: public CxxTest::TestSuite +{ + public: + + /** + * @brief Verify we can mark a cache as invalid then mark it valid again + */ + void test_invalidateCache( void ) + { + uint8_t l_numTests = 0; + uint8_t l_numFails = 0; + + TRACFCOMP( g_trac_eeprom, ENTER_MRK"test_invalidateCache" ); + + do{ + // Uncomment to verify manually + //printTableOfContents(); + + // Get a processor Target + TARGETING::TargetService& tS = TARGETING::targetService(); + TARGETING::Target* testTarget = NULL; + tS.masterProcChipTargetHandle( testTarget ); + assert(testTarget != NULL); + + // Create dummy eeprom info w/ VPD_PRIMARY set + const EEPROM_ROLE l_eepromRole = EEPROM::VPD_PRIMARY; + + eeprom_addr_t l_primaryVpdEeprom; + l_primaryVpdEeprom.eepromRole = l_eepromRole; + + eepromRecordHeader l_eepromRecordHeader_forLookup; + eepromRecordHeader * l_eepromRecordHeader_realPnor; + + buildEepromRecordHeader( testTarget, + l_primaryVpdEeprom, + l_eepromRecordHeader_forLookup); + + l_eepromRecordHeader_realPnor = reinterpret_cast<eepromRecordHeader *>(lookupEepromHeaderAddr(l_eepromRecordHeader_forLookup)); + + l_numTests++; + if(l_eepromRecordHeader_realPnor->completeRecord.cached_copy_valid != 1) + { + TS_FAIL("test_invalidateCache Master Proc VPD EECACHE is expected to be valid at start of test!"); + l_numFails++; + break; + } + + // Invalidate the cache entry + setIsValidCacheEntry(testTarget, l_eepromRole, 0); + + l_numTests++; + if(l_eepromRecordHeader_realPnor->completeRecord.cached_copy_valid != 0) + { + TS_FAIL("test_invalidateCache Master Proc VPD EECACHE is expected to be invalid after setIsValidCacheEntry(invalid) is called!"); + l_numFails++; + break; + } + + // Re-validate the cache entry + setIsValidCacheEntry(testTarget, l_eepromRole, 1); + + l_numTests++; + if(l_eepromRecordHeader_realPnor->completeRecord.cached_copy_valid != 1) + { + TS_FAIL("test_invalidateCache Master Proc VPD EECACHE is expected to be invalid after setIsValidCacheEntry(valid) is called!"); + l_numFails++; + break; + } + + // Uncomment to verify manually + // printTableOfContents(); + + }while(0); + + TRACFCOMP( g_trac_eeprom, EXIT_MRK"test_getEEPROMs numTests = %d / num fails = %d", l_numTests, l_numFails ); + } + +}; + +#endif
\ No newline at end of file diff --git a/src/usr/i2c/test/makefile b/src/usr/i2c/test/makefile index ef774e6e0..fa9cf31c0 100644 --- a/src/usr/i2c/test/makefile +++ b/src/usr/i2c/test/makefile @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2011,2015 +# Contributors Listed Below - COPYRIGHT 2011,2019 # [+] International Business Machines Corp. # # @@ -26,6 +26,7 @@ ROOTPATH = ../../../.. MODULE = testi2c TESTS = eepromddtest.H +TESTS += $(if $(CONFIG_SUPPORT_EEPROM_CACHING), eecachetest.H, ) TESTS += i2ctest.H TESTS += $(if $(CONFIG_TPMDD),tpmddtest.H,) diff --git a/src/usr/i2c/test/tpmddtest.H b/src/usr/i2c/test/tpmddtest.H index 8cd1fbc2c..0ea987949 100755 --- a/src/usr/i2c/test/tpmddtest.H +++ b/src/usr/i2c/test/tpmddtest.H @@ -111,21 +111,33 @@ class TPMDDTest: public CxxTest::TestSuite uint32_t data = 0x0; size_t dataSize = sizeof(data); + // default to most common ID + uint32_t expected_vendorID = TPMDD::TPM_VENDORID_65x; + uint8_t tpmModel = TPM_MODEL_UNDETERMINED; + TRACFCOMP( g_trac_tpmdd, "testTPMReadVendorID - Start" ); do { -#ifdef CONFIG_AXONE_BRING_UP - TRACFCOMP( g_trac_tpmdd,"Skipping test on Axone" ); - break; -#endif - // Get a TPM Target TARGETING::Target* testTarget = getTestTarget(); if (NULL == testTarget) { - continue; + break; + } + + if ( !(testTarget->tryGetAttr<ATTR_TPM_MODEL>(tpmModel)) ) + { + TS_FAIL("Unable to read ATTR_TPM_MODEL for %.8X target", + get_huid(testTarget)); + break; + } + + // This should match Axone and later systems + if (TPM_MODEL_75x == tpmModel) + { + expected_vendorID = TPMDD::TPM_VENDORID_75x; } num_ops++; @@ -144,16 +156,16 @@ class TPMDDTest: public CxxTest::TestSuite TPMDD_COMP_ID ); delete err; err = NULL; - continue; + break; } else if ((data & TPMDD::TPM_VENDORID_MASK) - // Only 65x supported in simics for now: - != TPMDD::TPM_VENDORID_65x) + != expected_vendorID) { fails++; TS_FAIL( "testTPMReadVendorID - Failed to read " - "correct vendor id ID=0x%X", data); - continue; + "correct vendor id ID=0x%X, expected 0x%X", data, + expected_vendorID); + break; } else @@ -161,7 +173,7 @@ class TPMDDTest: public CxxTest::TestSuite TRACUCOMP(g_trac_tpmdd, "testTPMReadVendorID - " "VendorID returned as expected. ID=0x%X", data); - continue; + break; } } while( 0 ); TRACFCOMP( g_trac_tpmdd, diff --git a/src/usr/i2c/tpmdd.C b/src/usr/i2c/tpmdd.C index a6f96514b..93aac12b9 100755 --- a/src/usr/i2c/tpmdd.C +++ b/src/usr/i2c/tpmdd.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2019 */ +/* Contributors Listed Below - COPYRIGHT 2011,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -51,7 +51,6 @@ #include <i2c/i2cif.H> #include <secureboot/service.H> #include <secureboot/trustedbootif.H> -#include <scom/centaurScomCache.H> // for TRACE_ERR_FMT, TRACE_ERR_ARGS #include "tpmdd.H" #include "errlud_i2c.H" diff --git a/src/usr/initservice/baseinitsvc/initservice.C b/src/usr/initservice/baseinitsvc/initservice.C index d06b36f6a..acd70bb42 100644 --- a/src/usr/initservice/baseinitsvc/initservice.C +++ b/src/usr/initservice/baseinitsvc/initservice.C @@ -1060,8 +1060,7 @@ bool InitService::unregisterShutdownEvent(msg_q_t i_msgQ) { for(EventRegistry_t::iterator r = iv_regMsgQ.begin(); - r != iv_regMsgQ.end(); - ++r) + r != iv_regMsgQ.end();) { // erase all instances if(r->msgQ == i_msgQ) @@ -1072,7 +1071,11 @@ bool InitService::unregisterShutdownEvent(msg_q_t i_msgQ) r->compID, r->msgQ, r->msgType, r->msgPriority); result = true; - iv_regMsgQ.erase(r); + r = iv_regMsgQ.erase(r); + } + else + { + ++r; } } } diff --git a/src/usr/initservice/bootconfig/bootconfig.C b/src/usr/initservice/bootconfig/bootconfig.C index 8e2bf266b..f4839eee7 100644 --- a/src/usr/initservice/bootconfig/bootconfig.C +++ b/src/usr/initservice/bootconfig/bootconfig.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,7 +27,6 @@ /******************************************************************************/ #include <lpc/lpcif.H> #include <devicefw/userif.H> -#include <config.h> #include <errl/errlentry.H> #include "bootconfig.H" diff --git a/src/usr/initservice/bootconfig/bootconfig_ast2400.C b/src/usr/initservice/bootconfig/bootconfig_ast2400.C index 87caa32a5..cd4916203 100644 --- a/src/usr/initservice/bootconfig/bootconfig_ast2400.C +++ b/src/usr/initservice/bootconfig/bootconfig_ast2400.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -33,7 +33,6 @@ #include <trace/interface.H> #include <hwas/common/deconfigGard.H> #include <console/consoleif.H> -#include <config.h> #include <sio/sio.H> #include <devicefw/driverif.H> diff --git a/src/usr/initservice/bootconfig/bootconfigif.C b/src/usr/initservice/bootconfig/bootconfigif.C index 488a8f537..1d931d705 100644 --- a/src/usr/initservice/bootconfig/bootconfigif.C +++ b/src/usr/initservice/bootconfig/bootconfigif.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,12 +27,10 @@ /******************************************************************************/ #include <lpc/lpcif.H> #include <devicefw/userif.H> -#include <config.h> #include <errl/errlentry.H> #include <initservice/bootconfigif.H> #include "bootconfig.H" #include "bootconfig_ast2400.H" -#include <config.h> namespace INITSERVICE { diff --git a/src/usr/initservice/extinitsvc/extinitsvctasks.H b/src/usr/initservice/extinitsvc/extinitsvctasks.H index ef8fb76f0..70b88a0d4 100644 --- a/src/usr/initservice/extinitsvc/extinitsvctasks.H +++ b/src/usr/initservice/extinitsvc/extinitsvctasks.H @@ -276,7 +276,17 @@ const TaskInfo g_exttaskinfolist[] = { EXT_IMAGE, // Extended Module } }, - + /** + * @brief fapiwrap task, handles fapi wrapper for platform libraries + */ + { + "libfapiwrap.so" , // taskname + NULL, // no pointer to fn + { + INIT_TASK, // task type + EXT_IMAGE, // Extended Module + } + }, // @todo RTC:145354 Restore testprdf and testattn in p9 branch /** @@ -430,6 +440,18 @@ const TaskInfo g_exttaskinfolist[] = { }, #endif + /** + * @brief SMF module + */ + { + "libsmf.so", // taskname + NULL, // no pointer to fn + { + INIT_TASK, // task type + EXT_IMAGE, // Extended Module + } + }, + // !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! // NOTE: libistepdisp.so needs to always be last in this list!! // !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! diff --git a/src/usr/initservice/istepdispatcher/istepdispatcher.C b/src/usr/initservice/istepdispatcher/istepdispatcher.C index 8f2d57298..4680bb82c 100644 --- a/src/usr/initservice/istepdispatcher/istepdispatcher.C +++ b/src/usr/initservice/istepdispatcher/istepdispatcher.C @@ -78,7 +78,6 @@ #include <ipmi/ipmiif.H> #endif -#include <config.h> #include <initservice/bootconfigif.H> #include <trace/trace.H> #include <util/utilmbox_scratch.H> @@ -94,6 +93,7 @@ #include <p9_perv_scom_addresses.H> // --------------------------- #include <initservice/extinitserviceif.H> +#include <kernel/terminate.H> namespace ISTEPS_TRACE @@ -2508,6 +2508,9 @@ errlHndl_t IStepDispatcher::sendProgressCode(bool i_needsLock) Util::writeScratchReg( SPLESS::MBOX_SCRATCH_REG5, l_scratch5.data32 ); + //--- Push the scratch reg into kernel to be added into TI area + termSetIstep(l_scratch5.data32); + #ifdef CONFIG_ISTEP_LPC_PORT80_DEBUG // Starting port 80h value for hostboot isteps. Each step started will // increase the value by one. diff --git a/src/usr/initservice/istepdispatcher/istepdispatcher.H b/src/usr/initservice/istepdispatcher/istepdispatcher.H index 558fc95d1..ea383c4c9 100644 --- a/src/usr/initservice/istepdispatcher/istepdispatcher.H +++ b/src/usr/initservice/istepdispatcher/istepdispatcher.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2018 */ +/* Contributors Listed Below - COPYRIGHT 2011,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -44,7 +44,6 @@ #include <initservice/taskargs.H> #include <initservice/initsvcreasoncodes.H> #include <initservice/initsvcstructs.H> -#include <config.h> #include "../baseinitsvc/initservice.H" #include "splesscommon.H" #include "istep_mbox_msgs.H" diff --git a/src/usr/intr/intrrp.C b/src/usr/intr/intrrp.C index d198610af..37b40ca97 100644 --- a/src/usr/intr/intrrp.C +++ b/src/usr/intr/intrrp.C @@ -53,7 +53,6 @@ #include <arch/ppc.H> #include <arch/pirformat.H> #include <arch/pvrformat.H> -#include <config.h> #include <p9_misc_scom_addresses.H> #include <p9n2_misc_scom_addresses_fld.H> #include <util/utilmbox_scratch.H> @@ -547,13 +546,6 @@ errlHndl_t IntrRp::_init() break; } - //Route LSI interrupt events over PSIHB instead of local wire - // This is a HW Bug Workaround for slaves using the PSIHB and - // the master using the local wire - routeLSIInterrupts(l_procIntrHdlr); - - enableLsiInterrupts(); - TRACFCOMP(g_trac_intr, "IntrRp::_init() Enabling PSIHB Interrupts"); //Enable PSIHB Interrupts l_err = enableInterrupts(l_procIntrHdlr); @@ -562,6 +554,13 @@ errlHndl_t IntrRp::_init() TRACFCOMP(g_trac_intr, "IntrRp::_init() Error enabling Interrupts"); break; } + + //Route LSI interrupt events over PSIHB instead of local wire + // This is a HW Bug Workaround for slaves using the PSIHB and + // the master using the local wire + routeLSIInterrupts(l_procIntrHdlr); + + enableLsiInterrupts(); } // Build up list of unregistered LSI sources, at this point no sourced diff --git a/src/usr/ipmibase/ipmibt.C b/src/usr/ipmibase/ipmibt.C index 1f99a3384..8e4a3b38f 100644 --- a/src/usr/ipmibase/ipmibt.C +++ b/src/usr/ipmibase/ipmibt.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2018 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -38,7 +38,6 @@ #include "ipmirp.H" #include <ipmi/ipmiif.H> #include <errno.h> -#include <config.h> // Defined in ipmidd.C extern trace_desc_t * g_trac_ipmi; diff --git a/src/usr/ipmibase/ipmiconfig.C b/src/usr/ipmibase/ipmiconfig.C index 269ae00b2..278f21028 100644 --- a/src/usr/ipmibase/ipmiconfig.C +++ b/src/usr/ipmibase/ipmiconfig.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014,2018 */ +/* Contributors Listed Below - COPYRIGHT 2014,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -30,7 +30,7 @@ // Information contained in the Get Interface Capabilities command // // Request to response time default, in seconds -const uint8_t IPMI::g_bmc_timeout = 5; +const uint8_t IPMI::g_bmc_timeout = 30; // Number of allowed outstanding requests default const uint8_t IPMI::g_outstanding_req = 0x01; diff --git a/src/usr/ipmibase/ipmidd.C b/src/usr/ipmibase/ipmidd.C index 647930442..16582af68 100644 --- a/src/usr/ipmibase/ipmidd.C +++ b/src/usr/ipmibase/ipmidd.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2018 */ +/* Contributors Listed Below - COPYRIGHT 2011,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -42,7 +42,6 @@ #include <initservice/initserviceif.H> #include <util/align.H> #include <lpc/lpcif.H> -#include <config.h> #include <sys/msg.h> #include <errno.h> diff --git a/src/usr/ipmibase/ipmimsg.C b/src/usr/ipmibase/ipmimsg.C index d86b68229..f4d1705bd 100644 --- a/src/usr/ipmibase/ipmimsg.C +++ b/src/usr/ipmibase/ipmimsg.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2018 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -32,7 +32,6 @@ #include "ipmimsg.H" #include <kernel/console.H> -#include <config.h> // Defined in ipmidd.C extern trace_desc_t * g_trac_ipmi; diff --git a/src/usr/ipmibase/ipmirp.C b/src/usr/ipmibase/ipmirp.C index fb502ee98..152521cc0 100644 --- a/src/usr/ipmibase/ipmirp.C +++ b/src/usr/ipmibase/ipmirp.C @@ -36,7 +36,6 @@ #include <devicefw/driverif.H> #include <devicefw/userif.H> -#include <config.h> #include <sys/task.h> #include <initservice/taskargs.H> #include <initservice/initserviceif.H> diff --git a/src/usr/ipmiext/ipmidcmi.C b/src/usr/ipmiext/ipmidcmi.C index 24f192d29..b3f9d1e22 100644 --- a/src/usr/ipmiext/ipmidcmi.C +++ b/src/usr/ipmiext/ipmidcmi.C @@ -5,8 +5,9 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ +/* [+] Maxim Polyakov */ /* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ @@ -34,6 +35,8 @@ #include <ipmi/ipmi_reasoncodes.H> extern trace_desc_t * g_trac_ipmi; +#define DCMI_CAP_RESPONSE_DATA_LENGTH 7 + namespace SENSOR { enum dcmi_cc @@ -42,6 +45,107 @@ namespace SENSOR POWER_LIMIT_NOT_ACTIVE = 0x80, }; + static errlHndl_t getPowerManagementSupportStatus(bool &support) + { + errlHndl_t err = NULL; + IPMI::completion_code cc = IPMI::CC_UNKBAD; + + support = false; + + size_t len = 2; + uint8_t* data = new uint8_t[len]; + data[0] = 0xDC; // Group Extension Identification + data[1] = 0x01; // Selector - Supported DCMI Capabilities + + err = IPMI::sendrecv(IPMI::get_dcmi_capability_info(), cc, len, data); + do + { + if (err) + { + TRACFCOMP(g_trac_ipmi, + "Failed to send DCMI Capabilities Command to BMC"); + break; + } + + if (cc != IPMI::CC_OK) + { + TRACFCOMP(g_trac_ipmi, + "Get DCMI Capabilities Command: " + "bad completion code from BMC=0x%x", + cc); + + /*@ + * @errortype ERRL_SEV_INFORMATIONAL + * @moduleid IPMI::MOD_IPMIDCMI + * @reasoncode IPMI::RC_GET_DCMI_CAP_CMD_FAILED + * @userdata1 BMC IPMI Completion code. + * @devdesc Request to get DCMI Capabilities information + * failed + * @custdesc The DCMI Capabilities Info Command retrieve + * data from the BMC has failed. + * + */ + + err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_INFORMATIONAL, + IPMI::MOD_IPMIDCMI, + IPMI::RC_GET_DCMI_CAP_CMD_FAILED, + static_cast<uint64_t>(cc), + 0, + true); + break; + } + + if (len != DCMI_CAP_RESPONSE_DATA_LENGTH) + { + TRACFCOMP(g_trac_ipmi, + "Get DCMI Capabilities Command: " + "invalid data length=%d", + len); + + /*@ + * @errortype ERRL_SEV_INFORMATIONAL + * @moduleid IPMI::MOD_IPMIDCMI + * @reasoncode IPMI::RC_INVALID_QRESPONSE + * @userdata1 Response data length. + * @devdesc Request to get DCMI Capabilities information + * failed + * @custdesc The DCMI Capabilities Info Command retrieve + * data with invalid length. + * + */ + + err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_INFORMATIONAL, + IPMI::MOD_IPMIDCMI, + IPMI::RC_INVALID_QRESPONSE, + static_cast<uint64_t>(len), + 0, + true); + break; + } + + // from the DCMI spec v1.5, Revision 1.0, August 23, 2011 + // DCMI Capabilities Response Command Format: + // cc: byte 1 completion code + // data: + // data[0]: byte 1 0xDC + // data[1]: byte 2 Major Version (01h) + // data[2]: byte 3 Minor Version (05h) + // data[3]: byte 4 Parameter Revision (02h) + // data[4]: byte 5 Reserved + // data[5]: byte 6 Platform capabilities + // [7:1] Reserved + // [0] Power management + // data[6]: byte 7 Manageability Access Capabilities + support = !!(data[5] & 0x1); + + } while(false); + + delete[] data; + return err; + } + // fetch the user defined power limit stored on the BMC // using the DCMI Get Power Limit command errlHndl_t getUserPowerLimit( uint16_t &o_powerLimit, bool &o_limitActive ) @@ -53,6 +157,31 @@ namespace SENSOR errlHndl_t l_err = NULL; + // Power Management support check + bool support; + l_err = getPowerManagementSupportStatus(support); + if (l_err != NULL) + { + // Since the Power Management support information isn`t received, + // commit this error and still try to read the power limit. If the + // Power Management is really unsupported, the DCMI Get Power Limit + // command will return error code in l_cc + l_err->collectTrace(IPMI_COMP_NAME); + errlCommit(l_err, IPMI_COMP_ID); + + TRACFCOMP(g_trac_ipmi, + "Failed to determine if the BMC supports Power Management"); + + support = true; + } + + if (!support) + { + TRACFCOMP(g_trac_ipmi, + "Power Management is not supported by BMC"); + return NULL; + } + // per DCMI spec data size is 3 bytes size_t len = 3; diff --git a/src/usr/ipmiext/ipmifruinv.C b/src/usr/ipmiext/ipmifruinv.C index e70d5afa0..14ad957d1 100644 --- a/src/usr/ipmiext/ipmifruinv.C +++ b/src/usr/ipmiext/ipmifruinv.C @@ -7,8 +7,9 @@ /* */ /* Contributors Listed Below - COPYRIGHT 2014,2019 */ /* [+] International Business Machines Corp. */ -/* [+] Jim Yuan */ -/* [+] Maxim Polyakov */ +/* [+] Super Micro Computer, Inc. */ +/* [+] YADRO */ +/* [+] lixg */ /* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ @@ -546,42 +547,43 @@ errlHndl_t IpmiFruInv::formatMfgData(std::vector<uint8_t> i_mfgDateData, { errlHndl_t l_errl = NULL; - // MB keyword size is 8 hex bytes, throw an error if it is smaller so we - // don't do an invalid access. - if (i_mfgDateData.size() != 8) + do { - /*@ - * @errortype - * @moduleid IPMI::MOD_IPMIFRU_INV - * @reasoncode IPMI::RC_INVALID_VPD_DATA - * @userdata1 Size of vpd data - * - * @devdesc VPD data is invalid size - */ - l_errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_INFORMATIONAL, - IPMI::MOD_IPMIFRU_INV, - IPMI::RC_INVALID_VPD_DATA, - i_mfgDateData.size()); - - TARGETING::Target* nodeTarget = NULL; - TARGETING::PredicateCTM nodeFilter(TARGETING::CLASS_ENC, - TARGETING::TYPE_NODE); - TARGETING::TargetRangeFilter nodeItr( - TARGETING::targetService().begin(), - TARGETING::targetService().end(), - &nodeFilter); - - nodeTarget = *nodeItr; - - // Callout out node since that is where the VPD lives - l_errl->addHwCallout(nodeTarget, - HWAS::SRCI_PRIORITY_HIGH, - HWAS::NO_DECONFIG, - HWAS::GARD_NULL ); + // MB keyword size is 8 hex bytes, throw an error if it is smaller so we + // don't do an invalid access. + if (i_mfgDateData.size() != 8) + { + /*@ + * @errortype + * @moduleid IPMI::MOD_IPMIFRU_INV + * @reasoncode IPMI::RC_INVALID_VPD_DATA + * @userdata1 Size of vpd data + * + * @devdesc VPD data is invalid size + */ + l_errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_INFORMATIONAL, + IPMI::MOD_IPMIFRU_INV, + IPMI::RC_INVALID_VPD_DATA, + i_mfgDateData.size()); + + TARGETING::Target* nodeTarget = NULL; + TARGETING::PredicateCTM nodeFilter(TARGETING::CLASS_ENC, + TARGETING::TYPE_NODE); + TARGETING::TargetRangeFilter nodeItr( + TARGETING::targetService().begin(), + TARGETING::targetService().end(), + &nodeFilter); + + nodeTarget = *nodeItr; + + // Callout out node since that is where the VPD lives + l_errl->addHwCallout(nodeTarget, + HWAS::SRCI_PRIORITY_HIGH, + HWAS::NO_DECONFIG, + HWAS::GARD_NULL ); + break; + } - } - else - { // Convert Centuries / Years / months / day / hour / minute / second // into a uint64 representing number of minute since 1/1/96 @@ -594,6 +596,25 @@ errlHndl_t IpmiFruInv::formatMfgData(std::vector<uint8_t> i_mfgDateData, uint8_t hour = bcd2_to_int(i_mfgDateData.at(5)); uint8_t minute = bcd2_to_int(i_mfgDateData.at(6)); + // Do some sanity checking on the data so the math below doesn't + // go crazy and cause a crash + if ( (century < 20) + || (month < 1) || (month > 12) + || (day < 1) || (day > 31) + || (hour > 23) || (minute > 59) ) + { + o_mfgDate = 0xFFFFFFFF; + TRACFCOMP(g_trac_ipmi,"MfgDate error: %02X %02X %02X %02X %02X %02X %02X ", + i_mfgDateData.at(0), + i_mfgDateData.at(1), + i_mfgDateData.at(2), + i_mfgDateData.at(3), + i_mfgDateData.at(4), + i_mfgDateData.at(5), + i_mfgDateData.at(6)); + break; + } + // Subtract year uint8_t numOfYears = (century*100 + year) - 1996; // Subtract month @@ -612,6 +633,7 @@ errlHndl_t IpmiFruInv::formatMfgData(std::vector<uint8_t> i_mfgDateData, // Add a day for every leap year // Check if we need to consider the current year + // Year is related to century, anybody familiar with this may fix it if (month <= 2) { // We don't need to consider this year for a leap year, as it @@ -638,7 +660,7 @@ errlHndl_t IpmiFruInv::formatMfgData(std::vector<uint8_t> i_mfgDateData, // Convert into minutes o_mfgDate = (((numOfDays*24)*60) + (hour*60) + minute); - } + } while(0); return l_errl; } @@ -2406,6 +2428,8 @@ void IPMIFRUINV::gatherSetData(const TARGETING::Target* i_pSys, TARGETING::PredicateCTM predChip(TARGETING::CLASS_CHIP); TARGETING::PredicateCTM predDimm(TARGETING::CLASS_LOGICAL_CARD, TARGETING::TYPE_DIMM); + TARGETING::PredicateCTM predOcmb(TARGETING::CLASS_CHIP, + TARGETING::TYPE_OCMB_CHIP); TARGETING::PredicatePostfixExpr checkExpr; TARGETING::PredicateHwas l_present; // @todo-RTC:124553 - Additional logic for deconfigured Frus @@ -2427,6 +2451,9 @@ void IPMIFRUINV::gatherSetData(const TARGETING::Target* i_pSys, checkExpr.push(&predDimm).Or().push(&l_present).And(); } + // We do NOT want to process fruInv for OCMB_CHIP targets + checkExpr.push(&predOcmb).Not().And(); + TARGETING::TargetHandleList pCheckPres; TARGETING::targetService().getAssociated( pCheckPres, i_pSys, TARGETING::TargetService::CHILD, TARGETING::TargetService::ALL, diff --git a/src/usr/ipmiext/ipmisensor.C b/src/usr/ipmiext/ipmisensor.C index 5dd428d06..ae6032353 100644 --- a/src/usr/ipmiext/ipmisensor.C +++ b/src/usr/ipmiext/ipmisensor.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014,2018 */ +/* Contributors Listed Below - COPYRIGHT 2014,2019 */ /* [+] Google Inc. */ /* [+] International Business Machines Corp. */ /* */ @@ -1363,7 +1363,7 @@ namespace SENSOR TARGETING::targetService().getTopLevelTarget(sys); assert(sys != NULL); getChildAffinityTargets(nodes, sys, TARGETING::CLASS_ENC, - TARGETING::TYPE_NODE); + TARGETING::TYPE_NODE, false); assert(!nodes.empty()); //Backplane sensor ID @@ -1390,8 +1390,13 @@ namespace SENSOR static uint16_t L_NV_bits = 0; errlHndl_t l_err = nullptr; - if (L_NV_bits == 0) - { + do { + // only do the lookup once + if (L_NV_bits != 0) + { + break; + } + // grab system enclosure node TARGETING::TargetHandle_t l_sys = NULL; TARGETING::TargetHandleList l_nodeTargets; @@ -1399,61 +1404,63 @@ namespace SENSOR assert(l_sys != NULL); getChildAffinityTargets(l_nodeTargets, l_sys, TARGETING::CLASS_ENC, TARGETING::TYPE_NODE); - assert(!l_nodeTargets.empty()); + if(l_nodeTargets.empty()) + { + TRACFCOMP(g_trac_ipmi,"getNVCfgIDBit(): No functional nodes - forcing invalid config"); + break; + } // get keyword size first PVPD::pvpdRecord l_Record = PVPD::VNDR; PVPD::pvpdKeyword l_KeyWord = PVPD::NV; size_t l_nvKwdSize = 0; l_err = deviceRead(l_nodeTargets[0],NULL,l_nvKwdSize, - DEVICE_PVPD_ADDRESS(l_Record,l_KeyWord)); - if (!l_err) + DEVICE_PVPD_ADDRESS(l_Record,l_KeyWord)); + if (l_err) { - if (l_nvKwdSize == sizeof(HDAT::hdatNVKwdStruct_t)) + TRACFCOMP(g_trac_ipmi,"getNVCfgIDBit(): Error getting VNDR:NV size"); + break; + } + + if (l_nvKwdSize != sizeof(HDAT::hdatNVKwdStruct_t)) + { + TRACFCOMP(g_trac_ipmi,"Invalid NV keyword size: %d, expected %d",l_nvKwdSize,sizeof(HDAT::hdatNVKwdStruct_t)); + break; + } + + uint8_t l_kwd[l_nvKwdSize] = {0}; + // now read the keyword + l_err = deviceRead(l_nodeTargets[0],l_kwd,l_nvKwdSize, + DEVICE_PVPD_ADDRESS(l_Record,l_KeyWord)); + if (l_err) + { + TRACFCOMP(g_trac_ipmi,"getNVCfgIDBit(): Error reading VNDR:NV"); + break; + } + + HDAT::hdatNVKwdStruct_t * NVptr = + reinterpret_cast<HDAT::hdatNVKwdStruct_t*>(l_kwd); + + // Valid NV keyword config has NV00 as magic header + if ( !memcmp((char*)&(NVptr->magic),"NV00", 4) ) + { + uint8_t cfgID = NVptr->config; + if (cfgID < 16) // maximum setting (bits 0-15) { - uint8_t l_kwd[l_nvKwdSize] = {0}; - // now read the keyword - l_err = deviceRead(l_nodeTargets[0],l_kwd,l_nvKwdSize, - DEVICE_PVPD_ADDRESS(l_Record,l_KeyWord)); - if (!l_err) - { - HDAT::hdatNVKwdStruct_t * NVptr = - reinterpret_cast<HDAT::hdatNVKwdStruct_t*>(l_kwd); - - // Valid NV keyword config has NV00 as magic header - if ( !memcmp((char*)&(NVptr->magic),"NV00", 4) ) - { - uint8_t cfgID = NVptr->config; - if (cfgID < 16) // maximum setting (bits 0-15) - { - L_NV_bits = 0x0001 << cfgID; - } - else - { - TRACFCOMP(g_trac_ipmi,"getNVCfgIDBit(): Invalid NV config 0x%02X", cfgID); - } - } - else - { - TRACFCOMP(g_trac_ipmi, "Invalid NV magic header: 0x%.8X", NVptr->magic); - TRACFBIN(g_trac_ipmi, "NV KEYWORD", l_kwd, l_nvKwdSize); - } - } - else - { - TRACFCOMP(g_trac_ipmi,ERR_MRK"%.8X Error getting VNDR record data",l_err->eid()); - } + L_NV_bits = 0x0001 << cfgID; } else { - TRACFCOMP(g_trac_ipmi,"Invalid NV keyword size: %d, expected %d",l_nvKwdSize,sizeof(HDAT::hdatNVKwdStruct_t)); + TRACFCOMP(g_trac_ipmi,"getNVCfgIDBit(): Invalid NV config 0x%02X", cfgID); + break; } } else { - TRACFCOMP(g_trac_ipmi,ERR_MRK"%.8X Error getting VNDR record size",l_err->eid()); + TRACFCOMP(g_trac_ipmi, "Invalid NV magic header: 0x%.8X", NVptr->magic); + TRACFBIN(g_trac_ipmi, "NV KEYWORD", l_kwd, l_nvKwdSize); } - } + } while(0); o_cfgID_bitwise = L_NV_bits; diff --git a/src/usr/ipmiext/runtime/rt_ipmirp.C b/src/usr/ipmiext/runtime/rt_ipmirp.C index 496b3f782..83b4d9b10 100644 --- a/src/usr/ipmiext/runtime/rt_ipmirp.C +++ b/src/usr/ipmiext/runtime/rt_ipmirp.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -30,7 +30,6 @@ #include <ipmi/ipmi_reasoncodes.H> #include <ipmi/ipmiif.H> -#include <config.h> #include <sys/task.h> #include <initservice/taskargs.H> #include <initservice/initserviceif.H> diff --git a/src/usr/isteps/expupd/expupd.C b/src/usr/isteps/expupd/expupd.C new file mode 100644 index 000000000..3f63ac191 --- /dev/null +++ b/src/usr/isteps/expupd/expupd.C @@ -0,0 +1,393 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/isteps/expupd/expupd.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +#include <expupd/expupd_reasoncodes.H> +#include <pnor/pnorif.H> +#include <targeting/common/commontargeting.H> +#include <targeting/common/utilFilter.H> +#include <errl/errlentry.H> +#include <errl/errlmanager.H> +#include <isteps/hwpisteperror.H> +#include <isteps/hwpistepud.H> +#include <fapi2.H> +#include <fapi2/plat_hwp_invoker.H> +#include <fapi2/hw_access.H> +#include <chipids.H> +#include <trace/interface.H> +#include <hbotcompid.H> +#include "ocmbFwImage.H" +#include <exp_fw_update.H> +#include <initservice/istepdispatcherif.H> + +using namespace ISTEP_ERROR; +using namespace ERRORLOG; +using namespace TARGETING; + +namespace expupd +{ + +// Initialize the trace buffer for this component +trace_desc_t* g_trac_expupd = nullptr; +TRAC_INIT(&g_trac_expupd, EXPUPD_COMP_NAME, 2*KILOBYTE); + +/** + * @brief Structure for retrieving the explorer SHA512 hash value + * + */ +typedef union sha512regs +{ + struct + { + uint32_t imageId; + uint8_t sha512Hash[HEADER_SHA512_SIZE]; + }; + uint8_t unformatted[sizeof(uint32_t) + HEADER_SHA512_SIZE]; +}sha512regs_t; + +/** + * @brief Retrieve the SHA512 hash for the currently flashed explorer + * firmware image. + * + * @param[in] i_target Target of the OCMB chip to retrieve the SHA512 hash + * @param[out] o_regs Structure for storing the retrieved SHA512 hash + * + * @return NULL on success. Non-null on failure. + */ +errlHndl_t getFlashedHash(TargetHandle_t i_target, sha512regs_t& o_regs) +{ + fapi2::buffer<uint64_t> l_scomBuffer; + uint8_t* l_scomPtr = reinterpret_cast<uint8_t*>(l_scomBuffer.pointer()); + fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>l_fapi2Target(i_target); + errlHndl_t l_err = nullptr; + + //Start addres of hash register (a.k.a. RAM1 register) + const uint32_t HASH_REG_ADDR = 0x00002200; + + // loop until we've filled the sha512regs_t struct + for(uint32_t l_bytesCopied = 0; l_bytesCopied < sizeof(sha512regs_t); + l_bytesCopied += sizeof(uint32_t)) + { + // Use getScom, this knows internally whether to use i2c or inband + FAPI_INVOKE_HWP(l_err, getScom, + l_fapi2Target, + HASH_REG_ADDR + l_bytesCopied, + l_scomBuffer); + if(l_err) + { + TRACFCOMP(g_trac_expupd, ERR_MRK + "getFlashedHash: Failed reading SHA512 hash from" + " ocmb[0x%08x]. bytesCopied[%u]", + TARGETING::get_huid(i_target), l_bytesCopied); + + break; + } + + // copy scom buffer into the unformatted uint8_t array. + // Even though the scom buffer is 8 bytes, only 4 bytes are read and + // copied into the least significant 4 bytes. + memcpy(&o_regs.unformatted[l_bytesCopied], l_scomPtr + sizeof(uint32_t), + sizeof(uint32_t)); + } + + return l_err; +} + +/** + * @brief Check flash image SHA512 hash value of each explorer chip + * and update the flash if it does not match the SHA512 hash + * of the image in PNOR. + * + * @param[out] o_stepError Error handle for logging istep failures + * + */ +void updateAll(IStepError& o_stepError) +{ + bool l_imageLoaded = false; + errlHndl_t l_err = nullptr; + bool l_rebootRequired = false; + + // Get a list of OCMB chips + TARGETING::TargetHandleList l_ocmbTargetList; + getAllChips(l_ocmbTargetList, TYPE_OCMB_CHIP); + + Target* l_pTopLevel = nullptr; + targetService().getTopLevelTarget( l_pTopLevel ); + assert(l_pTopLevel, "expupd::updateAll: no TopLevelTarget"); + + TRACFCOMP(g_trac_expupd, ENTER_MRK + "updateAll: %d ocmb chips found", + l_ocmbTargetList.size()); + + do + { + // If no OCMB chips exist, we're done. + if(l_ocmbTargetList.size() == 0) + { + break; + } + + // Check if we have any overrides to force our behavior + auto l_forced_behavior = + l_pTopLevel->getAttr<TARGETING::ATTR_OCMB_FW_UPDATE_OVERRIDE>(); + + // Exit now if told to + if( TARGETING::OCMB_FW_UPDATE_BEHAVIOR_PREVENT_UPDATE + == l_forced_behavior ) + { + TRACFCOMP(g_trac_expupd, INFO_MRK "Skipping update due to override (PREVENT_UPDATE)"); + break; + } + + // Read explorer fw image from pnor + PNOR::SectionInfo_t l_pnorSectionInfo; + rawImageInfo_t l_imageInfo; + +#ifdef CONFIG_SECUREBOOT + l_err = PNOR::loadSecureSection(PNOR::OCMBFW); + if(l_err) + { + TRACFCOMP(g_trac_expupd, ERR_MRK + "updateAll: Failed to load OCMBFW section" + " from PNOR!"); + + l_err->collectTrace(EXPUPD_COMP_NAME); + + // Create IStep error log and cross reference to error that occurred + o_stepError.addErrorDetails( l_err ); + + // Commit Error + errlCommit( l_err, EXPUPD_COMP_ID ); + + break; + } +#endif //CONFIG_SECUREBOOT + + l_imageLoaded = true; + + // get address and size of packaged image + l_err = PNOR::getSectionInfo(PNOR::OCMBFW, l_pnorSectionInfo); + if(l_err) + { + TRACFCOMP(g_trac_expupd, ERR_MRK + "updateAll: Failure in getSectionInfo()"); + + l_err->collectTrace(EXPUPD_COMP_NAME); + + // Create IStep error log and cross reference to error that occurred + o_stepError.addErrorDetails( l_err ); + + // Commit Error + errlCommit( l_err, EXPUPD_COMP_ID ); + break; + } + + // Verify the header and retrieve address, size and + // SHA512 hash of unpackaged image + l_err = ocmbFwValidateImage( + l_pnorSectionInfo.vaddr, + l_pnorSectionInfo.secureProtectedPayloadSize, + l_imageInfo); + if(l_err) + { + TRACFCOMP(g_trac_expupd, ERR_MRK + "updateAll: Failure in expupdValidateImage"); + + l_err->collectTrace(EXPUPD_COMP_NAME); + + // Create IStep error log and cross reference to error that occurred + o_stepError.addErrorDetails( l_err ); + + // Commit Error + errlCommit( l_err, EXPUPD_COMP_ID ); + break; + } + + // For each explorer chip, compare flash hash with PNOR hash and + // create a list of explorer chips with differing hash values. + TARGETING::TargetHandleList l_flashUpdateList; + for(const auto & l_ocmbTarget : l_ocmbTargetList) + { + sha512regs_t l_regs; + + //skip all gemini ocmb chips (not updateable) + if(l_ocmbTarget->getAttr<TARGETING::ATTR_CHIP_ID>() == + POWER_CHIPID::GEMINI_16) + { + TRACFCOMP(g_trac_expupd, + "updateAll: skipping update of gemini OCMB 0x%08x", + TARGETING::get_huid(l_ocmbTarget)); + continue; + } + + //retrieve the SHA512 hash for the currently flashed image. + l_err = getFlashedHash(l_ocmbTarget, l_regs); + if(l_err) + { + TRACFCOMP(g_trac_expupd, ERR_MRK + "updateAll: Failure in getFlashedHash(huid = 0x%08x)", + TARGETING::get_huid(l_ocmbTarget)); + + l_err->collectTrace(EXPUPD_COMP_NAME); + + // Create IStep error log and cross reference to error + // that occurred + o_stepError.addErrorDetails(l_err); + + errlCommit(l_err, EXPUPD_COMP_ID); + + //Don't stop on error, go to next target. + continue; + } + + // Trace the hash and image ID values + TRACFCOMP(g_trac_expupd, + "updateAll: OCMB 0x%08x image ID=0x%08x", + TARGETING::get_huid(l_ocmbTarget), l_regs.imageId); + TRACFBIN(g_trac_expupd, "SHA512 HASH FROM EXPLORER", + l_regs.sha512Hash, HEADER_SHA512_SIZE); + + //Compare hashes. If different, add to list for update. + if(memcmp(l_regs.sha512Hash, l_imageInfo.imageSHA512HashPtr, + HEADER_SHA512_SIZE)) + { + TRACFCOMP(g_trac_expupd, + "updateAll: SHA512 hash mismatch on ocmb[0x%08x]", + TARGETING::get_huid(l_ocmbTarget)); + + //add target to our list of targets needing an update + l_flashUpdateList.push_back(l_ocmbTarget); + } + else + { + TRACFCOMP(g_trac_expupd, + "updateAll: SHA512 hash for ocmb[0x%08x]" + " matches SHA512 hash of PNOR image.", + TARGETING::get_huid(l_ocmbTarget)); + + // Add every OCMB to the update list if told to + if( TARGETING::OCMB_FW_UPDATE_BEHAVIOR_FORCE_UPDATE + == l_forced_behavior ) + { + TRACFCOMP(g_trac_expupd, INFO_MRK "Forcing update due to override (FORCE_UPDATE)"); + l_flashUpdateList.push_back(l_ocmbTarget); + } + } + } + + TRACFCOMP(g_trac_expupd, + "updateAll: updating flash for %d OCMB chips", + l_flashUpdateList.size()); + + // Exit now if we were asked to only do the check portion + if( TARGETING::OCMB_FW_UPDATE_BEHAVIOR_CHECK_BUT_NO_UPDATE + == l_forced_behavior ) + { + TRACFCOMP(g_trac_expupd, INFO_MRK "Skipping update due to override (CHECK_BUT_NO_UPDATE)"); + break; + } + + // update each explorer in the list of chips needing updates + for(const auto & l_ocmb : l_flashUpdateList) + { + TRACFCOMP(g_trac_expupd, "updateAll: updating OCMB 0x%08x", + TARGETING::get_huid(l_ocmb)); + fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>l_fapi2Target(l_ocmb); + + // reset watchdog for each ocmb as this function can be very slow + INITSERVICE::sendProgressCode(); + + // Invoke procedure + FAPI_INVOKE_HWP(l_err, exp_fw_update, l_fapi2Target, + l_imageInfo.imagePtr, l_imageInfo.imageSize); + if (l_err) + { + TRACFCOMP(g_trac_expupd, + "Error from exp_fw_update for OCMB 0x%08x", + TARGETING::get_huid(l_ocmb)); + + l_err->collectTrace(EXPUPD_COMP_NAME); + + // Create IStep error log and cross reference to error + // that occurred + o_stepError.addErrorDetails( l_err ); + + errlCommit(l_err, EXPUPD_COMP_ID); + + // Don't stop on error, go to next target. + continue; + } + else + { + TRACFCOMP(g_trac_expupd, + "updateAll: successfully updated OCMB 0x%08x", + TARGETING::get_huid(l_ocmb)); + + // Request reboot for new firmware to be used + l_rebootRequired = true; + } + } + }while(0); + + // unload explorer fw image + if(l_imageLoaded) + { +#ifdef CONFIG_SECUREBOOT + l_err = PNOR::unloadSecureSection(PNOR::OCMBFW); + if(l_err) + { + TRACFCOMP(g_trac_expupd, ERR_MRK + "updateAll: Failed to unload OCMBFW"); + + l_err->collectTrace(EXPUPD_COMP_NAME); + + // Create IStep error log and cross reference to error that occurred + o_stepError.addErrorDetails( l_err ); + + // Commit Error + errlCommit( l_err, EXPUPD_COMP_ID ); + } +#endif //CONFIG_SECUREBOOT + } + + // force reboot if any updates were successful + if(l_rebootRequired) + { + TRACFCOMP(g_trac_expupd, + "updateAll: OCMB chip(s) was updated. Requesting reboot..."); + auto l_reconfigAttr = + l_pTopLevel->getAttr<TARGETING::ATTR_RECONFIGURE_LOOP>(); + l_reconfigAttr |= RECONFIGURE_LOOP_OCMB_FW_UPDATE; + l_pTopLevel->setAttr<TARGETING::ATTR_RECONFIGURE_LOOP>(l_reconfigAttr); + } + else + { + TRACFCOMP(g_trac_expupd, "updateAll: No OCMB chips were updated"); + } + + + TRACFCOMP(g_trac_expupd, EXIT_MRK"updateAll()"); +} + +}//namespace expupd diff --git a/src/usr/isteps/expupd/expupd.mk b/src/usr/isteps/expupd/expupd.mk new file mode 100644 index 000000000..b7b769e7a --- /dev/null +++ b/src/usr/isteps/expupd/expupd.mk @@ -0,0 +1,38 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/isteps/expupd/expupd.mk $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2019 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +EXTRAINCDIR += ${ROOTPATH}/src/import +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/explorer/common/include/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/explorer/procedures/hwp/memory/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/utils/imageProcs +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/procedures/hwp/ffdc/ +EXTRAINCDIR += ${ROOTPATH}/src/import/hwpf/fapi2/include +EXTRAINCDIR += ${ROOTPATH}/src/include/usr/fapi2 +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/utils + +OBJS += expupd.o +OBJS += ocmbFwImage.o + +# Need to build exp_fw_update procedure +OBJS += exp_fw_update.o diff --git a/src/usr/isteps/expupd/expupd_trace.H b/src/usr/isteps/expupd/expupd_trace.H new file mode 100644 index 000000000..a2da13a8f --- /dev/null +++ b/src/usr/isteps/expupd/expupd_trace.H @@ -0,0 +1,40 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/isteps/expupd/expupd_trace.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef __EXPUPD_TRACE_H +#define __EXPUPD_TRACE_H + +/******************************************************************************/ +// Includes +/******************************************************************************/ +#include <trace/interface.H> + +namespace expupd +{ + +extern trace_desc_t *g_trac_expupd; + +} // end namespace + +#endif diff --git a/src/usr/isteps/expupd/makefile b/src/usr/isteps/expupd/makefile new file mode 100644 index 000000000..2ee89f6e4 --- /dev/null +++ b/src/usr/isteps/expupd/makefile @@ -0,0 +1,35 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/isteps/expupd/makefile $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2019 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +ROOTPATH = ../../../.. +MODULE = expupd + +SUBDIRS += test.d + +include expupd.mk + +include ${ROOTPATH}/config.mk + +VPATH += ${ROOTPATH}/src/import/chips/ocmb/explorer/procedures/hwp/memory/ diff --git a/src/usr/isteps/expupd/ocmbFwImage.C b/src/usr/isteps/expupd/ocmbFwImage.C new file mode 100644 index 000000000..dee2affdd --- /dev/null +++ b/src/usr/isteps/expupd/ocmbFwImage.C @@ -0,0 +1,391 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/isteps/expupd/ocmbFwImage.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#include "ocmbFwImage.H" +#include <expupd/ocmbFwImage_const.H> +#include <expupd/expupd_reasoncodes.H> +#include "expupd_trace.H" +#include <errl/errlentry.H> +#include <errl/errlmanager.H> +#include <hbotcompid.H> +#include <algorithm> + +#define EXPUPD_8BYTE_ALIGNED(_SIZE) (!(_SIZE & 0x7)) + +namespace expupd +{ + +/** + * @brief Validates a tagged data triplet + * @param[in] i_tripletPtr starting address of a tagged data triplet + * @param[in] i_endDataPtr ending address of the OCMB firmware header + * @param[out] o_imageInfo Structure will hold pointer to SHA512 hash (if found) + * @param[out] o_numBytes total number of bytes used by this tagged data triplet + * @return errlHndl_t indicating success or failure + * + */ +errlHndl_t parseTaggedDataTriplet(const uint8_t* i_tripletPtr, + const uint8_t* i_endDataPtr, + rawImageInfo_t& o_imageInfo, + uint32_t& o_numBytes) +{ + errlHndl_t l_err = nullptr; + + // Determine start of the data for the tagged data triplet + const uint8_t* l_dataStartPtr = i_tripletPtr + sizeof(taggedTriplet_t); + const taggedTriplet_t* l_ttPtr = + reinterpret_cast<const taggedTriplet_t*>(i_tripletPtr); + + // Assume failure and set number of bytes consumed to 0 + o_numBytes = 0; + + do + { + // Check that we have enough room for the triplet + if((l_dataStartPtr > i_endDataPtr) || + ((l_dataStartPtr + l_ttPtr->dataSize) > i_endDataPtr) || + !EXPUPD_8BYTE_ALIGNED(l_ttPtr->dataSize)) + { + int64_t l_reqdSize = sizeof(taggedTriplet_t); + l_reqdSize += (l_dataStartPtr > i_endDataPtr)? 0: l_ttPtr->dataSize; + + int64_t l_allocSize = + reinterpret_cast<int64_t>(i_endDataPtr - i_tripletPtr); + + TRACFCOMP(g_trac_expupd, ERR_MRK + "parseTaggedDataTriplet: Triplet does not fit or is" + " misaligned. bytesReqd[%d] bytesAllocated[%d]", + l_reqdSize, + l_allocSize); + + /* @errorlog + * @errortype ERRL_SEV_PREDICTIVE + * @moduleid EXPUPD::MOD_PARSE_TAGGED_DATA_TRIPLET + * @reasoncode EXPUPD::INVALID_DATA_TRIPLET_SIZE + * @userdata1 allocated size + * @userdata2 required size + * @devdesc Tagged data triplet size is too big or misaligned + * @custdesc Error occurred during system boot. + */ + l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_PREDICTIVE, + EXPUPD::MOD_PARSE_TAGGED_DATA_TRIPLET, + EXPUPD::INVALID_DATA_TRIPLET_SIZE, + l_allocSize, + l_reqdSize, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + break; + } + + // Check for the SHA512 tag + if(l_ttPtr->tagId == TAG_SHA512) + { + // Check that hash data is complete + if(l_ttPtr->dataSize != HEADER_SHA512_SIZE) + { + TRACFCOMP(g_trac_expupd, ERR_MRK + "parseTaggedDataTriplet: Invalid hash triplet size." + " expected[%u] actual[%u]", + HEADER_SHA512_SIZE, + l_ttPtr->dataSize); + + /* @errorlog + * @errortype ERRL_SEV_PREDICTIVE + * @moduleid EXPUPD::MOD_PARSE_TAGGED_DATA_TRIPLET + * @reasoncode EXPUPD::INVALID_HASH_TRIPLET_SIZE + * @userdata1 Expected Size + * @userdata2 Actual Size + * @devdesc Incorrect hash size in OCMB image header + * @custdesc Error occurred during system boot. + */ + l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_PREDICTIVE, + EXPUPD::MOD_PARSE_TAGGED_DATA_TRIPLET, + EXPUPD::INVALID_HASH_TRIPLET_SIZE, + HEADER_SHA512_SIZE, + l_ttPtr->dataSize, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + break; + } + + // Save off pointer to hash for later. + o_imageInfo.imageSHA512HashPtr = l_dataStartPtr; + } + else if(l_ttPtr->tagId == TAG_KEY_VALUE_PAIRS) + { + //trace up to MAX_BIN_TRACE bytes of the data in case it is useful + TRACFBIN(g_trac_expupd, "OCMB FW IMAGE KEY/VALUE DATA", + l_dataStartPtr, + std::min(l_ttPtr->dataSize, MAX_BIN_TRACE)); + } + else + { + //unsupported tag id. + TRACFCOMP(g_trac_expupd, ERR_MRK + "parseTaggedDataTriplet: Invalid tag id[%u].", + l_ttPtr->tagId); + + /* @errorlog + * @errortype ERRL_SEV_PREDICTIVE + * @moduleid EXPUPD::MOD_PARSE_TAGGED_DATA_TRIPLET + * @reasoncode EXPUPD::INVALID_TAG_ID + * @userdata1 tag id + * @userdata2 <unused> + * @devdesc Invalid tag id found in OCMB image header + * @custdesc Error occurred during system boot. + */ + l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_PREDICTIVE, + EXPUPD::MOD_PARSE_TAGGED_DATA_TRIPLET, + EXPUPD::INVALID_TAG_ID, + l_ttPtr->tagId, + 0, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + break; + } + + //Parsing was successful. Set bytes consumed. + o_numBytes = sizeof(taggedTriplet_t) + l_ttPtr->dataSize; + }while(0); + + return l_err; +} + +/** + * @brief Validates OCMB firmware header of packaged image + * + * @param[in] i_imageStart Start address of packaged image + * @param[in] i_imageSize Size of packaged image + * @param[out] o_imageInfo Information pertaining to image after + * being stripped of OCMB firmware header + * @return errlHndl_t indicating success or failure + * + */ +errlHndl_t ocmbFwValidateImage(const uint64_t i_imageStart, + const uint64_t i_imageSize, + rawImageInfo_t& o_imageInfo) +{ + const uint8_t* l_imageStartPtr = + reinterpret_cast<const uint8_t*>(i_imageStart); + errlHndl_t l_err = nullptr; + + TRACFCOMP(g_trac_expupd, + ENTER_MRK "ocmbFwValidateImage(): startAddr[0x%016x] size[%u]", + i_imageStart, i_imageSize); + + //clear out o_imageInfo + memset(&o_imageInfo, 0, sizeof(o_imageInfo)); + + do + { + const uint64_t l_minHeaderSize = + sizeof(ocmbFwHeader_t) + + sizeof(taggedTriplet_t) + HEADER_SHA512_SIZE; + + const uint64_t l_maxHeaderSize = + std::min(static_cast<const uint64_t>(HEADER_MAX_SIZE), + i_imageSize); + + // Check input parameters + if((!l_imageStartPtr) || (i_imageSize < l_minHeaderSize)) + { + TRACFCOMP(g_trac_expupd, ERR_MRK + "ocmbFwValidateImage: Invalid image address[%p] or" + " size[%u]", + l_imageStartPtr, i_imageSize); + + /* @errorlog + * @errortype ERRL_SEV_PREDICTIVE + * @moduleid EXPUPD::MOD_OCMB_FW_VALIDATE_IMAGE + * @reasoncode EXPUPD::INVALID_PARMS + * @userdata1 i_imageStart + * @userdata2 i_imageSize + * @devdesc Invalid size or address for OCMB Flash Image + * @custdesc Error occurred during system boot. + */ + l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_PREDICTIVE, + EXPUPD::MOD_OCMB_FW_VALIDATE_IMAGE, + EXPUPD::INVALID_PARMS, + i_imageStart, + i_imageSize, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + break; + } + + const ocmbFwHeader_t* l_header = + reinterpret_cast<const ocmbFwHeader_t*>(l_imageStartPtr); + + // Check eye catcher value + if(l_header->eyeCatcher != EYE_CATCHER_VALUE) + { + TRACFCOMP(g_trac_expupd, ERR_MRK + "ocmbFwValidateImage: Invalid eye catcher value: " + "expected[0x%016llx] actual[0x%016llx]", + EYE_CATCHER_VALUE, l_header->eyeCatcher); + /* @errorlog + * @errortype ERRL_SEV_PREDICTIVE + * @moduleid EXPUPD::MOD_OCMB_FW_VALIDATE_IMAGE + * @reasoncode EXPUPD::INVALID_EYE_CATCHER + * @userdata1 Expected Value + * @userdata2 Actual Value + * @devdesc Invalid eye catcher value for OCMB Flash Image + * @custdesc Error occurred during system boot. + */ + l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_PREDICTIVE, + EXPUPD::MOD_OCMB_FW_VALIDATE_IMAGE, + EXPUPD::INVALID_EYE_CATCHER, + EYE_CATCHER_VALUE, + l_header->eyeCatcher, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + break; + } + + // Check header version + if((l_header->majorVersion != HEADER_VERSION_MAJOR) || + (l_header->minorVersion != HEADER_VERSION_MINOR)) + { + TRACFCOMP(g_trac_expupd, ERR_MRK + "ocmbFwValidateImage: Unsupported header version: %u.%u", + l_header->majorVersion, l_header->minorVersion); + /* @errorlog + * @errortype ERRL_SEV_PREDICTIVE + * @moduleid EXPUPD::MOD_OCMB_FW_VALIDATE_IMAGE + * @reasoncode EXPUPD::INVALID_HEADER_VERSION + * @userdata1 majorVersion + * @userdata2 minorVersion + * @devdesc Invalid header version for OCMB Flash Image + * @custdesc Error occurred during system boot. + */ + l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_PREDICTIVE, + EXPUPD::MOD_OCMB_FW_VALIDATE_IMAGE, + EXPUPD::INVALID_HEADER_VERSION, + l_header->majorVersion, + l_header->minorVersion, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + break; + } + + //Check that header size is within min/max range and 8byte aligned + if((l_header->headerSize < l_minHeaderSize) || + (l_header->headerSize > l_maxHeaderSize) || + !EXPUPD_8BYTE_ALIGNED(l_header->headerSize)) + { + TRACFCOMP(g_trac_expupd, ERR_MRK + "ocmbFwValidateImage: Unsupported header size: %u bytes", + l_header->headerSize); + /* @errorlog + * @errortype ERRL_SEV_PREDICTIVE + * @moduleid EXPUPD::MOD_OCMB_FW_VALIDATE_IMAGE + * @reasoncode EXPUPD::INVALID_HEADER_SIZE + * @userdata1 header size + * @userdata2 maximum allowed size + * @devdesc Invalid header size for OCMB Flash Image + * @custdesc Error occurred during system boot. + */ + l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_PREDICTIVE, + EXPUPD::MOD_OCMB_FW_VALIDATE_IMAGE, + EXPUPD::INVALID_HEADER_SIZE, + l_header->headerSize, + l_maxHeaderSize, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + break; + } + + // Trace header information. + TRACFCOMP(g_trac_expupd, "OCMB HEADER: Version[%u.%u] size[%u]" + " triplets[%u]", + l_header->majorVersion, + l_header->minorVersion, + l_header->headerSize, + l_header->numTriplets); + + // Parse all tagged triplet data + const uint8_t* l_curTripletPtr = l_imageStartPtr + sizeof(*l_header); + const uint8_t* l_endDataPtr = l_imageStartPtr + l_header->headerSize; + for(uint32_t l_curTriplet = 0; + l_curTriplet < l_header->numTriplets; + l_curTriplet++) + { + uint32_t l_numBytes = 0; + + // This will set o_imageInfo.imageSHA512Ptr if + // SHA512 hash is found + l_err = parseTaggedDataTriplet(l_curTripletPtr, + l_endDataPtr, + o_imageInfo, + l_numBytes); + if(l_err) + { + TRACFCOMP(g_trac_expupd, ERR_MRK + "ocmbFwValidateImage: Failed parsing tagged data" + " triplet %u of %u", + l_curTriplet + 1, l_header->numTriplets); + break; + } + + // Advance to next triplet + l_curTripletPtr += l_numBytes; + } + if(l_err) + { + break; + } + + // Check if we found a SHA512 hash in the header + if(!o_imageInfo.imageSHA512HashPtr) + { + TRACFCOMP(g_trac_expupd, ERR_MRK + "ocmbFwValidateImage: No SHA512 Hash found in header!"); + /* @errorlog + * @errortype ERRL_SEV_PREDICTIVE + * @moduleid EXPUPD::MOD_OCMB_FW_VALIDATE_IMAGE + * @reasoncode EXPUPD::MISSING_SHA512_HASH + * @userdata1 <unused> + * @userdata2 <unused> + * @devdesc Missing SHA512 hash in OCMB Flash Image + * @custdesc Error occurred during system boot. + */ + l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_PREDICTIVE, + EXPUPD::MOD_OCMB_FW_VALIDATE_IMAGE, + EXPUPD::MISSING_SHA512_HASH, + 0, 0, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + break; + } + + //** Header is valid if we made it this far ** + + // Trace the SHA512 hash + TRACFBIN(g_trac_expupd, "OCMB FW IMAGE SHA512 HASH", + o_imageInfo.imageSHA512HashPtr, HEADER_SHA512_SIZE); + + // Set the image start address and size and we are done here. + o_imageInfo.imagePtr = l_imageStartPtr + l_header->headerSize; + o_imageInfo.imageSize = i_imageSize - l_header->headerSize; + + }while(0); + + TRACFCOMP(g_trac_expupd, EXIT_MRK "ocmbFwValidateImage()"); + return l_err; +} + +} //namespace expupd + diff --git a/src/usr/isteps/expupd/ocmbFwImage.H b/src/usr/isteps/expupd/ocmbFwImage.H new file mode 100644 index 000000000..5e5de2e64 --- /dev/null +++ b/src/usr/isteps/expupd/ocmbFwImage.H @@ -0,0 +1,68 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/isteps/expupd/ocmbFwImage.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef __OCMBFWIMAGE_H +#define __OCMBFWIMAGE_H + +/** + * @file ocmbFwImage.H + * + * Interface for validating the OCMB firmware image from PNOR + * + */ + +#include <errl/errlentry.H> + +namespace expupd +{ + +constexpr uint32_t HEADER_SHA512_SIZE = 64; + +/** + * @brief Parameters pertaining to an unpackaged (raw) OCMB firmware image + */ +typedef struct rawImageInfo +{ + const uint8_t* imagePtr; + size_t imageSize; + const uint8_t* imageSHA512HashPtr; +}rawImageInfo_t; + +/** + * @brief Validates OCMB firmware header of packaged image + * + * @param[in] i_imageStart Start address of packaged image + * @param[in] i_imageSize Size of packaged image + * @param[out] o_imageInfo Information pertaining to image after + * being stripped of OCMB firmware header + * @return errlHndl_t indicating success or failure + * + */ +errlHndl_t ocmbFwValidateImage(const uint64_t i_imageStart, + const uint64_t i_imageSize, + rawImageInfo_t& o_imageInfo); + +}//namespace expupd + +#endif diff --git a/src/usr/isteps/expupd/test/expupdatetest.H b/src/usr/isteps/expupd/test/expupdatetest.H new file mode 100644 index 000000000..1fed4813e --- /dev/null +++ b/src/usr/isteps/expupd/test/expupdatetest.H @@ -0,0 +1,175 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/isteps/expupd/test/expupdatetest.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +#ifndef __EXPUPDATETEST_H +#define __EXPUPDATETEST_H + +/** + * @file expupdatetest.H + * + * @brief Test cases for explorer chip firmware update + */ + +#include <cxxtest/TestSuite.H> +#include <errl/errlmanager.H> +#include <errl/errlentry.H> +#include <fapi2.H> +#include <plat_hwp_invoker.H> +#include <lib/inband/exp_inband.H> +#include <exp_data_structs.H> +#include <exp_fw_update.H> +#include <generic/memory/lib/utils/endian_utils.H> +#ifndef __HOSTBOOT_RUNTIME +#include <vfs/vfs.H> // module_is_loaded & module_load +#endif +#include <test/exptest_utils.H> + +const char MSS_LIBRARY_NAME[] = "libisteps_mss.so"; +const char EXPUPD_LIBRARY_NAME[] = "libexpupd.so"; + +/** + * @brief Generic function to load a module + * @param i_modName - module name to load + * @return error handle if module_load call fails + */ +errlHndl_t loadModule(const char * i_modName) +{ + errlHndl_t err = nullptr; + +// VFS functions only compilable in non-runtime environment +#ifndef __HOSTBOOT_RUNTIME + if(!VFS::module_is_loaded(i_modName)) + { + err = VFS::module_load(i_modName); + if(err) + { + TS_FAIL("loadModule() - %s load failed", i_modName ); + } + else + { + TS_TRACE("loadModule: %s loaded", i_modName); + } + } +#endif + return err; +} + + +class ExpUpdateTest: public CxxTest::TestSuite +{ + public: + + /** + * @brief Test the explorer firmware update procedure + */ + void testExpFwUpdate( void ) + { + errlHndl_t l_errl = nullptr; + + uint8_t l_dataBuffer[4096] = {0}; + + // Create a vector of TARGETING::Target pointers + TARGETING::TargetHandleList l_chipList; + + // Get a list of all of the functioning ocmb chips + TARGETING::getAllChips(l_chipList, TARGETING::TYPE_OCMB_CHIP, true); + + TARGETING::HB_MUTEX_SERIALIZE_TEST_LOCK_ATTR l_mutex = exptest::getTestMutex(); + if (l_mutex == nullptr) + { + TS_FAIL("testExpFwUpdate: unable to get test mutex"); + } + else + { + for (const auto & l_ocmb: l_chipList) + { + fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>l_fapi2_target(l_ocmb); + + // Inband operations can't be run at the same time + // atomic section >> + mutex_lock(l_mutex); + + // Invoke procedure + FAPI_INVOKE_HWP(l_errl, exp_fw_update, l_fapi2_target, + l_dataBuffer, sizeof(l_dataBuffer)); + + // << atomic section + mutex_unlock(l_mutex); + if (l_errl) + { +#if 0 // skipping exp_fw_update error until simics is changed - @fixme:RTC-209865 + TS_FAIL("Error from exp_fw_update for 0x%.8X target", + TARGETING::get_huid(l_ocmb)); +#endif + break; + } + } + + if (l_errl) + { + errlCommit(l_errl, CXXTEST_COMP_ID); + } + } + + TS_INFO("testExpFwUpdate: exiting"); + }; + + /** + * @brief Constructor + */ + ExpUpdateTest() : CxxTest::TestSuite() + { + // All modules are loaded by runtime, + // so testcase loading of modules is not required +#ifndef __HOSTBOOT_RUNTIME + errlHndl_t err = nullptr; + + err = loadModule(MSS_LIBRARY_NAME); + if(err) + { + TS_FAIL("ExpUpdateTest() - Constuctor: failed to load MSS module"); + errlCommit( err, CXXTEST_COMP_ID ); + } + err = loadModule(EXPUPD_LIBRARY_NAME); + if(err) + { + TS_FAIL("ExpUpdateTest() - Constuctor: failed to load EXPUPD module"); + errlCommit( err, CXXTEST_COMP_ID ); + } +#endif + }; + + + /** + * @brief Destructor + */ + ~ExpUpdateTest() + { + }; + + private: +}; + +#endif diff --git a/src/usr/isteps/expupd/test/makefile b/src/usr/isteps/expupd/test/makefile new file mode 100644 index 000000000..d028105f9 --- /dev/null +++ b/src/usr/isteps/expupd/test/makefile @@ -0,0 +1,33 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/isteps/expupd/test/makefile $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2019 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +ROOTPATH = ../../../../.. +MODULE = testexpupd + +include test.mk + +TESTS = expupdatetest.H + +include ${ROOTPATH}/config.mk diff --git a/src/usr/isteps/expupd/test/test.mk b/src/usr/isteps/expupd/test/test.mk new file mode 100644 index 000000000..aca30b7f4 --- /dev/null +++ b/src/usr/isteps/expupd/test/test.mk @@ -0,0 +1,35 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/isteps/expupd/test/test.mk $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2019 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +EXTRAINCDIR += ${ROOTPATH}/src/include/usr/fapi2 +EXTRAINCDIR += ${ROOTPATH}/src/import/hwpf/fapi2/include +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/utils/imageProcs +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/procedures/hwp/ffdc +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/explorer/procedures/hwp/memory/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/explorer/common/include +EXTRAINCDIR += ${ROOTPATH}/src/import +EXTRAINCDIR += ${ROOTPATH}/src/usr/expaccess + diff --git a/src/usr/isteps/istep06/call_host_update_master_tpm.C b/src/usr/isteps/istep06/call_host_update_master_tpm.C index 284d43450..fa374f279 100644 --- a/src/usr/isteps/istep06/call_host_update_master_tpm.C +++ b/src/usr/isteps/istep06/call_host_update_master_tpm.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -31,6 +31,8 @@ #include <trustedbootif.H> #include <initservice/isteps_trace.H> #include <secureboot/service.H> +#include <secureboot/phys_presence_if.H> +#include <config.h> namespace ISTEP_06 { @@ -39,7 +41,7 @@ void* call_host_update_master_tpm( void *io_pArgs ) { ISTEP_ERROR::IStepError l_stepError; - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_host_update_master_tpm entry" ); errlHndl_t l_err = nullptr; @@ -67,10 +69,28 @@ void* call_host_update_master_tpm( void *io_pArgs ) ERRORLOG::errlCommit( l_err, SECURE_COMP_ID ); } - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "call_host_update_master_tpm exit" ); + // Check for Physical Presence +#ifdef CONFIG_PHYS_PRES_PWR_BUTTON + l_err = SECUREBOOT::detectPhysPresence(); + if (l_err) + { + // @TODO RTC 210301 - Handle Error Log Correctly, but for now + // just delete it + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "call_host_update_master_tpm: Error back from " + "SECUREBOOT::detectPhysPresence: rc=0x%X, plid=0x%X. " + "Deleting error for now", + ERRL_GETRC_SAFE(l_err), ERRL_GETPLID_SAFE(l_err)); + delete l_err; + l_err = nullptr; + } +#endif + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "call_host_update_master_tpm exit" ); return l_stepError.getErrorHandle(); + + } }; diff --git a/src/usr/isteps/istep06/call_host_voltage_config.C b/src/usr/isteps/istep06/call_host_voltage_config.C index 6cb647e9b..5e7b0eb94 100644 --- a/src/usr/isteps/istep06/call_host_voltage_config.C +++ b/src/usr/isteps/istep06/call_host_voltage_config.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -489,7 +489,7 @@ void* call_host_voltage_config( void *io_pArgs ) l_err->addHwCallout(l_proc, HWAS::SRCI_PRIORITY_HIGH, - HWAS::DECONFIG, + HWAS::DELAYED_DECONFIG, HWAS::GARD_NULL ); // Create IStep error log and @@ -538,7 +538,7 @@ void* call_host_voltage_config( void *io_pArgs ) l_err->addHwCallout(l_proc, HWAS::SRCI_PRIORITY_HIGH, - HWAS::DECONFIG, + HWAS::DELAYED_DECONFIG, HWAS::GARD_NULL ); // Create IStep error log and diff --git a/src/usr/isteps/istep06/host_discover_targets.C b/src/usr/isteps/istep06/host_discover_targets.C index 89e0dd8dd..7884056c1 100644 --- a/src/usr/isteps/istep06/host_discover_targets.C +++ b/src/usr/isteps/istep06/host_discover_targets.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] Google Inc. */ /* [+] International Business Machines Corp. */ /* */ @@ -59,6 +59,7 @@ //SBE interfacing #include <sbeio/sbeioif.H> #include <sys/misc.h> +#include <sbe/sbeif.H> #include <p9_query_core_access_state.H> #include <p9_setup_sbe_config.H> @@ -618,13 +619,71 @@ void* host_discover_targets( void *io_pArgs ) errlCommit (l_err, ISTEP_COMP_ID); } } // end if (l_pMasterProcChip) - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "host_discover_targets exit" ); #ifdef CONFIG_PRINT_SYSTEM_INFO print_system_info(); #endif + // Handle the case where we don't have a valid memory map swap victim due + // to a module swap - See TARGETING::adjustMemoryMap() + if( l_pTopLevel->getAttr<TARGETING::ATTR_FORCE_SBE_UPDATE>() + == TARGETING::FORCE_SBE_UPDATE_BAR_MISMATCH ) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "Forcing SBE update to handle swapped memory map" ); + l_err = SBE::updateProcessorSbeSeeproms(); + if(l_err) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "host_discover_targets: Error calling updateProcessorSbeSeeproms"); + l_stepError.addErrorDetails( l_err ); + errlCommit( l_err, ISTEP_COMP_ID ); + } + + // We should never get here, if we do that means the SBE update didn't + // actually happen. That is a problem since we're currently running + // with mismatched BAR data + TARGETING::ATTR_XSCOM_BASE_ADDRESS_type l_xscom = + l_pMasterProcChip->getAttr<TARGETING::ATTR_XSCOM_BASE_ADDRESS>(); + TARGETING::ATTR_PROC_EFF_FABRIC_GROUP_ID_type l_group = + l_pMasterProcChip->getAttr<TARGETING::ATTR_PROC_EFF_FABRIC_GROUP_ID>(); + TARGETING::ATTR_PROC_EFF_FABRIC_CHIP_ID_type l_chip = + l_pMasterProcChip->getAttr<TARGETING::ATTR_PROC_EFF_FABRIC_CHIP_ID>(); + /*@ + * @errortype + * @moduleid ISTEP::MOD_DISCOVER_TARGETS + * @reasoncode ISTEP::RC_CANNOT_BOOT_WITH_MISMATCHED_BARS + * @userdata1 Current XSCOM BAR + * @userdata2[0-31] Desired ATTR_PROC_EFF_FABRIC_GROUP_ID + * @userdata2[32:63] Desired ATTR_PROC_EFF_FABRIC_GROUP_ID + * @devdesc Not able to update the SBE to correct the BAR mismatch + * @custdesc Required module update failed + */ + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + ISTEP::MOD_DISCOVER_TARGETS, + ISTEP::RC_CANNOT_BOOT_WITH_MISMATCHED_BARS, + l_xscom, + TWO_UINT32_TO_UINT64( + l_group, + l_chip)); + + l_err->addHwCallout( l_pMasterProcChip, + HWAS::SRCI_PRIORITY_HIGH, + HWAS::NO_DECONFIG, + HWAS::GARD_NULL ); + + l_err->collectTrace(TARG_COMP_NAME); + l_err->collectTrace(SBE_COMP_NAME); + l_err->collectTrace("ISTEPS_TRACE",256); + + // Create IStep error log and cross ref error that occurred + l_stepError.addErrorDetails( l_err ); + errlCommit( l_err, ISTEP_COMP_ID ); + } + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "host_discover_targets exit" ); + return l_stepError.getErrorHandle(); } diff --git a/src/usr/isteps/istep06/host_gard.C b/src/usr/isteps/istep06/host_gard.C index 4a9852e17..1f16c866c 100644 --- a/src/usr/isteps/istep06/host_gard.C +++ b/src/usr/isteps/istep06/host_gard.C @@ -51,7 +51,6 @@ #include <console/consoleif.H> // Custom compile configs -#include <config.h> #ifdef CONFIG_DRTM #include <secureboot/drtm.H> diff --git a/src/usr/isteps/istep06/host_init_fsi.C b/src/usr/isteps/istep06/host_init_fsi.C index 2e294893e..455068633 100644 --- a/src/usr/isteps/istep06/host_init_fsi.C +++ b/src/usr/isteps/istep06/host_init_fsi.C @@ -37,7 +37,6 @@ #include <isteps/hwpisteperror.H> #include <attributeenums.H> #include <secureboot/trustedbootif.H> -#include <config.h> //Targeting #include <targeting/common/commontargeting.H> diff --git a/src/usr/isteps/istep07/call_mss_attr_update.C b/src/usr/isteps/istep07/call_mss_attr_update.C index 4e015d7b8..a9e10d040 100644 --- a/src/usr/isteps/istep07/call_mss_attr_update.C +++ b/src/usr/isteps/istep07/call_mss_attr_update.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -62,7 +62,6 @@ #include <fapi2/target.H> #include <fapi2/plat_hwp_invoker.H> -#include <config.h> // HWP #include <p9_mss_attr_update.H> @@ -72,6 +71,9 @@ #include <isteps/mem_utils.H> +#include <secureboot/smf_utils.H> +#include <initservice/mboxRegs.H> + namespace ISTEP_07 { @@ -307,6 +309,33 @@ errlHndl_t check_proc0_memory_config(IStepError & io_istepErr) (l_procIds[i].proc)->getAttr<ATTR_FABRIC_CHIP_ID>()); } + TARGETING::Target* l_sys = nullptr; + TARGETING::targetService().getTopLevelTarget(l_sys); + assert(l_sys != nullptr, "Top level target is nullptr!"); + + TARGETING::ATTR_MASTER_MBOX_SCRATCH_type l_scratchRegs; + assert( + l_sys->tryGetAttr<TARGETING::ATTR_MASTER_MBOX_SCRATCH>(l_scratchRegs), + "failed to get MASTER_MBOX_SCRATCH"); + INITSERVICE::SPLESS::MboxScratch6_t l_scratch6 { + l_scratchRegs[INITSERVICE::SPLESS::SCRATCH_6]}; + + // If the smfConfig bit in scratch reg6 does not match the SMF_ENABLED + // setting on the system, then the SBE is in disagreement with the system on + // whether SMF mode should be enabled. We need to force SBE update here so + // that the XSCOM BAR on the slave proc is set correctly before + // we try to perform XSCOM operations in istep10. + if(l_scratch6.smfConfig != SECUREBOOT::SMF::isSmfEnabled()) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "SBE and SYS disagree on the SMF setting; SBE thinks it " + "should be %s, but it should actually be %s;" + "requesting SBE update.", + l_scratch6.smfConfig ? "enabled" : "disabled", + SECUREBOOT::SMF::isSmfEnabled() ? "enabled" : "disabled"); + l_updateNeeded = true; + } + if(l_updateNeeded) { do diff --git a/src/usr/isteps/istep07/call_mss_eff_config.C b/src/usr/isteps/istep07/call_mss_eff_config.C index 3f9b52371..e5ac21875 100644 --- a/src/usr/isteps/istep07/call_mss_eff_config.C +++ b/src/usr/isteps/istep07/call_mss_eff_config.C @@ -30,46 +30,59 @@ /******************************************************************************/ // Includes /******************************************************************************/ + +// STD #include <stdint.h> +#include <stdlib.h> #include <map> +// Generated +#include <attributeenums.H> +#include <config.h> + +// Errors and Tracing Support #include <trace/interface.H> #include <initservice/taskargs.H> +#include <initservice/isteps_trace.H> #include <errl/errlentry.H> - -#include <isteps/hwpisteperror.H> #include <errl/errludtarget.H> +#include <isteps/hwpisteperror.H> +#include <hbotcompid.H> -#include <initservice/isteps_trace.H> - +// Pnor Support #include <pnor/pnorif.H> -// targeting support +// Targeting Support #include <targeting/common/commontargeting.H> #include <targeting/common/utilFilter.H> -#include <config.h> +// Fapi Support #include <fapi2.H> #include <fapi2/plat_hwp_invoker.H> -// HWP +// Nimbus Specific HWPs #include <p9_mss_eff_config.H> #include <p9_mss_eff_config_thermal.H> #include <p9_mss_eff_grouping.H> + +// Cumulus Specific HWPs #include <p9c_mss_eff_config.H> #include <p9c_mss_eff_mb_interleave.H> #include <p9c_mss_eff_config_thermal.H> +// Axone Specific HWPs #ifdef CONFIG_AXONE #include <p9a_mss_eff_config.H> -#include <p9a_mss_eff_config_thermal.H> +#include <exp_mss_eff_config_thermal.H> #endif -#include <hbotcompid.H> +// SMF Support +#include <secureboot/smf.H> +// NVDIMM Support #include <nvram/nvram_interface.H> -#include <secureboot/smf.H> -#include <stdlib.h> + + namespace ISTEP_07 { @@ -167,13 +180,13 @@ void* call_mss_eff_config( void *io_pArgs ) { IStepError l_StepError; errlHndl_t l_err = nullptr; -#ifdef CONFIG_SECUREBOOT +#if (defined CONFIG_SECUREBOOT && ! defined CONFIG_AXONE) auto memdLoaded = false; #endif do { - #ifdef CONFIG_SECUREBOOT + #if (defined CONFIG_SECUREBOOT && ! defined CONFIG_AXONE) // MEMD used by p9_mss_eff_config HWP l_err = loadSecureSection(PNOR::MEMD); if (l_err) @@ -194,14 +207,11 @@ void* call_mss_eff_config( void *io_pArgs ) TARGETING::ATTR_MODEL_type l_procModel = TARGETING::targetService().getProcessorModel(); - TARGETING::Target* l_sys = nullptr; - targetService().getTopLevelTarget(l_sys); - assert( l_sys != nullptr ); - TARGETING::TargetHandleList l_membufTargetList; TARGETING::TargetHandleList l_mcsTargetList; TARGETING::TargetHandleList l_memportTargetList; - std::vector<fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>> l_fapi_memport_targets; + std::vector<fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>> l_fapi_ocmb_targets; + if(l_procModel == TARGETING::MODEL_CUMULUS) { @@ -310,11 +320,10 @@ void* call_mss_eff_config( void *io_pArgs ) const fapi2::Target <fapi2::TARGET_TYPE_MEM_PORT> l_fapi_memport_target (l_memport_target); - // TODO RTC: 207850 Remove workaround setting EFF_DIMM_SIZE when MSS has code that sets this - uint32_t l_defaultMemSize[] = {0x8, 0x0}; - FAPI_ATTR_SET(fapi2::ATTR_MEM_EFF_DIMM_SIZE, l_fapi_memport_target, l_defaultMemSize); + const auto l_fapi2_ocmb_target = + l_fapi_memport_target.getParent<fapi2::TARGET_TYPE_OCMB_CHIP>(); - l_fapi_memport_targets.push_back(l_fapi_memport_target); + l_fapi_ocmb_targets.push_back(l_fapi2_ocmb_target); TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call p9a_mss_eff_config HWP on MEM_PORT HUID %.8X", @@ -475,18 +484,18 @@ void* call_mss_eff_config( void *io_pArgs ) #ifdef CONFIG_AXONE else if(l_procModel == TARGETING::MODEL_AXONE) { - if(l_fapi_memport_targets.size() > 0) + if(l_fapi_ocmb_targets.size() > 0) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "call p9a_mss_eff_config_thermal HWP on %d MEM_PORT targets", - l_fapi_memport_targets.size()); + "call exp_mss_eff_config_thermal HWP on %d OCMB_CHIP targets", + l_fapi_ocmb_targets.size()); - FAPI_INVOKE_HWP(l_err, p9a_mss_eff_config_thermal, l_fapi_memport_targets); + FAPI_INVOKE_HWP(l_err, exp_mss_eff_config_thermal, l_fapi_ocmb_targets); if (l_err) { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X: p9a_mss_eff_config_thermal HWP", + "ERROR 0x%.8X: exp_mss_eff_config_thermal HWP", l_err->reasonCode()); // Ensure istep error created and has same plid as this error @@ -498,13 +507,13 @@ void* call_mss_eff_config( void *io_pArgs ) else { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : p9a_mss_eff_config_thermal HWP"); + "SUCCESS : exp_mss_eff_config_thermal HWP"); } } else { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "No MEM_PORT targets found, skipping p9a_mss_eff_config_thermal HWP"); + "No OCMB_CHIP targets found, skipping exp_mss_eff_config_thermal HWP"); } } #endif @@ -564,7 +573,7 @@ void* call_mss_eff_config( void *io_pArgs ) } while (0); - #ifdef CONFIG_SECUREBOOT + #if (defined CONFIG_SECUREBOOT && ! defined CONFIG_AXONE) if(memdLoaded) { l_err = unloadSecureSection(PNOR::MEMD); diff --git a/src/usr/isteps/istep07/call_mss_freq.C b/src/usr/isteps/istep07/call_mss_freq.C index c6e6ac038..5495526ee 100644 --- a/src/usr/isteps/istep07/call_mss_freq.C +++ b/src/usr/isteps/istep07/call_mss_freq.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2019 */ +/* Contributors Listed Below - COPYRIGHT 2015,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -78,9 +78,9 @@ using namespace TARGETING; void* call_mss_freq( void *io_pArgs ) { IStepError l_StepError; - errlHndl_t l_err = NULL; + errlHndl_t l_err = nullptr; - #ifdef CONFIG_SECUREBOOT + #if (defined CONFIG_SECUREBOOT && ! defined CONFIG_AXONE) bool l_isMemdLoaded = false; #endif @@ -88,7 +88,7 @@ void* call_mss_freq( void *io_pArgs ) do { - #ifdef CONFIG_SECUREBOOT + #if (defined CONFIG_SECUREBOOT && ! defined CONFIG_AXONE) // Load MEMD so that vpd_supported_freqs can use it. l_err = loadSecureSection(PNOR::MEMD); if (l_err) @@ -197,30 +197,30 @@ void* call_mss_freq( void *io_pArgs ) #ifdef CONFIG_AXONE else if(l_procModel == TARGETING::MODEL_AXONE) { - TARGETING::TargetHandleList l_memportTargetList; - getAllChiplets(l_memportTargetList, TYPE_MEM_PORT); + TARGETING::TargetHandleList l_procTargList; + getAllChips(l_procTargList, TYPE_PROC); - for (const auto & l_memport_target : l_memportTargetList) + for (const auto & l_proc_target : l_procTargList) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "p9a_mss_freq HWP target HUID %.8x", - TARGETING::get_huid(l_memport_target)); + TARGETING::get_huid(l_proc_target)); // call the HWP with each target ( if parallel, spin off a task ) - fapi2::Target <fapi2::TARGET_TYPE_MEM_PORT> l_fapi_memport_target - (l_memport_target); + fapi2::Target <fapi2::TARGET_TYPE_PROC_CHIP> l_fapi_proc_target + (l_proc_target); - FAPI_INVOKE_HWP(l_err, p9a_mss_freq, l_fapi_memport_target); + FAPI_INVOKE_HWP(l_err, p9a_mss_freq, l_fapi_proc_target); // process return code. if ( l_err ) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "ERROR 0x%.8X: p9a_mss_freq HWP on target HUID %.8x", - l_err->reasonCode(), TARGETING::get_huid(l_memport_target) ); + l_err->reasonCode(), TARGETING::get_huid(l_proc_target) ); // capture the target data in the elog - ErrlUserDetailsTarget(l_memport_target).addToLog( l_err ); + ErrlUserDetailsTarget(l_proc_target).addToLog( l_err ); // Create IStep error log and cross reference to error that occurred l_StepError.addErrorDetails( l_err ); @@ -248,13 +248,25 @@ void* call_mss_freq( void *io_pArgs ) // allow it to change here TARGETING::Target * l_sys = nullptr; TARGETING::targetService().getTopLevelTarget( l_sys ); - // TODO RTC: 207596 Get nest boot freq for OMIs - #ifndef CONFIG_AXONE_BRING_UP - uint32_t l_originalNest = Util::getBootNestFreq(); - #endif + + TARGETING::ATTR_FREQ_PB_MHZ_type l_originalNestFreq = Util::getBootNestFreq(); + + // Omi Freq is only used in P9a and beyond, to limit #ifdef + // craziness below just leave it at 0 so it never changes + TARGETING::ATTR_FREQ_OMI_MHZ_type l_originalOmiFreq = 0; +#ifdef CONFIG_AXONE + TARGETING::ATTR_OMI_PLL_VCO_type l_originalOmiVco = 0; // unused but needed for func call + l_err = fapi2::platAttrSvc::getOmiFreqAndVco(l_originalOmiFreq, l_originalOmiVco); + if(l_err) + { + l_StepError.addErrorDetails( l_err ); + errlCommit( l_err, ISTEP_COMP_ID ); + break; + } +#endif // Read MC_SYNC_MODE from SBE itself and set the attribute - uint8_t l_bootSyncMode = 0; + TARGETING::ATTR_MC_SYNC_MODE_type l_bootSyncMode = 0; l_err = SBE::getBootMcSyncMode( l_bootSyncMode ); if( l_err ) { @@ -318,23 +330,23 @@ void* call_mss_freq( void *io_pArgs ) #ifdef CONFIG_AXONE else if(l_procModel == TARGETING::MODEL_AXONE) { - TARGETING::TargetHandleList l_mcTargetList; - getAllChiplets(l_mcTargetList, TYPE_MC); - for (const auto & l_mc_target : l_mcTargetList) + TARGETING::TargetHandleList l_procTargetList; + getAllChips(l_procTargetList, TYPE_PROC); + for (const auto & l_proc_target : l_procTargetList) { // call the HWP with each target ( if parallel, spin off a task ) - fapi2::Target <fapi2::TARGET_TYPE_MC> l_fapi_mc_target(l_mc_target); + fapi2::Target <fapi2::TARGET_TYPE_PROC_CHIP> l_fapi_proc_target(l_proc_target); TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "START : running p9a_mss_freq_system HWP on target 0x%.08X", TARGETING::get_huid(l_mc_target));; + "START : running p9a_mss_freq_system HWP on target 0x%.08X", TARGETING::get_huid(l_proc_target));; - FAPI_INVOKE_HWP(l_err, p9a_mss_freq_system, l_fapi_mc_target); + FAPI_INVOKE_HWP(l_err, p9a_mss_freq_system, l_proc_target); // process return code. if ( l_err ) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR: p9a_mss_freq_system HWP while running on mc target 0x%.08X", TARGETING::get_huid(l_mc_target));; + "ERROR: p9a_mss_freq_system HWP while running on mc target 0x%.08X", TARGETING::get_huid(l_proc_target));; - ERRORLOG::ErrlUserDetailsTarget(l_mc_target).addToLog(l_err); + ERRORLOG::ErrlUserDetailsTarget(l_proc_target).addToLog(l_err); // Create IStep error log and cross reference to error that occurred l_StepError.addErrorDetails( l_err ); @@ -345,7 +357,7 @@ void* call_mss_freq( void *io_pArgs ) else { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : p9a_mss_freq_system HWP on target 0x%.08X", TARGETING::get_huid(l_mc_target));; + "SUCCESS : p9a_mss_freq_system HWP on target 0x%.08X", TARGETING::get_huid(l_proc_target));; } } } @@ -357,34 +369,55 @@ void* call_mss_freq( void *io_pArgs ) break; } - // TODO RTC: 207596 Get nest boot freq for OMIs - #ifndef CONFIG_AXONE_BRING_UP // Get latest MC_SYNC_MODE and FREQ_PB_MHZ - uint8_t l_mcSyncMode = l_masterProc->getAttr<TARGETING::ATTR_MC_SYNC_MODE>(); - uint32_t l_newNest = l_sys->getAttr<TARGETING::ATTR_FREQ_PB_MHZ>(); + TARGETING::ATTR_MC_SYNC_MODE_type l_mcSyncMode = l_masterProc->getAttr<TARGETING::ATTR_MC_SYNC_MODE>(); + TARGETING::ATTR_FREQ_OMI_MHZ_type l_newOmiFreq = 0; + TARGETING::ATTR_FREQ_PB_MHZ_type l_newNestFreq = l_sys->getAttr<TARGETING::ATTR_FREQ_PB_MHZ>(); +#ifdef CONFIG_AXONE + TARGETING::ATTR_OMI_PLL_VCO_type l_newOmiVco = 0; // unused but needed for func call + l_err = fapi2::platAttrSvc::getOmiFreqAndVco(l_newOmiFreq, l_newOmiVco); + if(l_err) + { + l_StepError.addErrorDetails( l_err ); + errlCommit( l_err, ISTEP_COMP_ID ); + break; + } +#endif //Trigger sbe update if the nest frequency changed. - if( (l_newNest != l_originalNest) || (l_mcSyncMode != l_bootSyncMode) ) + if( (l_newNestFreq != l_originalNestFreq) + || (l_mcSyncMode != l_bootSyncMode) + || (l_newOmiFreq != l_originalOmiFreq) + ) { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "The nest frequency or sync mode changed!" " Original Nest: %d New Nest: %d" - " Original syncMode: %d New syncMode: %d", - l_originalNest, l_newNest, l_bootSyncMode, l_mcSyncMode ); + " Original syncMode: %d New syncMode: %d" + " Original Omi : %d New Omi : %d" + , l_originalNestFreq, l_newNestFreq, l_bootSyncMode, l_mcSyncMode + , l_originalOmiFreq, l_newOmiFreq + ); if(l_sys->getAttr<TARGETING::ATTR_IS_MPIPL_HB>() == true) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "Error: SBE update detected in MPIPL"); + // It is highly unlikely nest frequency will change + // in Axone systems but OMI freq might. Its is impossible + // for OMI freq to change in Nimbus/Cumulus systems. So + // we will display Nest freq in error for Nimbus/Cumulus and + // display OMI freq for Axone. + /*@ * @errortype * @moduleid MOD_SBE_PERFORM_UPDATE_CHECK * @reasoncode RC_SBE_UPDATE_IN_MPIPL * @userdata1[0:31] original mc sync mode * @userdata1[32:63] new mc sync mode - * @userdata2[0:31] original nest frequency - * @userdata2[32:63] new nest frequency + * @userdata2[0:31] original (nest p9 | omi p9a+) frequency + * @userdata2[32:63] new (nest p9 | omi p9a+) frequency * @devdesc SBE cannot be reset during MPIPL * @custdesc Illegal action during boot */ @@ -394,8 +427,16 @@ void* call_mss_freq( void *io_pArgs ) TWO_UINT32_TO_UINT64( TO_UINT32(l_bootSyncMode), TO_UINT32(l_mcSyncMode)), +#ifndef CONFIG_AXONE + TWO_UINT32_TO_UINT64( + l_originalNestFreq, + l_newNestFreq)); +#else TWO_UINT32_TO_UINT64( - l_originalNest, l_newNest)); + l_originalOmiFreq, + l_newOmiFreq)); +#endif + l_err->collectTrace("ISTEPS_TRACE"); l_StepError.addErrorDetails( l_err ); errlCommit( l_err, ISTEP_COMP_ID ); @@ -403,8 +444,9 @@ void* call_mss_freq( void *io_pArgs ) else { TARGETING::setFrequencyAttributes(l_sys, - l_newNest); + l_newNestFreq); l_err = SBE::updateProcessorSbeSeeproms(); + if( l_err ) { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, @@ -419,11 +461,10 @@ void* call_mss_freq( void *io_pArgs ) } } } - #endif } while(0); - #ifdef CONFIG_SECUREBOOT + #if (defined CONFIG_SECUREBOOT && ! defined CONFIG_AXONE) if(l_isMemdLoaded) { // Should not have any uncommitted errors at this point. diff --git a/src/usr/isteps/istep07/host_mss_attr_cleanup.C b/src/usr/isteps/istep07/host_mss_attr_cleanup.C index ed1cbc25a..4456018ae 100644 --- a/src/usr/isteps/istep07/host_mss_attr_cleanup.C +++ b/src/usr/isteps/istep07/host_mss_attr_cleanup.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -56,7 +56,6 @@ #include <fapi2/target.H> #include <fapi2/plat_hwp_invoker.H> -#include <config.h> // HWP #include <p9c_mss_attr_cleanup.H> @@ -75,7 +74,6 @@ using namespace TARGETING; void* host_mss_attr_cleanup( void *io_pArgs ) { IStepError l_StepError; - errlHndl_t l_err = NULL; TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "host_mss_attr_cleanup entry"); // errlHndl_t l_err = NULL; @@ -98,7 +96,9 @@ void* host_mss_attr_cleanup( void *io_pArgs ) l_pTopLevel->setAttr<TARGETING::ATTR_MRW_HW_MIRRORING_ENABLE> (fapi2::ENUM_ATTR_MRW_HW_MIRRORING_ENABLE_FALSE); } - + // TODO RTC 198112 Memory Reconfig Loop for Axone + #ifndef CONFIG_AXONE + errlHndl_t l_err = nullptr; TargetHandleList l_funcDimmList; // Get all the functional Dimms TARGETING::getAllLogicalCards(l_funcDimmList, TYPE_DIMM, true); @@ -123,6 +123,7 @@ void* host_mss_attr_cleanup( void *io_pArgs ) } } + #endif TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "host_mss_attr_cleanup exit" ); diff --git a/src/usr/isteps/istep07/makefile b/src/usr/isteps/istep07/makefile index c9dfba28a..3befa6684 100644 --- a/src/usr/isteps/istep07/makefile +++ b/src/usr/isteps/istep07/makefile @@ -31,6 +31,7 @@ HWP_PATH_P9 += ${ROOTPATH}/src/import/chips/p9/procedures/hwp/memory HWP_PATH_CEN += ${ROOTPATH}/src/import/chips/centaur/procedures/hwp/memory # Axone HWP_PATH_P9A += ${ROOTPATH}/src/import/chips/p9a/procedures/hwp/memory +HWP_PATH_P9A += ${ROOTPATH}/src/import/chips/ocmb/common/procedures/hwp/pmic # Explorer HWP_PATH_EXP += ${ROOTPATH}/src/import/chips/ocmb/explorer/procedures/hwp/memory @@ -71,14 +72,19 @@ EXTRAINCDIR += ${HWP_PATH_CEN}/lib/ EXTRAINCDIR += ${HWP_PATH_CEN}/lib/shared/ EXTRAINCDIR += ${HWP_PATH_CEN}/lib/utils/ EXTRAINCDIR += ${HWP_PATH_EXP}/lib/eff_config/ -EXTRAINCDIR += ${ROOTPATH}/obj/genfiles/chips/ocmb/explorer/procedures/hwp/memory/ +EXTRAINCDIR += ${ROOTPATH}/obj/genfiles/chips/ocmb/explorer/procedures/hwp/memory/lib/ EXTRAINCDIR += ${ROOTPATH}/obj/genfiles/generic/memory/lib/ EXTRAINCDIR += ${EXP_COMMON_PATH}/include/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/common/procedures/hwp/pmic/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/common/include +EXTRAINCDIR += ${ROOTPATH}/obj/genfiles/chips/ocmb/common/procedures/hwp/pmic/ +EXTRAINCDIR += ${ROOTPATH}/obj/genfiles/chips/ocmb/common/procedures/hwp/pmic/lib VPATH += ${HWP_PATH} ${HWP_PATH_P9}/lib/spd VPATH += $(PROCEDURES_PATH)/hwp/nest ${ROOTPATH}/src/usr/fapi2 VPATH += ${PROCEDURES_PATH}/hwp/perv VPATH += ${HWP_PATH_P9}/lib ${HWP_PATH_P9}/lib/utils ${HWP_PATH_P9}/lib/eff_config +VPATH += ${HWP_PATH_P9A}/lib/eff_config VPATH += ${HWP_PATH_P9}/lib/freq ${HWP_PATH_P9}/lib/dimm VPATH += ${ROOTPATH}/src/usr/sbe @@ -108,12 +114,13 @@ include $(HWP_PATH_CEN)/p9c_mss_bulk_pwr_throttles.mk include $(HWP_PATH_CEN)/p9c_mss_eff_mb_interleave.mk -# Axone only objects +# Axone only objects OBJS += $(if $(CONFIG_AXONE),p9a_mss_volt.o,) OBJS += $(if $(CONFIG_AXONE),p9a_mss_freq.o,) OBJS += $(if $(CONFIG_AXONE),p9a_mss_freq_system.o,) OBJS += $(if $(CONFIG_AXONE),p9a_mss_eff_config.o,) -OBJS += $(if $(CONFIG_AXONE),p9a_mss_eff_config_thermal.o,) +OBJS += $(if $(CONFIG_AXONE),exp_mss_eff_config_thermal.o,) +OBJS += $(if $(CONFIG_AXONE),pmic_efd_processing.o,) #host_mss_attr_cleanup : MSS ATTR Cleanup include $(HWP_PATH_CEN)/p9c_mss_attr_cleanup.mk diff --git a/src/usr/isteps/istep08/call_host_set_voltages.C b/src/usr/isteps/istep08/call_host_set_voltages.C index 11c37a50d..fe37ef21b 100644 --- a/src/usr/isteps/istep08/call_host_set_voltages.C +++ b/src/usr/isteps/istep08/call_host_set_voltages.C @@ -46,7 +46,10 @@ #include <p9_setup_evid.H> #include <nest/nestHwpHelperFuncs.H> // fapiHWPCallWrapperForChip #include <hbToHwsvVoltageMsg.H> // platform_set_nest_voltages - +#ifdef CONFIG_AXONE +#include <chipids.H> // for EXPLORER ID +#include <pmic_enable.H> +#endif // Init Service support #include <initservice/initserviceif.H> // INITSERVICE::spBaseServicesEnabled @@ -69,9 +72,6 @@ void* call_host_set_voltages(void *io_pArgs) do { - // Skip p9_setup_evid on Axone, no targets exist - #ifndef CONFIG_AXONE_BRING_UP - TargetHandleList l_procList; // Get the system's procs getAllChips( l_procList, @@ -115,7 +115,6 @@ void* call_host_set_voltages(void *io_pArgs) { break; } - #endif // If no error occurred and FSP is present, // send voltage information to HWSV @@ -156,8 +155,43 @@ void* call_host_set_voltages(void *io_pArgs) fapiHWPCallWrapperHandler(P9_IO_XBUS_IMAGE_BUILD, l_stepError, HWPF_COMP_ID, TYPE_PROC); } - }while( 0 ); +#ifdef CONFIG_AXONE + // Create a vector of TARGETING::Target pointers + TargetHandleList l_chipList; + + // Get a list of all of the functioning ocmb chips + TARGETING::getAllChips(l_chipList, TARGETING::TYPE_OCMB_CHIP, true); + + for (const auto & l_ocmb: l_chipList) + { + // PMICs are not present on Gemini, so skip this enable call + // check EXPLORER first as this is most likely the configuration + uint32_t chipId = l_ocmb->getAttr< TARGETING::ATTR_CHIP_ID>(); + if (chipId == POWER_CHIPID::EXPLORER_16) + { + TRACFCOMP( g_trac_isteps_trace, "call_host_set_voltages: " + "calling pmic_enable on OCMB 0x%.8X", get_huid(l_ocmb) ); + + fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>l_fapi2_target(l_ocmb); + + // Invoke procedure + FAPI_INVOKE_HWP(l_err, pmic_enable, l_fapi2_target); + } + + if (l_err) + { + TRACFCOMP(g_trac_isteps_trace, + "Error from pmic_enable for 0x%.8X target", + TARGETING::get_huid(l_ocmb)); + + // Capture error and continue to next OCMB + captureError(l_err, l_stepError, HWPF_COMP_ID, l_ocmb); + } + } +#endif + + }while( 0 ); TRACFCOMP(g_trac_isteps_trace, EXIT_MRK"call_host_set_voltages exit"); diff --git a/src/usr/isteps/istep08/call_proc_attr_update.C b/src/usr/isteps/istep08/call_proc_attr_update.C index 0b73652b5..d287c09ef 100644 --- a/src/usr/isteps/istep08/call_proc_attr_update.C +++ b/src/usr/isteps/istep08/call_proc_attr_update.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -57,7 +57,6 @@ #include <devicefw/userif.H> #include <vpd/mvpdenums.H> -#include <config.h> #include <p9_attr_update.H> diff --git a/src/usr/isteps/istep08/call_proc_xbus_scominit.C b/src/usr/isteps/istep08/call_proc_xbus_scominit.C index b446f7b06..970f1b608 100644 --- a/src/usr/isteps/istep08/call_proc_xbus_scominit.C +++ b/src/usr/isteps/istep08/call_proc_xbus_scominit.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -59,7 +59,6 @@ #include <devicefw/userif.H> #include <vpd/mvpdenums.H> -#include <config.h> #include <p9_io_xbus_scominit.H> namespace ISTEP_08 diff --git a/src/usr/isteps/istep08/makefile b/src/usr/isteps/istep08/makefile index 225e07735..5b1da4f21 100644 --- a/src/usr/isteps/istep08/makefile +++ b/src/usr/isteps/istep08/makefile @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2015,2018 +# Contributors Listed Below - COPYRIGHT 2015,2019 # [+] International Business Machines Corp. # # @@ -24,6 +24,10 @@ # IBM_PROLOG_END_TAG ROOTPATH = ../../../.. PROCEDURES_PATH = ${ROOTPATH}/src/import/chips/p9/procedures + +# OCMB path +COMMON_PATH_OCMB += ${ROOTPATH}/src/import/chips/ocmb/common + MODULE = istep08 EXTRAINCDIR += ${PROCEDURES_PATH}/hwp/pm/ @@ -38,10 +42,18 @@ EXTRAINCDIR += ${ROOTPATH}/src/include/usr/fapi2/ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/common/include/ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/utils/ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/utils/imageProcs/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/utils/ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/utils/imageProcs/ EXTRAINCDIR += ${ROOTPATH}/src/usr/isteps/ EXTRAINCDIR += ${ROOTPATH}/src/usr/sbeio/ EXTRAINCDIR += ${PROCEDURES_PATH}/hwp/pm/include/registers +EXTRAINCDIR += ${COMMON_PATH_OCMB}/procedures/hwp/pmic/ +EXTRAINCDIR += ${COMMON_PATH_OCMB}/procedures/hwp/pmic/lib/utils/ +EXTRAINCDIR += ${COMMON_PATH_OCMB}/include/ +EXTRAINCDIR += ${ROOTPATH}/src/import/ +EXTRAINCDIR += ${ROOTPATH}/obj/genfiles/chips/ocmb/common/procedures/hwp/pmic/lib/ +EXTRAINCDIR += ${ROOTPATH}/obj/genfiles/generic/memory/lib/ + OBJS += call_host_slave_sbe_config.o OBJS += call_host_setup_sbe.o @@ -61,6 +73,10 @@ VPATH += ${PROCEDURES_PATH}/hwp/io/ ${PROCEDURES_PATH}/hwp/initfiles/ VPATH += ${PROCEDURES_PATH}/hwp/sbe/ VPATH += ${PROCEDURES_PATH}/hwp/pm/ VPATH += ${PROCEDURES_PATH}/hwp/lib +VPATH += ${COMMON_PATH_OCMB}/pmic/ +VPATH += ${COMMON_PATH_OCMB}/procedures/hwp/pmic/ +VPATH += ${COMMON_PATH_OCMB}/procedures/hwp/pmic/lib/utils/ +VPATH += ${COMMON_PATH_OCMB}/include/ include ${ROOTPATH}/procedure.rules.mk @@ -110,4 +126,9 @@ MODULE = istep08 # Take another look at PM lib include $(PROCEDURES_PATH)/hwp/pm/p9_pm_utils.mk +# Axone only objects +OBJS += $(if $(CONFIG_AXONE),pmic_common_utils.o,) +OBJS += $(if $(CONFIG_AXONE),pmic_enable_utils.o,) +OBJS += $(if $(CONFIG_AXONE),pmic_enable.o,) + include ${ROOTPATH}/config.mk diff --git a/src/usr/isteps/istep10/call_host_rng_bist.C b/src/usr/isteps/istep10/call_host_rng_bist.C index 68d243547..70b82a274 100644 --- a/src/usr/isteps/istep10/call_host_rng_bist.C +++ b/src/usr/isteps/istep10/call_host_rng_bist.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -55,7 +55,6 @@ #include <devicefw/userif.H> #include <vpd/mvpdenums.H> -#include <config.h> #include <fapi2/plat_hwp_invoker.H> #include <p9_rng_init_phase1.H> @@ -121,7 +120,7 @@ void* call_host_rng_bist( void *io_pArgs ) { l_err->addHwCallout( l_nxTarget, HWAS::SRCI_PRIORITY_HIGH, - HWAS::DECONFIG, + HWAS::DELAYED_DECONFIG, HWAS::GARD_NULL ); } } diff --git a/src/usr/isteps/istep10/call_host_slave_sbe_update.C b/src/usr/isteps/istep10/call_host_slave_sbe_update.C index 6e230fc38..d008e8cbd 100644 --- a/src/usr/isteps/istep10/call_host_slave_sbe_update.C +++ b/src/usr/isteps/istep10/call_host_slave_sbe_update.C @@ -249,6 +249,7 @@ void* call_host_slave_sbe_update (void *io_pArgs) { errlHndl_t l_errl = NULL; IStepError l_StepError; + bool l_testAltMaster = true; TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_host_slave_sbe_update entry" ); @@ -275,7 +276,6 @@ void* call_host_slave_sbe_update (void *io_pArgs) errlCommit( l_errl, HWPF_COMP_ID ); } - #ifndef CONFIG_AXONE_BRING_UP // Call to check state of Processor SBE SEEPROMs and // make any necessary updates l_errl = SBE::updateProcessorSbeSeeproms( @@ -290,8 +290,6 @@ void* call_host_slave_sbe_update (void *io_pArgs) break; } - #endif - // Run LPC Init on Alt Master Procs // Get list of all processors TARGETING::TargetHandleList l_procList; @@ -325,6 +323,7 @@ void* call_host_slave_sbe_update (void *io_pArgs) l_errl->removeDeconfigure(); // Commit error errlCommit( l_errl, HWPF_COMP_ID ); + l_testAltMaster = false; } else { @@ -337,14 +336,17 @@ void* call_host_slave_sbe_update (void *io_pArgs) // Call to Validate any Alternative Master's connection to PNOR // Any error returned should not fail istep - l_errl = PNOR::validateAltMaster(); - if (l_errl) + if (l_testAltMaster == true) { - //Remove any deconfigure information, we only need the PNOR Part callout and do not want - // to deconfigure the entire proc because of a PNOR part problem - l_errl->removeDeconfigure(); - // Commit error - errlCommit( l_errl, HWPF_COMP_ID ); + l_errl = PNOR::validateAltMaster(); + if (l_errl) + { + //Remove any deconfigure information, we only need the PNOR Part callout and do not want + // to deconfigure the entire proc because of a PNOR part problem + l_errl->removeDeconfigure(); + // Commit error + errlCommit( l_errl, HWPF_COMP_ID ); + } } // Set SEEPROM_VERSIONS_MATCH attributes for each processor diff --git a/src/usr/isteps/istep10/call_host_update_redundant_tpm.C b/src/usr/isteps/istep10/call_host_update_redundant_tpm.C index 878b1b1e3..4f872f995 100644 --- a/src/usr/isteps/istep10/call_host_update_redundant_tpm.C +++ b/src/usr/isteps/istep10/call_host_update_redundant_tpm.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -35,11 +35,11 @@ #include <errl/errludtarget.H> #include <attributetraits.H> -#include <config.h> #include <util/align.H> #include <util/algorithm.H> #include <istepHelperFuncs.H> #include <secureboot/trustedbootif.H> +#include <secureboot/phys_presence_if.H> namespace ISTEP_10 { @@ -50,6 +50,7 @@ void* call_host_update_redundant_tpm (void *io_pArgs) ENTER_MRK"call_host_update_redundant_tpm"); ISTEP_ERROR::IStepError l_istepError; + #ifdef CONFIG_TPMDD TARGETING::Target* l_backupTpm = nullptr; @@ -67,6 +68,26 @@ void* call_host_update_redundant_tpm (void *io_pArgs) } while(0); #endif +#ifdef CONFIG_PHYS_PRES_PWR_BUTTON + // Check to see if a Physical Presence Window should be opened, + // and if so, open it. This could result in the system being shutdown + // to allow the system administrator to assert physical presence + errlHndl_t l_err = nullptr; + l_err = SECUREBOOT::handlePhysPresenceWindow(); + if (l_err) + { + // @TODO RTC 210301 - Handle Error Log Correctly, but for now + // just delete it + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "call_host_update_redundant_tpm: Error back from " + "SECUREBOOT::handlePhysPresence: rc=0x%X, plid=0x%X. " + "Deleting error for now", + ERRL_GETRC_SAFE(l_err), ERRL_GETPLID_SAFE(l_err)); + delete l_err; + l_err = nullptr; + } +#endif + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, EXIT_MRK"call_host_update_redundant_tpm"); diff --git a/src/usr/isteps/istep10/call_proc_abus_scominit.C b/src/usr/isteps/istep10/call_proc_abus_scominit.C index 745fabae3..cefb9f6d0 100644 --- a/src/usr/isteps/istep10/call_proc_abus_scominit.C +++ b/src/usr/isteps/istep10/call_proc_abus_scominit.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -58,7 +58,6 @@ #include <devicefw/userif.H> #include <vpd/mvpdenums.H> -#include <config.h> namespace ISTEP_10 diff --git a/src/usr/isteps/istep10/call_proc_build_smp.C b/src/usr/isteps/istep10/call_proc_build_smp.C index b3ce48516..599e6f98e 100644 --- a/src/usr/isteps/istep10/call_proc_build_smp.C +++ b/src/usr/isteps/istep10/call_proc_build_smp.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ diff --git a/src/usr/isteps/istep10/call_proc_cen_ref_clk_enable.C b/src/usr/isteps/istep10/call_proc_cen_ref_clk_enable.C index 67a11b775..81478303a 100644 --- a/src/usr/isteps/istep10/call_proc_cen_ref_clk_enable.C +++ b/src/usr/isteps/istep10/call_proc_cen_ref_clk_enable.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2019 */ +/* Contributors Listed Below - COPYRIGHT 2015,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -80,7 +80,6 @@ #include <errl/errludtarget.H> #include <attributetraits.H> -#include <config.h> #include <util/align.H> #include <util/algorithm.H> @@ -1064,9 +1063,25 @@ void* call_proc_cen_ref_clk_enable(void *io_pArgs ) "for 0x%.08X", TARGETING::get_huid(l_ocmb)); fapi2::Target <fapi2::TARGET_TYPE_OCMB_CHIP> l_fapi_ocmb_target(l_ocmb); - FAPI_INVOKE_HWP(l_errl, - exp_check_for_ready, - l_fapi_ocmb_target); + + // TODO CQ:SW482291 Remove this retry workaround when ocmb check_for_ready timeout issue is resolved + for(uint8_t i = 0; i < 10; i++) + { + FAPI_INVOKE_HWP(l_errl, + exp_check_for_ready, + l_fapi_ocmb_target); + + // Preserve the error log if this is the last loop. + if(l_errl == NULL || i == 9) + { + break; + } + else + { + delete l_errl; + l_errl = NULL; + } + } if (l_errl) { @@ -1086,8 +1101,41 @@ void* call_proc_cen_ref_clk_enable(void *io_pArgs ) else { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : exp_check_for_ready" + "SUCCESS : exp_check_for_ready " "completed ok"); + + size_t size = 0; + + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "Read IDEC from OCMB 0x%.8X", + TARGETING::get_huid(l_ocmb)); + + // This write gets translated into a read of the explorer chip + // in the device driver. First, a read of the chip's IDEC + // register occurs then ATTR_EC, ATTR_HDAT_EC, and ATTR_CHIP_ID + // are set with the values found in that register. So, this + // deviceWrite functions more as a setter for an OCMB target's + // attributes. + // Pass 2 as a va_arg to signal the ocmbIDEC function to execute + // phase 2 of it's read process. + const uint64_t Phase2 = 2; + l_errl = DeviceFW::deviceWrite(l_ocmb, + nullptr, + size, + DEVICE_IDEC_ADDRESS(), + Phase2); + if (l_errl) + { + // read of ID/EC failed even though we THOUGHT we were + // present. + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "OCMB 0x%.8X - read IDEC failed (eid 0x%X) - bad", + TARGETING::get_huid(l_ocmb), l_errl->eid()); + + // commit the error but keep going + errlCommit(l_errl, HWAS_COMP_ID); + // l_errl is now nullptr + } } } #endif diff --git a/src/usr/isteps/istep10/call_proc_chiplet_scominit.C b/src/usr/isteps/istep10/call_proc_chiplet_scominit.C index 8e2950163..c0b9f2619 100644 --- a/src/usr/isteps/istep10/call_proc_chiplet_scominit.C +++ b/src/usr/isteps/istep10/call_proc_chiplet_scominit.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -74,6 +74,8 @@ void* call_proc_chiplet_scominit( void *io_pArgs ) TRACFCOMP(g_trac_isteps_trace, ENTER_MRK"call_proc_chiplet_scominit entry" ); + do{ + if (!INITSERVICE::isSMPWrapConfig()) { // Make the FAPI call to p9_chiplet_scominit @@ -108,6 +110,8 @@ void* call_proc_chiplet_scominit( void *io_pArgs ) } } + }while(0); + TRACFCOMP(g_trac_isteps_trace, EXIT_MRK"call_proc_chiplet_scominit exit" ); return l_stepError.getErrorHandle(); diff --git a/src/usr/isteps/istep10/call_proc_enable_osclite.C b/src/usr/isteps/istep10/call_proc_enable_osclite.C index dd3c6147e..ccfa653b6 100644 --- a/src/usr/isteps/istep10/call_proc_enable_osclite.C +++ b/src/usr/isteps/istep10/call_proc_enable_osclite.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -55,7 +55,6 @@ #include <devicefw/userif.H> #include <vpd/mvpdenums.H> -#include <config.h> // -- prototype includes -- // Add any customized routines that you don't want overwritten into diff --git a/src/usr/isteps/istep10/call_proc_npu_scominit.C b/src/usr/isteps/istep10/call_proc_npu_scominit.C index c29be9535..7fd76d010 100644 --- a/src/usr/isteps/istep10/call_proc_npu_scominit.C +++ b/src/usr/isteps/istep10/call_proc_npu_scominit.C @@ -67,7 +67,6 @@ void* call_proc_npu_scominit( void *io_pArgs ) { IStepError l_stepError; - #ifndef CONFIG_AXONE_BRING_UP TRACFCOMP(g_trac_isteps_trace, ENTER_MRK"call_proc_npu_scominit entry"); if (!INITSERVICE::isSMPWrapConfig()) { @@ -76,9 +75,6 @@ void* call_proc_npu_scominit( void *io_pArgs ) HWPF_COMP_ID, TYPE_PROC); } TRACFCOMP(g_trac_isteps_trace, EXIT_MRK"call_proc_npu_scominit exit"); - #else - TRACFCOMP(g_trac_isteps_trace, "Skipping call_proc_npu_scominit in Axone during bringup"); - #endif return l_stepError.getErrorHandle(); } diff --git a/src/usr/isteps/istep10/call_proc_pcie_scominit.C b/src/usr/isteps/istep10/call_proc_pcie_scominit.C index 664a966e9..82bd05f55 100644 --- a/src/usr/isteps/istep10/call_proc_pcie_scominit.C +++ b/src/usr/isteps/istep10/call_proc_pcie_scominit.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -58,7 +58,6 @@ #include <devicefw/userif.H> #include <vpd/mvpdenums.H> -#include <config.h> #include "host_proc_pcie_scominit.H" #include <p9_pcie_scominit.H> diff --git a/src/usr/isteps/istep10/call_proc_scomoverride_chiplets.C b/src/usr/isteps/istep10/call_proc_scomoverride_chiplets.C index 0d4c6d58f..9476672e8 100644 --- a/src/usr/isteps/istep10/call_proc_scomoverride_chiplets.C +++ b/src/usr/isteps/istep10/call_proc_scomoverride_chiplets.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -58,7 +58,6 @@ #include <devicefw/userif.H> #include <vpd/mvpdenums.H> -#include <config.h> #include <p9_scomoverride_chiplets.H> diff --git a/src/usr/isteps/istep10/host_proc_pcie_scominit.C b/src/usr/isteps/istep10/host_proc_pcie_scominit.C index 8895ed405..69a41ab36 100644 --- a/src/usr/isteps/istep10/host_proc_pcie_scominit.C +++ b/src/usr/isteps/istep10/host_proc_pcie_scominit.C @@ -44,7 +44,6 @@ #include <fapi2/target.H> #include <fapi2/plat_hwp_invoker.H> #include <devicefw/userif.H> -#include <config.h> #include "host_proc_pcie_scominit.H" #include <hwas/common/hwas.H> #include <hwas/common/deconfigGard.H> diff --git a/src/usr/isteps/istep10/makefile b/src/usr/isteps/istep10/makefile index ac6233867..2590c4f63 100644 --- a/src/usr/isteps/istep10/makefile +++ b/src/usr/isteps/istep10/makefile @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2015,2019 +# Contributors Listed Below - COPYRIGHT 2015,2020 # [+] International Business Machines Corp. # # @@ -51,6 +51,7 @@ EXTRAINCDIR += ${INITFILES_HWP_PATH} EXTRAINCDIR += ${PERV_HWP_PATH} EXTRAINCDIR += ${OCMB_HWP_PATH} EXTRAINCDIR += ${ROOTPATH}/src/import/ +EXTRAINCDIR += ${ROOTPATH}/obj/genfiles/chips/ocmb/explorer/procedures/hwp/memory/lib/ OBJS += call_proc_build_smp.o diff --git a/src/usr/isteps/istep11/call_host_prd_hwreconfig.C b/src/usr/isteps/istep11/call_host_prd_hwreconfig.C index e3a0a434a..2b32b625e 100644 --- a/src/usr/isteps/istep11/call_host_prd_hwreconfig.C +++ b/src/usr/isteps/istep11/call_host_prd_hwreconfig.C @@ -26,7 +26,6 @@ #include <errl/errlmanager.H> #include <isteps/hwpisteperror.H> #include <pnor/pnorif.H> -#include <config.h> #include <initservice/isteps_trace.H> using namespace ERRORLOG; @@ -40,7 +39,7 @@ void* call_host_prd_hwreconfig (void *io_pArgs) ISTEP_ERROR::IStepError l_StepError; //@TODO-RTC:158411 call p9_enable_reconfig.C -#ifdef CONFIG_SECUREBOOT +#if (defined CONFIG_SECUREBOOT && ! defined CONFIG_AXONE) errlHndl_t l_err = NULL; // Load the MEMD section here as the first part of step11, it // will stay loaded until the end of step14 diff --git a/src/usr/isteps/istep12/call_cen_dmi_scominit.C b/src/usr/isteps/istep12/call_cen_dmi_scominit.C index 8e7a9feef..868f1da2a 100644 --- a/src/usr/isteps/istep12/call_cen_dmi_scominit.C +++ b/src/usr/isteps/istep12/call_cen_dmi_scominit.C @@ -46,10 +46,6 @@ // HWP #include <p9_io_cen_scominit.H> -#ifdef CONFIG_AXONE -#include <p9a_omi_setup_bars.H> -#endif - using namespace ISTEP; using namespace ISTEP_ERROR; using namespace ERRORLOG; @@ -107,50 +103,6 @@ void* call_cen_dmi_scominit (void *io_pArgs) } - #ifdef CONFIG_AXONE - TARGETING::TargetHandleList l_procTargetList; - getAllChips(l_procTargetList, TYPE_PROC); - - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_dmi_scominit: %d procs found", - l_procTargetList.size()); - - for (const auto & l_proc_target : l_procTargetList) - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "p9a_omi_setup_bars HWP target HUID %.8x", - TARGETING::get_huid(l_proc_target)); - - // call the HWP with each target - fapi2::Target <fapi2::TARGET_TYPE_PROC_CHIP> l_fapi_proc_target - (l_proc_target); - - FAPI_INVOKE_HWP(l_err, p9a_omi_setup_bars, l_fapi_proc_target); - - // process return code. - if ( l_err ) - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X: p9a_omi_setup_bars HWP on target HUID %.8x", - l_err->reasonCode(), TARGETING::get_huid(l_proc_target) ); - - // capture the target data in the elog - ErrlUserDetailsTarget(l_proc_target).addToLog( l_err ); - - // Create IStep error log and cross reference to error that occurred - l_StepError.addErrorDetails( l_err ); - - // Commit Error - errlCommit( l_err, ISTEP_COMP_ID ); - } - else - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : p9a_omi_setup_bars HWP"); - } - - } - #endif // CONFIG_AXONE - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_dmi_scominit exit" ); // end task, returning any errorlogs to IStepDisp diff --git a/src/usr/isteps/istep12/call_cen_set_inband_addr.C b/src/usr/isteps/istep12/call_cen_set_inband_addr.C index 196f7bed7..1b1161298 100644 --- a/src/usr/isteps/istep12/call_cen_set_inband_addr.C +++ b/src/usr/isteps/istep12/call_cen_set_inband_addr.C @@ -44,12 +44,15 @@ #include <util/utilmbox_scratch.H> #include <util/misc.H> -//HWP -#include <p9c_set_inband_addr.H> - #ifdef CONFIG_AXONE +// Axone HWPs #include <exp_omi_init.H> #include <p9a_omi_init.H> +#include <p9a_disable_ocmb_i2c.H> +#include <expupd/expupd.H> +#else +// Cumulus HWP +#include <p9c_set_inband_addr.H> #endif //Inband SCOM @@ -60,169 +63,313 @@ using namespace ISTEP_ERROR; using namespace ERRORLOG; using namespace TARGETING; - namespace ISTEP_12 { +void cumulus_call_cen_set_inband_addr(IStepError & io_istepError); +void axone_call_cen_set_inband_addr(IStepError & io_istepError); +void enableInbandScomsOCMB( TARGETING::TargetHandleList i_ocmbTargetList ); +void disableI2cAccessToOcmbs(IStepError & io_istepError); + void* call_cen_set_inband_addr (void *io_pArgs) { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_set_inband_addr entry" ); IStepError l_StepError; - errlHndl_t l_err = NULL; auto l_procModel = TARGETING::targetService().getProcessorModel(); - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_set_inband_addr entry" ); + switch (l_procModel) + { + case TARGETING::MODEL_CUMULUS: + cumulus_call_cen_set_inband_addr(l_StepError); + // @todo RTC 187913 inband centaur scom in P9 + // Re-enable when support available in simics + if ( Util::isSimicsRunning() == false ) + { + //Now enable Inband SCOM for all memory mapped chips. + IBSCOM::enableInbandScoms(); + } + break; + case TARGETING::MODEL_AXONE: + axone_call_cen_set_inband_addr(l_StepError); + + // No need to disable i2c access if and error was encountered setting up the inband addr + if(l_StepError.isNull()) + { + disableI2cAccessToOcmbs(l_StepError); + } + break; + case TARGETING::MODEL_NIMBUS: + break; // do nothing step + default: + assert(0, "call_cen_set_inband_addr: Unsupported model type 0x%04X", + l_procModel); + break; + } + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_set_inband_addr exit" ); + + // end task, returning any errorlogs to IStepDisp + return l_StepError.getErrorHandle(); +} + +#ifndef CONFIG_AXONE +void cumulus_call_cen_set_inband_addr(IStepError & io_istepError) +{ + errlHndl_t l_err = nullptr; + TARGETING::TargetHandleList l_procTargetList; + getAllChips(l_procTargetList, TYPE_PROC); + + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_set_inband_addr: %d proc chips found", + l_procTargetList.size()); - if(l_procModel == TARGETING::MODEL_CUMULUS) + for (const auto & l_proc_target : l_procTargetList) { - TARGETING::TargetHandleList l_procTargetList; - getAllChips(l_procTargetList, TYPE_PROC); + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "p9c_set_inband_addr HWP target HUID %.8x", + TARGETING::get_huid(l_proc_target)); - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_set_inband_addr: %d proc chips found", - l_procTargetList.size()); + // call the HWP with each target + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_fapi_proc_target + (l_proc_target); - for (const auto & l_proc_target : l_procTargetList) - { + FAPI_INVOKE_HWP(l_err, p9c_set_inband_addr, l_fapi_proc_target); + // process return code. + if ( l_err ) + { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "p9c_set_inband_addr HWP target HUID %.8x", - TARGETING::get_huid(l_proc_target)); + "ERROR 0x%.8X: p9c_set_inband_addr HWP on target HUID %.8x", + l_err->reasonCode(), TARGETING::get_huid(l_proc_target) ); - // call the HWP with each target - fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_fapi_proc_target - (l_proc_target); + // capture the target data in the elog + ErrlUserDetailsTarget(l_proc_target).addToLog( l_err ); - FAPI_INVOKE_HWP(l_err, p9c_set_inband_addr, l_fapi_proc_target); + // Create IStep error log and cross reference to error that occurred + io_istepError.addErrorDetails( l_err ); - // process return code. - if ( l_err ) - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X: p9c_set_inband_addr HWP on target HUID %.8x", - l_err->reasonCode(), TARGETING::get_huid(l_proc_target) ); + // Commit Error + errlCommit( l_err, ISTEP_COMP_ID ); - // capture the target data in the elog - ErrlUserDetailsTarget(l_proc_target).addToLog( l_err ); + } + else + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : p9c_set_inband_addr HWP"); + } + } // proc target loop +} - // Create IStep error log and cross reference to error that occurred - l_StepError.addErrorDetails( l_err ); +void axone_call_cen_set_inband_addr(IStepError & io_istepError) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'exp_omi_init/p9a_omi_init' but Axone code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); +} - // Commit Error - errlCommit( l_err, ISTEP_COMP_ID ); +void enableInbandScomsOCMB( TARGETING::TargetHandleList l_ocmbTargetList ) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'enableInbandScomsOCMB' but Axone code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); +} + +void disableI2cAccessToOcmbs(IStepError & io_istepError) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'disableI2cAccessToOcmbs' but Axone code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); +} - } - else - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : p9c_set_inband_addr HWP"); - } - } - } +#else - // @todo RTC 187913 inband centaur scom in P9 - // Re-enable when support available in simics - if ( Util::isSimicsRunning() == false ) - { - //Now enable Inband SCOM for all membuf chips. - IBSCOM::enableInbandScoms(); - } +void cumulus_call_cen_set_inband_addr(IStepError & io_istepError) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'p9c_set_inband_addr' but Cumulus code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); +} -#ifdef CONFIG_AXONE - if(l_procModel == TARGETING::MODEL_AXONE) +void axone_call_cen_set_inband_addr(IStepError & io_istepError) +{ + errlHndl_t l_err = nullptr; + TARGETING::TargetHandleList l_ocmbTargetList; + getAllChips(l_ocmbTargetList, TYPE_OCMB_CHIP); + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "axone_call_cen_set_inband_addr: %d ocmb chips found", + l_ocmbTargetList.size()); + + for (const auto & l_ocmb_target : l_ocmbTargetList) { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "exp_omi_init HWP target HUID %.8x", + TARGETING::get_huid(l_ocmb_target) ); - TARGETING::TargetHandleList l_ocmbTargetList; - getAllChips(l_ocmbTargetList, TYPE_OCMB_CHIP); + // call the HWP with each target + fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> l_fapi_ocmb_target + (l_ocmb_target); - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_set_inband_addr: %d ocmb chips found", - l_ocmbTargetList.size()); + FAPI_INVOKE_HWP(l_err, exp_omi_init , l_fapi_ocmb_target); - for (const auto & l_ocmb_target : l_ocmbTargetList) + // process return code. + if ( l_err ) { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "exp_omi_init HWP target HUID %.8x", - TARGETING::get_huid(l_ocmb_target)); + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, ERR_MRK + "ERROR 0x%.8X: exp_omi_init HWP on target HUID 0x%.8x", + l_err->reasonCode(), TARGETING::get_huid(l_ocmb_target) ); - // call the HWP with each target - fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> l_fapi_ocmb_target - (l_ocmb_target); + // capture the target data in the elog + ErrlUserDetailsTarget(l_ocmb_target).addToLog( l_err ); - FAPI_INVOKE_HWP(l_err, exp_omi_init , l_fapi_ocmb_target); + // Create IStep error log and cross reference to error that occurred + io_istepError.addErrorDetails( l_err ); - // process return code. - if ( l_err ) - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X: exp_omi_init HWP on target HUID 0x%.8x", - l_err->reasonCode(), TARGETING::get_huid(l_ocmb_target) ); + // Commit Error + errlCommit( l_err, ISTEP_COMP_ID ); + } + else + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : exp_omi_init HWP on target HUID 0x%.8x", + TARGETING::get_huid(l_ocmb_target) ); + } + } // ocmb loop - // capture the target data in the elog - ErrlUserDetailsTarget(l_ocmb_target).addToLog( l_err ); + TargetHandleList l_mccTargetList; + getAllChiplets(l_mccTargetList, TYPE_MCC); - // Create IStep error log and cross reference to error that occurred - l_StepError.addErrorDetails( l_err ); + for (const auto & l_mcc_target : l_mccTargetList) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "p9a_omi_init HWP target HUID %.8x", + TARGETING::get_huid(l_mcc_target) ); - // Commit Error - errlCommit( l_err, ISTEP_COMP_ID ); + // call the HWP with each target + fapi2::Target<fapi2::TARGET_TYPE_MCC> l_fapi_mcc_target + (l_mcc_target); - } - else - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : exp_omi_init HWP on target HUID 0x%.8x", - TARGETING::get_huid(l_ocmb_target)); - } + FAPI_INVOKE_HWP(l_err, p9a_omi_init, l_fapi_mcc_target); - } + // process return code. + if ( l_err ) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, ERR_MRK + "ERROR 0x%.8X: p9a_omi_init HWP on target HUID %.8x", + l_err->reasonCode(), TARGETING::get_huid(l_mcc_target) ); - TARGETING::TargetHandleList l_mccTargetList; - getAllChiplets(l_mccTargetList, TYPE_MCC); + // capture the target data in the elog + ErrlUserDetailsTarget(l_mcc_target).addToLog( l_err ); - for (const auto & l_mcc_target : l_mccTargetList) + // Create IStep error log and cross reference to error that occurred + io_istepError.addErrorDetails( l_err ); + + // Commit Error + errlCommit( l_err, ISTEP_COMP_ID ); + } + else { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "p9a_omi_init HWP target HUID %.8x", + "SUCCESS : p9a_omi_init HWP on target HUID 0x%.8x ," + "setting scom settings to use inband for all ocmb children", TARGETING::get_huid(l_mcc_target)); - // call the HWP with each target - fapi2::Target<fapi2::TARGET_TYPE_MCC> l_fapi_mcc_target - (l_mcc_target); + TargetHandleList l_ocmbTargetList; + getChildAffinityTargets(l_ocmbTargetList , l_mcc_target, + CLASS_CHIP, TARGETING::TYPE_OCMB_CHIP); + enableInbandScomsOCMB(l_ocmbTargetList); + } + } // MCC loop + + // Check if any explorer chips require a firmware update and update them + // (skipped on MPIPL) + // We should be checking for updates and perform the updates even if OMI + // initialization failed. It's possible that the OMI failure was due to + // the OCMB having an old image. The update code will automatically + // switch to using i2c if OMI is not enabled. + Target* l_pTopLevel = nullptr; + targetService().getTopLevelTarget( l_pTopLevel ); + assert(l_pTopLevel, "axone_call_cen_set_inband_addr: no TopLevelTarget"); + if (l_pTopLevel->getAttr<TARGETING::ATTR_IS_MPIPL_HB>()) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "skipping expupdUpdateAll due to MPIPL"); + } + else + { + expupd::updateAll(io_istepError); + } +} - FAPI_INVOKE_HWP(l_err, p9a_omi_init, l_fapi_mcc_target); +/** + * @brief Loop over all processors and disable i2c path to ocmb + * After this point no i2c commands will be possible until we + * power the chip off and on. + * @param io_istepError - Istep error that tracks error logs for this step + */ +void disableI2cAccessToOcmbs(IStepError & io_istepError) +{ + errlHndl_t l_err = nullptr; + TARGETING::TargetHandleList l_procTargetList; + getAllChips(l_procTargetList, TARGETING::TYPE_PROC); + // We only want to disable i2c if we are in secure mode + const bool FORCE_DISABLE = false; - // process return code. - if ( l_err ) - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X: p9a_omi_init HWP on target HUID %.8x", - l_err->reasonCode(), TARGETING::get_huid(l_mcc_target) ); + for ( const auto & l_proc : l_procTargetList ) + { + // call the HWP with each proc + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_fapi_proc_target + (l_proc); - // capture the target data in the elog - ErrlUserDetailsTarget(l_mcc_target).addToLog( l_err ); + FAPI_INVOKE_HWP(l_err, p9a_disable_ocmb_i2c, l_fapi_proc_target, FORCE_DISABLE); - // Create IStep error log and cross reference to error that occurred - l_StepError.addErrorDetails( l_err ); + // process return code. + if ( l_err ) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, ERR_MRK + "ERROR 0x%.8X: p9a_disable_ocmb_i2c HWP on target HUID %.8x", + l_err->reasonCode(), TARGETING::get_huid(l_proc) ); - // Commit Error - errlCommit( l_err, ISTEP_COMP_ID ); + // capture the target data in the elog + ErrlUserDetailsTarget(l_proc).addToLog( l_err ); - } - else - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : p9a_omi_init HWP on target HUID 0x%.8x", - TARGETING::get_huid(l_mcc_target)); - } + // Create IStep error log and cross reference to error that occurred + io_istepError.addErrorDetails( l_err ); + // Commit Error + errlCommit( l_err, ISTEP_COMP_ID ); + } + else + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : p9a_disable_ocmb_i2c HWP on target HUID 0x%.8x", + TARGETING::get_huid(l_proc)); } } -#endif // CONFIG_AXONE +} +/** + * @brief Enable Inband Scom for the OCMB targets + * @param i_ocmbTargetList - OCMB targets + */ +void enableInbandScomsOCMB( TARGETING::TargetHandleList i_ocmbTargetList ) +{ + mutex_t* l_mutex = NULL; - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_set_inband_addr exit" ); + for ( const auto & l_ocmb : i_ocmbTargetList ) + { + //don't mess with attributes without the mutex (just to be safe) + l_mutex = l_ocmb->getHbMutexAttr<TARGETING::ATTR_IBSCOM_MUTEX>(); + mutex_lock(l_mutex); - // end task, returning any errorlogs to IStepDisp - return l_StepError.getErrorHandle(); + ScomSwitches l_switches = l_ocmb->getAttr<ATTR_SCOM_SWITCHES>(); + l_switches.useI2cScom = 0; + l_switches.useInbandScom = 1; + // Modify attribute + l_ocmb->setAttr<ATTR_SCOM_SWITCHES>(l_switches); + mutex_unlock(l_mutex); + } } +#endif // CONFIG_AXONE + }; diff --git a/src/usr/isteps/istep12/call_dmi_io_dccal.C b/src/usr/isteps/istep12/call_dmi_io_dccal.C index ca2d11aef..339c8be9c 100644 --- a/src/usr/isteps/istep12/call_dmi_io_dccal.C +++ b/src/usr/isteps/istep12/call_dmi_io_dccal.C @@ -43,113 +43,257 @@ #include <fapi2/plat_hwp_invoker.H> #include <util/utilmbox_scratch.H> -// HWP +// HWP (only bring in model-specific HWP headers to save space) +#ifdef CONFIG_AXONE +#include <p9a_io_omi_dccal.H> +#include <p9a_io_omi_scominit.H> +#else #include <p9_io_dmi_dccal.H> #include <p9_io_cen_dccal.H> +#endif using namespace ISTEP; using namespace ISTEP_ERROR; using namespace ERRORLOG; using namespace TARGETING; +#define POS_0_VECTOR 0x000000FF +#define BITS_PER_BYTE 8 namespace ISTEP_12 { + +// Declare local functions +void cumulus_dccal_setup(IStepError & io_istepError); +void axone_dccal_setup(IStepError & io_istepError); + void* call_dmi_io_dccal (void *io_pArgs) { IStepError l_StepError; - errlHndl_t l_err = NULL; TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_dmi_io_dccal entry" ); do { + auto l_procModel = TARGETING::targetService().getProcessorModel(); - TARGETING::TargetHandleList l_procTargetList; - getAllChips(l_procTargetList, TYPE_PROC); + switch (l_procModel) + { + case TARGETING::MODEL_CUMULUS: + cumulus_dccal_setup(l_StepError); + break; + case TARGETING::MODEL_AXONE: + axone_dccal_setup(l_StepError); + break; + case TARGETING::MODEL_NIMBUS: + default: + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "skipping p9_io_dmi_dccal because not required for current processor model 0x%x", l_procModel); + break; + } - if(l_procTargetList[0]->getAttr<TARGETING::ATTR_MODEL>() != TARGETING::MODEL_CUMULUS) + }while(0); + + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_dmi_io_dccal exit" ); + + // end task, returning any errorlogs to IStepDisp + return l_StepError.getErrorHandle(); +} + +#ifndef CONFIG_AXONE +void cumulus_dccal_setup(IStepError & io_istepError) +{ + errlHndl_t l_err = nullptr; + TARGETING::TargetHandleList l_procTargetList; + getAllChips(l_procTargetList, TYPE_PROC); + + for (const auto & l_proc_target : l_procTargetList) + { + // a. p9_io_dmi_dccal.C (DMI target) + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "p9_io_dmi_dccal HWP target HUID %.8x", + TARGETING::get_huid(l_proc_target)); + + // call the HWP with each target + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_fapi_proc_target + (l_proc_target); + + FAPI_INVOKE_HWP(l_err, p9_io_dmi_dccal, l_fapi_proc_target); + + // process return code. + if ( l_err ) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "p9_io_dmi_dccal Proccessor model is not CUMULUS , skipping this step"); - break; - } + "ERROR 0x%.8X: p9_io_dmi_dccal HWP on target HUID %.8x", + l_err->reasonCode(), TARGETING::get_huid(l_proc_target) ); + + // capture the target data in the elog + ErrlUserDetailsTarget(l_proc_target).addToLog( l_err ); - for (const auto & l_proc_target : l_procTargetList) + // Create IStep error log and cross reference to error that occurred + io_istepError.addErrorDetails( l_err ); + + // Commit Error + errlCommit( l_err, ISTEP_COMP_ID ); + } + else { - // a. p9_io_dmi_dccal.C (DMI target) + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : p9_io_dmi_dccal HWP on target HUID %.8x", + TARGETING::get_huid(l_proc_target) ); + } + + // b. p9_io_cen_dccal.C (Centaur target) + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "p9_io_cen_dccal HWP target HUID %.8x", + TARGETING::get_huid(l_proc_target)); + FAPI_INVOKE_HWP(l_err, p9_io_cen_dccal, l_fapi_proc_target); + + // process return code. + if ( l_err ) + { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "p9_io_dmi_dccal HWP target HUID %.8x", - TARGETING::get_huid(l_proc_target)); + "ERROR 0x%.8X: p9_io_cen_dccal HWP on target HUID %.8x", + l_err->reasonCode(), TARGETING::get_huid(l_proc_target) ); - // call the HWP with each target - fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_fapi_proc_target - (l_proc_target); + // capture the target data in the elog + ErrlUserDetailsTarget(l_proc_target).addToLog( l_err ); - FAPI_INVOKE_HWP(l_err, p9_io_dmi_dccal, l_fapi_proc_target); + // Create IStep error log and cross reference to error that occurred + io_istepError.addErrorDetails( l_err ); - // process return code. - if ( l_err ) - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X: p9_io_dmi_dccal HWP on target HUID %.8x", - l_err->reasonCode(), TARGETING::get_huid(l_proc_target) ); + // Commit Error + errlCommit( l_err, ISTEP_COMP_ID ); + } + else + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : p9_io_cen_dccal HWP on target HUID %.8x", + TARGETING::get_huid(l_proc_target) ); + } - // capture the target data in the elog - ErrlUserDetailsTarget(l_proc_target).addToLog( l_err ); + } +} +#else +void cumulus_dccal_setup(IStepError & io_istepError) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'p9_io_dmi_dccal' and 'p9_io_cen_dccal' but Cumulus code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); +} +#endif - // Create IStep error log and cross reference to error that occurred - l_StepError.addErrorDetails( l_err ); +#ifdef CONFIG_AXONE +void axone_dccal_setup(IStepError & io_istepError) +{ + errlHndl_t l_err = nullptr; + TargetHandleList l_omic_target_list; + getAllChiplets(l_omic_target_list, TYPE_OMIC); - // Commit Error - errlCommit( l_err, ISTEP_COMP_ID ); - } - else - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : p9_io_dmi_dccal HWP"); - } + for (const auto & l_omic_target : l_omic_target_list) + { + // call the HWP with each target + fapi2::Target<fapi2::TARGET_TYPE_OMIC> l_fapi_omic_target + (l_omic_target); - // b. p9_io_cen_dccal.C (Centaur target) + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "p9a_io_omi_scominit HWP target HUID %.8x", + get_huid(l_omic_target)); - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "p9_io_cen_dccal HWP target HUID %.8x", - TARGETING::get_huid(l_proc_target)); + FAPI_INVOKE_HWP(l_err, p9a_io_omi_scominit, l_fapi_omic_target); + // process return code. + if ( l_err ) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X: p9a_io_omi_scominit HWP on target HUID %.8x", + l_err->reasonCode(), TARGETING::get_huid(l_omic_target) ); - FAPI_INVOKE_HWP(l_err, p9_io_cen_dccal, l_fapi_proc_target); + // capture the target data in the elog + ErrlUserDetailsTarget(l_omic_target).addToLog( l_err ); - // process return code. - if ( l_err ) - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X: p9_io_cen_dccal HWP on target HUID %.8x", - l_err->reasonCode(), TARGETING::get_huid(l_proc_target) ); + // Create IStep error log and cross reference to error that occurred + io_istepError.addErrorDetails( l_err ); - // capture the target data in the elog - ErrlUserDetailsTarget(l_proc_target).addToLog( l_err ); + // Commit Error + errlCommit( l_err, ISTEP_COMP_ID ); + } + else + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : p9a_io_omi_scominit HWP on target HUID %.8x", + TARGETING::get_huid(l_omic_target) ); + } - // Create IStep error log and cross reference to error that occurred - l_StepError.addErrorDetails( l_err ); + TargetHandleList l_omi_target_list; - // Commit Error - errlCommit( l_err, ISTEP_COMP_ID ); - } - else - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : p9_io_cen_dccal HWP"); - } + getChildOmiTargetsByState(l_omi_target_list, + l_omic_target, + CLASS_UNIT, + TYPE_OMI, + UTIL_FILTER_FUNCTIONAL); + + uint32_t l_laneVector = 0x00000000; + + for(const auto & l_omi_target : l_omi_target_list) + { + // The OMI dc calibration HWP requires us to pass in the OMIC target + // and then a bit mask representing which positon of OMI we are calibrating. + // To get the position of the OMI relative to its parent OMIC, look up + // ATTR_OMI_DL_GROUP_POS then shift the POS_0_VECTOR = 0x000000FF by 1 byte to the left + // for every position away from 0 OMI_DL_GROUP_POS is. + // Therefore + // POS_0_VECTOR = 0x000000FF + // POS_1_VECTOR = 0x0000FF00 + // POS_2_VECTOR = 0x00FF0000 + + l_laneVector |= + POS_0_VECTOR << (l_omi_target->getAttr<ATTR_OMI_DL_GROUP_POS>() * BITS_PER_BYTE); } - }while(0); + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "p9a_io_omi_dccal HWP target HUID %.8x with lane vector 0x%x", + TARGETING::get_huid(l_omic_target), l_laneVector); + FAPI_INVOKE_HWP(l_err, p9a_io_omi_dccal, l_fapi_omic_target, l_laneVector); - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_dmi_io_dccal exit" ); + // process return code. + if ( l_err ) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X: p9a_io_omi_dccal HWP on target HUID %.8x with lane vector 0x%x", + l_err->reasonCode(), TARGETING::get_huid(l_omic_target), l_laneVector); - // end task, returning any errorlogs to IStepDisp - return l_StepError.getErrorHandle(); + // capture the target data in the elog + ErrlUserDetailsTarget(l_omic_target).addToLog( l_err ); + l_err->collectTrace("ISTEPS_TRACE", 256); + + // Create IStep error log and cross reference to error that occurred + io_istepError.addErrorDetails( l_err ); + + // Commit Error + errlCommit( l_err, ISTEP_COMP_ID ); + } + else + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : p9a_io_omi_dccal HWP on target HUID %.8x with lane vector 0x%x", + TARGETING::get_huid(l_omic_target), l_laneVector ); + } + + } +} +#else +void axone_dccal_setup(IStepError & io_istepError) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'p9a_io_omi_scominit' but Axone code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); } +#endif }; diff --git a/src/usr/isteps/istep12/call_dmi_io_run_training.C b/src/usr/isteps/istep12/call_dmi_io_run_training.C index 064a63a94..17bef45da 100644 --- a/src/usr/isteps/istep12/call_dmi_io_run_training.C +++ b/src/usr/isteps/istep12/call_dmi_io_run_training.C @@ -26,12 +26,12 @@ #include <trace/interface.H> #include <initservice/taskargs.H> +#include <initservice/isteps_trace.H> #include <errl/errlentry.H> - -#include <isteps/hwpisteperror.H> #include <errl/errludtarget.H> - -#include <initservice/isteps_trace.H> +#include <util/utilmbox_scratch.H> +#include <util/misc.H> +#include <isteps/hwpisteperror.H> // targeting support. #include <targeting/common/commontargeting.H> @@ -41,14 +41,15 @@ #include <config.h> #include <fapi2.H> #include <fapi2/plat_hwp_invoker.H> -#include <util/utilmbox_scratch.H> //HWP #include <p9_io_dmi_linktrain.H> #ifdef CONFIG_AXONE #include <exp_omi_setup.H> +#include <p9a_omi_train.H> #include <exp_omi_train.H> +#include <chipids.H> // for EXPLORER ID #endif using namespace ISTEP; @@ -109,69 +110,91 @@ void* call_dmi_io_run_training (void *io_pArgs) } #ifdef CONFIG_AXONE - TARGETING::TargetHandleList l_ocmbTargetList; - getAllChips(l_ocmbTargetList, TYPE_OCMB_CHIP); - for (const auto & l_ocmb_target : l_ocmbTargetList) - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "exp_omi_setup HWP target HUID 0x%.08x", - TARGETING::get_huid(l_ocmb_target)); - - // call the HWP with each target - fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> l_fapi_ocmb_target - (l_ocmb_target); - - FAPI_INVOKE_HWP(l_err, exp_omi_setup, l_fapi_ocmb_target); + TARGETING::TargetHandleList l_ocmbTargetList; + getAllChips(l_ocmbTargetList, TYPE_OCMB_CHIP); - // process return code. - if ( l_err ) + for (const auto & l_ocmb_target : l_ocmbTargetList) { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X: exp_omi_setup HWP on target HUID 0x%.08x", - l_err->reasonCode(), TARGETING::get_huid(l_ocmb_target) ); - - // capture the target data in the elog - ErrlUserDetailsTarget(l_ocmb_target).addToLog( l_err ); + // Only run exp_omi_train on EXPLORER OCMB targets. This step + // cannot run on GEMINI targets. + uint32_t chipId = l_ocmb_target->getAttr< TARGETING::ATTR_CHIP_ID>(); + fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> l_fapi_ocmb_target( l_ocmb_target ); + if (chipId == POWER_CHIPID::EXPLORER_16) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Start omi training on target HUID 0x%.8X", + TARGETING::get_huid(l_ocmb_target) ); + FAPI_INVOKE_HWP(l_err, exp_omi_train, l_fapi_ocmb_target); + + // process return code. + if ( l_err ) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X: exp_omi_train HWP on target HUID 0x%.08x", + l_err->reasonCode(), TARGETING::get_huid(l_ocmb_target) ); + + // capture the target data in the elog + ErrlUserDetailsTarget(l_ocmb_target).addToLog( l_err ); + + // Create IStep error log and cross reference to error that occurred + l_StepError.addErrorDetails( l_err ); + + // Commit Error , continue on to next OCMB + errlCommit( l_err, ISTEP_COMP_ID ); + } + else + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : exp_omi_train HWP on target 0x%.08X", TARGETING::get_huid(l_ocmb_target)); + } + } + else + { + // Gemini, just skip exp_omi_train call + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Skipping exp_omi_train HWP on because target HUID 0x%.8X, chipId 0x%.4X is a Gemini OCMB", + TARGETING::get_huid(l_ocmb_target), chipId ); + } + } - // Create IStep error log and cross reference to error that occurred - l_StepError.addErrorDetails( l_err ); + TARGETING::TargetHandleList l_omiTargetList; + getAllChiplets(l_omiTargetList, TYPE_OMI); - // Commit Error , continue on to next OCMB - errlCommit( l_err, ISTEP_COMP_ID ); - } - else + for (const auto & l_omi_target : l_omiTargetList) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : exp_omi_setup HWP on target 0x%.08X, starting training", TARGETING::get_huid(l_ocmb_target)); + "p9a_omi_train HWP target HUID %.8x", + TARGETING::get_huid(l_omi_target)); + + // call the HWP with each OMI target + fapi2::Target<fapi2::TARGET_TYPE_OMI> l_fapi_omi_target(l_omi_target); - FAPI_INVOKE_HWP(l_err, exp_omi_train, l_fapi_ocmb_target); + FAPI_INVOKE_HWP(l_err, p9a_omi_train , l_fapi_omi_target ); // process return code. if ( l_err ) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X: exp_omi_train HWP on target HUID 0x%.08x", - l_err->reasonCode(), TARGETING::get_huid(l_ocmb_target) ); + "ERROR 0x%.8X: p9a_omi_train HWP on target HUID %.8x", + l_err->reasonCode(), TARGETING::get_huid(l_omi_target) ); // capture the target data in the elog - ErrlUserDetailsTarget(l_ocmb_target).addToLog( l_err ); + ErrlUserDetailsTarget(l_omi_target).addToLog( l_err ); // Create IStep error log and cross reference to error that occurred l_StepError.addErrorDetails( l_err ); - // Commit Error , continue on to next OCMB + // Commit Error errlCommit( l_err, ISTEP_COMP_ID ); } else { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : exp_omi_train HWP on target 0x%.08X", TARGETING::get_huid(l_ocmb_target)); + "SUCCESS : p9a_omi_train HWP on 0x%.08X", TARGETING::get_huid(l_omi_target)); } } - } - #endif TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_dmi_io_run_training exit" ); diff --git a/src/usr/isteps/istep12/call_dmi_post_trainadv.C b/src/usr/isteps/istep12/call_dmi_post_trainadv.C index 8f5e34106..af8ca6d0f 100644 --- a/src/usr/isteps/istep12/call_dmi_post_trainadv.C +++ b/src/usr/isteps/istep12/call_dmi_post_trainadv.C @@ -26,12 +26,13 @@ #include <trace/interface.H> #include <initservice/taskargs.H> +#include <initservice/isteps_trace.H> #include <errl/errlentry.H> - -#include <isteps/hwpisteperror.H> #include <errl/errludtarget.H> +#include <isteps/hwpisteperror.H> +#include <util/utilmbox_scratch.H> +#include <util/misc.H> -#include <initservice/isteps_trace.H> // targeting support. #include <targeting/common/commontargeting.H> @@ -41,13 +42,14 @@ #include <config.h> #include <fapi2.H> #include <fapi2/plat_hwp_invoker.H> -#include <util/utilmbox_scratch.H> //HWP #include <p9_io_dmi_post_trainadv.H> #ifdef CONFIG_AXONE #include <p9a_omi_train_check.H> +#include <exp_omi_train_check.H> +#include <chipids.H> // for EXPLORER ID #endif using namespace ISTEP; @@ -129,41 +131,87 @@ void* call_dmi_post_trainadv (void *io_pArgs) } #ifdef CONFIG_AXONE - // Find omi targets - TARGETING::TargetHandleList l_omiTargetList; - getAllChiplets(l_omiTargetList, TYPE_OMI); - - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_dmi_post_trainadv: %d OMIs found", - l_omiTargetList.size()); - - for (const auto & l_omi_target : l_omiTargetList) + if( ! Util::isSimicsRunning() ) { - // call the HWP with each OMI target - fapi2::Target<fapi2::TARGET_TYPE_OMI> l_fapi_omi_target(l_omi_target); + // Find ocmb targets + TARGETING::TargetHandleList l_chipList; + TARGETING::getAllChips(l_chipList, TARGETING::TYPE_OCMB_CHIP, true); - FAPI_INVOKE_HWP(l_err, p9a_omi_train_check, l_fapi_omi_target ); + for (auto & l_ocmb: l_chipList) + { + // Only run exp_omi_train on EXPLORER OCMB targets. This step + // cannot run on GEMINI targets. + uint32_t chipId = l_ocmb->getAttr< TARGETING::ATTR_CHIP_ID>(); + if (chipId == POWER_CHIPID::EXPLORER_16) + { + fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> l_ocmb_target( l_ocmb ); + FAPI_INVOKE_HWP(l_err, exp_omi_train_check, l_ocmb_target ); + + // process return code. + if ( l_err ) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X: exp_omi_train_check HWP on target HUID %.8x", + l_err->reasonCode(), TARGETING::get_huid(l_ocmb) ); + + // capture the target data in the elog + ErrlUserDetailsTarget(l_ocmb).addToLog( l_err ); + + // Create IStep error log and cross reference to error that occurred + l_StepError.addErrorDetails( l_err ); + + // Commit Error + errlCommit( l_err, ISTEP_COMP_ID ); + } + else + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : exp_omi_train_check HWP on target HUID %.08x", + TARGETING::get_huid(l_ocmb)); + } + } + else + { + // Gemini, just skip exp_omi_train_check call + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Skipping exp_omi_train_check HWP on because target HUID 0x%.8X, chipId 0x%.4X is a Gemini OCMB", + TARGETING::get_huid(l_ocmb), chipId ); + } + } - // process return code. - if ( l_err ) + // Find omi targets + TARGETING::TargetHandleList l_omiTargetList; + getAllChiplets(l_omiTargetList, TYPE_OMI); + + for (const auto & l_omi_target : l_omiTargetList) { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X: p9a_omi_train_check HWP on target HUID %.8x", - l_err->reasonCode(), TARGETING::get_huid(l_omi_target) ); + // call the HWP with each OMI target + fapi2::Target<fapi2::TARGET_TYPE_OMI> l_fapi_omi_target(l_omi_target); - // capture the target data in the elog - ErrlUserDetailsTarget(l_omi_target).addToLog( l_err ); + FAPI_INVOKE_HWP(l_err, p9a_omi_train_check, l_fapi_omi_target ); - // Create IStep error log and cross reference to error that occurred - l_StepError.addErrorDetails( l_err ); + // process return code. + if ( l_err ) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X: p9a_omi_train_check HWP on target HUID %.8x", + l_err->reasonCode(), TARGETING::get_huid(l_omi_target) ); - // Commit Error - errlCommit( l_err, ISTEP_COMP_ID ); - } - else - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : p9a_omi_train_check HWP on target HUID %.08x", - TARGETING::get_huid(l_omi_target)); + // capture the target data in the elog + ErrlUserDetailsTarget(l_omi_target).addToLog( l_err ); + + // Create IStep error log and cross reference to error that occurred + l_StepError.addErrorDetails( l_err ); + + // Commit Error + errlCommit( l_err, ISTEP_COMP_ID ); + } + else + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : p9a_omi_train_check HWP on target HUID %.08x", + TARGETING::get_huid(l_omi_target)); + } } } #endif diff --git a/src/usr/isteps/istep12/call_dmi_pre_trainadv.C b/src/usr/isteps/istep12/call_dmi_pre_trainadv.C index da8a9bb96..09aa8a81f 100644 --- a/src/usr/isteps/istep12/call_dmi_pre_trainadv.C +++ b/src/usr/isteps/istep12/call_dmi_pre_trainadv.C @@ -26,12 +26,12 @@ #include <trace/interface.H> #include <initservice/taskargs.H> +#include <initservice/isteps_trace.H> #include <errl/errlentry.H> - -#include <isteps/hwpisteperror.H> #include <errl/errludtarget.H> - -#include <initservice/isteps_trace.H> +#include <isteps/hwpisteperror.H> +#include <util/misc.H> +#include <util/utilmbox_scratch.H> // targeting support. #include <targeting/common/commontargeting.H> @@ -41,11 +41,13 @@ #include <config.h> #include <fapi2.H> #include <fapi2/plat_hwp_invoker.H> -#include <util/utilmbox_scratch.H> + //HWP #include <p9_io_dmi_pre_trainadv.H> #ifdef CONFIG_AXONE +#include <exp_omi_setup.H> +#include <p9a_omi_setup.H> #include <p9a_omi_train.H> #endif @@ -128,45 +130,81 @@ void* call_dmi_pre_trainadv (void *io_pArgs) } #ifdef CONFIG_AXONE - TARGETING::TargetHandleList l_omiTargetList; - getAllChiplets(l_omiTargetList, TYPE_OMI); - - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_dmi_pre_trainadv: %d OMIs found", - l_omiTargetList.size()); - for (const auto & l_omi_target : l_omiTargetList) - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "p9a_omi_train HWP target HUID %.8x", - TARGETING::get_huid(l_omi_target)); + TARGETING::TargetHandleList l_ocmbTargetList; + getAllChips(l_ocmbTargetList, TYPE_OCMB_CHIP); - // call the HWP with each OMI target - fapi2::Target<fapi2::TARGET_TYPE_OMI> l_fapi_omi_target(l_omi_target); + for (const auto & l_ocmb_target : l_ocmbTargetList) + { + // call the HWP with each target + fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> l_fapi_ocmb_target + (l_ocmb_target); - FAPI_INVOKE_HWP(l_err, p9a_omi_train , l_fapi_omi_target ); - // process return code. - if ( l_err ) - { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X: p9a_omi_train HWP on target HUID %.8x", - l_err->reasonCode(), TARGETING::get_huid(l_omi_target) ); + "exp_omi_setup HWP target HUID 0x%.08x", + TARGETING::get_huid(l_ocmb_target)); + + FAPI_INVOKE_HWP(l_err, exp_omi_setup, l_fapi_ocmb_target); + + // process return code. + if ( l_err ) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X: exp_omi_setup HWP on target HUID 0x%.08x", + l_err->reasonCode(), TARGETING::get_huid(l_ocmb_target) ); - // capture the target data in the elog - ErrlUserDetailsTarget(l_omi_target).addToLog( l_err ); + // capture the target data in the elog + ErrlUserDetailsTarget(l_ocmb_target).addToLog( l_err ); - // Create IStep error log and cross reference to error that occurred - l_StepError.addErrorDetails( l_err ); + // Create IStep error log and cross reference to error that occurred + l_StepError.addErrorDetails( l_err ); - // Commit Error - errlCommit( l_err, ISTEP_COMP_ID ); + // Commit Error , continue on to next OCMB + errlCommit( l_err, ISTEP_COMP_ID ); + } } - else + + TARGETING::TargetHandleList l_omiTargetList; + getAllChiplets(l_omiTargetList, TYPE_OMI); + + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_dmi_pre_trainadv: %d OMIs found", + l_omiTargetList.size()); + + for (const auto & l_omi_target : l_omiTargetList) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : p9a_omi_train HWP on 0x%.08X", TARGETING::get_huid(l_omi_target)); + "p9a_omi_setup HWP target HUID %.8x", + TARGETING::get_huid(l_omi_target)); + + // call the HWP with each OMI target + fapi2::Target<fapi2::TARGET_TYPE_OMI> l_fapi_omi_target(l_omi_target); + + FAPI_INVOKE_HWP(l_err, p9a_omi_setup , l_fapi_omi_target ); + + // process return code. + if ( l_err ) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X: p9a_omi_setup HWP on target HUID %.8x", + l_err->reasonCode(), TARGETING::get_huid(l_omi_target) ); + + // capture the target data in the elog + ErrlUserDetailsTarget(l_omi_target).addToLog( l_err ); + + // Create IStep error log and cross reference to error that occurred + l_StepError.addErrorDetails( l_err ); + + // Commit Error + errlCommit( l_err, ISTEP_COMP_ID ); + } + else + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : p9a_omi_setup HWP on 0x%.08X", TARGETING::get_huid(l_omi_target)); + } } - } + #endif diff --git a/src/usr/isteps/istep12/call_mss_getecid.C b/src/usr/isteps/istep12/call_mss_getecid.C index 644661946..732862d32 100644 --- a/src/usr/isteps/istep12/call_mss_getecid.C +++ b/src/usr/isteps/istep12/call_mss_getecid.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -46,7 +46,14 @@ #include <util/utilmbox_scratch.H> //HWP -#include <p9c_mss_get_cen_ecid.H> +#ifndef CONFIG_AXONE + #include <p9c_mss_get_cen_ecid.H> +#else + #include <chipids.H> + #include <exp_getecid.H> + #include <gem_getecid.H> +#endif + using namespace ISTEP; using namespace ISTEP_ERROR; @@ -56,10 +63,39 @@ using namespace TARGETING; namespace ISTEP_12 { +void cumulus_mss_getecid(IStepError & io_istepError); +void axone_mss_getecid(IStepError & io_istepError); + void* call_mss_getecid (void *io_pArgs) { IStepError l_StepError; + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_getecid entry" ); + auto l_procModel = TARGETING::targetService().getProcessorModel(); + + switch (l_procModel) + { + case TARGETING::MODEL_CUMULUS: + cumulus_mss_getecid(l_StepError); + break; + case TARGETING::MODEL_AXONE: + axone_mss_getecid(l_StepError); + break; + case TARGETING::MODEL_NIMBUS: + default: + break; + } + + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_getecid exit" ); + + // end task, returning any errorlogs to IStepDisp + return l_StepError.getErrorHandle(); +} + +#ifndef CONFIG_AXONE +void cumulus_mss_getecid(IStepError & io_istepError) +{ errlHndl_t l_err = NULL; uint8_t l_ddr_port_status = 0; uint8_t l_cache_enable = 0; @@ -71,28 +107,20 @@ void* call_mss_getecid (void *io_pArgs) { MSS_GET_CEN_ECID_DDR_STATUS_MBA0_BAD, MSS_GET_CEN_ECID_DDR_STATUS_MBA1_BAD }; - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_getecid entry" ); - // Get all Centaur targets TARGETING::TargetHandleList l_membufTargetList; getAllChips(l_membufTargetList, TYPE_MEMBUF); - for (TargetHandleList::const_iterator - l_membuf_iter = l_membufTargetList.begin(); - l_membuf_iter != l_membufTargetList.end(); - ++l_membuf_iter) + for ( const auto & l_membuf_target : l_membufTargetList ) { - // make a local copy of the target for ease of use - TARGETING::Target* l_pCentaur = *l_membuf_iter; - // Dump current run on target TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "Running p9c_mss_get_cen_ecid HWP on " - "target HUID %.8X", TARGETING::get_huid(l_pCentaur)); + "target HUID %.8X", TARGETING::get_huid(l_membuf_target)); // call the HWP with each target fapi2::Target <fapi2::TARGET_TYPE_MEMBUF_CHIP> l_fapi_centaur - (l_pCentaur); + (l_membuf_target); // call the HWP with each fapi2::Target // Note: This HWP does not actually return the entire ECID data. It @@ -108,10 +136,10 @@ void* call_mss_getecid (void *io_pArgs) l_err->reasonCode()); // capture the target data in the elog - ErrlUserDetailsTarget(l_pCentaur).addToLog( l_err ); + ErrlUserDetailsTarget(l_membuf_target).addToLog( l_err ); // Create IStep error log and cross reference error that occurred - l_StepError.addErrorDetails( l_err ); + io_istepError.addErrorDetails( l_err ); // Commit Error errlCommit( l_err, HWPF_COMP_ID ); @@ -131,22 +159,14 @@ void* call_mss_getecid (void *io_pArgs) PredicateCTM l_mba_pred(CLASS_UNIT,TYPE_MBA); TARGETING::TargetHandleList l_mbaTargetList; getChildChiplets(l_mbaTargetList, - l_pCentaur, + l_membuf_target, TYPE_MBA); - uint8_t l_num_func_mbas = l_mbaTargetList.size(); - - for (TargetHandleList::const_iterator - l_mba_iter = l_mbaTargetList.begin(); - l_mba_iter != l_mbaTargetList.end(); - ++l_mba_iter) + for ( const auto & l_mba_target : l_mbaTargetList ) { - // Make a local copy of the target for ease of use - TARGETING::Target* l_pMBA = *l_mba_iter; - // Get the MBA chip unit position ATTR_CHIP_UNIT_type l_pos = - l_pMBA->getAttr<ATTR_CHIP_UNIT>(); + l_mba_target->getAttr<ATTR_CHIP_UNIT>(); // Check the DDR port status to see if this MBA should be // set to nonfunctional. @@ -154,10 +174,9 @@ void* call_mss_getecid (void *io_pArgs) { // call HWAS to deconfigure this target l_err = HWAS::theDeconfigGard().deconfigureTarget( - *l_pMBA, HWAS::DeconfigGard:: - DECONFIGURED_BY_MEMORY_CONFIG); - l_num_func_mbas--; - + *l_mba_target, + HWAS::DeconfigGard:: + DECONFIGURED_BY_MEMORY_CONFIG); if (l_err) { // shouldn't happen, but if it does, stop trying to @@ -173,7 +192,7 @@ void* call_mss_getecid (void *io_pArgs) "ERROR: error deconfiguring MBA or Centaur"); // Create IStep error log and cross ref error that occurred - l_StepError.addErrorDetails( l_err ); + io_istepError.addErrorDetails( l_err ); // Commit Error errlCommit( l_err, HWPF_COMP_ID ); @@ -212,12 +231,12 @@ void* call_mss_getecid (void *io_pArgs) // ATTR_CEN_MSS_CACHE_ENABLE is not set as writeable in src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml // Should we remove below code? // Set the ATTR_CEN_MSS_CACHE_ENABLE attribute - //l_pCentaur->setAttr<TARGETING::ATTR_CEN_MSS_CACHE_ENABLE>( + //l_membuf_target->setAttr<TARGETING::ATTR_CEN_MSS_CACHE_ENABLE>( // l_cache_enable); // Read the ATTR_CEN_MSS_CACHE_ENABLE back to pick up any override uint8_t l_cache_enable_attr = - l_pCentaur->getAttr<TARGETING::ATTR_CEN_MSS_CACHE_ENABLE>(); + l_membuf_target->getAttr<TARGETING::ATTR_CEN_MSS_CACHE_ENABLE>(); if (l_cache_enable != l_cache_enable_attr) { @@ -237,25 +256,21 @@ void* call_mss_getecid (void *io_pArgs) { // Deconfigure the L4 Cache Targets (there should be 1) TargetHandleList l_list; - getChildChiplets(l_list, l_pCentaur, TYPE_L4, false); + getChildChiplets(l_list, l_membuf_target, TYPE_L4, false); TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_getecid: deconfiguring %d L4s (Centaur huid: 0x%.8X)", - l_list.size(), get_huid(l_pCentaur)); + l_list.size(), get_huid(l_membuf_target)); - for (TargetHandleList::const_iterator - l_l4_iter = l_list.begin(); - l_l4_iter != l_list.end(); - ++l_l4_iter) + for ( const auto & l_l4_target : l_list ) { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_getecid: deconfiguring L4 (huid: 0x%.8X)", - get_huid( *l_l4_iter)); + get_huid(l_l4_target)); l_err = HWAS::theDeconfigGard(). - deconfigureTarget(**l_l4_iter , - HWAS::DeconfigGard:: - DECONFIGURED_BY_MEMORY_CONFIG); + deconfigureTarget( *l_l4_target, + HWAS::DeconfigGard::DECONFIGURED_BY_MEMORY_CONFIG); if (l_err) { @@ -264,7 +279,7 @@ void* call_mss_getecid (void *io_pArgs) // Create IStep error log // and cross reference error that occurred - l_StepError.addErrorDetails( l_err); + io_istepError.addErrorDetails( l_err); // Commit Error errlCommit(l_err, HWPF_COMP_ID); @@ -281,11 +296,82 @@ void* call_mss_getecid (void *io_pArgs) TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "SUCCESS : mss_get_cen_ecid HWP( )" ); } +} +#else +void cumulus_mss_getecid(IStepError & io_istepError) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'p9c_mss_get_cen_ecid' but Cumulus code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); +} +#endif - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_getecid exit" ); +#ifdef CONFIG_AXONE +void axone_mss_getecid(IStepError & io_istepError) +{ + errlHndl_t l_err = NULL; - // end task, returning any errorlogs to IStepDisp - return l_StepError.getErrorHandle(); -} + // Get all OCMB targets + TARGETING::TargetHandleList l_ocmbTargetList; + getAllChips(l_ocmbTargetList, TYPE_OCMB_CHIP); + + bool isGeminiChip = false; + for (const auto & l_ocmb_target : l_ocmbTargetList) + { + fapi2::Target <fapi2::TARGET_TYPE_OCMB_CHIP> + l_fapi_ocmb_target(l_ocmb_target); + + // check EXPLORER first as this is most likely the configuration + uint32_t chipId = l_ocmb_target->getAttr< TARGETING::ATTR_CHIP_ID>(); + if (chipId == POWER_CHIPID::EXPLORER_16) + { + isGeminiChip = false; + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running exp_getecid HWP on target HUID 0x%.8X", + TARGETING::get_huid(l_ocmb_target) ); + FAPI_INVOKE_HWP(l_err, exp_getecid, l_fapi_ocmb_target); + } + else + { + isGeminiChip = true; + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running gem_getecid HWP on target HUID 0x%.8X, chipId 0x%.4X", + TARGETING::get_huid(l_ocmb_target), chipId ); + FAPI_INVOKE_HWP(l_err, gem_getecid, l_fapi_ocmb_target); + } + + // process return code. + if ( l_err ) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X : %s_getecid HWP returned error", + l_err->reasonCode(), isGeminiChip?"gem":"exp"); + + // capture the target data in the elog + ErrlUserDetailsTarget(l_ocmb_target).addToLog(l_err); + + // Create IStep error log and cross reference to error that occurred + io_istepError.addErrorDetails( l_err ); + // Commit Error + errlCommit( l_err, HWPF_COMP_ID ); + + break; + } + else + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS running %s_getecid HWP on target HUID 0x%.8X", + isGeminiChip?"gem":"exp", TARGETING::get_huid(l_ocmb_target) ); + } + } +} +#else +void axone_mss_getecid(IStepError & io_istepError) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'gem_getecid' or 'exp_getecid' but Axone code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); +} +#endif }; diff --git a/src/usr/isteps/istep12/call_proc_dmi_scominit.C b/src/usr/isteps/istep12/call_proc_dmi_scominit.C index b875322b4..e0c452206 100644 --- a/src/usr/isteps/istep12/call_proc_dmi_scominit.C +++ b/src/usr/isteps/istep12/call_proc_dmi_scominit.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -46,6 +46,11 @@ // HWP #include <p9_io_dmi_scominit.H> +#ifdef CONFIG_AXONE +#include <p9a_omi_setup_bars.H> +#endif + + #include <mmio/mmio.H> using namespace ISTEP; @@ -63,6 +68,7 @@ void* call_proc_dmi_scominit (void *io_pArgs) TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_dmi_scominit entry" ); +#ifndef CONFIG_AXONE TARGETING::TargetHandleList l_dmiTargetList; getAllChiplets(l_dmiTargetList, TYPE_DMI); @@ -105,6 +111,51 @@ void* call_proc_dmi_scominit (void *io_pArgs) } +#else // CONFIG_AXONE + + TARGETING::TargetHandleList l_procTargetList; + getAllChips(l_procTargetList, TYPE_PROC); + + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_dmi_scominit: %d procs found", + l_procTargetList.size()); + + for (const auto & l_proc_target : l_procTargetList) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "p9a_omi_setup_bars HWP target HUID %.8x", + TARGETING::get_huid(l_proc_target)); + + // call the HWP with each target + fapi2::Target <fapi2::TARGET_TYPE_PROC_CHIP> l_fapi_proc_target + (l_proc_target); + + FAPI_INVOKE_HWP(l_err, p9a_omi_setup_bars, l_fapi_proc_target); + + // process return code. + if ( l_err ) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X: p9a_omi_setup_bars HWP on target HUID %.8x", + l_err->reasonCode(), TARGETING::get_huid(l_proc_target) ); + + // capture the target data in the elog + ErrlUserDetailsTarget(l_proc_target).addToLog( l_err ); + + // Create IStep error log and cross reference to error that occurred + l_StepError.addErrorDetails( l_err ); + + // Commit Error + errlCommit( l_err, ISTEP_COMP_ID ); + } + else + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : p9a_omi_setup_bars HWP"); + } + + } +#endif // CONFIG_AXONE + // map OCMBs into Hostboot memory l_err = MMIO::mmioSetup(); if ( l_err ) diff --git a/src/usr/isteps/istep12/makefile b/src/usr/isteps/istep12/makefile index 6e565529d..62f6d5727 100644 --- a/src/usr/isteps/istep12/makefile +++ b/src/usr/isteps/istep12/makefile @@ -44,6 +44,9 @@ CENT_IO_HWP_PATH = $(CENT_PROC_PATH)/hwp/io CENT_MEM_HWP_PATH = $(CENT_PROC_PATH)/hwp/memory CENT_INITFILE_PATH = $(CENT_PROC_PATH)/hwp/initfiles +GEM_PROCEDURES_PATH = ${ROOTPATH}/src/import/chips/ocmb/gemini/procedures + + #Add all the extra include paths EXTRAINCDIR += ${ROOTPATH}/src/include/usr/fapi2/ EXTRAINCDIR += ${ROOTPATH}/src/import/hwpf/fapi2/include/ @@ -68,6 +71,10 @@ EXTRAINCDIR += ${P9A_MSS_HWP_PATH} EXTRAINCDIR += ${EXPLORER_HWP_PATH} EXTRAINCDIR += ${EXPLORER_INC_PATH} EXTRAINCDIR += ${P9A_MSS_ACCESSOR_PATH} +EXTRAINCDIR += ${GEM_PROCEDURES_PATH}/hwp/memory +EXTRAINCDIR += ${GEM_PROCEDURES_PATH}/hwp/memory/lib/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/utils +EXTRAINCDIR += ${EXPLORER_HWP_PATH}/lib VPATH += $(P9_NEST_HWP_PATH) VPATH += $(P9_PERV_HWP_PATH) @@ -121,21 +128,30 @@ include $(P9_IO_HWP_PATH)/p9_io_dmi_clear_firs.mk include $(CENT_INITFILE_PATH)/centaur_dmi_scom.mk include $(P9_IO_HWP_PATH)/p9_io_erepairAccessorHwpFuncs.mk - VPATH += $(if $(CONFIG_AXONE),${P9A_MSS_HWP_PATH},) VPATH += $(if $(CONFIG_AXONE),${EXPLORER_HWP_PATH},) VPATH += $(if $(CONFIG_AXONE),${EXPLORER_OMI_HWP_PATH},) VPATH += $(if $(CONFIG_AXONE),${P9_MEMORY_HWP_PATH},) +VPATH += $(if $(CONFIG_AXONE),${GEM_PROCEDURES_PATH}/hwp/memory,) + OBJS += $(if $(CONFIG_AXONE),exp_omi_utils.o,) OBJS += $(if $(CONFIG_AXONE),exp_omi_setup.o,) OBJS += $(if $(CONFIG_AXONE),exp_omi_train.o,) +OBJS += $(if $(CONFIG_AXONE),p9a_omi_setup.o,) OBJS += $(if $(CONFIG_AXONE),p9a_omi_train.o,) OBJS += $(if $(CONFIG_AXONE),p9a_omi_train_check.o,) +OBJS += $(if $(CONFIG_AXONE),exp_omi_train_check.o,) OBJS += $(if $(CONFIG_AXONE),p9a_omi_setup_bars.o,) OBJS += $(if $(CONFIG_AXONE),p9a_addr_ext.o,) OBJS += $(if $(CONFIG_AXONE),exp_omi_init.o,) OBJS += $(if $(CONFIG_AXONE),p9a_omi_init.o,) OBJS += $(if $(CONFIG_AXONE),p9a_omi_init_scom.o,) - +OBJS += $(if $(CONFIG_AXONE),p9a_omi_io_scom.o,) +OBJS += $(if $(CONFIG_AXONE),p9a_omic_io_scom.o,) +OBJS += $(if $(CONFIG_AXONE),p9a_io_omi_scominit.o,) +OBJS += $(if $(CONFIG_AXONE),p9a_io_omi_dccal.o,) +OBJS += $(if $(CONFIG_AXONE),gem_getecid.o,) +OBJS += $(if $(CONFIG_AXONE),exp_getecid.o,) +OBJS += $(if $(CONFIG_AXONE),p9a_disable_ocmb_i2c.o,) include ${ROOTPATH}/config.mk diff --git a/src/usr/isteps/istep13/call_mss_ddr_phy_reset.C b/src/usr/isteps/istep13/call_mss_ddr_phy_reset.C index 00ffaf2fb..4f28f980b 100644 --- a/src/usr/isteps/istep13/call_mss_ddr_phy_reset.C +++ b/src/usr/isteps/istep13/call_mss_ddr_phy_reset.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -41,7 +41,9 @@ #include <fapi2.H> #include <fapi2/plat_hwp_invoker.H> #include <p9_mss_ddr_phy_reset.H> +#ifndef CONFIG_AXONE #include <p9c_mss_ddr_phy_reset.H> +#endif using namespace ERRORLOG; using namespace ISTEP; @@ -103,6 +105,7 @@ void* call_mss_ddr_phy_reset (void *io_pArgs) } // end l_mcbist loop +#ifndef CONFIG_AXONE if(l_stepError.getErrorHandle() == NULL) { // Get all Centaur targets @@ -169,6 +172,7 @@ void* call_mss_ddr_phy_reset (void *io_pArgs) } } +#endif TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_ddr_phy_reset exit" ); diff --git a/src/usr/isteps/istep13/call_mss_draminit.C b/src/usr/isteps/istep13/call_mss_draminit.C index 915bc992b..012d3111a 100644 --- a/src/usr/isteps/istep13/call_mss_draminit.C +++ b/src/usr/isteps/istep13/call_mss_draminit.C @@ -23,7 +23,7 @@ /* */ /* IBM_PROLOG_END_TAG */ -//Error handling and tracing +// Error Handling and Tracing Support #include <errl/errlentry.H> #include <errl/errlmanager.H> #include <errl/errludtarget.H> @@ -32,12 +32,15 @@ #include <initservice/initserviceif.H> #include <plat_trace.H> -//Istep 13 framework +// Generated files +#include <config.h> + +// Istep 13 framework #include <istepHelperFuncs.H> #include "istep13consts.H" #include "platform_vddr.H" -// targeting support +// Targeting support #include <targeting/common/commontargeting.H> #include <targeting/common/util.H> #include <targeting/common/utilFilter.H> @@ -47,14 +50,21 @@ //From Import Directory (EKB Repository) #include <fapi2.H> -#include <p9_mss_draminit.H> -#include <p9c_mss_draminit.H> +#ifndef CONFIG_AXONE + #include <p9_mss_draminit.H> + #include <p9c_mss_draminit.H> +#else +#include <chipids.H> + #include <exp_draminit.H> + #include <gem_draminit.H> +#endif -#ifdef CONFIG_NVDIMM // NVDIMM support +#ifdef CONFIG_NVDIMM #include <isteps/nvdimm/nvdimm.H> #endif + using namespace ERRORLOG; using namespace ISTEP; using namespace ISTEP_ERROR; @@ -62,8 +72,49 @@ using namespace TARGETING; namespace ISTEP_13 { +// Declare local functions +void nimbus_mss_draminit(IStepError & io_istepError); +void cumulus_mss_draminit(IStepError & io_istepError); +void axone_mss_draminit(IStepError & io_istepError); +void mss_post_draminit( IStepError & io_stepError ); -void mss_post_draminit( IStepError & io_stepError ) +void* call_mss_draminit (void *io_pArgs) +{ + IStepError l_stepError; + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_draminit entry" ); + auto l_procModel = TARGETING::targetService().getProcessorModel(); + + switch (l_procModel) + { + case TARGETING::MODEL_CUMULUS: + cumulus_mss_draminit(l_stepError); + break; + case TARGETING::MODEL_AXONE: + axone_mss_draminit(l_stepError); + break; + case TARGETING::MODEL_NIMBUS: + nimbus_mss_draminit(l_stepError); + break; + default: + assert(0, "call_mss_draminit: Unsupported model type 0x%04X", + l_procModel); + break; + } + + // call POST_DRAM_INIT function, if nothing failed above + if( INITSERVICE::spBaseServicesEnabled() && + (l_stepError.getErrorHandle() == nullptr) ) + { + mss_post_draminit(l_stepError); + } + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_draminit exit" ); + + return l_stepError.getErrorHandle(); +} + +void mss_post_draminit( IStepError & io_stepError ) { errlHndl_t l_err = NULL; bool rerun_vddr = false; @@ -144,14 +195,11 @@ void mss_post_draminit( IStepError & io_stepError ) return; } -void* call_mss_draminit (void *io_pArgs) +#ifndef CONFIG_AXONE +void nimbus_mss_draminit(IStepError & io_istepError) { errlHndl_t l_err = NULL; - IStepError l_stepError; - - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_draminit entry" ); - // Get all MCBIST targets TARGETING::TargetHandleList l_mcbistTargetList; getAllChiplets(l_mcbistTargetList, TYPE_MCBIST); @@ -171,6 +219,10 @@ void* call_mss_draminit (void *io_pArgs) TARGETING::TargetHandleList l_dimmTargetList; getChildAffinityTargets(l_dimmTargetList, l_mcbist_target, CLASS_NA, TYPE_DIMM); + // Generate valid encryption keys + NVDIMM::nvdimm_gen_keys(); + + // Walk the dimm list and init nvdimms for (const auto & l_dimm : l_dimmTargetList) { if (isNVDIMM(l_dimm)) @@ -178,7 +230,12 @@ void* call_mss_draminit (void *io_pArgs) NVDIMM::nvdimm_init(l_dimm); } } + // After nvdimm init + // - nvdimm controller initialized + // - nvdimm encryption unlocked + // - nvdimms disarmed #endif + FAPI_INVOKE_HWP(l_err, p9_mss_draminit, l_fapi_mcbist_target); if (l_err) @@ -191,12 +248,12 @@ void* call_mss_draminit (void *io_pArgs) ErrlUserDetailsTarget(l_mcbist_target).addToLog(l_err); // Create IStep error log and cross reference to error that occurred - l_stepError.addErrorDetails( l_err ); - - break; + io_istepError.addErrorDetails( l_err ); // Commit Error errlCommit( l_err, HWPF_COMP_ID ); + + break; } else { @@ -206,85 +263,145 @@ void* call_mss_draminit (void *io_pArgs) } } // endfor mcbist's +} +void cumulus_mss_draminit(IStepError & io_istepError) +{ + errlHndl_t l_err = NULL; + // Get all Centaur targets + TARGETING::TargetHandleList l_membufTargetList; + getAllChips(l_membufTargetList, TYPE_MEMBUF); - if(l_stepError.getErrorHandle() == NULL) + for (const auto & l_membufTarget : l_membufTargetList ) { - // Get all Centaur targets - TARGETING::TargetHandleList l_membufTargetList; - getAllChips(l_membufTargetList, TYPE_MEMBUF); - - for (TargetHandleList::const_iterator - l_membuf_iter = l_membufTargetList.begin(); - l_membuf_iter != l_membufTargetList.end(); - ++l_membuf_iter) + TARGETING::TargetHandleList l_mbaTargetList; + getChildChiplets(l_mbaTargetList, l_membufTarget, TYPE_MBA); + + for (const auto & l_mbaTarget : l_mbaTargetList ) { - // make a local copy of the target for ease of use - TARGETING::Target* l_pCentaur = *l_membuf_iter; - - TARGETING::TargetHandleList l_mbaTargetList; - getChildChiplets(l_mbaTargetList, - l_pCentaur, - TYPE_MBA); - - for (TargetHandleList::const_iterator - l_mba_iter = l_mbaTargetList.begin(); - l_mba_iter != l_mbaTargetList.end(); - ++l_mba_iter) - { - // Make a local copy of the target for ease of use - TARGETING::Target* l_mbaTarget = *l_mba_iter; - - // Dump current run on target - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "Running p9c_mss_draminit HWP on " - "target HUID %.8X", TARGETING::get_huid(l_mbaTarget)); - - // call the HWP with each target - fapi2::Target <fapi2::TARGET_TYPE_MBA_CHIPLET> l_fapi_mba_target(l_mbaTarget); - - FAPI_INVOKE_HWP(l_err, p9c_mss_draminit, l_fapi_mba_target); - - // process return code. - if ( l_err ) - { - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X : p9c_mss_draminit HWP returns error", - l_err->reasonCode()); - - // capture the target data in the elog - ErrlUserDetailsTarget(l_mbaTarget).addToLog(l_err); - - // Create IStep error log and cross reference to error that occurred - l_stepError.addErrorDetails( l_err ); - - // Commit Error - errlCommit( l_err, HWPF_COMP_ID ); - - break; - } - else - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS running p9c_mss_draminit HWP on " - "target HUID %.8X", TARGETING::get_huid(l_mbaTarget)); - } - - } - } + // Dump current run on target + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running p9c_mss_draminit HWP on " + "target HUID %.8X", TARGETING::get_huid(l_mbaTarget)); - } + // call the HWP with each target + fapi2::Target <fapi2::TARGET_TYPE_MBA_CHIPLET> l_fapi_mba_target(l_mbaTarget); + + FAPI_INVOKE_HWP(l_err, p9c_mss_draminit, l_fapi_mba_target); + + // process return code. + if ( l_err ) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X : p9c_mss_draminit HWP returns error", + l_err->reasonCode()); + + // capture the target data in the elog + ErrlUserDetailsTarget(l_mbaTarget).addToLog(l_err); + + // Create IStep error log and cross reference to error that occurred + io_istepError.addErrorDetails( l_err ); + + // Commit Error + errlCommit( l_err, HWPF_COMP_ID ); - // call POST_DRAM_INIT function - if(INITSERVICE::spBaseServicesEnabled()) + break; + } + else + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS running p9c_mss_draminit HWP on " + "target HUID %.8X", TARGETING::get_huid(l_mbaTarget)); + } + } // end MBA loop + } // end MEMBUF loop +} + +#else +void nimbus_mss_draminit(IStepError & io_istepError) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'p9_mss_draminit' but Nimbus code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); +} + +void cumulus_mss_draminit(IStepError & io_istepError) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'p9c_mss_draminit' but Cumulus code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); +} +#endif + +#ifdef CONFIG_AXONE +void axone_mss_draminit(IStepError & io_istepError) +{ + errlHndl_t l_err = NULL; + + // Get all OCMB targets + TARGETING::TargetHandleList l_ocmbTargetList; + getAllChips(l_ocmbTargetList, TYPE_OCMB_CHIP); + + bool isGeminiChip = false; + for ( const auto & l_ocmb : l_ocmbTargetList ) { - mss_post_draminit(l_stepError); - } + fapi2::Target <fapi2::TARGET_TYPE_OCMB_CHIP> l_fapi_ocmb_target(l_ocmb); - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_draminit exit" ); + // check EXPLORER first as this is most likely the configuration + uint32_t chipId = l_ocmb->getAttr< TARGETING::ATTR_CHIP_ID>(); + if (chipId == POWER_CHIPID::EXPLORER_16) + { + isGeminiChip = false; + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running exp_draminit HWP on target HUID 0x%.8X", + TARGETING::get_huid(l_ocmb) ); + FAPI_INVOKE_HWP(l_err, exp_draminit, l_fapi_ocmb_target); + } + else + { + isGeminiChip = true; + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running gem_draminit HWP on target HUID 0x%.8X, chipId 0x%.4X", + TARGETING::get_huid(l_ocmb), chipId ); + FAPI_INVOKE_HWP(l_err, gem_draminit, l_fapi_ocmb_target); + } - return l_stepError.getErrorHandle(); + // process return code. + if ( l_err ) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X : %s_draminit HWP returned error", + l_err->reasonCode(), isGeminiChip?"gem":"exp"); + + // capture the target data in the elog + ErrlUserDetailsTarget(l_ocmb).addToLog(l_err); + + // Create IStep error log and cross reference to error that occurred + io_istepError.addErrorDetails( l_err ); + + // Commit Error + errlCommit( l_err, HWPF_COMP_ID ); + + break; + } + else + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS running %s_draminit HWP on target HUID 0x%.8X", + isGeminiChip?"gem":"exp", TARGETING::get_huid(l_ocmb) ); + } + } // end of OCMB loop +} + +#else + +void axone_mss_draminit(IStepError & io_istepError) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'exp_draminit' or 'gem_draminit' but Axone code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); } +#endif }; diff --git a/src/usr/isteps/istep13/call_mss_draminit_mc.C b/src/usr/isteps/istep13/call_mss_draminit_mc.C index cee7771bf..54b790de2 100644 --- a/src/usr/isteps/istep13/call_mss_draminit_mc.C +++ b/src/usr/isteps/istep13/call_mss_draminit_mc.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -44,8 +44,14 @@ //From Import Directory (EKB Repository) #include <config.h> #include <fapi2.H> +#ifdef CONFIG_AXONE +#include <exp_draminit_mc.H> +#include <chipids.H> // for EXPLORER ID +#else #include <p9_mss_draminit_mc.H> #include <p9c_mss_draminit_mc.H> +#endif + using namespace ERRORLOG; @@ -66,6 +72,8 @@ void* call_mss_draminit_mc (void *io_pArgs) TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,"call_mss_draminit_mc entry" ); +#ifndef CONFIG_AXONE + // Get all MCBIST TARGETING::TargetHandleList l_mcbistTargetList; getAllChiplets(l_mcbistTargetList, TYPE_MCBIST); @@ -117,8 +125,8 @@ void* call_mss_draminit_mc (void *io_pArgs) { // Dump current run on target TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "Running p9_mss_draminit_mc HWP on " - "target HUID %.8X", TARGETING::get_huid(l_membuf_target)); + "Running p9_mss_draminit_mc HWP on target HUID %.8X", + TARGETING::get_huid(l_membuf_target) ); fapi2::Target <fapi2::TARGET_TYPE_MEMBUF_CHIP> l_fapi_membuf_target (l_membuf_target); @@ -133,26 +141,84 @@ void* call_mss_draminit_mc (void *io_pArgs) l_err->reasonCode()); // capture the target data in the elog - ErrlUserDetailsTarget(l_fapi_membuf_target).addToLog( l_err ); + ErrlUserDetailsTarget(l_membuf_target).addToLog( l_err ); - // Create IStep error log and cross reference to error that occurred + // Create IStep error log and cross reference to error + // that occurred l_stepError.addErrorDetails( l_err ); // Commit Error errlCommit( l_err, HWPF_COMP_ID ); - + break; } else { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "SUCCESS running p9c_mss_draminit_mc HWP on " - "target HUID %.8X", TARGETING::get_huid(l_fapi_membuf_target)); + "target HUID %.8X", + TARGETING::get_huid(l_membuf_target)); } - } } +#else + + // Get all OCMB targets + TARGETING::TargetHandleList l_ocmbTargetList; + getAllChips(l_ocmbTargetList, TYPE_OCMB_CHIP); + + for (const auto & l_ocmb_target : l_ocmbTargetList) + { + // check EXPLORER first as this is most likely the configuration + uint32_t chipId = l_ocmb_target->getAttr< TARGETING::ATTR_CHIP_ID>(); + if (chipId == POWER_CHIPID::EXPLORER_16) + { + fapi2::Target <fapi2::TARGET_TYPE_OCMB_CHIP> l_fapi_ocmb_target + (l_ocmb_target); + + // Dump current run on target + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running exp_draminit_mc HWP on " + "target HUID %.8X", TARGETING::get_huid(l_ocmb_target)); + + // call the HWP with each fapi2::Target + FAPI_INVOKE_HWP(l_err, exp_draminit_mc, l_fapi_ocmb_target); + } + else + { + // Gemini, NOOP + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Skipping draminit_mc HWP on target HUID 0x%.8X, chipId 0x%.4X", + TARGETING::get_huid(l_ocmb_target), chipId ); + } + if (l_err) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X : exp_draminit_mc HWP returns error", + l_err->reasonCode()); + + // capture the target data in the elog + ErrlUserDetailsTarget(l_ocmb_target).addToLog( l_err ); + + // Create IStep error log and cross reference to error that occurred + l_stepError.addErrorDetails( l_err ); + + // Commit Error + errlCommit( l_err, HWPF_COMP_ID ); + + break; + } + else if (chipId == POWER_CHIPID::EXPLORER_16) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS running exp_draminit_mc HWP on target HUID %.8X", + TARGETING::get_huid(l_ocmb_target)); + } + } + +#endif + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_draminit_mc exit" ); return l_stepError.getErrorHandle(); diff --git a/src/usr/isteps/istep13/call_mss_draminit_trainadv.C b/src/usr/isteps/istep13/call_mss_draminit_trainadv.C index fc42f7264..31e0a50d3 100644 --- a/src/usr/isteps/istep13/call_mss_draminit_trainadv.C +++ b/src/usr/isteps/istep13/call_mss_draminit_trainadv.C @@ -110,6 +110,7 @@ class MembufWorkItem: public IStepWorkItem //****************************************************************************** void MembufWorkItem::operator()() { +#ifndef CONFIG_AXONE errlHndl_t l_err = nullptr; // reset watchdog for each memb as this function can be very slow @@ -154,7 +155,7 @@ void MembufWorkItem::operator()() mutex_unlock(&g_stepErrorMutex); // Commit Error - errlCommit( l_err, HWPF_COMP_ID ); + errlCommit( l_err, ISTEP_COMP_ID ); break; } @@ -165,6 +166,8 @@ void MembufWorkItem::operator()() TARGETING::get_huid(l_mbaTarget)); } } +#endif + } @@ -210,7 +213,7 @@ void* call_mss_draminit_trainadv (void *io_pArgs) l_stepError.addErrorDetails( l_err ); // Commit Error - errlCommit( l_err, HWPF_COMP_ID ); + errlCommit( l_err, ISTEP_COMP_ID ); } TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, @@ -252,7 +255,14 @@ void* call_mss_draminit_trainadv (void *io_pArgs) tp.start(); //wait for all workitems to complete, then clean up all threads. - tp.shutdown(); + l_err = tp.shutdown(); + if(l_err) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + ERR_MRK"call_mss_draminit_trainadv: thread pool returned an error"); + l_stepError.addErrorDetails(l_err); + errlCommit(l_err, ISTEP_COMP_ID); + } } TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, diff --git a/src/usr/isteps/istep13/call_mss_draminit_training.C b/src/usr/isteps/istep13/call_mss_draminit_training.C index a167457e9..d790e3483 100644 --- a/src/usr/isteps/istep13/call_mss_draminit_training.C +++ b/src/usr/isteps/istep13/call_mss_draminit_training.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -102,6 +102,7 @@ void* call_mss_draminit_training (void *io_pArgs) } } +#ifndef CONFIG_AXONE if(l_stepError.getErrorHandle() == NULL) { // Get all Centaur targets @@ -169,6 +170,7 @@ void* call_mss_draminit_training (void *io_pArgs) } } +#endif TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_draminit_training exit" ); diff --git a/src/usr/isteps/istep13/call_mss_scominit.C b/src/usr/isteps/istep13/call_mss_scominit.C index 69e05c7ee..6c623f1d2 100644 --- a/src/usr/isteps/istep13/call_mss_scominit.C +++ b/src/usr/isteps/istep13/call_mss_scominit.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2019 */ +/* Contributors Listed Below - COPYRIGHT 2015,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -42,10 +42,13 @@ #include <config.h> #include <fapi2.H> #include <p9_mss_scominit.H> -#include <p9_throttle_sync.H> -#include <p9c_mss_scominit.H> #ifdef CONFIG_AXONE -#include <exp_scominit.H> + #include <exp_scominit.H> + #include <chipids.H> // for EXPLORER ID + #include <p9a_throttle_sync.H> +#else + #include <p9c_mss_scominit.H> + #include <p9_throttle_sync.H> #endif using namespace ERRORLOG; @@ -55,163 +58,290 @@ using namespace TARGETING; namespace ISTEP_13 { +void nimbus_call_mss_scominit(IStepError & io_istepError); +void cumulus_call_mss_scominit(IStepError & io_istepError); +void axone_call_mss_scominit(IStepError & io_istepError); +void run_proc_throttle_sync(IStepError & io_istepError); + void* call_mss_scominit (void *io_pArgs) { - errlHndl_t l_err = NULL; - - IStepError l_stepError; + IStepError l_StepError; TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_scominit entry" ); + auto l_procModel = TARGETING::targetService().getProcessorModel(); - do + switch (l_procModel) { - // Get all MCBIST targets - TARGETING::TargetHandleList l_mcbistTargetList; - getAllChiplets(l_mcbistTargetList, TYPE_MCBIST); + case TARGETING::MODEL_CUMULUS: + cumulus_call_mss_scominit(l_StepError); + break; + case TARGETING::MODEL_AXONE: + axone_call_mss_scominit(l_StepError); + break; + case TARGETING::MODEL_NIMBUS: + nimbus_call_mss_scominit(l_StepError); + break; + default: + assert(0, "call_mss_scominit: Unsupported model type 0x%04X", + l_procModel); + break; + } + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_scominit exit" ); + + // end task, returning any errorlogs to IStepDisp + return l_StepError.getErrorHandle(); +} + +#ifndef CONFIG_AXONE + +void nimbus_call_mss_scominit(IStepError & io_istepError) +{ + errlHndl_t l_err = nullptr; - for (const auto & l_target : l_mcbistTargetList) + // Get all MCBIST targets + TARGETING::TargetHandleList l_mcbistTargetList; + getAllChiplets(l_mcbistTargetList, TYPE_MCBIST); + + for (const auto & l_target : l_mcbistTargetList) + { + // Dump current run on target + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running p9_mss_scominit HWP on target HUID %.8X", + TARGETING::get_huid(l_target)); + + fapi2::Target <fapi2::TARGET_TYPE_MCBIST> l_fapi_target + (l_target); + + // call the HWP with each fapi2::Target + FAPI_INVOKE_HWP(l_err, p9_mss_scominit, l_fapi_target); + + if (l_err) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X: p9_mss_scominit HWP returns error", + l_err->reasonCode()); + + // capture the target data in the elog + ErrlUserDetailsTarget(l_target).addToLog(l_err); + + // Create IStep error log and cross reference to error that + // occurred + io_istepError.addErrorDetails( l_err ); + + // Commit Error + errlCommit( l_err, HWPF_COMP_ID ); + + break; + } + else { - // Dump current run on target TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "Running p9_mss_scominit HWP on " - "target HUID %.8X", + "SUCCESS running p9_mss_scominit HWP on target HUID %.8X", TARGETING::get_huid(l_target)); + } + } +} - fapi2::Target <fapi2::TARGET_TYPE_MCBIST> l_fapi_target - (l_target); +void cumulus_call_mss_scominit(IStepError & io_istepError) +{ - // call the HWP with each fapi2::Target - FAPI_INVOKE_HWP(l_err, p9_mss_scominit, l_fapi_target); - - if (l_err) - { - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X: p9_mss_scominit HWP returns error", - l_err->reasonCode()); - - // capture the target data in the elog - ErrlUserDetailsTarget(l_target).addToLog(l_err); - - // Create IStep error log and cross reference to error that - // occurred - l_stepError.addErrorDetails( l_err ); - - // Commit Error - errlCommit( l_err, HWPF_COMP_ID ); - - break; - } - else - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS running p9_mss_scominit HWP on " - "target HUID %.8X", TARGETING::get_huid(l_target)); - } - } + errlHndl_t l_err = nullptr; - if (!l_stepError.isNull()) + // Get all MBA targets + TARGETING::TargetHandleList l_membufTargetList; + getAllChips(l_membufTargetList, TYPE_MEMBUF); + + for (const auto & l_membuf_target : l_membufTargetList) + { + // Dump current run on target + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running p9c_mss_scominit HWP on target HUID %.8X", + TARGETING::get_huid(l_membuf_target)); + + fapi2::Target <fapi2::TARGET_TYPE_MEMBUF_CHIP> l_fapi_membuf_target + (l_membuf_target); + + // call the HWP with each fapi2::Target + FAPI_INVOKE_HWP(l_err, p9c_mss_scominit, l_fapi_membuf_target); + + if (l_err) { - break; - } + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X: p9c_mss_scominit HWP returns error", + l_err->reasonCode()); + + // capture the target data in the elog + ErrlUserDetailsTarget(l_membuf_target).addToLog(l_err); + + // Create IStep error log and cross reference to error that + // occurred + io_istepError.addErrorDetails( l_err ); - // Get all MBA targets - TARGETING::TargetHandleList l_membufTargetList; - getAllChips(l_membufTargetList, TYPE_MEMBUF); + // Commit Error + errlCommit( l_err, HWPF_COMP_ID ); - for (const auto & l_membuf_target : l_membufTargetList) + break; + } + else { - // Dump current run on target TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "Running p9c_mss_scominit HWP on " - "target HUID %.8X", - TARGETING::get_huid(l_membuf_target)); + "SUCCESS running p9c_mss_scominit HWP on target HUID %.8X", + TARGETING::get_huid(l_membuf_target)); + } + } - fapi2::Target <fapi2::TARGET_TYPE_MEMBUF_CHIP> l_fapi_membuf_target - (l_membuf_target); + // Setup the memory throttles for worstcase mode + run_proc_throttle_sync(io_istepError); + +} +#else +void nimbus_call_mss_scominit(IStepError & io_istepError) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'p9_mss_scominit' but Nimbus code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); +} + +void cumulus_call_mss_scominit(IStepError & io_istepError) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'p9c_mss_scominit' but Cumulus code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); +} + +#endif - // call the HWP with each fapi2::Target - FAPI_INVOKE_HWP(l_err, p9c_mss_scominit, l_fapi_membuf_target); - - if (l_err) - { - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X: p9c_mss_scominit HWP returns error", - l_err->reasonCode()); - - // capture the target data in the elog - ErrlUserDetailsTarget(l_membuf_target).addToLog(l_err); - - // Create IStep error log and cross reference to error that - // occurred - l_stepError.addErrorDetails( l_err ); - - // Commit Error - errlCommit( l_err, HWPF_COMP_ID ); - - break; - } - else - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS running p9c_mss_scominit HWP on " - "target HUID %.8X", TARGETING::get_huid(l_membuf_target)); - } - } #ifdef CONFIG_AXONE - // Get all OCMB targets - TARGETING::TargetHandleList l_ocmbTargetList; - getAllChips(l_ocmbTargetList, TYPE_OCMB_CHIP); +void axone_call_mss_scominit(IStepError & io_istepError) +{ - for (const auto & l_ocmb_target : l_ocmbTargetList) - { - // Dump current run on target - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "Running exp_scominit HWP on " - "target HUID %.8X", - TARGETING::get_huid(l_ocmb_target)); + errlHndl_t l_err = nullptr; + + // Get all OCMB targets + TARGETING::TargetHandleList l_ocmbTargetList; + getAllChips(l_ocmbTargetList, TYPE_OCMB_CHIP); + for (const auto & l_ocmb_target : l_ocmbTargetList) + { + // check EXPLORER first as this is most likely the configuration + uint32_t chipId = l_ocmb_target->getAttr< TARGETING::ATTR_CHIP_ID>(); + if (chipId == POWER_CHIPID::EXPLORER_16) + { fapi2::Target <fapi2::TARGET_TYPE_OCMB_CHIP> l_fapi_ocmb_target (l_ocmb_target); + // Dump current run on target + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running exp_scominit HWP on target HUID %.8X", + TARGETING::get_huid(l_ocmb_target)); + // call the HWP with each fapi2::Target FAPI_INVOKE_HWP(l_err, exp_scominit, l_fapi_ocmb_target); - - if (l_err) - { - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X: exp_scominit HWP returns error", - l_err->reasonCode()); - - // capture the target data in the elog - ErrlUserDetailsTarget(l_fapi_ocmb_target).addToLog(l_err); - - // Create IStep error log and cross reference to error that - // occurred - l_stepError.addErrorDetails( l_err ); - - // Commit Error - errlCommit( l_err, HWPF_COMP_ID ); - - break; - } - else - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS running exp_scominit HWP on " - "target HUID %.8X", TARGETING::get_huid(l_ocmb_target)); - } + } + else + { + // Gemini, NOOP + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Skipping scominit HWP on target HUID 0x%.8X, chipId 0x%.4X", + TARGETING::get_huid(l_ocmb_target), chipId ); } - if (!l_stepError.isNull()) + if (l_err) { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X: exp_scominit HWP returns error", + l_err->reasonCode()); + + // capture the target data in the elog + ErrlUserDetailsTarget(l_ocmb_target).addToLog(l_err); + + // Create IStep error log and cross reference to error that + // occurred + io_istepError.addErrorDetails( l_err ); + + // Commit Error + errlCommit( l_err, HWPF_COMP_ID ); + break; } + else if (chipId == POWER_CHIPID::EXPLORER_16) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS running exp_scominit HWP on " + "target HUID %.8X", TARGETING::get_huid(l_ocmb_target)); + } + } + + // Need to setup the memory throttles for worstcase mode until + // we get the thermals really setup later + run_proc_throttle_sync(io_istepError); + +} +#else +void axone_call_mss_scominit(IStepError & io_istepError) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'exp_scominit' but Axone code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); +} #endif - } while (0); +void run_proc_throttle_sync(IStepError & io_istepError) +{ + errlHndl_t l_errl = nullptr; + + // Run proc throttle sync + // Get all functional proc chip targets + // Use targeting code to get a list of all processors + TARGETING::TargetHandleList l_procChips; + getAllChips( l_procChips, TARGETING::TYPE_PROC ); - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_scominit exit" ); - return l_stepError.getErrorHandle(); + for (const auto & l_procChip: l_procChips) + { + //Convert the TARGETING::Target into a fapi2::Target by passing + //l_procChip into the fapi2::Target constructor + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> + l_fapi2CpuTarget((l_procChip)); + + // Call p9_throttle_sync +#ifndef CONFIG_AXONE + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running p9_throttle_sync HWP on target HUID %.8X", + TARGETING::get_huid(l_procChip) ); + FAPI_INVOKE_HWP( l_errl, p9_throttle_sync, l_fapi2CpuTarget ); +#else + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running p9a_throttle_sync HWP on target HUID %.8X", + TARGETING::get_huid(l_procChip) ); + FAPI_INVOKE_HWP( l_errl, p9a_throttle_sync, l_fapi2CpuTarget ); +#endif + + if (l_errl) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X: p9_throttle_sync HWP returns error", + l_errl->reasonCode()); + + // Capture the target data in the elog + ErrlUserDetailsTarget(l_procChip).addToLog(l_errl); + + // Create IStep error log and cross reference + // to error that occurred + io_istepError.addErrorDetails( l_errl ); + + // Commit Error + errlCommit( l_errl, HWPF_COMP_ID ); + + break; + } + else + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : p9_throttle_sync HWP on 0x%.8X processor", + TARGETING::get_huid(l_procChip) ); + } + } } }; diff --git a/src/usr/isteps/istep13/istep13consts.H b/src/usr/isteps/istep13/istep13consts.H index cf459f82e..218c89283 100644 --- a/src/usr/isteps/istep13/istep13consts.H +++ b/src/usr/isteps/istep13/istep13consts.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -29,5 +29,5 @@ const uint8_t UNLIMITED_RUN = 0xFF; const uint8_t VPO_NUM_OF_MBAS_TO_RUN = UNLIMITED_RUN; const uint8_t VPO_NUM_OF_MEMBUF_TO_RUN = UNLIMITED_RUN; -const uint8_t ISTEP13_MAX_THREADS = 1; +const uint8_t ISTEP13_MAX_THREADS = 4; #endif diff --git a/src/usr/isteps/istep13/makefile b/src/usr/isteps/istep13/makefile index bd38d4f71..d85873963 100644 --- a/src/usr/isteps/istep13/makefile +++ b/src/usr/isteps/istep13/makefile @@ -25,11 +25,12 @@ ROOTPATH = ../../../.. MODULE = istep13 -PROCEDURES_PATH = ${ROOTPATH}/src/import/chips/p9/procedures -CEN_PROCEDURES_PATH = ${ROOTPATH}/src/import/chips/centaur/procedures +P9_PROCEDURES_PATH = ${ROOTPATH}/src/import/chips/p9/procedures +CEN_PROCEDURES_PATH = ${ROOTPATH}/src/import/chips/centaur/procedures OCMB_PROCEDURES_PATH = ${ROOTPATH}/src/import/chips/ocmb/procedures -EXP_PROCEDURES_PATH = ${ROOTPATH}/src/import/chips/ocmb/explorer/procedures - +EXP_PROCEDURES_PATH = ${ROOTPATH}/src/import/chips/ocmb/explorer/procedures +EXP_INCLUDE_PATH = ${ROOTPATH}/src/import/chips/ocmb/explorer/common/include/ +GEM_PROCEDURES_PATH = ${ROOTPATH}/src/import/chips/ocmb/gemini/procedures #Add all the extra include paths EXTRAINCDIR += ${ROOTPATH}/src/include/usr/fapi2 @@ -42,14 +43,14 @@ EXTRAINCDIR += ${ROOTPATH}/src/import/ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/utils/imageProcs/ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/utils/imageProcs/ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/common/include -EXTRAINCDIR += ${PROCEDURES_PATH}/hwp/memory -EXTRAINCDIR += ${PROCEDURES_PATH}/hwp/memory/lib -EXTRAINCDIR += ${PROCEDURES_PATH}/hwp/memory/lib/utils -EXTRAINCDIR += ${PROCEDURES_PATH}/hwp/memory/lib/mc/ -EXTRAINCDIR += ${PROCEDURES_PATH}/hwp/memory/lib/fir/ -EXTRAINCDIR += ${PROCEDURES_PATH}/hwp/perv -EXTRAINCDIR += ${PROCEDURES_PATH}/hwp/nest -EXTRAINCDIR += ${PROCEDURES_PATH}/hwp/initfiles +EXTRAINCDIR += ${P9_PROCEDURES_PATH}/hwp/memory +EXTRAINCDIR += ${P9_PROCEDURES_PATH}/hwp/memory/lib +EXTRAINCDIR += ${P9_PROCEDURES_PATH}/hwp/memory/lib/utils +EXTRAINCDIR += ${P9_PROCEDURES_PATH}/hwp/memory/lib/mc/ +EXTRAINCDIR += ${P9_PROCEDURES_PATH}/hwp/memory/lib/fir/ +EXTRAINCDIR += ${P9_PROCEDURES_PATH}/hwp/perv +EXTRAINCDIR += ${P9_PROCEDURES_PATH}/hwp/nest +EXTRAINCDIR += ${P9_PROCEDURES_PATH}/hwp/initfiles EXTRAINCDIR += ${ROOTPATH}/src/import/chips/centaur/common/include/ EXTRAINCDIR += ${ROOTPATH}/src/import/ EXTRAINCDIR += ${ROOTPATH}/ @@ -60,7 +61,13 @@ EXTRAINCDIR += ${CEN_PROCEDURES_PATH}/hwp/memory/lib/utils/ EXTRAINCDIR += ${CEN_PROCEDURES_PATH}/hwp/initfiles EXTRAINCDIR += ${EXP_PROCEDURES_PATH}/hwp/memory/ EXTRAINCDIR += ${OCMB_PROCEDURES_PATH}/hwp/initfiles/ - +EXTRAINCDIR += ${EXP_INCLUDE_PATH}/ +EXTRAINCDIR += ${ROOTPATH}/obj/genfiles/ +EXTRAINCDIR += ${ROOTPATH}/obj/genfiles/chips/ocmb/explorer/procedures/hwp/memory/lib/ +EXTRAINCDIR += ${ROOTPATH}/obj/genfiles/generic/memory/lib/ +EXTRAINCDIR += ${GEM_PROCEDURES_PATH}/hwp/memory +EXTRAINCDIR += ${GEM_PROCEDURES_PATH}/hwp/memory/lib/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/utils # from src/usr/isteps/istep13 OBJS += call_host_disable_memvolt.o @@ -81,61 +88,63 @@ OBJS += call_mss_draminit_mc.o include ${ROOTPATH}/procedure.rules.mk # PLL HWPs -include ${PROCEDURES_PATH}/hwp/perv/p9_mem_pll_initf.mk -include ${PROCEDURES_PATH}/hwp/perv/p9_mem_pll_setup.mk -include ${PROCEDURES_PATH}/hwp/perv/p9_mem_pll_reset.mk +include ${P9_PROCEDURES_PATH}/hwp/perv/p9_mem_pll_initf.mk +include ${P9_PROCEDURES_PATH}/hwp/perv/p9_mem_pll_setup.mk +include ${P9_PROCEDURES_PATH}/hwp/perv/p9_mem_pll_reset.mk #Start Memclocks -include ${PROCEDURES_PATH}/hwp/perv/p9_mem_startclocks.mk +include ${P9_PROCEDURES_PATH}/hwp/perv/p9_mem_startclocks.mk #Scom init -include ${PROCEDURES_PATH}/hwp/memory/p9_mss_scominit.mk -include ${PROCEDURES_PATH}/hwp/nest/p9_throttle_sync.mk -include ${CEN_PROCEDURES_PATH}/hwp/memory/p9c_mss_scominit.mk +include ${P9_PROCEDURES_PATH}/hwp/memory/p9_mss_scominit.mk +OBJS += $(if $(CONFIG_AXONE),,p9c_mss_scominit.o) -include ${PROCEDURES_PATH}/hwp/initfiles/p9n_ddrphy_scom.mk -include ${PROCEDURES_PATH}/hwp/initfiles/p9n_mca_scom.mk -include ${PROCEDURES_PATH}/hwp/initfiles/p9n_mcbist_scom.mk +include ${P9_PROCEDURES_PATH}/hwp/initfiles/p9n_ddrphy_scom.mk +include ${P9_PROCEDURES_PATH}/hwp/initfiles/p9n_mca_scom.mk +include ${P9_PROCEDURES_PATH}/hwp/initfiles/p9n_mcbist_scom.mk #Dram init -include ${PROCEDURES_PATH}/hwp/memory/p9_mss_draminit.mk -include ${PROCEDURES_PATH}/hwp/memory/p9_mss_draminit_training.mk -include ${PROCEDURES_PATH}/hwp/memory/p9_mss_draminit_mc.mk -include ${PROCEDURES_PATH}/hwp/memory/p9_mss_ddr_phy_reset.mk -include ${PROCEDURES_PATH}/hwp/memory/p9_mss_draminit_training_adv.mk - -include ${CEN_PROCEDURES_PATH}/hwp/memory/p9c_mss_mcbist.mk -include ${CEN_PROCEDURES_PATH}/hwp/memory/p9c_mss_mcbist_common.mk -include ${CEN_PROCEDURES_PATH}/hwp/memory/p9c_mss_mcbist_address.mk -include ${CEN_PROCEDURES_PATH}/hwp/memory/p9c_mss_generic_shmoo.mk -include ${CEN_PROCEDURES_PATH}/hwp/memory/p9c_mss_draminit.mk -include ${CEN_PROCEDURES_PATH}/hwp/memory/p9c_mss_draminit_mc.mk -include ${CEN_PROCEDURES_PATH}/hwp/memory/p9c_mss_draminit_training.mk -include ${CEN_PROCEDURES_PATH}/hwp/memory/p9c_mss_ddr_phy_reset.mk -include ${CEN_PROCEDURES_PATH}/hwp/memory/p9c_mss_draminit_training_advanced.mk -include ${CEN_PROCEDURES_PATH}/hwp/memory/p9c_mss_mrs6_DDR4.mk -include ${CEN_PROCEDURES_PATH}/hwp/memory/p9c_mss_ddr4_pda.mk -include ${CEN_PROCEDURES_PATH}/hwp/memory/p9c_mss_ddr4_funcs.mk -include ${CEN_PROCEDURES_PATH}/hwp/memory/p9c_mss_termination_control.mk -include ${CEN_PROCEDURES_PATH}/hwp/memory/p9c_mss_access_delay_reg.mk -include ${CEN_PROCEDURES_PATH}/hwp/memory/p9c_mss_unmask_errors.mk -include ${CEN_PROCEDURES_PATH}/hwp/memory/p9c_dimmBadDqBitmapFuncs.mk -include ${CEN_PROCEDURES_PATH}/hwp/memory/p9c_mss_funcs.mk -include ${CEN_PROCEDURES_PATH}/hwp/initfiles/centaur_mbs_scom.mk -include ${CEN_PROCEDURES_PATH}/hwp/initfiles/centaur_mba_scom.mk -include ${CEN_PROCEDURES_PATH}/hwp/initfiles/centaur_ddrphy_scom.mk -include ${CEN_PROCEDURES_PATH}/hwp/memory/p9c_mss_row_repair.mk +include ${P9_PROCEDURES_PATH}/hwp/memory/p9_mss_draminit.mk +include ${P9_PROCEDURES_PATH}/hwp/memory/p9_mss_draminit_training.mk +include ${P9_PROCEDURES_PATH}/hwp/memory/p9_mss_draminit_mc.mk +include ${P9_PROCEDURES_PATH}/hwp/memory/p9_mss_ddr_phy_reset.mk +include ${P9_PROCEDURES_PATH}/hwp/memory/p9_mss_draminit_training_adv.mk + +OBJS += $(if $(CONFIG_AXONE),,p9c_mss_mcbist.o) +OBJS += $(if $(CONFIG_AXONE),,p9c_mss_mcbist_common.o) +OBJS += $(if $(CONFIG_AXONE),,p9c_mss_mcbist_address.o) +OBJS += $(if $(CONFIG_AXONE),,p9c_mss_generic_shmoo.o) +OBJS += $(if $(CONFIG_AXONE),,p9c_mss_draminit.o) +OBJS += $(if $(CONFIG_AXONE),,p9c_mss_draminit_mc.o) +OBJS += $(if $(CONFIG_AXONE),,p9c_mss_draminit_training.o) +OBJS += $(if $(CONFIG_AXONE),,p9c_mss_ddr_phy_reset.o) +OBJS += $(if $(CONFIG_AXONE),,p9c_mss_draminit_training_advanced.o) +OBJS += $(if $(CONFIG_AXONE),,p9c_mss_mrs6_DDR4.o) +OBJS += $(if $(CONFIG_AXONE),,p9c_mss_ddr4_pda.o) +OBJS += $(if $(CONFIG_AXONE),,p9c_mss_ddr4_funcs.o) +OBJS += $(if $(CONFIG_AXONE),,p9c_mss_termination_control.o) +OBJS += $(if $(CONFIG_AXONE),,p9c_mss_access_delay_reg.o) +OBJS += $(if $(CONFIG_AXONE),,p9c_mss_unmask_errors.o) +OBJS += $(if $(CONFIG_AXONE),,p9c_dimmBadDqBitmapFuncs.o) +OBJS += $(if $(CONFIG_AXONE),,p9c_mss_funcs.o) +OBJS += $(if $(CONFIG_AXONE),,centaur_mbs_scom.o) +OBJS += $(if $(CONFIG_AXONE),,centaur_mba_scom.o) +OBJS += $(if $(CONFIG_AXONE),,centaur_ddrphy_scom.o) +OBJS += $(if $(CONFIG_AXONE),,p9c_mss_row_repair.o) OBJS += $(if $(CONFIG_AXONE),exp_scominit.o,) OBJS += $(if $(CONFIG_AXONE),explorer_scom.o,) +OBJS += $(if $(CONFIG_AXONE),exp_draminit_mc.o,) +OBJS += $(if $(CONFIG_AXONE),exp_draminit.o,) +OBJS += $(if $(CONFIG_AXONE),gem_draminit.o,) include ${ROOTPATH}/config.mk -VPATH += ${PROCEDURES_PATH}/hwp/memory ${PROCEDURES_PATH}/hwp/nest ${PROCEDURES_PATH}/hwp/perv ${PROCEDURES_PATH}/hwp/initfiles/ -VPATH += ${PROCEDURES_PATH}/hwp/memory/lib/ccs/ ${PROCEDURES_PATH}/hwp/memory/lib/dimm/ ${PROCEDURES_PATH}/hwp/memory/lib/utils/ ${PROCEDURES_PATH}/hwp/memory/lib/phy/ -VPATH += ${PROCEDURES_PATH}/hwp/memory/lib/mc/ -VPATH += ${PROCEDURES_PATH}/hwp/memory/lib/fir/ -VPATH += ${PROCEDURES_PATH}/hwp/memory/lib/dimm/ddr4/ +VPATH += ${P9_PROCEDURES_PATH}/hwp/memory ${P9_PROCEDURES_PATH}/hwp/nest ${P9_PROCEDURES_PATH}/hwp/perv ${P9_PROCEDURES_PATH}/hwp/initfiles/ +VPATH += ${P9_PROCEDURES_PATH}/hwp/memory/lib/ccs/ ${P9_PROCEDURES_PATH}/hwp/memory/lib/dimm/ ${P9_PROCEDURES_PATH}/hwp/memory/lib/utils/ ${P9_PROCEDURES_PATH}/hwp/memory/lib/phy/ +VPATH += ${P9_PROCEDURES_PATH}/hwp/memory/lib/mc/ +VPATH += ${P9_PROCEDURES_PATH}/hwp/memory/lib/fir/ +VPATH += ${P9_PROCEDURES_PATH}/hwp/memory/lib/dimm/ddr4/ VPATH += ${CEN_PROCEDURES_PATH} VPATH += ${CEN_PROCEDURES_PATH}/hwp/memory/ VPATH += ${CEN_PROCEDURES_PATH}/hwp/memory/lib/ @@ -144,4 +153,5 @@ VPATH += ${CEN_PROCEDURES_PATH}/hwp/memory/lib/utils/ VPATH += ${CEN_PROCEDURES_PATH}/hwp/initfiles VPATH += $(if $(CONFIG_AXONE),${EXP_PROCEDURES_PATH}/hwp/memory,) +VPATH += $(if $(CONFIG_AXONE),${GEM_PROCEDURES_PATH}/hwp/memory,) VPATH += $(if $(CONFIG_AXONE),${OCMB_PROCEDURES_PATH}/hwp/initfiles/,) diff --git a/src/usr/isteps/istep14/call_host_mpipl_service.C b/src/usr/isteps/istep14/call_host_mpipl_service.C index d8bdaa5af..bab3ace62 100644 --- a/src/usr/isteps/istep14/call_host_mpipl_service.C +++ b/src/usr/isteps/istep14/call_host_mpipl_service.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -44,7 +44,6 @@ #include <vfs/vfs.H> #include <dump/dumpif.H> -#include <config.h> #ifdef CONFIG_DRTM #include <secureboot/drtm.H> @@ -158,10 +157,10 @@ void* call_host_mpipl_service (void *io_pArgs) do { - // In non-FSP based system SBE collects architected register + // In OPAL based system SBE collects architected register // data. Copy architected register data from Reserved Memory // to hypervisor memory. - if ( !INITSERVICE::spBaseServicesEnabled() ) + if( TARGETING::is_sapphire_load() ) { l_err = DUMP::copyArchitectedRegs(); if (l_err) diff --git a/src/usr/isteps/istep14/call_mss_memdiag.C b/src/usr/isteps/istep14/call_mss_memdiag.C index 38736d2c7..4c4c6b5b2 100644 --- a/src/usr/isteps/istep14/call_mss_memdiag.C +++ b/src/usr/isteps/istep14/call_mss_memdiag.C @@ -33,14 +33,21 @@ #include <util/misc.H> #include <plat_hwp_invoker.H> // for FAPI_INVOKE_HWP -#include <lib/shared/nimbus_defaults.H> // Needed before memdiags_fir.H -#include <lib/fir/memdiags_fir.H> // for mss::unmask::after_memdiags +#include <lib/shared/nimbus_defaults.H> // Needed before unmask.H +#include <lib/fir/unmask.H> // for mss::unmask::after_memdiags #include <lib/mc/port.H> // for mss::reset_reorder_queue_settings #if defined(CONFIG_IPLTIME_CHECKSTOP_ANALYSIS) && !defined(__HOSTBOOT_RUNTIME) #include <isteps/pm/occCheckstop.H> #endif +// TODO RTC:245219 +// use PRD's version of memdiags instead of this cronus verison once its working +#ifdef CONFIG_AXONE +#include <exp_mss_memdiag.H> +#include <chipids.H> // for EXPLORER ID +#endif + using namespace ISTEP; using namespace ISTEP_ERROR; using namespace ERRORLOG; @@ -161,6 +168,37 @@ void* call_mss_memdiag (void* io_pArgs) // No need to unmask or turn off FIFO. That is already contained // within the other Centaur HWPs. } +#ifdef CONFIG_AXONE + else if (MODEL_AXONE == procType ) + { + // no need to run in simics + if ( Util::isSimicsRunning() == false ) + { + // TODO RTC:245219 + // use PRD's version of memdiags instead of this cronus verison once its working + TargetHandleList trgtList; getAllChips( trgtList, TYPE_OCMB_CHIP ); + for (const auto & l_ocmb_target : trgtList) + { + uint32_t chipId = l_ocmb_target->getAttr< TARGETING::ATTR_CHIP_ID>(); + // Only call memdiags on Explorer cards, it breaks when you run on Gemini + if (chipId == POWER_CHIPID::EXPLORER_16) + { + fapi2::Target <fapi2::TARGET_TYPE_OCMB_CHIP> l_fapi_ocmb_target(l_ocmb_target); + // Start Memory Diagnostics. + FAPI_INVOKE_HWP( errl, exp_mss_memdiag, l_fapi_ocmb_target ); + if ( nullptr != errl ) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "exp_mss_memdiag (0x%08x) " + "failed", get_huid(l_ocmb_target) ); + break; + } + } + } + } + + } +#endif } while (0); diff --git a/src/usr/isteps/istep14/call_mss_power_cleanup.C b/src/usr/isteps/istep14/call_mss_power_cleanup.C index 3ca963678..524d2a536 100644 --- a/src/usr/isteps/istep14/call_mss_power_cleanup.C +++ b/src/usr/isteps/istep14/call_mss_power_cleanup.C @@ -129,9 +129,10 @@ void* call_mss_power_cleanup (void *io_pArgs) } } - // Run the nvdimm management function if the list is not empty + // Run the nvdimm management functions if the list is not empty if (!l_nvdimmTargetList.empty()){ NVDIMM::nvdimm_restore(l_nvdimmTargetList); + NVDIMM::nvdimm_encrypt_enable(l_nvdimmTargetList); } } #endif diff --git a/src/usr/isteps/istep14/call_mss_thermal_init.C b/src/usr/isteps/istep14/call_mss_thermal_init.C index 8e00df762..c11731e1d 100644 --- a/src/usr/isteps/istep14/call_mss_thermal_init.C +++ b/src/usr/isteps/istep14/call_mss_thermal_init.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -37,10 +37,16 @@ #include <config.h> #include <fapi2.H> #include <fapi2/plat_hwp_invoker.H> -#include <p9c_mss_thermal_init.H> -#include <p9_mss_thermal_init.H> -#include <p9_throttle_sync.H> +#ifdef CONFIG_AXONE + #include <exp_mss_thermal_init.H> + #include <chipids.H> // for EXPLORER ID + #include <p9a_throttle_sync.H> +#else + #include <p9c_mss_thermal_init.H> + #include <p9_mss_thermal_init.H> + #include <p9_throttle_sync.H> +#endif using namespace ISTEP; using namespace ISTEP_ERROR; @@ -49,43 +55,79 @@ using namespace TARGETING; namespace ISTEP_14 { +void nimbus_call_mss_thermal_init(IStepError & io_istepError); +void cumulus_call_mss_thermal_init(IStepError & io_istepError); +void axone_call_mss_thermal_init(IStepError & io_istepError); +void run_proc_throttle_sync(IStepError & io_istepError); + void* call_mss_thermal_init (void *io_pArgs) { IStepError l_StepError; + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_thermal_init entry"); + + auto l_procModel = TARGETING::targetService().getProcessorModel(); + switch (l_procModel) + { + case TARGETING::MODEL_CUMULUS: + cumulus_call_mss_thermal_init(l_StepError); + break; + case TARGETING::MODEL_AXONE: + axone_call_mss_thermal_init(l_StepError); + break; + case TARGETING::MODEL_NIMBUS: + nimbus_call_mss_thermal_init(l_StepError); + break; + default: + assert(0, "call_mss_thermal_init: Unsupported model type 0x%04X", + l_procModel); + break; + } + + // This should run whether or not mss_thermal_init worked + run_proc_throttle_sync(l_StepError); + + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_thermal_init exit"); + + // end task, returning any errorlogs to IStepDisp + return l_StepError.getErrorHandle(); +} + +#ifndef CONFIG_AXONE +void nimbus_call_mss_thermal_init(IStepError & io_istepError) +{ errlHndl_t l_errl = nullptr; - // -- Cumulus only --- - // Get all Centaur targets - TARGETING::TargetHandleList l_memBufTargetList; - getAllChips(l_memBufTargetList, TYPE_MEMBUF); + // -- Nimbus only --- + // Get all MCS targets + TARGETING::TargetHandleList l_mcsTargetList; + getAllChiplets(l_mcsTargetList, TYPE_MCS); // -------------------------------------------------------------------- - // run mss_thermal_init on all functional Centaur chips + // run mss_thermal_init on all functional MCS chiplets // -------------------------------------------------------------------- - for (auto l_pCentaur : l_memBufTargetList) + for (const auto & l_pMcs : l_mcsTargetList) { - fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP> l_fapi_pCentaur - (l_pCentaur); + fapi2::Target<fapi2::TARGET_TYPE_MCS> l_fapi_pMcs(l_pMcs); // Current run on target TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "Running call_mss_thermal_init HWP on " - "target HUID %.8X", TARGETING::get_huid(l_pCentaur)); + "Running p9_mss_thermal_init HWP on target HUID %.8X", + TARGETING::get_huid(l_pMcs) ); - FAPI_INVOKE_HWP( l_errl, p9c_mss_thermal_init, l_fapi_pCentaur ); + FAPI_INVOKE_HWP( l_errl, p9_mss_thermal_init, l_fapi_pMcs ); if ( l_errl ) { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X: p9c_mss_thermal_init HWP returns error", + "ERROR 0x%.8X: p9_mss_thermal_init HWP returns error", l_errl->reasonCode()); // capture the target data in the elog - ErrlUserDetailsTarget(l_pCentaur).addToLog( l_errl ); + ErrlUserDetailsTarget(l_pMcs).addToLog( l_errl ); // Create IStep error log and cross reference // to error that occurred - l_StepError.addErrorDetails( l_errl ); + io_istepError.addErrorDetails( l_errl ); // Commit Error errlCommit( l_errl, HWPF_COMP_ID ); @@ -94,43 +136,50 @@ void* call_mss_thermal_init (void *io_pArgs) } else { - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : p9c_mss_thermal_init HWP( )" ); + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : p9_mss_thermal_init HWP() on 0x%.8X MCS", + TARGETING::get_huid(l_pMcs) ); } - } + } // end MCS loop - // -- Nimbus only --- - // Get all MCS targets - TARGETING::TargetHandleList l_mcsTargetList; - getAllChiplets(l_mcsTargetList, TYPE_MCS); +} + +void cumulus_call_mss_thermal_init(IStepError & io_istepError) +{ + errlHndl_t l_errl = nullptr; + + // -- Cumulus only --- + // Get all Centaur targets + TARGETING::TargetHandleList l_memBufTargetList; + getAllChips(l_memBufTargetList, TYPE_MEMBUF); // -------------------------------------------------------------------- - // run mss_thermal_init on all functional MCS chiplets + // run mss_thermal_init on all functional Centaur chips // -------------------------------------------------------------------- - for (auto l_pMcs : l_mcsTargetList) + for (const auto & l_pCentaur : l_memBufTargetList) { - fapi2::Target<fapi2::TARGET_TYPE_MCS> l_fapi_pMcs - (l_pMcs); + fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP> l_fapi_pCentaur + (l_pCentaur); // Current run on target TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "Running call_mss_thermal_init HWP on " - "target HUID %.8X", TARGETING::get_huid(l_pMcs)); + "Running p9c_mss_thermal_init HWP on target HUID %.8X", + TARGETING::get_huid(l_pCentaur) ); - FAPI_INVOKE_HWP( l_errl, p9_mss_thermal_init, l_fapi_pMcs ); + FAPI_INVOKE_HWP( l_errl, p9c_mss_thermal_init, l_fapi_pCentaur ); if ( l_errl ) { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X: p9_mss_thermal_init HWP returns error", + "ERROR 0x%.8X: p9c_mss_thermal_init HWP returns error", l_errl->reasonCode()); // capture the target data in the elog - ErrlUserDetailsTarget(l_pMcs).addToLog( l_errl ); + ErrlUserDetailsTarget(l_pCentaur).addToLog( l_errl ); // Create IStep error log and cross reference // to error that occurred - l_StepError.addErrorDetails( l_errl ); + io_istepError.addErrorDetails( l_errl ); // Commit Error errlCommit( l_errl, HWPF_COMP_ID ); @@ -139,70 +188,153 @@ void* call_mss_thermal_init (void *io_pArgs) } else { - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : p9_mss_thermal_init HWP( )" ); + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : p9c_mss_thermal_init HWP( ) on 0x%.8X target", + TARGETING::get_huid(l_pCentaur) ); } - } + } // end MEMBUF loop +} +#else +void nimbus_call_mss_thermal_init(IStepError & io_istepError) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'p9_mss_thermal_init' but Nimbus code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); +} - do +void cumulus_call_mss_thermal_init(IStepError & io_istepError) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'p9c_mss_thermal_init' but Cumulus code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); +} +#endif + +#ifdef CONFIG_AXONE +void axone_call_mss_thermal_init(IStepError & io_istepError) +{ + errlHndl_t l_err = nullptr; + + // Get all OCMB targets + TARGETING::TargetHandleList l_ocmbTargetList; + getAllChips(l_ocmbTargetList, TYPE_OCMB_CHIP); + + for (const auto & l_ocmb_target : l_ocmbTargetList) { - // Run proc throttle sync - // Get all functional proc chip targets - //Use targeting code to get a list of all processors - TARGETING::TargetHandleList l_procChips; - getAllChips( l_procChips, TARGETING::TYPE_PROC ); + // check EXPLORER first as this is most likely the configuration + uint32_t chipId = l_ocmb_target->getAttr< TARGETING::ATTR_CHIP_ID>(); + if (chipId == POWER_CHIPID::EXPLORER_16) + { + fapi2::Target <fapi2::TARGET_TYPE_OCMB_CHIP> l_fapi_ocmb_target + (l_ocmb_target); + + // Dump current run on target + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running exp_mss_thermal_init HWP on target HUID %.8X", + TARGETING::get_huid(l_ocmb_target)); - for (const auto & l_procChip: l_procChips) + // call the HWP with each fapi2::Target + FAPI_INVOKE_HWP(l_err, exp_mss_thermal_init, l_fapi_ocmb_target); + } + else { - //Convert the TARGETING::Target into a fapi2::Target by passing - //l_procChip into the fapi2::Target constructor - fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> - l_fapi2CpuTarget((l_procChip)); + // Gemini, NOOP + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Skipping thermal_init HWP on axone target HUID 0x%.8X, chipId 0x%.4X", + TARGETING::get_huid(l_ocmb_target), chipId ); + } + + if (l_err) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X: exp_mss_thermal_init HWP returns error", + l_err->reasonCode()); + // capture the target data in the elog + ErrlUserDetailsTarget(l_ocmb_target).addToLog(l_err); + + // Create IStep error log and cross reference to error that + // occurred + io_istepError.addErrorDetails( l_err ); + + // Commit Error + errlCommit( l_err, HWPF_COMP_ID ); + + break; + } + else if (chipId == POWER_CHIPID::EXPLORER_16) + { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "Running p9_throttle_sync HWP on " - "target HUID %.8X", TARGETING::get_huid(l_procChip)); - - // Call p9_throttle_sync - FAPI_INVOKE_HWP( l_errl, p9_throttle_sync, l_fapi2CpuTarget ); - - if (l_errl) - { - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X: p9_throttle_sync HWP returns error", - l_errl->reasonCode()); - - // Capture the target data in the elog - ErrlUserDetailsTarget(l_procChip).addToLog(l_errl); - - // Create IStep error log and cross reference - // to error that occurred - l_StepError.addErrorDetails( l_errl ); - - // Commit Error - errlCommit( l_errl, HWPF_COMP_ID ); - - break; - } - else - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : p9_throttle_sync HWP( )" ); - } + "SUCCESS running exp_mss_thermal_init HWP on target HUID %.8X", + TARGETING::get_huid(l_ocmb_target)); } + } // end OCMB loop +} +#else +void axone_call_mss_thermal_init(IStepError & io_istepError) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'exp_mss_thermal_init' but Axone code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); +} +#endif - } while (0); +void run_proc_throttle_sync(IStepError & io_istepError) +{ + errlHndl_t l_errl = nullptr; + + // Run proc throttle sync + // Get all functional proc chip targets + // Use targeting code to get a list of all processors + TARGETING::TargetHandleList l_procChips; + getAllChips( l_procChips, TARGETING::TYPE_PROC ); - if(l_StepError.isNull()) + for (const auto & l_procChip: l_procChips) { + //Convert the TARGETING::Target into a fapi2::Target by passing + //l_procChip into the fapi2::Target constructor + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> + l_fapi2CpuTarget((l_procChip)); + + // Call p9_throttle_sync +#ifndef CONFIG_AXONE TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : call_mss_thermal_init" ); - } + "Running p9_throttle_sync HWP on target HUID %.8X", + TARGETING::get_huid(l_procChip) ); + FAPI_INVOKE_HWP( l_errl, p9_throttle_sync, l_fapi2CpuTarget ); +#else + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running p9a_throttle_sync HWP on target HUID %.8X", + TARGETING::get_huid(l_procChip) ); + FAPI_INVOKE_HWP( l_errl, p9a_throttle_sync, l_fapi2CpuTarget ); +#endif + if (l_errl) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X: p9_throttle_sync HWP returns error", + l_errl->reasonCode()); - // end task, returning any errorlogs to IStepDisp - return l_StepError.getErrorHandle(); + // Capture the target data in the elog + ErrlUserDetailsTarget(l_procChip).addToLog(l_errl); + + // Create IStep error log and cross reference + // to error that occurred + io_istepError.addErrorDetails( l_errl ); + + // Commit Error + errlCommit( l_errl, HWPF_COMP_ID ); + + break; + } + else + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : p9_throttle_sync HWP on 0x%.8X processor", + TARGETING::get_huid(l_procChip) ); + } + } } }; diff --git a/src/usr/isteps/istep14/call_proc_exit_cache_contained.C b/src/usr/isteps/istep14/call_proc_exit_cache_contained.C index 897bb58ac..b118401f6 100644 --- a/src/usr/isteps/istep14/call_proc_exit_cache_contained.C +++ b/src/usr/isteps/istep14/call_proc_exit_cache_contained.C @@ -47,7 +47,6 @@ #include <arch/pirformat.H> #include <isteps/hwpf_reasoncodes.H> #include <devicefw/userif.H> -#include <config.h> #include <util/misc.H> #include <hwas/common/hwas.H> #include <sys/misc.h> @@ -81,7 +80,7 @@ void* call_proc_exit_cache_contained (void *io_pArgs) "call_proc_exit_cache_contained entry" ); errlHndl_t l_errl = nullptr; -#ifdef CONFIG_SECUREBOOT +#if (defined CONFIG_SECUREBOOT && ! defined CONFIG_AXONE) if(SECUREBOOT::enabled()) { SECUREBOOT::CENTAUR_SECURITY::ScomCache& centaurCache = @@ -537,7 +536,7 @@ void* call_proc_exit_cache_contained (void *io_pArgs) errlCommit( l_errl, HWPF_COMP_ID ); } -#ifdef CONFIG_SECUREBOOT +#if (defined CONFIG_SECUREBOOT && ! defined CONFIG_AXONE) // Unload the MEMD section that was loaded at the beginning of step11 l_errl = unloadSecureSection(PNOR::MEMD); if (l_errl) diff --git a/src/usr/isteps/istep14/call_proc_setup_bars.C b/src/usr/isteps/istep14/call_proc_setup_bars.C index 25ed067d2..9cb0f402a 100644 --- a/src/usr/isteps/istep14/call_proc_setup_bars.C +++ b/src/usr/isteps/istep14/call_proc_setup_bars.C @@ -22,7 +22,6 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -#include <config.h> #include <errl/errlentry.H> #include <isteps/hwpisteperror.H> #include <initservice/isteps_trace.H> diff --git a/src/usr/isteps/istep14/makefile b/src/usr/isteps/istep14/makefile index 47c6c15e6..9aaa19c97 100644 --- a/src/usr/isteps/istep14/makefile +++ b/src/usr/isteps/istep14/makefile @@ -26,18 +26,22 @@ ROOTPATH = ../../../.. MODULE = istep14 PROCEDURE_PATH = ${ROOTPATH}/src/import/chips/p9/procedures +AXONE_PROCEDURE_PATH = ${ROOTPATH}/src/import/chips/p9a/procedures CEN_PROC_PATH = ${ROOTPATH}/src/import/chips/centaur/procedures EXP_COMMON_PATH = ${ROOTPATH}/src/import/chips/ocmb/explorer/common +EXPLORER_HWP_PATH = ${ROOTPATH}/src/import/chips/ocmb/explorer/procedures/hwp/memory/ #Add all the extra include paths EXTRAINCDIR += ${ROOTPATH}/obj/genfiles/ +EXTRAINCDIR += ${ROOTPATH}/obj/genfiles/generic/memory/lib +EXTRAINCDIR += ${ROOTPATH}/obj/genfiles/chips/ocmb/explorer/procedures/hwp/memory/lib/ +EXTRAINCDIR += ${ROOTPATH}/src/import/ EXTRAINCDIR += ${ROOTPATH}/src/import/hwpf/fapi2/include EXTRAINCDIR += ${ROOTPATH}/src/include/usr/fapi2 EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/utils EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/utils/imageProcs EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/utils/imageProcs EXTRAINCDIR += ${PROCEDURE_PATH}/hwp/nest -EXTRAINCDIR += ${ROOTPATH}/src/import/ EXTRAINCDIR += ${PROCEDURE_PATH}/hwp/memory EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/common/include/ EXTRAINCDIR += ${PROCEDURE_PATH}/hwp/memory/lib/eff_config/ @@ -50,6 +54,9 @@ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/centaur/common/include/ EXTRAINCDIR += ${PROCEDURE_PATH}/hwp/memory/lib/dimm/ddr4/ EXTRAINCDIR += ${EXP_COMMON_PATH}/include/ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/explorer/procedures/hwp/memory +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/utils +EXTRAINCDIR += ${AXONE_PROCEDURE_PATH}/hwp/memory/ +EXTRAINCDIR += ${EXPLORER_HWP_PATH} OBJS += call_mss_memdiag.o OBJS += call_mss_thermal_init.o @@ -92,14 +99,24 @@ OBJS += p9_revert_sbe_mcs_setup.o # include ${PROCEDURE_PATH}/hwp/memory/p9_mss_thermal_init.mk # include ${CEN_PROC_PATH}/hwp/memory/p9c_mss_thermal_init.mk # include ${CEN_PROC_PATH}/hwp/memory/p9c_mss_unmask_errors.mk -include ${PROCEDURE_PATH}/hwp/nest/p9_throttle_sync.mk + include ${PROCEDURE_PATH}/hwp/memory/p9_mss_power_cleanup.mk -include ${ROOTPATH}/config.mk -VPATH += ${PROCEDURE_PATH}/hwp/nest/ ${PROCEDURE_PATH}/hwp/memory/ +VPATH += ${PROCEDURE_PATH}/hwp/nest/ +VPATH += ${PROCEDURE_PATH}/hwp/memory/ VPATH += ${PROCEDURE_PATH}/hwp/memory/lib/eff_config/ VPATH += ${PROCEDURE_PATH}/hwp/memory/lib/utils/ VPATH += ${PROCEDURE_PATH}/hwp/memory/lib/mcbist/ VPATH += ${PROCEDURE_PATH}/hwp/memory/lib/dimm/ VPATH += ${CEN_PROC_PATH}/hwp/memory/ VPATH += ${PROCEDURE_PATH}/hwp/memory/lib/dimm/ddr4/ + +# Axone vs non-Axone specific HWP +VPATH += $(if $(CONFIG_AXONE),${EXPLORER_HWP_PATH},) +OBJS += $(if $(CONFIG_AXONE),exp_mss_thermal_init.o,) +# TODO RTC:245219 +# use PRD's version of memdiags instead of this cronus verison once its working +OBJS += $(if $(CONFIG_AXONE),exp_mss_memdiag.o,) + +include ${ROOTPATH}/config.mk + diff --git a/src/usr/isteps/istep15/host_build_stop_image.C b/src/usr/isteps/istep15/host_build_stop_image.C index 26e3677f4..6bc755314 100644 --- a/src/usr/isteps/istep15/host_build_stop_image.C +++ b/src/usr/isteps/istep15/host_build_stop_image.C @@ -445,7 +445,17 @@ void* host_build_stop_image (void *io_pArgs) //If running Sapphire need to place this at the top of memory instead if(is_sapphire_load()) { - l_memBase = get_top_homer_mem_addr(); + //Because the way P9N/P9C are init'ed for backwards HB / SBE + //compatibility (SMF never enabled -- thus unsecure homer to + //secure homer sc2 (system call to Ultravisor) doesn't work) during + //istep 15 need to "trick" hostboot into placing HOMER into normal + //memory @HRMOR (instead of secure SMF memory). When HB goes + //through istep 16 it will enter UV mode if SMF is enabled, and then + //when PM complex is restarted in istep 21, HOMER is moved to right + //spot. No movement of HOME oocurs in non-SMF mode; HOMER lands in + //non-secure memory. + + l_memBase = get_top_mem_addr(); assert (l_memBase != 0, "host_build_stop_image: Top of memory was 0!"); @@ -502,9 +512,6 @@ void* host_build_stop_image (void *io_pArgs) "Found %d functional procs in system", l_procChips.size() ); - auto l_unsecureHomerSize = - l_sys->getAttr<TARGETING::ATTR_UNSECURE_HOMER_SIZE>(); - for (const auto & l_procChip: l_procChips) { do { @@ -563,22 +570,12 @@ void* host_build_stop_image (void *io_pArgs) break; } - if(SECUREBOOT::SMF::isSmfEnabled()) - { - // In SMF mode, unsecure HOMER goes to the top of unsecure - // memory (2MB aligned); we need to subtract the size of the - // unsecure HOMER and align the resulting address to arrive - // at the correct location. - uint64_t l_unsecureHomerAddr = ALIGN_DOWN_X( - ISTEP::get_top_mem_addr() - - MAX_UNSECURE_HOMER_SIZE, - 2 * MEGABYTE); - l_procChip->setAttr<TARGETING::ATTR_UNSECURE_HOMER_ADDRESS> - (l_unsecureHomerAddr); - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "host_build_stop_image: unsecure HOMER addr = 0x%.16llX", - l_unsecureHomerAddr); - } + //Set unsecure HOMER address to real HOMER, as this + //will allow SMF inits to become active (results in + //URMOR == HRMOR in non SMF memory). The processor self-restore + //code is 2MB into HOMER, so point the unsecure HOMER there. + l_procChip->setAttr<TARGETING::ATTR_UNSECURE_HOMER_ADDRESS> + (l_procRealMemAddr + (2 * MEGABYTE)); //Call p9_hcode_image_build.C HWP FAPI_INVOKE_HWP( l_errl, @@ -608,58 +605,6 @@ void* host_build_stop_image (void *io_pArgs) break; } - // We now need to copy the data that was put in l_temp_buffer2 - // by the p9_hcode_image_build procedure into the unsecure - // HOMER memory - if(SECUREBOOT::SMF::isSmfEnabled()) - { - auto l_unsecureHomerAddr = l_procChip-> - getAttr<TARGETING::ATTR_UNSECURE_HOMER_ADDRESS>(); - - - assert(l_unsecureHomerSize <= MAX_RING_BUF_SIZE, - "host_build_stop_image: unsecure HOMER is bigger than the output buffer"); - assert(l_unsecureHomerSize <= MAX_UNSECURE_HOMER_SIZE, - "host_build_stop_image: the size of unsecure HOMER is more than 0x%x", MAX_UNSECURE_HOMER_SIZE); - assert(l_unsecureHomerAddr, - "host_build_stop_image: the unsecure HOMER addr is 0"); - - void* l_unsecureHomerVAddr = mm_block_map( - reinterpret_cast<void*>(l_unsecureHomerAddr), - l_unsecureHomerSize); - assert(l_unsecureHomerVAddr, - "host_build_stop_image: could not map unsecure HOMER phys addr"); - memcpy(l_unsecureHomerVAddr, - l_temp_buffer2, - l_unsecureHomerSize); - int l_rc = mm_block_unmap(l_unsecureHomerVAddr); - if(l_rc) - { - /*@ - * @errortype - * @reasoncode ISTEP::RC_MM_UNMAP_FAILED - * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE - * @moduleid ISTEP::MOD_BUILD_HCODE_IMAGES - * @userdata1 Unsecure HOMER addr - * @userdata2 RC from mm_block_unmap - * @devdesc Could not unmap unsecure HOMER's virtual - * address - * @custdesc A problem occurred during the IPL of the - * system - */ - l_errl = new ERRORLOG::ErrlEntry( - ERRORLOG::ERRL_SEV_UNRECOVERABLE, - ISTEP::MOD_BUILD_HCODE_IMAGES, - ISTEP::RC_MM_UNMAP_FAILED, - reinterpret_cast<uint64_t>( - l_unsecureHomerVAddr), - l_rc, - ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); - l_errl->collectTrace(ISTEP_COMP_NAME); - break; - } - } - l_errl = applyHcodeGenCpuRegs( l_procChip, l_pImageOut, l_sizeImageOut ); diff --git a/src/usr/isteps/istep15/host_establish_ex_chiplet.C b/src/usr/isteps/istep15/host_establish_ex_chiplet.C index be5640167..1d89bfa80 100644 --- a/src/usr/isteps/istep15/host_establish_ex_chiplet.C +++ b/src/usr/isteps/istep15/host_establish_ex_chiplet.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -53,7 +53,6 @@ void* host_establish_ex_chiplet (void *io_pArgs) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "host_establish_ex_chiplet entry" ); ISTEP_ERROR::IStepError l_StepError; - #ifndef CONFIG_AXONE_BRING_UP errlHndl_t l_errl = NULL; do { //Use targeting code to get a list of all processors @@ -64,6 +63,7 @@ void* host_establish_ex_chiplet (void *io_pArgs) { const fapi2::Target<TARGET_TYPE_PROC_CHIP> l_fapi_cpu_target(l_procChip); + // call p9_update_ec_eq_state.C HWP FAPI_INVOKE_HWP( l_errl, p9_update_ec_eq_state, @@ -78,7 +78,6 @@ void* host_establish_ex_chiplet (void *io_pArgs) } } }while(0); - #endif // end task, returning any errorlogs to IStepDisp TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "host_establish_ex_chiplet exit" ); diff --git a/src/usr/isteps/istep15/host_start_stop_engine.C b/src/usr/isteps/istep15/host_start_stop_engine.C index 27580947d..b89804fe3 100644 --- a/src/usr/isteps/istep15/host_start_stop_engine.C +++ b/src/usr/isteps/istep15/host_start_stop_engine.C @@ -55,7 +55,7 @@ void* host_start_stop_engine (void *io_pArgs) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_host_start_stop_engine entry" ); ISTEP_ERROR::IStepError l_StepError; - errlHndl_t l_errl = NULL; + errlHndl_t l_errl __attribute__((unused)) = NULL; // Cast to void just to get around unused var warning if #ifdef's dont work // out to actually use the l_errl variable @@ -79,11 +79,9 @@ void* host_start_stop_engine (void *io_pArgs) } #endif -// Skip initializing the PM complex in axone simics for now -#ifndef CONFIG_AXONE_BRING_UP //Use targeting code to get a list of all processors TARGETING::TargetHandleList l_procChips; - getAllChips( l_procChips, TARGETING::TYPE_PROC ); + getAllChips( l_procChips, TARGETING::TYPE_PROC ); for (const auto & l_procChip: l_procChips) { @@ -92,6 +90,10 @@ void* host_start_stop_engine (void *io_pArgs) fapi2::Target<TARGET_TYPE_PROC_CHIP>l_fapi2CpuTarget( (l_procChip)); + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Calling p9_pm_stop_gpe_init for 0x%.8X target", + TARGETING::get_huid(l_procChip) ); + //call p9_pm_stop_gpe_init.C HWP FAPI_INVOKE_HWP(l_errl, p9_pm_stop_gpe_init, @@ -105,7 +107,6 @@ void* host_start_stop_engine (void *io_pArgs) TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "host_start_stop_engine:: failed on proc with HUID : %d",TARGETING::get_huid(l_procChip) ); } } -#endif #ifdef CONFIG_IPLTIME_CHECKSTOP_ANALYSIS // Starting SGPE in istep15.4 causes OIMR0 register to be improperly diff --git a/src/usr/isteps/istep15/proc_set_pba_homer_bar.C b/src/usr/isteps/istep15/proc_set_pba_homer_bar.C index 0173b1a15..5c02af9df 100644 --- a/src/usr/isteps/istep15/proc_set_pba_homer_bar.C +++ b/src/usr/isteps/istep15/proc_set_pba_homer_bar.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -46,10 +46,17 @@ #include <return_code.H> #include <p9_pm_set_homer_bar.H> +#include <secureboot/smf_utils.H> +#include <secureboot/smf.H> +#include <isteps/mem_utils.H> +#include <util/align.H> + + //Namespaces using namespace ERRORLOG; using namespace TARGETING; using namespace fapi2; +using namespace ISTEP; namespace ISTEP_15 { @@ -62,12 +69,56 @@ void* proc_set_pba_homer_bar (void *io_pArgs) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_set_pba_homer_bar entry" ); ISTEP_ERROR::IStepError l_StepError; - errlHndl_t l_errl = NULL; + errlHndl_t l_errl = nullptr; TARGETING::TargetHandleList l_procChips; + uint64_t l_smfBase = 0x0; + uint64_t l_unsecureHomerAddr = get_top_mem_addr(); + + + //Determine top-level system target + TARGETING::Target* l_sys = nullptr; + TARGETING::targetService().getTopLevelTarget(l_sys); + assert(l_sys != nullptr, "Top level target was nullptr!"); + + //Because the way P9N/P9C are init'ed for backwards HB / SBE + //compatibility (SMF never enabled -- thus unsecure homer to + //secure homer sc2 (system call to Ultravisor) doesn't work) during istep 15 + //need to "trick" hostboot into placing HOMER into normal memory @ + //HRMOR. When HB goes through istep 16 it will enter UV + //mode if SMF is enabled, and then when PM complex is restarted + //in istep 21, HOMER is moved to right spot + if(SECUREBOOT::SMF::isSmfEnabled()) + { + l_smfBase = get_top_homer_mem_addr(); + assert(l_smfBase != 0, + "proc_set_pba_homer_bar: Top of SMF memory was 0!"); + if(is_sapphire_load()) + { + l_smfBase -= VMM_ALL_HOMER_OCC_MEMORY_SIZE; + // Unsecure HOMER address is used in istep21 to place the + // unsecure part of the HOMER image outside of SMF memory. + // Unsecure HOMER goes to the top of unsecure + // memory (2MB aligned); we need to subtract the size of the + // unsecure HOMER and align the resulting address to arrive + // at the correct location. + l_unsecureHomerAddr = ALIGN_DOWN_X(l_unsecureHomerAddr - + MAX_UNSECURE_HOMER_SIZE, + 2 * MEGABYTE); + } + assert(l_unsecureHomerAddr != 0, + "proc_set_pba_homer_bar: Unsecure HOMER addr was 0!"); + + //Since we have the HOMER location defined, set the + // OCC common attribute to be used later by pm code + l_sys->setAttr<TARGETING::ATTR_OCC_COMMON_AREA_PHYS_ADDR> + (l_smfBase + VMM_HOMER_REGION_SIZE); + } //Use targeting code to get a list of all processors getAllChips( l_procChips, TARGETING::TYPE_PROC ); + + //Loop through all of the procs and call the HWP on each one for (const auto & l_procChip: l_procChips) { @@ -92,6 +143,29 @@ void* proc_set_pba_homer_bar (void *io_pArgs) l_StepError.addErrorDetails( l_errl ); errlCommit( l_errl, HWPF_COMP_ID ); } + + if(SECUREBOOT::SMF::isSmfEnabled()) + { + //Set correct SMF value used later in istep 21 + // calculate size and location of the HCODE output buffer + uint32_t l_procNum = + l_procChip->getAttr<TARGETING::ATTR_POSITION>(); + uint64_t l_procOffsetAddr = l_procNum * VMM_HOMER_INSTANCE_SIZE; + + l_procChip->setAttr<TARGETING::ATTR_HOMER_PHYS_ADDR> + (l_smfBase + l_procOffsetAddr); + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "Update %.8X HOMER from 0x%.16llX to 0x%.16llX for SMF", + TARGETING::get_huid(l_procChip), homerAddr, + (l_smfBase + l_procOffsetAddr)); + + l_procChip->setAttr<TARGETING::ATTR_UNSECURE_HOMER_ADDRESS> + (l_unsecureHomerAddr); + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "proc_set_pba_homer_bar: unsecure HOMER addr = 0x%.16llX", + l_unsecureHomerAddr); + } + } TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_set_pba_homer_bar exit" ); diff --git a/src/usr/isteps/istep16/call_host_activate_master.C b/src/usr/isteps/istep16/call_host_activate_master.C index ecbf78325..63a882886 100644 --- a/src/usr/isteps/istep16/call_host_activate_master.C +++ b/src/usr/isteps/istep16/call_host_activate_master.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -204,7 +204,8 @@ void* call_host_activate_master (void *io_pArgs) TARGETING::get_huid(l_proc_target)); //In the future possibly move default "waitTime" value to SBEIO code - uint64_t waitTime = 1000000; // bump the wait time to 1 sec + uint64_t waitTime = 10500; // wait time 10.5 sec, anything larger than 10737 ms can cause + // overflow on SBE side of the tiemout calculations l_errl = SBEIO::startDeadmanLoop(waitTime); if ( l_errl ) diff --git a/src/usr/isteps/istep16/call_host_activate_slave_cores.C b/src/usr/isteps/istep16/call_host_activate_slave_cores.C index c5f941e8f..1abc215ed 100644 --- a/src/usr/isteps/istep16/call_host_activate_slave_cores.C +++ b/src/usr/isteps/istep16/call_host_activate_slave_cores.C @@ -293,7 +293,7 @@ void* call_host_activate_slave_cores (void *io_pArgs) // Callout and gard core that failed to wake up. l_errl->addHwCallout(*l_core, HWAS::SRCI_PRIORITY_HIGH, - HWAS::DECONFIG, + HWAS::DELAYED_DECONFIG, HWAS::GARD_Predictive); // Could be an interrupt issue diff --git a/src/usr/isteps/istep16/call_host_secure_rng.C b/src/usr/isteps/istep16/call_host_secure_rng.C index 9ca7e0f45..5df147559 100644 --- a/src/usr/isteps/istep16/call_host_secure_rng.C +++ b/src/usr/isteps/istep16/call_host_secure_rng.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -58,7 +58,6 @@ #include <devicefw/userif.H> #include <vpd/mvpdenums.H> -#include <config.h> #include <fapi2/plat_hwp_invoker.H> #include <p9_rng_init_phase2.H> diff --git a/src/usr/isteps/istep16/call_mss_scrub.C b/src/usr/isteps/istep16/call_mss_scrub.C index e7727a7ee..0d4db2acd 100644 --- a/src/usr/isteps/istep16/call_mss_scrub.C +++ b/src/usr/isteps/istep16/call_mss_scrub.C @@ -32,7 +32,8 @@ #include <diag/prdf/prdfMain.H> #include <plat_hwp_invoker.H> // for FAPI_INVOKE_HWP -#include <lib/fir/memdiags_fir.H> // for mss::unmask::after_background_scrub +#include <lib/shared/nimbus_defaults.H> // Needed before unmask.H +#include <lib/fir/unmask.H> // for mss::unmask::after_background_scrub using namespace ERRORLOG; using namespace TARGETING; @@ -54,6 +55,7 @@ void* call_mss_scrub (void *io_pArgs) do { + if ( Util::isSimicsRunning() ) { // There are performance issues and some functional deficiencies @@ -71,11 +73,12 @@ void* call_mss_scrub (void *io_pArgs) // Determine which target type runs the maintenance commands. TARGETING::MODEL masterProcModel = masterProc->getAttr<ATTR_MODEL>(); - TARGETING::TYPE maintTrgtType; + TARGETING::TYPE maintTrgtType = TYPE_MBA; switch ( masterProcModel ) { case MODEL_CUMULUS: maintTrgtType = TYPE_MBA; break; case MODEL_NIMBUS: maintTrgtType = TYPE_MCBIST; break; + case MODEL_AXONE: maintTrgtType = TYPE_OCMB_CHIP; break; default: TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, ISTEP_FUNC "Master PROC model %d not supported", diff --git a/src/usr/isteps/istep18/establish_system_smp.C b/src/usr/isteps/istep18/establish_system_smp.C index 2a59046d1..241ab5384 100644 --- a/src/usr/isteps/istep18/establish_system_smp.C +++ b/src/usr/isteps/istep18/establish_system_smp.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2018 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -53,7 +53,6 @@ #include <istep_mbox_msgs.H> #include <vfs/vfs.H> -#include <config.h> // targeting support #include <targeting/common/commontargeting.H> @@ -674,6 +673,8 @@ void *host_sys_fab_iovalid_processing(void* io_ptr ) "returned err: plid=0x%X. Deleting err and continuing", err->plid()); err->collectTrace("ISTEPS_TRACE"); + // Let the caller know that an error occurred + io_pMsg->data[0] = err->plid(); errlCommit(err, SECURE_COMP_ID); } diff --git a/src/usr/isteps/istep18/smp_unfencing_inter_enclosure_abus_links.C b/src/usr/isteps/istep18/smp_unfencing_inter_enclosure_abus_links.C index 4e35e5a48..e21ce54c9 100644 --- a/src/usr/isteps/istep18/smp_unfencing_inter_enclosure_abus_links.C +++ b/src/usr/isteps/istep18/smp_unfencing_inter_enclosure_abus_links.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2018 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -56,7 +56,6 @@ #include <fapi2/plat_hwp_invoker.H> #include <isteps/hwpf_reasoncodes.H> #include <isteps/hwpisteperror.H> -#include <config.h> #include <vector> #include "smp_unfencing_inter_enclosure_abus_links.H" diff --git a/src/usr/isteps/istep20/call_host_load_payload.C b/src/usr/isteps/istep20/call_host_load_payload.C index 44e7672f4..5190649c9 100644 --- a/src/usr/isteps/istep20/call_host_load_payload.C +++ b/src/usr/isteps/istep20/call_host_load_payload.C @@ -38,7 +38,6 @@ #include <arch/ppc.H> #include <kernel/console.H> #include <xz/xz.h> -#include <config.h> using namespace ERRORLOG; @@ -121,7 +120,13 @@ void* call_host_load_payload (void *io_pArgs) // Load payload data in PHYP mode or in Sapphire mode if(is_sapphire_load() || is_phyp_load()) { - l_err = load_pnor_section( PNOR::PAYLOAD, payloadBase ); + PNOR::SectionId l_secID = PNOR::PAYLOAD; + if (is_phyp_load()) + { + l_secID = PNOR::BOOTKERNEL; + } + + l_err = load_pnor_section( l_secID, payloadBase ); if ( l_err ) { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, diff --git a/src/usr/isteps/istep21/call_host_runtime_setup.C b/src/usr/isteps/istep21/call_host_runtime_setup.C index 4a87ddefd..db0fc2d5f 100644 --- a/src/usr/isteps/istep21/call_host_runtime_setup.C +++ b/src/usr/isteps/istep21/call_host_runtime_setup.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2019 */ +/* Contributors Listed Below - COPYRIGHT 2015,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -23,7 +23,6 @@ /* */ /* IBM_PROLOG_END_TAG */ -#include <config.h> #include <errl/errlentry.H> #include <errl/errlmanager.H> #include <initservice/isteps_trace.H> @@ -68,8 +67,12 @@ #ifdef CONFIG_NVDIMM #include "call_nvdimm_update.H" +#include <isteps/nvdimm/nvdimm.H> #endif +#include <dump/dumpif.H> + + using namespace ERRORLOG; using namespace ISTEP; using namespace ISTEP_ERROR; @@ -290,8 +293,8 @@ errlHndl_t verifyAndMovePayload(void) break; } - // If in Secure Mode Verify PHYP at Temporary TCE-related Memory Location - if (SECUREBOOT::enabled() && is_phyp) + // If in Secure Mode Verify Payload at Temporary TCE-related Memory Location + if (SECUREBOOT::enabled()) { TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,"verifyAndMovePayload() " "Verifying PAYLOAD: physAddr=0x%.16llX, virtAddr=0x%.16llX", @@ -736,6 +739,19 @@ void* call_host_runtime_setup (void *io_pArgs) errlCommit(l_err, ISTEP_COMP_ID); pmStartSuccess = false; } + else + { +#ifdef CONFIG_NVDIMM + // Arm the nvdimms + // Only get here if is_sapphire_load and PM started and have NVDIMMs + TARGETING::TargetHandleList l_nvdimmTargetList; + NVDIMM::nvdimm_getNvdimmList(l_nvdimmTargetList); + if (l_nvdimmTargetList.size() != 0) + { + NVDIMM::nvdimmArm(l_nvdimmTargetList); + } +#endif + } #ifdef CONFIG_HTMGT // Report PM status to HTMGT @@ -767,7 +783,7 @@ void* call_host_runtime_setup (void *io_pArgs) uint8_t l_skip_fir_attr_reset = 1; // Since we are not leaving the PM complex alive, we will // explicitly put it into reset and clean up any memory - l_err = HBPM::resetPMAll(HBPM::RESET_AND_CLEAR_ATTRIBUTES, + l_err = HBPM::resetPMAll(HBPM::RESET_AND_CLEAR_ATTRIBUTES, l_skip_fir_attr_reset); if (l_err) { @@ -846,11 +862,20 @@ void* call_host_runtime_setup (void *io_pArgs) break; } } - + // Update the MDRT Count and PDA Table Entries from Attribute TargetService& l_targetService = targetService(); Target* l_sys = nullptr; l_targetService.getTopLevelTarget(l_sys); + + // Default captured data to 0s -- MPIPL if check fills in if + // valid + uint32_t threadRegSize = sizeof(DUMP::hostArchRegDataHdr)+ + (95 * sizeof(DUMP::hostArchRegDataEntry)); + uint8_t threadRegFormat = REG_DUMP_SBE_HB_STRUCT_VER; + uint64_t capThreadArrayAddr = 0; + uint64_t capThreadArraySize = 0; + if(l_sys->getAttr<ATTR_IS_MPIPL_HB>()) { uint32_t l_mdrtCount = @@ -862,25 +887,23 @@ void* call_host_runtime_setup (void *io_pArgs) l_mdrtCount); } - // Update PDA Table entries - if ( !INITSERVICE::spBaseServicesEnabled() ) - { - uint32_t threadRegSize = - l_sys->getAttr<TARGETING::ATTR_PDA_THREAD_REG_ENTRY_SIZE>(); - uint8_t threadRegFormat = - l_sys->getAttr<TARGETING::ATTR_PDA_THREAD_REG_STATE_ENTRY_FORMAT>(); - uint64_t capThreadArrayAddr = - l_sys->getAttr<TARGETING::ATTR_PDA_CAPTURED_THREAD_REG_ARRAY_ADDR>(); - uint64_t capThreadArraySize = - l_sys->getAttr<TARGETING::ATTR_PDA_CAPTURED_THREAD_REG_ARRAY_SIZE>(); - - // Ignore return value - RUNTIME::updateHostProcDumpActual( RUNTIME::PROC_DUMP_AREA_TBL, - threadRegSize, threadRegFormat, - capThreadArrayAddr, capThreadArraySize); - } + + threadRegSize = + l_sys->getAttr<TARGETING::ATTR_PDA_THREAD_REG_ENTRY_SIZE>(); + threadRegFormat = + l_sys->getAttr<TARGETING::ATTR_PDA_THREAD_REG_STATE_ENTRY_FORMAT>(); + capThreadArrayAddr = + l_sys->getAttr<TARGETING::ATTR_PDA_CAPTURED_THREAD_REG_ARRAY_ADDR>(); + capThreadArraySize = + l_sys->getAttr<TARGETING::ATTR_PDA_CAPTURED_THREAD_REG_ARRAY_SIZE>(); } + // Ignore return value + RUNTIME::updateHostProcDumpActual( RUNTIME::PROC_DUMP_AREA_TBL, + threadRegSize, threadRegFormat, + capThreadArrayAddr, capThreadArraySize); + + //Update the MDRT value (for MS Dump) l_err = RUNTIME::writeActualCount(RUNTIME::MS_DUMP_RESULTS_TBL); if(l_err != NULL) diff --git a/src/usr/isteps/istep21/call_host_start_payload.C b/src/usr/isteps/istep21/call_host_start_payload.C index f8cfd3172..85bf3c9f5 100644 --- a/src/usr/isteps/istep21/call_host_start_payload.C +++ b/src/usr/isteps/istep21/call_host_start_payload.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] Google Inc. */ /* [+] International Business Machines Corp. */ /* */ @@ -54,7 +54,6 @@ #include <p9n2_quad_scom_addresses_fld.H> #include <p9_quad_scom_addresses.H> #include <ipmi/ipmiwatchdog.H> -#include <config.h> #include <errno.h> #include <p9_int_scom.H> #include <sbeio/sbeioif.H> @@ -110,15 +109,6 @@ errlHndl_t broadcastShutdown ( uint64_t i_hbInstance ); errlHndl_t enableCoreCheckstops(); /** - * @brief This function will clear the PORE BARs. Needs to be done - * depending on payload type - * - * @return errlHndl_t - nullptr if successful, otherwise a pointer to the error - * log. - */ -errlHndl_t clearPoreBars ( void ); - -/** * @brief This function will check the Istep mode and send the appropriate * mailbox message to the Fsp to indicate what we're doing. * @@ -479,19 +469,6 @@ errlHndl_t callShutdown ( uint64_t i_masterInstance, break; } - if(is_phyp_load()) - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "calling clearPoreBars() in node"); - - //If PHYP then clear out the PORE BARs - err = clearPoreBars(); - if( err ) - { - break; - } - } - // Get Target Service, and the system target. TargetService& tS = targetService(); TARGETING::Target* sys = nullptr; @@ -793,77 +770,6 @@ errlHndl_t enableCoreCheckstops() return l_errl; } -/** - * @brief This function will clear the PORE BARs. Needs to be done - * depending on payload type - * - * @return errlHndl_t - nullptr if successful, otherwise a pointer to the error - * log. - */ -errlHndl_t clearPoreBars ( void ) -{ - errlHndl_t l_errl = nullptr; - - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "set PORE bars back to 0" ); - - TARGETING::TargetHandleList l_procTargetList; - getAllChips(l_procTargetList, TYPE_PROC); - - // loop thru all the cpus and reset the pore bars. - for (TargetHandleList::const_iterator - l_proc_iter = l_procTargetList.begin(); - l_proc_iter != l_procTargetList.end(); - ++l_proc_iter) - { - // make a local copy of the CPU target - const TARGETING::Target* l_proc_target = *l_proc_iter; - - // trace HUID - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "target HUID %.8X", TARGETING::get_huid(l_proc_target)); - - //@TODO RTC:133848 cast OUR type of target to a FAPI type of target. -#if 0 - fapi::Target l_fapi_proc_target( TARGET_TYPE_PROC_CHIP, - (const_cast<TARGETING::Target*>( - l_proc_target)) ); - - // reset pore bar notes: - // A mem_size of 0 means to ignore the image address - // This image should have been moved to memory after winkle - - // call the HWP with each fapi::Target - FAPI_INVOKE_HWP( l_errl, - p8_set_pore_bar, - l_fapi_proc_target, - 0, - 0, - 0, - SLW_MEMORY - ); -#endif - if ( l_errl ) - { - // capture the target data in the elog - ERRORLOG::ErrlUserDetailsTarget(l_proc_target).addToLog( l_errl ); - - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR : p8_set_pore_bar, PLID=0x%x", - l_errl->plid() ); - break; - } - else - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : p8_set_pore_bar" ); - } - - } // end for - - return l_errl; -} - // // Notify the Fsp via Mailbox Message // diff --git a/src/usr/isteps/istep21/call_nvdimm_update.C b/src/usr/isteps/istep21/call_nvdimm_update.C index 1204adb61..be1f5b22d 100644 --- a/src/usr/isteps/istep21/call_nvdimm_update.C +++ b/src/usr/isteps/istep21/call_nvdimm_update.C @@ -68,6 +68,9 @@ void call_nvdimm_update() TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_nvdimm_update(): nvdimm update failed"); } + + // Set the threshold warnings + NVDIMM::nvdimm_thresholds(l_nvdimmTargetList); } TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,EXIT_MRK"call_nvdimm_update()"); diff --git a/src/usr/isteps/istep21/call_update_ucd_flash.C b/src/usr/isteps/istep21/call_update_ucd_flash.C index 46d843579..89032ddd3 100644 --- a/src/usr/isteps/istep21/call_update_ucd_flash.C +++ b/src/usr/isteps/istep21/call_update_ucd_flash.C @@ -30,7 +30,6 @@ #include <util/utilmclmgr.H> #include <errl/errlmanager.H> #include <hbotcompid.H> -#include <config.h> #include <initservice/isteps_trace.H> #include <isteps/ucd/updateUcdFlash.H> #include <secureboot/trustedbootif.H> diff --git a/src/usr/isteps/istep21/freqAttrData.C b/src/usr/isteps/istep21/freqAttrData.C index 9dc60bfff..ed8c7df4a 100644 --- a/src/usr/isteps/istep21/freqAttrData.C +++ b/src/usr/isteps/istep21/freqAttrData.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2018 */ +/* Contributors Listed Below - COPYRIGHT 2011,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -48,7 +48,6 @@ #include <sys/time.h>
#include <sys/vfs.h>
#include <arch/ppc.H>
-#include <config.h>
#include <mbox/ipc_msg_types.H>
#include <fapi2.H>
diff --git a/src/usr/isteps/makefile b/src/usr/isteps/makefile index dca7777f7..5a53e3291 100644 --- a/src/usr/isteps/makefile +++ b/src/usr/isteps/makefile @@ -50,8 +50,9 @@ SUBDIRS+=tod.d SUBDIRS+=fab_iovalid.d SUBDIRS+=nest.d SUBDIRS+=io.d -SUBDIRS+=nvdimm.d +SUBDIRS+=$(if $(CONFIG_NVDIMM),nvdimm.d) SUBDIRS+=ucd.d +SUBDIRS+=expupd.d #TODO: RTC 176018 EXTRAINCDIR += ${ROOTPATH}/src/import/ diff --git a/src/usr/isteps/mem_utils.C b/src/usr/isteps/mem_utils.C index 89961ef5e..948dbdf17 100644 --- a/src/usr/isteps/mem_utils.C +++ b/src/usr/isteps/mem_utils.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -28,6 +28,7 @@ #include <errl/hberrltypes.H> #include <secureboot/smf_utils.H> #include <stdint.h> +#include <isteps/nvdimm/nvdimmif.H> namespace ISTEP { @@ -208,6 +209,11 @@ uint64_t get_top_homer_mem_addr() l_top_homer_addr = get_top_mem_addr(); } + // Need to make sure we don't choose a range that is owned by + // the NVDIMMs + l_top_homer_addr = + NVDIMM::get_top_addr_with_no_nvdimms(l_top_homer_addr); + }while(0); return l_top_homer_addr; diff --git a/src/usr/isteps/mss/HBconfig b/src/usr/isteps/mss/HBconfig index f48017fe1..56334c98c 100644 --- a/src/usr/isteps/mss/HBconfig +++ b/src/usr/isteps/mss/HBconfig @@ -1,4 +1,4 @@ config LRDIMM_CAPABLE default n help - Enable the use of LRDIMM code + Enable the use of LRDIMM code
\ No newline at end of file diff --git a/src/usr/isteps/mss/makefile b/src/usr/isteps/mss/makefile index 40eec68d9..f0901b170 100644 --- a/src/usr/isteps/mss/makefile +++ b/src/usr/isteps/mss/makefile @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2016,2019 +# Contributors Listed Below - COPYRIGHT 2016,2020 # [+] International Business Machines Corp. # # @@ -28,6 +28,7 @@ IMPORT_PATH = ${ROOTPATH}/src/import PROCEDURES_PATH = ${IMPORT_PATH}/chips/p9/procedures AXONE_PROCEDURES_PATH = ${IMPORT_PATH}/chips/p9a/procedures EXPLORER_PROCEDURES_PATH = ${IMPORT_PATH}/chips/ocmb/explorer/procedures +GEMINI_PROCEDURES_PATH = ${IMPORT_PATH}/chips/ocmb/gemini/procedures #Add all the extra include paths EXTRAINCDIR += ${ROOTPATH}/src/import/hwpf/fapi2/include @@ -38,6 +39,7 @@ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/utils/imageProcs/ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/common/include/ EXTRAINCDIR += ${IMPORT_PATH}/chips/ocmb/explorer/common/include/ EXTRAINCDIR += ${ROOTPATH}/obj/genfiles/chips/ocmb/explorer/procedures/hwp/memory/lib/ +EXTRAINCDIR += ${ROOTPATH}/obj/genfiles/chips/p9a/procedures/hwp/memory/lib/ EXTRAINCDIR += ${ROOTPATH}/obj/genfiles/generic/memory/lib/ EXTRAINCDIR += ${ROOTPATH}/obj/genfiles/ @@ -72,6 +74,9 @@ MSS_LIB += ${AXONE_PROCEDURES_PATH}/hwp/memory/lib/ MSS_LIB += ${AXONE_PROCEDURES_PATH}/hwp/memory/lib/eff_config/ MSS_LIB += ${AXONE_PROCEDURES_PATH}/hwp/memory/lib/utils/ MSS_LIB += ${AXONE_PROCEDURES_PATH}/hwp/memory/lib/freq/ +MSS_LIB += ${AXONE_PROCEDURES_PATH}/hwp/memory/lib/workarounds/ +MSS_LIB += ${AXONE_PROCEDURES_PATH}/hwp/memory/lib/fir/ +MSS_LIB += ${AXONE_PROCEDURES_PATH}/hwp/memory/lib/plug_rules/ MSS_LIB += ${EXPLORER_PROCEDURES_PATH}/hwp/memory/ MSS_LIB += ${EXPLORER_PROCEDURES_PATH}/hwp/memory/lib/ MSS_LIB += ${EXPLORER_PROCEDURES_PATH}/hwp/memory/lib/eff_config/ @@ -80,10 +85,18 @@ MSS_LIB += ${EXPLORER_PROCEDURES_PATH}/hwp/memory/lib/freq/ MSS_LIB += ${EXPLORER_PROCEDURES_PATH}/hwp/memory/lib/power_thermal/ MSS_LIB += ${EXPLORER_PROCEDURES_PATH}/hwp/memory/lib/omi/ MSS_LIB += ${EXPLORER_PROCEDURES_PATH}/hwp/memory/lib/i2c/ +MSS_LIB += ${EXPLORER_PROCEDURES_PATH}/hwp/memory/lib/inband/ MSS_LIB += ${EXPLORER_PROCEDURES_PATH}/hwp/memory/lib/fir/ MSS_LIB += ${EXPLORER_PROCEDURES_PATH}/hwp/memory/lib/mcbist/ MSS_LIB += ${EXPLORER_PROCEDURES_PATH}/hwp/memory/lib/phy/ MSS_LIB += ${EXPLORER_PROCEDURES_PATH}/hwp/memory/lib/ecc/ +MSS_LIB += ${EXPLORER_PROCEDURES_PATH}/hwp/memory/lib/ccs/ +MSS_LIB += ${EXPLORER_PROCEDURES_PATH}/hwp/memory/lib/workarounds/ +MSS_LIB += ${EXPLORER_PROCEDURES_PATH}/hwp/memory/lib/plug_rules/ +MSS_LIB += ${EXPLORER_PROCEDURES_PATH}/hwp/memory/lib/mc/ +MSS_LIB += ${GEMINI_PROCEDURES_PATH}/hwp/memory/ +MSS_LIB += ${GEMINI_PROCEDURES_PATH}/hwp/memory/lib/ + EXTRAINCDIR += ${MSS_LIB} @@ -170,6 +183,7 @@ FILE_PREFIX = mss_p9a SOURCES += $(ROOTPATH)/chips/p9/procedures/xml/attribute_info/p9a_io_attributes.xml SOURCES += $(ROOTPATH)/chips/p9/procedures/xml/attribute_info/p9a_omi_setup_bars.xml SOURCES += $(ROOTPATH)/chips/p9/procedures/xml/attribute_info/p9a_omi_init.xml +SOURCES += $(ROOTPATH)/chips/p9/procedures/xml/attribute_info/p9a_omi_train.xml CLEAN_TARGETS += ${OUTPATH}/mss_p9a_attribute_getters.H CLEAN_TARGETS += ${OUTPATH}/mss_p9a_attribute_setters.H @@ -182,6 +196,27 @@ endef $(call BUILD_GENERATED) +# Generate pmic_accessors header file +GENERATED = gen_pmic_accessors +COMMAND = gen_accessors.pl +$(GENERATED)_COMMAND_PATH = $(IMPORT_PATH)/generic/memory/tools/ + +OUTPATH = ${ROOTPATH}/obj/genfiles/chips/ocmb/common/procedures/hwp/pmic/lib/ +FILE_PREFIX = mss_pmic + +SOURCES += $(ROOTPATH)/chips/ocmb/common/procedures/xml/attribute_info/pmic_eff_attributes.xml + +CLEAN_TARGETS += ${OUTPATH}/mss_pmic_attribute_getters.H +CLEAN_TARGETS += ${OUTPATH}/mss_pmic_attribute_setters.H +CLEAN_TARGETS += ${OUTPATH}/.gen_pmic_accessors.built + +define gen_pmic_accessors_RUN + $(C1) mkdir $(OUTPATH) -p + $(C1) $$< --system=AXONE --output-dir=$(OUTPATH) --output-file-prefix=$(FILE_PREFIX) $$(filter-out $$<,$$^) +endef + +$(call BUILD_GENERATED) + # Add common and generated parts to object list. MSS_PATH := $(PROCEDURES_PATH)/hwp/memory/lib @@ -198,13 +233,16 @@ MSS_MODULE_OBJS += $(if $(CONFIG_AXONE),$(patsubst %.C,%.o,$(MSS_AXONE_SOURCE)), MSS_PATH_EXPLORER := $(EXPLORER_PROCEDURES_PATH)/hwp/memory/lib MSS_EXPLORER_SOURCE := $(shell find $(MSS_PATH_EXPLORER) -name '*.C' -exec basename {} \;) -# TODO RTC: 207832 Remove filter-out commands when new lib files come -MSS_EXPLORER_SOURCE := $(filter-out memdiags.C,$(MSS_EXPLORER_SOURCE)) -MSS_EXPLORER_SOURCE := $(filter-out mcbist.C,$(MSS_EXPLORER_SOURCE)) -MSS_EXPLORER_SOURCE := $(filter-out memory_size.C,$(MSS_EXPLORER_SOURCE)) #must bring explorer_memory_size.o in even in Nimbus/Cumulus builds because of p9_mss_grouping nest HWP MSS_MODULE_OBJS += $(if $(CONFIG_AXONE),$(patsubst %.C,%.o,$(MSS_EXPLORER_SOURCE)),explorer_memory_size.o) + +MSS_PATH_GEMINI := $(GEMINI_PROCEDURES_PATH)/hwp/memory/lib +MSS_GEMINI_SOURCE := $(shell find $(MSS_PATH_GEMINI) -name '*.C' -exec basename {} \;) +MSS_MODULE_OBJS += $(if $(CONFIG_AXONE),$(patsubst %.C,%.o,$(MSS_GEMINI_SOURCE)),) + + MODULE = isteps_mss + OBJS += $(MSS_MODULE_OBJS) $(call BUILD_MODULE) diff --git a/src/usr/isteps/mss/runtime/makefile b/src/usr/isteps/mss/runtime/makefile index 400025498..530a68f8d 100644 --- a/src/usr/isteps/mss/runtime/makefile +++ b/src/usr/isteps/mss/runtime/makefile @@ -68,6 +68,7 @@ MSS_LIB += ${IMPORT_PATH}/generic/memory/lib/spd/ MSS_LIB += ${IMPORT_PATH}/generic/memory/lib/utils/ MSS_LIB += ${IMPORT_PATH}/generic/memory/lib/utils/shared/ MSS_LIB += ${IMPORT_PATH}/generic/memory/lib/utils/freq/ +MSS_LIB += ${IMPORT_PATH}/generic/memory/lib/utils/mcbist # Axone MSS_LIB += ${IMPORT_PATH}/chips/p9a/procedures/hwp/memory/lib/utils/ @@ -86,10 +87,9 @@ OBJS += axone_c_str.o OBJS += nimbus_c_str.o OBJS += mcbist.o OBJS += mcbist_workarounds.o -OBJS += sim.o OBJS += rank.o OBJS += memory_size.o -OBJS += patterns.o +OBJS += gen_mss_mcbist_patterns.o OBJS += axone_pos.o OBJS += nimbus_pos.o diff --git a/src/usr/isteps/nest/makefile b/src/usr/isteps/nest/makefile index aa22887c3..a995b7cd0 100644 --- a/src/usr/isteps/nest/makefile +++ b/src/usr/isteps/nest/makefile @@ -41,6 +41,7 @@ EXTRAINCDIR += ${PROCEDURES_PATH}/hwp/initfiles OBJS += nestHwpHelperFuncs.o OBJS += p9_io_obus_firmask_save_restore.o +OBJS += p9_fbc_ioo_dl_npu_scom.o VPATH += ${PROCEDURES_PATH}/hwp/initfiles VPATH += ${PROCEDURES_PATH}/hwp/io diff --git a/src/usr/isteps/nvdimm/ReadMe.md b/src/usr/isteps/nvdimm/ReadMe.md new file mode 100644 index 000000000..1f98438b2 --- /dev/null +++ b/src/usr/isteps/nvdimm/ReadMe.md @@ -0,0 +1,278 @@ +# Battery Power Module (BPM) Updates Overview
+To support different firmware versions released by SMART, the bpm_update.C and
+bpm_update.H files were created to facilitate upgrades and downgrades of the
+firmware version on a BPM attached to an NVDIMM. There are two kinds of BPM, one
+that supports 16GB type NVDIMMs and one that supports 32GB type NVDIMMs.
+Although they have separate image files, the update is functionally the same for
+each. This overview will not go into fine-grain detail on every process of the
+update. For more information see the comments in bpm_update.H, bpm_update.C and
+in the various supporting files.
+
+Supporting Files:
+* Two image files, e.g., SRCA8062IBMH012B_FULL_FW_Rev1.03_02282019.txt or
+SRCA8062IBMH011B_FULL_FW_Rev1.04_05172019.txt
+ * The image file names are important in that they contain information that
+ is not found anywhere else in the files. For example, After SRCA8062IBMH01
+ but right before the B is a number. That signifies which kind of BPM type
+ that image is for. A 1 means 32gb type, a 2 means 16gb type. Also, note that
+ the version Rev1.0x is in the file name. There is no other place where this
+ occurs within the image file. So, to differentiate the updates from each
+ other the file names must be left intact.
+* src/build/buildpnor/buildBpmFlashImages.pl
+ * This perl script is responsible for packaging the image files listed above
+ into binaries that can then be associated with LIDs for use during the BPM
+ update.
+* src/build/buildpnor/bpm-utils/imageCrc.c and
+src/build/buildpnor/bpm-utils/insertBpmFwCrc.py
+ * These are provided by SMART and utilized by buildBpmFlashImages.pl to
+ generate the correct CRC for the firmware image during the fsp build.
+* src/build/mkrules/dist.targets.mk
+ * This file puts src/build/buildpnor/buildBpmFlashImages.pl,
+ src/build/buildpnor/bpm-utils/imageCrc.c,
+ and src/build/buildpnor/bpm-utils/insertBpmFwCrc.py into the fsp.tar which
+ can then be primed over to an FSP sandbox.
+* <fsp_sandbox>/src/engd/nvdimm/makefile
+ * This makefile compiles the src/build/buildpnor/bpm-utils/imageCrc.c and
+ calls src/build/buildpnor/buildBpmFlashImages.pl to do all the necessary
+ work to bring the flash image binaries up-to-date.
+* In <fsp_sandbox>/obj/ppc/engd/nvdimm/bpm/ are 16GB-NVDIMM-BPM-CONFIG.bin,
+16GB-NVDIMM-BPM-FW.bin, 32GB-NVDIMM-BPM-CONFIG.bin, and 32GB-NVDIMM-BPM-FW.bin
+ * These are the output binaries which will be associated to LIDs for
+ hostboot use.
+
+### BPM Update Flow Overview
+The update procedure for the BPM is fairly rigid. There are many steps that must
+occur in a precise order otherwise the update will fail. We aren't able to
+communicate directly to the BPM for these updates. Instead, we send commands to
+the NVDIMM which in-turn passes those along to the BPM. There are a couple
+"modes" that must be enabled to begin the update process and be able to
+communicate with the BPM. These are:
+
+##### Update Mode
+This is a mode for the NVDIMM. To enter this mode a command is sent to the
+NVDIMM so that the NVDIMM can do some house-keeping work to prepare for the BPM
+update. Since the NVDIMM is always doing background scans of the BPM, this mode
+will quiet those scans so that we are able to communicate with the BPM.
+Otherwise, the communication would be too chaotic to perform the update.
+
+##### Boot Strap Loader (BSL) Mode (Currently, only BSL 1.4 is supported)
+This is the mode that the BPM enters in order to perform the update.In order to
+execute many of the commands necessary to perform the update, the BPM **must**
+be in BSL mode. There are varying versions of BSL mode and these versions are
+not coupled with the firmware version at all. In order for the BSL version to be
+updated on a BPM, the device must be shipped back to SMART because it requires a
+specific hardware programmer device to be updated.
+
+The update procedure does vary between BSL versions, so to ensure a successful
+update the code will first read the BSL version on the BPM. If the BSL version
+is not 1.4 (the supported version) then the update process will not occur as it
+is known that BSL versions prior to 1.4 are different enough that the update
+would fail if attempted and it is unknown if future BSL versions will be
+backward compatible with the BSL 1.4 procedure.
+
+If something happens to the firmware during an update such that the firmware on
+the device is missing or invalid, the BPM is designed to always fall back to
+this mode so that valid firmware can be loaded onto the BPM and the device can
+be recovered. However, if the firmware is corrupted by any means outside of an
+update then it is highly likely that the BPM will not be recoverable and it may
+need to be sent back to SMART for recovery.
+
+#### An update in two parts
+The BPM update cannot be done in one single pass. This is because there are two
+sections of data on the BPM that must be modified to successfully update the
+BPM. These are refered to as the Firmware portion of the update and the
+Configuration Data Segment portion of the update.
+
+##### The Firmware Portion
+This is the actual firmware update. Although, when someone says the BPM Firmware
+Update they are often implicitly referring to both parts of the update. In order
+for the full update to be a success, the firmware portion of the update is
+reliant upon another part to have access to all of the features in a given
+update. That is the Configuration Segment Data. It is safe, and advisable, to
+update the firmware part first and then the configuration part second.
+
+##### The Configuration Data Portion
+The Configuration Data Segment portion is commonly referred to as the segment
+update, config update, or any other variation of the name. The config segment
+portion **requires** working firmware on the BPM to succeed. This is because we
+must read out some of the segment data on the BPM and merge it with parts from
+the image. Without working firmware, it will not work and the update will
+_never_ succeed.
+
+The configuration data on the BPM is broken into four segments, A, B, C, and D.
+These are in reverse order in memory such that D has the lowest address offset.
+For our purposes, we only care about Segment D and B. A and C contain logging
+information and are not necessary to touch. Segment D will be completely
+replaced by the data in the image file. Segment B is the critical segment,
+however, because we must splice data from the image into it. Segment B contains
+statistical information and other valuable information that should never be lost
+during an update. If this segment becomes corrupted then it is very likely the
+BPM will be stuck in a bad state.
+
+##### Bpm::runUpdate Flow
+1. Read the current firmware version on the BPM to determine if updates are
+necessary. If this cannot be done, that is to say that an error occurs during
+this process, then updates will not be attempted due to a probable
+communication issue with the BPM.
+2. Read the current BSL mode version to determine if the BSL version on the BPM
+is compatible with the versions we support. If this cannot be done due to some
+kind of error, then the updates will not be attempted since we cannot be sure
+that the BPM has a compatible BSL version.
+3. Perform the firmware portion of the update. If an error occurs during this
+part of the update then the segment portion of the updates will not be attempt
+as per the given requirement above.
+4. Perform the segment portion of the update.
+
+##### Common Operating Processes between functions
+Reading the BSL version, and performing the firmware and segment updates all
+follow a common operating process to do their work successfully. The steps laid
+out in those functions must be followed in the given order otherwise the
+functions will not execute successfully and the BPM may go into a bad state.
+These steps are:
+1. Enter Update Mode
+2. Verify the NVDIMM is in Update Mode
+3. Command the BPM to enter BSL mode
+4. Unlock the BPM so that writing can be performed.
+5. Do function's work.
+6. Reset the BPM, which is the way that BSL mode is exited.
+7. Exit Update Mode
+
+By following these steps, the BPM is able to some background work to verify its
+state. If firmware and config updates are attempted at the same time this will
+introduce unpredicatable behavior. Meaning if only one set of steps 1-4 have
+executed then step 5a and 5b are to perform firmware and config updates, and
+then 6-7 are done that will produce unpredicable behavior. It is best run
+through the whole process for each. Reading the BSL version does not have this
+limitation. As long as steps 1-4 have been executed, the BSL version can be read
+at any time.
+
+-------------------------------------------------------------------------------
+# Node Controller (NC) Update Overview
+To support different firmware versions released by SMART, the nvdimm_update.C
+and nvdimm_update.H files were created to facilitate upgrades and downgrades of
+the firmware version of node controllers for NVDIMM. There are two kinds of
+NVDIMM node controllers: one that supports 16GB type NVDIMMs and one that
+supports 32GB type NVDIMMs. Although they have separate image files, the update
+is functionally the same for each. This overview will not go into fine-grain
+detail on every process of the update. For more information see the comments in
+nvdimm_update.H, nvdimm_update.C and in the various supporting files.
+
+Supporting Files:
+* Two signed image files are provided by SMART.
+ The name contains the NC type (16GB or 32GB) + the version (v##)
+
+ Example:
+ nvc4_fpga_31mm_X4_16GB_A7_2TLC_GA6_IBM_JEDEC_2019_03_22_v30_r29325-SIGNED.bin
+ nvc4_fpga_31mm_X4_32GB_A7_2TLC_GA6_IBM_JEDEC_2019_03_22_v30_r29325-SIGNED.bin
+
+* Files checked into cmvc/build process
+ Note: Each file contains two bytes that describe the NC type and version, so
+ we can use a generic name in CMVC
+ * NVDIMM_SRN7A2G4IBM26MP1SC.bin (16GB one)
+ * NVDIMM_SRN7A4G4IBM24KP2SB.bin (32GB one)
+
+* Build process creates lid files that are loaded on system
+ * 80d00025.lid (secure content LID)
+ * 81e00640.lid (signed 16GB)
+ * 81e00641.lid (signed 32GB)
+
+### NC Update Flow Overview
+The update procedure for the NC is fairly rigid. There are many steps that must
+occur in a precise order otherwise the update will fail.
+
+### Design points
+Three classes are used for the NC update
+* NvdimmsUpdate -- container/driver class
+ This is where all the functional NVDIMM NCs are checked and updated if necessary
+* NvdimmLidImage -- accessors for a given NC LID image (16 or 32)
+ This provides the LID content for easy checking and use during update
+* NvdimmInstalledImage -- accessor to current installed NC image
+ This is the main workhorse. It uses i2c communication to check what is
+ installed and performs the update to a new LID image level
+
+##### NvdimmsUpdate::runUpdate Flow
+1. Build up installed NVDIMM image lists (determine what NC types are installed)
+2. Using secure content lid, now call runUpdateUsingLid() for each LID type
+with the appropriate target NVDIMMs associated with that type.
+3. runUpdateUsingLid() cycles through each NVDIMM target and checks if the
+current NC level is different then the lid version level.
+Only update if the levels do not match to allow upgrade and downgrading.
+4. NvdimmInstalledImage::updateImage() is called on each NVDIMM node controller
+that requires an update
+5. updateImage runs through the steps outlined in 9.7 Firmware Update workflow
+in the JEDEC document JESD245B
+6. Basic steps of the update done one NVDIMM controller at a time
+ 1. Validate module manufacturer ID and module product identifier (done before this)
+ 2. Verify 'Operation In Progress' bit in the NVDIMM_CMD_STATUS0
+ register is cleared (ie. NV controller is NOT busy)
+ 3. Make sure we start from a cleared state
+ 4. Enable firmware update mode
+ 5. Clear the Firmware Operation status
+ 6. Clear the firmware data block to ensure there is no residual data
+ 7. Send the first part (header + SMART signature) of the Firmware Image Data
+ Include sending data and checking checksum after data is sent
+ 8. Command the module to validate that the firmware image is valid for
+ the module based on the header
+ 9. Commit the first firmware data region
+ 10. Send and commit the remaining firmware data in REGION_BLOCK_SIZE regions
+ - each block is 32 bytes
+ - each region contains upto REGION_BLOCK_SIZE blocks (currently 1,024)
+ - each region is verfied by checksum before next region is sent
+ 11. Command the module to validate the firmware data
+ 12. Disable firmware update mode
+ 13. Switch from slot0 to slot1 which contains the new image code
+ 14. Validate running new code level
+
+# NVDIMM Secure Erase Verify Flow
+DS8K lpar -> HBRT NVDIMM operation = factory_default + secure_erase_verify_start
+ HBRT executes factory_default and steps 1) and 2)
+DS8K lpar -> HBRT NVDIMM operation = secure_erase_verify_complete
+ HBRT executes step 3)
+ If secure erase verify has not completed, return status with verify_complete bit = 0
+ DS8K lpar is responsible for monitoring elapsed time (2/4 hours) and restart process (step 6)
+ If secure erase verify has completed
+ HBRT executes steps 4) and 5), generating error logs for any non-zero register values
+ Return status with verify_complete bit = 1
+
+## Procedure Flow for NVDIMM Secure Erase Verify
+ *Note: Secure Erase Verify should only be run after a Factory Default operation.
+ Secure Erase Verify is intended to verify whether all NAND blocks have been erased.
+ *Note: Full breakout of all Page 5 Secure Erase Verify registers can be found in
+ SMART document "JEDEC NVDIMM Vendor Page 2 Extensions".
+ 1) Set Page 5 Register 0x1B to value "0x00"
+ // this clears the status register
+ 2) Set Page 5 Register 0x1A to value "0xC0"
+ // this kicks off the erase verify operation
+ 3) Wait for Page 5 Register 0x1A Bit 7 to be reset to value "0"
+ // i.e., the overall register value should be "0x40";
+ this means that erase verify has completed
+ a. If Page 5 Register 0x1A Bit 7 has not reset to value "0"
+ after 2 hours (16GB NVDIMM) or after 4 hours (32GB NVDIMM),
+ report a timeout error and skip to step (6)
+ 4) Read Page 5 Register 0x1B; value should be "0x00"
+ // this is the erase verify status register
+ a. If Page 5 Register 0x1B value is not "0x00",
+ report any/all errors as outlined in the table at the end of this document,
+ then skip to step (6)
+ 5) Read Page 5 Registers 0x1D (MSB) and 0x1C (LSB);
+ combined the two registers should have a value of "0x0000"
+ // this is the number of chunks failing Secure Erase Verify
+ a. If the combined value of the two registers is not "0x0000",
+ report a threshold exceeded error along with the combined value of the two registers,
+ then skip to step (6)
+ 6) If any errors have been reported in steps (3), (4), or (5),
+ retry the secure erase verify operation starting again from step (1)
+ a. If the secure erase verify operation fails even after retrying,
+ report that secure erase verify operation has failed
+ 7) If no errors have been reported, report that secure erase verify operation
+ has been completed successfully
+ *Addendum: Breakout of Page 5 Register 0x1B Erase Verify Status bit values referenced in step (4) above.
+ All these bits should return as "0". Any bits returning as "1" should be reported with the error name below.
+ Bits 7:6 - Reserved
+ Bit 5 - BAD BLOCK
+ Bit 4 - OTHER
+ Bit 3 - ENCRYPTION LOCKED
+ Bit 2 - INVALID PARAMETER
+ Bit 1 - INTERRUPTED
+ Bit 0 - NAND ERROR
+
diff --git a/src/usr/isteps/nvdimm/bpm_update.C b/src/usr/isteps/nvdimm/bpm_update.C new file mode 100644 index 000000000..3ffdb595b --- /dev/null +++ b/src/usr/isteps/nvdimm/bpm_update.C @@ -0,0 +1,4108 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/isteps/nvdimm/bpm_update.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +#include "nvdimm.H" +#include "bpm_update.H" +#include "nvdimm_update.H" + +#include <isteps/nvdimm/nvdimm.H> +#include <errl/hberrltypes.H> +#include <errl/errlmanager.H> +#include <endian.h> +#include <sys/time.h> +#include <hbotcompid.H> +#include <trace/interface.H> +#include <initservice/istepdispatcherif.H> +#include <isteps/nvdimm/bpmreasoncodes.H> + +#include <hwas/common/hwasCallout.H> + +#include <targeting/common/targetservice.H> +#include <attributeenums.H> + +namespace NVDIMM +{ +namespace BPM +{ + +trace_desc_t* g_trac_bpm = nullptr; +TRAC_INIT(&g_trac_bpm, BPM_COMP_NAME, 4*KILOBYTE); + +// For debug traces +#define TRACUCOMP(args...) +//#define TRACUCOMP(args...) TRACFCOMP(args) +#define TRACUBIN(args...) +//#define TRACUBIN(args...) TRACUBIN(args) + +// These constants are kept out of the header file since they aren't relevant +// outside of this file. +const uint16_t BPM_ADDRESS_ZERO = 0; +const uint16_t BPM_CONFIG_START_ADDRESS = 0x1800; +// There are two potential start addresses for the firmware section. +// They are: +const uint16_t MAIN_PROGRAM_ADDRESS = 0x8000; +const uint16_t MAIN_PROGRAM_ADDRESS_ALT = 0xA000; + +// In order to disable write protection on the BPM to perform updates a sequence +// of characters must be written. The hex represenation of those characters are +// defined by this constant. The sequence is SMOD +const uint8_t BPM_PASSWORD[] = {0x53, 0x4D, 0x4F, 0x44}; +const size_t BPM_PASSWORD_LENGTH = 4; + +// These are the segment codes used to dump out a particular config data segment +// on the BPM. +const uint16_t DEFAULT_REG_PAGE = 0x905E; +const uint16_t SEGMENT_A_CODE = 0x9A5E; +const uint16_t SEGMENT_B_CODE = 0x9B5E; +const uint16_t SEGMENT_C_CODE = 0x9C5E; +const uint16_t SEGMENT_D_CODE = 0x9D5E; + +// Starting addresses relative to address 0x1800. +// Segments appear in reverse order on BPM. +// Each segment is SEGMENT_SIZE long. +const size_t SEGMENT_D_START_ADDR = 0x000; +const size_t SEGMENT_C_START_ADDR = 0x080; +const size_t SEGMENT_B_START_ADDR = 0x100; +const size_t SEGMENT_A_START_ADDR = 0x180; + +const std::map<uint16_t, size_t> segmentMap +{ + {SEGMENT_A_CODE, SEGMENT_A_START_ADDR}, + {SEGMENT_B_CODE, SEGMENT_B_START_ADDR}, + {SEGMENT_C_CODE, SEGMENT_C_START_ADDR}, + {SEGMENT_D_CODE, SEGMENT_D_START_ADDR}, +}; + +const uint8_t MAX_RETRY = 3; + +/** + * @brief A helper function used in assert statements to verify the correct + * BSP commands were passed into the correct function arguments. + * + * @param[in] i_command The command that will verified to be a BSP command. + * + * @return bool true if i_command is a BSP command. + * false if it's not a BSP command. + */ +bool isBspCommand(const uint8_t i_command) +{ + bool result = ((i_command == BPM_PASSTHROUGH) || (i_command == BPM_LOCAL)) + ? true : false; + + return result; +} + +/** + * @brief A helper function used in assert statements to verify the correct + * BCL commands were passed into the correct function arguments. + * + * @param[in] i_command The command that will verified to be a BCL command. + * + * @return bool true if i_command is a BCL command. + * false if it's not a BCL command. + */ +bool isBclCommand(const uint8_t i_command) +{ + bool result = false; + switch(i_command) + { + case BCL_ENTER_BSL_MODE: + case BCL_IS_BSL_MODE: + case BCL_WRITE_REG: + case BCL_START_UPDATE: + case BCL_END_UPDATE: + case BCL_IS_UPDATE_IN_PROGRESS: + { + result = true; + break; + } + default: + { + result = false; + break; + } + } + + return result; +} + +/** + * @brief A helper function used in assert statements to verify the correct + * BSL commands were passed into the correct function arguments. + * + * @param[in] i_command The command that will verified to be a BSL command. + * + * @return bool true if i_command is a BSL command. + * false if it's not a BSL command. + */ +bool isBslCommand(const uint8_t i_command) +{ + bool result = false; + switch(i_command) + { + case BSL_RX_DATA_BLOCK: + case BSL_RX_PASSWORD: + case BSL_ERASE_SEGMENT: + case BSL_TOGGLE_INFO: + case BSL_ERASE_BLOCK: + case BSL_MASS_ERASE: + case BSL_CRC_CHECK: + case BSL_LOAD_PC: + case BSL_TX_DATA_BLOCK: + case BSL_TX_BSL_VERSION: + case BSL_TX_BUFFER_SIZE: + case BSL_RX_DATA_BLOCK_FAST: + case BSL_RESET_DEVICE: + case BSL_VERIFY_BLOCK: + { + result = true; + break; + } + default: + { + result = false; + break; + } + } + + return result; +} + +/** + * @brief Helper function to pull out the BPM address offset in the given + * payload. + * + * @param[in] i_payload The payload from which to extract the address + * offset. + */ +uint16_t getPayloadAddressBE(payload_t i_payload) +{ + // Get the payload address and convert back to big endian. + uint16_t payloadAddress = (i_payload[PAYLOAD_ADDRESS_START_INDEX]) + | (i_payload[PAYLOAD_ADDRESS_START_INDEX + 1] << 8); + return payloadAddress; +} + +/** + * @brief Helper function to extract the Segement ID from the segment code. + * + * @param[in] i_segmentCode The Segment code to pull the segment ID from + * + * @return uint8_t The Segment ID (A, B, C, D) as a hex value. + * For example 0xA, 0xB, etc. + */ +uint8_t getSegmentIdentifier(uint16_t i_segmentCode) +{ + uint8_t segmentId = (i_segmentCode >> 8) & 0xF; + return segmentId; +} + +/** + * @brief Helper function to sleep for longer durations in 5 second increments. + * + * @param[in] i_sleepInSeconds How many seconds to sleep. + */ +void longSleep(uint8_t const i_sleepInSeconds) +{ + int iterations = i_sleepInSeconds / 5; + do + { + // Send progress code. + INITSERVICE::sendProgressCode(); + + // Sleep for 5 seconds + nanosleep(5, 0); + + --iterations; + } while (iterations > 0); +} + +void runBpmUpdates(bpmList_t * const i_16gb_BPMs, + bpmList_t * const i_32gb_BPMs, + BpmFirmwareLidImage * const i_16gb_fwImage, + BpmFirmwareLidImage * const i_32gb_fwImage, + BpmConfigLidImage * const i_16gb_configImage, + BpmConfigLidImage * const i_32gb_configImage) +{ + + assert( (i_16gb_BPMs == nullptr) + || i_16gb_BPMs->empty() + || ((i_16gb_fwImage != nullptr) && (i_16gb_configImage != nullptr)), + "BPM::runBpmUpdates(): Update images for 16gb BPMs was nullptr and " + "there are 16gb BPMs in the system to may require updates."); + assert( (i_32gb_BPMs == nullptr) + || i_32gb_BPMs->empty() + || ((i_32gb_fwImage != nullptr) && (i_32gb_configImage != nullptr)), + "BPM::runBpmUpdates(): Update images for 32gb BPMs was nullptr and " + "there are 32gb BPMs in the system to may require updates."); + + errlHndl_t errl = nullptr; + + do { + + if ( (i_16gb_BPMs != nullptr) + && (i_16gb_fwImage != nullptr) + && (i_16gb_configImage != nullptr)) + { + TRACFCOMP(g_trac_bpm, + "Check/update %d BPMs on 16GB_TYPE NVDIMMs", + i_16gb_BPMs->size()); + + for(auto& bpm : *i_16gb_BPMs) + { + errl = bpm.runUpdate(*i_16gb_fwImage, *i_16gb_configImage); + if (errl != nullptr) + { + uint32_t nvdimmHuid = TARGETING::get_huid(bpm.getNvdimm()); + if (bpm.attemptAnotherUpdate()) + { + TRACFCOMP(g_trac_bpm, ERR_MRK + "An error occurred during a 16GB_TYPE BPM " + "update for NVDIMM 0x%.8X. " + "Try again.", + nvdimmHuid); + + delete errl; + errl = bpm.runUpdate(*i_16gb_fwImage, + *i_16gb_configImage); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, ERR_MRK + "Another error occurred while attempting " + "to update the same 16GB_TYPE BPM for " + "NVDIMM 0x%.8X. Commit and move onto the " + "next BPM", + nvdimmHuid); + } + else + { + continue; + } + } + else + { + TRACFCOMP(g_trac_bpm, ERR_MRK + "An error occurred during a 16GB_TYPE BPM " + "update for NVDIMM 0x%.8X. " + "Commit and move onto the next BPM", + nvdimmHuid); + } + ERRORLOG::errlCommit(errl, BPM_COMP_ID); + } + } + } + + if ( (i_32gb_BPMs != nullptr) + && (i_32gb_fwImage != nullptr) + && (i_32gb_configImage != nullptr)) + { + TRACFCOMP(g_trac_bpm, + "Check/update %d BPMs on 32GB_TYPE NVDIMMs", + i_32gb_BPMs->size()); + + for(auto& bpm : *i_32gb_BPMs) + { + errl = bpm.runUpdate(*i_32gb_fwImage, *i_32gb_configImage); + if (errl != nullptr) + { + uint32_t nvdimmHuid = TARGETING::get_huid(bpm.getNvdimm()); + if (bpm.attemptAnotherUpdate()) + { + TRACFCOMP(g_trac_bpm, ERR_MRK + "An error occurred during a 32GB_TYPE BPM " + "update for NVDIMM 0x%.8X. " + "Try again.", + nvdimmHuid); + + delete errl; + errl = bpm.runUpdate(*i_32gb_fwImage, + *i_32gb_configImage); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, ERR_MRK + "Another error occurred while attempting " + "to update the same 32GB_TYPE BPM for " + "NVDIMM 0x%.8X. Commit and move onto the " + "next BPM", + nvdimmHuid); + } + else + { + continue; + } + } + else + { + TRACFCOMP(g_trac_bpm, ERR_MRK + "An error occurred during a 32GB_TYPE BPM " + "update for NVDIMM 0x%.8X. " + "Commit and move onto the next BPM", + nvdimmHuid); + } + ERRORLOG::errlCommit(errl, BPM_COMP_ID); + } + } + } + } while(0); +} + +// ============================================================================= +// BpmFirmwareLidImage Class Functions +// ============================================================================= + +BpmFirmwareLidImage::BpmFirmwareLidImage(void * const i_lidImageAddr, + size_t i_size) + : iv_lidImage(i_lidImageAddr), iv_lidImageSize(i_size) +{ + assert(i_lidImageAddr != nullptr, + "BPM::BpmFirmwareLidImage(): Provided LID image must not be nullptr"); +} + +uint16_t BpmFirmwareLidImage::getVersion() const +{ + uint16_t version = INVALID_VERSION; + + if (iv_lidImageSize >= sizeof(firmware_image_header_t)) + { + const firmware_image_header_t * header = + reinterpret_cast<const firmware_image_header_t*>(iv_lidImage); + + version = TWO_UINT8_TO_UINT16(header->iv_versionMajor, + header->iv_versionMinor); + } + + return version; +} + +uint16_t BpmFirmwareLidImage::getNumberOfBlocks() const +{ + uint16_t numberOfBlocks = 0; + + if (iv_lidImageSize >= sizeof(firmware_image_header_t)) + { + const firmware_image_header_t * header = + reinterpret_cast<const firmware_image_header_t*>(iv_lidImage); + + numberOfBlocks = header->iv_numberOfBlocks; + } + + return numberOfBlocks; +} + +void const * BpmFirmwareLidImage::getFirstBlock() const +{ + void * block = nullptr; + + if (getNumberOfBlocks() > 0) + { + block = reinterpret_cast<uint8_t* const>(iv_lidImage) + + sizeof(firmware_image_header_t); + } + + return block; +} + +// ============================================================================= +// BpmConfigLidImage Class Functions +// ============================================================================= + +BpmConfigLidImage::BpmConfigLidImage(void * const i_lidImageAddr, + size_t i_size) + : iv_lidImage(i_lidImageAddr), iv_lidImageSize(i_size) +{ + assert(i_lidImageAddr != nullptr, + "BPM::BpmConfigLidImage(): Provided LID image must not be nullptr"); +} + +uint16_t BpmConfigLidImage::getVersion() const +{ + uint16_t version = INVALID_VERSION; + + if (iv_lidImageSize >= sizeof(config_image_header_t)) + { + const config_image_header_t * header = + reinterpret_cast<const config_image_header_t*>(iv_lidImage); + + version = TWO_UINT8_TO_UINT16(header->iv_versionMajor, + header->iv_versionMinor); + } + + return version; +} + +uint16_t BpmConfigLidImage::getNumberOfFragments() const +{ + uint16_t numberOfFragments = 0; + + if (iv_lidImageSize >= sizeof(config_image_header_t)) + { + const config_image_header_t * header = + reinterpret_cast<const config_image_header_t*>(iv_lidImage); + + numberOfFragments = header->iv_numberOfFragments; + } + + return numberOfFragments; +} + +void const * BpmConfigLidImage::getFirstFragment() const +{ + void * fragment = nullptr; + + if (getNumberOfFragments() > 0) + { + fragment = reinterpret_cast<uint8_t* const>(iv_lidImage) + + sizeof(config_image_header_t); + } + + return fragment; +} + +// ============================================================================= +// Bpm Class Functions +// ============================================================================= + +Bpm::Bpm(const TARGETING::TargetHandle_t i_nvdimm) + : iv_nvdimm(i_nvdimm), + iv_bslVersion(0), + iv_firmwareStartAddress(0), + iv_attemptAnotherUpdate(false), + iv_segmentDMerged(false), + iv_segmentBMerged(false), + iv_updateAttempted(false) +{ + assert((i_nvdimm != nullptr) && (isNVDIMM(i_nvdimm)), + "BPM::Bpm(): An nvdimm target must be given."); + + memset(&iv_segmentD, 0, SEGMENT_SIZE); + memset(&iv_segmentB, 0, SEGMENT_SIZE); + +} + +bool Bpm::attemptAnotherUpdate() +{ + return iv_attemptAnotherUpdate; +} + +bool Bpm::hasAttemptedUpdate() +{ + return iv_updateAttempted; +} + +void Bpm::setAttemptAnotherUpdate() +{ + + if (iv_updateAttempted) + { + // Since iv_updateAttempted is true that means that this function was + // called on a subsequent update attempt, meaning we should no longer + // attempt updates if the current attempt fails. + iv_attemptAnotherUpdate = false; + } + else + { + // Since iv_updateAttempted is false that means that this function was + // called on the first update attempt because by default + // iv_updateAttempted is false and is only set to true as the last part + // of the update procedure. + iv_attemptAnotherUpdate = true; + } + +} + +const TARGETING::TargetHandle_t Bpm::getNvdimm() +{ + return iv_nvdimm; +} + +errlHndl_t Bpm::readBslVersion() +{ + TRACFCOMP(g_trac_bpm, ENTER_MRK"Bpm::readBslVersion()"); + errlHndl_t errl = nullptr; + + do { + // Enter Update mode + errl = enterUpdateMode(); + if (errl != nullptr) + { + break; + } + + // Verify in Update mode + errl = inUpdateMode(); + if (errl != nullptr) + { + break; + } + + // Enter Bootstrap Loader (BSL) mode + errl = enterBootstrapLoaderMode(); + if (errl != nullptr) + { + break; + } + + // Unlock the device. This is a BSL command so we must already be in + // BSL mode to execute it. + errl = unlockDevice(); + if (errl != nullptr) + { + break; + } + + // Command to get the version is a BSL command, so it has to be sent as + // a payload. + payload_t payload; + errl = setupPayload(payload, BSL_TX_BSL_VERSION, BPM_ADDRESS_ZERO); + if (errl != nullptr) + { + break; + } + + // Issue the BSL command + errl = issueCommand(BPM_PASSTHROUGH, + payload, + WRITE, + NO_DELAY_EXTERNAL_RESPONSE); + if (errl != nullptr) + { + break; + } + + // Get the result from the BPM. + errl = getResponse(&iv_bslVersion, sizeof(uint8_t)); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::readBslVersion(): " + "Failed to determine BSL Version."); + break; + } + + TRACFCOMP(g_trac_bpm, "Bpm::readBslVersion(): BSL Version is 0x%X", + iv_bslVersion); + } while(0); + + // Reset the device. This will exit BSL mode. + errlHndl_t exitErrl = resetDevice(); + if (exitErrl != nullptr) + { + handleMultipleErrors(errl, exitErrl); + } + + // Exit update mode + exitErrl = exitUpdateMode(); + if (exitErrl != nullptr) + { + handleMultipleErrors(errl, exitErrl); + } + + return errl; +} + +errlHndl_t Bpm::getFwVersion(uint16_t & o_fwVersion) const +{ + TRACFCOMP(g_trac_bpm, ENTER_MRK"Bpm::getFwVersion()"); + errlHndl_t errl = nullptr; + + do { + uint8_t bpmMajor = 0, bpmMinor = 0; + errl = nvdimmReadReg(iv_nvdimm, + ES_FWREV1, + bpmMajor); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::getFwVersion(): " + "Failed to read BPM major version byte"); + errl->collectTrace(BPM_COMP_NAME); + break; + } + + errl = nvdimmReadReg(iv_nvdimm, + ES_FWREV0, + bpmMinor); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::getFwVersion(): " + "Failed to read BPM minor version byte"); + errl->collectTrace(BPM_COMP_NAME); + break; + } + + o_fwVersion = TWO_UINT8_TO_UINT16(bpmMajor, bpmMinor); + + } while(0); + + return errl; +} + +errlHndl_t Bpm::issueCommand(const uint8_t i_bspCommand, + const uint8_t i_command, + const uint8_t i_opType, + const int i_msDelay) +{ + assert(isBspCommand(i_bspCommand), + "i_bspCommand must be a valid BSP command"); + assert(isBclCommand(i_command), + "i_command must be a valid BCL command"); + // i_opType gets set in the BPM_CMD_STATUS register where it is only given + // two bits. So any value above 3 is not valid. + assert(i_opType <= 3, "i_opType can only range between 0 and 3"); + + errlHndl_t errl = nullptr; + + // i_command must be sent in BPM_REG_PAYLOAD_START, but it doesn't need to + // be formatted into a typical payload since the command isn't a BSL + // command. So, just create a payload_t, push_back the command, and let the + // issueCommand function that takes a payload_t parameter handle the rest. + payload_t payloadCommand; + payloadCommand.push_back(i_command); + + errl = issueCommand(i_bspCommand, payloadCommand, i_opType, i_msDelay); + + return errl; +} + +errlHndl_t Bpm::issueCommand(const uint8_t i_command, + payload_t i_payload, + const uint8_t i_opType, + const int i_msDelay) +{ + assert(isBspCommand(i_command), + "i_bspCommand must be a valid BSP command"); + + // i_opType gets set in the BPM_CMD_STATUS register where it is only given + // two bits. So any value above 3 is not valid. + assert(i_opType <= 3, "i_opType can only range between 0 and 3"); + + errlHndl_t errl = nullptr; + + do { + + // Check the full payload size to make sure it's not too large. Add the + // size of the SYNC_BYTE that was dropped during payload creation to + // verify that the full payload sent by the NVDIMM won't exceed the max + // size the BPM is able to receive. + if ((i_payload.size() + SYNC_BYTE_SIZE) > MAX_PAYLOAD_SIZE) + { + uint8_t payloadSize = i_payload.size() + SYNC_BYTE_SIZE; + uint8_t payloadHeaderDataSize = + i_payload[PAYLOAD_HEADER_DATA_LENGTH_INDEX]; + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::issueCommand(): " + "payload size %d exceeds max payload size of %d", + payloadSize, MAX_PAYLOAD_SIZE); + /*@ + * @errortype + * @severity ERRORLOG::ERRL_SEV_PREDICTIVE + * @moduleid BPM_RC::BPM_ISSUE_COMMAND + * @reasoncode BPM_RC::BPM_INVALID_PAYLOAD_SIZE + * @userdata1[00:31] Full Payload Size, including SYNC_BYTE + * @userdata1[32:63] MAX_PAYLOAD_SIZE + * @userdata2[00:31] Payload Header + Data size + * @userdata2[32:63] NVDIMM Target HUID associated with this BPM + * @devdesc The maximum payload size to be sent to the BPM + * was exceeded. + * @custdesc A problem occurred during IPL of the system. + */ + errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_PREDICTIVE, + BPM_RC::BPM_ISSUE_COMMAND, + BPM_RC::BPM_INVALID_PAYLOAD_SIZE, + TWO_UINT16_TO_UINT32(payloadSize, + MAX_PAYLOAD_SIZE), + TWO_UINT32_TO_UINT64( + payloadHeaderDataSize, + TARGETING::get_huid(iv_nvdimm)) + ); + errl->addProcedureCallout(HWAS::EPUB_PRC_HB_CODE, + HWAS::SRCI_PRIORITY_HIGH); + errl->collectTrace(BPM_COMP_NAME); + nvdimmAddPage4Regs(iv_nvdimm,errl); + nvdimmAddVendorLog(iv_nvdimm, errl); + break; + } + + // Load the payload + int i = 0; + for (const auto& byte : i_payload) + { + errl = nvdimmWriteReg(iv_nvdimm, + (BPM_REG_PAYLOAD_START + (i * sizeof(uint8_t))), + byte); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::issueCommand(): " + "Failed to write payload to BPM_REG_PAYLOAD_START"); + errl->collectTrace(BPM_COMP_NAME); + break; + } + + ++i; + } + if (errl != nullptr) + { + break; + } + + // Clear the error status register + errl = nvdimmWriteReg(iv_nvdimm, + BPM_REG_ERR_STATUS, + 0x00); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::issueCommand(): " + "Failed to clear error status register"); + errl->collectTrace(BPM_COMP_NAME); + break; + } + + // Set the payload length. This is the actual length of the payload + // excluding the size of the SYNC_BYTE that was dropped during payload + // creation which is already missing from size(). + uint8_t data = i_payload.size(); + errl = nvdimmWriteReg(iv_nvdimm, + BPM_PAYLOAD_LENGTH, + data); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::issueCommand(): " + "Failed to set payload length"); + errl->collectTrace(BPM_COMP_NAME); + break; + } + + // Setup the command status register + command_status_register_t commandStatus; + commandStatus.bits.Bsp_Cmd_In_Progress = 1; + commandStatus.bits.Operator_Type = i_opType; + errl = nvdimmWriteReg(iv_nvdimm, + BPM_CMD_STATUS, + commandStatus.value); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::issueCommand(): " + "Failed to setup the command status register"); + errl->collectTrace(BPM_COMP_NAME); + break; + } + + // Setup command type. The basically executes the command + errl = nvdimmWriteReg(iv_nvdimm, + BPM_REG_CMD, + i_command); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::issueCommand(): " + "Failed to set the command type. " + "The command was not issued to the BPM"); + errl->collectTrace(BPM_COMP_NAME); + break; + } + + errl = waitForCommandStatusBitReset(commandStatus); + if (errl != nullptr) + { + break; + } + + // If a delay was given then wait for the delay and check the response. + // Otherwise, do not wait and do not check the response. For a list of + // commands and delays, see bpm_update.H for more info. + if (i_msDelay > 0) + { + // Wait the given time in ms. Default 1ms for most commands. + nanosleep(0, i_msDelay * NS_PER_MSEC); + + // Check the response from the BPM. A non-zero response value + // indicates failure. So, assume a failure and check for success. + uint8_t data = 0xFF; + errl = getResponse(&data, sizeof(uint8_t)); + if (errl != nullptr) + { + break; + } + + // If the data read from the response is a non-zero value then the + // issued command failed. + if (data != 0) + { + /*@ + * @errortype + * @severity ERRORLOG::ERRL_SEV_PREDICTIVE + * @moduleid BPM_RC::BPM_ISSUE_COMMAND + * @reasoncode BPM_RC::BPM_BAD_RESPONSE + * @userdata1 The command that failed to execute. + * See bpm_update.H for list of commands. + * @userdata2 NVDIMM Target HUID associated with this BPM + * @devdesc The command sent to the BPM failed. + * @custdesc A problem occurred during IPL of the system. + */ + errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_PREDICTIVE, + BPM_RC::BPM_ISSUE_COMMAND, + BPM_RC::BPM_BAD_RESPONSE, + i_payload[PAYLOAD_COMMAND_INDEX], + TARGETING::get_huid(iv_nvdimm)); + errl->addPartCallout(iv_nvdimm, + HWAS::BPM_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + errl->collectTrace(BPM_COMP_NAME); + nvdimmAddPage4Regs(iv_nvdimm,errl); + nvdimmAddVendorLog(iv_nvdimm, errl); + break; + } + } + + } while(0); + + return errl; +} + +errlHndl_t Bpm::runUpdate(BpmFirmwareLidImage i_fwImage, + BpmConfigLidImage i_configImage) +{ + TRACFCOMP(g_trac_bpm, ENTER_MRK"Bpm::runUpdate(): " + "Running BPM Update for NVDIMM 0x%.8X", + TARGETING::get_huid(iv_nvdimm)); + + errlHndl_t errl = nullptr; + // Assume an update is necessary for the BPM and determine if it isn't. + bool shouldPerformUpdate = true; + + // Get the sys target to check for attribute overrides. + TARGETING::Target* sys = nullptr; + TARGETING::targetService().getTopLevelTarget(sys); + + auto updateOverride = + sys->getAttr<TARGETING::ATTR_BPM_UPDATE_OVERRIDE>(); + uint16_t firmwareOverrideFlag = (updateOverride & 0xFF00); + uint16_t configOverrideFlag = (updateOverride & 0x00FF); + + do { + + // First check if there is a BPM connected + errl = verifyGoodBpmState(); + if (errl != nullptr) + { + // Either there isn't a BPM connected to this NVDIMM or it's not + // functional. Don't bother with updates. + shouldPerformUpdate = false; + iv_attemptAnotherUpdate = false; + break; + } + + // Check the version on the BPM against the version in the image. + uint16_t bpmFwVersion = INVALID_VERSION; + errl = getFwVersion(bpmFwVersion); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::runUpdate(): " + "Could not determine firmware version on BPM " + "Skipping update."); + break; + } + + TRACFCOMP(g_trac_bpm, INFO_MRK"Bpm::runUpdate(): " + "Firmware version on the BPM 0x%.4X, " + "Firmware version of image 0x%.4X.", + bpmFwVersion, i_fwImage.getVersion()); + + if (i_fwImage.getVersion() == bpmFwVersion) + { + shouldPerformUpdate = false; + if (updateOverride == TARGETING::BPM_UPDATE_BEHAVIOR_DEFAULT_ALL) + { + TRACFCOMP(g_trac_bpm, INFO_MRK"Bpm::runUpdate(): " + "Firmware version on the BPM matches the version in " + "the image. Skipping update."); + break; + } + } + + if (updateOverride == TARGETING::BPM_UPDATE_BEHAVIOR_SKIP_ALL) + { + TRACFCOMP(g_trac_bpm, INFO_MRK"Bpm::runUpdate(): " + "ATTR_BPM_UPDATE_OVERRIDE set to SKIP_ALL. " + "Skipping update."); + break; + } + + // Depending on the BSL version a CRC check may be necessary + errl = readBslVersion(); + if (errl != nullptr) + { + break; + } + + // If the BSL version read from the BPM isn't a supported version then + // don't perform the updates as the update flow may have changed between + // BSL versions. + if (iv_bslVersion != BSL_VERSION_1_4) + { + TRACFCOMP(g_trac_bpm, "Bpm::runUpdate(): " + "Unsupported BSL Version 0x%.2X detected on BPM. " + "Cancelling Update."); + + break; + } + + if ((shouldPerformUpdate + || (firmwareOverrideFlag == TARGETING::BPM_UPDATE_BEHAVIOR_FORCE_FW)) + && !(firmwareOverrideFlag == TARGETING::BPM_UPDATE_BEHAVIOR_SKIP_FW)) + { + if (firmwareOverrideFlag == TARGETING::BPM_UPDATE_BEHAVIOR_FORCE_FW) + { + TRACFCOMP(g_trac_bpm, INFO_MRK"Bpm::runUpdate(): " + "ATTR_BPM_UPDATE_OVERRIDE set to force firmware " + "portion of BPM updates. Running Firmware Update..."); + } + + errl = runFirmwareUpdates(i_fwImage); + if (errl != nullptr) + { + break; + } + } + else + { + if (firmwareOverrideFlag == TARGETING::BPM_UPDATE_BEHAVIOR_SKIP_FW) + { + TRACFCOMP(g_trac_bpm, INFO_MRK"Bpm::runUpdate(): " + "ATTR_BPM_UPDATE_OVERRIDE set to skip firmware " + "portion of BPM updates. Skipping Firmware Update..."); + } + else + { + TRACFCOMP(g_trac_bpm, INFO_MRK"Bpm::runUpdate(): " + "Firmware Data on BPM already up-to-date. " + "Skipping Firmware Update..."); + } + } + + if ((shouldPerformUpdate + || (configOverrideFlag == TARGETING::BPM_UPDATE_BEHAVIOR_FORCE_CONFIG)) + && !(configOverrideFlag == TARGETING::BPM_UPDATE_BEHAVIOR_SKIP_CONFIG)) + { + if (configOverrideFlag == TARGETING::BPM_UPDATE_BEHAVIOR_FORCE_CONFIG) + { + TRACFCOMP(g_trac_bpm, INFO_MRK"Bpm::runUpdate(): " + "ATTR_BPM_UPDATE_OVERRIDE set to force config " + "portion of BPM updates. Running Config Update..."); + } + errl = runConfigUpdates(i_configImage); + if (errl != nullptr) + { + break; + } + } + else + { + if (configOverrideFlag == TARGETING::BPM_UPDATE_BEHAVIOR_SKIP_CONFIG) + { + TRACFCOMP(g_trac_bpm, INFO_MRK"Bpm::runUpdate(): " + "ATTR_BPM_UPDATE_OVERRIDE set to skip config " + "portion of BPM updates. Skipping Config Update..."); + } + else + { + TRACFCOMP(g_trac_bpm, INFO_MRK"Bpm::runUpdate(): " + "Configuration Data on BPM already up-to-date. " + "Skipping Config Update..."); + } + } + + } while(0); + + if ((shouldPerformUpdate + || (configOverrideFlag == TARGETING::BPM_UPDATE_BEHAVIOR_FORCE_CONFIG) + || (firmwareOverrideFlag == TARGETING::BPM_UPDATE_BEHAVIOR_FORCE_FW)) + && (updateOverride != TARGETING::BPM_UPDATE_BEHAVIOR_SKIP_ALL)) + { + // Reset controller and unlock encryption if necessary + errlHndl_t exitErrl = nvdimmResetController(iv_nvdimm); + if (exitErrl != nullptr) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::runUpdate() " + "Couldn't reset NVDIMM controller."); + handleMultipleErrors(errl, exitErrl); + } + + // If the update was successful then we must wait for 15 seconds before + // polling the status of the BPM since it has to finish updating its + // firmware and resetting. + TRACFCOMP(g_trac_bpm, "Bpm::runUpdate(): " + "Wait for the BPM to finish update and reset procedure, " + "sleep for 15 seconds"); + longSleep(15); + + // Poll SCAP_STATUS register for BPM state before we check final + // firmware version. + exitErrl = verifyGoodBpmState(); + if (exitErrl != nullptr) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::runUpdate(): " + "Could not verify that BPM was present and enabled!"); + handleMultipleErrors(errl, exitErrl); + } + + uint16_t bpmFwVersion = INVALID_VERSION; + exitErrl = getFwVersion(bpmFwVersion); + if (exitErrl != nullptr) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::runUpdate(): " + "Could not determine firmware version on the BPM"); + handleMultipleErrors(errl, exitErrl); + } + + TRACFCOMP(g_trac_bpm, INFO_MRK"Bpm::runUpdate(): " + "Firmware version on the BPM 0x%.4X, " + "Firmware version of image 0x%.4X.", + bpmFwVersion, i_fwImage.getVersion()); + + if (i_fwImage.getVersion() == bpmFwVersion) + { + TRACFCOMP(g_trac_bpm, INFO_MRK"Bpm::runUpdate(): " + "Firmware version on the BPM matches the version in the " + "image. Firmware Update Successful."); + iv_attemptAnotherUpdate = false; + } + else + { + // Attempt another update if one hasn't already been attempted. + setAttemptAnotherUpdate(); + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::runUpdate(): " + "Version on BPM didn't match image. %s ", + iv_attemptAnotherUpdate ? + "Attempt another update..." + : "Attempts to update the BPM have failed."); + if (iv_attemptAnotherUpdate == false) + { + /*@ + * @errortype + * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE + * @moduleid BPM_RC::BPM_RUN_FW_UPDATES + * @reasoncode BPM_RC::BPM_VERSION_MISMATCH + * @userdata1[00:31] Version on the BPM + * @userdata1[32:63] Version of the flash image + * @userdata2 NVDIMM Target HUID associated with this BPM + * @devdesc The version on the BPM didn't match the + * version in the flash image. + * @custdesc A problem occurred during IPL of the system. + */ + exitErrl = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + BPM_RC::BPM_RUN_FW_UPDATES, + BPM_RC::BPM_VERSION_MISMATCH, + TWO_UINT32_TO_UINT64(bpmFwVersion, + i_fwImage.getVersion()), + TARGETING::get_huid(iv_nvdimm)); + exitErrl->collectTrace(BPM_COMP_NAME); + handleMultipleErrors(errl, exitErrl); + } + } + + TRACFCOMP(g_trac_bpm, EXIT_MRK"Bpm::runUpdate(): " + "Concluding BPM Update for NVDIMM 0x%.8X %s", + TARGETING::get_huid(iv_nvdimm), + (errl != nullptr) ? "with errors" : "without errors"); + } + + // An update has been attempted at least once. Set member variable to true + // to dictate future update attempts. This variable should only be set at + // the end of the update procedure in order to properly control future + // update attempts. + iv_updateAttempted = true; + + if (errl == nullptr) + { + /*@ + * @errortype + * @severity ERRORLOG::ERRL_SEV_INFORMATIONAL + * @moduleid BPM_RC::BPM_RUN_UPDATE + * @reasoncode BPM_RC::BPM_UPDATE_SUCCESSFUL + * @userdata1 NVDIMM Target HUID associated with this BPM + * @devdesc BPM Update finished without errors. + * @custdesc Informational log associated with DIMM updates. + */ + errlHndl_t infoErrl = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_INFORMATIONAL, + BPM_RC::BPM_RUN_UPDATE, + BPM_RC::BPM_UPDATE_SUCCESSFUL, + TARGETING::get_huid(iv_nvdimm)); + infoErrl->collectTrace(BPM_COMP_NAME); + ERRORLOG::errlCommit(infoErrl, BPM_COMP_ID); + } + + return errl; +} + +errlHndl_t Bpm::inUpdateMode() +{ + TRACFCOMP(g_trac_bpm, ENTER_MRK"Bpm::inUpdateMode()"); + errlHndl_t errl = nullptr; + + do { + + errl = issueCommand(BPM_LOCAL, + BCL_IS_UPDATE_IN_PROGRESS, + READ, + NO_DELAY_NO_RESPONSE); + if (errl != nullptr) + { + break; + } + + uint8_t isUpdateInProgress = 0; + errl = nvdimmReadReg(iv_nvdimm, + BPM_REG_ERR_STATUS, + isUpdateInProgress); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::inUpdateMode(): " + "Failed to read error status register"); + errl->collectTrace(BPM_COMP_NAME); + nvdimmAddVendorLog(iv_nvdimm, errl); + break; + } + + if (!isUpdateInProgress) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::inUpdateMode(): " + "Failed to enter update mode"); + /*@ + * @errortype + * @severity ERRORLOG::ERRL_SEV_PREDICTIVE + * @moduleid BPM_RC::BPM_IN_UPDATE_MODE + * @reasoncode BPM_RC::BPM_UPDATE_MODE_VERIFICATION_FAIL + * @userdata1 NVDIMM Target HUID associated with this BPM + * @devdesc Failed to verify update mode was entered using + * the BSL interface. + * @custdesc A problem occurred during IPL of the system. + */ + errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_PREDICTIVE, + BPM_RC::BPM_IN_UPDATE_MODE, + BPM_RC::BPM_UPDATE_MODE_VERIFICATION_FAIL, + TARGETING::get_huid(iv_nvdimm)); + errl->addPartCallout(iv_nvdimm, + HWAS::BPM_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + errl->collectTrace(BPM_COMP_NAME); + nvdimmAddPage4Regs(iv_nvdimm,errl); + nvdimmAddVendorLog(iv_nvdimm, errl); + break; + } + + } while(0); + + return errl; +} + +errlHndl_t Bpm::enterUpdateMode() +{ + TRACFCOMP(g_trac_bpm, ENTER_MRK"Bpm::enterUpdateMode()"); + errlHndl_t errl = nullptr; + + do { + + // Disable write protection on the BPM. Otherwise, we can't write the + // magic values that enable the nvdimm-bpm interface. + errl = disableWriteProtection(); + if (errl != nullptr) + { + break; + } + + // Write the magic values to enable nvdimm-bpm interface + errl = writeToMagicRegisters(UPDATE_MODE_MAGIC_VALUES); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::enterUpdateMode(): " + "Failed to write magic numbers that enable " + "update mode"); + break; + } + + TRACFCOMP(g_trac_bpm, "Bpm::enterUpdateMode(): " + "Issuing BPM_LOCAL BCL_START_UPDATE command."); + + errl = issueCommand(BPM_LOCAL, + BCL_START_UPDATE, + WRITE, + NO_DELAY_NO_RESPONSE); + if (errl != nullptr) + { + break; + } + + nanosleep(2,0); + + /*@ + * @errortype + * @severity ERRORLOG::ERRL_SEV_INFORMATIONAL + * @moduleid BPM_RC::BPM_START_UPDATE + * @reasoncode BPM_RC::BPM_ENTER_UPDATE_MODE + * @userdata1 NVDIMM Target HUID associated with this BPM + * @devdesc BPM has entered update mode. + * @custdesc Informational log associated with DIMM updates. + */ + errlHndl_t infoErrl = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_INFORMATIONAL, + BPM_RC::BPM_START_UPDATE, + BPM_RC::BPM_ENTER_UPDATE_MODE, + TARGETING::get_huid(iv_nvdimm)); + infoErrl->addPartCallout(iv_nvdimm, + HWAS::BPM_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + infoErrl->collectTrace(BPM_COMP_NAME); + nvdimmAddVendorLog(iv_nvdimm, infoErrl); + nvdimmAddPage4Regs(iv_nvdimm, infoErrl); + ERRORLOG::errlCommit(infoErrl, BPM_COMP_ID); + + } while(0); + + return errl; +} + +errlHndl_t Bpm::exitUpdateMode() +{ + TRACFCOMP(g_trac_bpm, ENTER_MRK"Bpm::exitUpdateMode()"); + errlHndl_t errl = nullptr; + + do { + + errl = writeToMagicRegisters(UPDATE_MODE_MAGIC_VALUES); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::exitUpdateMode(): " + "Failed to write the update magic values to " + " be able to send BPM_LOCAL commands."); + break; + } + + errl = issueCommand(BPM_LOCAL, + BCL_IS_UPDATE_IN_PROGRESS, + READ, + NO_DELAY_NO_RESPONSE); + if (errl != nullptr) + { + break; + } + + uint8_t isUpdateInProgress = 0; + errl = nvdimmReadReg(iv_nvdimm, + BPM_REG_ERR_STATUS, + isUpdateInProgress); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::exitUpdateMode(): " + "Failed to read BPM_REG_ERR_STATUS register to determine " + "if BPM is in update mode."); + errl->collectTrace(BPM_COMP_NAME); + break; + } + + // Sending the exit update command when the BPM isn't in update mode can + // cause unpredicatable behavior and errors. + if (isUpdateInProgress) + { + errl = issueCommand(BPM_LOCAL, + BCL_END_UPDATE, + WRITE, + NO_DELAY_NO_RESPONSE); + if (errl != nullptr) + { + break; + } + } + else + { + TRACFCOMP(g_trac_bpm, "Bpm::exitUpdateMode(): " + "Not in update mode. " + "Exit update command will not be sent."); + } + + // Write back the production magic values + errl = writeToMagicRegisters(PRODUCTION_MAGIC_VALUES); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::exitUpdateMode(): " + "Failed to write the production magic values to " + "disable update mode."); + break; + } + + /*@ + * @errortype + * @severity ERRORLOG::ERRL_SEV_INFORMATIONAL + * @moduleid BPM_RC::BPM_END_UPDATE + * @reasoncode BPM_RC::BPM_EXIT_UPDATE_MODE + * @userdata1 NVDIMM Target HUID associated with this BPM + * @devdesc BPM has exited update mode. + * @custdesc Informational log associated with DIMM updates. + */ + errlHndl_t infoErrl = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_INFORMATIONAL, + BPM_RC::BPM_END_UPDATE, + BPM_RC::BPM_EXIT_UPDATE_MODE, + TARGETING::get_huid(iv_nvdimm)); + infoErrl->addPartCallout(iv_nvdimm, + HWAS::BPM_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + infoErrl->collectTrace(BPM_COMP_NAME); + nvdimmAddVendorLog(iv_nvdimm, infoErrl); + nvdimmAddPage4Regs(iv_nvdimm, infoErrl); + ERRORLOG::errlCommit(infoErrl, BPM_COMP_ID); + + } while(0); + + return errl; +} + +errlHndl_t Bpm::updateFirmware(BpmFirmwareLidImage i_image) +{ + TRACFCOMP(g_trac_bpm, ENTER_MRK"Bpm::updateFirmware()"); + errlHndl_t errl = nullptr; + + // The reset vector address is near the end of the firmware section. + // We must do a special operation on it when it shows up during the update. + const uint16_t RESET_VECTOR_ADDRESS = 0xFFFE; + + bool mainAddressEncountered = false; + + // Get the number of blocks in the image + const uint16_t NUMBER_OF_BLOCKS = i_image.getNumberOfBlocks(); + + char const * data = + reinterpret_cast<char const *>(i_image.getFirstBlock()); + + firmware_image_block_t const * block = + reinterpret_cast<firmware_image_block_t const *> + (data); + + for(size_t i = 0; i < NUMBER_OF_BLOCKS; ++i) + { + // This is done once at the main program address. + if ( ((block->iv_addressOffset == MAIN_PROGRAM_ADDRESS) + || (block->iv_addressOffset == MAIN_PROGRAM_ADDRESS_ALT)) + && !mainAddressEncountered) + { + // Only execute this once. + mainAddressEncountered = true; + + // Save the firmware start address for later. This will be needed + // for the final CRC check when the update is completed. + iv_firmwareStartAddress = block->iv_addressOffset; + + payload_t payload; + errl = setupPayload(payload, + BSL_MASS_ERASE, + iv_firmwareStartAddress); + if (errl != nullptr) + { + break; + } + + errl = issueCommand(BPM_PASSTHROUGH, + payload, + WRITE, + ERASE_FIRMWARE_DELAY); + if (errl != nullptr) + { + break; + } + + TRACFCOMP(g_trac_bpm, "Bpm::updateFirmware(): " + "Performing BSL_MASS_ERASE on BPM, sleep for 5 seconds."); + longSleep(5); + + TRACFCOMP(g_trac_bpm, "Bpm::updateFirmware(): " + "Begin writing flash image to BPM " + "with a starting address of 0x%.4X", + iv_firmwareStartAddress); + + } + + if (block->iv_addressOffset % 0x400 == 0) + { + TRACFCOMP(g_trac_bpm, "Bpm::updateFirmware(): " + "Writing to address offset 0x%.4X. " + "Firmware blocks written: %d; Remaining: %d", + block->iv_addressOffset, + i, (NUMBER_OF_BLOCKS - i)); + } + + // Construct the payload for this block in the image + payload_t payload; + errl = setupPayload(payload, block, BSL_RX_DATA_BLOCK); + if (errl != nullptr) + { + break; + } + + if (block->iv_addressOffset == RESET_VECTOR_ADDRESS) + { + TRACFCOMP(g_trac_bpm, "Bpm::updateFirmware(): " + "Encountered RESET_VECTOR_ADDRESS 0x%.4X. " + "Attempt to write RESET_VECTOR to BPM up to %d times.", + RESET_VECTOR_ADDRESS, + MAX_RETRY); + // Attempting to BSL_VERIFY_BLOCK on the reset vector data will + // fail. To verify that this data is written correctly we will check + // the response packet sent by the BPM. + const uint8_t RESET_VECTOR_RECEIVE_SUCCESS = 0x80; + uint8_t retry = 1; + do + { + // Issue the write command to the BPM. + // The RESET_VECTOR is special in that its response is checked + // externally. + errl = issueCommand(BPM_PASSTHROUGH, + payload, + WRITE, + NO_DELAY_EXTERNAL_RESPONSE); + if (errl != nullptr) + { + break; + } + + // Get the response packet and verify that the status is + // RESET_VECTOR_RECEIVE_SUCCESS. + // + // Any status besides RESET_VECTOR_RECEIVE_SUCCESS is considered + // a fail. So, assume a failure and check. + uint8_t status = 0xFF; + errl = getResponse(&status, + sizeof(uint8_t)); + if (errl != nullptr) + { + break; + } + + if (status != RESET_VECTOR_RECEIVE_SUCCESS) + { + TRACFCOMP(g_trac_bpm, "Bpm::updateFirmware(): " + "status %d from BPM was not " + "RESET_VECTOR_RECEIVE_SUCCESS value of %d. " + "Retrying...", + status, + RESET_VECTOR_RECEIVE_SUCCESS); + + if (++retry > MAX_RETRY) + { + TRACFCOMP(g_trac_bpm, "Bpm::updateFirmware(): " + "Never received RESET_VECTOR_RECEIVE_SUCCESS " + "status from BPM in three attempts. " + "Aborting Update"); + /*@ + * @errortype + * @severity ERRORLOG::ERRL_SEV_PREDICTIVE + * @moduleid BPM_RC::BPM_UPDATE_FIRMWARE + * @reasoncode BPM_RC::BPM_RESET_VECTOR_NEVER_RECEIVED + * @userdata1 NVDIMM Target HUID associated with this BPM + * @devdesc RESET_VECTOR_RECEIVE_SUCCESS status was not + * received in three attempts. + * @custdesc A problem occurred during IPL of the system. + */ + errl = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_PREDICTIVE, + BPM_RC::BPM_UPDATE_FIRMWARE, + BPM_RC::BPM_RESET_VECTOR_NEVER_RECEIVED, + TARGETING::get_huid(iv_nvdimm)); + errl->addPartCallout(iv_nvdimm, + HWAS::BPM_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + errl->collectTrace(BPM_COMP_NAME); + nvdimmAddPage4Regs(iv_nvdimm,errl); + nvdimmAddVendorLog(iv_nvdimm, errl); + + // Change the state of iv_attemptAnotherUpdate to signal + // if another update attempt should occur. + setAttemptAnotherUpdate(); + + break; + } + } + else + { + // RESET_VECTOR was written and received successfully. + // Exit retry loop. + break; + } + + // Sleep for 0.001 second before attempting again. + nanosleep(0, 1 * NS_PER_MSEC); + + } while(retry <= MAX_RETRY); + if (errl != nullptr) + { + break; + } + } + else + { + // Attempt to write the data using a retry loop. This will also + // verify that the data was correctly written to the BPM. + errl = blockWrite(payload); + if (errl != nullptr) + { + break; + } + } + + // Move to the next block + // iv_blocksize doesn't include the sizeof itself. So, add another byte + // for it. + data += block->iv_blockSize + sizeof(uint8_t); + block = reinterpret_cast<firmware_image_block_t const *>(data); + } + + TRACFCOMP(g_trac_bpm, EXIT_MRK"Bpm::updateFirmware(): " + "Firmware flash image write and verification completed " + "%s", + (errl == nullptr) ? "without errors" : "with errors"); + + return errl; +} + +errlHndl_t Bpm::updateConfig() +{ + TRACFCOMP(g_trac_bpm, ENTER_MRK"Bpm::updateConfig()"); + errlHndl_t errl = nullptr; + + do { + + // Erase Segment D on the BPM via the BSL interface. + errl = eraseSegment(SEGMENT_D_CODE); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::updateConfig(): " + "Failed to erase Segment D."); + break; + } + + // Write the updated Segment D buffer to the BPM via the BSL interface. + errl = writeSegment(iv_segmentD, SEGMENT_D_CODE); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::updateConfig(): " + "Failed to write Segment D."); + break; + } + + + // Erase Segment B on the BPM via the BSL interface. + errl = eraseSegment(SEGMENT_B_CODE); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::updateConfig(): " + "Failed to erase Segment B."); + break; + } + + // Write the updated Segment B buffer to the BPM via the BSL interface. + errl = writeSegment(iv_segmentB, SEGMENT_B_CODE); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::updateConfig(): " + "Failed to write Segment B."); + break; + } + + } while(0); + + return errl; +} + +errlHndl_t Bpm::enterBootstrapLoaderMode() +{ + TRACFCOMP(g_trac_bpm, ENTER_MRK"Bpm::enterBootstrapLoaderMode()"); + errlHndl_t errl = nullptr; + + do { + + // Entering BSL mode depends on the state of the BPM and it may need + // several retries in order to successfully enter BSL mode. + int retry = 5; + bool inBslMode = false; + + while (retry != 0) + { + + errl = issueCommand(BPM_LOCAL, + BCL_IS_BSL_MODE, + WRITE, + NO_DELAY_NO_RESPONSE); + if (errl != nullptr) + { + break; + } + + uint8_t data = 0; + errl = nvdimmReadReg(iv_nvdimm, + BPM_REG_ERR_STATUS, + data); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::enterBootstrapLoaderMode(): " + "Failed to read BPM_REG_ERR_STATUS to verify that " + "BSL mode was enabled."); + errl->collectTrace(BPM_COMP_NAME); + break; + } + // data will be 1 if the BPM successfully entered BSL mode. + if (data == 1) + { + inBslMode = true; + TRACFCOMP(g_trac_bpm, "Bpm::enterBootstrapLoaderMode(): " + "BSL Mode entered, sleep for 5 seconds."); + longSleep(5); + break; + } + + // Sleep for 0.001 second. + nanosleep(0, 1 * NS_PER_MSEC); + + errl = issueCommand(BPM_LOCAL, + BCL_ENTER_BSL_MODE, + WRITE, + NO_DELAY_NO_RESPONSE); + if (errl != nullptr) + { + break; + } + + TRACUCOMP(g_trac_bpm, "Bpm::enterBootstrapLoaderMode(): " + "Unable to enter BSL Mode, retries remaining %d. " + "Sleep for 2 seconds before trying again.", + (retry - 1)); + nanosleep(2,0); + --retry; + + } + if (errl != nullptr) + { + break; + } + + if (!inBslMode) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::enterBootstrapLoaderMode(): " + "Failed to enter BSL mode on the BPM"); + /*@ + * @errortype + * @severity ERRORLOG::ERRL_SEV_PREDICTIVE + * @moduleid BPM_RC::BPM_ENTER_BSL_MODE + * @reasoncode BPM_RC::BPM_FAILED_TO_ENTER_BSL_MODE + * @userdata1[0:63] NVDIMM Target HUID associated with this BPM + * @devdesc Failed to enter BSL mode after several attempts. + * @custdesc A problem occurred during IPL of the system. + */ + errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_PREDICTIVE, + BPM_RC::BPM_ENTER_BSL_MODE, + BPM_RC::BPM_FAILED_TO_ENTER_BSL_MODE, + TARGETING::get_huid(iv_nvdimm)); + errl->addPartCallout(iv_nvdimm, + HWAS::BPM_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + nvdimmAddVendorLog(iv_nvdimm, errl); + errl->collectTrace(BPM_COMP_NAME); + nvdimmAddPage4Regs(iv_nvdimm,errl); + break; + } + + } while(0); + + return errl; +} + +errlHndl_t Bpm::setupPayload(payload_t & o_payload, + const uint8_t i_command, + const uint16_t i_address, + const uint8_t i_data[], + const size_t i_length) +{ + // Enforce sane inputs + assert(( (i_data == nullptr && i_length == 0) + || (i_data != nullptr && i_length != 0)), + "if i_length is non-zero then i_data must not be nullptr, otherwise i_data must be nullptr."); + assert(isBslCommand(i_command), + "i_command must be a valid BSL command"); + + errlHndl_t errl = nullptr; + + // Calculate the block size. + size_t blockSize = sizeof(uint16_t) + i_length; + + // Allocate memory for the block + firmware_image_block_t* myBlock = reinterpret_cast<firmware_image_block_t*>( + malloc(sizeof(firmware_image_block_t) + i_length)); + + // Setup the block "header" info + myBlock->iv_blockSize = blockSize; + myBlock->iv_addressOffset = i_address; + + // Copy the data if any exists. + if (i_data != nullptr) + { + memcpy(&myBlock->iv_data, i_data, i_length); + } + + // Setup the return payload + errl = setupPayload(o_payload, myBlock, i_command); + + // Block is no longer needed. + free(myBlock); + + return errl; +} + +errlHndl_t Bpm::setupPayload(payload_t & o_payload, + const firmware_image_block_t * i_block, + const uint8_t i_command) +{ + assert(i_block != nullptr, "i_block must not be nullptr."); + assert(isBslCommand(i_command), + "i_command must be a valid BSL command"); + + errlHndl_t errl = nullptr; + + // The data size in the block is the total block size + // minus the 2 bytes for the address offset. + const uint8_t blockDataSize = i_block->iv_blockSize - sizeof(uint16_t); + + // The header plus payload data section size. This excludes the address + // offset, extra bytes, and CRC bytes. + const uint8_t headerDataSize = PAYLOAD_HEADER_SIZE + blockDataSize; + + do { + + if (blockDataSize > MAX_PAYLOAD_DATA_SIZE) + { + TRACFCOMP(g_trac_bpm, ERR_MRK + "Bpm::setupPayload(): Block Data Size %d exceeds max payload " + "size of %d", + blockDataSize, + MAX_PAYLOAD_DATA_SIZE); + /*@ + * @errortype + * @severity ERRORLOG::ERRL_SEV_PREDICTIVE + * @moduleid BPM_RC::BPM_SETUP_PAYLOAD + * @reasoncode BPM_RC::BPM_INVALID_PAYLOAD_DATA_SIZE + * @userdata1[0:7] Block Data Size + * @userdata1[8:15] MAX_PAYLOAD_DATA_SIZE + * @userdata2[0:63] NVDIMM Target HUID associated with this BPM + * @devdesc Failed to enter BSL mode after several attempts. + * @custdesc A problem occurred during IPL of the system. + */ + errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_PREDICTIVE, + BPM_RC::BPM_SETUP_PAYLOAD, + BPM_RC::BPM_INVALID_PAYLOAD_DATA_SIZE, + TWO_UINT8_TO_UINT16(blockDataSize, + MAX_PAYLOAD_DATA_SIZE), + TARGETING::get_huid(iv_nvdimm)); + errl->collectTrace(BPM_COMP_NAME); + nvdimmAddPage4Regs(iv_nvdimm,errl); + nvdimmAddVendorLog(iv_nvdimm, errl); + break; + } + + // Create the payload with the exact size needed. + payload_t payload(MAX_PAYLOAD_OTHER_DATA_SIZE + blockDataSize); + + // Instead of using push_back, use a pointer to an element in the vector. + // Since the size of the vector is declared and intialized to zero ahead of + // time push_back will not work. Also, some of the data is larger than + // uint8_t and so it's easier to just use memcpy for insertion. + // NOTE: Because push_back isn't being used the size() of the vector doesn't + // change along with the data being added to the vector. This was + // corrected by explicitly setting the payload size in the constructor + // call above. + uint8_t * payloadIterator = payload.data(); + + // According to SMART, we must supply the header + data size twice. + uint8_t header[PAYLOAD_HEADER_SIZE] = { SYNC_BYTE, + i_command, + headerDataSize, + headerDataSize }; + + memcpy(payloadIterator, &header, PAYLOAD_HEADER_SIZE); + + // Move past the header + payloadIterator += PAYLOAD_HEADER_SIZE; + + // Write the address offset in little endian form. + uint16_t addressLE = htole16(i_block->iv_addressOffset); + uint8_t* addressOffset = reinterpret_cast<uint8_t*>(&addressLE); + memcpy(payloadIterator, addressOffset, sizeof(uint16_t)); + + // Move past the address + payloadIterator += sizeof(uint16_t); + + // The extra bytes vary based on the given command. + // These are the extra bytes for their corresponding bootstrap loader + // commands. They are arranged in little endian form so that no byte + // swapping is required. + const uint8_t BSL_ERASE_SEGMENT_EXTRA_BYTES[] = {0x02, 0xA5}; + const uint8_t BSL_MASS_ERASE_EXTRA_BYTES[] = {0x06, 0xA5}; + switch(i_command) + { + case BSL_ERASE_SEGMENT: + { + memcpy(payloadIterator, + &BSL_ERASE_SEGMENT_EXTRA_BYTES, + sizeof(uint16_t)); + + break; + } + case BSL_MASS_ERASE: + { + memcpy(payloadIterator, + &BSL_MASS_ERASE_EXTRA_BYTES, + sizeof(uint16_t)); + break; + } + default: + { + // Give the size of the data section as a uint16_t in little + // endian form. + uint8_t dataLength[] = {blockDataSize, 0x0}; + memcpy(payloadIterator, &dataLength, sizeof(uint16_t)); + break; + } + } + + // Move past the payload's extra bytes. + payloadIterator += sizeof(uint16_t); + + if (blockDataSize > 0) + { + // Copy the payload data from the LID image block to the payload's data + // section. + memcpy(payloadIterator, &i_block->iv_data, blockDataSize); + + // Move past the payload's data section. + payloadIterator += blockDataSize; + } + + // Calculate the CRC bytes + // Pass in the size of the payload excluding the two reserved bytes + // for the CRC. + uint16_t crc = htole16(crc16_calc(payload.data(), payload.size()-2)); + + // Write the CRC bytes + uint8_t* crcBytes = reinterpret_cast<uint8_t*>(&crc); + memcpy(payloadIterator, crcBytes, sizeof(uint16_t)); + + // The sync byte is automatically sent by the NVDIMM to the BPM so + // including it in the payload isn't necessary. It is only needed to + // calculate the CRC bytes. + payload.erase(payload.begin()); + // Force the returned payload to have the exact capacity and size of the + // payload. + o_payload.swap(payload); + + } while(0); + + return errl; +} + +errlHndl_t Bpm::unlockDevice() +{ + TRACFCOMP(g_trac_bpm, ENTER_MRK"Bpm::unlockDevice()"); + errlHndl_t errl = nullptr; + + do { + + // This is a BSL command, so it must be formatted into a payload. + payload_t payload; + + // This command must send the password in order to unlock the device. + errl = setupPayload(payload, + BSL_RX_PASSWORD, + BPM_ADDRESS_ZERO, + BPM_PASSWORD, + BPM_PASSWORD_LENGTH); + if (errl != nullptr) + { + break; + } + + errl = issueCommand(BPM_PASSTHROUGH, payload, WRITE); + if (errl != nullptr) + { + break; + } + + } while(0); + + return errl; +} + +errlHndl_t Bpm::resetDevice() +{ + TRACFCOMP(g_trac_bpm, ENTER_MRK"Bpm::resetDevice()"); + errlHndl_t errl = nullptr; + + do { + + // Verify we are in BSL mode by checking SCAP_STATUS because if we aren't + // then we don't need to do anything. + scap_status_register_t status; + errl = nvdimmReadReg(iv_nvdimm, + SCAP_STATUS, + status.full); + if (errl != nullptr) + { + errl->collectTrace(BPM_COMP_NAME); + break; + } + + if (status.bit.Bpm_Bsl_Mode) + { + // This is a BSL command, so it must be formatted into a payload. + payload_t payload; + errl = setupPayload(payload, BSL_RESET_DEVICE, BPM_ADDRESS_ZERO); + if (errl != nullptr) + { + break; + } + + // Despite this being a BSL command we cannot check the response + // because the BPM will either be offline and cannot respond or + // the command will have completed and we won't be in BSL mode + // anymore and therefor shouldn't check the response. + errl = issueCommand(BPM_PASSTHROUGH, + payload, + WRITE, + NO_DELAY_NO_RESPONSE); + if (errl != nullptr) + { + break; + } + + // If we wait less than 15 seconds for the reset to occur it is + // possible that BPM won't be ready for more commands via the NVDIMM + TRACFCOMP(g_trac_bpm, "Bpm::resetDevice(): " + "Resetting BPM for NVDIMM 0x%.8X, sleep for 15 seconds.", + TARGETING::get_huid(iv_nvdimm)); + longSleep(15); + } + else + { + TRACFCOMP(g_trac_bpm, "Bpm::resetDevice(): " + "Not in BSL Mode. Don't send the reset command."); + break; + } + + } while(0); + + return errl; +} + +errlHndl_t Bpm::readViaScapRegister(uint8_t const i_reg, uint8_t & io_data) +{ + TRACUCOMP(g_trac_bpm, ENTER_MRK"Bpm::readViaScapRegister()"); + errlHndl_t errl = nullptr; + + do { + + // Wait for the SCAP_STATUS Busy bit to be zero. + errl = waitForBusyBit(); + if (errl != nullptr) + { + break; + } + + // Write to SCAP register which register we're attempting to access on + // the BPM + errl = nvdimmWriteReg(iv_nvdimm, + SCAP_REG, + i_reg); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::readViaScapRegister(): " + "Failed to set SCAP_REG to register 0x%.2X", + i_reg); + errl->collectTrace(BPM_COMP_NAME); + break; + } + + // Wait for the SCAP_STATUS Busy bit to be zero. + errl = waitForBusyBit(); + if (errl != nullptr) + { + break; + } + + // Read out the data from the requested register + errl = nvdimmReadReg(iv_nvdimm, + SCAP_DATA, + io_data); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "BPM::readViaScapRegister(): " + "Failed to read data from SCAP_DATA for register 0x%.2X.", + i_reg); + errl->collectTrace(BPM_COMP_NAME); + break; + } + + } while(0); + + return errl; +} + +errlHndl_t Bpm::writeViaScapRegister(uint8_t const i_reg, uint8_t const i_data) +{ + TRACUCOMP(g_trac_bpm, ENTER_MRK"Bpm::writeViaScapRegister()"); + errlHndl_t errl = nullptr; + + do { + + // The SCAP_REG and SCAP_DATA registers require a few retries to get the + // values to stick. This loop sets SCAP_REG to i_reg + uint8_t retry = 0; + uint8_t data = 0; + do { + + // Wait for the SCAP_STATUS Busy bit to be zero. + errl = waitForBusyBit(); + if (errl != nullptr) + { + break; + } + + // Write to SCAP register which register we're attempting to access + // on the BPM + errl = nvdimmWriteReg(iv_nvdimm, + SCAP_REG, + i_reg); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::writeViaScapRegister(): " + "Failed to set SCAP_REG to register 0x%.2X", + i_reg); + errl->collectTrace(BPM_COMP_NAME); + break; + } + + // Wait for the SCAP_STATUS Busy bit to be zero. + errl = waitForBusyBit(); + if (errl != nullptr) + { + break; + } + + // Wait 100ms + nanosleep(0, 100 * NS_PER_MSEC); + + errl = nvdimmReadReg(iv_nvdimm, + SCAP_REG, + data); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "BPM::writeViaScapRegister(): " + "Failed to read from SCAP_REG to verify that " + "requested register 0x%.2X was written successfully.", + i_reg); + errl->collectTrace(BPM_COMP_NAME); + break; + } + + if (data == i_reg) + { + TRACUCOMP(g_trac_bpm, "Bpm::writeViaScapRegister(): " + "REG 0x%X was successfully written to SCAP_REG 0x434. " + "Stop retries.", + i_reg); + break; + } + + } while(++retry < MAX_RETRY); + if (errl != nullptr) + { + break; + } + if ((retry >= MAX_RETRY) && (data != i_reg)) + { + /*@ + * @errortype + * @severity ERRORLOG::ERRL_SEV_PREDICTIVE + * @moduleid BPM_RC::BPM_WRITE_VIA_SCAP + * @reasoncode BPM_RC::BPM_EXCEEDED_RETRY_LIMIT_REG + * @userdata1[0:31] The register that we were attempting to write to + * SCAP_REG. + * @userdata1[32:63] The data that was found in the register on the + * final attempt. + * @userdata2 NVDIMM Target HUID associated with this BPM + * @devdesc The command sent to the BPM failed. + * @custdesc A problem occurred during IPL of the system. + */ + errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_PREDICTIVE, + BPM_RC::BPM_WRITE_VIA_SCAP, + BPM_RC::BPM_EXCEEDED_RETRY_LIMIT_REG, + TWO_UINT32_TO_UINT64(i_reg, + data), + TARGETING::get_huid(iv_nvdimm)); + errl->addPartCallout(iv_nvdimm, + HWAS::BPM_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + errl->collectTrace(BPM_COMP_NAME); + nvdimmAddPage4Regs(iv_nvdimm,errl); + nvdimmAddVendorLog(iv_nvdimm, errl); + break; + } + + // The SCAP_REG and SCAP_DATA registers require a few retries to get the + // values to stick. This loop sets SCAP_DATA to i_data + retry = 0; + data = 0; + do { + + // Wait for the SCAP_STATUS Busy bit to be zero. + errl = waitForBusyBit(); + if (errl != nullptr) + { + break; + } + + // Write the data to the register we're attempting to access + // on the BPM. + errl = nvdimmWriteReg(iv_nvdimm, + SCAP_DATA, + i_data); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"BPM::writeViaScapRegister(): " + "Failed to write data 0x%.2X to SCAP_DATA for " + "register 0x%.2X.", + i_data, + i_reg); + errl->collectTrace(BPM_COMP_NAME); + break; + } + + // Wait for the SCAP_STATUS Busy bit to be zero. + errl = waitForBusyBit(); + if (errl != nullptr) + { + break; + } + + // Wait 100ms + nanosleep(0, 100 * NS_PER_MSEC); + + errl = nvdimmReadReg(iv_nvdimm, + SCAP_DATA, + data); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"BPM::writeViaScapRegister(): " + "Failed to read from SCAP_DATA to verify " + "that requested data 0x%.2X was written successfully.", + i_data); + errl->collectTrace(BPM_COMP_NAME); + break; + } + + if (data == i_data) + { + TRACUCOMP(g_trac_bpm, "Bpm::writeViaScapRegister(): " + "DATA 0x%X was successfully written to SCAP_DATA 0x435." + " Stop retries.", + i_data); + break; + } + + } while(++retry < MAX_RETRY); + if (errl != nullptr) + { + break; + } + if ((retry >= MAX_RETRY) && (data != i_data)) + { + /*@ + * @errortype + * @severity ERRORLOG::ERRL_SEV_PREDICTIVE + * @moduleid BPM_RC::BPM_WRITE_VIA_SCAP + * @reasoncode BPM_RC::BPM_EXCEEDED_RETRY_LIMIT_DATA + * @userdata1[0:31] The data that we were attempting to write to + * SCAP_DATA. + * @userdata1[32:63] The data that was found in the register on the + * final attempt. + * @userdata2 NVDIMM Target HUID associated with this BPM + * @devdesc The command sent to the BPM failed. + * @custdesc A problem occurred during IPL of the system. + */ + errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_PREDICTIVE, + BPM_RC::BPM_WRITE_VIA_SCAP, + BPM_RC::BPM_EXCEEDED_RETRY_LIMIT_DATA, + TWO_UINT32_TO_UINT64(i_data, + data), + TARGETING::get_huid(iv_nvdimm)); + errl->addPartCallout(iv_nvdimm, + HWAS::BPM_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + errl->collectTrace(BPM_COMP_NAME); + nvdimmAddPage4Regs(iv_nvdimm,errl); + nvdimmAddVendorLog(iv_nvdimm, errl); + break; + } + + } while(0); + + return errl; +} + +errlHndl_t Bpm::disableWriteProtection() +{ + TRACFCOMP(g_trac_bpm, ENTER_MRK"Bpm::disableWriteProtection()"); + errlHndl_t errl = nullptr; + + do { + + // The following write sequence to the I2C_REG_PROTECT register + // indirectly removes write protection from registers 0x40-0x7F on + // page 4. + for ( size_t i = 0; i < BPM_PASSWORD_LENGTH; ++i) + { + errl = nvdimmWriteReg(iv_nvdimm, + I2C_REG_PROTECT, + BPM_PASSWORD[i]); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::disableWriteProtection(): " + "Failed to write the unlock sequence to " + "I2C_REG_PROTECT"); + errl->collectTrace(BPM_COMP_NAME); + break; + } + } + if (errl != nullptr) + { + break; + } + + nanosleep(0, 100 * NS_PER_MSEC); + + // Make sure protection was removed + uint8_t data = 0; + errl = nvdimmReadReg(iv_nvdimm, + I2C_REG_PROTECT, + data); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::disableWriteProtection(): " + "Failed to verify that write protection was removed"); + errl->collectTrace(BPM_COMP_NAME); + break; + } + const uint8_t WRITE_PROTECT_DISABLED = 0x80; + if (!(data & WRITE_PROTECT_DISABLED)) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::disableWriteProtection(): " + "Failed to disable write protection. I2C_REG_PROTECT"); + /*@ + * @errortype + * @severity ERRORLOG::ERRL_SEV_PREDICTIVE + * @moduleid BPM_RC::BPM_DISABLE_WRITE_PROTECTION + * @reasoncode BPM_RC::BPM_DISABLE_WRITE_PROTECTION_FAILED + * @userdata1 NVDIMM Target HUID associated with this BPM + * @devdesc Failed to enter BSL mode after several attempts. + * @custdesc A problem occurred during IPL of the system. + */ + errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_PREDICTIVE, + BPM_RC::BPM_DISABLE_WRITE_PROTECTION, + BPM_RC::BPM_DISABLE_WRITE_PROTECTION_FAILED, + TARGETING::get_huid(iv_nvdimm)); + errl->addPartCallout(iv_nvdimm, + HWAS::BPM_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + errl->collectTrace(BPM_COMP_NAME); + nvdimmAddPage4Regs(iv_nvdimm,errl); + nvdimmAddVendorLog(iv_nvdimm, errl); + break; + } + + } while(0); + + return errl; +} + +errlHndl_t Bpm::switchBpmPage(uint16_t const i_segmentCode) +{ + + errlHndl_t errl = nullptr; + + do { + const uint8_t SPECIAL_CONTROL_COMMAND1 = 0x3E; + const uint8_t SPECIAL_CONTROL_COMMAND2 = 0x3F; + // Next, switch to the desired BPM segment by writing the segment code + // to the BPM's Special Control Command registers. + // + // Since the SCAP_DATA register can only hold 1 byte at a time we must + // do this in two steps. + // According to SMART, the segment code must be written in the following + // form to those registers: + // Register 0x3E gets LO(i_segmentCode) byte + // Register 0x3F gets HI(i_segmentCode) byte + // Example: 0x9D5E is the segment code for Segment D. It must be written + // as follows + // 0x3E, 0x5E + // 0x3F, 0x9D + const uint8_t loSegCode = i_segmentCode & 0xFF; + const uint8_t hiSegCode = (i_segmentCode >> 8) & 0xFF; + + TRACUCOMP(g_trac_bpm, "Bpm::switchBpmPage(): " + "Writing 0x%.2X to SPECIAL_CONTROL_COMMAND1 and " + "0x%.2X to SPECIAL_CONTROL_COMMAND2", + loSegCode, + hiSegCode); + + // First, clear the SPECIAL_CONTROL_COMMAND2 register so that we can + // write the full sequence without issue. + errl = writeViaScapRegister(SPECIAL_CONTROL_COMMAND2, 0x00); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::switchBpmPage(): " + "Writing 0x%.2X to SPECIAL_CONTROL_COMMAND2 " + "FAILED. BPM page will not have switched properly!!", + hiSegCode); + break; + } + + // Write the LO segment code. + errl = writeViaScapRegister(SPECIAL_CONTROL_COMMAND1, loSegCode); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::switchBpmPage(): " + "Writing 0x%.2X to SPECIAL_CONTROL_COMMAND1 " + "FAILED. BPM page will not have switched properly!!", + loSegCode); + break; + } + + // Write the HI segment code. + errl = writeViaScapRegister(SPECIAL_CONTROL_COMMAND2, hiSegCode); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::switchBpmPage(): " + "Writing 0x%.2X to SPECIAL_CONTROL_COMMAND2 " + "FAILED. BPM page will not have switched properly!!", + hiSegCode); + break; + } + + + // Request to open segment page is sent. + // Wait a few seconds for the operation to complete. + nanosleep(2,0); + + } while(0); + + return errl; +} + +errlHndl_t Bpm::writeToMagicRegisters( + uint8_t const (&i_magicValues)[NUM_MAGIC_REGISTERS]) +{ + TRACFCOMP(g_trac_bpm, ENTER_MRK"Bpm::writeToMagicRegisters() 0x%.2X 0x%.2X", + i_magicValues[0], + i_magicValues[1]); + errlHndl_t errl = nullptr; + + do { + const uint16_t magic_registers[NUM_MAGIC_REGISTERS] = + {BPM_MAGIC_REG1, BPM_MAGIC_REG2}; + + for (size_t i = 0; i < NUM_MAGIC_REGISTERS; ++i) + { + errl = nvdimmWriteReg(iv_nvdimm, + magic_registers[i], + i_magicValues[i]); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::writeToMagicRegisters(): " + "Failed to write the magic values to the magic " + "registers"); + errl->collectTrace(BPM_COMP_NAME); + break; + } + } + if (errl != nullptr) + { + break; + } + + // Verify the magic values were written + uint8_t magic_data[NUM_MAGIC_REGISTERS] = {0}; + for (size_t i = 0; i < NUM_MAGIC_REGISTERS; ++i) + { + errl = nvdimmReadReg(iv_nvdimm, + magic_registers[i], + magic_data[i]); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::writeToMagicRegisters(): " + "Failed to read back magic values to verify that " + "they were written."); + errl->collectTrace(BPM_COMP_NAME); + break; + } + } + if (errl != nullptr) + { + break; + } + + // If either of the magic values stored in magic_data don't match the + // corresponding expected values in magic_values then an error occurred. + if ( (magic_data[0] != i_magicValues[0]) + || (magic_data[1] != i_magicValues[1])) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::writeToMagicRegisters(): " + "Magic values read from BPM didn't match expected values " + "BPM_MAGIC_REG1 Expected 0x%.2X Actual 0x%.2X " + "BPM_MAGIC_REG2 Expected 0x%.2X Actual 0x%.2X", + i_magicValues[0], magic_data[0], + i_magicValues[1], magic_data[1]); + + /*@ + * @errortype + * @severity ERRORLOG::ERRL_SEV_PREDICTIVE + * @moduleid BPM_RC::BPM_WRITE_MAGIC_REG + * @reasoncode BPM_RC::BPM_WRITE_TO_MAGIC_REG_FAILED + * @userdata1[0:7] BPM_MAGIC_REG1 expected value + * @userdata1[8:15] BPM_MAGIC_REG1 actual value + * @userdata1[16:23] BPM_MAGIC_REG2 expected value + * @userdata1[24:31] BPM_MAGIC_REG2 actual value + * @userdata2[0:63] NVDIMM Target HUID associated with this BPM + * @devdesc Failed to write values to the magic registers on + * the BPM. + * @custdesc A problem occurred during IPL of the system. + */ + errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_PREDICTIVE, + BPM_RC::BPM_WRITE_MAGIC_REG, + BPM_RC::BPM_WRITE_TO_MAGIC_REG_FAILED, + TWO_UINT16_TO_UINT32( + TWO_UINT8_TO_UINT16(i_magicValues[0], + magic_data[0]), + TWO_UINT8_TO_UINT16(i_magicValues[1], + magic_data[1])), + TARGETING::get_huid(iv_nvdimm)); + errl->addPartCallout(iv_nvdimm, + HWAS::BPM_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + errl->collectTrace(BPM_COMP_NAME); + nvdimmAddPage4Regs(iv_nvdimm,errl); + nvdimmAddVendorLog(iv_nvdimm, errl); + break; + } + + TRACUCOMP(g_trac_bpm, "Bpm::writeToMagicRegisters(): " + "Magic values successfully written to BPM " + "BPM_MAGIC_REG1 0x%.2X " + "BPM_MAGIC_REG2 0x%.2X ", + magic_data[0], + magic_data[1]); + + } while(0); + + return errl; +} + +errlHndl_t Bpm::dumpSegment(uint16_t const i_segmentCode, + uint8_t (&o_buffer)[SEGMENT_SIZE]) +{ + TRACFCOMP(g_trac_bpm, ENTER_MRK"Bpm::dumpSegment(): Segment %X", + getSegmentIdentifier(i_segmentCode)); + assert(i_segmentCode == SEGMENT_B_CODE, "Bpm::dumpSegment(): Only Segment B is supported."); + + errlHndl_t errl = nullptr; + + do { + + errl = disableWriteProtection(); + if (errl != nullptr) + { + break; + } + + // We cannot be in BSL mode when dumping the config segments. Verify we + // aren't in BSL mode by checking SCAP_STATUS + scap_status_register_t status; + errl = nvdimmReadReg(iv_nvdimm, + SCAP_STATUS, + status.full); + if (errl != nullptr) + { + errl->collectTrace(BPM_COMP_NAME); + break; + } + + if (status.bit.Bpm_Bsl_Mode) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::dumpSegment(): " + "BSL Mode is enabled. Attempting to exit BSL mode."); + + // Try to exit BSL mode. This function will exit BSL. + errl = resetDevice(); + if (errl != nullptr) + { + break; + } + + // Exit update mode if on and write back production magic values. + errl = exitUpdateMode(); + if (errl != nullptr) + { + break; + } + + errl = nvdimmReadReg(iv_nvdimm, + SCAP_STATUS, + status.full); + if (errl != nullptr) + { + errl->collectTrace(BPM_COMP_NAME); + break; + } + if (status.bit.Bpm_Bsl_Mode) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::dumpSegment(): " + "Couldn't dump Segment %X. BSL Mode is enabled.", + getSegmentIdentifier(i_segmentCode)); + + /*@ + * @errortype + * @severity ERRORLOG::ERRL_SEV_PREDICTIVE + * @moduleid BPM_RC::BPM_DUMP_SEGMENT + * @reasoncode BPM_RC::BPM_BSL_MODE_ENABLED + * @userdata1[0:63] NVDIMM Target HUID associated with this BPM + * @devdesc Couldn't dump segment data because BSL mode + * was enabled. + * @custdesc A problem occurred during IPL of the system. + */ + errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_PREDICTIVE, + BPM_RC::BPM_DUMP_SEGMENT, + BPM_RC::BPM_BSL_MODE_ENABLED, + TARGETING::get_huid(iv_nvdimm)); + errl->addPartCallout(iv_nvdimm, + HWAS::BPM_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + errl->collectTrace(BPM_COMP_NAME); + nvdimmAddPage4Regs(iv_nvdimm,errl); + nvdimmAddVendorLog(iv_nvdimm, errl); + + break; + } + } + + // First the NVDIMM MAGIC registers BPM_MAGIC_REG1 and BPM_MAGIC_REG2 + // must be programmed to 0xBA and 0xAB respectively. + const uint8_t magic_values[NUM_MAGIC_REGISTERS] = {0xBA, 0xAB}; + errl = writeToMagicRegisters(magic_values); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::dumpSegment(): " + "Failed to write magic numbers that enable " + "reading of segment data."); + break; + } + + uint8_t retry = 1; + // Attempt to switch to the correct page and dump data twice. + do { + // Set buffer to be all zeroes. + memset(&o_buffer, 0, SEGMENT_SIZE); + + // Open this segments page on the BPM. + errl = switchBpmPage(i_segmentCode); + if (errl != nullptr) + { + break; + } + + TRACFCOMP(g_trac_bpm, "Bpm::dumpSegment(): " + "Dumping Segment %X to buffer.", + getSegmentIdentifier(i_segmentCode)); + + // Dump the segment data + bool wrongPage = false; + for (uint8_t reg = 0; reg < SEGMENT_SIZE; ++reg) + { + errl = readViaScapRegister(reg, o_buffer[reg]); + if (errl != nullptr) + { + break; + } + + // We can determine if the page switch succeeded based on the + // first three bytes from regs 0x10-0x12. If Segment B was + // opened, then 0x10-0x1F is serial number for the BPM. + // SMART guarantees the first three bytes to be as follows: + if ((reg == 0x10) && (o_buffer[reg] != 0x53)) + { + TRACFCOMP(g_trac_bpm, INFO_MRK"Bpm::dumpSegment " + "data 0x%.2X at offset 0x%.2x wasn't expected " + "value 0x53", + o_buffer[reg], reg); + wrongPage = true; + } + if ((reg == 0x11) && (o_buffer[reg] != 0x46)) + { + TRACFCOMP(g_trac_bpm, INFO_MRK"Bpm::dumpSegment " + "data 0x%.2X at offset 0x%.2x wasn't expected " + "value 0x46", + o_buffer[reg], reg); + wrongPage = true; + } + if ((reg == 0x12) && (o_buffer[reg] != 0x52)) + { + TRACFCOMP(g_trac_bpm, INFO_MRK"Bpm::dumpSegment " + "data 0x%.2X at offset 0x%.2x wasn't expected " + "value 0x52", + o_buffer[reg], reg); + wrongPage = true; + } + + if (wrongPage && (reg == 0x20)) + { + break; + } + + } + + TRACUBIN(g_trac_bpm, "Segment BIN DUMP", o_buffer, SEGMENT_SIZE); + + if ((errl != nullptr) || (wrongPage == false)) + { + break; + } + + // Close this segments page on the BPM before making another + // attempt. + errl = switchBpmPage(DEFAULT_REG_PAGE); + if (errl != nullptr) + { + break; + } + + } while(++retry < MAX_RETRY); + if (errl != nullptr) + { + break; + } + if (retry >= MAX_RETRY) + { + /*@ + * @errortype + * @severity ERRORLOG::ERRL_SEV_PREDICTIVE + * @moduleid BPM_RC::BPM_DUMP_SEGMENT + * @reasoncode BPM_RC::BPM_EXCEEDED_RETRY_LIMIT + * @userdata1 The segment code for the page that failed to + * open. + * @userdata2 NVDIMM Target HUID associated with this BPM + * @devdesc Failed to open the segment page in the given + * amount of retries. + * @custdesc A problem occurred during IPL of the system. + */ + errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_PREDICTIVE, + BPM_RC::BPM_DUMP_SEGMENT, + BPM_RC::BPM_EXCEEDED_RETRY_LIMIT, + i_segmentCode, + TARGETING::get_huid(iv_nvdimm)); + errl->addPartCallout(iv_nvdimm, + HWAS::BPM_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + errl->collectTrace(BPM_COMP_NAME); + nvdimmAddPage4Regs(iv_nvdimm,errl); + nvdimmAddVendorLog(iv_nvdimm, errl); + setAttemptAnotherUpdate(); + break; + } + + } while(0); + + TRACFCOMP(g_trac_bpm, "Bpm::dumpSegment(): " + "Closing Segment %X's page.", + getSegmentIdentifier(i_segmentCode)); + + // Close the Segment page by switching back to the default page. + errlHndl_t closeSegmentErrl = switchBpmPage(DEFAULT_REG_PAGE); + if (closeSegmentErrl != nullptr) + { + handleMultipleErrors(errl, closeSegmentErrl); + } + + // Write back the production magic values. + errlHndl_t magicErrl = writeToMagicRegisters(PRODUCTION_MAGIC_VALUES); + if (magicErrl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::dumpSegment(): " + "Failed to write update mode magic numbers."); + handleMultipleErrors(errl, magicErrl); + } + + return errl; +} + +errlHndl_t Bpm::mergeSegment(BpmConfigLidImage const i_configImage, + uint16_t const i_segmentCode, + uint8_t (&o_buffer)[SEGMENT_SIZE]) +{ + TRACFCOMP(g_trac_bpm, ENTER_MRK"Bpm::mergeSegment(): Segment %X", + getSegmentIdentifier(i_segmentCode)); + errlHndl_t errl = nullptr; + + size_t segmentStartOffset = 0; + auto it = segmentMap.find(i_segmentCode); + if (it != segmentMap.end()) + { + segmentStartOffset = it->second; + } + else + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::mergeSegment(): " + "Couldn't find start offset for Segment %X", + getSegmentIdentifier(i_segmentCode)); + assert(false, "Add the missing Segment %X Start Offset to the offset map", getSegmentIdentifier(i_segmentCode)); + } + + TRACFCOMP(g_trac_bpm, "Bpm::mergeSegment(): " + "Segment %X Start offset: 0x%X", + getSegmentIdentifier(i_segmentCode), + segmentStartOffset); + + do { + + const size_t NUMBER_OF_FRAGMENTS = i_configImage.getNumberOfFragments(); + char const * data = reinterpret_cast<char const *>( + i_configImage.getFirstFragment()); + + config_image_fragment_t const * fragment = + reinterpret_cast<config_image_fragment_t const *>(data); + + TRACUCOMP(g_trac_bpm, "mergeSegment(): " + "NUMBER_OF_FRAGMENTS = 0x%.4X", NUMBER_OF_FRAGMENTS); + + for(size_t i = 0; i < NUMBER_OF_FRAGMENTS; ++i) + { + // The fragment offsets are given as offsets within the + // configuration segment data. So, if the fragment offset is less + // than the starting offset of this segment then the fragment is not + // relevant to this segment. + if (fragment->iv_offset < segmentStartOffset) + { + // This fragment is not for the segment we are dealing with. + TRACUCOMP(g_trac_bpm, "mergeSegment(): " + "Fragment with offset 0x%.4X not related to " + "Segment %X, skipping", + fragment->iv_offset, + getSegmentIdentifier(i_segmentCode)); + + // Move to the next fragment + data += sizeof(config_image_fragment_t) + + fragment->iv_fragmentSize; + fragment = + reinterpret_cast<config_image_fragment_t const *>(data); + continue; + } + // Each segment is 128 bytes in size. So, if the offset given for + // the fragment is greater than the upper boundry then no more + // fragments exist for this segment. + if (fragment->iv_offset >= segmentStartOffset + SEGMENT_SIZE) + { + // This fragment and all other fragments afterward are not for + // this segment. + TRACUCOMP(g_trac_bpm, "mergeSegment(): " + "Fragment with offset 0x%.4X greater than/equal to " + "Segment %X ending offset, skipping", + fragment->iv_offset, + getSegmentIdentifier(i_segmentCode)); + break; + } + + // The fragment offset may be out of bounds for the buffer so + // scale it down to be within the buffer size. + size_t offset = fragment->iv_offset % SEGMENT_SIZE; + + // Overwrite the BPM segment data at the offset specified by the + // fragment. + memcpy(&o_buffer[offset], + &(fragment->iv_data), + fragment->iv_fragmentSize); + + // Move to the next fragment + data += sizeof(config_image_fragment_t) + fragment->iv_fragmentSize; + fragment = reinterpret_cast<config_image_fragment_t const *>(data); + } + + TRACUBIN(g_trac_bpm, "Merged Segment", o_buffer, SEGMENT_SIZE); + + } while(0); + + return errl; +} + +errlHndl_t Bpm::eraseSegment(uint16_t i_segmentCode) +{ + TRACFCOMP(g_trac_bpm, ENTER_MRK"Bpm::eraseSegment(): Segment %X", + getSegmentIdentifier(i_segmentCode)); + errlHndl_t errl = nullptr; + + do { + + payload_t payload; + + size_t segmentStartOffset = 0; + auto it = segmentMap.find(i_segmentCode); + if (it != segmentMap.end()) + { + segmentStartOffset = it->second; + } + else + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::mergeSegment(): " + "Couldn't find start offset for Segment %X", + getSegmentIdentifier(i_segmentCode)); + assert(false, "Add the missing Segment %X Start Offset to the offset map", getSegmentIdentifier(i_segmentCode)); + } + errl = setupPayload(payload, + BSL_ERASE_SEGMENT, + BPM_CONFIG_START_ADDRESS + segmentStartOffset); + if (errl != nullptr) + { + break; + } + + errl = issueCommand(BPM_PASSTHROUGH, + payload, + WRITE, + ERASE_SEGMENT_DELAY); + if (errl != nullptr) + { + break; + } + + // Wait 1 second for the operation to complete. + TRACFCOMP(g_trac_bpm, "Bpm::eraseSegment(): " + "Erasing Segment %X. " + "Waiting 1 second for operation to complete.", + getSegmentIdentifier(i_segmentCode)); + nanosleep(1,0); + + } while(0); + + TRACFCOMP(g_trac_bpm, EXIT_MRK"Bpm::eraseSegment(): " + "Segment %X erase operation completed " + "%s", + getSegmentIdentifier(i_segmentCode), + (errl == nullptr) ? "without errors" : "with errors"); + + return errl; +} + +errlHndl_t Bpm::writeSegment(uint8_t const (&i_buffer)[SEGMENT_SIZE], + uint16_t const i_segmentCode) +{ + TRACFCOMP(g_trac_bpm, ENTER_MRK"Bpm::writeSegment(): Segment %X", + getSegmentIdentifier(i_segmentCode)); + errlHndl_t errl = nullptr; + + do { + + auto it = segmentMap.find(i_segmentCode); + size_t segmentStartOffset = 0; + if (it != segmentMap.end()) + { + segmentStartOffset = it->second; + } + + // To update the given segment, we have to send over the data as + // payloads. Since the max size of a payload's data is 16 bytes, there + // will be 8 payloads sent to update a given segment because each + // segment is 128 bytes. + for (size_t offset = 0; + offset < SEGMENT_SIZE; + offset += MAX_PAYLOAD_DATA_SIZE) + { + // Construct a payload for the data at this offset up to the + // MAX_PAYLOAD_DATA_SIZE. + payload_t payload; + // Each segment is 128 bytes and the segment start addresses + // are their relative position to BPM_CONFIG_START_ADDRESS. To + // arrive at the correct address offset for this data we must + // calculate the addressOffset in the following way. + uint16_t addressOffset = BPM_CONFIG_START_ADDRESS + + segmentStartOffset + + offset; + errl = setupPayload(payload, + BSL_RX_DATA_BLOCK, + addressOffset, + &i_buffer[offset], + MAX_PAYLOAD_DATA_SIZE); + if (errl != nullptr) + { + break; + } + + if (addressOffset % 0x20 == 0) + { + TRACFCOMP(g_trac_bpm, "Bpm::writeSegment(): " + "Writing to address offset 0x%.4X. " + "Config bytes written: 0x%X; Remaining: 0x%X", + addressOffset, + offset, (SEGMENT_SIZE - offset)); + } + + // Attempt to write the payload using a retry loop. + errl = blockWrite(payload); + if (errl != nullptr) + { + break; + } + } + if (errl != nullptr) + { + break; + } + + } while(0); + + TRACFCOMP(g_trac_bpm, EXIT_MRK"Bpm::writeSegment(): " + "Segment %X write and verification completed " + "%s", + getSegmentIdentifier(i_segmentCode), + (errl == nullptr) ? "without errors" : "with errors"); + + return errl; +} + +errlHndl_t Bpm::preprocessSegments(BpmConfigLidImage const i_configImage) +{ + TRACFCOMP(g_trac_bpm, ENTER_MRK"Bpm::preprocessSegments()"); + errlHndl_t errl = nullptr; + + do { + + if (iv_attemptAnotherUpdate && iv_segmentDMerged && iv_segmentBMerged) + { + // The segment data has already been merged with the flash image + // data. Doing it again has the potential to fail depending on where + // the last update attempt failed. + TRACFCOMP(g_trac_bpm, "Bpm::preprocessSegments(): " + "Segment data was merged in a previous update attempt, " + "skipping preprocessing and using existing data."); + break; + } + + // Merge the fragments for D with the data from the BPM. For D, this + // will just populate the empty segment with the data from the flash + // image. + if (!iv_segmentDMerged) + { + errl = mergeSegment(i_configImage, SEGMENT_D_CODE, iv_segmentD); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::preprocessSegments(): " + "Failed to merge Segment D."); + break; + } + iv_segmentDMerged = true; + } + else + { + TRACFCOMP(g_trac_bpm, INFO_MRK"Bpm::preprocessSegments(): " + "Segment %X has been merged already. Skipping merge...", + getSegmentIdentifier(SEGMENT_D_CODE)); + } + + // Merge the fragments for B with the data from the BPM. + if (!iv_segmentBMerged) + { + // Dump the segment into a buffer. This is only necessary for + // segment B as segment D comes straight from the flash image file. + errl = dumpSegment(SEGMENT_B_CODE, iv_segmentB); + if (errl != nullptr) + { + break; + } + + errl = mergeSegment(i_configImage, SEGMENT_B_CODE, iv_segmentB); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::preprocessSegments(): " + "Failed to merge Segment B."); + break; + } + iv_segmentBMerged = true; + } + else + { + TRACFCOMP(g_trac_bpm, INFO_MRK"Bpm::preprocessSegments(): " + "Segment %X has been merged already. Skipping merge...", + getSegmentIdentifier(SEGMENT_B_CODE)); + } + + } while(0); + + return errl; +} + +errlHndl_t Bpm::getResponse(uint8_t * const o_responseData, + uint8_t const i_responseSize) +{ + TRACUCOMP(g_trac_bpm, ENTER_MRK"Bpm::getResponse()"); + + errlHndl_t errl = nullptr; + memset(o_responseData, 0xFF, i_responseSize); + + do { + + // Get the result from the BPM. + // First clear the error status register + errl = nvdimmWriteReg(iv_nvdimm, + BPM_REG_ERR_STATUS, + 0x00); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::getResponse(): " + "Failed to clear error status register"); + errl->collectTrace(BPM_COMP_NAME); + break; + } + + // Set the payload length + // The 4 header bytes plus 2 CRC bytes make up the other data size in + // the response payload. + const uint8_t RESPONSE_PAYLOAD_OTHER_DATA_SIZE = 6; + uint8_t responsePayloadSize = RESPONSE_PAYLOAD_OTHER_DATA_SIZE + + i_responseSize; + + errl = nvdimmWriteReg(iv_nvdimm, + BPM_PAYLOAD_LENGTH, + responsePayloadSize); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::getResponse(): " + "Failed to set payload length"); + errl->collectTrace(BPM_COMP_NAME); + break; + } + + // Setup the command status register + command_status_register_t commandStatus; + commandStatus.bits.Bsp_Cmd_In_Progress = 1; + commandStatus.bits.Operator_Type = READ; + errl = nvdimmWriteReg(iv_nvdimm, + BPM_CMD_STATUS, + commandStatus.value); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::getResponse(): " + "Failed to setup command status register"); + errl->collectTrace(BPM_COMP_NAME); + break; + } + + // Setup command type. + errl = nvdimmWriteReg(iv_nvdimm, + BPM_REG_CMD, + BPM_PASSTHROUGH); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::getResponse(): " + "Failed to setup command type."); + errl->collectTrace(BPM_COMP_NAME); + break; + } + + errl = waitForCommandStatusBitReset(commandStatus); + if (errl != nullptr) + { + break; + } + + // Read out the response payload. + payload_t responsePayload; + + for (size_t i = 0; i < responsePayloadSize; ++i) + { + uint8_t data = 0; + errl = nvdimmReadReg(iv_nvdimm, + (BPM_REG_PAYLOAD_START + (i * sizeof(uint8_t))), + data); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::getResponse(): " + "Failed to read response payload"); + errl->collectTrace(BPM_COMP_NAME); + break; + } + + responsePayload.push_back(data); + } + if (errl != nullptr) + { + break; + } + + // Verify the data from the response was good. + uint8_t* responseIterator = responsePayload.data(); + uint16_t responseCrc = *(reinterpret_cast<uint16_t *> + (&responseIterator[PAYLOAD_HEADER_SIZE + i_responseSize])); + // The BPM is going to give the response CRC in LE. So convert it to BE. + responseCrc = le16toh(responseCrc); + uint16_t expectedCrc = crc16_calc(responseIterator, + PAYLOAD_HEADER_SIZE + i_responseSize); + if (responseCrc != expectedCrc) + { + memset(o_responseData, 0xFF, i_responseSize); + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::getResponse(): " + "Response CRC verification failed. " + "Received invalid data from BPM."); + /*@ + * @errortype + * @severity ERRORLOG::ERRL_SEV_PREDICTIVE + * @moduleid BPM_RC::BPM_GET_RESPONSE + * @reasoncode BPM_RC::BPM_RESPONSE_CRC_MISMATCH + * @userdata1[00:31] Expected Response CRC (in Big Endian) + * @userdata1[32:63] Actual Response CRC (in Big Endian) + * @userdata2 NVDIMM Target HUID associated with this BPM + * @devdesc The response CRC calculated by the BPM didn't + * match the CRC calculated by hostboot. + * @custdesc A problem occurred during IPL of the system. + */ + errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_PREDICTIVE, + BPM_RC::BPM_GET_RESPONSE, + BPM_RC::BPM_RESPONSE_CRC_MISMATCH, + TWO_UINT32_TO_UINT64(expectedCrc, + responseCrc), + TARGETING::get_huid(iv_nvdimm)); + errl->addPartCallout(iv_nvdimm, + HWAS::BPM_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + errl->collectTrace(BPM_COMP_NAME); + nvdimmAddPage4Regs(iv_nvdimm,errl); + nvdimmAddVendorLog(iv_nvdimm, errl); + break; + } + + // Write the data to the output buffer + for (size_t i = 0; i < i_responseSize; ++i) + { + // Only copy the response data from the payload to the output buffer + o_responseData[i] = responsePayload[i + PAYLOAD_HEADER_SIZE]; + } + + } while(0); + + return errl; +} + +errlHndl_t Bpm::verifyBlockWrite(payload_t i_payload, + uint8_t i_dataLength, + uint8_t & o_status) +{ + errlHndl_t errl = nullptr; + // Assume a bad status. + o_status = 0xFF; + + do { + + // Pull the address to verify out of the payload. It was inserted in + // little endian form so it needs to be converted back to big endian + // because setupPayload expects an address in big endian. + uint16_t address = getPayloadAddressBE(i_payload); + + // The data section of the payload is organized in the following way: + // 2 bytes: uint16_t size of data to verify in little endian format + // 2 bytes: CRC of the data to be verified on the BPM in little endian. + const size_t VERIFY_BLOCK_PAYLOAD_DATA_SIZE = 4; + uint8_t data[VERIFY_BLOCK_PAYLOAD_DATA_SIZE] = {0}; + + // Since the data length is stored as uint16_t but the length we deal + // with is uint8_t we can easily convert this to little endian by + // storing our uint8_t data length in the first index of the array and + // leaving the next index 0. + data[0] = i_dataLength; + + // Calculate the uint16_t CRC for the data that was written to the BPM. + // The BPM will compare its calculated CRC with this one to verify if + // the block was written correctly. + uint16_t crc = htole16(crc16_calc(&i_payload[PAYLOAD_DATA_START_INDEX], + i_dataLength)); + + memcpy(&data[2], &crc, sizeof(uint16_t)); + + payload_t verifyPayload; + errl = setupPayload(verifyPayload, + BSL_VERIFY_BLOCK, + address, + data, + VERIFY_BLOCK_PAYLOAD_DATA_SIZE); + if (errl != nullptr) + { + break; + } + + // Issue the command to the BPM. + errl = issueCommand(BPM_PASSTHROUGH, + verifyPayload, + WRITE, + NO_DELAY_EXTERNAL_RESPONSE); + if (errl != nullptr) + { + break; + } + + errl = getResponse(&o_status, sizeof(uint8_t)); + if (errl != nullptr) + { + break; + } + + } while(0); + + return errl; +} + +errlHndl_t Bpm::blockWrite(payload_t i_payload) +{ + assert(i_payload[PAYLOAD_COMMAND_INDEX] == BSL_RX_DATA_BLOCK, + "Bpm::blockWrite(): " + "Can only write BSL_RX_DATA_BLOCK commands"); + + errlHndl_t errl = nullptr; + uint8_t retry = 0; + + // Get the payload address for trace output. + uint16_t payloadAddress = getPayloadAddressBE(i_payload); + + // Any status from verifyBlockWrite that is non-zero is considered a + // fail. So, assume a fail and check. + uint8_t wasVerified = 0xFF; + do { + + + // Since the write command has its response packet checked within the + // issueCommand() function we must attempt to retry the write if we get + // a bad response from the BPM. + errl = blockWriteRetry(i_payload); + if (errl != nullptr) + { + break; + } + + // Sleep for 0.001 second + nanosleep(0, 1 * NS_PER_MSEC); + + uint8_t dataLength = i_payload[PAYLOAD_HEADER_DATA_LENGTH_INDEX] + - PAYLOAD_HEADER_SIZE; + errl = verifyBlockWrite(i_payload, + dataLength, + wasVerified); + if ( (errl != nullptr) + && (errl->reasonCode() == BPM_RC::BPM_RESPONSE_CRC_MISMATCH) + && ((retry + 1) < MAX_RETRY)) + { + // Delete the retryable error and continue + TRACFCOMP(g_trac_bpm, "Bpm::blockWrite(): " + "Encountered a retryable error. Delete and continue."); + delete errl; + errl = nullptr; + } + else if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::blockWrite(): " + "BSL_VERIFY_BLOCK failed for address 0x%.4X. " + "A non-retryable error occurred on attempt %d/%d", + payloadAddress, + (retry + 1), + MAX_RETRY); + // A non-retryable error occurred. Break from retry loop. + break; + } + + if (wasVerified != 0) + { + TRACUCOMP(g_trac_bpm, "Bpm::blockWrite(): " + "BSL_VERIFY_BLOCK failed for address 0x%.4X. " + "Attempt %d/%d", + payloadAddress, + (retry + 1), + MAX_RETRY); + } + else + { + // Write verified successfully, stop retries. + break; + } + + } while (++retry < MAX_RETRY); + if ((errl == nullptr) && (retry >= MAX_RETRY) && (wasVerified != 0)) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::blockWrite(): " + "Failed to write payload data to BPM after %d retries.", + MAX_RETRY); + /*@ + * @errortype + * @severity ERRORLOG::ERRL_SEV_PREDICTIVE + * @moduleid BPM_RC::BPM_BLOCK_WRITE + * @reasoncode BPM_RC::BPM_EXCEEDED_RETRY_LIMIT + * @userdata1[0:63] NVDIMM Target HUID associated with this BPM + * @devdesc The block of data to be written to the BPM + * failed to write successfully in the given number + * of retries. + * @custdesc A problem occurred during IPL of the system. + */ + errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_PREDICTIVE, + BPM_RC::BPM_BLOCK_WRITE, + BPM_RC::BPM_EXCEEDED_RETRY_LIMIT, + TARGETING::get_huid(iv_nvdimm)); + errl->addPartCallout(iv_nvdimm, + HWAS::BPM_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + errl->collectTrace(BPM_COMP_NAME); + nvdimmAddVendorLog(iv_nvdimm, errl); + + } + + if (errl != nullptr) + { + // Change the state of iv_attemptAnotherUpdate. This will signal + // another update attempt or cease further attempts. + setAttemptAnotherUpdate(); + } + + return errl; +} + +errlHndl_t Bpm::blockWriteRetry(payload_t i_payload) +{ + assert(i_payload[PAYLOAD_COMMAND_INDEX] == BSL_RX_DATA_BLOCK, + "Bpm::blockWriteRetry(): " + "Can only retry BSL_RX_DATA_BLOCK commands"); + + errlHndl_t errl = nullptr; + uint8_t retry = 0; + + // Get the payload address for trace output. + uint16_t payloadAddress = getPayloadAddressBE(i_payload); + + do { + + // Send the payload data over as a pass-through command. The response + // will be checked internally. + errl = issueCommand(BPM_PASSTHROUGH, i_payload, WRITE); + if (errl == nullptr) + { + // Command was a success. Stop retries. + break; + } + + if ( (errl != nullptr) + && (errl->reasonCode() == BPM_RC::BPM_RESPONSE_CRC_MISMATCH) + && ((retry + 1) < MAX_RETRY)) + { + // Delete the retryable error and continue + TRACFCOMP(g_trac_bpm, "Bpm::blockWriteRetry(): " + "Encountered a retryable error. Delete and continue."); + delete errl; + errl = nullptr; + } + else if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::blockWriteRetry(): " + "BSL_RX_DATA_BLOCK failed for address 0x%.4X. " + "A non-retryable error occurred on attempt %d/%d", + payloadAddress, + (retry + 1), + MAX_RETRY); + // A non-retryable error occurred. Break from retry loop. + break; + } + + } while (++retry < MAX_RETRY); + if ((errl == nullptr) && (retry >= MAX_RETRY)) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::blockWriteRetry(): " + "Failed to write payload data to BPM after %d retries.", + MAX_RETRY); + /*@ + * @errortype + * @severity ERRORLOG::ERRL_SEV_PREDICTIVE + * @moduleid BPM_RC::BPM_RETRY_BLOCK_WRITE + * @reasoncode BPM_RC::BPM_EXCEEDED_RETRY_LIMIT + * @userdata1[0:63] NVDIMM Target HUID associated with this BPM + * @devdesc The block of data to be written to the BPM + * failed to write successfully in the given number + * of retries. + * @custdesc A problem occurred during IPL of the system. + */ + errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_PREDICTIVE, + BPM_RC::BPM_RETRY_BLOCK_WRITE, + BPM_RC::BPM_EXCEEDED_RETRY_LIMIT, + TARGETING::get_huid(iv_nvdimm)); + errl->addPartCallout(iv_nvdimm, + HWAS::BPM_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + errl->collectTrace(BPM_COMP_NAME); + nvdimmAddPage4Regs(iv_nvdimm,errl); + nvdimmAddVendorLog(iv_nvdimm, errl); + + } + + if (errl != nullptr) + { + // Change the state of iv_attemptAnotherUpdate. This will signal + // another update attempt or cease further attempts. + setAttemptAnotherUpdate(); + } + + return errl; +} + +errlHndl_t Bpm::waitForCommandStatusBitReset( + command_status_register_t i_commandStatus) +{ + errlHndl_t errl = nullptr; + + do { + // Wait until the COMMAND_IN_PROGRESS bit is reset + errl = nvdimmReadReg(iv_nvdimm, + BPM_CMD_STATUS, + i_commandStatus.value); + if (errl != nullptr) + { + errl->collectTrace(BPM_COMP_NAME); + break; + } + + // Give the BPM 20 seconds to complete any given command before we time + // out and cancel the update procedure. + int retry = 20 * MS_PER_SEC; + + while (i_commandStatus.bits.Bsp_Cmd_In_Progress) + { + nanosleep(0, 1 * NS_PER_MSEC); + errl = nvdimmReadReg(iv_nvdimm, + BPM_CMD_STATUS, + i_commandStatus.value); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::waitForCommandStatusBitReset(): " + "Failed to read BPM_CMD_STATUS register"); + errl->collectTrace(BPM_COMP_NAME); + break; + } + + if (--retry <= 0) + { + TRACFCOMP(g_trac_bpm, ERR_MRK + "BPM::waitForCommandStatusBitReset(): " + "BSP_CMD_IN_PROGRESS bit has not reset in allotted " + "number of retries. Cancel update procedure"); + /*@ + * @errortype + * @severity ERRORLOG::ERRL_SEV_PREDICTIVE + * @moduleid BPM_RC::BPM_WAIT_FOR_CMD_BIT_RESET + * @reasoncode BPM_RC::BPM_EXCEEDED_RETRY_LIMIT + * @userdata1[0:63] NVDIMM Target HUID associated with this BPM + * @devdesc The command status bit failed to reset in + * the given number of retries. + * @custdesc A problem occurred during IPL of the system. + */ + errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_PREDICTIVE, + BPM_RC::BPM_WAIT_FOR_CMD_BIT_RESET, + BPM_RC::BPM_EXCEEDED_RETRY_LIMIT, + TARGETING::get_huid(iv_nvdimm)); + errl->addPartCallout(iv_nvdimm, + HWAS::BPM_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + errl->collectTrace(BPM_COMP_NAME); + nvdimmAddPage4Regs(iv_nvdimm,errl); + nvdimmAddVendorLog(iv_nvdimm, errl); + break; + } + + } + if (errl != nullptr) + { + break; + } + + // Check for error + if (i_commandStatus.bits.Error_Flag) + { + uint8_t error = 0; + errl = nvdimmReadReg(iv_nvdimm, + BPM_REG_ERR_STATUS, + error); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::waitForCommandStatusBitReset(): " + "Failed to read BPM_REG_ERR_STATUS"); + errl->collectTrace(BPM_COMP_NAME); + break; + } + + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::waitForCommandStatusBitReset(): " + "BPM_CMD_STATUS Error Flag is set"); + /*@ + * @errortype + * @severity ERRORLOG::ERRL_SEV_PREDICTIVE + * @moduleid BPM_RC::BPM_WAIT_FOR_CMD_BIT_RESET + * @reasoncode BPM_RC::BPM_CMD_STATUS_ERROR_BIT_SET + * @userdata1[0:7] Error status code returned by BPM + * @userdata2[0:63] NVDIMM Target HUID associated with this BPM + * @devdesc The command status register returned an error. + * @custdesc A problem occurred during IPL of the system. + */ + errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_PREDICTIVE, + BPM_RC::BPM_WAIT_FOR_CMD_BIT_RESET, + BPM_RC::BPM_CMD_STATUS_ERROR_BIT_SET, + error, + TARGETING::get_huid(iv_nvdimm)); + errl->collectTrace(BPM_COMP_NAME); + nvdimmAddPage4Regs(iv_nvdimm,errl); + nvdimmAddVendorLog(iv_nvdimm, errl); + break; + + } + + } while(0); + + return errl; +} + +errlHndl_t Bpm::verifyGoodBpmState() +{ + errlHndl_t errl = nullptr; + int retry = 100; + scap_status_register_t status; + const uint8_t BPM_PRESENT_AND_ENABLED = 0x11; + + while (retry > 0) + { + + errl = nvdimmReadReg(iv_nvdimm, + SCAP_STATUS, + status.full); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::verifyGoodBpmState(): " + "Failed to read SCAP_STATUS to determine " + "state of BPM."); + errl->collectTrace(BPM_COMP_NAME); + break; + } + + if ((status.full & 0xFF) == BPM_PRESENT_AND_ENABLED) + { + // BPM is present and enabled. Stop retries. + break; + } + + --retry; + nanosleep(0, 1 * NS_PER_MSEC); + } + if (retry <= 0) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::verifyGoodBpmState(): " + "BPM failed to become present and enabled " + "in 100 retries."); + /*@ + * @errortype + * @severity ERRORLOG::ERRL_SEV_PREDICTIVE + * @moduleid BPM_RC::BPM_VERIFY_GOOD_BPM_STATE + * @reasoncode BPM_RC::BPM_EXCEEDED_RETRY_LIMIT + * @userdata1 NVDIMM Target HUID associated with this BPM + * @userdata2 SCAP_STATUS register contents. See nvdimm.H + * for bits associated with this register. + * @devdesc The BPM did not become present and enabled + * in given number of retries. + * @custdesc A problem occurred during IPL of the system. + */ + errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_PREDICTIVE, + BPM_RC::BPM_VERIFY_GOOD_BPM_STATE, + BPM_RC::BPM_EXCEEDED_RETRY_LIMIT, + TARGETING::get_huid(iv_nvdimm), + status.full); + errl->collectTrace(BPM_COMP_NAME); + errl->addPartCallout(iv_nvdimm, + HWAS::BPM_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + nvdimmAddPage4Regs(iv_nvdimm,errl); + nvdimmAddVendorLog(iv_nvdimm, errl); + } + + return errl; +} + +errlHndl_t Bpm::waitForBusyBit() +{ + errlHndl_t errl = nullptr; + int retry = 10; + scap_status_register_t status; + + while (retry > 0) + { + + errl = nvdimmReadReg(iv_nvdimm, + SCAP_STATUS, + status.full); + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, "Bpm::waitForBusyBit(): " + "Failed to read from SCAP_STATUS to determine " + "state of Busy bit."); + errl->collectTrace(BPM_COMP_NAME); + break; + } + + if (!status.bit.Busy) + { + // SCAP Register is no longer busy. Stop retries. + break; + } + + if (retry <= 0) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::waitForBusyBit(): " + "SCAP_STATUS Busy bit failed to reset to 0 " + "in 10 retries."); + /*@ + * @errortype + * @severity ERRORLOG::ERRL_SEV_PREDICTIVE + * @moduleid BPM_RC::BPM_WAIT_FOR_BUSY_BIT_RESET + * @reasoncode BPM_RC::BPM_EXCEEDED_RETRY_LIMIT + * @userdata1[0:63] NVDIMM Target HUID associated with this BPM + * @devdesc The SCAP status register busy bit failed to + * reset in given number of retries. + * @custdesc A problem occurred during IPL of the system. + */ + errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_PREDICTIVE, + BPM_RC::BPM_WAIT_FOR_BUSY_BIT_RESET, + BPM_RC::BPM_EXCEEDED_RETRY_LIMIT, + TARGETING::get_huid(iv_nvdimm)); + errl->collectTrace(BPM_COMP_NAME); + nvdimmAddPage4Regs(iv_nvdimm,errl); + nvdimmAddVendorLog(iv_nvdimm, errl); + break; + } + + --retry; + nanosleep(0, 2 * NS_PER_MSEC); + } + + return errl; +} + +errlHndl_t Bpm::runConfigUpdates(BpmConfigLidImage i_configImage) +{ + TRACFCOMP(g_trac_bpm, ENTER_MRK"Bpm::runConfigUpdates()"); + errlHndl_t errl = nullptr; + + do { + + // Before the entering BSL mode, we must do preprocessing prior to the + // config part of the update. Segment B needs to be dumped from the + // BPM into a buffer and then the config data from the image needs to be + // inserted into it. To dump segment data, it is required to have + // working firmware which will not be the case during BSL mode. + errl = preprocessSegments(i_configImage); + if (errl != nullptr) + { + break; + } + + // Enter Update mode + errl = enterUpdateMode(); + if (errl != nullptr) + { + break; + } + + // Verify in Update mode + errl = inUpdateMode(); + if (errl != nullptr) + { + break; + } + + // Enter Bootstrap Loader (BSL) mode to perform firmware update + errl = enterBootstrapLoaderMode(); + if (errl != nullptr) + { + break; + } + + // Unlock the device. This is a BSL command so we must already be in + // BSL mode to execute it. + errl = unlockDevice(); + if (errl != nullptr) + { + break; + } + + // Perform the configuration data segment updates. + // As of BSL 1.4 this is done via the BSL interface instead of SCAP + // registers. + errl = updateConfig(); + if (errl != nullptr) + { + // We are returning with an error. Since the error is from the + // config part of the updates it's best to erase the firmware on the + // BPM so that updates will be attempted on it in the future. + // Because there isn't a way to determine the validity of the config + // section on the BPM we're completely reliant on what the firmware + // version reports to decide if we need to update or not. If we see + // that the firmware version matches the image but for some reason + // the config data wasn't updated properly we could believe we + // updated successfully when, in fact, we just left the BPM in a bad + // state. + if ( (iv_firmwareStartAddress == MAIN_PROGRAM_ADDRESS) + || (iv_firmwareStartAddress == MAIN_PROGRAM_ADDRESS_ALT)) + { + payload_t payload; + errlHndl_t fwEraseErrl = setupPayload(payload, + BSL_MASS_ERASE, + iv_firmwareStartAddress); + if (fwEraseErrl != nullptr) + { + handleMultipleErrors(errl, fwEraseErrl); + break; + } + + fwEraseErrl = issueCommand(BPM_PASSTHROUGH, + payload, + WRITE, + ERASE_FIRMWARE_DELAY); + if (fwEraseErrl != nullptr) + { + handleMultipleErrors(errl, fwEraseErrl); + break; + } + + TRACFCOMP(g_trac_bpm, "Bpm::updateFirmware(): " + "Performing BSL_MASS_ERASE on BPM to force full " + "update on any subsequent attempt. Sleep for 5 " + "seconds."); + longSleep(5); + } + break; + } + + } while(0); + + // Reset the device. This will exit BSL mode. + errlHndl_t exitErrl = resetDevice(); + if (exitErrl != nullptr) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::runConfigUpdates(): " + "Failed to reset the device"); + handleMultipleErrors(errl, exitErrl); + } + + // Exit update mode + exitErrl = exitUpdateMode(); + if (exitErrl != nullptr) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::runConfigUpdates(): " + "Failed to exit update mode"); + handleMultipleErrors(errl, exitErrl); + } + + + return errl; +} + +errlHndl_t Bpm::runFirmwareUpdates(BpmFirmwareLidImage i_image) +{ + TRACFCOMP(g_trac_bpm, ENTER_MRK"Bpm::runFirmwareUpdates()"); + errlHndl_t errl = nullptr; + + do { + + // Enter Update mode + errl = enterUpdateMode(); + if (errl != nullptr) + { + break; + } + + // Verify in Update mode + errl = inUpdateMode(); + if (errl != nullptr) + { + break; + } + + // Enter Bootstrap Loader (BSL) mode to perform firmware update + errl = enterBootstrapLoaderMode(); + if (errl != nullptr) + { + break; + } + + // Unlock the device. This is a BSL command so we must already be in + // BSL mode to execute it. + errl = unlockDevice(); + if (errl != nullptr) + { + break; + } + + // Run Firmware Update + errl = updateFirmware(i_image); + if (errl != nullptr) + { + break; + } + + TRACFCOMP(g_trac_bpm, "Bpm::runFirmwareUpdates(): " + "Perform final CRC check on entire BPM flash to load " + "new firmware."); + + errl = checkFirmwareCrc(); + if (errl != nullptr) + { + setAttemptAnotherUpdate(); + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm:: runFirmwareUpdates(): " + "Final CRC check failed. %s ", + (iv_attemptAnotherUpdate == false) ? + "Attempt another update..." + : "Attempts to update the BPM have failed. Firmware will not load."); + break; + } + + } while(0); + + // Reset the device. This will exit BSL mode. + errlHndl_t exitErrl = resetDevice(); + if (exitErrl != nullptr) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::runFirmwareUpdates(): " + "Failed to reset the device"); + handleMultipleErrors(errl, exitErrl); + } + + // Exit update mode + exitErrl = exitUpdateMode(); + if (exitErrl != nullptr) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::runFirmwareUpdates(): " + "Failed to exit update mode"); + handleMultipleErrors(errl, exitErrl); + } + + return errl; +} + +errlHndl_t Bpm::checkFirmwareCrc() +{ + TRACFCOMP(g_trac_bpm, ENTER_MRK"Bpm::checkFirmwareCrc()"); + errlHndl_t errl = nullptr; + + // The COMMAND_CRC_CHECK would return a 3 byte response in the following + // format: + // + // ======================================================================== + // [Status Code] [Computed_CRC_Lo] [Computed_CRC_Hi] + // ======================================================================== + // BSL_LOCKED 0x00 0x00 + // PARAMETER_ERROR 0x00 0x00 + // MAIN_FW_NOT_SUPPORT_CRC_CHECK 0x00 0x00 + // MEMORY_WRITE_CHECK_FAILED CRC_Low CRC_Hi + // WRITE_FORBIDDEN CRC_Low CRC_Hi + // VERIFY_MISMATCH CRC_Low CRC_Hi + // SUCCESSFUL_OPERATION CRC_Low CRC_Hi + // + // For status codes BSL_LOCKED, PARAMETER_ERROR, and + // MAIN_FW_NOT_SUPPORT_CRC_CHECK the response CRC values are considered + // as DONT CARE. + // + // For the remainder of the status codes the CRC values are the + // computed CRC of the image. + // + // For SUCCESSFUL_OPERATION, the RESET_VECTOR was written. + // See bpm_update.H for more info on the status codes + const uint8_t CRC_CHECK_RESPONSE_SIZE = 3; + uint8_t responseData[CRC_CHECK_RESPONSE_SIZE] = {0}; + + do { + + TRACFCOMP(g_trac_bpm, "Bpm::checkFirmwareCrc(): " + "Performing final CRC check."); + payload_t crcPayload; + errl = setupPayload(crcPayload, + BSL_CRC_CHECK, + iv_firmwareStartAddress); + if (errl != nullptr) + { + break; + } + + errl = issueCommand(BPM_PASSTHROUGH, + crcPayload, + WRITE, + NO_DELAY_EXTERNAL_RESPONSE); + if (errl != nullptr) + { + break; + } + + // Wait 10 seconds for the CRC check to complete. + TRACFCOMP(g_trac_bpm, "Bpm::checkFirmwareCrc(): " + "Allow CRC check to complete on BPM by waiting 10 seconds."); + longSleep(10); + + errl = getResponse(responseData, CRC_CHECK_RESPONSE_SIZE); + if (errl != nullptr) + { + break; + } + + TRACFCOMP(g_trac_bpm, "Bpm::checkFirmwareCrc(): " + "Response Packet CRC check status = 0x%X, CRC_Low = 0x%X, " + "CRC_Hi = 0x%X", + responseData[0], + responseData[1], + responseData[2]); + + if (responseData[0] != SUCCESSFUL_OPERATION) + { + /*@ + * @errortype + * @severity ERRORLOG::ERRL_SEV_PREDICTIVE + * @moduleid BPM_RC::BPM_CHECK_FIRMWARE_CRC + * @reasoncode BPM_RC::BPM_FIRMWARE_CRC_VERIFY_FAILURE + * @userdata1[0:7] CRC check response status code. See bpm_update.H + * @userdata1[8:15] CRC low byte + * @userdata1[16:23] CRC high byte + * @userdata2[0:63] NVDIMM Target HUID associated with this BPM + * @devdesc The firmware CRC check failed. Cross check the + * CRC check response status code for more details. + * @custdesc A problem occurred during IPL of the system. + */ + errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_PREDICTIVE, + BPM_RC::BPM_CHECK_FIRMWARE_CRC, + BPM_RC::BPM_FIRMWARE_CRC_VERIFY_FAILURE, + FOUR_UINT8_TO_UINT32(responseData[0], + responseData[1], + responseData[2], + 0), + TARGETING::get_huid(iv_nvdimm)); + nvdimmAddPage4Regs(iv_nvdimm,errl); + nvdimmAddVendorLog(iv_nvdimm, errl); + break; + } + + } while(0); + + if (errl != nullptr) + { + TRACFCOMP(g_trac_bpm, ERR_MRK"Bpm::checkFirmwareCrc(): " + "Error occurred during BPM Firmware CRC check. " + "Firmware image will not load on BPM and update must be " + "attempted again."); + errl->collectTrace(BPM_COMP_NAME); + } + + return errl; +} + +/** + * @brief Helper function to handle two potential errors that might occur in a + * function that only returns a single error log. If the return error is + * not nullptr then the second error will be linked to it and committed + * if this is the final update attempt. Otherwise, it will be deleted + * since the update procedure will occur again and may be successful. + * If the return error is nullptr then the return error will point to + * the second's error and the second error will point to nullptr. + * + * @param[in/out] io_returnErrl A pointer to the error that would be + * returned by the function that called + * this one. If nullptr, then it will be + * set point to the secondary error and + * that error will become nullptr. + * + * @param[in/out] io_secondErrl The secondary error that occurred which + * in addition to the usual returned error. + */ +void Bpm::handleMultipleErrors(errlHndl_t& io_returnErrl, + errlHndl_t& io_secondErrl) +{ + if (iv_updateAttempted && (io_returnErrl != nullptr)) + { + io_secondErrl->plid(io_returnErrl->plid()); + TRACFCOMP(g_trac_bpm, "Committing second error eid=0x%X with plid of " + "returned error: 0x%X", + io_secondErrl->eid(), + io_returnErrl->plid()); + io_secondErrl->collectTrace(BPM_COMP_NAME); + io_secondErrl->addPartCallout(iv_nvdimm, + HWAS::BPM_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + ERRORLOG::errlCommit(io_secondErrl, BPM_COMP_ID); + } + else if (io_returnErrl == nullptr) + { + io_returnErrl = io_secondErrl; + io_secondErrl = nullptr; + } + else + { + // Another update attempt will be made, delete this secondary error. + delete io_secondErrl; + io_secondErrl = nullptr; + } +} + +uint16_t Bpm::crc16_calc(const void* i_ptr, int i_size) +{ + uint16_t crc = 0xFFFF; + const uint8_t* data = reinterpret_cast<const uint8_t*>(i_ptr); + + while (--i_size >= 0) + { + crc = crc ^ *(data++) << 8; + for (size_t i = 0; i < 8; ++i) + { + if (crc & 0x8000) + { + crc = crc << 1 ^ 0x1021; + } + else + { + crc = crc << 1; + } + } + } + + return (crc & 0xFFFF); +} + +}; // End of BPM namespace +}; // End of NVDIMM namespace diff --git a/src/usr/isteps/nvdimm/bpm_update.H b/src/usr/isteps/nvdimm/bpm_update.H new file mode 100644 index 000000000..4886a8abd --- /dev/null +++ b/src/usr/isteps/nvdimm/bpm_update.H @@ -0,0 +1,1078 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/isteps/nvdimm/bpm_update.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +#ifndef BPM_UPDATE_H +#define BPM_UPDATE_H + +/* @file bpm_update.H + * + * + */ + +#include <vector> +#include <errl/errlentry.H> +#include <targeting/common/util.H> + +namespace NVDIMM +{ +namespace BPM +{ + +/* + * All of the various commands used for the BPM update. All commands can only be + * sent after write protection on the BPM has been disabled and the update magic + * values have been written to the BPM's magic registers. + * + * BSL: Bootstrap Loader commands + * BPM: Backup Power Module +*/ +enum COMMAND : uint8_t +{ + // A payload sent with this command will be interpreted and processed by the + // NVDIMM module. + BPM_LOCAL = 0xFF, + + /* + * These are LOCAL commands. These commands MUST be sent only outside of BSL + * BSL mode and must be paired with the BSP command BPM_LOCAL. Otherwise, + * unpredicatable errors will occur. + * + * When using issueCommand() for these commands they should always be sent + * with a 0 ms delay. This will ensure that the response packet is not + * checked from the BPM. Since these are processed by the NVDIMM it makes + * no sense to get a response from the BPM and attempting to do so will + * cause errors. + */ + BCL_ENTER_BSL_MODE = 0x01, + BCL_IS_BSL_MODE = 0x02, + BCL_WRITE_REG = 0x03, + BCL_START_UPDATE = 0x04, + BCL_END_UPDATE = 0x05, + BCL_IS_UPDATE_IN_PROGRESS = 0x06, + + // A payload sent with this command will be sent transparently to the BPM. + // This command must only be used while the BPM is in BSL mode. + BPM_PASSTHROUGH = 0xFE, + + /* + * These are PASSTHROUGH commands. These commands MUST be sent only while in + * BSL mode and must be paired with BSP command BPM_PASSTHROUGH. Otherwise, + * unpredicatable errors will occur. + */ + // Writes a block of data to the BPM. + // Delay 1ms (default) + BSL_RX_DATA_BLOCK = 0x10, + // Unlocks the BPM that is in BSL mode so that updates can occur. + // Delay 1ms (default) + BSL_RX_PASSWORD = 0x11, + // Erases 128 bytes at the given address offset. + // WARNING: Due to BSL memory limitations, BSL cannot verify the address + // is a valid config segment address offset and will blindly + // erase 128 bytes of data starting at that offset. If an invalid + // address is sent then the BPM will be bricked in a very + // unpredicatable/unrecoverable way. + // Delay 250ms + BSL_ERASE_SEGMENT = 0x12, + // Unknown, unused. + // Delay 0ms + BSL_TOGGLE_INFO = 0x13, + // Unknown, unused. + // Delay 1ms (default) + BSL_ERASE_BLOCK = 0x14, + // Erases the full firmware section on the BPM. The start of the firmware + // address must be supplied with this command. + // WARNING: Due to BSL memory limitations, BSL cannot verify the address + // is a valid firmware address offset and will blindly erase 128 + // data starting at that offset. If an invalid address is sent + // then the BPM will be bricked in a very + // unpredicatable/unrecoverable way. + // Delay 250ms + BSL_MASS_ERASE = 0x15, + // Sends the command to the BPM to perform the final CRC check on the + // firmware written to the BPM. If the CRC check doesn't match the expected + // CRC in the flash image then the firmware will not load on the BPM and it + // will remain in BSL mode until new firmware is loaded onto it. + // + // Delay 0 + // The response packet must be checked externally from the issueCommand() + // function because the response packet returned from this command is unique + // to this command and will return the results of this command. For more + // info see the checkFirmwareCrc() function description, implementation, and + // the COMMAND_BSL_CRC_CHECK_RESPONSE_CODES enum. + BSL_CRC_CHECK = 0x16, + // Unknown, unused. + // Delay 1ms (default) + BSL_LOAD_PC = 0x17, + // Unknown, unused. + // Delay 1ms (default) + BSL_TX_DATA_BLOCK = 0x18, + // Checks the Bootstrap Loader mode version on the BPM. Depending on this + // version, some parts of the update procedure may have changed. + // + // Delay 0ms + // The response packet must be checked externally from the issueCommand() + // function because the response packet returned from this command is unique + // to this command and will return the results of this command. For more + // info see the readBslVersion() function description and implementation. + BSL_TX_BSL_VERSION = 0x19, + // Unknown, unused. + // Delay 1ms (default) + BSL_TX_BUFFER_SIZE = 0x1A, + // Unknown, unused. + // Delay 1ms (default) + BSL_RX_DATA_BLOCK_FAST = 0x1B, + // Resets the BPM and exits BSL mode. + // Delay 0ms + // Never check for a response packet from the BPM after sending the reset + // command because the BPM may not be back up and if it is it will not be + // in BSL mode anymore. If the response packet is checked then errors will + // occur. + BSL_RESET_DEVICE = 0x1C, + // Verifies the block of data written to the BPM flash is identical to what + // was sent to it in a prior write. For more information see the + // verifyBlockWrite() description and implementation. + // + // Delay 0ms + // The response packet must be checked externally from the issueCommand() + // function because the response packet returned from this command is unique + // to this command and will return the results of this command. + BSL_VERIFY_BLOCK = 0x1D, +}; + +// These consts serve as reminders in the code for what was explained in the +// COMMAND enum. +const int NO_DELAY_NO_RESPONSE = 0; +const int NO_DELAY_EXTERNAL_RESPONSE = 0; +const int ERASE_SEGMENT_DELAY = 250; +const int ERASE_FIRMWARE_DELAY = 250; + +// These are the various response codes returned by the BPM after the +// BSL_CRC_CHECK command is sent at the end of the update procedure. +enum COMMAND_BSL_CRC_CHECK_RESPONSE_CODES : uint16_t +{ + // The updated firmware is set up with all necessary loading parameters to + // load and execute upon reset. + SUCCESSFUL_OPERATION = 0x00, + + // Error setting up the necessary loading parameters for the updated + // firmware image. + MEMORY_WRITE_CHECK_FAILED = 0x01, + + // The command was attempted without unlocking the BSL with the password. + BSL_LOCKED = 0x04, + + // Error setting up the necessary loading parameters for the updated + // firmware image. + WRITE_FORBIDDEN = 0x06, + + // The checksum validation of the updated firmware image failed. The + // calculated checksum doesn't match the checksum data provided @FF7A in the + // firmware image file. + VERIFY_MISMATCH = 0x09, + + // The firmware image start address given for the command is wrong. + PARAMETER_ERROR = 0x0A, + + // Firmware image file used for the update doesn't hae the checksum data + // defined @FF7A + MAIN_FW_NOT_SUPPORT_CRC_CHECK = 0x0B, +}; + +// BSL versions that this code supports. +const uint8_t BSL_VERSION_1_4 = 0x14; + +// The operator types for the BPM_CMD_STATUS register +enum COMMAND_STATUS_REGISTER_OP_TYPES : uint8_t +{ + NOP = 0x00, + READ = 0x01, + WRITE = 0x02, + NO_TRASFER = 0x03, +}; + +// Used to overlay onto the LID image +struct firmware_image_block +{ + // The block size is the sizeof(iv_addressOffset) plus sizeof(iv_data). + uint8_t iv_blockSize; + + // The address offset where the first byte in iv_data came from in the + // firmware image. + uint16_t iv_addressOffset; + + // A variable sized array of firmware data. The size of which is always + // iv_blockSize - sizeof(iv_addressOffset) and the max this can be is + // MAX_PAYLOAD_SIZE. + char iv_data[0]; + +} PACKED; + +typedef firmware_image_block firmware_image_block_t; + + +// Used to overlay onto the LID image +struct config_image_fragment +{ + // The fragment size is the size of iv_data. + uint8_t iv_fragmentSize; + + // The offset where the first byte in iv_data should begin overwritting the + // BPM config data in the BPM configuration segment dump buffer. + uint16_t iv_offset; + + // A variable sized array of config segment data. + char iv_data[0]; + +} PACKED; + +typedef config_image_fragment config_image_fragment_t; + + +/* Max payload size is 26 bytes + * 4 bytes: header + * 1 byte: sync byte + * 1 byte: command + * 1 byte: header size + data size + * 1 byte: header size + data size + * 2 bytes: address + * 2 bytes: extra + * 16 bytes: data + * 2 bytes: CRC + */ +constexpr size_t MAX_PAYLOAD_SIZE = 26; + +// Max number of bytes data section of payload can be. +constexpr size_t MAX_PAYLOAD_DATA_SIZE = 16; + +// Number of bytes for header, address, extra, and CRC +constexpr size_t MAX_PAYLOAD_OTHER_DATA_SIZE = 10; + +// Number of bytes for the header. +constexpr uint8_t PAYLOAD_HEADER_SIZE = 4; + +// Indices of where to find certain data within a constructed payload. +// These indices have been subtracted by 1 from the given payload format because +// after a payload is constructed the sync byte is removed from the front. +constexpr uint8_t PAYLOAD_COMMAND_INDEX = 0; +constexpr uint8_t PAYLOAD_ADDRESS_START_INDEX = 3; +constexpr uint8_t PAYLOAD_DATA_START_INDEX = 7; +constexpr uint8_t PAYLOAD_HEADER_DATA_LENGTH_INDEX = 1; + +// The sync byte that must always be at the front of a BPM payload. This is used +// calculate the CRC of the payload and then removed because the nvdimm +// automatically sends the sync byte ahead of the payload. +constexpr uint8_t SYNC_BYTE = 0x80; +constexpr uint8_t SYNC_BYTE_SIZE = sizeof(uint8_t); + +// Maximum size of any segment in the config data section +constexpr size_t SEGMENT_SIZE = 128; + +// Maximum size of the config data section. +constexpr size_t ALL_SEGMENTS_SIZE = 512; + +// Number of magic registers for the BPM +constexpr size_t NUM_MAGIC_REGISTERS = 2; + +// These are the production magic values for the BPM that should be written in +// BPM_MAGIC_REG1 and BPM_MAGIC_REG2 respectively. +const uint8_t PRODUCTION_MAGIC_VALUES[NUM_MAGIC_REGISTERS] = {0x55, 0xAA}; +// These magic values to enable nvdimm-bpm interface. They must be written to +// the magic registers BEFORE writing flash updates to the BPM in BSL mode. +const uint8_t UPDATE_MODE_MAGIC_VALUES[NUM_MAGIC_REGISTERS] = {0xB0, 0xDA}; +// These are the segment read magic values that allow dumping of the segment +// data from the BPM. +const uint8_t SEGMENT_READ_MAGIC_VALUES[NUM_MAGIC_REGISTERS] = {0xBA, 0xAB}; + +typedef std::vector<uint8_t> payload_t; + + +/** + * @brief BPM_CMD_STATUS register bits + */ +struct command_status_register_bits +{ + uint8_t Abort_Request : 1; // Bit 7 + uint8_t Abort_Acknowledge : 1; // Bit 6 + uint8_t Reserved1 : 1; // Bit 5 + uint8_t Reserved2 : 1; // Bit 4 + uint8_t Error_Flag : 1; // Bit 3 + uint8_t Bsp_Cmd_In_Progress : 1; // Bit 2 + uint8_t Operator_Type : 2; // Bit 1-0 +} PACKED; + +/** + * @brief Union simplifying manipulation of REG_CMD_STATUS value + */ +union command_status_register_union +{ + uint8_t value; + command_status_register_bits bits; + + /** + * @brief Constructor + */ + command_status_register_union() + : value(0) + {} + +} PACKED; + +typedef command_status_register_union command_status_register_t; + +class BpmFirmwareLidImage +{ +public: + + /** + * @brief Constructor that sets access to LID information + * + * @param[in] i_lidImageAddr virtual address where LID was loaded + * @param[in] i_size size of the loaded LID + */ + BpmFirmwareLidImage(void * const i_lidImageAddr, size_t i_size); + + /** + * @brief Returns the version of the firmware binary as a uint16_t + * + * @return uint16_t version of the firmware image as MMmm. + * MM = major version, mm = minor. + */ + uint16_t getVersion() const; + + /** + * @brief Returns the number of blocks in the LID image. + * + */ + uint16_t getNumberOfBlocks() const; + + /** + * @brief Returns a pointer to the first block in LID image. + */ + void const * getFirstBlock() const; + + /* Layout of the BPM Firmware image + * Byte 1: Major version number (MM) + * Byte 2: Minor version number (mm) + * Byte 3-4: N number of blocks in the file (NN NN) + * Byte 5-EOF: Blocks of the form: + * BLOCK_SIZE Byte 1: X number of bytes in block excluding + * this byte. (XX) + * ADDRESS_OFFSET Byte 2-3: Original address offset of the + * first data byte. (AD DR) + * DATA_BYTES Byte 4-X: Firmware data bytes (DD) + * + * Example file: + * 01 03 00 01 06 80 00 6a 14 31 80 + * MM mm NN NN XX AD DR DD DD DD DD + */ + typedef struct firmware_image_header + { + uint8_t iv_versionMajor; + uint8_t iv_versionMinor; + uint16_t iv_numberOfBlocks; + } firmware_image_header_t; + +private: + + // Pointer to the LID image allocated outside of the class + void * const iv_lidImage; + + // The size of the LID image. + size_t iv_lidImageSize; +}; + + +class BpmConfigLidImage +{ +public: + + /** + * @brief Constructor that sets access to LID information + * + * @param[in] i_lidImageAddr virtual address where LID was loaded + * @param[in] i_size size of the loaded LID + */ + BpmConfigLidImage(void * const i_lidImageAddr, size_t i_size); + + /** + * @brief Returns the version of the config binary as a uint16_t. There isn't + * a way to check the version of the config data on the BPM but the + * config binary still has the version of the flash image it + * originally came from. + * + * @return uint16_t version of the firmware image as MMmm. + * MM = major version, mm = minor. + */ + uint16_t getVersion() const; + + /** + * @brief Returns the number of fragments in the LID image. + * + */ + uint16_t getNumberOfFragments() const; + + /** + * @brief Returns a pointer to the first fragment in LID image. + */ + void const * getFirstFragment() const; + + /* The binary will be organized in the following way: + * Byte 1: Major version number (MM) + * Byte 2: Minor version number (mm) + * Byte 3: N number of fragments in the file (NN) + * Byte 4-EOF: Fragments of the form: + * FRAGMENT_SIZE Byte 1: X number of bytes in fragment data + * section. (XX) + * INDEX_OFFSET Byte 2-3: Each BPM's config section is unique + * to itself. So, during the update + * the contents of a BPM's config data + * will be dumped into a buffer. + * These two bytes will be used as an + * offset into that buffer from which + * overwritting will take place. + * (IN DX) + * DATA_BYTES Byte 4-X: Fragment data bytes to be written + * at the INDEX_OFFSET in the dumped + * config data buffer. (DD) + * + * Example file output: + * 01 05 01 04 01 28 6a 14 31 80 + * MM mm NN XX IN DX DD DD DD DD + */ + typedef struct config_image_header + { + uint8_t iv_versionMajor; + uint8_t iv_versionMinor; + uint16_t iv_numberOfFragments; + } config_image_header_t; + +private: + + // Pointer to the LID image allocated outside of the class + void * const iv_lidImage; + + // The size of the LID image. + size_t iv_lidImageSize; +}; + +class Bpm +{ + /* + * The Bpm can either be in Bootstrap Loader (BSL) mode or not. Many of + * member functions utilize BSL mode for the update procedure and must + * therefore be in BSL mode to succeed. Other functions perform operations + * that will not work in BSL mode since that mode is strictly for updating + * the device and turns of some functionality while in that mode. The "mode" + * the BPM must be in is given in the function brief description. + */ +public: + + + explicit Bpm(const TARGETING::TargetHandle_t i_nvdimm); + + // Force User to supply a nvdimm target. + Bpm() = delete; + + /** + * @brief Runs the BPM firmware update using the given image. + * + * @param[in] i_image The BPM firmware image. + * + * @return errlHndl_t nullptr on success. Otherwise, pointer to an + * errlEntry. + */ + errlHndl_t runUpdate(BpmFirmwareLidImage i_fwImage, + BpmConfigLidImage i_configImage); + + /** + * @brief At most, one full update retry should occur in some + * circumstances. If one of those occurances happens then the + * member iv_attemptAnotherUpdate will be set to true. Otherwise, it + * will remain false. + * + * @return bool true if another update should be attempted. + * Otherwise, false. + */ + bool attemptAnotherUpdate(); + + /** + * @brief Returns if an update has been attempted on this BPM. + * + * @return bool true if an update has been attempted before. + * Otherwise, false. + */ + bool hasAttemptedUpdate(); + + /** + * @brief returns the nvdimm that is associated with this BPM. + */ + const TARGETING::TargetHandle_t getNvdimm(); + +private: + + // The nvdimm whose battery firmware will be updated. + const TARGETING::TargetHandle_t iv_nvdimm; + + // The Bootstrap Loader version of the BPM + uint8_t iv_bslVersion; + + // The firmware address for the BPM image can be either 0x8000 or 0xA000. + // This member will keep track of which one it is. + uint16_t iv_firmwareStartAddress; + + // Keeps track of if the update should be attempted again. + bool iv_attemptAnotherUpdate; + + // Buffers for the segment data in case another update attempt is needed. + // If the first update fails there won't be any running firmware on the + // device which is required to dump the segment data. + uint8_t iv_segmentD[SEGMENT_SIZE]; + uint8_t iv_segmentB[SEGMENT_SIZE]; + + // Keeps track if the segments have been merged with the flash image data + // yet. + bool iv_segmentDMerged; + bool iv_segmentBMerged; + + // Keeps track of if an update has been attempted at least once. + bool iv_updateAttempted; + + /** + * @brief Determines if another update attempt should occur for this BPM. + */ + void setAttemptAnotherUpdate(); + + /** + * @brief Gets the BSL version from the BPM and sets the iv_bslVersion + * member. Only needs to be called once. + * + * @return errlHndl_t nullptr on success. Otherwise, pointer to an + * errlEntry. + */ + errlHndl_t readBslVersion(); + + /** + * @brief Gets the Firmware version from the BPM + * + * @param[out] o_fwVersion The firmware version currently on the BPM. + * + * @return errlHndl_t nullptr on success. Otherwise, pointer to an + * errlEntry. + */ + errlHndl_t getFwVersion(uint16_t & o_fwVersion) const; + + /** + * @brief This function issues a command to the BPM using a payload as the + * means of sending the command. + * + * @param[in] i_command The BSP command to send to the BPM. + * @param[in] i_payload The payload to write to the + * BPM_REG_PAYLOAD_START register. + * @param[in] i_opType The operation type of the command. Must be one + * of the COMMAND_STATUS_REGISTER_OP_TYPES + * + * @param[in] i_msDelay How long to wait before the response from the + * BPM should be checked. Default 1 ms. If a delay + * of 0 ms is given then the response will not be + * read and it is the caller's responsibilty to + * check the response status. See COMMAND enum for + * required delays. + * + * @return errlHndl_t nullptr on success. Otherwise, pointer to an + * errlEntry. + */ + errlHndl_t issueCommand(uint8_t i_command, + payload_t i_payload, + uint8_t i_opType, + int i_msDelay = 1); + + /** + * @brief This function issues a BSP command to the BPM by setting up a + * payload containing only that command and then calling the + * issueCommand function that accepts a payload as an argument. + * + * NOTE: Since the BSP command is not a BSL command, it doesn't need + * to be formatted as a BSL payload but it still must be written to + * the BPM_REG_PAYLOAD_START register. + * + * @param[in] i_bspCommand The BSP command to send to the BPM. + * @param[in] i_command The BCL command to be written to the + * BPM_REG_PAYLOAD_START register. Must be one + * of the BCL_ commands. + * @param[in] i_opType The operation type of the BSP command. Must + * be a COMMAND_STATUS_REGISTER_OP_TYPES + * + * @param[in] i_msDelay How long to wait before the response from the + * BPM should be checked. Default 1 ms. If a delay + * of 0 ms is given then the response will not be + * read and it is the caller's responsibilty to + * check the response status. See COMMAND enum for + * required delays. + * + * @return errlHndl_t nullptr on success. Otherwise, pointer to an + * errlEntry. + */ + errlHndl_t issueCommand(uint8_t i_bspCommand, + uint8_t i_command, + uint8_t i_opType, + int i_msDelay = 1); + + /** + * @brief This function checks if the BPM has entered update mode + * + * @return errlHndl_t nullptr on success. + * Otherwise, pointer to an errlEntry. + */ + errlHndl_t inUpdateMode(); + + /** + * @brief Send the command to the BPM to enter update mode + * + * @return errlHndl_t nullptr if no errors occurred during command + * execution. Otherwise, pointer to an errlEntry. + */ + errlHndl_t enterUpdateMode(); + + /** + * @brief Send the command to the BPM to exit update mode + * + * @return errlHndl_t nullptr if no errors occurred during command + * execution. Otherwise, pointer to an errlEntry. + */ + errlHndl_t exitUpdateMode(); + + /** + * @brief Executes the firmware portion of the BPM update. + * + * @param[in] i_image The BPM firmware LID image to apply to the BPM. + * + * @return errlHndl_t nullptr if no errors occurred. + * Otherwise, pointer to an errlEntry. + */ + errlHndl_t updateFirmware(BpmFirmwareLidImage i_image); + + /** + * @brief Helper function that executes the firmware portion of the BPM + * update by calling all necessary functions in order. + * + * @param[in] i_image The BPM firmware LID image to apply to the BPM. + * + * @return errlHndl_t nullptr if no errors occurred. + * Otherwise, pointer to an errlEntry. + */ + errlHndl_t runFirmwareUpdates(BpmFirmwareLidImage i_image); + + /** + * @brief Executes the config portion of the BPM update. + * + * @return errlHndl_t nullptr on success. Otherwise, an Error. + */ + errlHndl_t updateConfig(); + + /** + * @brief Helper function that executes the config portion of the BPM + * update by calling all necessary functions in order. + * + * @param[in] i_image The BPM config LID image to apply to the BPM. + * + * @return errlHndl_t nullptr on success. Otherwise, an Error. + */ + errlHndl_t runConfigUpdates(BpmConfigLidImage i_image); + + /** + * @brief Commands the BPM to enter BSL mode to allow for BSL commands to be + * executed. + * + * @return errlHndl_t nullptr on success. Otherwise, pointer to an + * errlEntry. + */ + errlHndl_t enterBootstrapLoaderMode(); + + /** + * @brief Creates a valid BSL payload given a firmware_image_block_t. + * + * @param[out] o_payload The BSL payload + * @param[in] i_block A pointer to a firmware image block. + * @param[in] i_command The BSL command to be included with the payload + * + * @return errlHndl_t nullptr on success. Otherwise, pointer to an + * errlEntry. + */ + errlHndl_t setupPayload(payload_t & o_payload, + const firmware_image_block_t * i_block, + uint8_t i_command); + + /** + * @brief Creates a valid BSL payload given a BSL command, address, and + * optionally data to include with the command. This function is used + * to create firmware_image_block_t objects which are then passed + * onto the version of setupPayload that turns them into payloads. + * + * @param[out] o_payload The BSL payload + * @param[in] i_command The BSL command to be included with the payload + * @param[in] i_address The address to execute the command from. This + * will be zero or the address to execute the + * command from. + * @param[in] i_data The array of data to be included with the BSL + * command. Default nullptr. + * @param[in] i_length Length of the i_data array parameter. Default 0. + * + * @return errlHndl_t nullptr on success. Otherwise, pointer to an + * errlEntry. + */ + errlHndl_t setupPayload(payload_t & o_payload, + uint8_t i_command, + uint16_t i_address, + const uint8_t i_data[] = nullptr, + size_t i_length = 0); + + /** + * @brief This function unlocks the BPM. + * + * @return errlHndl_t nullptr on success. Otherwise, pointer to an + * errlEntry. + */ + errlHndl_t unlockDevice(); + + /** + * @brief This function will send the command to reset the BPM. This will + * exit BSL mode if the BPM was in that mode. + * + * @return errlHndl_t nullptr on success. Otherwise, pointer to an + * errlEntry. + */ + errlHndl_t resetDevice(); + + /** + * @brief Write to the BPM register via the SCAP registers + * + * @param[in] i_reg The BPM register to write to. + * + * @param[in] i_data The data to write to the given register. + * + * @return errlHndl_t nullptr on success. Otherwise, an error. + */ + errlHndl_t writeViaScapRegister(uint8_t i_reg, uint8_t i_data); + + /** + * @brief Reads the BPM register via the SCAP registers + * + * @param[in] i_reg The BPM register to read from. + * + * @param[in/out] io_data The data that was in the given register. + * + * @return errlHndl_t nullptr on success. Otherwise, an error. + */ + errlHndl_t readViaScapRegister(uint8_t i_reg, uint8_t & io_data); + + /** + * @brief Disables write protection on the BPM by sending the password + * sequence to I2C_REG_PROTECT + * + * @return errlHndl_t nullptr on success. Otherwise, an error. + */ + errlHndl_t disableWriteProtection(); + + /** + * @brief Many operations performed on the BPM require the magic registers + * to have specific values written in them. This function acts as a + * helper to facilitate that process. + * + * NOTE: Write protection on the BPM must be disabled, otherwise + * this function will fail. + * + * @param[in] i_magicValues The pair of magic values to be written to + * BPM_MAGIC_REG1 and BPM_MAGIC_REG2 + * respectively. + * + * @return errlHndl_t nullptr on success. Otherwise, an error. + */ + errlHndl_t writeToMagicRegisters( + uint8_t const (&i_magicValues)[NUM_MAGIC_REGISTERS]); + + /** + * @brief Switches the page on the BPM to the given page. This function + * must be executed only after the segment read magic values have + * been written to the BPM's magic registers. + * + * @param[in] i_segmentCode The segment code that corresponds to the + * page to switch to on the BPM. + * + * @return errlHndl_t nullptr on success. Otherwise, an error + * + */ + errlHndl_t switchBpmPage(uint16_t i_segmentCode); + + /** + * @brief Dumps the given segment data from the BPM. CANNOT be in BSL mode. + * + * @param[in] i_segmentCode The segment code that corresponds to the + * segment to dump from the BPM. + * + * @param[out] o_buffer A pointer to the buffer to fill with segment + * data. Must be SEGMENT_SIZE in size. + * + * @return errlHndl_t nullptr on success. Otherwise, an error + * + */ + errlHndl_t dumpSegment(uint16_t i_segmentCode, + uint8_t (&o_buffer)[SEGMENT_SIZE]); + + /** + * @brief Merges the segment data dumped from the BPM with the segment data + * fragments present in the BpmConfigLidImage that correspond to the + * given segment code. + * + * @param[in] i_configImage The image that holds the fragments of + * segment data. + * + * @param[in] i_segmentCode The segment code that corresponds to the + * segment to dump from the BPM. + * + * @param[out] o_buffer The merged segment data for the BPM. + * Must be SEGMENT_SIZE in length. + * + * @return errlHndl_t nullptr on success. Otherwise, an error. + */ + errlHndl_t mergeSegment(BpmConfigLidImage i_configImage, + uint16_t i_segmentCode, + uint8_t (&o_buffer)[SEGMENT_SIZE]); + + /** + * @brief Commands the BPM to erase the segment data on the BPM using the + * given segment code to tell it which to erase. + * The BPM must be in BSL mode for this function to work. + * + * @param[in] i_segmentCode The segment from the config data section to + * erase. + * + * @return errlHndl_t nullptr on success. Otherwise, an error. + */ + errlHndl_t eraseSegment(uint16_t i_segmentCode); + + /** + * @brief Writes the segment data from the buffer to the BPM using the + * given segment code to determine which segment the data belongs + * to. The BPM must be in BSL mode for this function to work. + * + * @param[in] i_buffer The segment data to write to the BPM. + * + * @param[in] i_segmentCode The segment from the config data section the + * data belongs to. + * + * @return errlHndl_t nullptr on success. Otherwise, an error. + */ + errlHndl_t writeSegment(uint8_t const (&i_buffer)[SEGMENT_SIZE], + uint16_t i_segmentCode); + + /** + * @brief Dumps segment D and B data from the BPM and merges it with the + * data from the config image to create the unique updated segments + * for this BPM. The BPM CANNOT be in BSL mode for this function to + * work because the data is dumped using SCAP registers. There must + * also be working firmware on the device otherwise this will fail. + * + * @param[in] i_configImage The config image that has the fragments to + * merge into the BPM's existing segment data. + * + * @return errlHndl_t nullptr on success. Otherwise, an error. + */ + errlHndl_t preprocessSegments(BpmConfigLidImage i_configImage); + + /** + * @brief Verifies that the data written into the flash on the BPM is what + * was sent by hostboot in a payload. + * + * @param[in] i_payload The payload that was just sent to the BPM to + * be verified. + * + * @param[in] i_dataLength The length of the data section of the + * payload. + * + * @param[in] o_status The status code returned from the BPM. + * A status of 0 indicates success, all other + * values are a failure. + * + * @return errlHndl_t nullptr if no errors. Otherwise, an error. + */ + errlHndl_t verifyBlockWrite(payload_t i_payload, + uint8_t i_dataLength, + uint8_t & o_status); + + /** + * @brief Attempts a BSL_RX_DATA_BLOCK command up to three times by calling + * blockWriteRetry. + * + * @param[in] i_payload The payload containing the BSL_RX_DATA_BLOCK + * command and the data to be attempted to be + * written. + * + * @return errlHndl_t nullptr on success. Otherwise, an error. + */ + errlHndl_t blockWrite(payload_t i_payload); + + /** + * @brief Attempts a BSL_RX_DATA_BLOCK command up to three times. + * + * @param[in] i_payload The payload containing the BSL_RX_DATA_BLOCK + * command and the data to be attempted to be + * written. + * + * @return errlHndl_t nullptr on success. Otherwise, an error. + */ + errlHndl_t blockWriteRetry(payload_t i_payload); + + /** + * @brief A helper function used to wait for the command status bit to reset + * after a command is executed. + * + * @param[in] i_commandStatus The command status register union made + * by the caller to identify the type of + * command that was sent. + * + * @return errlHndl_t nullptr on success. Otherwise, an error. + */ + errlHndl_t waitForCommandStatusBitReset( + command_status_register_t i_commandStatus); + + errlHndl_t verifyGoodBpmState(); + + /** + * @brief Helper function for the SCAP register functions that will poll + * the busy bit in SCAP_STATUS until it is zero. + * + * @return errlHndl_t nullptr on success. Otherwise, an error. + */ + errlHndl_t waitForBusyBit(); + + /** + * @brief Starting with BSL version 1.4 it is necessary to check the CRC of + * the firmware image once it has been written to the BPM. If this + * is not done or fails to succeed then the firmware image will not + * be loaded and executed by the BPM. If the CRC check fails then + * the update must be attempted again. + * Must be in BSL mode. + * + * @return errlHndl_t nullptr on success. Otherwise, an error. + */ + errlHndl_t checkFirmwareCrc(); + + /** + * @brief After a command is sent to the BPM to request info from it this + * function processes the response and returns it to the caller. + * A response packet can only be received once per command sent to + * the BPM. Which means that the caller must resend the command + * again to get another response packet. Simply calling the function + * repeatedly will not work. BPM must be in BSL mode. + * + * @param[in] o_responseData The buffer to be filled with the + * response data from the BPM. + * + * @param[in] i_responseSize The size of the buffer to be filled. + * + * @return errlHndl_t nullptr on success. Otherwise, an error. + */ + errlHndl_t getResponse(uint8_t * o_responseData, + uint8_t i_responseSize); + + + /** + * @brief Helper function to handle two potential errors that might occur in a + * function that only returns a single error log. If the return error is + * not nullptr then the second error will be linked to it and committed + * if this is the final update attempt. Otherwise, it will be deleted + * since the update procedure will occur again and may be successful. + * If the return error is nullptr then the return error will point to + * the second's error and the second error will point to nullptr. + * + * @param[in/out] io_returnErrl A pointer to the error that would be + * returned by the function that called + * this one. If nullptr, then it will be + * set point to the secondary error and + * that error will become nullptr. + * + * @param[in/out] io_secondErrl The secondary error that occurred which + * in addition to the usual returned error. + */ + void handleMultipleErrors(errlHndl_t& io_returnErrl, + errlHndl_t& io_secondErrl); + + /** + * @brief Calculates the CRC16 bytes for the BSL payload. This CRC differs + * from the NVDIMM CRC calculation in that the initial value is + * 0xFFFF instead of 0x0000. + * + * NOTE: To calculate a correct CRC for the BSL payload the SYNC_BYTE + * must be included in the payload despite the fact that it + * should be removed from the payload before sending to the BPM + * because the NVDIMM sends the SYNC_BYTE automatically. + * + * @param[in] i_ptr A pointer to the start of the data to calculate the + * CRC for. + * @param[in] i_size This size of the data pointed at by i_ptr. + * + * @return uint16_t The CRC bytes. + */ + uint16_t crc16_calc(const void* const i_ptr, int i_size); + + +}; + +typedef std::vector<Bpm> bpmList_t; + +/** + * @brief Runs the firmware and config updates on the list of BPMs given. + * + * @param[in] i_16gb_BPMs The list of BPMs sitting on 16gb NVDIMMs that + * potentially need to be updated. + * + * @param[in] i_32gb_BPMs The list of BPMs sitting on 32gb NVDIMMs that + * potentially need to be updated. + * + * @param[in] i_16gb_fwImage The firmware image associated with BPMs sitting + * on 16gb NVDIMMs. + * + * @param[in] i_32gb_fwImage The firmware image associated with BPMs sitting + * on 32gb NVDIMMs. + * + * @param[in] i_16gb_configImage The configuration data associated with BPMs + * sitting on 16gb NVDIMMs. + * + * @param[in] i_32gb_configImage The configuration data associated with BPMs + * sitting on 32gb NVDIMMs. + * + */ +void runBpmUpdates(bpmList_t * const i_16gb_BPMs, + bpmList_t * const i_32gb_BPMs, + BpmFirmwareLidImage * const i_16gb_fwImage, + BpmFirmwareLidImage * const i_32gb_fwImage, + BpmConfigLidImage * const i_16gb_configImage, + BpmConfigLidImage * const i_32gb_configImage); + +}; // end of BPM namespace +}; // end of NVDIMM namespace + +#endif + diff --git a/src/usr/isteps/nvdimm/errlud_nvdimm.C b/src/usr/isteps/nvdimm/errlud_nvdimm.C index 743297b94..07afa187a 100644 --- a/src/usr/isteps/nvdimm/errlud_nvdimm.C +++ b/src/usr/isteps/nvdimm/errlud_nvdimm.C @@ -158,9 +158,53 @@ UdNvdimmParms::UdNvdimmParms( uint8_t i_opType, } //------------------------------------------------------------------------------ -UdNvdimmParms::~UdNvdimmParms() -{ +UdNvdimmParms::~UdNvdimmParms() = default; +//------------------------------------------------------------------------------ +// NVDIMM Dimm Operation Parameters and Errors +//------------------------------------------------------------------------------ +UdNvdimmOPParms::UdNvdimmOPParms( const nvdimm_reg_t &i_RegInfo ) +{ + // Version control for ErrorUD struct + iv_CompId = NVDIMM_COMP_ID; + iv_Version = 3; + iv_SubSection = NVDIMM_OP_PARAMETERS; + + //***** Memory Layout ***** + // 1 byte : MODULE_HEALTH + // 1 byte : MODULE_HEALTH_STATUS0 + // 1 byte : MODULE_HEALTH_STATUS1 + // 1 byte : CSAVE_STATUS + // 1 byte : CSAVE_INFO + // 1 byte : CSAVE_FAIL_INFO0 + // 1 byte : CSAVE_FAIL_INFO1 + // 1 byte : CSAVE_TIMEOUT_INFO0 + // 1 byte : CSAVE_TIMEOUT_INFO1 + // 1 byte : ERROR_THRESHOLD_STATUS + // 1 byte : NVDIMM_READY + // 1 byte : NVDIMM_CMD_STATUS0 + // 1 byte : ABORT_CMD_TIMEOUT + // 1 byte : ERASE_STATUS + // 1 byte : ERASE_FAIL_INFO + // 1 byte : ERASE_TIMEOUT0 + // 1 byte : ERASE_TIMEOUT1 + // 1 byte : SET_ES_POLICY_STATUS + // 1 byte : RESTORE_STATUS + // 1 byte : RESTORE_FAIL_INFO + // 1 byte : RESTORE_TIMEOUT0 + // 1 byte : RESTORE_TIMEOUT1 + // 1 byte : ARM_STATUS + // 1 byte : ARM_FAIL_INFO + // 1 byte : ARM_TIMEOUT0 + // 1 byte : ARM_TIMEOUT1 + // 1 byte : SET_EVENT_NOTIFICATION_STATUS + // 1 byte : ENCRYPTION_CONFIG_STATUS + + char * l_pBuf = reinterpret_cast<char *>( reallocUsrBuf(sizeof(i_RegInfo))); + memcpy(l_pBuf, &i_RegInfo, sizeof(i_RegInfo)); } +// Default the deconstructor +UdNvdimmOPParms::~UdNvdimmOPParms() = default; + } // end NVDIMM namespace diff --git a/src/usr/isteps/nvdimm/errlud_nvdimm.H b/src/usr/isteps/nvdimm/errlud_nvdimm.H index 55b5f9b20..2041da054 100644 --- a/src/usr/isteps/nvdimm/errlud_nvdimm.H +++ b/src/usr/isteps/nvdimm/errlud_nvdimm.H @@ -61,12 +61,37 @@ class UdNvdimmParms : public ERRORLOG::ErrlUserDetails */ virtual ~UdNvdimmParms(); - private: // Disabled - UdNvdimmParms(UdNvdimmParms &); - UdNvdimmParms & operator=(UdNvdimmParms &); + UdNvdimmParms(UdNvdimmParms &) = delete; + UdNvdimmParms & operator=(UdNvdimmParms &) = delete; }; -} // end NVDIMM namespace +/** + * @class UdNvdimmOPParms + * + * Adds NVDIMM information to an error log as user detail data + */ +class UdNvdimmOPParms : public ERRORLOG::ErrlUserDetails +{ + public: + /** + * @brief Constructor + * + * @param i_i2cInfo Miscellaneous Parameters + */ + UdNvdimmOPParms( const nvdimm_reg_t &i_RegInfo ); + + /** + * @brief Destructor + */ + virtual ~UdNvdimmOPParms(); + + // Disabled + UdNvdimmOPParms() = delete; + UdNvdimmOPParms(UdNvdimmOPParms &) = delete; + UdNvdimmOPParms & operator=(UdNvdimmOPParms &) = delete; +}; + +} // end of namespace NVDIMM #endif diff --git a/src/usr/isteps/nvdimm/nvdimm.C b/src/usr/isteps/nvdimm/nvdimm.C index 79d7b679d..e93271e5e 100644 --- a/src/usr/isteps/nvdimm/nvdimm.C +++ b/src/usr/isteps/nvdimm/nvdimm.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014,2019 */ +/* Contributors Listed Below - COPYRIGHT 2014,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -28,6 +28,8 @@ #include <errl/errlentry.H> #include <errl/errlmanager.H> #include <errl/errludtarget.H> +#include <errl/errludlogregister.H> +#include <errl/errludstring.H> #include <targeting/common/commontargeting.H> #include <targeting/common/util.H> #include <targeting/common/utilFilter.H> @@ -36,33 +38,39 @@ #include <fapi2.H> #include <fapi2/plat_hwp_invoker.H> #include <lib/shared/nimbus_defaults.H> +#include <lib/ccs/ccs_nimbus.H> #include <lib/dimm/ddr4/nvdimm_utils.H> #include <lib/mc/port.H> #include <isteps/nvdimm/nvdimmreasoncodes.H> +#include "errlud_nvdimm.H" +#include "nvdimmErrorLog.H" #include <isteps/nvdimm/nvdimm.H> #include <vpd/spdenums.H> +#include <secureboot/trustedbootif.H> +#include <targeting/common/targetUtil.H> +#ifdef __HOSTBOOT_RUNTIME +#include <runtime/hbrt_utilities.H> +#include <targeting/runtime/rt_targeting.H> +#else +#include <initservice/istepdispatcherif.H> +#endif using namespace TARGETING; using namespace DeviceFW; using namespace EEPROM; +using namespace ERRORLOG; trace_desc_t* g_trac_nvdimm = NULL; TRAC_INIT(&g_trac_nvdimm, NVDIMM_COMP_NAME, 2*KILOBYTE); // Easy macro replace for unit testing -#define TRACUCOMP(args...) TRACFCOMP(args) -//#define TRACUCOMP(args...) +//#define TRACUCOMP(args...) TRACFCOMP(args) +#define TRACUCOMP(args...) namespace NVDIMM { #define NUM_OFFSET 2 -#define NVDIMM_SET_USER_DATA_1(left_32_ops_id, right_32_huid) \ - TWO_UINT32_TO_UINT64(left_32_ops_id, right_32_huid) - -#define NVDIMM_SET_USER_DATA_2_TIMEOUT(left_32_polled, right_32_timeout) \ - NVDIMM_SET_USER_DATA_1(left_32_polled, right_32_timeout) - typedef struct ops_timeoutInfo{ const char * desc; @@ -83,6 +91,173 @@ constexpr ops_timeoutInfo_t timeoutInfoTable[] = {"CHARGE", {ES_CHARGE_TIMEOUT1, ES_CHARGE_TIMEOUT0}, CHARGE , MODULE_HEALTH_STATUS1, CHARGE_IN_PROGRESS}, }; +// Definition of ENCRYPTION_CONFIG_STATUS -- page 5 offset 0x20 +typedef union { + uint8_t whole; + struct + { + uint8_t reserved : 1; // [7] + uint8_t unsupported_field : 1; // [6] + uint8_t erase_pending : 1; // [5] + uint8_t encryption_unlocked : 1; // [4] + uint8_t encryption_enabled : 1; // [3] + uint8_t erase_key_present : 1; // [2] + uint8_t random_string_present : 1; // [1] + uint8_t encryption_supported : 1; // [0] + } PACKED; +} encryption_config_status_t; + +// Valid bits to check against (skips reserved and unsupported) +static constexpr uint8_t ENCRYPTION_STATUS_CHECK_MASK = 0x3F; +static constexpr uint8_t ENCRYPTION_STATUS_DISABLED = 0x01; +static constexpr uint8_t ENCRYPTION_STATUS_ENABLED = 0x1F; + +// NV_STATUS masks +static constexpr uint8_t NV_STATUS_OR_MASK = 0xFB; +static constexpr uint8_t NV_STATUS_AND_MASK = 0x04; +static constexpr uint8_t NV_STATUS_UNPROTECTED_SET = 0x01; +static constexpr uint8_t NV_STATUS_UNPROTECTED_CLR = 0xFE; +static constexpr uint8_t NV_STATUS_ENCRYPTION_SET = 0x10; +static constexpr uint8_t NV_STATUS_ENCRYPTION_CLR = 0xEF; +static constexpr uint8_t NV_STATUS_ERASE_VERIFY_SET = 0x20; +static constexpr uint8_t NV_STATUS_ERASE_VERIFY_CLR = 0xDF; +static constexpr uint8_t NV_STATUS_POSSIBLY_UNPROTECTED_SET = 0x40; + +// NVDIMM key consts +static constexpr size_t NUM_KEYS_IN_ATTR = 3; +static constexpr size_t MAX_TPM_SIZE = 34; +static constexpr uint8_t KEY_TERMINATE_BYTE = 0x00; +static constexpr uint8_t KEY_ABORT_BYTE = 0xFF; + +// NVDIMM CSAVE_FAIL_INFO1 Bit mask +// Currently only bits 1:6 need to be checked during init +static constexpr uint8_t CSAVE_FAIL_BITS_MASK = 0x7E; + +// LOG PAGE INFO +static constexpr size_t VENDOR_LOG_UNIT_SIZE = 256; +static constexpr size_t VENDOR_LOG_BLOCK_SIZE = 32; +static constexpr size_t VENDOR_BLOCK_DATA_BYTES = 32; + +// TYPED_BLOCK_DATA +static constexpr uint8_t VENDOR_DATA_TYPE = 0x04; +static constexpr uint8_t VENDOR_DEFAULT = 0x00; +static constexpr uint8_t FIRMWARE_IMAGE_DATA = 0x02; + +// Commands to OPERATIONAL_UNIT_OPS_CMD +static constexpr uint8_t GET_OPERATIONAL_UNIT = 0x01; +static constexpr uint8_t GENERATE_OPERATIONAL_UNIT_CKSUM = 0x08; + +static constexpr uint8_t MSBIT_SET_MASK = 0x80; +static constexpr uint8_t MSBIT_CLR_MASK = 0x7F; +static constexpr uint8_t OPERATION_SLEEP_SECONDS = 0x1; + +// Bit mask for checking the fw slot running +static constexpr uint8_t RUNNING_FW_SLOT = 0xF0; + +// NOTE: If the ARM_MAX_RETRY_COUNT is greater than 1 then +// previous error logs may be lost and not reported +static constexpr size_t ARM_MAX_RETRY_COUNT = 1; +static constexpr uint8_t FW_OPS_UPDATE = 0x04; + +// Secure erase verify operations +static constexpr uint8_t ERASE_VERIFY_CLEAR = 0x00; +static constexpr uint8_t ERASE_VERIFY_START = 0xC0; +static constexpr uint8_t ERASE_VERIFY_TRIGGER = 0x80; + +#ifndef __HOSTBOOT_RUNTIME +// Warning thresholds +static constexpr uint8_t THRESHOLD_ES_LIFETIME = 0x07; // 7% +static constexpr uint8_t THRESHOLD_NVM_LIFETIME = 0x31; // 49% + +// 12 bit fixed point temperature in celsius degrees +// with following bit format: +// [15:13]Reserved +// [12]Sign 0 = positive, 1 = negative The value of 0 C should be expressed as a positive value +// [11]128 [10]64 [9]32 [8]16 [7]8 [6]4 [5]2 [4]1 [3]0.5 [2]0.25 +// [1]0.125 Optional for temperature reporting fields; not used for temperature threshold fields +// [0]0.0625 Optional for temperature reporting fields; not used for temperature threshold fields +static constexpr uint8_t THRESHOLD_ES_TEMP_HIGH_1 = 0x03; // 52.5 C +static constexpr uint8_t THRESHOLD_ES_TEMP_HIGH_0 = 0x48; // 52.5 C +static constexpr uint8_t THRESHOLD_ES_TEMP_LOW_1 = 0x00; // 2.5 C +static constexpr uint8_t THRESHOLD_ES_TEMP_LOW_0 = 0x28; // 2.5 C +#endif + +// Definition of ENCRYPTION_KEY_VALIDATION -- page 5 offset 0x2A +typedef union { + uint8_t whole; + struct + { + uint8_t reserved : 5; // [7:3] + uint8_t keys_validated : 1; // [2] + uint8_t access_key_valid : 1; // [1] + uint8_t erase_key_valid : 1; // [0] + } PACKED; +} encryption_key_validation_t; + +/** + * @brief Utility function to send the value of + * ATTR_NVDIMM_ARMED to the FSP + */ +void send_ATTR_NVDIMM_ARMED( Target* i_nvdimm, + ATTR_NVDIMM_ARMED_type& i_val ); + +/** + * @brief Utility function to set ATTR_NVDIMM_ENCRYPTION_KEYS_FW + * and send the value to the FSP + */ +void set_ATTR_NVDIMM_ENCRYPTION_KEYS_FW( + ATTR_NVDIMM_ENCRYPTION_KEYS_FW_typeStdArr& i_val ) +{ + Target* l_sys = nullptr; + targetService().getTopLevelTarget( l_sys ); + assert(l_sys, "set_ATTR_NVDIMM_ENCRYPTION_KEYS_FW: no TopLevelTarget"); + + l_sys->setAttrFromStdArr + <ATTR_NVDIMM_ENCRYPTION_KEYS_FW>(i_val); + +#ifdef __HOSTBOOT_RUNTIME + errlHndl_t l_err = nullptr; + + // Send attr to HWSV if at runtime + AttributeTank::Attribute l_attr = {}; + if( !makeAttributeStdArr<ATTR_NVDIMM_ENCRYPTION_KEYS_FW> + (l_sys, l_attr) ) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"set_ATTR_NVDIMM_ENCRYPTION_KEYS_FW() Could not create Attribute"); + /*@ + *@errortype + *@reasoncode NVDIMM_CANNOT_MAKE_ATTRIBUTE + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid SET_ATTR_NVDIMM_ENCRYPTION_KEYS_FW + *@devdesc Couldn't create an Attribute to send the data + * to the FSP + *@custdesc NVDIMM encryption error + */ + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_PREDICTIVE, + SET_ATTR_NVDIMM_ENCRYPTION_KEYS_FW, + NVDIMM_CANNOT_MAKE_ATTRIBUTE, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT ); + l_err->collectTrace(NVDIMM_COMP_NAME); + errlCommit( l_err, NVDIMM_COMP_ID ); + } + else + { + std::vector<TARGETING::AttributeTank::Attribute> l_attrList; + l_attrList.push_back(l_attr); + l_err = sendAttributes( l_attrList ); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"set_ATTR_NVDIMM_ENCRYPTION_KEYS_FW() Error sending ATTR_NVDIMM_ENCRYPTION_KEYS_FW down to FSP"); + l_err->setSev(ERRORLOG::ERRL_SEV_PREDICTIVE); + l_err->collectTrace(NVDIMM_COMP_NAME); + errlCommit( l_err, NVDIMM_COMP_ID ); + } + } +#endif //__HOSTBOOT_RUNTIME + +} + /** * @brief Wrapper to call deviceOp to read the NV controller via I2C * @@ -103,8 +278,8 @@ errlHndl_t nvdimmReadReg(Target* i_nvdimm, uint8_t & o_data, const bool page_verify) { - TRACUCOMP(g_trac_nvdimm, ENTER_MRK"NVDIMM Read HUID %X, addr 0x%X", - TARGETING::get_huid(i_nvdimm), i_addr); + TRACUCOMP(g_trac_nvdimm, ENTER_MRK"NVDIMM Read HUID 0x%X, addr 0x%X", + get_huid(i_nvdimm), i_addr); errlHndl_t l_err = nullptr; size_t l_numBytes = 1; @@ -123,7 +298,7 @@ errlHndl_t nvdimmReadReg(Target* i_nvdimm, if (l_err) { TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmReadReg() nvdimm[%X] - failed to read the current page", - TARGETING::get_huid(i_nvdimm)); + get_huid(i_nvdimm)); break; } @@ -134,7 +309,7 @@ errlHndl_t nvdimmReadReg(Target* i_nvdimm, if (l_err) { TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmReadReg() nvdimm[%X] - failed to verify page", - TARGETING::get_huid(i_nvdimm)); + get_huid(i_nvdimm)); break; } } @@ -144,11 +319,16 @@ errlHndl_t nvdimmReadReg(Target* i_nvdimm, i_nvdimm, &o_data, l_numBytes, - DEVICE_NVDIMM_ADDRESS(l_reg_addr)); + DEVICE_NVDIMM_RAW_ADDRESS(l_reg_addr)); }while(0); - TRACUCOMP(g_trac_nvdimm, EXIT_MRK"NVDIMM Read HUID %X, page 0x%X, addr 0x%X = %X", - TARGETING::get_huid(i_nvdimm), l_reg_page, l_reg_addr, o_data); + if (l_err) + { + nvdimmAddPage4Regs(i_nvdimm,l_err); + } + + TRACUCOMP(g_trac_nvdimm, EXIT_MRK"NVDIMM Read HUID 0x%X, page 0x%X, addr 0x%X = 0x%X", + get_huid(i_nvdimm), l_reg_page, l_reg_addr, o_data); return l_err; } @@ -173,8 +353,8 @@ errlHndl_t nvdimmWriteReg(Target* i_nvdimm, uint8_t i_data, const bool page_verify) { - TRACUCOMP(g_trac_nvdimm, ENTER_MRK"NVDIMM Write HUID %X, addr 0x%X = %X", - TARGETING::get_huid(i_nvdimm), i_addr, i_data); + TRACUCOMP(g_trac_nvdimm, ENTER_MRK"NVDIMM Write HUID 0x%X, addr 0x%X = 0x%X", + get_huid(i_nvdimm), i_addr, i_data); errlHndl_t l_err = nullptr; size_t l_numBytes = 1; @@ -193,7 +373,7 @@ errlHndl_t nvdimmWriteReg(Target* i_nvdimm, if (l_err) { TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmWriteReg() nvdimm[%X] - failed to read the current page", - TARGETING::get_huid(i_nvdimm)); + get_huid(i_nvdimm)); break; } @@ -204,7 +384,7 @@ errlHndl_t nvdimmWriteReg(Target* i_nvdimm, if (l_err) { TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmWriteReg() nvdimm[%X] - failed to verify page", - TARGETING::get_huid(i_nvdimm)); + get_huid(i_nvdimm)); break; } } @@ -214,11 +394,16 @@ errlHndl_t nvdimmWriteReg(Target* i_nvdimm, i_nvdimm, &i_data, l_numBytes, - DEVICE_NVDIMM_ADDRESS(l_reg_addr)); + DEVICE_NVDIMM_RAW_ADDRESS(l_reg_addr)); }while(0); - TRACUCOMP(g_trac_nvdimm, EXIT_MRK"NVDIMM Write HUID %X, page = 0x%X, addr 0x%X = %X", - TARGETING::get_huid(i_nvdimm), l_reg_page, l_reg_addr, i_data); + if (l_err) + { + nvdimmAddPage4Regs(i_nvdimm,l_err); + } + + TRACUCOMP(g_trac_nvdimm, EXIT_MRK"NVDIMM Write HUID 0x%X, page = 0x%X, addr 0x%X = 0x%X", + get_huid(i_nvdimm), l_reg_page, l_reg_addr, i_data); return l_err; } @@ -234,43 +419,48 @@ errlHndl_t nvdimmWriteReg(Target* i_nvdimm, void nvdimmSetStatusFlag(Target *i_nvdimm, const uint8_t i_status_flag) { TRACUCOMP(g_trac_nvdimm, ENTER_MRK"nvdimmSetStatusFlag() HUID[%X], i_status_flag[%X]" - ,TARGETING::get_huid(i_nvdimm), i_status_flag); + ,get_huid(i_nvdimm), i_status_flag); - auto l_statusFlag = i_nvdimm->getAttr<TARGETING::ATTR_NV_STATUS_FLAG>(); + auto l_statusFlag = i_nvdimm->getAttr<ATTR_NV_STATUS_FLAG>(); switch(i_status_flag) { - // Make sure NSTD_VAL_PRSV (content preserved) is unset before setting NSTD_VAL_NOPRSV - // (data not preserved) or NSTD_ERR_NOPRSV (error preserving data) + // Make sure NSTD_VAL_RESTORED (content preserved) is unset before setting NSTD_VAL_ERASED + // (data not preserved) or NSTD_VAL_SR_FAILED (error preserving data) case NSTD_ERR: - case NSTD_VAL_NOPRSV: - case NSTD_ERR_NOPRSV: - l_statusFlag &= NSTD_VAL_PRSV_MASK; + case NSTD_VAL_ERASED: + case NSTD_VAL_SR_FAILED: + l_statusFlag &= NSTD_VAL_RESTORED_MASK; l_statusFlag |= i_status_flag; break; // If the content preserved(restore sucessfully), make sure - // NSTD_VAL_NOPRSV (not preserved) and NSTD_ERR_NOPRSV (error preserving) + // NSTD_VAL_ERASED (not preserved) and NSTD_VAL_SR_FAILED (error preserving) // are unset before setting this flag. - case NSTD_VAL_PRSV: - l_statusFlag &= (NSTD_VAL_NOPRSV_MASK & NSTD_ERR_NOPRSV_MASK); + case NSTD_VAL_RESTORED: + l_statusFlag &= (NSTD_VAL_ERASED_MASK & NSTD_VAL_SR_FAILED_MASK); l_statusFlag |= i_status_flag; break; - case NSTD_ERR_NOBKUP: + case NSTD_VAL_DISARMED: + l_statusFlag |= i_status_flag; + break; + + // Error detected but save/restore might work. May coexsit with other bits. + case NSTD_ERR_VAL_SR: l_statusFlag |= i_status_flag; break; default: assert(0, "nvdimmSetStatusFlag() HUID[%X], i_status_flag[%X] invalid flag!", - TARGETING::get_huid(i_nvdimm), i_status_flag); + get_huid(i_nvdimm), i_status_flag); break; } - i_nvdimm->setAttr<TARGETING::ATTR_NV_STATUS_FLAG>(l_statusFlag); + i_nvdimm->setAttr<ATTR_NV_STATUS_FLAG>(l_statusFlag); TRACUCOMP(g_trac_nvdimm, EXIT_MRK"nvdimmSetStatusFlag() HUID[%X], i_status_flag[%X]" - ,TARGETING::get_huid(i_nvdimm), i_status_flag); + ,get_huid(i_nvdimm), i_status_flag); } @@ -284,10 +474,11 @@ void nvdimmSetStatusFlag(Target *i_nvdimm, const uint8_t i_status_flag) */ errlHndl_t nvdimmReady(Target *i_nvdimm) { - TRACUCOMP(g_trac_nvdimm, ENTER_MRK"nvdimmReady() HUID[%X]",TARGETING::get_huid(i_nvdimm)); + TRACUCOMP(g_trac_nvdimm, ENTER_MRK"nvdimmReady() HUID[%X]",get_huid(i_nvdimm)); errlHndl_t l_err = nullptr; - uint8_t l_data = 0x0; + nvdimm_reg_t l_RegInfo; + uint8_t l_data; uint8_t l_nvm_init_time = 0; size_t l_numBytes = 1; @@ -300,17 +491,17 @@ errlHndl_t nvdimmReady(Target *i_nvdimm) DEVICE_SPD_ADDRESS(SPD::NVM_INIT_TIME)); TRACUCOMP(g_trac_nvdimm, "nvdimmReady() HUID[%X] l_nvm_init_time = %u", - TARGETING::get_huid(i_nvdimm), l_nvm_init_time); + get_huid(i_nvdimm), l_nvm_init_time); if (l_err) { TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmReady() nvdimm[%X] - failed to retrieve NVM_INIT_TIME from SPD", - TARGETING::get_huid(i_nvdimm)); + get_huid(i_nvdimm)); break; } - // Convert to ms for polling - uint32_t l_nvm_init_time_ms = l_nvm_init_time * MS_PER_SEC; + // Convert to ms for polling and double the value to avoid edge condition + uint32_t l_nvm_init_time_ms = l_nvm_init_time * MS_PER_SEC * 2; uint32_t l_poll = 0; do @@ -320,7 +511,7 @@ errlHndl_t nvdimmReady(Target *i_nvdimm) if (l_err) { TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmReady() nvdimm[%X] - error getting ready status[%d]", - TARGETING::get_huid(i_nvdimm), l_data); + get_huid(i_nvdimm), l_data); break; } @@ -336,8 +527,50 @@ errlHndl_t nvdimmReady(Target *i_nvdimm) if ((l_data != NV_READY) && !l_err) { + + // Collect available status registers for error log + do + { + // Read and save NVDIMM_READY for traces + l_err = nvdimmReadReg(i_nvdimm, NVDIMM_READY, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + break; + } + l_RegInfo.NVDimm_Ready = l_data; + + // Read and save MODULE_HEALTH for traces + l_err = nvdimmReadReg(i_nvdimm, MODULE_HEALTH, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + break; + } + l_RegInfo.Module_Health = l_data; + + // Read and save MODULE_HEALTH_STATUS0 for traces + l_err = nvdimmReadReg(i_nvdimm, MODULE_HEALTH_STATUS0, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + break; + } + l_RegInfo.Module_Health_Status0 = l_data; + + // Read and save MODULE_HEALTH_STATUS1 for traces + l_err = nvdimmReadReg(i_nvdimm, MODULE_HEALTH_STATUS1, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + break; + } + l_RegInfo.Module_Health_Status1 = l_data; + + }while(0); + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmReady() nvdimm[%X] - nvdimm not ready[%d]", - TARGETING::get_huid(i_nvdimm), l_data); + get_huid(i_nvdimm), l_data); /*@ *@errortype *@reasoncode NVDIMM_NOT_READY @@ -350,26 +583,33 @@ errlHndl_t nvdimmReady(Target *i_nvdimm) * for host access. (userdata1 != 0xA5) *@custdesc NVDIMM not ready */ - l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_UNRECOVERABLE, - NVDIMM_CHECK_READY, - NVDIMM_NOT_READY, - NVDIMM_SET_USER_DATA_1(l_data, TARGETING::get_huid(i_nvdimm)), - 0x0, - ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + NVDIMM_CHECK_READY, + NVDIMM_NOT_READY, + NVDIMM_SET_USER_DATA_1(l_data, get_huid(i_nvdimm)), + 0x0, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); - l_err->collectTrace(NVDIMM_COMP_NAME, 1024 ); + l_err->collectTrace(NVDIMM_COMP_NAME); // If nvdimm is not ready for access by now, this is // a failing indication on the NV controller - l_err->addPartCallout( i_nvdimm, - HWAS::NV_CONTROLLER_PART_TYPE, - HWAS::SRCI_PRIORITY_HIGH); + l_err->addHwCallout( i_nvdimm, + HWAS::SRCI_PRIORITY_HIGH, + HWAS::DECONFIG, + HWAS::GARD_Fatal); + + // Add Register Traces to error log + NVDIMM::UdNvdimmOPParms( l_RegInfo ).addToLog(l_err); + nvdimmAddPage4Regs(i_nvdimm,l_err); + nvdimmAddVendorLog(i_nvdimm, l_err); } }while(0); TRACUCOMP(g_trac_nvdimm, EXIT_MRK"nvdimmReady() HUID[%X] ready[%X]", - TARGETING::get_huid(i_nvdimm), l_data); + get_huid(i_nvdimm), l_data); return l_err; } @@ -386,7 +626,7 @@ errlHndl_t nvdimmReady(Target *i_nvdimm) */ errlHndl_t nvdimmResetController(Target *i_nvdimm) { - TRACUCOMP(g_trac_nvdimm, ENTER_MRK"nvdimmResetController() HUID[%X]",TARGETING::get_huid(i_nvdimm)); + TRACUCOMP(g_trac_nvdimm, ENTER_MRK"nvdimmResetController() HUID[%X]",get_huid(i_nvdimm)); errlHndl_t l_err = nullptr; do @@ -396,7 +636,7 @@ errlHndl_t nvdimmResetController(Target *i_nvdimm) if (l_err) { TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmResetController() nvdimm[%X] - error reseting the controller", - TARGETING::get_huid(i_nvdimm)); + get_huid(i_nvdimm)); break; } @@ -404,12 +644,17 @@ errlHndl_t nvdimmResetController(Target *i_nvdimm) if (l_err) { TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmResetController() nvdimm[%X] - not ready after reset.", - TARGETING::get_huid(i_nvdimm)); + get_huid(i_nvdimm)); } }while(0); - TRACUCOMP(g_trac_nvdimm, EXIT_MRK"nvdimmResetController() HUID[%X]",TARGETING::get_huid(i_nvdimm)); + // Reset will lock encryption so unlock again + TargetHandleList l_nvdimmTargetList; + l_nvdimmTargetList.push_back(i_nvdimm); + nvdimm_encrypt_unlock(l_nvdimmTargetList); + + TRACUCOMP(g_trac_nvdimm, EXIT_MRK"nvdimmResetController() HUID[%X]",get_huid(i_nvdimm)); return l_err; } @@ -436,8 +681,8 @@ errlHndl_t nvdimmPollStatus ( Target *i_nvdimm, bool l_done = false; // Get the timeout value for ops_id - assert(i_nvdimm->tryGetAttr<TARGETING::ATTR_NV_OPS_TIMEOUT_MSEC>(l_target_timeout_values), - "nvdimmPollStatus() HUID[%X], failed reading ATTR_NV_OPS_TIMEOUT_MSEC!", TARGETING::get_huid(i_nvdimm)); + assert(i_nvdimm->tryGetAttr<ATTR_NV_OPS_TIMEOUT_MSEC>(l_target_timeout_values), + "nvdimmPollStatus() HUID[%X], failed reading ATTR_NV_OPS_TIMEOUT_MSEC!", get_huid(i_nvdimm)); uint32_t l_timeout = l_target_timeout_values[i_ops_id]; do @@ -461,13 +706,13 @@ errlHndl_t nvdimmPollStatus ( Target *i_nvdimm, o_poll += OPS_POLL_TIME_MS; - } while (o_poll < l_timeout); + } while (o_poll <= l_timeout); if (!l_done && !l_err) { TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmPollStatus() nvdimm[%X] - Status timed out ops_id[%d]", - TARGETING::get_huid(i_nvdimm), i_ops_id); + get_huid(i_nvdimm), i_ops_id); /*@ *@errortype *@reasoncode NVDIMM_STATUS_TIMEOUT @@ -481,20 +726,17 @@ errlHndl_t nvdimmPollStatus ( Target *i_nvdimm, * Refer to userdata1 for which operation it timed out. *@custdesc NVDIMM timed out */ - l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, - NVDIMM_POLL_STATUS, - NVDIMM_STATUS_TIMEOUT, - NVDIMM_SET_USER_DATA_1(i_ops_id, TARGETING::get_huid(i_nvdimm)), - NVDIMM_SET_USER_DATA_2_TIMEOUT(o_poll, l_timeout), - ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); - - l_err->collectTrace(NVDIMM_COMP_NAME, 1024 ); - - // May have to move the error handling to the caller - // as different op could have different error severity - l_err->addPartCallout( i_nvdimm, - HWAS::NV_CONTROLLER_PART_TYPE, - HWAS::SRCI_PRIORITY_HIGH); + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_POLL_STATUS, + NVDIMM_STATUS_TIMEOUT, + NVDIMM_SET_USER_DATA_1(i_ops_id, get_huid(i_nvdimm)), + NVDIMM_SET_USER_DATA_2_TIMEOUT(o_poll, l_timeout), + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + + l_err->collectTrace(NVDIMM_COMP_NAME); + nvdimmAddPage4Regs(i_nvdimm,l_err); + nvdimmAddVendorLog(i_nvdimm, l_err); } return l_err; @@ -516,14 +758,46 @@ errlHndl_t nvdimmPollBackupDone(Target* i_nvdimm, uint32_t &o_poll) { TRACUCOMP(g_trac_nvdimm, ENTER_MRK"nvdimmPollBackupDone() nvdimm[%X]", - TARGETING::get_huid(i_nvdimm)); + get_huid(i_nvdimm)); errlHndl_t l_err = nullptr; + nvdimm_reg_t l_RegInfo = nvdimm_reg_t(); l_err = nvdimmPollStatus ( i_nvdimm, SAVE, o_poll); + if (l_err) + { + errlCommit(l_err, NVDIMM_COMP_ID); + + /*@ + *@errortype + *@reasoncode NVDIMM_BACKUP_TIMEOUT + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_POLL_BACKUP + *@userdata1[0:31] Related ops (0xff = NA) + *@userdata1[32:63] Target Huid + *@devdesc Encountered timeout while performing NVDIMM Restore operation + *@custdesc NVDIMM timed out + */ + l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_POLL_BACKUP, + NVDIMM_BACKUP_TIMEOUT, + NVDIMM_SET_USER_DATA_1(SAVE, TARGETING::get_huid(i_nvdimm)), + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + + l_err->collectTrace( NVDIMM_COMP_NAME ); + nvdimmAddVendorLog(i_nvdimm, l_err); + + // Collect register data for FFDC Traces + nvdimmTraceRegs ( i_nvdimm, l_RegInfo ); + nvdimmAddPage4Regs(i_nvdimm,l_err); + + // Add reg traces to the error log + NVDIMM::UdNvdimmOPParms( l_RegInfo ).addToLog(l_err); + } + TRACUCOMP(g_trac_nvdimm, EXIT_MRK"nvdimmPollBackupDone() nvdimm[%X]", - TARGETING::get_huid(i_nvdimm)); + get_huid(i_nvdimm)); return l_err; } @@ -543,18 +817,57 @@ errlHndl_t nvdimmPollRestoreDone(Target* i_nvdimm, uint32_t &o_poll) { TRACUCOMP(g_trac_nvdimm, ENTER_MRK"nvdimmPollRestoreDone() nvdimm[%X]", - TARGETING::get_huid(i_nvdimm)); + get_huid(i_nvdimm)); errlHndl_t l_err = nullptr; + nvdimm_reg_t l_RegInfo = nvdimm_reg_t(); l_err = nvdimmPollStatus ( i_nvdimm, RESTORE, o_poll ); + if (l_err) + { + errlCommit(l_err, NVDIMM_COMP_ID); + + /*@ + *@errortype + *@reasoncode NVDIMM_RESTORE_TIMEOUT + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_POLL_RESTORE + *@userdata1[0:31] Related ops (0xff = NA) + *@userdata1[32:63] Target Huid + *@devdesc Encountered timeout while performing NVDIMM Restore operation + *@custdesc NVDIMM timed out + */ + l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_POLL_RESTORE, + NVDIMM_RESTORE_TIMEOUT, + NVDIMM_SET_USER_DATA_1(RESTORE, TARGETING::get_huid(i_nvdimm)), + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + + l_err->collectTrace( NVDIMM_COMP_NAME ); + + // May have to move the error handling to the caller + // as different op could have different error severity + l_err->addPartCallout( i_nvdimm, + HWAS::NV_CONTROLLER_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + + // Collect register data for FFDC Traces + nvdimmTraceRegs ( i_nvdimm, l_RegInfo ); + nvdimmAddPage4Regs(i_nvdimm,l_err); + nvdimmAddVendorLog(i_nvdimm, l_err); + + // Add reg traces to the error log + NVDIMM::UdNvdimmOPParms( l_RegInfo ).addToLog(l_err); + } + TRACUCOMP(g_trac_nvdimm, EXIT_MRK"nvdimmPollRestoreDone() nvdimm[%X]", - TARGETING::get_huid(i_nvdimm)); + get_huid(i_nvdimm)); return l_err; } + /** * @brief This function polls the command status register for erase * completion (does not indicate success or fail) @@ -570,14 +883,39 @@ errlHndl_t nvdimmPollEraseDone(Target* i_nvdimm, uint32_t &o_poll) { TRACUCOMP(g_trac_nvdimm, ENTER_MRK"nvdimmPollEraseDone() nvdimm[%X]", - TARGETING::get_huid(i_nvdimm)); + get_huid(i_nvdimm)); errlHndl_t l_err = nullptr; - l_err = nvdimmPollStatus ( i_nvdimm, ERASE, o_poll); + l_err = nvdimmPollStatus( i_nvdimm, ERASE, o_poll); + + if (l_err) + { + errlCommit(l_err, NVDIMM_COMP_ID); + + /*@ + *@errortype + *@reasoncode NVDIMM_ERASE_TIMEOUT + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_POLL_ERASE + *@userdata1[0:31] Related ops (0xff = NA) + *@userdata1[32:63] Target Huid + *@devdesc Encountered timeout while performing NVDIMM Restore operation + *@custdesc NVDIMM timed out + */ + l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_POLL_ERASE, + NVDIMM_ERASE_TIMEOUT, + NVDIMM_SET_USER_DATA_1(ERASE, TARGETING::get_huid(i_nvdimm)), + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + + l_err->collectTrace( NVDIMM_COMP_NAME ); + nvdimmAddPage4Regs(i_nvdimm,l_err); + nvdimmAddVendorLog(i_nvdimm, l_err); + } TRACUCOMP(g_trac_nvdimm, EXIT_MRK"nvdimmPollEraseDone() nvdimm[%X]", - TARGETING::get_huid(i_nvdimm)); + get_huid(i_nvdimm)); return l_err; } @@ -598,14 +936,18 @@ errlHndl_t nvdimmPollESChargeStatus(Target* i_nvdimm, uint32_t &o_poll) { TRACUCOMP(g_trac_nvdimm, ENTER_MRK"nvdimmPollESChargeDone() nvdimm[%X]", - TARGETING::get_huid(i_nvdimm)); + get_huid(i_nvdimm)); errlHndl_t l_err = nullptr; - l_err = nvdimmPollStatus ( i_nvdimm, CHARGE, o_poll ); + l_err = nvdimmPollStatus( i_nvdimm, CHARGE, o_poll ); + + l_err->addPartCallout( i_nvdimm, + HWAS::NV_CONTROLLER_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); TRACUCOMP(g_trac_nvdimm, EXIT_MRK"nvdimmPollESChargeDone() nvdimm[%X]", - TARGETING::get_huid(i_nvdimm)); + get_huid(i_nvdimm)); return l_err; } @@ -623,7 +965,7 @@ errlHndl_t nvdimmPollESChargeStatus(Target* i_nvdimm, errlHndl_t nvdimmGetRestoreValid(Target* i_nvdimm, uint8_t & o_rstrValid) { TRACUCOMP(g_trac_nvdimm, ENTER_MRK"nvdimmGetRestoreValid() nvdimm[%X]", - TARGETING::get_huid(i_nvdimm)); + get_huid(i_nvdimm)); errlHndl_t l_err = nullptr; @@ -631,11 +973,11 @@ errlHndl_t nvdimmGetRestoreValid(Target* i_nvdimm, uint8_t & o_rstrValid) if (l_err){ TRACFCOMP(g_trac_nvdimm, ERR_MRK"NDVIMM HUID[%X], Error getting restore status!", - TARGETING::get_huid(i_nvdimm)); + get_huid(i_nvdimm)); } TRACUCOMP(g_trac_nvdimm, EXIT_MRK"nvdimmGetRestoreValid() nvdimm[%X], restore_status[%x],", - TARGETING::get_huid(i_nvdimm), o_rstrValid); + get_huid(i_nvdimm), o_rstrValid); return l_err; } @@ -651,10 +993,11 @@ errlHndl_t nvdimmGetRestoreValid(Target* i_nvdimm, uint8_t & o_rstrValid) errlHndl_t nvdimmSetESPolicy(Target* i_nvdimm) { TRACUCOMP(g_trac_nvdimm, ENTER_MRK"nvdimmSetESPolicy() nvdimm[%X]", - TARGETING::get_huid(i_nvdimm)); + get_huid(i_nvdimm)); errlHndl_t l_err = nullptr; - uint8_t l_data; + uint8_t l_data = 0x0; + nvdimm_reg_t l_RegInfo = nvdimm_reg_t(); do { @@ -663,9 +1006,9 @@ errlHndl_t nvdimmSetESPolicy(Target* i_nvdimm) if (l_err) { - nvdimmSetStatusFlag(i_nvdimm, NSTD_ERR_NOBKUP); + nvdimmSetStatusFlag(i_nvdimm, NSTD_VAL_DISARMED); TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmSetESPolicy() nvdimm[%X]" - "failed to write ES register!",TARGETING::get_huid(i_nvdimm)); + "failed to write ES register!",get_huid(i_nvdimm)); break; } @@ -677,16 +1020,16 @@ errlHndl_t nvdimmSetESPolicy(Target* i_nvdimm) if (l_err) { - nvdimmSetStatusFlag(i_nvdimm, NSTD_ERR_NOBKUP); + nvdimmSetStatusFlag(i_nvdimm, NSTD_VAL_DISARMED); TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmSetESPolicy() nvdimm[%X]" - "failed to read ES register!",TARGETING::get_huid(i_nvdimm)); + "failed to read ES register!",get_huid(i_nvdimm)); break; } - if ((l_data & ES_SUCCESS) != ES_SUCCESS) + if (((l_data & ES_SUCCESS) != ES_SUCCESS) || ((l_data & ES_POLICY_ERROR) == ES_POLICY_ERROR)) { TRACFCOMP(g_trac_nvdimm, EXIT_MRK"NDVIMM HUID[%X], nvdimmSetESPolicy() " - "failed!",TARGETING::get_huid(i_nvdimm)); + "failed!",get_huid(i_nvdimm)); /*@ *@errortype *@reasoncode NVDIMM_SET_ES_ERROR @@ -700,28 +1043,28 @@ errlHndl_t nvdimmSetESPolicy(Target* i_nvdimm) * NVDIMM is intact *@custdesc NVDIMM encountered error setting the energy source policy */ - l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, - NVDIMM_SET_ES, - NVDIMM_SET_ES_ERROR, - NVDIMM_SET_USER_DATA_1(CHARGE, TARGETING::get_huid(i_nvdimm)), - 0x0, - ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); - - l_err->collectTrace(NVDIMM_COMP_NAME, 1024 ); - - // Failure setting the energy source policy could mean error on the - // battery or even the cabling - l_err->addPartCallout( i_nvdimm, - HWAS::BPM_PART_TYPE, - HWAS::SRCI_PRIORITY_HIGH); - l_err->addPartCallout( i_nvdimm, - HWAS::BPM_CABLE_PART_TYPE, - HWAS::SRCI_PRIORITY_HIGH); + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_SET_ES, + NVDIMM_SET_ES_ERROR, + NVDIMM_SET_USER_DATA_1(CHARGE, get_huid(i_nvdimm)), + 0x0, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + + l_err->collectTrace(NVDIMM_COMP_NAME); + + // Read relevant regs for trace data + nvdimmTraceRegs(i_nvdimm, l_RegInfo); + nvdimmAddPage4Regs(i_nvdimm,l_err); + nvdimmAddVendorLog(i_nvdimm, l_err); + + // Add reg traces to the error log + NVDIMM::UdNvdimmOPParms( l_RegInfo ).addToLog(l_err); } }while(0); TRACUCOMP(g_trac_nvdimm, EXIT_MRK"NDVIMM HUID[%X], nvdimmSetESPolicy()," - ,TARGETING::get_huid(i_nvdimm)); + ,get_huid(i_nvdimm)); return l_err; } @@ -739,7 +1082,7 @@ errlHndl_t nvdimmSetESPolicy(Target* i_nvdimm) errlHndl_t nvdimmChangeArmState(Target *i_nvdimm, bool i_state) { TRACUCOMP(g_trac_nvdimm, ENTER_MRK"nvdimmChangeArmState() nvdimm[%X]", - TARGETING::get_huid(i_nvdimm)); + get_huid(i_nvdimm)); errlHndl_t l_err = nullptr; @@ -753,11 +1096,11 @@ errlHndl_t nvdimmChangeArmState(Target *i_nvdimm, bool i_state) if (l_err) { TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmChangeArmState() nvdimm[%X] error %s nvdimm!!", - TARGETING::get_huid(i_nvdimm), i_state? "arming" : "disarming"); + get_huid(i_nvdimm), i_state? "arming" : "disarming"); } TRACUCOMP(g_trac_nvdimm, EXIT_MRK"nvdimmChangeArmState() nvdimm[%X]", - TARGETING::get_huid(i_nvdimm)); + get_huid(i_nvdimm)); return l_err; } @@ -774,7 +1117,7 @@ errlHndl_t nvdimmChangeArmState(Target *i_nvdimm, bool i_state) errlHndl_t nvdimmValidImage(Target *i_nvdimm, bool &o_imgValid) { TRACUCOMP(g_trac_nvdimm, ENTER_MRK"nvdimmValidImage(): nvdimm[%X]", - TARGETING::get_huid(i_nvdimm)); + get_huid(i_nvdimm)); errlHndl_t l_err = nullptr; uint8_t l_data = 0x0; @@ -785,7 +1128,7 @@ errlHndl_t nvdimmValidImage(Target *i_nvdimm, bool &o_imgValid) if (l_err) { TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmValidImage() nvdimm[%X]" - "failed to for image!",TARGETING::get_huid(i_nvdimm) ); + "failed to for image!",get_huid(i_nvdimm) ); } else if(l_data & VALID_IMAGE) { @@ -793,55 +1136,70 @@ errlHndl_t nvdimmValidImage(Target *i_nvdimm, bool &o_imgValid) } TRACUCOMP(g_trac_nvdimm, EXIT_MRK"nvdimmValidImage(): nvdimm[%X] ret[%X]", - TARGETING::get_huid(i_nvdimm), l_data); + get_huid(i_nvdimm), l_data); return l_err; } +void maskMbacalfir_eventn(TARGETING::Target* i_nvdimm) +{ + errlHndl_t l_err = nullptr; + TargetHandleList l_mcaList; + uint64_t l_writeData; + uint32_t l_writeAddress; + size_t l_writeSize = sizeof(l_writeData); + + getParentAffinityTargets(l_mcaList, i_nvdimm, CLASS_UNIT, TYPE_MCA); + assert(l_mcaList.size(), "maskMbacalfir_eventn() failed to find parent MCA."); + + l_writeAddress = MBACALFIR_OR_MASK_REG; + l_writeData = MBACALFIR_EVENTN_OR_BIT; + l_err = deviceWrite(l_mcaList[0], &l_writeData, l_writeSize, + DEVICE_SCOM_ADDRESS(l_writeAddress)); + if(l_err) + { + TRACFCOMP(g_trac_nvdimm, + ERR_MRK "Failed to mask MBACALFIR EventN using address " + "0x%08x on NVDIMM 0x%08X MCA 0x%08X", + l_writeAddress, get_huid(i_nvdimm), get_huid(l_mcaList[0])); + l_err->collectTrace(NVDIMM_COMP_NAME); + errlCommit( l_err, NVDIMM_COMP_ID ); + } +} + #ifndef __HOSTBOOT_RUNTIME /** * @brief This function handles all the restore related operations. * SRE -> restore -> SRX/RCD/MRS * - * @param[in] i_nvdimmList - list of nvdimms + * @param[in,out] io_nvdimmList - list of nvdimms. Each nvdimm is removed + * from the list after a successful restore. Leftover nvdimm + * is returned to the caller for error handling. * * @param[in] i_mpipl - MPIPL mode * * @return errlHndl_t - Null if successful, otherwise a pointer to * the error log. */ -errlHndl_t nvdimmRestore(TargetHandleList i_nvdimmList, uint8_t &i_mpipl) +errlHndl_t nvdimmRestore(TargetHandleList& io_nvdimmList, uint8_t &i_mpipl) { errlHndl_t l_err = nullptr; - bool l_imgValid; uint8_t l_rstrValid; uint32_t l_poll = 0; + TargetHandleList l_nvdimmList = io_nvdimmList; do { // Put NVDIMM into self-refresh - for (TargetHandleList::iterator it = i_nvdimmList.begin(); - it != i_nvdimmList.end();) + for (TargetHandleList::iterator it = io_nvdimmList.begin(); + it != io_nvdimmList.end();) { - l_err = nvdimmValidImage(*it, l_imgValid); - // No reason to run if we can't figure out - // if there is an image or not - if (l_err) - { - nvdimmSetStatusFlag(*it, NSTD_ERR_NOPRSV); - break; - } + // Default state during boot is unarmed, therefore not preserved + nvdimmSetStatusFlag(*it, NSTD_VAL_DISARMED); - if (!l_imgValid) - { - nvdimmSetStatusFlag(*it, NSTD_VAL_NOPRSV); - i_nvdimmList.erase(it); - continue; - } - - TARGETING::TargetHandleList l_mcaList; - getParentAffinityTargets(l_mcaList, *it, TARGETING::CLASS_UNIT, TARGETING::TYPE_MCA); + TargetHandleList l_mcaList; + getParentAffinityTargets(l_mcaList, *it, CLASS_UNIT, TYPE_MCA); assert(l_mcaList.size(), "nvdimmRestore() failed to find parent MCA."); fapi2::Target<fapi2::TARGET_TYPE_MCA> l_fapi_mca(l_mcaList[0]); @@ -850,21 +1208,40 @@ errlHndl_t nvdimmRestore(TargetHandleList i_nvdimmList, uint8_t &i_mpipl) // is de-asserted before kicking off the restore if (i_mpipl) { + TRACFCOMP(g_trac_nvdimm, "nvdimmRestore(): in MPIPL"); + + // To avoid PRD error during mpipl need to Mask MBACALFIR EventN + // Note: a regular IPL will already have this masked + maskMbacalfir_eventn(*it); + + // Call init for error checking skipped in the SAVE step + nvdimm_init(*it); + FAPI_INVOKE_HWP(l_err, mss::ddr_resetn, l_fapi_mca, HIGH); if (l_err) { TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmRestore() HUID[%X] i_mpipl[%u] failed to de-assert resetn!", - TARGETING::get_huid(*it), i_mpipl); - - nvdimmSetStatusFlag(*it, NSTD_ERR_NOPRSV); - //@TODO RTC 199645 - add HW callout on dimm target - // If we failed to de-assert reset_n, the dimm is pretty much useless. - // Let's not restore if that happens - // The callout will be added inside the HWP - // Leaving this comment here as a reminder, will remove later + get_huid(*it), i_mpipl); break; } + + // In MPIPL, invalidate the BAR to prevent any traffic from stepping on + // the restore + FAPI_INVOKE_HWP(l_err, mss::nvdimm::change_bar_valid_state, l_fapi_mca, LOW); + + // This should not fail at all (scom read/write). If it does, post an informational log + // to leave some breadcrumbs + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmRestore() HUID[%X] i_mpipl[%u] failed to invalidate BAR!", + get_huid(*it), i_mpipl); + + l_err->setSev(ERRORLOG::ERRL_SEV_INFORMATIONAL); + l_err->collectTrace( NVDIMM_COMP_NAME ); + ERRORLOG::errlCommit(l_err, NVDIMM_COMP_ID); + } + } // Self-refresh is done at the port level @@ -873,13 +1250,7 @@ errlHndl_t nvdimmRestore(TargetHandleList i_nvdimmList, uint8_t &i_mpipl) if (l_err) { TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmRestore() HUID[%X] self_refresh_entry failed!", - TARGETING::get_huid(*it)); - - nvdimmSetStatusFlag(*it, NSTD_ERR_NOPRSV); - //@TODO RTC 199645 - add HW callout on dimm target - // Without SRE the data could be not reliably restored - // The callout will be added inside the HWP - // Leaving this comment here as a reminder, will remove later + get_huid(*it)); break; } it++; @@ -890,21 +1261,14 @@ errlHndl_t nvdimmRestore(TargetHandleList i_nvdimmList, uint8_t &i_mpipl) break; } - // Nothing to do. Move on. - if (i_nvdimmList.empty()) - { - break; - } - // Kick off the restore on each nvdimm in the nvdimm list - for (const auto & l_nvdimm : i_nvdimmList) + for (const auto & l_nvdimm : io_nvdimmList) { l_err = nvdimmWriteReg(l_nvdimm, NVDIMM_FUNC_CMD, RESTORE_IMAGE); if (l_err) { - nvdimmSetStatusFlag(l_nvdimm, NSTD_ERR_NOPRSV); TRACFCOMP(g_trac_nvdimm, ERR_MRK"NDVIMM HUID[%X], error initiating restore!!", - TARGETING::get_huid(l_nvdimm)); + get_huid(l_nvdimm)); break; } } @@ -915,7 +1279,7 @@ errlHndl_t nvdimmRestore(TargetHandleList i_nvdimmList, uint8_t &i_mpipl) } // Make sure the restore completed - for (const auto & l_nvdimm : i_nvdimmList) + for (const auto & l_nvdimm : io_nvdimmList) { // Since we kicked off the restore on all the modules at once, the restore // should complete on all of the modules in one restore window. Use the @@ -923,10 +1287,8 @@ errlHndl_t nvdimmRestore(TargetHandleList i_nvdimmList, uint8_t &i_mpipl) l_err = nvdimmPollRestoreDone(l_nvdimm, l_poll); if (l_err) { - nvdimmSetStatusFlag(l_nvdimm, NSTD_ERR_NOPRSV); TRACFCOMP(g_trac_nvdimm, ERR_MRK"NDVIMM HUID[%X], error restoring!", - TARGETING::get_huid(l_nvdimm)); - errlCommit(l_err, NVDIMM_COMP_ID); + get_huid(l_nvdimm)); break; } } @@ -936,22 +1298,23 @@ errlHndl_t nvdimmRestore(TargetHandleList i_nvdimmList, uint8_t &i_mpipl) break; } - // Make sure the restore is valid - for (const auto & l_nvdimm : i_nvdimmList) + // Check for restore errors + for (TargetHandleList::iterator it = io_nvdimmList.begin(); + it != io_nvdimmList.end();) { - l_err = nvdimmGetRestoreValid(l_nvdimm, l_rstrValid); + l_err = nvdimmGetRestoreValid(*it, l_rstrValid); if (l_err) { - nvdimmSetStatusFlag(l_nvdimm, NSTD_ERR_NOPRSV); TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmRestore Target[%X] error validating restore status!", - TARGETING::get_huid(l_nvdimm)); + get_huid(*it)); break; } - if ((l_rstrValid & RSTR_SUCCESS) != RSTR_SUCCESS){ + if ((l_rstrValid & RSTR_ERROR) == RSTR_ERROR) + { - TRACFCOMP(g_trac_nvdimm, ERR_MRK"NDVIMM HUID[%X] restoreValid[%d], restore failed!", - TARGETING::get_huid(l_nvdimm), l_rstrValid); + TRACFCOMP(g_trac_nvdimm, ERR_MRK"NDVIMM HUID[%X] restore failed due to errors", + get_huid(*it)); /*@ *@errortype *@reasoncode NVDIMM_RESTORE_FAILED @@ -964,36 +1327,21 @@ errlHndl_t nvdimmRestore(TargetHandleList i_nvdimmList, uint8_t &i_mpipl) * restore timeout (Controller error) *@custdesc NVDIMM failed to restore data */ - l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_UNRECOVERABLE, - NVDIMM_RESTORE, - NVDIMM_RESTORE_FAILED, - TARGETING::get_huid(l_nvdimm), - 0x0, - ERRORLOG::ErrlEntry::NO_SW_CALLOUT); - - l_err->collectTrace(NVDIMM_COMP_NAME, 1024 ); - nvdimmSetStatusFlag(l_nvdimm, NSTD_ERR_NOPRSV); - - // Invalid restore could be due to dram not in self-refresh - // or controller issue. Data should not be trusted at this point - l_err->addPartCallout( l_nvdimm, - HWAS::NV_CONTROLLER_PART_TYPE, - HWAS::SRCI_PRIORITY_HIGH); + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + NVDIMM_RESTORE, + NVDIMM_RESTORE_FAILED, + get_huid(*it), + 0x0, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT); + nvdimmAddPage4Regs(*it,l_err); + nvdimmAddVendorLog(*it, l_err); break; } - } - - if (l_err) - { - break; - } - // Exit self-refresh - for (const auto & l_nvdimm : i_nvdimmList) - { - - TARGETING::TargetHandleList l_mcaList; - getParentAffinityTargets(l_mcaList, l_nvdimm, TARGETING::CLASS_UNIT, TARGETING::TYPE_MCA); + // Exit self-refresh + TargetHandleList l_mcaList; + getParentAffinityTargets(l_mcaList, *it, CLASS_UNIT, TYPE_MCA); assert(l_mcaList.size(), "nvdimmRestore() failed to find parent MCA."); fapi2::Target<fapi2::TARGET_TYPE_MCA> l_fapi_mca(l_mcaList[0]); @@ -1005,16 +1353,48 @@ errlHndl_t nvdimmRestore(TargetHandleList i_nvdimmList, uint8_t &i_mpipl) if (l_err) { TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmRestore() HUID[%X] post_restore_transition failed!", - TARGETING::get_huid(l_nvdimm)); - - // Commit the error from the HWP - nvdimmSetStatusFlag(l_nvdimm, NSTD_ERR_NOPRSV); + get_huid(*it)); + nvdimmAddPage4Regs(*it,l_err); break; } else { // Restore success! - nvdimmSetStatusFlag(l_nvdimm, NSTD_VAL_PRSV); + // Remove dimm from list for error handling + it = io_nvdimmList.erase(it); + } + } + + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, "nvdimmRestore() HUID[%X] encounrterd an error during restore"); + break; + } + + if (i_mpipl) + { + for (const auto & l_nvdimm : l_nvdimmList) + { + TargetHandleList l_mcaList; + errlHndl_t err = nullptr; + getParentAffinityTargets(l_mcaList, l_nvdimm, CLASS_UNIT, TYPE_MCA); + assert(l_mcaList.size(), "nvdimmRestore() failed to find parent MCA."); + + // Re-validate the BAR after restore + fapi2::Target<fapi2::TARGET_TYPE_MCA> l_fapi_mca(l_mcaList[0]); + FAPI_INVOKE_HWP(err, mss::nvdimm::change_bar_valid_state, l_fapi_mca, HIGH); + + // This should not fail at all (scom read/write). If it does, post an informational log + // to leave some breadcrumbs + if (err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmRestore() HUID[%X] i_mpipl[%u] failed to invalidate BAR!", + get_huid(l_nvdimm), i_mpipl); + + err->setSev(ERRORLOG::ERRL_SEV_INFORMATIONAL); + err->collectTrace( NVDIMM_COMP_NAME ); + ERRORLOG::errlCommit(err, NVDIMM_COMP_ID); + } } } @@ -1027,66 +1407,124 @@ errlHndl_t nvdimmRestore(TargetHandleList i_nvdimmList, uint8_t &i_mpipl) #endif /** - * @brief This function checks the erase status register to make sure - * the last erase completed witout error + * @brief This function checks the status and success of an erase * * @param[in] i_nvdimm - nvdimm target with NV controller + * @param[in] i_statusOnly - check just the status register (not the image) * * @return errlHndl_t - Null if successful, otherwise a pointer to * the error log. */ -errlHndl_t nvdimmCheckEraseSuccess(Target *i_nvdimm) +errlHndl_t nvdimmEraseCheck(Target *i_nvdimm, bool i_statusOnly) { - TRACUCOMP(g_trac_nvdimm, ENTER_MRK"nvdimmCheckEraseSuccess() : nvdimm[%X]", - TARGETING::get_huid(i_nvdimm)); - - uint8_t l_data = 0; errlHndl_t l_err = nullptr; + nvdimm_reg_t l_RegInfo; + uint8_t l_data = 0; + bool l_valid = false; - l_err = nvdimmReadReg(i_nvdimm, ERASE_STATUS, l_data); + // Erase happens one module at a time. No need to set any offset on the counter + uint32_t l_poll = 0; + l_err = nvdimmPollEraseDone(i_nvdimm, l_poll); + // Add part callout, currently all erase calls have same callout + // Dump traces to the error log if error exists if (l_err) { - TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmCheckEraseSuccess() nvdimm[%X]" - "failed to read erase status reg!",TARGETING::get_huid(i_nvdimm)); + // For both Erase timeout and Erase fail + // Callout nvdimm on high, gard and deconfig + l_err->addHwCallout( i_nvdimm, + HWAS::SRCI_PRIORITY_HIGH, + HWAS::DECONFIG, + HWAS::GARD_Fatal); + + // Collect register data for FFDC Traces + nvdimmTraceRegs ( i_nvdimm, l_RegInfo ); + nvdimmAddPage4Regs(i_nvdimm,l_err); + + // Add reg traces to the error log + NVDIMM::UdNvdimmOPParms( l_RegInfo ).addToLog(l_err); } - else if ((l_data & ERASE_SUCCESS) != ERASE_SUCCESS) + else { + do + { + // Read Erase Status register + l_err = nvdimmReadReg ( i_nvdimm, ERASE_STATUS, l_data); + if (l_err) + { + nvdimmSetStatusFlag(i_nvdimm, NSTD_VAL_DISARMED); + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm[%X], failed to read erase status", + get_huid(i_nvdimm)); + break; + } - TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmCheckEraseSuccess() nvdimm[%X]" - "failed to erase!",TARGETING::get_huid(i_nvdimm)); - /*@ - *@errortype - *@reasoncode NVDIMM_ERASE_FAILED - *@severity ERRORLOG_SEV_PREDICTIVE - *@moduleid NVDIMM_CHECK_ERASE - *@userdata1[0:31] Related ops (0xff = NA) - *@userdata1[32:63] Target Huid - *@userdata2 <UNUSED> - *@devdesc Encountered error erasing previously stored data image - * on NVDIMM. Likely due to timeout and/or controller error - *@custdesc NVDIMM error erasing data image - */ - l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, - NVDIMM_CHECK_ERASE, - NVDIMM_ERASE_FAILED, - NVDIMM_SET_USER_DATA_1(ERASE, TARGETING::get_huid(i_nvdimm)), - 0x0, - ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + if (i_statusOnly) + { + // assume image is cleared, do not check + TRACFCOMP(g_trac_nvdimm, "nvdimmEraseCheck() - skipping image check for nvdimm[%X]", + get_huid(i_nvdimm)); + l_valid = false; + } + else + { + // Check for a valid image + l_err = nvdimmValidImage( i_nvdimm, l_valid ); + if (l_err) + { + nvdimmSetStatusFlag(i_nvdimm, NSTD_VAL_DISARMED); + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm[%X] Failed to detect valid image", + get_huid(i_nvdimm)); + break; + } + } - l_err->collectTrace(NVDIMM_COMP_NAME, 1024 ); - errlCommit( l_err, NVDIMM_COMP_ID ); + if ( (l_data & ERASE_ERROR) || l_valid ) + { + nvdimmSetStatusFlag(i_nvdimm, NSTD_VAL_DISARMED); + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm[%X] NVDimm Erase failed due to error (ERASE_STATUS: 0x%02X, Image %s)", + get_huid(i_nvdimm), l_data, l_valid?"not erased":"erased"); + /*@ + *@errortype + *@reasoncode NVDIMM_ERASE_ERROR + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_CHECK_ERASE + *@userdata1[0:31] ERASE_STATUS register + *@userdata1[32:63] Target Huid + *@userdata2 ERASE_ERROR status bit + *@userdata2 Image validity + *@devdesc Encountered error during image erase function + * on NVDIMM. Check error register trace for details + *@custdesc NVDIMM error during nvdimm erase + */ + l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_CHECK_ERASE, + NVDIMM_ERASE_ERROR, + NVDIMM_SET_USER_DATA_1(l_data, get_huid(i_nvdimm)), + NVDIMM_SET_USER_DATA_1(ERASE_ERROR, l_valid), + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + + l_err->collectTrace( NVDIMM_COMP_NAME ); + break; + } - // Failure to erase could mean internal NV controller error and/or - // HW error on nand flash. NVDIMM will lose persistency if failed to - // erase nand flash - l_err->addPartCallout( i_nvdimm, - HWAS::NV_CONTROLLER_PART_TYPE, - HWAS::SRCI_PRIORITY_HIGH); - } + } while(0); - TRACUCOMP(g_trac_nvdimm, EXIT_MRK"nvdimmCheckEraseSuccess(): nvdimm[%X] ret[%X]", - TARGETING::get_huid(i_nvdimm), l_data); + if(l_err) + { + // Callout nvdimm on high, gard and deconfig + l_err->addHwCallout( i_nvdimm, + HWAS::SRCI_PRIORITY_HIGH, + HWAS::DECONFIG, + HWAS::GARD_Fatal); + + // Collect register data for FFDC Traces + nvdimmTraceRegs ( i_nvdimm, l_RegInfo ); + nvdimmAddPage4Regs(i_nvdimm,l_err); + + // Add reg traces to the error log + NVDIMM::UdNvdimmOPParms( l_RegInfo ).addToLog(l_err); + } + } return l_err; } @@ -1102,7 +1540,7 @@ errlHndl_t nvdimmCheckEraseSuccess(Target *i_nvdimm) errlHndl_t nvdimmEraseNF(Target *i_nvdimm) { TRACUCOMP(g_trac_nvdimm, ENTER_MRK"nvdimmEraseNF() nvdimm[%X]", - TARGETING::get_huid(i_nvdimm)); + get_huid(i_nvdimm)); errlHndl_t l_err = nullptr; @@ -1112,22 +1550,17 @@ errlHndl_t nvdimmEraseNF(Target *i_nvdimm) if (l_err) { TRACFCOMP(g_trac_nvdimm, ERR_MRK"NDVIMM HUID[%X] error initiating erase!!", - TARGETING::get_huid(i_nvdimm)); + get_huid(i_nvdimm)); break; } - // Erase happens one module at a time. No need to set any offset on the counter - uint32_t l_poll = 0; - l_err = nvdimmPollEraseDone(i_nvdimm, l_poll); - if (!l_err) - { - l_err = nvdimmCheckEraseSuccess(i_nvdimm); - } + // Poll for success, then check the status and image + l_err = nvdimmEraseCheck(i_nvdimm, false); }while(0); TRACUCOMP(g_trac_nvdimm, EXIT_MRK"nvdimmEraseNF() nvdimm[%X]", - TARGETING::get_huid(i_nvdimm)); + get_huid(i_nvdimm)); return l_err; } @@ -1146,15 +1579,15 @@ errlHndl_t nvdimmEraseNF(Target *i_nvdimm) errlHndl_t nvdimmOpenPage(Target *i_nvdimm, uint8_t i_page) { - TRACUCOMP(g_trac_nvdimm, ENTER_MRK"nvdimmOpenPage nvdimm[%X]", TARGETING::get_huid(i_nvdimm)); + TRACUCOMP(g_trac_nvdimm, ENTER_MRK"nvdimmOpenPage nvdimm[%X]", get_huid(i_nvdimm)); errlHndl_t l_err = nullptr; bool l_success = false; uint8_t l_data; uint32_t l_poll = 0; uint32_t l_target_timeout_values[6]; - assert(i_nvdimm->tryGetAttr<TARGETING::ATTR_NV_OPS_TIMEOUT_MSEC>(l_target_timeout_values), - "nvdimmOpenPage() HUID[%X], failed reading ATTR_NV_OPS_TIMEOUT_MSEC!", TARGETING::get_huid(i_nvdimm)); + assert(i_nvdimm->tryGetAttr<ATTR_NV_OPS_TIMEOUT_MSEC>(l_target_timeout_values), + "nvdimmOpenPage() HUID[%X], failed reading ATTR_NV_OPS_TIMEOUT_MSEC!", get_huid(i_nvdimm)); uint32_t l_timeout = l_target_timeout_values[PAGE_SWITCH]; @@ -1167,7 +1600,7 @@ errlHndl_t nvdimmOpenPage(Target *i_nvdimm, if (l_err) { TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmOpenPage nvdimm[%X]" - "error writing to page change reg", TARGETING::get_huid(i_nvdimm)); + "error writing to page change reg", get_huid(i_nvdimm)); break; } @@ -1200,7 +1633,7 @@ errlHndl_t nvdimmOpenPage(Target *i_nvdimm, if (!l_success && !l_err) { TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmOpenPage nvdimm[%X] openpage_success[%d]," - "failure to open page!", TARGETING::get_huid(i_nvdimm), static_cast<uint8_t>(l_success)); + "failure to open page!", get_huid(i_nvdimm), static_cast<uint8_t>(l_success)); /*@ *@errortype @@ -1215,25 +1648,28 @@ errlHndl_t nvdimmOpenPage(Target *i_nvdimm, *@custdesc Encountered error performing internal operaiton * on NVDIMM */ - l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_UNRECOVERABLE, - NVDIMM_POLL_STATUS, - NVDIMM_STATUS_TIMEOUT, - NVDIMM_SET_USER_DATA_1(PAGE_SWITCH, TARGETING::get_huid(i_nvdimm)), - NVDIMM_SET_USER_DATA_2_TIMEOUT(l_poll, l_timeout), - ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + NVDIMM_OPEN_PAGE, + NVDIMM_OPEN_PAGE_TIMEOUT, + NVDIMM_SET_USER_DATA_1(PAGE_SWITCH, get_huid(i_nvdimm)), + NVDIMM_SET_USER_DATA_2_TIMEOUT(l_poll, l_timeout), + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); l_err->collectTrace(NVDIMM_COMP_NAME, 256 ); + nvdimmAddVendorLog(i_nvdimm, l_err); // Failure to open page most likely means problem with // the NV controller. l_err->addPartCallout( i_nvdimm, HWAS::NV_CONTROLLER_PART_TYPE, HWAS::SRCI_PRIORITY_HIGH); + nvdimmAddPage4Regs(i_nvdimm,l_err); } }while(0); TRACUCOMP(g_trac_nvdimm, EXIT_MRK"nvdimmOpenPage nvdimm[%X] nvdimmOpenPage.success[%d]," - ,TARGETING::get_huid(i_nvdimm), static_cast<uint8_t>(l_success)); + ,get_huid(i_nvdimm), static_cast<uint8_t>(l_success)); return l_err; } @@ -1250,12 +1686,12 @@ errlHndl_t nvdimmOpenPage(Target *i_nvdimm, errlHndl_t nvdimmGetTimeoutVal(Target* i_nvdimm) { TRACUCOMP(g_trac_nvdimm, ENTER_MRK"nvdimmGetTimeoutVal() HUID[%X]" - ,TARGETING::get_huid(i_nvdimm)); + ,get_huid(i_nvdimm)); errlHndl_t l_err = nullptr; uint8_t l_data = 0; uint32_t timeout_map[6]; - i_nvdimm->tryGetAttr<TARGETING::ATTR_NV_OPS_TIMEOUT_MSEC>(timeout_map); + i_nvdimm->tryGetAttr<ATTR_NV_OPS_TIMEOUT_MSEC>(timeout_map); //Get the 6 main timeout values for (uint8_t i = SAVE; i <= CHARGE; i++) @@ -1282,28 +1718,33 @@ errlHndl_t nvdimmGetTimeoutVal(Target* i_nvdimm) if (l_err) { TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmGetTimeoutVal() HUID[%X] " - "error reading timeout value for op[%d]!", TARGETING::get_huid(i_nvdimm), i); + "error reading timeout value for op[%d]!", get_huid(i_nvdimm), i); break; } //Converting to msec depending on bit 15. 1 = sec, 0 = msec //except for charge. Charge is only in seconds so convert anyway + //Double the timeout values for margins if (timeout_map[i] >= 0x8000 || i == CHARGE){ timeout_map[i] = timeout_map[i] & 0x7FFF; - timeout_map[i] = timeout_map[i] * MS_PER_SEC; + timeout_map[i] = timeout_map[i] * MS_PER_SEC * 2; + } + else + { + timeout_map[i] = timeout_map[i] * 2; } TRACUCOMP(g_trac_nvdimm, "nvdimmGetTimeoutVal() HUID[%X], timeout_idx[%d], timeout_ms[%d]" - ,TARGETING::get_huid(i_nvdimm), timeoutInfoTable[i].idx, timeout_map[i]); + ,get_huid(i_nvdimm), timeoutInfoTable[i].idx, timeout_map[i]); } if (!l_err) { - i_nvdimm->setAttr<TARGETING::ATTR_NV_OPS_TIMEOUT_MSEC>(timeout_map); + i_nvdimm->setAttr<ATTR_NV_OPS_TIMEOUT_MSEC>(timeout_map); } TRACUCOMP(g_trac_nvdimm, EXIT_MRK"nvdimmGetTimeoutVal() HUID[%X]" - ,TARGETING::get_huid(i_nvdimm)); + ,get_huid(i_nvdimm)); return l_err; } @@ -1327,8 +1768,8 @@ errlHndl_t nvdimmEpowSetup(TargetHandleList &i_nvdimmList) for (TargetHandleList::iterator it = i_nvdimmList.begin(); it != i_nvdimmList.end();) { - TARGETING::TargetHandleList l_mcaList; - getParentAffinityTargets(l_mcaList, *it, TARGETING::CLASS_UNIT, TARGETING::TYPE_MCA); + TargetHandleList l_mcaList; + getParentAffinityTargets(l_mcaList, *it, CLASS_UNIT, TYPE_MCA); assert(l_mcaList.size(), "nvdimmEpowSetup() failed to find parent MCA."); fapi2::Target<fapi2::TARGET_TYPE_MCA> l_fapi_mca(l_mcaList[0]); @@ -1340,9 +1781,10 @@ errlHndl_t nvdimmEpowSetup(TargetHandleList &i_nvdimmList) if (l_err) { TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmEpowSetup() HUID[%X] failed to setup epow!", - TARGETING::get_huid(*it)); + get_huid(*it)); - nvdimmSetStatusFlag(*it, NSTD_ERR_NOPRSV); + nvdimmSetStatusFlag(*it, NSTD_VAL_SR_FAILED); + nvdimmAddPage4Regs(*it,l_err); break; } it++; @@ -1354,6 +1796,7 @@ errlHndl_t nvdimmEpowSetup(TargetHandleList &i_nvdimmList) return l_err; } + /** * @brief Entry function to NVDIMM restore * - Restore image from NVDIMM NAND flash to DRAM @@ -1365,31 +1808,21 @@ errlHndl_t nvdimmEpowSetup(TargetHandleList &i_nvdimmList) void nvdimm_restore(TargetHandleList &i_nvdimmList) { TRACUCOMP(g_trac_nvdimm, ENTER_MRK"nvdimm_restore()"); + errlHndl_t l_err = nullptr; + bool l_valid = false; + bool l_continue = true; TARGETING::Target* l_sys = nullptr; TARGETING::targetService().getTopLevelTarget( l_sys ); assert(l_sys, "nvdimm_restore: no TopLevelTarget"); uint8_t l_mpipl = l_sys->getAttr<ATTR_IS_MPIPL_HB>(); + nvdimm_reg_t l_RegInfo = nvdimm_reg_t(); + TargetHandleList l_nvdimm_restore_list = i_nvdimmList; + uint8_t l_rstrValid; do { - // Set the energy policy to device-managed - // Don't think this is needed for the supercaps to start charging - // but do it anyway to get the charging going - for (const auto & l_nvdimm : i_nvdimmList) - { - l_err = nvdimmSetESPolicy(l_nvdimm); - if (l_err) - { - // Failing this is an indication of power pack issue. - // This will prevent future backup, but let's continue - // since we can still restore the data if there is any - nvdimmSetStatusFlag(l_nvdimm, NSTD_ERR_NOBKUP); - TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_restore() - Failing nvdimmSetESPolicy()"); - errlCommit( l_err, NVDIMM_COMP_ID ); - } - } - + // Check MPIPL case first to make sure any on-going backup is complete if (l_mpipl) { // During MPIPL, make sure any in-progress save is completed before proceeding @@ -1401,41 +1834,118 @@ void nvdimm_restore(TargetHandleList &i_nvdimmList) if (l_err) { - nvdimmSetStatusFlag(l_nvdimm, NSTD_ERR_NOPRSV); + nvdimmSetStatusFlag(l_nvdimm, NSTD_VAL_ERASED); TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_restore() nvdimm[%X], error backing up the DRAM!", - TARGETING::get_huid(l_nvdimm)); + get_huid(l_nvdimm)); errlCommit(l_err, NVDIMM_COMP_ID); break; } } } + // Compile a list of nvdimms with valid image + // TODO: Reach out to RAS on how to handle odd number of nvdimms + // since we always operate in pairs + for (TargetHandleList::iterator it = l_nvdimm_restore_list.begin(); + it != l_nvdimm_restore_list.end();) + { + // Check for a valid image + l_err = nvdimmValidImage( *it, l_valid ); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_restore() nvdimm[%X] Failed to detect valid image", get_huid(*it)); + errlCommit(l_err, NVDIMM_COMP_ID); + } + + // Remove it from the restore list if there is no valid image + if (!l_valid) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_restore() nvdimm[%X] No valid image discovered", get_huid(*it)); + // Set ATTR NV STATUS FLAG to Erased + nvdimmSetStatusFlag(*it, NSTD_VAL_ERASED); + it = l_nvdimm_restore_list.erase(it); + + } + else + { + it++; + } + } + + // Exit if there is nothing to restore + if (l_nvdimm_restore_list.empty()) + { + break; + } + // Start the restore - l_err = nvdimmRestore(i_nvdimmList, l_mpipl); + l_err = nvdimmRestore(l_nvdimm_restore_list, l_mpipl); + // Check if restore completed successfully if (l_err) { + const auto l_nvdimm = l_nvdimm_restore_list.front(); + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_restore() - Failing nvdimmRestore()"); - errlCommit( l_err, NVDIMM_COMP_ID ); + nvdimmSetStatusFlag(l_nvdimm, NSTD_VAL_SR_FAILED); + + // Invalid restore could be due to dram not in self-refresh + // or controller issue. Data should not be trusted at this point + l_err->addHwCallout( l_nvdimm, + HWAS::SRCI_PRIORITY_HIGH, + HWAS::DECONFIG, + HWAS::GARD_Fatal); + + // Collect register data for FFDC Traces + nvdimmTraceRegs ( l_nvdimm, l_RegInfo ); + nvdimmAddPage4Regs(l_nvdimm,l_err); + + // Add reg traces to the error log + NVDIMM::UdNvdimmOPParms( l_RegInfo ).addToLog(l_err); break; } - // Make sure the energy source is fully charged before erasing the images - // Doing this on all the nvdimms since the ones w/o image will need - // to be fully charged before arming the trigger - uint32_t l_poll = 0; + // Check health status registers and exit if required for (const auto & l_nvdimm : i_nvdimmList) { - l_err = nvdimmPollESChargeStatus(l_nvdimm, l_poll); + // Post restore health check. l_continue gets set per the health check logic + // and used later to determine if boot shall continue on error condition + l_err = nvdimmHealthStatusCheck( l_nvdimm, HEALTH_RESTORE, l_continue ); - if (l_err){ - nvdimmSetStatusFlag(l_nvdimm, NSTD_ERR_NOBKUP); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_restore() nvdimm[%X] failed during health status check", get_huid(l_nvdimm)); errlCommit( l_err, NVDIMM_COMP_ID ); + if (!l_continue) + { + break; + } } + + // Make sure the restore is valid + l_err = nvdimmGetRestoreValid(l_nvdimm, l_rstrValid); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_restore Target[%X] error validating restore status!", + get_huid(l_nvdimm)); + break; + } + + if ((l_rstrValid & RSTR_SUCCESS) == RSTR_SUCCESS) + { + // Restore success! + nvdimmSetStatusFlag(l_nvdimm, NSTD_VAL_RESTORED); + } + } }while(0); + if (l_err) + { + errlCommit(l_err, NVDIMM_COMP_ID); + } + // At the end, pre-load CCS with commands for EPOW. This will stage the CCS // with the require commands to trigger the save on NVDIMMs. The actual // triggering will be done by OCC when EPOW is detected. @@ -1455,6 +1965,7 @@ void nvdimm_restore(TargetHandleList &i_nvdimmList) * - Checks for ready state * - Gathers timeout values * - Waits for the ongoing backup to complete + * - Unlocks encryption * - Disarms the trigger for draminit * * @param[in] i_nvdimm - nvdimm target @@ -1463,66 +1974,3903 @@ void nvdimm_restore(TargetHandleList &i_nvdimmList) void nvdimm_init(Target *i_nvdimm) { TRACUCOMP(g_trac_nvdimm, ENTER_MRK"nvdimm_init() nvdimm[%X]", - TARGETING::get_huid(i_nvdimm)); + get_huid(i_nvdimm)); errlHndl_t l_err = nullptr; + bool l_continue = true; + uint8_t l_data = 0; + uint8_t l_failinfo0 = 0; + uint8_t l_failinfo1 = 0; + nvdimm_reg_t l_RegInfo; + uint32_t l_poll = 0; do { - l_err = nvdimmReady(i_nvdimm); + // Force a factory reset if told to via attribute override + // This will allow us to recover from bad images, lost keys, etc + Target* l_sys = nullptr; + targetService().getTopLevelTarget( l_sys ); + assert(l_sys, "nvdimm_init: no TopLevelTarget"); + if( l_sys->getAttr<ATTR_FORCE_NVDIMM_RESET>() ) + { + l_err = nvdimm_factory_reset(i_nvdimm); + if (l_err) + { + nvdimmSetStatusFlag(i_nvdimm, NSTD_ERR); + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_init() nvdimm[%X], factory reset failed", + get_huid(i_nvdimm)); + errlCommit(l_err, NVDIMM_COMP_ID); + } + } + // Set ATTR_NV_STATUS_FLAG to default disarmed state + l_err = notifyNvdimmProtectionChange(i_nvdimm, NVDIMM_DISARMED); if (l_err) { nvdimmSetStatusFlag(i_nvdimm, NSTD_ERR); - TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_int() nvdimm[%X], controller not ready", - TARGETING::get_huid(i_nvdimm)); errlCommit(l_err, NVDIMM_COMP_ID); + } + + // Check if the nvdimm ready status + l_err = nvdimmReady(i_nvdimm); + + if (l_err) + { + nvdimmSetStatusFlag(i_nvdimm, NSTD_ERR); + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_init() nvdimm[%X], controller not ready", + get_huid(i_nvdimm)); break; } + // Check if the firmware slot is 0 + l_err = nvdimmGetRunningSlot(i_nvdimm, l_data); + if (l_err) + { + nvdimmSetStatusFlag(i_nvdimm, NSTD_ERR); + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_init() nvdimm[%X], failed to read slot info", + get_huid(i_nvdimm)); + break; + } + + if (l_data == 0) + { + nvdimmSetStatusFlag(i_nvdimm, NSTD_ERR_VAL_SR); + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_init() nvdimm[%X], running on fw slot 0", + get_huid(i_nvdimm)); + /*@ + *@errortype + *@reasoncode NVDIMM_INVALID_FW_SLOT + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_CHECK_FW_SLOT + *@userdata1[0:31] Slot running + *@userdata1[32:63] Target Huid + *@userdata2 <UNUSED> + *@devdesc Encountered error when checking the firmware slot running + * on NVDIMM. Firmware is running on slot 0 instead of 1 + *@custdesc NVDIMM incorrect firmware slot + */ + l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_CHECK_FW_SLOT, + NVDIMM_INVALID_FW_SLOT, + NVDIMM_SET_USER_DATA_1(l_data, get_huid(i_nvdimm)), + 0x0, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + + l_err->collectTrace( NVDIMM_COMP_NAME ); + + // Add callout of nvdimm with no deconfig/gard + l_err->addHwCallout( i_nvdimm, + HWAS::SRCI_PRIORITY_LOW, + HWAS::NO_DECONFIG, + HWAS::GARD_NULL); + + errlCommit(l_err, NVDIMM_COMP_ID); + } + // Get the timeout values for the major ops at init l_err = nvdimmGetTimeoutVal(i_nvdimm); if (l_err) { nvdimmSetStatusFlag(i_nvdimm, NSTD_ERR); - TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_int() nvdimm[%X], error retrieving timeout values", - TARGETING::get_huid(i_nvdimm)); - errlCommit(l_err, NVDIMM_COMP_ID); + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_init() nvdimm[%X], error retrieving timeout values", + get_huid(i_nvdimm)); break; } - //Check save progress - uint32_t l_poll = 0; - l_err = nvdimmPollBackupDone(i_nvdimm, l_poll); + // Check for Erase in progress and verify good status + l_err = nvdimmEraseCheck(i_nvdimm, true); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_init() nvdimm[%X], error checking erase status", + get_huid(i_nvdimm)); + break; + } + // Check NO_RESET_N bit for power loss without save + l_err = nvdimmReadReg ( i_nvdimm, CSAVE_FAIL_INFO1, l_data); if (l_err) { - nvdimmSetStatusFlag(i_nvdimm, NSTD_ERR_NOPRSV); - TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_int() nvdimm[%X], error backing up the DRAM!", - TARGETING::get_huid(i_nvdimm)); - errlCommit(l_err, NVDIMM_COMP_ID); break; } + else if ((l_data & NO_RESET_N) == NO_RESET_N) + { + // Set ATTR_NV_STATUS_FLAG to partial working as data may persist + nvdimmSetStatusFlag(i_nvdimm, NSTD_ERR_VAL_SR); + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmInit() nvdimm[%X]" + "failed to save due to power loss!",get_huid(i_nvdimm)); + /*@ + *@errortype + *@reasoncode NVDIMM_POWER_SAVE_FAILURE + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_CHECK_RESETN + *@userdata1[0:31] Related ops (0xff = NA) + *@userdata1[32:63] Target Huid + *@userdata2 <UNUSED> + *@devdesc NO_RESET_N: The NVDIMM experienced a power loss, but no CSAVE + * was triggered since the NVDIMM did not detect an asserted + * RESET_N. If there is a prior predicitve log for OCC in safe + * mode, than this would be the reason for NO_RESET_N. Otherwise + * there could be a problem with the RESET_N signal between proc + * and NVDIMM. + *@custdesc NVDIMM error erasing data image + */ + l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_CHECK_RESETN, + NVDIMM_POWER_SAVE_FAILURE, + NVDIMM_SET_USER_DATA_1(l_data, get_huid(i_nvdimm)), + 0x0, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + + l_err->collectTrace( NVDIMM_COMP_NAME ); + nvdimmAddVendorLog(i_nvdimm, l_err); + + // Failure to erase could mean internal NV controller error and/or + // HW error on nand flash. NVDIMM will lose persistency if failed to + // erase nand flash + l_err->addHwCallout( i_nvdimm, + HWAS::SRCI_PRIORITY_LOW, + HWAS::NO_DECONFIG, + HWAS::GARD_NULL); + + // Collect register data for FFDC Traces + nvdimmTraceRegs ( i_nvdimm, l_RegInfo ); + nvdimmAddPage4Regs(i_nvdimm,l_err); + + // Add reg traces to the error log + NVDIMM::UdNvdimmOPParms( l_RegInfo ).addToLog(l_err); - // Disarm the ddr_resetn here in case it came in armed. When the nvdimm is - // armed the reset_n is masked off from the host, meaning the drams won't - // be able to get reset properly later, causing training to fail. - l_err = nvdimmChangeArmState(i_nvdimm, DISARM_TRIGGER); + errlCommit(l_err, NVDIMM_COMP_ID); + } + else + { + // Check save progress + l_err = nvdimmPollBackupDone(i_nvdimm, l_poll); + if (l_err) + { + // May have to move the error handling to the caller + // as different op could have different error severity + l_err->addHwCallout( i_nvdimm, + HWAS::SRCI_PRIORITY_HIGH, + HWAS::DECONFIG, + HWAS::GARD_Fatal); + + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_int() nvdimm[%X], error backing up the DRAM!", + get_huid(i_nvdimm)); + break; + } + } + // Check CSAVE FAIL INFO registers for fail errors + l_err = nvdimmReadReg( i_nvdimm, CSAVE_FAIL_INFO0, l_failinfo0 ); + if (l_err) + { + break; + } + l_err = nvdimmReadReg ( i_nvdimm, CSAVE_FAIL_INFO1, l_failinfo1 ); + if (l_err) + { + break; + } + // Apply mask for relevant 1:6 bits to failinfo1 + l_failinfo1 &= CSAVE_FAIL_BITS_MASK; + + // Check CSAVE_STATUS Register + l_err = nvdimmReadReg( i_nvdimm, CSAVE_STATUS, l_data ); if (l_err) { - nvdimmSetStatusFlag(i_nvdimm, NSTD_ERR_NOPRSV); - TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_init() nvdimm[%X], error disarming the nvdimm!", - TARGETING::get_huid(i_nvdimm)); - errlCommit(l_err, NVDIMM_COMP_ID); break; } + else if ((l_data == SAVE_ERROR) && ((l_failinfo0 != ZERO) || (l_failinfo1 != ZERO))) + { + /*@ + *@errortype + *@reasoncode NVDIMM_CSAVE_ERROR + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_CHECK_CSAVE + *@userdata1[0:31] Related ops (0xff = NA) + *@userdata1[32:63] Target Huid + *@userdata2 <UNUSED> + *@devdesc Encountered error saving during catastrophic save + * on NVDIMM. Check error register trace for details + *@custdesc NVDIMM error during Catastrophic Save + */ + l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_CHECK_CSAVE, + NVDIMM_CSAVE_ERROR, + NVDIMM_SET_USER_DATA_1(l_data, get_huid(i_nvdimm)), + 0x0, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + + l_err->collectTrace( NVDIMM_COMP_NAME ); + + // Collect register data for FFDC Traces + nvdimmTraceRegs ( i_nvdimm, l_RegInfo ); + nvdimmAddPage4Regs(i_nvdimm,l_err); + nvdimmAddVendorLog(i_nvdimm, l_err); + + // Add reg traces to the error log + NVDIMM::UdNvdimmOPParms( l_RegInfo ).addToLog(l_err); + + // Check if the image is still valid + if ( l_RegInfo.CSave_Info != VALID_IMAGE ) + { + // Callout and gard dimm if image is not valid + l_err->addHwCallout( i_nvdimm, + HWAS::SRCI_PRIORITY_HIGH, + HWAS::DECONFIG, + HWAS::GARD_Fatal); + break; + } + else + { + // Callout dimm without gard if image is valid + l_err->addHwCallout( i_nvdimm, + HWAS::SRCI_PRIORITY_LOW, + HWAS::NO_DECONFIG, + HWAS::GARD_NULL); + + // Set ATTR_NV_STATUS_FLAG to partial working as data may persist + nvdimmSetStatusFlag(i_nvdimm, NSTD_ERR_VAL_SR); + errlCommit(l_err, NVDIMM_COMP_ID); + } + } + + // Check Health Status Registers + l_err = nvdimmHealthStatusCheck(i_nvdimm, HEALTH_SAVE, l_continue); + if(!l_continue) + { + break; + } + + // Unlock encryption if enabled + TargetHandleList l_nvdimmTargetList; + l_nvdimmTargetList.push_back(i_nvdimm); + NVDIMM::nvdimm_encrypt_unlock(l_nvdimmTargetList); }while(0); TRACUCOMP(g_trac_nvdimm, EXIT_MRK"nvdimm_init() nvdimm[%X]", - TARGETING::get_huid(i_nvdimm)); + get_huid(i_nvdimm)); + + if (l_err) + { + l_err->collectTrace( NVDIMM_COMP_NAME ); + errlCommit(l_err, NVDIMM_COMP_ID); + } } + + +void nvdimm_thresholds(TARGETING::TargetHandleList &i_nvdimmList) +{ + TRACUCOMP(g_trac_nvdimm, ENTER_MRK"nvdimm_thresholds()"); + + errlHndl_t l_err = nullptr; + + for (const auto & l_nvdimm : i_nvdimmList) + { + // ES_LIFETIME_WARNING_THRESHOLD + l_err = nvdimmWriteReg(l_nvdimm, + ES_LIFETIME_WARNING_THRESHOLD, + THRESHOLD_ES_LIFETIME); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, + ERR_MRK"nvdimm_thresholds() nvdimm[%X] " + "error setting ES_LIFETIME_WARNING_THRESHOLD", + get_huid(l_nvdimm)); + errlCommit( l_err, NVDIMM_COMP_ID ); + } + + // NVM_LIFETIME_WARNING_THRESHOLD + l_err = nvdimmWriteReg(l_nvdimm, + NVM_LIFETIME_WARNING_THRESHOLD, + THRESHOLD_NVM_LIFETIME); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, + ERR_MRK"nvdimm_thresholds() nvdimm[%X] " + "error setting NVM_LIFETIME_WARNING_THRESHOLD", + get_huid(l_nvdimm)); + errlCommit( l_err, NVDIMM_COMP_ID ); + } + + // ES_TEMP_WARNING_HIGH_THRESHOLD1 + l_err = nvdimmWriteReg(l_nvdimm, + ES_TEMP_WARNING_HIGH_THRESHOLD1, + THRESHOLD_ES_TEMP_HIGH_1); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, + ERR_MRK"nvdimm_thresholds() nvdimm[%X] " + "error setting ES_TEMP_WARNING_HIGH_THRESHOLD1", + get_huid(l_nvdimm)); + errlCommit( l_err, NVDIMM_COMP_ID ); + } + + // ES_TEMP_WARNING_HIGH_THRESHOLD0 + l_err = nvdimmWriteReg(l_nvdimm, + ES_TEMP_WARNING_HIGH_THRESHOLD0, + THRESHOLD_ES_TEMP_HIGH_0); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, + ERR_MRK"nvdimm_thresholds() nvdimm[%X] " + "error setting ES_TEMP_WARNING_HIGH_THRESHOLD0", + get_huid(l_nvdimm)); + errlCommit( l_err, NVDIMM_COMP_ID ); + } + + // ES_TEMP_WARNING_LOW_THRESHOLD1 + l_err = nvdimmWriteReg(l_nvdimm, + ES_TEMP_WARNING_LOW_THRESHOLD1, + THRESHOLD_ES_TEMP_LOW_1); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, + ERR_MRK"nvdimm_thresholds() nvdimm[%X] " + "error setting ES_TEMP_WARNING_LOW_THRESHOLD1", + get_huid(l_nvdimm)); + errlCommit( l_err, NVDIMM_COMP_ID ); + } + + // ES_TEMP_WARNING_LOW_THRESHOLD0 + l_err = nvdimmWriteReg(l_nvdimm, + ES_TEMP_WARNING_LOW_THRESHOLD0, + THRESHOLD_ES_TEMP_LOW_0); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, + ERR_MRK"nvdimm_thresholds() nvdimm[%X] " + "error setting ES_TEMP_WARNING_LOW_THRESHOLD0", + get_huid(l_nvdimm)); + errlCommit( l_err, NVDIMM_COMP_ID ); + } + } + + TRACUCOMP(g_trac_nvdimm, EXIT_MRK"nvdimm_thresholds()"); +} + + +errlHndl_t nvdimm_getRandom(uint8_t* o_genData) +{ + errlHndl_t l_err = nullptr; + uint8_t l_xtraData[ENC_KEY_SIZE] = {0}; + + do + { + // Get a pointer to the TPM + Target* l_tpm = nullptr; + l_err = nvdimm_getTPM(l_tpm); + if (l_err) + { + break; + } + + // Get a random number from the TPM + l_err = TRUSTEDBOOT::GetRandom(l_tpm, ENC_KEY_SIZE, o_genData); + if (l_err) + { + break; + } + + // Validate and update the random number + // Retry if more randomness required + do + { + //Get replacement data + l_err = TRUSTEDBOOT::GetRandom(l_tpm, ENC_KEY_SIZE, l_xtraData); + if (l_err) + { + break; + } + + }while (nvdimm_keyifyRandomNumber(o_genData, l_xtraData)); + + } while(0); + + return l_err; +} + + +errlHndl_t nvdimm_getTPM(Target*& o_tpm) +{ + errlHndl_t l_err = nullptr; + + do + { + // Get all functional TPMs + TargetHandleList l_tpmList; + TRUSTEDBOOT::getTPMs(l_tpmList, + TRUSTEDBOOT::TPM_FILTER::ALL_FUNCTIONAL); + + if (l_tpmList.size()) + { + o_tpm = l_tpmList[0]; + break; + } + + // No TPMs, generate error + TRACFCOMP(g_trac_nvdimm,ERR_MRK"nvdimm_getTPM() No functional TPMs found"); + + /*@ + *@errortype + *@reasoncode NVDIMM_TPM_NOT_FOUND + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_GET_TPM + *@devdesc Functional TPM required to generate encryption keys + *@custdesc NVDIMM error generating encryption keys + */ + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_GET_TPM, + NVDIMM_TPM_NOT_FOUND, + 0x0, + 0x0, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + + l_err->collectTrace(NVDIMM_COMP_NAME); + + // Get all TPMs + TRUSTEDBOOT::getTPMs(l_tpmList, + TRUSTEDBOOT::TPM_FILTER::ALL_IN_BLUEPRINT); + if (l_tpmList.size() == 0) + { + // No TPMs, we probably have nvdimms enabled + // when they should not be + l_err->addProcedureCallout( + HWAS::EPUB_PRC_HB_CODE, + HWAS::SRCI_PRIORITY_HIGH); + } + else + { + // If a TPM exists it must be deconfigured + l_err->addProcedureCallout( + HWAS::EPUB_PRC_FIND_DECONFIGURED_PART, + HWAS::SRCI_PRIORITY_HIGH); + l_err->addProcedureCallout( + HWAS::EPUB_PRC_HB_CODE, + HWAS::SRCI_PRIORITY_MED); + } + + }while(0); + + // Functional TPM not found + return l_err; +} + + +#endif + + +/** + * @brief Force a factory reset of the NV logic and flash + * + * @param[in] i_nvdimm - NVDIMM Target + */ +errlHndl_t nvdimm_factory_reset(Target *i_nvdimm) +{ + TRACFCOMP(g_trac_nvdimm, ENTER_MRK"nvdimm_factory_reset() nvdimm[%X]", + get_huid(i_nvdimm)); + errlHndl_t l_err = nullptr; + + do + { + // Send the reset command + l_err = nvdimmWriteReg(i_nvdimm, NVDIMM_FUNC_CMD, FACTORY_DEFAULT); + if( l_err ) + { + break; + } + + // Poll 2 minutes for completion + // We could get the timeout value from the dimm but since we're + // doing a hard reset anyway I just want to use a big number that + // can handle any lies that the controller might tell us. + uint8_t l_data = 0; + constexpr uint64_t MAX_POLL_SECONDS = 120; + uint64_t poll = 0; + for( poll = 0; poll < MAX_POLL_SECONDS; poll++ ) + { + l_err = nvdimmReadReg(i_nvdimm, NVDIMM_CMD_STATUS0, l_data); + if( l_err ) + { + break; + } + + if( l_data != FACTORY_RESET_IN_PROGRESS ) + { + break; + } + +#ifndef __HOSTBOOT_RUNTIME + // kick the watchdog since this can take awhile + INITSERVICE::sendProgressCode(); #endif + // sleep 1 second + nanosleep(1, 0); + } + if( l_err ) { break; } + + // Make an error if it never finished + if( poll >= MAX_POLL_SECONDS ) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_factory_reset() nvdimm[%X] - factory reset never completed[%d]", + get_huid(i_nvdimm), l_data); + /*@ + *@errortype + *@reasoncode NVDIMM_NOT_READY + *@severity ERRORLOG_SEV_UNRECOVERABLE + *@moduleid NVDIMM_FACTORY_RESET + *@userdata1[0:31] Ret value from ready register + *@userdata1[32:63] Target Huid + *@userdata2 Number of seconds waited + *@devdesc NVDIMM factory reset never completed + *@custdesc NVDIMM still in reset + */ + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + NVDIMM_FACTORY_RESET, + NVDIMM_NOT_READY, + NVDIMM_SET_USER_DATA_1(l_data, get_huid(i_nvdimm)), + MAX_POLL_SECONDS, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + + l_err->collectTrace(NVDIMM_COMP_NAME); + nvdimmAddVendorLog(i_nvdimm, l_err); + + // If nvdimm is not ready for access by now, this is + // a failing indication on the NV controller + l_err->addPartCallout( i_nvdimm, + HWAS::NV_CONTROLLER_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + nvdimmAddPage4Regs(i_nvdimm,l_err); + } + } while(0); + + return l_err; +} + + +bool nvdimm_encrypt_unlock(TargetHandleList &i_nvdimmList) +{ + TRACFCOMP(g_trac_nvdimm, ENTER_MRK"nvdimm_encrypt_unlock()"); + errlHndl_t l_err = nullptr; + bool l_success = true; + + do + { + // Do not check ATTR_NVDIMM_ENCRYPTION_ENABLE + // The attribute could have been reset by flashing the FSP + // Unlock if the keys are valid and NVDIMM hw encryption is enabled + + // Get the sys pointer, attribute keys are system level + Target* l_sys = nullptr; + targetService().getTopLevelTarget( l_sys ); + assert(l_sys, "nvdimm_encrypt_unlock() no TopLevelTarget"); + + // Get the FW key attributes + auto l_attrKeysFw = + l_sys->getAttrAsStdArr<ATTR_NVDIMM_ENCRYPTION_KEYS_FW>(); + + // Cast to key data struct type for easy access to each key + nvdimmKeyData_t* l_keysFw = + reinterpret_cast<nvdimmKeyData_t*>(&l_attrKeysFw); + + // Check encryption unlock for all nvdimms + for (const auto & l_nvdimm : i_nvdimmList) + { + // Get encryption state in the config/status reg + encryption_config_status_t l_encStatus = {0}; + l_err = nvdimmReadReg(l_nvdimm, + ENCRYPTION_CONFIG_STATUS, + l_encStatus.whole); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_encrypt_unlock() nvdimm[%X] error reading ENCRYPTION_CONFIG_STATUS",get_huid(l_nvdimm)); + errlCommit( l_err, NVDIMM_COMP_ID ); + nvdimmSetEncryptionError(l_nvdimm); + l_success = false; + continue; + } + + // Already unlocked or not enabled then exit + if (l_encStatus.encryption_unlocked || + !l_encStatus.encryption_enabled) + { + break; + } + + // Check for valid key attribute data + l_err = nvdimm_checkValidAttrKeys(l_keysFw); + if (l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + nvdimmSetEncryptionError(l_nvdimm); + l_success = false; + break; + } + + // Else encryption is enabled but needs unlock + TRACFCOMP(g_trac_nvdimm, "nvdimm_encrypt_unlock() nvdimm[%X] enabled, unlocking...",get_huid(l_nvdimm)); + + // Set the Unlock Access Key Reg + l_err = nvdimm_setKeyReg(l_nvdimm, + l_keysFw->ak, + ENCRYPTION_ACCESS_KEY_UNLOCK, + ENCRYPTION_ACCESS_KEY_VERIFY, + false); + if (l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + nvdimmSetEncryptionError(l_nvdimm); + l_success = false; + continue; + } + + // Verify encryption is unlocked + l_err = nvdimmReadReg(l_nvdimm, + ENCRYPTION_CONFIG_STATUS, + l_encStatus.whole); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_encrypt_unlock() nvdimm[%X] error reading ENCRYPTION_CONFIG_STATUS after unlock",get_huid(l_nvdimm)); + errlCommit( l_err, NVDIMM_COMP_ID ); + nvdimmSetEncryptionError(l_nvdimm); + l_success = false; + continue; + } + + if (!l_encStatus.encryption_unlocked) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_encrypt_unlock() nvdimm[%X] encryption unlock failed, expected ENCRYPTION_CONFIG_STATUS=0x%.02X, expected=0x1F ",get_huid(l_nvdimm),l_encStatus.whole); + /*@ + *@errortype + *@reasoncode NVDIMM_ENCRYPTION_UNLOCK_FAILED + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_ENCRYPT_UNLOCK + *@userdata1 NVDIMM HUID + *@userdata2 ENCRYPTION_CONFIG_STATUS + *@devdesc NVDIMM failed to unlock encryption + *@custdesc NVDIMM encryption error + */ + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_ENCRYPT_UNLOCK, + NVDIMM_ENCRYPTION_UNLOCK_FAILED, + get_huid(l_nvdimm), + l_encStatus.whole, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + + l_err->collectTrace(NVDIMM_COMP_NAME); + nvdimmAddVendorLog(l_nvdimm, l_err); + l_err->addPartCallout( l_nvdimm, + HWAS::NV_CONTROLLER_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + l_err->addHwCallout( l_nvdimm, + HWAS::SRCI_PRIORITY_MED, + HWAS::DELAYED_DECONFIG, + HWAS::GARD_NULL ); + + nvdimmAddPage4Regs(l_nvdimm,l_err); + errlCommit( l_err, NVDIMM_COMP_ID ); + nvdimmSetEncryptionError(l_nvdimm); + l_success = false; + } + else + { + TRACFCOMP(g_trac_nvdimm, "nvdimm_encrypt_unlock() nvdimm[%X] encryption is unlocked 0x%.02x",get_huid(l_nvdimm),l_encStatus.whole); + } + } + }while(0); + + TRACFCOMP(g_trac_nvdimm, EXIT_MRK"nvdimm_encrypt_unlock()"); + return l_success; +} + + +void nvdimmSetEncryptionError(Target *i_nvdimm) +{ + ATTR_NVDIMM_ARMED_type l_armed_state = {}; + l_armed_state = i_nvdimm->getAttr<ATTR_NVDIMM_ARMED>(); + + l_armed_state.encryption_error_detected = 1; + + i_nvdimm->setAttr<ATTR_NVDIMM_ARMED>(l_armed_state); +} + + +bool nvdimm_keyifyRandomNumber(uint8_t* o_genData, uint8_t* i_xtraData) +{ + bool l_failed = false; + uint32_t l_xtraByte = 0; + + for (uint32_t l_byte = 0; l_byte < ENC_KEY_SIZE; l_byte++) + { + if ((o_genData[l_byte] != KEY_TERMINATE_BYTE) && + (o_genData[l_byte] != KEY_ABORT_BYTE)) + { + // This byte is valid + continue; + } + + // This byte is not valid, replace it + // Find a valid byte in the replacement data + while ((i_xtraData[l_xtraByte] == KEY_TERMINATE_BYTE) || + (i_xtraData[l_xtraByte] == KEY_ABORT_BYTE)) + { + l_xtraByte++; + + if (l_xtraByte == ENC_KEY_SIZE) + { + l_failed = true; + break; + } + } + + if (l_failed) + { + break; + } + + // Replace the invalid byte with the valid extra byte + o_genData[l_byte] = i_xtraData[l_xtraByte]; + } + + return l_failed; +} + + +bool nvdimm_validRandomNumber(uint8_t* i_genData) +{ + bool l_valid = true; + for (uint32_t l_byte = 0; l_byte < ENC_KEY_SIZE; l_byte++) + { + if ((i_genData[l_byte] == KEY_TERMINATE_BYTE) || + (i_genData[l_byte] == KEY_ABORT_BYTE)) + { + l_valid = false; + break; + } + } + return l_valid; +} + + +errlHndl_t nvdimm_checkValidAttrKeys( nvdimmKeyData_t* i_attrData ) +{ + errlHndl_t l_err = nullptr; + bool l_valid = false; + + do + { + l_valid = nvdimm_validRandomNumber(i_attrData->rs); + if (!l_valid) + { + break; + } + l_valid = nvdimm_validRandomNumber(i_attrData->ek); + if (!l_valid) + { + break; + } + l_valid = nvdimm_validRandomNumber(i_attrData->ak); + if (!l_valid) + { + break; + } + }while(0); + + if (!l_valid) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_checkValidAttrKeys() ATTR_NVDIMM_ENCRYPTION_KEYS_FW contains invalid data"); + /*@ + *@errortype + *@reasoncode NVDIMM_ENCRYPTION_INVALID_ATTRIBUTE + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_CHECK_VALID_ATTR_DATA + *@devdesc ATTR_NVDIMM_ENCRYPTION_KEYS_FW has invalid data + *@custdesc NVDIMM encryption error + */ + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_CHECK_VALID_ATTR_DATA, + NVDIMM_ENCRYPTION_INVALID_ATTRIBUTE, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT ); + + l_err->collectTrace(NVDIMM_COMP_NAME); + } + + return l_err; +} + + +errlHndl_t nvdimm_handleConflictingKeys( + ATTR_NVDIMM_ENCRYPTION_KEYS_FW_typeStdArr& i_attrKeysFw, + ATTR_NVDIMM_ENCRYPTION_KEYS_ANCHOR_typeStdArr& i_attrKeysAnchor) +{ + TRACFCOMP(g_trac_nvdimm, ENTER_MRK"nvdimm_handleConflictingKeys()"); + errlHndl_t l_err = nullptr; + bool l_validKeyFound = false; + + // Recast to key data type to simplify parsing + nvdimmKeyData_t* l_keysFw = + reinterpret_cast<nvdimmKeyData_t*>(&i_attrKeysFw); + nvdimmKeyData_t* l_keysAnchor = + reinterpret_cast<nvdimmKeyData_t*>(&i_attrKeysAnchor); + + // Get the nvdimm target pointers + TargetHandleList l_nvdimmTargetList; + nvdimm_getNvdimmList(l_nvdimmTargetList); + for (const auto & l_nvdimm : l_nvdimmTargetList) + { + // Check encryption state in the config/status reg + encryption_config_status_t l_encStatus = {0}; + l_err = nvdimmReadReg(l_nvdimm, + ENCRYPTION_CONFIG_STATUS, + l_encStatus.whole); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_handleConflictingKeys() nvdimm[%X] error reading ENCRYPTION_CONFIG_STATUS",get_huid(l_nvdimm)); + errlCommit( l_err, NVDIMM_COMP_ID ); + nvdimmSetEncryptionError(l_nvdimm); + continue; + } + + // Encryption is not enabled + // Keys are not in use so could use either set of keys + // Use the ANCHOR card keys + if (!l_encStatus.encryption_enabled) + { + TRACFCOMP(g_trac_nvdimm, "nvdimm_handleConflictingKeys() nvdimm[%X] copying ANCHOR keys to FW",get_huid(l_nvdimm)); + l_validKeyFound = true; + set_ATTR_NVDIMM_ENCRYPTION_KEYS_FW(i_attrKeysAnchor); + continue; + } + + // Encryption is enabled, test the keys + // Write the EK test reg with the FW attr value + l_err = nvdimm_setKeyReg(l_nvdimm, + l_keysFw->ek, + ENCRYPTION_ERASE_KEY_TEST, + ENCRYPTION_ERASE_KEY_TEST_VERIFY, + false); + if (l_err) + { + break; + } + + // Check for erase key valid in the validation reg + encryption_key_validation_t l_keyValid = {0}; + l_err = nvdimmReadReg(l_nvdimm, + ENCRYPTION_KEY_VALIDATION, + l_keyValid.whole); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_handleConflictingKeys() nvdimm[%X] error reading ENCRYPTION_KEY_VALIDATION",get_huid(l_nvdimm)); + break; + } + if (l_keyValid.erase_key_valid) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_handleConflictingKeys() nvdimm[%X] ATTR_NVDIMM_ENCRYPTION_KEYS_FW valid",get_huid(l_nvdimm)); + l_validKeyFound = true; + // Re-write the FW keys, this will also update the ANCHOR keys + set_ATTR_NVDIMM_ENCRYPTION_KEYS_FW(i_attrKeysFw); + break; + } + + // Write the EK test reg with the Anchor attr value + l_err = nvdimm_setKeyReg(l_nvdimm, + l_keysAnchor->ek, + ENCRYPTION_ERASE_KEY_TEST, + ENCRYPTION_ERASE_KEY_TEST_VERIFY, + false); + if (l_err) + { + break; + } + + // Check for erase key valid in the validation reg + l_keyValid.whole = 0; + l_err = nvdimmReadReg(l_nvdimm, + ENCRYPTION_KEY_VALIDATION, + l_keyValid.whole); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_handleConflictingKeys() nvdimm[%X] error reading ENCRYPTION_KEY_VALIDATION",get_huid(l_nvdimm)); + break; + } + if (l_keyValid.erase_key_valid) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_handleConflictingKeys() nvdimm[%X] ATTR_NVDIMM_ENCRYPTION_KEYS_ANCHOR valid",get_huid(l_nvdimm)); + l_validKeyFound = true; + // Copy anchor attr value to FW attribute + set_ATTR_NVDIMM_ENCRYPTION_KEYS_FW(i_attrKeysAnchor); + + break; + } + } + + if (!l_validKeyFound) + { + // Neither key attribute is valid + TRACFCOMP(g_trac_nvdimm,ERR_MRK"nvdimm_handleConflictingKeys() ATTR_NVDIMM_ENCRYPTION_KEYS_FW and ATTR_NVDIMM_ENCRYPTION_KEYS_ANCHOR invalid."); + /*@ + *@errortype + *@reasoncode NVDIMM_ENCRYPTION_KEY_ATTRS_INVALID + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_HANDLE_CONFLICTING_KEYS + *@devdesc NVDIMM encryption key attributes invalid + *@custdesc NVDIMM encryption error + */ + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_HANDLE_CONFLICTING_KEYS, + NVDIMM_ENCRYPTION_KEY_ATTRS_INVALID, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT ); + + l_err->collectTrace(NVDIMM_COMP_NAME); + } + + TRACFCOMP(g_trac_nvdimm, EXIT_MRK"nvdimm_handleConflictingKeys()"); + return l_err; +} + + +void nvdimm_getNvdimmList(TargetHandleList &o_nvdimmTargetList) +{ + // Check for any NVDIMMs after the mss_power_cleanup + TargetHandleList l_dimmTargetList; + getAllLogicalCards(l_dimmTargetList, TYPE_DIMM); + + // Walk the dimm list and collect all the nvdimm targets + for (auto const l_dimm : l_dimmTargetList) + { + if (isNVDIMM(l_dimm)) + { + o_nvdimmTargetList.push_back(l_dimm); + } + } +} + + +bool nvdimm_gen_keys(void) +{ + TRACFCOMP(g_trac_nvdimm, ENTER_MRK"nvdimm_gen_keys()"); + errlHndl_t l_err = nullptr; + bool l_success = true; + + do + { + // Determine if key generation required + Target* l_sys = nullptr; + targetService().getTopLevelTarget( l_sys ); + assert(l_sys, "nvdimm_gen_keys: no TopLevelTarget"); + + // Key size must be less that max TPM random generator size + static_assert(ENC_KEY_SIZE <= MAX_TPM_SIZE, + "nvdimm_gen_keys() ENC_KEY_SIZE is greater than MAX_TPM_SIZE"); + + // Key attributes should be same size + static_assert( sizeof(ATTR_NVDIMM_ENCRYPTION_KEYS_ANCHOR_type) == + sizeof(ATTR_NVDIMM_ENCRYPTION_KEYS_FW_type), + "nvdimm_gen_keys() size of ATTR_NVDIMM_ENCRYPTION_KEYS_ANCHOR_type does not match ATTR_NVDIMM_ENCRYPTION_KEYS_FW_type"); + + // Get the key attributes + auto l_attrKeysFw = + l_sys->getAttrAsStdArr<ATTR_NVDIMM_ENCRYPTION_KEYS_FW>(); + auto l_attrKeysAn = + l_sys->getAttrAsStdArr<ATTR_NVDIMM_ENCRYPTION_KEYS_ANCHOR>(); + + // Check the attribute sizes + static_assert(sizeof(l_attrKeysFw) == (NUM_KEYS_IN_ATTR * ENC_KEY_SIZE), + "nvdimm_gen_keys() Size of ATTR_NVDIMM_ENCRYPTION_KEYS_FW does not match NUM_KEYS_IN_ATTR * ENC_KEY_SIZE"); + static_assert(sizeof(l_attrKeysAn) == (NUM_KEYS_IN_ATTR * ENC_KEY_SIZE), + "nvdimm_gen_keys() Size of ATTR_NVDIMM_ENCRYPTION_KEYS_ANCHOR does not match NUM_KEYS_IN_ATTR * ENC_KEY_SIZE"); + + // Compare attributes to zero + std::array<uint8_t,sizeof(l_attrKeysFw)> l_zero = {0}; + bool l_fwZero = (l_attrKeysFw == l_zero); + bool l_anZero = (l_attrKeysAn == l_zero); + + // Compare the attribute values + if (!l_fwZero && !l_anZero) + { + if (l_attrKeysFw != l_attrKeysAn) + { + // Handle conflicting keys + TRACFCOMP(g_trac_nvdimm, "nvdimm_gen_keys() ATTR_NVDIMM_ENCRYPTION_KEYS_FW != ATTR_NVDIMM_ENCRYPTION_KEYS_ANCHOR"); + l_err = nvdimm_handleConflictingKeys(l_attrKeysFw,l_attrKeysAn); + } + else + { + TRACFCOMP(g_trac_nvdimm, "nvdimm_gen_keys() ATTR_NVDIMM_ENCRYPTION_KEYS_FW == ATTR_NVDIMM_ENCRYPTION_KEYS_ANCHOR"); + } + break; + } + else if (!l_fwZero && l_anZero) + { + TRACFCOMP(g_trac_nvdimm, "nvdimm_gen_keys() ATTR_NVDIMM_ENCRYPTION_KEYS_FW != 0 and ATTR_NVDIMM_ENCRYPTION_KEYS_ANCHOR = 0"); + break; + } + else if (l_fwZero && !l_anZero) + { + // Set FW attr = Anchor attr + TRACFCOMP(g_trac_nvdimm, "nvdimm_gen_keys() Setting ATTR_NVDIMM_ENCRYPTION_KEYS_FW = ATTR_NVDIMM_ENCRYPTION_KEYS_ANCHOR"); + set_ATTR_NVDIMM_ENCRYPTION_KEYS_FW(l_attrKeysAn); + break; + } + + // If we get here then both key attributes are zero, generate new keys + assert(sizeof(l_attrKeysFw) == sizeof(nvdimmKeyData_t), + "nvdimm_gen_keys() ATTR_NVDIMM_ENCRYPTION_KEYS_FW size does not match nvdimmKeyData_t"); + nvdimmKeyData_t* l_keys = + reinterpret_cast<nvdimmKeyData_t*>(&l_attrKeysFw); + + // Generate Random String (RS) + l_err = nvdimm_getRandom(l_keys->rs); + if (l_err) + { + break; + } + + // Generate Erase Key (EK) + l_err = nvdimm_getRandom(l_keys->ek); + if (l_err) + { + break; + } + + // Generate Access Key (AK) + l_err = nvdimm_getRandom(l_keys->ak); + if (l_err) + { + break; + } + + // Set the FW attribute + set_ATTR_NVDIMM_ENCRYPTION_KEYS_FW(l_attrKeysFw); + + }while(0); + + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_gen_keys() Failed to generate keys, will not set ATTR_NVDIMM_ENCRYPTION_KEYS_FW"); + errlCommit( l_err, NVDIMM_COMP_ID ); + l_success = false; + + // Set the encryption error for all nvdimms + TargetHandleList l_nvdimmTargetList; + nvdimm_getNvdimmList(l_nvdimmTargetList); + for (const auto & l_nvdimm : l_nvdimmTargetList) + { + nvdimmSetEncryptionError(l_nvdimm); + } + } + + TRACFCOMP(g_trac_nvdimm, EXIT_MRK"nvdimm_gen_keys()"); + return l_success; +} + + +bool nvdimm_remove_keys(void) +{ + TRACFCOMP(g_trac_nvdimm, ENTER_MRK"nvdimm_remove_keys()"); + bool l_success = true; + + // Get the sys pointer, attribute keys are system level + Target* l_sys = nullptr; + targetService().getTopLevelTarget( l_sys ); + assert(l_sys, "nvdimm_remove_keys() no TopLevelTarget"); + + // Set the FW attribute = 0 + TRACFCOMP(g_trac_nvdimm, "nvdimm_remove_keys() Setting ATTR_NVDIMM_ENCRYPTION_KEYS_FW=0"); + ATTR_NVDIMM_ENCRYPTION_KEYS_FW_typeStdArr l_attrKeysFw = {0}; + set_ATTR_NVDIMM_ENCRYPTION_KEYS_FW(l_attrKeysFw); + + TRACFCOMP(g_trac_nvdimm, EXIT_MRK"nvdimm_remove_keys()"); + return l_success; +} + + +errlHndl_t nvdimm_setKeyReg(Target* i_nvdimm, + uint8_t* i_keyData, + uint32_t i_keyReg, + uint32_t i_verifyReg, + bool i_secondAttempt) +{ + TRACFCOMP(g_trac_nvdimm, ENTER_MRK"nvdimm_setKeyReg(0x%X) reg=0x%X",get_huid(i_nvdimm),i_keyReg); + errlHndl_t l_err = nullptr; + + do + { + uint32_t l_byte = 0; + uint8_t l_verifyData = 0x0; + + // Before setting the key reg we need to + // init the verif reg with a random value + uint8_t l_genData[ENC_KEY_SIZE] = {0}; + l_err = nvdimm_getRandom(l_genData); + if (l_err) + { + break; + } + + // Write the verif reg one byte at a time + for (l_byte = 0; l_byte < ENC_KEY_SIZE; l_byte++) + { + // Write the verification byte + l_err = nvdimmWriteReg(i_nvdimm, i_verifyReg, l_genData[l_byte]); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_setKeyReg() huid=0x%X, error writing verif reg=0x%.03X byte=0x%d", get_huid(i_nvdimm), i_verifyReg, l_byte); + break; + } + } + + // Delay to allow verif write to complete + nanosleep(0, KEY_WRITE_DELAY_MS*NS_PER_MSEC); + + // Write the reg, one byte at a time + for (l_byte = 0; l_byte < ENC_KEY_SIZE; l_byte++) + { + // Write the key byte + l_err = nvdimmWriteReg(i_nvdimm, i_keyReg, i_keyData[l_byte]); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_setKeyReg() huid=0x%X, error writing key reg 0x%.03X byte=0x%d", get_huid(i_nvdimm), i_keyReg, l_byte); + break; + } + + // Read the verification byte + l_err = nvdimmReadReg(i_nvdimm, i_verifyReg, l_verifyData); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_setKeyReg() huid=0x%X, error reading verif reg=0x%.03X byte=0x%d", get_huid(i_nvdimm), i_verifyReg, l_byte); + break; + } + + // Verify the key byte + if (l_verifyData != i_keyData[l_byte]) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_setKeyReg() huid=0x%X, key verification failed reg=0x%.03X byte=0x%d set=0x%.02x get=0x%.02x", get_huid(i_nvdimm), i_keyReg, l_byte, i_keyData[l_byte], l_verifyData); + // Write KEY_ABORT_BYTE to abort the key write sequence + l_err = nvdimmWriteReg(i_nvdimm, i_keyReg, KEY_ABORT_BYTE); + if (i_secondAttempt) + { + // Verify check byte failed for the second time + TRACFCOMP(g_trac_nvdimm,ERR_MRK"nvdimm_getTPM() Key verification byte check failed on second attempt."); + /*@ + *@errortype + *@reasoncode NVDIMM_VERIF_BYTE_CHECK_FAILED + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_SET_KEY_REG + *@userdata1 NVDIMM HUID + *@userdata2[0:31] Key Register + *@userdata2[32:63] Verif Register + *@devdesc NVDIMM failed to set encryption register + *@custdesc NVDIMM register error + */ + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_SET_KEY_REG, + NVDIMM_VERIF_BYTE_CHECK_FAILED, + get_huid(i_nvdimm), + NVDIMM_SET_USER_DATA_1(i_keyReg,i_verifyReg), + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + + l_err->collectTrace(NVDIMM_COMP_NAME); + nvdimmAddVendorLog(i_nvdimm, l_err); + l_err->addPartCallout( i_nvdimm, + HWAS::NV_CONTROLLER_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + nvdimmAddPage4Regs(i_nvdimm,l_err); + } + else + { + // Try writing the reg again + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_setKeyReg() huid=0x%X, writing reg=0x%.03X again", get_huid(i_nvdimm), i_keyReg); + l_err = nvdimm_setKeyReg(i_nvdimm, + i_keyData, + i_keyReg, + i_verifyReg, + true); + } + break; + } + } + + // Delay to allow write to complete + nanosleep(0, KEY_WRITE_DELAY_MS*NS_PER_MSEC); + + }while(0); + + TRACFCOMP(g_trac_nvdimm, EXIT_MRK"nvdimm_setKeyReg(0x%X) reg=0x%X",get_huid(i_nvdimm),i_keyReg); + return l_err; +} + + +bool nvdimm_encrypt_enable(TargetHandleList &i_nvdimmList) +{ + TRACFCOMP(g_trac_nvdimm, ENTER_MRK"nvdimm_encrypt_enable()"); + errlHndl_t l_err = nullptr; + bool l_success = true; + + do + { + // Get the sys pointer, attribute keys are system level + Target* l_sys = nullptr; + targetService().getTopLevelTarget( l_sys ); + assert(l_sys, "nvdimm_encrypt_enable() no TopLevelTarget"); + + // Exit if encryption is not enabled via the attribute + if (!l_sys->getAttr<ATTR_NVDIMM_ENCRYPTION_ENABLE>()) + { + TRACFCOMP(g_trac_nvdimm,"ATTR_NVDIMM_ENCRYPTION_ENABLE=0"); + break; + } + + // Get the FW key attributes + auto l_attrKeysFw = + l_sys->getAttrAsStdArr<ATTR_NVDIMM_ENCRYPTION_KEYS_FW>(); + + // Cast to key data struct type for easy access to each key + nvdimmKeyData_t* l_keysFw = + reinterpret_cast<nvdimmKeyData_t*>(&l_attrKeysFw); + + // Check for valid key attribute key data + l_err = nvdimm_checkValidAttrKeys(l_keysFw); + if (l_err) + { + break; + } + + // Handle encryption for all nvdimms + for (const auto & l_nvdimm : i_nvdimmList) + { + // Check encryption state in the config/status reg + encryption_config_status_t l_encStatus = {0}; + l_err = nvdimmReadReg(l_nvdimm, + ENCRYPTION_CONFIG_STATUS, + l_encStatus.whole); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_encrypt_enable() nvdimm[%X] error reading ENCRYPTION_CONFIG_STATUS",get_huid(l_nvdimm)); + errlCommit( l_err, NVDIMM_COMP_ID ); + nvdimmSetEncryptionError(l_nvdimm); + l_success = false; + continue; + } + + // Encryption is enabled and unlocked + if (l_encStatus.encryption_unlocked && + l_encStatus.encryption_enabled) + { + TRACFCOMP(g_trac_nvdimm, "nvdimm_encrypt_enable() nvdimm[%X] enabled and unlocked",get_huid(l_nvdimm)); + continue; + } + + // Need to handle these cases? + if (!((l_encStatus.whole & ENCRYPTION_STATUS_CHECK_MASK) + == ENCRYPTION_STATUS_DISABLED)) + { + TRACFCOMP(g_trac_nvdimm, "nvdimm_encrypt_enable() nvdimm[%X] unsupported state 0x%.02X",get_huid(l_nvdimm),l_encStatus.whole); + continue; + } + + // Status = 0x01, enable encryption + // Set the Random String (RS) reg + TRACFCOMP(g_trac_nvdimm,"nvdimm_encrypt_enable() nvdimm[%X] status=0x01 0x%.02x",get_huid(l_nvdimm),l_encStatus.whole); + l_err = nvdimm_setKeyReg(l_nvdimm, + l_keysFw->rs, + ENCRYPTION_RAMDOM_STRING_SET, + ENCRYPTION_RANDOM_STRING_VERIFY, + false); + if (l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + nvdimmSetEncryptionError(l_nvdimm); + l_success = false; + continue; + } + + // Set the Erase Key (EK) Reg + l_err = nvdimm_setKeyReg(l_nvdimm, + l_keysFw->ek, + ENCRYPTION_ERASE_KEY_SET, + ENCRYPTION_ERASE_KEY_VERIFY, + false); + if (l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + nvdimmSetEncryptionError(l_nvdimm); + l_success = false; + continue; + } + + // Set the Access Key (AK) Reg + l_err = nvdimm_setKeyReg(l_nvdimm, + l_keysFw->ak, + ENCRYPTION_ACCESS_KEY_SET, + ENCRYPTION_ACCESS_KEY_VERIFY, + false); + if (l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + nvdimmSetEncryptionError(l_nvdimm); + l_success = false; + continue; + } + + // Verify encryption is enabled + l_err = nvdimmReadReg(l_nvdimm, + ENCRYPTION_CONFIG_STATUS, + l_encStatus.whole); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_encrypt_enable() nvdimm[%X] error reading ENCRYPTION_CONFIG_STATUS after enable",get_huid(l_nvdimm)); + errlCommit( l_err, NVDIMM_COMP_ID ); + nvdimmSetEncryptionError(l_nvdimm); + l_success = false; + continue; + } + if (!((l_encStatus.whole & ENCRYPTION_STATUS_CHECK_MASK) + == ENCRYPTION_STATUS_ENABLED)) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_encrypt_enable() nvdimm[%X] encryption enable failed, ENCRYPTION_CONFIG_STATUS=0x%.02X, expected=0x1F ",get_huid(l_nvdimm),l_encStatus.whole); + /*@ + *@errortype + *@reasoncode NVDIMM_ENCRYPTION_ENABLE_FAILED + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_ENCRYPT_ENABLE + *@userdata1 NVDIMM HUID + *@userdata2 ENCRYPTION_CONFIG_STATUS + *@devdesc NVDIMM failed to enable encryption + *@custdesc NVDIMM encryption error + */ + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_ENCRYPT_ENABLE, + NVDIMM_ENCRYPTION_ENABLE_FAILED, + get_huid(l_nvdimm), + l_encStatus.whole, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + + l_err->collectTrace(NVDIMM_COMP_NAME); + nvdimmAddVendorLog(l_nvdimm, l_err); + l_err->addPartCallout( l_nvdimm, + HWAS::NV_CONTROLLER_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + + nvdimmAddPage4Regs(l_nvdimm,l_err); + errlCommit( l_err, NVDIMM_COMP_ID ); + nvdimmSetEncryptionError(l_nvdimm); + l_success = false; + } + else + { + TRACFCOMP(g_trac_nvdimm, "nvdimm_encrypt_enable() nvdimm[%X] encryption is enabled 0x%.02x",get_huid(l_nvdimm),l_encStatus.whole); + + l_err = notifyNvdimmProtectionChange(l_nvdimm, + ENCRYPTION_ENABLED); + if (l_err) + { + errlCommit(l_err, NVDIMM_COMP_ID); + } + } + } + }while(0); + + TRACFCOMP(g_trac_nvdimm, EXIT_MRK"nvdimm_encrypt_enable()"); + return l_success; +} + + +bool nvdimm_crypto_erase(TargetHandleList &i_nvdimmList) +{ + TRACFCOMP(g_trac_nvdimm, ENTER_MRK"nvdimm_crypto_erase()"); + errlHndl_t l_err = nullptr; + bool l_success = true; + + do + { + // Get the sys pointer, attribute keys are system level + Target* l_sys = nullptr; + targetService().getTopLevelTarget( l_sys ); + assert(l_sys, "nvdimm_crypto_erase: no TopLevelTarget"); + + // Exit if encryption is not enabled via the attribute + if (!l_sys->getAttr<ATTR_NVDIMM_ENCRYPTION_ENABLE>()) + { + TRACFCOMP(g_trac_nvdimm,"ATTR_NVDIMM_ENCRYPTION_ENABLE=0"); + break; + } + + // Get the FW key attributes + auto l_attrKeysFw = + l_sys->getAttrAsStdArr<ATTR_NVDIMM_ENCRYPTION_KEYS_FW>(); + + // Cast to key data struct type for easy access to each key + nvdimmKeyData_t* l_keysFw = + reinterpret_cast<nvdimmKeyData_t*>(&l_attrKeysFw); + + // Check for valid key attribute key data + l_err = nvdimm_checkValidAttrKeys(l_keysFw); + if (l_err) + { + break; + } + + // Handle erase for all nvdimms + for (const auto & l_nvdimm : i_nvdimmList) + { + // Check encryption state in the config/status reg + encryption_config_status_t l_encStatus = {0}; + l_err = nvdimmReadReg(l_nvdimm, + ENCRYPTION_CONFIG_STATUS, + l_encStatus.whole); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_crypto_erase() nvdimm[%X] error reading ENCRYPTION_CONFIG_STATUS",get_huid(l_nvdimm)); + errlCommit( l_err, NVDIMM_COMP_ID ); + nvdimmSetEncryptionError(l_nvdimm); + l_success = false; + continue; + } + // Encryption enabled must be set to crypto erase + if (!l_encStatus.encryption_enabled) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_crypto_erase() nvdimm[%X] encryption not enabled, will not cypto erase 0x%.02x",get_huid(l_nvdimm),l_encStatus.whole); + l_success = false; + continue; + } + else + { + TRACFCOMP(g_trac_nvdimm, "nvdimm_crypto_erase() nvdimm[%X] encryption enabled 0x%.02x",get_huid(l_nvdimm),l_encStatus.whole); + } + + // Set the Erase Key (EK) Reg + l_err = nvdimm_setKeyReg(l_nvdimm, + l_keysFw->ek, + ENCRYPTION_ERASE_KEY_SET, + ENCRYPTION_ERASE_KEY_VERIFY, + false); + if (l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + nvdimmSetEncryptionError(l_nvdimm); + l_success = false; + continue; + } + + // Check encryption state in the config/status reg + l_err = nvdimmReadReg(l_nvdimm, + ENCRYPTION_CONFIG_STATUS, + l_encStatus.whole); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_crypto_erase() nvdimm[%X] error reading ENCRYPTION_CONFIG_STATUS",get_huid(l_nvdimm)); + errlCommit( l_err, NVDIMM_COMP_ID ); + nvdimmSetEncryptionError(l_nvdimm); + l_success = false; + continue; + } + // Erase pending bit should be set + if (!l_encStatus.erase_pending) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_crypto_erase() nvdimm[%X] expected erase pending = 1 0x%.02x",get_huid(l_nvdimm),l_encStatus.whole); + /*@ + *@errortype + *@reasoncode NVDIMM_ENCRYPTION_ERASE_PENDING_FAILED + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_CRYPTO_ERASE + *@userdata1 NVDIMM HUID + *@userdata2 ENCRYPTION_CONFIG_STATUS + *@devdesc NVDIMM failed to set encryption register + *@custdesc NVDIMM register error + */ + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_CRYPTO_ERASE, + NVDIMM_ENCRYPTION_ERASE_PENDING_FAILED, + get_huid(l_nvdimm), + l_encStatus.whole, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + + l_err->collectTrace(NVDIMM_COMP_NAME); + nvdimmAddVendorLog(l_nvdimm, l_err); + l_err->addPartCallout( l_nvdimm, + HWAS::NV_CONTROLLER_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + + nvdimmAddPage4Regs(l_nvdimm,l_err); + errlCommit( l_err, NVDIMM_COMP_ID ); + nvdimmSetEncryptionError(l_nvdimm); + l_success = false; + continue; + } + else + { + TRACFCOMP(g_trac_nvdimm,"nvdimm_crypto_erase() nvdimm[%X] erase pending 0x%.02x",get_huid(l_nvdimm),l_encStatus.whole); + } + + // Generate a generic erase key + uint8_t l_genData[ENC_KEY_SIZE] = {0}; + l_err = nvdimm_getRandom(l_genData); + if (l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + nvdimmSetEncryptionError(l_nvdimm); + l_success = false; + continue; + } + + // Set the Erase Key (EK) Reg + l_err = nvdimm_setKeyReg(l_nvdimm, + l_genData, + ENCRYPTION_ERASE_KEY_SET, + ENCRYPTION_ERASE_KEY_VERIFY, + false); + if (l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + nvdimmSetEncryptionError(l_nvdimm); + l_success = false; + continue; + } + + // Check encryption state in the config/status reg + l_err = nvdimmReadReg(l_nvdimm, + ENCRYPTION_CONFIG_STATUS, + l_encStatus.whole); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_crypto_erase() nvdimm[%X] error reading ENCRYPTION_CONFIG_STATUS",get_huid(l_nvdimm)); + errlCommit( l_err, NVDIMM_COMP_ID ); + nvdimmSetEncryptionError(l_nvdimm); + l_success = false; + continue; + } + // Encryption enabled bit should not be set + if (l_encStatus.encryption_enabled) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_crypto_erase() nvdimm[%X] expected encryption enabled = 0 0x%.02x",get_huid(l_nvdimm),l_encStatus.whole); + /*@ + *@errortype + *@reasoncode NVDIMM_ENCRYPTION_ERASE_FAILED + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_CRYPTO_ERASE + *@userdata1 NVDIMM HUID + *@userdata2 ENCRYPTION_CONFIG_STATUS + *@devdesc NVDIMM failed to set encryption register + *@custdesc NVDIMM register error + */ + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_CRYPTO_ERASE, + NVDIMM_ENCRYPTION_ERASE_FAILED, + get_huid(l_nvdimm), + l_encStatus.whole, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + + l_err->collectTrace(NVDIMM_COMP_NAME); + nvdimmAddVendorLog(l_nvdimm, l_err); + l_err->addPartCallout( l_nvdimm, + HWAS::NV_CONTROLLER_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + + nvdimmAddPage4Regs(l_nvdimm,l_err); + errlCommit( l_err, NVDIMM_COMP_ID ); + nvdimmSetEncryptionError(l_nvdimm); + l_success = false; + continue; + } + else + { + TRACFCOMP(g_trac_nvdimm,"nvdimm_crypto_erase() nvdimm[%X] erase complete 0x%.02x",get_huid(l_nvdimm),l_encStatus.whole); + + l_err = notifyNvdimmProtectionChange(l_nvdimm, + ENCRYPTION_DISABLED); + if (l_err) + { + errlCommit(l_err, NVDIMM_COMP_ID); + } + } + } + }while(0); + + TRACFCOMP(g_trac_nvdimm, EXIT_MRK"nvdimm_crypto_erase()"); + return l_success; +} + + +errlHndl_t notifyNvdimmProtectionChange(Target* i_target, + const nvdimm_protection_t i_state) +{ + TRACFCOMP( g_trac_nvdimm, ENTER_MRK + "notifyNvdimmProtectionChange: Target huid 0x%.8X, state %d", + get_huid(i_target), i_state); + + errlHndl_t l_err = nullptr; + + do + { + // Get the type of target passed in + // It could be proc_type for OCC state + // Or dimm_type for ARM/ERROR state + ATTR_TYPE_type l_type = i_target->getAttr<ATTR_TYPE>(); + assert((l_type == TYPE_PROC)||(l_type == TYPE_DIMM), + "notifyNvdimmProtectionChange invalid target type"); + + // Load the nvdimm list + TargetHandleList l_nvdimmTargetList; + Target* l_proc = nullptr; + if (l_type == TYPE_PROC) + { + // Get the nvdimms under this proc target + l_nvdimmTargetList = getProcNVDIMMs(i_target); + + // Only send command if the processor has an NVDIMM under it + if (l_nvdimmTargetList.empty()) + { + TRACFCOMP( g_trac_nvdimm, "notifyNvdimmProtectionChange: " + "No NVDIMM found under processor 0x%.8X", + get_huid(i_target)); + break; + } + + // The proc target is the passed-in target + l_proc = i_target; + } + else + { + // Only a list of one but keep consistent with proc type + l_nvdimmTargetList.push_back(i_target); + + // Find the proc target from nvdimm target passed in + TargetHandleList l_procList; + getParentAffinityTargets(l_procList, + i_target, + CLASS_CHIP, + TYPE_PROC, + UTIL_FILTER_ALL); + assert(l_procList.size() == 1, "notifyNvdimmProtectionChange:" + "getParentAffinityTargets size != 1"); + l_proc = l_procList[0]; + } + + + // Update the nvdimm status attributes + for (auto const l_nvdimm : l_nvdimmTargetList) + { + // Get the armed status attr and update it + ATTR_NVDIMM_ARMED_type l_armed_state = {}; + l_armed_state = l_nvdimm->getAttr<ATTR_NVDIMM_ARMED>(); + + // If we change the armed state, need to tell FSP + bool l_armed_change = false; + bool l_set_encryption = false; + bool l_clr_encryption = false; + bool l_sev_started = false; + bool l_sev_completed = false; + + switch (i_state) + { + case NVDIMM_ARMED: + l_armed_state.armed = 1; + l_armed_change = true; + break; + case NVDIMM_DISARMED: + l_armed_state.armed = 0; + l_armed_change = true; + break; + case OCC_ACTIVE: + l_armed_state.occ_active = 1; + break; + case OCC_INACTIVE: + l_armed_state.occ_active = 0; + break; + case NVDIMM_FATAL_HW_ERROR: + l_armed_state.fatal_error_detected = 1; + break; + case NVDIMM_RISKY_HW_ERROR: + l_armed_state.risky_error_detected = 1; + break; + case NVDIMM_ENCRYPTION_ERROR: + l_armed_state.encryption_error_detected = 1; + break; + case ENCRYPTION_ENABLED: + l_set_encryption = true; + break; + case ENCRYPTION_DISABLED: + l_clr_encryption = true; + break; + case ERASE_VERIFY_STARTED: + l_sev_started = true; + break; + case ERASE_VERIFY_COMPLETED: + l_sev_completed = true; + break; + case SEND_NV_STATUS: + // no action, just send status + break; + } + + // Set the attribute and send it to the FSP if needed + l_nvdimm->setAttr<ATTR_NVDIMM_ARMED>(l_armed_state); + if( l_armed_change ) + { + send_ATTR_NVDIMM_ARMED( l_nvdimm, l_armed_state ); + } + + // Get the nv status flag attr and update it + ATTR_NV_STATUS_FLAG_type l_nv_status = + l_nvdimm->getAttr<ATTR_NV_STATUS_FLAG>(); + + // Clear bit 0 if protected nv state + if (l_armed_state.armed && + l_armed_state.occ_active && + !l_armed_state.fatal_error_detected) + { + l_nv_status &= NV_STATUS_UNPROTECTED_CLR; + } + + // Set bit 0 if unprotected nv state + else + { + l_nv_status |= NV_STATUS_UNPROTECTED_SET; + } + + // Set bit 4 if encryption enabled + if (l_set_encryption) + { + l_nv_status |= NV_STATUS_ENCRYPTION_SET; + } + + // Clear bit 4 if encryption disabled + if (l_clr_encryption) + { + l_nv_status &= NV_STATUS_ENCRYPTION_CLR; + } + + // Clear bit 5 if secure erase verify started + if (l_sev_started) + { + l_nv_status &= NV_STATUS_ERASE_VERIFY_CLR; + } + + // Set bit 5 if secure erase verify comlpleted + if (l_sev_completed) + { + l_nv_status |= NV_STATUS_ERASE_VERIFY_SET; + } + + // Set bit 6 if risky error + if (l_armed_state.risky_error_detected) + { + l_nv_status |= NV_STATUS_POSSIBLY_UNPROTECTED_SET; + } + + l_nvdimm->setAttr<ATTR_NV_STATUS_FLAG>(l_nv_status); + + } // for nvdimm list + + // Generate combined nvdimm status for the proc + // Bit 2 of NV_STATUS_FLAG is 'Device contents are persisted' + // and must be ANDed for all nvdimms + // the rest of the bits are ORed for all nvdimms + ATTR_NV_STATUS_FLAG_type l_combined_or = 0x00; + ATTR_NV_STATUS_FLAG_type l_combined_and = 0xFF; + ATTR_NV_STATUS_FLAG_type l_combined_status = 0x00; + l_nvdimmTargetList = getProcNVDIMMs(l_proc); + for (auto const l_nvdimm : l_nvdimmTargetList) + { + l_combined_or |= l_nvdimm->getAttr<ATTR_NV_STATUS_FLAG>(); + l_combined_and &= l_nvdimm->getAttr<ATTR_NV_STATUS_FLAG>(); + } + + // Bit 2 of NV_STATUS_FLAG is 'Device contents are persisted' + l_combined_status = + (l_combined_or & NV_STATUS_OR_MASK) | + (l_combined_and & NV_STATUS_AND_MASK); + + TRACFCOMP( g_trac_nvdimm, + "notifyNvdimmProtectionChange: NV_STATUS for proc %X 0x%.02X", + get_huid(l_proc), l_combined_status); + +#ifdef __HOSTBOOT_RUNTIME + + // Send combined status notification + // Get the Proc Chip Id + TARGETING::rtChipId_t l_chipId = 0; + + l_err = TARGETING::getRtTarget(l_proc, l_chipId); + if(l_err) + { + TRACFCOMP( g_trac_nvdimm, + ERR_MRK"notifyNvdimmProtectionChange: getRtTarget ERROR" ); + break; + } + + // Check for valid interface + if ((nullptr == g_hostInterfaces) || + (nullptr == g_hostInterfaces->firmware_request)) + { + TRACFCOMP( g_trac_nvdimm, ERR_MRK"notifyNvdimmProtectionChange: " + "Hypervisor firmware_request interface not linked"); + + /*@ + * @errortype + * @severity ERRL_SEV_PREDICTIVE + * @moduleid NOTIFY_NVDIMM_PROTECTION_CHG + * @reasoncode NVDIMM_NULL_FIRMWARE_REQUEST_PTR + * @userdata1 HUID of processor target + * @userdata2[0:31] NV_STATUS to PHYP + * @userdata2[32:63] In state change + * @devdesc Unable to inform PHYP of NVDIMM protection + * @custdesc Internal firmware error + */ + l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, + NOTIFY_NVDIMM_PROTECTION_CHG, + NVDIMM_NULL_FIRMWARE_REQUEST_PTR, + get_huid(l_proc), + TWO_UINT32_TO_UINT64( + l_combined_status, + i_state) + ); + + l_err->addProcedureCallout(HWAS::EPUB_PRC_PHYP_CODE, + HWAS::SRCI_PRIORITY_HIGH); + + break; + } + + TRACFCOMP( g_trac_nvdimm, + "notifyNvdimmProtectionChange: 0x%.8X " + "NV_STATUS to HYP: 0x%02X", + get_huid(l_proc), + l_combined_status ); + + // Create the firmware_request request struct to send data + hostInterfaces::hbrt_fw_msg l_req_fw_msg; + memset(&l_req_fw_msg, 0, sizeof(l_req_fw_msg)); // clear it all + + // actual msg size (one type of hbrt_fw_msg) + uint64_t l_req_fw_msg_size = hostInterfaces::HBRT_FW_MSG_BASE_SIZE + + sizeof(l_req_fw_msg.nvdimm_protection_state); + + // Populate the firmware_request request struct with given data + l_req_fw_msg.io_type = + hostInterfaces::HBRT_FW_MSG_TYPE_NVDIMM_PROTECTION; + l_req_fw_msg.nvdimm_protection_state.i_procId = l_chipId; + l_req_fw_msg.nvdimm_protection_state.i_state = l_combined_status; + + // Create the firmware_request response struct to receive data + hostInterfaces::hbrt_fw_msg l_resp_fw_msg; + uint64_t l_resp_fw_msg_size = sizeof(l_resp_fw_msg); + memset(&l_resp_fw_msg, 0, l_resp_fw_msg_size); + + // Make the firmware_request call + l_err = firmware_request_helper(l_req_fw_msg_size, + &l_req_fw_msg, + &l_resp_fw_msg_size, + &l_resp_fw_msg); +#endif + + } while (0); + + TRACFCOMP( g_trac_nvdimm, + EXIT_MRK "notifyNvdimmProtectionChange(%.8X, %d) - ERRL %.8X:%.4X", + get_huid(i_target), i_state, + ERRL_GETEID_SAFE(l_err), ERRL_GETRC_SAFE(l_err) ); + + return l_err; +} + + +/* + * @brief Get operational unit operation timeout + */ +errlHndl_t getOperOpsTimeout(TARGETING::Target* i_nvdimm, + uint16_t& o_timeout) +{ + errlHndl_t l_err = nullptr; + + do + { + // Get timeout lsb + uint8_t l_lsb = 0; + l_err = nvdimmReadReg(i_nvdimm, + OPERATIONAL_UNIT_OPS_TIMEOUT0, + l_lsb); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK + "getOperOpsTimeout() nvdimm[%X] error reading 0x%X", + get_huid(i_nvdimm), OPERATIONAL_UNIT_OPS_TIMEOUT0); + break; + } + + // Get timeout msb + uint8_t l_msb = 0; + l_err = nvdimmReadReg(i_nvdimm, + OPERATIONAL_UNIT_OPS_TIMEOUT1, + l_msb); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK + "getOperOpsTimeout() nvdimm[%X] error reading 0x%X", + get_huid(i_nvdimm), OPERATIONAL_UNIT_OPS_TIMEOUT1); + break; + } + + // Bit 7 of the MSB indicates whether the time should + // be interpreted in seconds or milliseconds + // 0 = millisecond + // 1 = second + if (l_msb < MSBIT_SET_MASK) + { + o_timeout = l_msb; + o_timeout <<= 8; + o_timeout += l_lsb; + o_timeout = o_timeout / MS_PER_SEC; + } + else + { + l_msb = l_msb & MSBIT_CLR_MASK; + o_timeout = l_msb; + o_timeout <<= 8; + o_timeout += l_lsb; + } + + } while(0); + + return l_err; +} + + +/* + * @brief Wait for operational unit operation to complete + */ +errlHndl_t waitOperOpsComplete(TARGETING::Target* i_nvdimm, uint8_t i_cmd) +{ + errlHndl_t l_err = nullptr; + bool l_complete = false; + uint16_t l_timeout = 0; + uint8_t l_status = 0; + + // Get the timeout + l_err = getOperOpsTimeout(i_nvdimm, l_timeout); + + do + { + // Exit if l_timeout invalid + if (l_err) + { + break; + } + + // Delay before reading status + nanosleep( OPERATION_SLEEP_SECONDS, 0 ); + if (OPERATION_SLEEP_SECONDS > l_timeout) + { + l_timeout = 0; + } + else + { + l_timeout = l_timeout - OPERATION_SLEEP_SECONDS; + } + + // Get timeout cmd status 1 + l_err = nvdimmReadReg(i_nvdimm, + NVDIMM_CMD_STATUS1, + l_status); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK + "waitOperOpsComplete() nvdimm[%X] error reading 0x%X", + get_huid(i_nvdimm), NVDIMM_CMD_STATUS1); + break; + } + + if (l_status >= 0x01) + { + // If bit 1 is set that means the command is in progress + // Wait for it to become 0 + } + else + { + l_complete = true; + break; + } + + } while(l_timeout > 0); + + // Timed out + if (!l_err && (l_complete == false) ) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK + "waitOperOpsComplete() nvdimm[%X] " + "Timeout waiting for operation 0x%X to complete, " + "NVDIMM_CMD_STATUS1 0x%X", + get_huid(i_nvdimm), i_cmd, l_status); + + // Get the timeout value again + getOperOpsTimeout(i_nvdimm, l_timeout); + + /*@ + *@errortype + *@reasoncode NVDIMM_VENDOR_LOG_TIMEOUT + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_WAIT_OPER_OPS_COMPLETE + *@userdata1[0:31] NVDIMM HUID + *@userdata1[32:63] OPERATIONAL_UNIT_OPS_CMD + *@userdata2[0:31] NVDIMM_CMD_STATUS1 + *@userdata2[32:63] OPERATIONAL_UNIT_OPS_TIMEOUT + *@devdesc NVDIMM timeout reading vendor log + *@custdesc NVDIMM logging error + */ + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_WAIT_OPER_OPS_COMPLETE, + NVDIMM_VENDOR_LOG_TIMEOUT, + TWO_UINT32_TO_UINT64( + get_huid(i_nvdimm), + i_cmd + ), + TWO_UINT32_TO_UINT64( + l_status, + l_timeout + ), + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + + l_err->collectTrace(NVDIMM_COMP_NAME); + l_err->addPartCallout( i_nvdimm, + HWAS::NV_CONTROLLER_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + } + + return l_err; +} + + +/* + * @brief Get the vendor log unit + */ +errlHndl_t getLogPerUnit(TARGETING::Target* i_nvdimm, + uint16_t i_unitId, + std::vector<uint8_t>& o_unitData) +{ + // 3a) write OPERATIONAL_UNIT_ID0 and OPERATIONAL_UNIT_ID1 with unit_id + // 3b) set OPERATIONAL_UNIT_OPS_CMD to GET_OPERATIONAL_UNIT + // 3c) wait for NVDIMM_CMD_STATUS1 to return 0 + // 3d) for (block_id = 0; + // block_id < VENDOR_LOG_UNIT_SIZE/BLOCKSIZE; + // block_id++) + // 3da) Write block_id to BLOCK_ID + // 3db) Read TYPED_BLOCK_DATA_BYTE0 to TYPED_BLOCK_DATA_BYTE31 + // 3dc) Save data to buffer + + errlHndl_t l_err = nullptr; + + do + { + // 3a) + // Write the unit LSB + l_err = nvdimmWriteReg(i_nvdimm, + OPERATIONAL_UNIT_ID0, + i_unitId & 0x00FF); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK + "getLogPerUnit() nvdimm[%X] error writing reg 0x%X to 0x%X", + get_huid(i_nvdimm), OPERATIONAL_UNIT_ID0, (i_unitId & 0x00FF)); + break; + } + + // Write the unit MSB + l_err = nvdimmWriteReg(i_nvdimm, + OPERATIONAL_UNIT_ID1, + i_unitId >> 8); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK + "getLogPerUnit() nvdimm[%X] error writing reg 0x%X to 0x%X", + get_huid(i_nvdimm), OPERATIONAL_UNIT_ID0, (i_unitId >> 8) ); + break; + } + + // 3b) + // Write the cmd + l_err = nvdimmWriteReg(i_nvdimm, + OPERATIONAL_UNIT_OPS_CMD, + GET_OPERATIONAL_UNIT); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK + "getLogPerUnit() nvdimm[%X] error writing reg 0x%X to 0x%X", + get_huid(i_nvdimm), OPERATIONAL_UNIT_OPS_CMD, + GET_OPERATIONAL_UNIT ); + break; + } + + // 3c + l_err = waitOperOpsComplete(i_nvdimm, GET_OPERATIONAL_UNIT); + if (l_err) + { + break; + } + + // 3d + for (uint8_t l_blockId = 0; + l_blockId < (VENDOR_LOG_UNIT_SIZE / VENDOR_LOG_BLOCK_SIZE); + l_blockId++) + { + // 3da + // Write the block id + l_err = nvdimmWriteReg(i_nvdimm, + BLOCK_ID, + l_blockId); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK + "getLogPerUnit() nvdimm[%X] error writing reg 0x%X to 0x%X", + get_huid(i_nvdimm), BLOCK_ID, l_blockId ); + break; + } + + // 3db + // Read all the block data + for (uint16_t l_byteId = TYPED_BLOCK_DATA_BYTE0; + l_byteId < (TYPED_BLOCK_DATA_BYTE0 + VENDOR_BLOCK_DATA_BYTES); + l_byteId++) + { + uint8_t l_data = 0; + l_err = nvdimmReadReg(i_nvdimm, + l_byteId, + l_data); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK + "getLogPerUnit() nvdimm[%X] error reading 0x%X", + get_huid(i_nvdimm), l_byteId); + break; + } + + // 3dc + o_unitData.push_back(l_data); + } // for byteId + + if (l_err) + { + break; + } + } // for blockId + + } while(0); + + return l_err; +} + + +/* + * @brief Calculate CRC + */ +uint16_t crc16(const uint8_t * i_data, int i_size) +{ + // From JEDEC JESD245B.01 document + // https://www.jedec.org/standards-documents/docs/jesd245a + int i, crc; + crc = 0; + while (--i_size >= 0) + { + crc = crc ^ (int)*i_data++ << 8; + for (i = 0; i < 8; ++i) + { + if (crc & 0x8000) + { + crc = crc << 1 ^ 0x1021; + } + else + { + crc = crc << 1; + } + } + } + return (crc & 0xFFFF); +} + + +/* + * @brief Get operational unit crc + */ +errlHndl_t getOperUnitCrc(TARGETING::Target* i_nvdimm, uint16_t& o_crc) +{ + errlHndl_t l_err = nullptr; + + do + { + // Get crc lsb + uint8_t l_lsb = 0; + l_err = nvdimmReadReg(i_nvdimm, + OPERATIONAL_UNIT_CRC0, + l_lsb); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK + "getOperUnitCrc() nvdimm[%X] error reading 0x%X", + get_huid(i_nvdimm), OPERATIONAL_UNIT_CRC0); + break; + } + + // Get crc msb + uint8_t l_msb = 0; + l_err = nvdimmReadReg(i_nvdimm, + OPERATIONAL_UNIT_CRC1, + l_msb); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK + "getOperUnitCrc() nvdimm[%X] error reading 0x%X", + get_huid(i_nvdimm), OPERATIONAL_UNIT_CRC1); + break; + } + + o_crc = l_msb; + o_crc <<= 8; + o_crc += l_lsb; + + } while(0); + + return l_err; +} + + +/* + * @brief Compare host and nvdimm checksum + */ +errlHndl_t compareCksum(TARGETING::Target* i_nvdimm, + std::vector<uint8_t>& i_unitData) +{ + // 3e) Compare checksum for unit retrieved + // 3ea) Write GENERATE_OPERATIONAL_UNIT_CKSUM + // to OPERATIONAL_UNIT_OPS_CMD + // 3eb) wait for NVDIMM_CMD_STATUS1 to return 0 + // 3ec) Read OPERATIONAL_UNIT_CRC1(MSB) and OPERATIONAL_UNIT_CRC0(LSB) + // 3ed) Calculate host checksum + // 3ee) return true if 3ec) == 3ed) + + errlHndl_t l_err = nullptr; + + do + { + // 3ea) + // Command the nvdimm to calculate the CRC on the unit + l_err = nvdimmWriteReg(i_nvdimm, + OPERATIONAL_UNIT_OPS_CMD, + GENERATE_OPERATIONAL_UNIT_CKSUM); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK + "compareCksum() nvdimm[%X] error writing reg 0x%X to 0x%X", + get_huid(i_nvdimm), OPERATIONAL_UNIT_OPS_CMD, + GENERATE_OPERATIONAL_UNIT_CKSUM ); + break; + } + + // 3eb) + // Wait for the command to finish + l_err = waitOperOpsComplete(i_nvdimm, + GENERATE_OPERATIONAL_UNIT_CKSUM); + if (l_err) + { + break; + } + + // 3ec) + // Read the HW CRC MSB + LSB + uint16_t l_nvdimmCrc = 0; + l_err = getOperUnitCrc(i_nvdimm, l_nvdimmCrc); + if (l_err) + { + break; + } + + // 3ed) + // Calculate the host checksum + uint8_t* l_hostData = reinterpret_cast<uint8_t*>(i_unitData.data()); + uint16_t l_hostCrc = crc16(l_hostData, i_unitData.size()); + + // 3ee) + if (l_hostCrc != l_nvdimmCrc) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK + "compareCksum() nvdimm[%X] compare cksum failed " + "hostCrc 0x%X nvdimmCrc 0x%X", + get_huid(i_nvdimm), l_hostCrc, l_nvdimmCrc); + /*@ + *@errortype + *@reasoncode NVDIMM_VENDOR_LOG_CKSUM_FAILED + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_COMPARE_CKSUM + *@userdata1 NVDIMM HUID + *@userdata2[0:31] HOST CRC + *@userdata2[32:63] NVDIMM CRC + *@devdesc NVDIMM vendor log checksum failed + *@custdesc NVDIMM logging error + */ + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_COMPARE_CKSUM, + NVDIMM_VENDOR_LOG_CKSUM_FAILED, + get_huid(i_nvdimm), + TWO_UINT32_TO_UINT64( + l_hostCrc, + l_nvdimmCrc), + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + + l_err->collectTrace(NVDIMM_COMP_NAME); + l_err->addPartCallout( i_nvdimm, + HWAS::NV_CONTROLLER_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + } + + } while(0); + + return l_err; +} + + +/* + * @brief Add vendor log data to FFDC + * Added to all NVDIMM HW errors + */ +void nvdimmAddVendorLog( TARGETING::Target* i_nvdimm, errlHndl_t& io_err ) +{ + TRACFCOMP( g_trac_nvdimm, ENTER_MRK + "nvdimmAddVendorLog: Target huid 0x%.8X", + get_huid(i_nvdimm)); + + /* + 1) Read VENDOR_LOG_PAGE_SIZE. Multiply the return value with BLOCKSIZE + to get the total page size (LOG_PAGE_SIZE) + 2) Set TYPED_BLOCK_DATA to VENDOR_DATA_TYPE + 3) for (unit_id = 0; + unit_id < LOG_PAGE_LENGTH/VENDOR_LOG_UNIT_SIZE; + unit_id++) + 3a) write OPERATIONAL_UNIT_ID0 and OPERATIONAL_UNIT_ID1 with unit_id + 3b) set OPERATIONAL_UNIT_OPS_CMD to GET_OPERATIONAL_UNIT + 3c) wait for NVDIMM_CMD_STATUS1 to return 0 + 3d) for (block_id = 0; + block_id < VENDOR_LOG_UNIT_SIZE/BLOCKSIZE; + block_id++) + 3da) Write block_id to BLOCK_ID + 3db) Read TYPED_BLOCK_DATA_BYTE0 to TYPED_BLOCK_DATA_BYTE31 + 3dc) Save data to buffer + 3e) Compare checksum for unit retrieved + 3ea) Write GENERATE_OPERATIONAL_UNIT_CKSUM + to OPERATIONAL_UNIT_OPS_CMD + 3eb) wait for NVDIMM_CMD_STATUS1 to return 0 + 3ec) Read OPERATIONAL_UNIT_CRC1(MSB) and OPERATIONAL_UNIT_CRC0(LSB) + 3ed) Calculate host checksum + 3ee) return true if 3ec) == 3ed) + */ + + errlHndl_t l_err = nullptr; + + // Get the vendor log attribute + auto l_vendorLog = i_nvdimm->getAttr<ATTR_NVDIMM_READING_VENDOR_LOG>(); + + do + { + // If attr is set we are already in the process of + // reading the vendor log, exit + if (l_vendorLog) + { + break; + } + + if (io_err == nullptr) + { + // A nullptr was given when it should not have been. Emit a trace + // and break out of this function. + TRACFCOMP(g_trac_nvdimm, ERR_MRK + "nvdimmAddVendorLog() io_err was nullptr!! Skip adding additional FFDC."); + break; + } + + + // Set the vendor log attribute so we don't recursively + // execute the nvdimmAddVendorLog function + l_vendorLog = 0x1; + i_nvdimm->setAttr<ATTR_NVDIMM_READING_VENDOR_LOG>(l_vendorLog); + + uint8_t l_readData = 0; + std::vector<uint8_t> l_fullData; + + // Step 1 + l_err = nvdimmReadReg(i_nvdimm, + VENDOR_LOG_PAGE_SIZE, + l_readData); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK + "nvdimmAddVendorLog() nvdimm[%X] error reading 0x%X", + get_huid(i_nvdimm), VENDOR_LOG_PAGE_SIZE); + break; + } + + size_t l_logPgeLength = l_readData * VENDOR_LOG_BLOCK_SIZE; + + // Step 2 + // Some weird bug here - switching directly to VENDOR_DATA_TYPE + // would not work. Need to switch to something else first + l_err = nvdimmWriteReg(i_nvdimm, + TYPED_BLOCK_DATA, + FIRMWARE_IMAGE_DATA); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK + "nvdimmAddVendorLog() nvdimm[%X] error writing 0x%X to 0x%X", + get_huid(i_nvdimm),TYPED_BLOCK_DATA, FIRMWARE_IMAGE_DATA ); + break; + } + + l_err = nvdimmWriteReg(i_nvdimm, + TYPED_BLOCK_DATA, + VENDOR_DATA_TYPE); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK + "nvdimmAddVendorLog() nvdimm[%X] error writing 0x%X to 0x%X", + get_huid(i_nvdimm),TYPED_BLOCK_DATA, VENDOR_DATA_TYPE ); + break; + } + + // Step 3 + // Loop through all the log units. + for (uint16_t l_unitId = 0; + l_unitId < (l_logPgeLength / VENDOR_LOG_UNIT_SIZE); + l_unitId++) + { + // Step 3a) - 3dc) + // Get one log unit + std::vector<uint8_t> l_unitData; + l_err = getLogPerUnit(i_nvdimm, l_unitId, l_unitData); + if (l_err) + { + break; + } + + // Step 3e) - 3ee) + // Check the checksum for the entire log unit + l_err = compareCksum(i_nvdimm, l_unitData); + if (l_err) + { + break; + } + + // Append to full data + l_fullData.insert(l_fullData.end(), + l_unitData.begin(), + l_unitData.end()); + } + + if (l_err) + { + break; + } + + // Find first NUL char in the vendor log data + bool l_foundNull = false; + uint32_t l_idx = 0; + for (l_idx = 0; l_idx < l_fullData.size(); l_idx++) + { + if (l_fullData[l_idx] == 0x00) + { + l_foundNull = true; + break; + } + } + + // If NULL char not found + // then this is the old log format + if (l_foundNull == false) + { + // Add NUL terminator to ascii data + l_fullData.push_back(0x00); + } + // Else new log format + else + { + // If the next char is not NULL + // then the log has wrapped + // Re-arrange the data in chronological order + if (l_fullData[l_idx + 1] != 0x00) + { + // Save the data after the NULL char + // This is the start of the log + std::vector<uint8_t> l_tmpData; + l_tmpData.insert(l_tmpData.begin(), + l_fullData.begin() + l_idx + 1, + l_fullData.end()); + + // Erase this data from the vector + l_fullData.erase(l_fullData.begin() + l_idx + 1, + l_fullData.end()); + + // Place the saved data at the front + l_fullData.insert(l_fullData.begin(), + l_tmpData.begin(), + l_tmpData.end()); + } + // Else log has not wrapped + else + { + // Erase the data at the end of the vector + l_fullData.erase(l_fullData.begin() + l_idx + 1, + l_fullData.end()); + } + } + + // Add vendor data to error log as string + const char* l_fullChar = reinterpret_cast<char*>(l_fullData.data()); + ERRORLOG::ErrlUserDetailsStringSet l_stringSet; + l_stringSet.add("Vendor Log", l_fullChar); + l_stringSet.addToLog(io_err); + + // Change back to default + l_err = nvdimmWriteReg(i_nvdimm, + TYPED_BLOCK_DATA, + VENDOR_DEFAULT); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK + "nvdimmAddVendorLog() nvdimm[%X] error writing 0x%X to 0x%X", + get_huid(i_nvdimm),TYPED_BLOCK_DATA, VENDOR_DEFAULT ); + break; + } + + } while(0); + + if (l_err) + { + // FFDC error, set as informational + l_err->setSev(ERRORLOG::ERRL_SEV_INFORMATIONAL); + errlCommit( l_err, NVDIMM_COMP_ID ); + } + + // Clear the vendor log attribute before exiting + l_vendorLog = 0x0; + i_nvdimm->setAttr<ATTR_NVDIMM_READING_VENDOR_LOG>(l_vendorLog); + + TRACFCOMP( g_trac_nvdimm, EXIT_MRK + "nvdimmAddVendorLog: Target huid 0x%.8X", + get_huid(i_nvdimm)); +} + + +/* + * @brief Add NVDIMM Update regs to FFDC for errors encountered + * during NVDIMM update process + */ +void nvdimmAddUpdateRegs( TARGETING::Target* i_nvdimm, errlHndl_t& io_err ) +{ + errlHndl_t l_err = nullptr; + + do { + + if (io_err == nullptr) + { + // A nullptr was given when it should not have been. Emit a trace + // and break out of this function. + TRACFCOMP(g_trac_nvdimm, ERR_MRK + "nvdimmAddUpdateRegs() io_err was nullptr!! Skip adding additional FFDC."); + break; + } + + ERRORLOG::ErrlUserDetailsLogRegister l_regUD(i_nvdimm); + const uint32_t l_regList[] = { + NVDIMM_READY, + FIRMWARE_OPS_STATUS, + NVDIMM_CMD_STATUS0, + FIRMWARE_OPS_TIMEOUT0, + FIRMWARE_OPS_TIMEOUT1, + FW_REGION_CRC0, + FW_REGION_CRC1, + MODULE_HEALTH, + MODULE_HEALTH_STATUS0, + MODULE_HEALTH_STATUS1, + ERROR_THRESHOLD_STATUS, + ENCRYPTION_CONFIG_STATUS, + FW_SLOT_INFO, + SLOT0_ES_FWREV0, + SLOT0_ES_FWREV1, + SLOT1_ES_FWREV0, + SLOT1_ES_FWREV1, + SLOT1_SUBFWREV, + CSAVE_INFO, + CSAVE_FAIL_INFO1, + RESTORE_STATUS, + RESTORE_FAIL_INFO, + }; + uint8_t l_readData = 0; + + for (auto l_reg : l_regList) + { + l_err = nvdimmReadReg(i_nvdimm, + l_reg, + l_readData); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK + "nvdimmAddUpdateRegs() nvdimm[%X] error reading 0x%X", + get_huid(i_nvdimm), l_reg); + + // Don't commit, just delete the error and continue + delete l_err; + l_err = nullptr; + continue; + } + + l_regUD.addDataBuffer(&l_readData, + sizeof(l_readData), + DEVICE_NVDIMM_ADDRESS(l_reg)); + } + + l_regUD.addToLog(io_err); + + } while(0); +} + + +/* + * @brief Add Page 4 regs to FFDC + * Added to all NVDIMM HW errors + */ +void nvdimmAddPage4Regs( TARGETING::Target* i_nvdimm, errlHndl_t& io_err ) +{ + errlHndl_t l_err = nullptr; + + do + { + if (io_err == nullptr) + { + // A nullptr was given when it should not have been. Emit a trace + // and break out of this function. + TRACFCOMP(g_trac_nvdimm, ERR_MRK + "nvdimmAddPage4Regs() io_err was nullptr!! Skip adding additional FFDC."); + break; + } + + + // Get the page4 attribute, if set we are already + // reading the page4 regs, exit + auto l_page4 = i_nvdimm->getAttr<ATTR_NVDIMM_READING_PAGE4>(); + if (l_page4) + { + break; + } + + // Set the page4 attribute so we don't recursively + // execute the nvdimmAddPage4Regs function + l_page4 = 0x1; + i_nvdimm->setAttr<ATTR_NVDIMM_READING_PAGE4>(l_page4); + + ERRORLOG::ErrlUserDetailsLogRegister l_regUD(i_nvdimm); + uint32_t l_regList[] = { + PANIC_CNT, + PARITY_ERROR_COUNT, + FLASH_ERROR_COUNT0, + FLASH_ERROR_COUNT1, + FLASH_ERROR_COUNT2, + FLASH_BAD_BLOCK_COUNT0, + FLASH_BAD_BLOCK_COUNT1, + SCAP_STATUS, + STATUS_EVENT_INT_INFO1, + STATUS_EVENT_INT_INFO2 + }; + uint8_t l_readData = 0; + + for (auto l_reg : l_regList) + { + l_err = nvdimmReadReg(i_nvdimm, + l_reg, + l_readData); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK + "nvdimmAddPage4Regs() nvdimm[%X] error reading 0x%X", + get_huid(i_nvdimm), l_reg); + + // Don't commit, just delete the error and continue + delete l_err; + l_err = nullptr; + continue; + } + + l_regUD.addDataBuffer(&l_readData, + sizeof(l_readData), + DEVICE_NVDIMM_ADDRESS(l_reg)); + } + + l_regUD.addToLog(io_err); + + // Clear the page4 attribute before exiting + l_page4 = 0x0; + i_nvdimm->setAttr<ATTR_NVDIMM_READING_PAGE4>(l_page4); + + } while(0); +} + +/* + * @brief Utility function to send the value of + * ATTR_NVDIMM_ARMED to the FSP + */ +void send_ATTR_NVDIMM_ARMED( Target* i_nvdimm, + ATTR_NVDIMM_ARMED_type& i_val ) +{ +#ifdef __HOSTBOOT_RUNTIME + errlHndl_t l_err = nullptr; + + // Send attr to HWSV if at runtime + AttributeTank::Attribute l_attr = {}; + if( !makeAttribute<ATTR_NVDIMM_ARMED> + (i_nvdimm, l_attr) ) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"send_ATTR_NVDIMM_ARMED() Could not create Attribute"); + /*@ + *@errortype + *@reasoncode NVDIMM_CANNOT_MAKE_ATTRIBUTE + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid SEND_ATTR_NVDIMM_ARMED + *@devdesc Couldn't create an Attribute to send the data + * to the FSP + *@custdesc NVDIMM encryption error + */ + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_PREDICTIVE, + SEND_ATTR_NVDIMM_ARMED, + NVDIMM_CANNOT_MAKE_ATTRIBUTE, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT ); + l_err->collectTrace(NVDIMM_COMP_NAME); + errlCommit( l_err, NVDIMM_COMP_ID ); + } + else + { + std::vector<TARGETING::AttributeTank::Attribute> l_attrList; + l_attrList.push_back(l_attr); + l_err = sendAttributes( l_attrList ); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"send_ATTR_NVDIMM_ARMED() Error sending ATTR_NVDIMM_ARMED down to FSP"); + l_err->setSev(ERRORLOG::ERRL_SEV_PREDICTIVE); + l_err->collectTrace(NVDIMM_COMP_NAME); + errlCommit( l_err, NVDIMM_COMP_ID ); + } + } +#endif //__HOSTBOOT_RUNTIME +} + +/** + * @brief Grab the current slot that NVDIMM code is running + */ +errlHndl_t nvdimmGetRunningSlot(TARGETING::Target *i_nvdimm, uint8_t & o_slot) +{ + errlHndl_t l_err = nullptr; + uint8_t l_data = 0; + o_slot = 0; //default to slot 0 + + // Check if the firmware slot is 0 + l_err = nvdimmReadReg ( i_nvdimm, FW_SLOT_INFO, l_data); + if (l_err) + { + nvdimmSetStatusFlag(i_nvdimm, NSTD_ERR); + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmGetRunningSlot() nvdimm[%X], failed to read slot info", + get_huid(i_nvdimm)); + } + else + { + // Bits 7-4 = RUNNING_FW_SLOT - slot number of running firmware + o_slot = (l_data & RUNNING_FW_SLOT) >> 4; + } + return l_err; +} + +/** + * @brief This function polls the command status register for arm completion + * + * @param[in] i_nvdimm - nvdimm target with NV controller + * + * @param[out] o_poll - total polled time in ms + * + * @return errlHndl_t - Null if successful, otherwise a pointer to + * the error log. + */ +errlHndl_t nvdimmPollArmDone(Target* i_nvdimm, + uint32_t &o_poll) +{ + TRACUCOMP(g_trac_nvdimm, ENTER_MRK"nvdimmPollArmDone() nvdimm[%X]", get_huid(i_nvdimm) ); + + errlHndl_t l_err = nullptr; + + l_err = nvdimmPollStatus ( i_nvdimm, ARM, o_poll); + + TRACUCOMP(g_trac_nvdimm, EXIT_MRK"nvdimmPollArmDone() nvdimm[%X]", + get_huid(i_nvdimm)); + + return l_err; +} + +/** + * @brief This function checks the arm status register to make sure + * the trigger has been armed to ddr_reset_n + * + * @param[in] i_nvdimm - nvdimm target with NV controller + * @param[in] i_arm_timeout - nvdimm local timeout status + * + * @return errlHndl_t - Null if successful, otherwise a pointer to + * the error log. + */ +errlHndl_t nvdimmCheckArmSuccess(Target *i_nvdimm, bool i_arm_timeout) +{ + TRACUCOMP(g_trac_nvdimm, ENTER_MRK"nvdimmCheckArmSuccess() nvdimm[%X]", + get_huid(i_nvdimm)); + + errlHndl_t l_err = nullptr; + uint8_t l_data = 0; + + l_err = nvdimmReadReg(i_nvdimm, ARM_STATUS, l_data); + + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmCheckArmSuccess() nvdimm[%X]" + "failed to read arm status reg!",get_huid(i_nvdimm)); + } + else if (((l_data & ARM_ERROR) == ARM_ERROR) || ((l_data & RESET_N_ARMED) != RESET_N_ARMED) || i_arm_timeout) + { + + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmCheckArmSuccess() nvdimm[%X]" + "failed to arm! ARM status 0x%X ARM timeout %d" + ,get_huid(i_nvdimm),l_data,i_arm_timeout); + /*@ + *@errortype + *@reasoncode NVDIMM_ARM_FAILED + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_SET_ARM + *@userdata1[0:31] Related ops (0xff = NA) + *@userdata1[32:63] Target Huid + *@userdata2[0:31] ARM Status + *@userdata2[32:63] ARM Timeout + *@devdesc Encountered error arming the catastrophic save + * trigger on NVDIMM. Make sure an energy source + * is connected to the NVDIMM and the ES policy + * is set properly + *@custdesc NVDIMM encountered error arming save trigger + */ + l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_SET_ARM, + NVDIMM_ARM_FAILED, + TWO_UINT32_TO_UINT64(ARM, get_huid(i_nvdimm)), + TWO_UINT32_TO_UINT64(l_data, i_arm_timeout), + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + + l_err->collectTrace(NVDIMM_COMP_NAME, 256 ); + nvdimmAddVendorLog(i_nvdimm, l_err); + + // Failure to arm could mean internal NV controller error or + // even error on the battery pack. NVDIMM will lose persistency + // if failed to arm trigger + l_err->addHwCallout( i_nvdimm, + HWAS::SRCI_PRIORITY_HIGH, + HWAS::NO_DECONFIG, + HWAS::GARD_Fatal); + } + + TRACUCOMP(g_trac_nvdimm, EXIT_MRK"nvdimmCheckArmSuccess() nvdimm[%X] ret[%X]", + get_huid(i_nvdimm), l_data); + + return l_err; +} + +/** + * @brief This function performs arm precheck. + * + * @param[in] i_nvdimm - nvdimm target with NV controller + * + * @return errlHndl_t - Null if successful, otherwise a pointer to + * the error log. + */ +errlHndl_t nvdimmArmPreCheck(Target* i_nvdimm) +{ + TRACUCOMP(g_trac_nvdimm, ENTER_MRK"nvdimmArmPreCheck() nvdimm[%X]", + get_huid(i_nvdimm)); + + errlHndl_t l_err = nullptr; + uint8_t l_ready = 0; + uint8_t l_fwupdate = 0; + uint8_t l_module_health = 0; + uint8_t l_continue = true; + auto l_RegInfo = nvdimm_reg_t(); + + do + { + // Read out the Module Health status register + l_err = nvdimmReadReg(i_nvdimm, MODULE_HEALTH_STATUS0, l_module_health); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmArmPreCheck() nvdimm[%X] - failed to read Module Health Status", + get_huid(i_nvdimm)); + errlCommit( l_err, NVDIMM_COMP_ID ); + l_continue = false; + break; + } + + // Read out the NVDimm Ready register + l_err = nvdimmReadReg(i_nvdimm, NVDIMM_READY, l_ready); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmArmPreCheck() nvdimm[%X] - failed to read NVDimm Ready register", + get_huid(i_nvdimm)); + errlCommit( l_err, NVDIMM_COMP_ID ); + l_continue = false; + break; + } + + // Read out the FW OPs Status register + l_err = nvdimmReadReg(i_nvdimm, FIRMWARE_OPS_STATUS, l_fwupdate); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmArmPreCheck() nvdimm[%X] - failed to read Firmware OPs Status register", + get_huid(i_nvdimm)); + errlCommit( l_err, NVDIMM_COMP_ID ); + l_continue = false; + } + + }while(0); + + // Check ARM pre-requisites + // All nvdimms in i_nvdimmTargetList must pass the pre-req checks + // before continuing with arm. + if ((!l_continue) || (l_module_health & NVM_LIFETIME_ERROR) + || (l_ready != NV_READY) + || (l_fwupdate & FW_OPS_UPDATE)) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmArmPreCheck() nvdimm[%X] - failed NVDimm Arm prechecks", + get_huid(i_nvdimm)); + /*@ + *@errortype + *@reasoncode NVDIMM_ARM_PRE_CHECK_FAILED + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_ARM_PRE_CHECK + *@userdata1[0:31] Target Huid + *@userdata1[32:39] l_continue + *@userdata1[40:47] l_module_health + *@userdata1[48:56] l_ready + *@userdata1[57:63] l_fwupdate + *@userdata2 <UNUSED> + *@devdesc NVDIMM failed arm precheck. Refer to FFDC for exact reason + *@custdesc NVDIMM failed the arm precheck and is unable to arm + */ + l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_ARM_PRE_CHECK, + NVDIMM_ARM_PRE_CHECK_FAILED, + NVDIMM_SET_USER_DATA_1(TARGETING::get_huid(i_nvdimm), + FOUR_UINT8_TO_UINT32(l_continue, l_module_health, l_ready, l_fwupdate)), + 0x0, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + + l_err->collectTrace( NVDIMM_COMP_NAME ); + + // Callout the dimm + l_err->addHwCallout( i_nvdimm, + HWAS::SRCI_PRIORITY_LOW, + HWAS::NO_DECONFIG, + HWAS::GARD_NULL); + + // Read relevant regs for trace data + nvdimmTraceRegs(i_nvdimm, l_RegInfo); + nvdimmAddPage4Regs(i_nvdimm,l_err); + nvdimmAddVendorLog(i_nvdimm, l_err); + + // Add reg traces to the error log + NVDIMM::UdNvdimmOPParms( l_RegInfo ).addToLog(l_err); + + } + + TRACUCOMP(g_trac_nvdimm, EXIT_MRK"nvdimmArmPreCheck() nvdimm[%X]", + get_huid(i_nvdimm)); + + return l_err; +} + + +bool nvdimmArm(TargetHandleList &i_nvdimmTargetList) +{ + bool o_arm_successful = true; + bool l_continue = true; + bool l_arm_timeout = false; + uint8_t l_data; + auto l_RegInfo = nvdimm_reg_t(); + uint64_t l_writeData; + uint32_t l_writeAddress; + size_t l_writeSize = sizeof(l_writeData); + + TRACFCOMP(g_trac_nvdimm, ENTER_MRK"nvdimmArm() numNvdimm[%d]", + i_nvdimmTargetList.size()); + + errlHndl_t l_err = nullptr; + errlHndl_t l_err_t = nullptr; + + // Prerequisite Arm Checks + for (auto const l_nvdimm : i_nvdimmTargetList) + { + l_err = nvdimmArmPreCheck(l_nvdimm); + + // If we are failing the precheck, commit the error then exit + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmArm() failed arm precheck, exiting"); + errlCommit(l_err, NVDIMM_COMP_ID); + return false; + } + } + + // Encryption unlocked check + // Check one nvdimm at a time + for (auto const l_nvdimm : i_nvdimmTargetList) + { + // Unlock function will create an error log + // Create another here to make it clear that the arm failed + TargetHandleList l_nvdimmTargetList; + l_nvdimmTargetList.push_back(l_nvdimm); + if (!nvdimm_encrypt_unlock(l_nvdimmTargetList)) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmArm() nvdimm[%X] - failed NVDimm Arm encryption unlock", + get_huid(l_nvdimm)); + /*@ + *@errortype + *@reasoncode NVDIMM_ARM_ENCRYPTION_UNLOCK_FAILED + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_ARM + *@userdata1 Target Huid + *@userdata2 <UNUSED> + *@devdesc NVDIMM failed to unlock encryption during arming + *@custdesc NVDIMM failed to ARM + */ + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_ARM, + NVDIMM_ARM_ENCRYPTION_UNLOCK_FAILED, + get_huid(l_nvdimm), + 0x0, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + + l_err->collectTrace( NVDIMM_COMP_NAME ); + + // Callout the dimm + l_err->addHwCallout( l_nvdimm, + HWAS::SRCI_PRIORITY_MED, + HWAS::DELAYED_DECONFIG, + HWAS::GARD_NULL); + + // Read relevant regs for trace data + nvdimmTraceRegs(l_nvdimm, l_RegInfo); + nvdimmAddPage4Regs(l_nvdimm,l_err); + nvdimmAddVendorLog(l_nvdimm, l_err); + + // Add reg traces to the error log + NVDIMM::UdNvdimmOPParms( l_RegInfo ).addToLog(l_err); + + // Commit the error then exit + errlCommit(l_err, NVDIMM_COMP_ID); + return false; + } + } + + // Mask MBACALFIR EventN to separate ARM handling + for (TargetHandleList::iterator it = i_nvdimmTargetList.begin(); + it != i_nvdimmTargetList.end();) + { + TargetHandleList l_mcaList; + getParentAffinityTargets(l_mcaList, *it, CLASS_UNIT, TYPE_MCA); + assert(l_mcaList.size(), "nvdimmArm() failed to find parent MCA."); + + l_writeAddress = MBACALFIR_OR_MASK_REG; + l_writeData = MBACALFIR_EVENTN_OR_BIT; + l_err = deviceWrite(l_mcaList[0], &l_writeData, l_writeSize, + DEVICE_SCOM_ADDRESS(l_writeAddress)); + if(l_err) + { + TRACFCOMP(g_trac_nvdimm, "SCOM to address 0x%08x failed", + l_writeAddress); + errlCommit( l_err, NVDIMM_COMP_ID ); + } + it++; + } + + for (auto const l_nvdimm : i_nvdimmTargetList) + { + l_arm_timeout = false; + + // skip if the nvdimm is already armed + ATTR_NVDIMM_ARMED_type l_armed_state = {}; + l_armed_state = l_nvdimm->getAttr<ATTR_NVDIMM_ARMED>(); + if (l_armed_state.armed) + { + TRACFCOMP(g_trac_nvdimm, "nvdimmArm() nvdimm[%X] called when already armed", get_huid(l_nvdimm)); + continue; + } + + // Set ES Policy, contains all of its status checks + l_err = nvdimmSetESPolicy(l_nvdimm); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, "nvdimmArm() nvdimm[%X] failed to set ES Policy", get_huid(l_nvdimm)); + o_arm_successful = false; + + nvdimmDisarm(i_nvdimmTargetList); + + // Committing the error as we don't want this to interrupt + // the boot. This will notify the user that action is needed + // on this module + l_err->setSev(ERRORLOG::ERRL_SEV_PREDICTIVE); + l_err->collectTrace(NVDIMM_COMP_NAME); + + // Callout the nvdimm on high and gard + l_err->addHwCallout( l_nvdimm, + HWAS::SRCI_PRIORITY_HIGH, + HWAS::NO_DECONFIG, + HWAS::GARD_Fatal); + + errlCommit( l_err, NVDIMM_COMP_ID ); + + break; + } + + // Clear all status registers in case of leftover bits + l_err = nvdimmWriteReg(l_nvdimm, NVDIMM_MGT_CMD0, CLEAR_ALL_STATUS); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmArm() nvdimm[%X] - error clearing all status registers", + get_huid(l_nvdimm)); + o_arm_successful = false; + break; + } + + bool l_is_retryable = true; + //continue flag set by the retry loop to continue on the outer loop + bool l_continue_arm = false; + //break flag set by the retry loop to break on the outer loop + bool l_break = false; + errlHndl_t l_err_retry = nullptr; + + // Attempt arm multiple times in case of glitches + for (size_t l_retry = 0; l_retry <= ARM_MAX_RETRY_COUNT; l_retry++) + { + + l_err = NVDIMM::nvdimmChangeArmState(l_nvdimm, ARM_TRIGGER); + // If we run into any error here we will just + // commit the error log and move on. Let the + // system continue to boot and let the user + // salvage the data + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, "nvdimmArm() nvdimm[%X] failed to trigger arm", get_huid(l_nvdimm)); + + nvdimmDisarm(i_nvdimmTargetList); + + // Committing the error as we don't want this to interrupt + // the boot. This will notify the user that action is needed + // on this module + l_err->setSev(ERRORLOG::ERRL_SEV_PREDICTIVE); + l_err->collectTrace(NVDIMM_COMP_NAME); + errlCommit( l_err, NVDIMM_COMP_ID ); + o_arm_successful = false; + + // Cause the main loop to skip the rest of the arm procedure + // and move to the next target + l_continue_arm = true; + break; + } + + // Arm happens one module at a time. No need to set any offset on the counter + uint32_t l_poll = 0; + l_err = nvdimmPollArmDone(l_nvdimm, l_poll); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, "nvdimmArm() nvdimm[%X] arm command timed out", get_huid(l_nvdimm)); + l_arm_timeout = true; + + l_err_t = notifyNvdimmProtectionChange(l_nvdimm, NVDIMM_DISARMED); + if (l_err_t) + { + errlCommit( l_err_t, NVDIMM_COMP_ID ); + } + + // Committing the error as we don't want this to interrupt + // the boot. This will notify the user that action is needed + // on this module + l_err->setSev(ERRORLOG::ERRL_SEV_PREDICTIVE); + l_err->collectTrace(NVDIMM_COMP_NAME); + + errlCommit( l_err, NVDIMM_COMP_ID ); + o_arm_successful = false; + } + + // Pass l_arm_timeout value in for health status check + l_continue = l_arm_timeout; + + // Sleep for 1 second before checking the health status + // to let the glitches settle in case there were any + nanosleep(1, 0); + + // Check health status registers and exit if required + l_err = nvdimmHealthStatusCheck( l_nvdimm, HEALTH_PRE_ARM, l_continue ); + + // Check for health status failure + // Any fail picked up by the health check is a legit fail + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, "nvdimmArm() nvdimm[%X] failed first health status check", get_huid(l_nvdimm)); + + // The arm timeout variable is used here as the continue variable for the + // health status check. This was done to include the timeout for use in the check + // If true either the arm timed out with a health status fail or the + // health status check failed with another disarm and exit condition + if (!l_continue) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + + // Disarming all dimms due to error + nvdimmDisarm(i_nvdimmTargetList); + o_arm_successful = false; + + // Cause the main loop to exit out of the main arm procedure + l_break = true; + break; + } + else + { + errlCommit( l_err, NVDIMM_COMP_ID ); + + // Cause the main loop to skip the rest of the arm procedure + // and move to the next target + l_continue_arm = true; + break; + } + } + + l_err = nvdimmCheckArmSuccess(l_nvdimm, l_arm_timeout); + + // At this point we have passed the health check. If the arm were + // to fail now, it is likely it was due to some glitch. Let's retry + // the arm again as long as the fail is not due to timeout. + // A timeout would mean a charging issue, it would have been caught + // by the health check. + l_is_retryable = !l_arm_timeout && l_retry < ARM_MAX_RETRY_COUNT; + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, "nvdimmArm() nvdimm[%X] failed to succesfully arm. %s retryable.", + get_huid(l_nvdimm), l_is_retryable? "IS" : "NOT"); + + if (l_is_retryable) + { + // Save the original error + // If a previous error was saved then delete it + if (l_err_retry) + { + delete l_err_retry; + } + l_err_retry = l_err; + + /*@ + *@errortype + *@reasoncode NVDIMM_ARM_RETRY + *@severity ERRORLOG_SEV_INFORMATIONAL + *@moduleid NVDIMM_ARM_ERASE + *@userdata1[0:31] Target Huid + *@userdata1[32:39] l_is_retryable + *@userdata1[40:47] MAX arm retry count + *@userdata2[0:31] Original errlog plid + *@userdata2[32:63] Original errlog reason code + *@devdesc NVDIMM encountered a glitch causing the initial + * arm to fail. System firmware will retry the arm + *@custdesc NVDIMM requires an arm retry + */ + l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_INFORMATIONAL, + NVDIMM_ARM_ERASE, + NVDIMM_ARM_RETRY, + NVDIMM_SET_USER_DATA_1(TARGETING::get_huid(l_nvdimm), + FOUR_UINT8_TO_UINT32(l_is_retryable, ARM_MAX_RETRY_COUNT,0,0)), + TWO_UINT32_TO_UINT64(l_err_retry->plid(), l_err_retry->reasonCode()), + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + + l_err->collectTrace( NVDIMM_COMP_NAME ); + + // Callout the dimm + l_err->addHwCallout( l_nvdimm, + HWAS::SRCI_PRIORITY_LOW, + HWAS::NO_DECONFIG, + HWAS::GARD_NULL); + + errlCommit( l_err, NVDIMM_COMP_ID ); + } + else + { + // Handle retryable error + if (l_err_retry) + { + ERRORLOG::ErrlUserDetailsString("Arm RETRY failed").addToLog(l_err_retry); + + // Delete the current errlog and use the original errlog for callout + delete l_err; + l_err = l_err_retry; + l_err_retry = nullptr; + } + + // Disarming all dimms due to error + nvdimmDisarm(i_nvdimmTargetList); + + l_err_t = notifyNvdimmProtectionChange(l_nvdimm, NVDIMM_DISARMED); + if (l_err_t) + { + errlCommit( l_err_t, NVDIMM_COMP_ID ); + } + + // Committing the error as we don't want this to interrupt + // the boot. This will notify the user that action is needed + // on this module + l_err->setSev(ERRORLOG::ERRL_SEV_PREDICTIVE); + l_err->collectTrace(NVDIMM_COMP_NAME); + + // Dump Traces for error logs + nvdimmTraceRegs( l_nvdimm, l_RegInfo ); + nvdimmAddPage4Regs(l_nvdimm,l_err); + + // Add reg traces to the error log + NVDIMM::UdNvdimmOPParms( l_RegInfo ).addToLog(l_err); + + errlCommit(l_err, NVDIMM_COMP_ID); + o_arm_successful = false; + + // Cause the main loop to exit out of the main arm procedure + l_break = true; + break; + } + } + else + { + // Arm worked. Exit the retry loop + break; + } // close nvdimmCheckArmSuccess check + } // close arm retry loop + + if (l_continue_arm) + { + continue; + } + else if (l_break) + { + break; + } + + // After arming the trigger, erase the image to prevent the possible + // stale image getting the restored on the next boot in case of failed + // save. + l_err = nvdimmEraseNF(l_nvdimm); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, "nvdimmArm() nvdimm[%X] failed to erase post arm", get_huid(l_nvdimm)); + + // Disarming all dimms due to error + nvdimmDisarm(i_nvdimmTargetList); + + // Committing the error as we don't want this to interrupt + // the boot. This will notify the user that action is needed + // on this module + l_err->setSev(ERRORLOG::ERRL_SEV_PREDICTIVE); + l_err->collectTrace(NVDIMM_COMP_NAME); + errlCommit( l_err, NVDIMM_COMP_ID ); + o_arm_successful = false; + break; + } + + // Arm successful, update armed status + l_err = NVDIMM::notifyNvdimmProtectionChange(l_nvdimm, + NVDIMM::NVDIMM_ARMED); + if (l_err) + { + l_err->setSev(ERRORLOG::ERRL_SEV_PREDICTIVE); + l_err->collectTrace(NVDIMM_COMP_NAME); + errlCommit(l_err, NVDIMM_COMP_ID); + } + + // Enable Persistency and Warning Threshold notifications + l_err = nvdimmWriteReg(l_nvdimm, SET_EVENT_NOTIFICATION_CMD, ENABLE_NOTIFICATIONS); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"NDVIMM HUID[%X] setting persistency notification", + TARGETING::get_huid(l_nvdimm)); + break; + } + + // Check notification status and errors + l_err = nvdimmReadReg(l_nvdimm, SET_EVENT_NOTIFICATION_STATUS, l_data); + if (l_err) + { + break; + } + else if (((l_data & SET_EVENT_NOTIFICATION_ERROR) == SET_EVENT_NOTIFICATION_ERROR) + || ((l_data & NOTIFICATIONS_ENABLED) != NOTIFICATIONS_ENABLED)) + { + TRACFCOMP(g_trac_nvdimm, "nvdimmArm() nvdimm[%X] failed to set event notification", + get_huid(l_nvdimm)); + + // Set NVDIMM Status flag to partial working, as error detected but data might persist + notifyNvdimmProtectionChange(l_nvdimm, NVDIMM_RISKY_HW_ERROR); + + /*@ + *@errortype + *@reasoncode NVDIMM_SET_EVENT_NOTIFICATION_ERROR + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_SET_EVENT_NOTIFICATION + *@userdata1[0:31] Target Huid + *@userdata2 <UNUSED> + *@devdesc NVDIMM threw an error or failed to set event + * notifications during arming + *@custdesc NVDIMM failed to enable event notificaitons + */ + l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_SET_EVENT_NOTIFICATION, + NVDIMM_SET_EVENT_NOTIFICATION_ERROR, + TARGETING::get_huid(l_nvdimm), + 0x0, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + + l_err->collectTrace( NVDIMM_COMP_NAME ); + + // Callout the dimm + l_err->addHwCallout( l_nvdimm, + HWAS::SRCI_PRIORITY_LOW, + HWAS::NO_DECONFIG, + HWAS::GARD_NULL); + + // Read relevant regs for trace data + nvdimmTraceRegs(l_nvdimm, l_RegInfo); + nvdimmAddPage4Regs(l_nvdimm,l_err); + nvdimmAddVendorLog(l_nvdimm, l_err); + + // Add reg traces to the error log + NVDIMM::UdNvdimmOPParms( l_RegInfo ).addToLog(l_err); + + errlCommit( l_err, NVDIMM_COMP_ID ); + + // We are after the arm step now, so on any error cases let's log it + // then move to the next nvdimm + continue; + } + + // Re-check health status registers + l_err = nvdimmHealthStatusCheck( l_nvdimm, HEALTH_POST_ARM, l_continue ); + + // Check for health status failure + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, "nvdimmArm() nvdimm[%X] failed final health status check", get_huid(l_nvdimm)); + + errlCommit( l_err, NVDIMM_COMP_ID ); + continue; + } + + } + + // Check for uncommited i2c fail error logs + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, "nvdimmArm() failed an i2c read/write"); + errlCommit( l_err, NVDIMM_COMP_ID ); + nvdimmDisarm(i_nvdimmTargetList); + return false; + } + + // Unmask firs if the arm completed successfully + if (o_arm_successful) + { + // Unmask MBACALFIR EventN and set to recoverable + for (TargetHandleList::iterator it = i_nvdimmTargetList.begin(); + it != i_nvdimmTargetList.end();) + { + TargetHandleList l_mcaList; + getParentAffinityTargets(l_mcaList, *it, CLASS_UNIT, TYPE_MCA); + assert(l_mcaList.size(), "nvdimmArm() failed to find parent MCA."); + + // Set MBACALFIR_ACTION0 to recoverable + l_writeAddress = MBACALFIR_ACTION0_REG; + l_writeData = 0; + l_err = deviceRead(l_mcaList[0], &l_writeData, l_writeSize, + DEVICE_SCOM_ADDRESS(l_writeAddress)); + if(l_err) + { + TRACFCOMP(g_trac_nvdimm, "SCOM to address 0x%08x failed", + l_writeAddress); + errlCommit( l_err, NVDIMM_COMP_ID ); + } + + + l_writeData &= MBACALFIR_EVENTN_AND_BIT; + l_err = deviceWrite(l_mcaList[0], &l_writeData, l_writeSize, + DEVICE_SCOM_ADDRESS(l_writeAddress)); + if(l_err) + { + TRACFCOMP(g_trac_nvdimm, "SCOM to address 0x%08x failed", + l_writeAddress); + errlCommit( l_err, NVDIMM_COMP_ID ); + } + + // Set MBACALFIR_ACTION1 to recoverable + l_writeAddress = MBACALFIR_ACTION1_REG; + l_writeData = 0; + l_err = deviceRead(l_mcaList[0], &l_writeData, l_writeSize, + DEVICE_SCOM_ADDRESS(l_writeAddress)); + if(l_err) + { + TRACFCOMP(g_trac_nvdimm, "SCOM to address 0x%08x failed", + l_writeAddress); + errlCommit( l_err, NVDIMM_COMP_ID ); + } + + l_writeData |= MBACALFIR_EVENTN_OR_BIT; + l_err = deviceWrite(l_mcaList[0], &l_writeData, l_writeSize, + DEVICE_SCOM_ADDRESS(l_writeAddress)); + if(l_err) + { + TRACFCOMP(g_trac_nvdimm, "SCOM to address 0x%08x failed", + l_writeAddress); + errlCommit( l_err, NVDIMM_COMP_ID ); + } + + // Unmask MBACALFIR[8] + l_writeAddress = MBACALFIR_AND_MASK_REG; + l_writeData = MBACALFIR_UNMASK_BIT; + l_err = deviceWrite(l_mcaList[0], &l_writeData, l_writeSize, + DEVICE_SCOM_ADDRESS(l_writeAddress)); + if(l_err) + { + TRACFCOMP(g_trac_nvdimm, "SCOM to address 0x%08x failed", + l_writeAddress); + errlCommit( l_err, NVDIMM_COMP_ID ); + } + + it++; + } + + } + + TRACFCOMP(g_trac_nvdimm, EXIT_MRK"nvdimmArm() returning %d", + o_arm_successful); + return o_arm_successful; +} + +bool nvdimmDisarm(TargetHandleList &i_nvdimmTargetList) +{ + bool o_disarm_successful = true; + + TRACFCOMP(g_trac_nvdimm, ENTER_MRK"nvdimmDisarm() %d", + i_nvdimmTargetList.size()); + + errlHndl_t l_err = nullptr; + + for (auto const l_nvdimm : i_nvdimmTargetList) + { + l_err = NVDIMM::nvdimmChangeArmState(l_nvdimm, DISARM_TRIGGER); + // If we run into any error here we will just + // commit the error log and move on. Let the + // system continue to boot and let the user + // salvage the data + if (l_err) + { + // Committing the error as we don't want this to interrupt + // the boot. This will notify the user that action is needed + // on this module + l_err->setSev(ERRORLOG::ERRL_SEV_PREDICTIVE); + l_err->collectTrace(NVDIMM_COMP_NAME); + errlCommit( l_err, NVDIMM_COMP_ID ); + o_disarm_successful = false; + continue; + } + + // Disarm successful, update armed status + l_err = NVDIMM::notifyNvdimmProtectionChange(l_nvdimm, + NVDIMM::NVDIMM_DISARMED); + if (l_err) + { + l_err->setSev(ERRORLOG::ERRL_SEV_PREDICTIVE); + l_err->collectTrace(NVDIMM_COMP_NAME); + errlCommit(l_err, NVDIMM_COMP_ID); + } + } + + TRACFCOMP(g_trac_nvdimm, EXIT_MRK"nvdimmDisarm() returning %d", + o_disarm_successful); + + return o_disarm_successful; + +} + + +/* + * @brief Wrapper function to return NVDIMMs to factory default + */ +bool nvdimmFactoryDefault(TargetHandleList &i_nvdimmList) +{ + errlHndl_t l_err = nullptr; + bool l_success = true; + + // Factory default for all nvdimms in the list + for (const auto & l_nvdimm : i_nvdimmList) + { + l_err = nvdimm_factory_reset(l_nvdimm); + if (l_err) + { + l_success = false; + errlCommit( l_err, NVDIMM_COMP_ID ); + continue; + } + + // Update nvdimm status + l_err = notifyNvdimmProtectionChange(l_nvdimm, NVDIMM_DISARMED); + if (l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + } + + return l_success; +} + + +/* + * @brief Function to start secure erase verify of NVDIMMs + */ +bool nvdimmSecureEraseVerifyStart(TargetHandleList &i_nvdimmList) +{ + errlHndl_t l_err = nullptr; + bool l_success = true; + + // Secure erase verify for all nvdimms in the list + for (const auto & l_nvdimm : i_nvdimmList) + { + // Clear the erase_verify_status reg + l_err = nvdimmWriteReg(l_nvdimm, + ERASE_VERIFY_STATUS, + ERASE_VERIFY_CLEAR); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK + "nvdimmSecureEraseVerifyStart() HUID 0x%X" + "Failed to write ERASE_VERIFY_STATUS register", + get_huid(l_nvdimm)); + l_success = false; + errlCommit( l_err, NVDIMM_COMP_ID ); + continue; + } + + // Start the erase verify operation + l_err = nvdimmWriteReg(l_nvdimm, + ERASE_VERIFY_CONTROL, + ERASE_VERIFY_START); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK + "nvdimmSecureEraseVerifyStart() HUID 0x%X" + "Failed to write ERASE_VERIFY_CONTROL register", + get_huid(l_nvdimm)); + l_success = false; + errlCommit( l_err, NVDIMM_COMP_ID ); + continue; + } + + // Call notify to clear NV_STATUS bit + l_err = notifyNvdimmProtectionChange(l_nvdimm, + ERASE_VERIFY_STARTED); + if (l_err) + { + l_success = false; + errlCommit(l_err, NVDIMM_COMP_ID); + continue; + } + } + + return l_success; +} + + +/* + * @brief Function to check status of secure erase verify of NVDIMMs + */ +bool nvdimmSecureEraseVerifyStatus(TargetHandleList &i_nvdimmList) +{ + errlHndl_t l_err = nullptr; + bool l_success = true; + uint8_t l_data = 0; + + // Check secure erase verify status for all nvdimms in the list + for (const auto & l_nvdimm : i_nvdimmList) + { + // Check if secure-erase-verify is already complete for this nvdimm + ATTR_NV_STATUS_FLAG_type l_nv_status = + l_nvdimm->getAttr<ATTR_NV_STATUS_FLAG>(); + if (l_nv_status & NV_STATUS_ERASE_VERIFY_SET) + { + continue; + } + + l_err = nvdimmReadReg(l_nvdimm, ERASE_VERIFY_CONTROL, l_data); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK + "nvdimmSecureEraseVerifyStatus() HUID 0x%X" + "Failed to read ERASE_VERIFY_CONTROL register", + get_huid(l_nvdimm)); + l_success = false; + errlCommit( l_err, NVDIMM_COMP_ID ); + continue; // Continue to next nvdimm + } + + // If trigger is set the operation is not yet complete + if (l_data & ERASE_VERIFY_TRIGGER) + { + continue; // Continue to next nvdimm + } + + // Secure erase verify on this nvdimm is complete + // Call notify to set NV_STATUS bit + l_err = notifyNvdimmProtectionChange(l_nvdimm, + ERASE_VERIFY_COMPLETED); + if (l_err) + { + l_success = false; + errlCommit(l_err, NVDIMM_COMP_ID); + } + + + // Check the status register + l_err = nvdimmReadReg(l_nvdimm, ERASE_VERIFY_STATUS, l_data); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK + "nvdimmSecureEraseVerifyStatus() HUID 0x%X" + "Failed to read ERASE_VERIFY_STATUS register", + get_huid(l_nvdimm)); + l_success = false; + errlCommit( l_err, NVDIMM_COMP_ID ); + continue; // Continue to next nvdimm + } + + // Non-zero status is an error + if (l_data) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmSecureEraseVerifyStatus() " + "HUID 0x%X ERASE_VERIFY_STATUS returned non-zero status", + get_huid(l_nvdimm)); + /*@ + *@errortype + *@reasoncode NVDIMM_ERASE_VERIFY_STATUS_NONZERO + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_SECURE_ERASE_VERIFY_STATUS + *@userdata1 NVDIMM HUID + *@userdata2 ERASE_VERIFY_STATUS + *@devdesc Error detected during secure erase verify + *@custdesc NVDIMM erase error + */ + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_SECURE_ERASE_VERIFY_STATUS, + NVDIMM_ERASE_VERIFY_STATUS_NONZERO, + get_huid(l_nvdimm), + l_data, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + l_err->collectTrace(NVDIMM_COMP_NAME); + l_err->addPartCallout( l_nvdimm, + HWAS::NV_CONTROLLER_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + nvdimmAddVendorLog(l_nvdimm, l_err); + errlCommit( l_err, NVDIMM_COMP_ID ); + l_success = false; + continue; // Continue to next nvdimm + } + + + // Check the result registers + uint16_t l_result = 0; + l_err = nvdimmReadReg(l_nvdimm, ERASE_VERIFY_RESULT_MSB, l_data); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK + "nvdimmSecureEraseVerifyStatus() HUID 0x%X" + "Failed to read ERASE_VERIFY_RESULT_MSB register", + get_huid(l_nvdimm)); + l_success = false; + errlCommit( l_err, NVDIMM_COMP_ID ); + continue; // Continue to next nvdimm + } + + // Save result + l_result = l_data << 8; + + l_err = nvdimmReadReg(l_nvdimm, ERASE_VERIFY_RESULT_LSB, l_data); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK + "nvdimmSecureEraseVerifyStatus() HUID 0x%X" + "Failed to read ERASE_VERIFY_RESULT_LSB register", + get_huid(l_nvdimm)); + l_success = false; + errlCommit( l_err, NVDIMM_COMP_ID ); + continue; // Continue to next nvdimm + } + + // Save result + l_result |= l_data; + + // Non-zero result is an error + if (l_result) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmSecureEraseVerifyStatus() " + "HUID 0x%X ERASE_VERIFY_RESULT returned non-zero data", + get_huid(l_nvdimm)); + /*@ + *@errortype + *@reasoncode NVDIMM_ERASE_VERIFY_RESULT_NONZERO + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_SECURE_ERASE_VERIFY_STATUS + *@userdata1 NVDIMM HUID + *@userdata2 ERASE_VERIFY_RESULT + *@devdesc Error detected during secure erase verify + *@custdesc NVDIMM erase error + */ + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_SECURE_ERASE_VERIFY_STATUS, + NVDIMM_ERASE_VERIFY_RESULT_NONZERO, + get_huid(l_nvdimm), + l_result, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + l_err->collectTrace(NVDIMM_COMP_NAME); + l_err->addPartCallout( l_nvdimm, + HWAS::NV_CONTROLLER_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + nvdimmAddVendorLog(l_nvdimm, l_err); + errlCommit( l_err, NVDIMM_COMP_ID ); + l_success = false; + continue; // Continue to next nvdimm + } + + } + + return l_success; +} + + } // end NVDIMM namespace diff --git a/src/usr/isteps/nvdimm/nvdimm.H b/src/usr/isteps/nvdimm/nvdimm.H index 4d97a9c66..e66e42470 100644 --- a/src/usr/isteps/nvdimm/nvdimm.H +++ b/src/usr/isteps/nvdimm/nvdimm.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014,2019 */ +/* Contributors Listed Below - COPYRIGHT 2014,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,6 +27,7 @@ #define NVDIMM_H__ #include <usr/errl/errlentry.H> +#include <targeting/common/target.H> #include <targeting/common/commontargeting.H> #include <targeting/common/util.H> #include <targeting/common/utilFilter.H> @@ -40,6 +41,12 @@ extern trace_desc_t* g_trac_nvdimm; namespace NVDIMM { +#define NVDIMM_SET_USER_DATA_1(left_32_ops_id, right_32_huid) \ + TWO_UINT32_TO_UINT64(left_32_ops_id, right_32_huid) + +#define NVDIMM_SET_USER_DATA_2_TIMEOUT(left_32_polled, right_32_timeout) \ + NVDIMM_SET_USER_DATA_1(left_32_polled, right_32_timeout) + // I2C registers for page 0-3, extracted from JEDEC BAEBI spec // Refer to BAEBI spec for details @@ -121,11 +128,13 @@ enum i2cReg : uint16_t SET_ES_POLICY_STATUS = 0x070, FIRMWARE_OPS_STATUS = 0x071, OPERATIONAL_UNIT_OPS_STATUS = 0x072, - RESTORE_FAIL_INFO = 0x088, - OPERATIONAL_UNIT_FAIL_INFO = 0x08F, + ERASE_FAIL_INFO = 0x073, + ARM_FAIL_INFO = 0x076, CSAVE_INFO = 0x080, CSAVE_FAIL_INFO0 = 0x084, CSAVE_FAIL_INFO1 = 0x085, + RESTORE_FAIL_INFO = 0x088, + OPERATIONAL_UNIT_FAIL_INFO = 0x08F, NVM_LIFETIME_ERROR_THRESHOLD = 0x090, ES_LIFETIME_ERROR_THRESHOLD = 0x091, ES_TEMP_ERROR_HIGH_THRESHOLD0 = 0x094, @@ -274,6 +283,45 @@ enum i2cReg : uint16_t TYPED_BLOCK_DATA_BYTE30 = 0x39E, TYPED_BLOCK_DATA_BYTE31 = 0x39F, TYPED_BLOCK_DATA_OFFSET = 0x3E0, + PANIC_CNT = 0x406, + STATUS_EVENT_INT_INFO1 = 0x40A, + STATUS_EVENT_INT_INFO2 = 0x40B, + FLASH_BAD_BLK_PCT = 0x41D, // Read only; Percentage of flash blocks + // in the flash array marked as bad blocks + PARITY_ERROR_COUNT = 0x423, + FLASH_ERROR_COUNT0 = 0x428, // Read only; LSB[7:0] Flash error count + FLASH_ERROR_COUNT1 = 0x429, // Read only; [15:8] + FLASH_ERROR_COUNT2 = 0x42A, // Read only; MSB[23:16] + FLASH_BAD_BLOCK_COUNT0 = 0x42B, + FLASH_BAD_BLOCK_COUNT1 = 0x42C, + BPM_MAGIC_REG1 = 0x430, + BPM_MAGIC_REG2 = 0x431, + SCAP_STATUS = 0x432, + SCAP_REG = 0x434, + SCAP_DATA = 0x435, + I2C_REG_PROTECT = 0x43D, + BPM_REG_CMD = 0x440, + BPM_CMD_STATUS = 0x441, + BPM_PAYLOAD_LENGTH = 0x442, + BPM_REG_ERR_STATUS = 0x443, + BPM_REG_PAYLOAD_START = 0x444, + ERASE_VERIFY_CONTROL = 0x51A, + ERASE_VERIFY_STATUS = 0x51B, + ERASE_VERIFY_RESULT_LSB = 0x51C, + ERASE_VERIFY_RESULT_MSB = 0x51D, + ERASE_VERIFY_TEST = 0x51E, + ENCRYPTION_COMMAND = 0x51F, + ENCRYPTION_CONFIG_STATUS = 0x520, + ENCRYPTION_ACCESS_KEY_SET = 0x521, + ENCRYPTION_ACCESS_KEY_VERIFY = 0x522, + ENCRYPTION_ACCESS_KEY_UNLOCK = 0x523, + ENCRYPTION_RAMDOM_STRING_SET = 0x524, + ENCRYPTION_RANDOM_STRING_VERIFY = 0x525, + ENCRYPTION_ERASE_KEY_SET = 0x526, + ENCRYPTION_ERASE_KEY_VERIFY = 0x527, + ENCRYPTION_ERASE_KEY_TEST = 0x528, + ENCRYPTION_ERASE_KEY_TEST_VERIFY = 0x529, + ENCRYPTION_KEY_VALIDATION = 0x52A, }; // i2cReg macros @@ -292,6 +340,7 @@ enum page : uint8_t TWO = 0x02, THREE = 0x03, FOUR = 0x04, + FIVE = 0x05, }; // Enums for inputs/expected output to/from the i2c registers @@ -306,6 +355,7 @@ enum i2c_in_values : uint8_t RESET_CTRLR = 0x01, VALID_IMAGE = 0x01, RESET_CONTROLLER = 0x01, + FACTORY_DEFAULT = 0x01, }; enum i2c_out_values : uint8_t @@ -317,11 +367,20 @@ enum i2c_out_values : uint8_t CHARGE_IN_PROGRESS = 0x01, SAVE_SUCCESS = 0x01, RSTR_SUCCESS = 0X01, - ARM_SUCCESS = 0X09, + ARM_SUCCESS = 0X01, ERASE_SUCCESS = 0X01, ES_SUCCESS = 0x05, CHARGE_SUCCESS = 0x00, NV_READY = 0xA5, + FACTORY_RESET_IN_PROGRESS = 0x03, + NO_RESET_N = 0x20, + RESET_N_ARMED = 0x08, + ES_POLICY_ERROR = 0x02, + ARM_ERROR = 0X02, + RSTR_ERROR = 0x02, + SAVE_ERROR = 0x02, + ERASE_ERROR = 0x02, + CLEAR_ALL_STATUS = 0x3C, //Clears CAVE, RESTORE, ERASE, and ARM status regs }; // Timeout-related enum @@ -330,6 +389,7 @@ enum timeout : uint32_t OPS_POLL_TIME_MS = 5000, NV_READY_POLL_TIME_MS = 1000, PAGE_SWITCH_POLL_TIME_NS = 100, + KEY_WRITE_DELAY_MS = 100, }; // Assign an id to each of the 6 major ops @@ -354,6 +414,119 @@ enum misc }; /** + * @brief Encryption key data + */ +static constexpr size_t ENC_KEY_SIZE = 32; +struct nvdimmKeyData_t +{ + uint8_t rs[ENC_KEY_SIZE]; // Random String (RS) + uint8_t ek[ENC_KEY_SIZE]; // Erase Key (EK) + uint8_t ak[ENC_KEY_SIZE]; // Access Key (AK) +}; + +struct scap_status_bits +{ + uint8_t Reserved1 : 1; // Bit 7 + uint8_t Bpm_Bsl_Mode : 1; // Bit 6 + uint8_t Reserved2 : 1; // Bit 5 + uint8_t Present : 1; // Bit 4 + uint8_t Delay : 1; // Bit 3 + uint8_t Error : 1; // Bit 2 + uint8_t Busy : 1; // Bit 1 + uint8_t Enable : 1; // Bit 0 +} PACKED; + +/** + * @brief Union simplifying manipulation of SCAP_STATUS bits + */ +union scap_status_union +{ + uint8_t full; + scap_status_bits bit; + + /** + * @brief Constructor + */ + scap_status_union() + : full(0) + {} +} PACKED; + +typedef scap_status_union scap_status_register_t; + +// Bits in Health Status Check Registers +enum health_status : uint8_t +{ + // Module Health Status0 + VOLTAGE_REGULATOR_FAILED = 0x01, + VDD_LOST = 0x02, + VPP_LOST = 0x04, + VTT_LOST = 0x08, + DRAM_NOT_SELF_REFRESH = 0x10, + CONTROLLER_HARDWARE_ERROR = 0x20, + NVM_CONTROLLER_ERROR = 0x40, + NVM_LIFETIME_ERROR = 0x80, + // Module Health Status1 + NOT_ENOUGH_ENERGY_FOR_CSAVE = 0x01, + INVALID_FIRMWARE_ERROR = 0x02, + CONFIG_DATA_ERROR = 0x04, + NO_ES_PRESENT = 0x08, + ES_POLICY_NOT_SET = 0x10, + ES_HARDWARE_FAILURE = 0x20, + ES_HEALTH_ASSESSMENT_ERROR = 0x40, + // Error Threshold Status + ES_LIFETIME_ERROR = 0x02, + ES_TEMP_ERROR = 0x04, +}; + +// Int representation for health status function call +enum health_function : uint8_t +{ + HEALTH_SAVE = 0x01, + HEALTH_RESTORE = 0x02, + HEALTH_UPDATE = 0x03, + HEALTH_PRE_ARM = 0x04, + HEALTH_POST_ARM = 0x05, +}; + +// Event notification register values +enum event_n : uint8_t +{ + PERSISTENCY_NOTIFICATION = 0x01, + SET_EVENT_NOTIFICATION_ERROR = 0x02, + WARNING_THRESHOLD_NOTIFICATION = 0x02, + PERSISTENCY_ENABLED = 0x04, + WARNING_THRESHOLD_ENABLED = 0x08, + ENABLE_NOTIFICATIONS = 0x03, + NOTIFICATIONS_ENABLED = 0x0C, +}; + +// MBACALFIR register addresses +enum mbacal_addresses : uint32_t +{ + MBACALFIR_AND_MASK_REG = 0x07010904, + MBACALFIR_OR_MASK_REG = 0x07010905, + MBACALFIR_ACTION0_REG = 0x07010906, + MBACALFIR_ACTION1_REG = 0x07010907, +}; + +// MBACALFIR bit masks for event n +enum mbacal_bitmask_values : uint64_t +{ + MBACALFIR_EVENTN_AND_BIT = 0xff7fffffffffffff, + MBACALFIR_EVENTN_OR_BIT = 0x0080000000000000, + MBACALFIR_UNMASK_BIT = 0xff7fffffffffffff, +}; + + +/** + * @brief Mask MCBACALFIR Event N to prevent PRD from handling event + * + * @param[in] - i_nvdimm - nvdimm target for operation on its parent MCA + */ +void maskMbacalfir_eventn(TARGETING::Target* i_nvdimm); + +/** * @brief Wrapper to call deviceOp to read the NV controller via I2C * * @param[in] i_nvdimm - nvdimm target with NV controller @@ -434,6 +607,169 @@ errlHndl_t nvdimmPollStatus(TARGETING::Target *i_nvdimm, ops_id i_ops_id, uint32 * the error log. */ errlHndl_t nvdimmSetESPolicy(TARGETING::Target* i_nvdimm); + +/** + * @brief Helper function to handle conflicting attribute keys + * + * @param[in] i_attrKeysFw - firmware key attribute + * + * @param[in] i_attrKeysAnchor - anchor key attribute + * + * @return errlHndl_t - Null if successful, otherwise a pointer to + * the error log + */ +errlHndl_t nvdimm_handleConflictingKeys( + TARGETING::ATTR_NVDIMM_ENCRYPTION_KEYS_FW_typeStdArr& i_attrKeysFw, + TARGETING::ATTR_NVDIMM_ENCRYPTION_KEYS_ANCHOR_typeStdArr& i_attrKeysAnchor); + + +/** + * @brief Helper function to validate attribute keys + * + * @param[in] i_attrData - pointer to attribute key data + * + * @return errlHndl_t - Null if successful, otherwise a pointer to + * the error log + */ +errlHndl_t nvdimm_checkValidAttrKeys( nvdimmKeyData_t* i_attrData ); + + +/** + * @brief Helper function to write encryption key regs (RS/EK/AK) + * + * @param[in] i_nvdimm - nvdimm target + * + * @param[in] i_keyData - data to write to the key reg + * + * @param[in] i_keyReg - enum register to write key + * + * @param[in] i_verifyReg - enum register to verify key written + * + * @param[in] i_secondAttempt - normally false, true if verif check failed + * + * @return errlHndl_t - Null if successful, otherwise a pointer to + * the error log + */ +errlHndl_t nvdimm_setKeyReg(TARGETING::Target* i_nvdimm, + uint8_t* i_keyData, + uint32_t i_keyReg, + uint32_t i_verifyReg, + bool i_secondAttempt); + + +/** + * @brief Helper function to generate randon number for encryption keys + * Generates ENC_KEY_SIZE bytes of data + * Different implementations for boot vs runtime + * + * @param[out] o_genData - pointer to generated data + * + * @return errlHndl_t - Null if successful, otherwise a pointer to + * the error log + */ +errlHndl_t nvdimm_getRandom(uint8_t* o_genData); + + +/** + * @brief Helper function to make a random number valid for keys + * Keys must not contain 0x00 or 0xFF + * - 0x00 KEY_TERMINATE_BYTE terminates a key < 32 bytes + * - 0xFF KEY_ABORT_BYTE aborts the key reg write process + * This function finds invalid bytes in the first random number + * and replaces with bytes from the second random number + * + * @param[out] o_genData - pointer to final generated data + * + * @param[in] i_xtraData - pointer to extra generated data + * + * @return - false if successful, true if failed + * + */ +bool nvdimm_keyifyRandomNumber(uint8_t* o_genData, uint8_t* i_xtraData); + + +/** + * @brief Helper function to validate a random number + * + * @param[in] i_genData - pointer to generated data + * + * @return - true if valid, false if invalid + * + */ +bool nvdimm_validRandomNumber(uint8_t* i_genData); + + +/** + * @brief Helper function to set encryption error + * in ATTR_NVDIMM_ARMED + * + * @param[in] i_nvdimm - nvdimm target + * + */ +void nvdimmSetEncryptionError(TARGETING::Target *i_nvdimm); + + +/** + * @brief Helper function to reset the NVDIMM controller + * + * @param[in] i_nvdimm - nvdimm target + * + * @return errlHndl_t - Null if successful, otherwise a pointer to + * the error log + */ +errlHndl_t nvdimmResetController(TARGETING::Target *i_nvdimm); + + +/** + * @brief Helper function to factory reset NVDIMM + * + * @param[in] i_nvdimm - nvdimm target + * + * @return errlHndl_t - Null if successful, otherwise a pointer to + * the error log + */ +errlHndl_t nvdimm_factory_reset(TARGETING::Target *i_nvdimm); + + +#ifndef __HOSTBOOT_RUNTIME + +/** + * @brief Helper function to get TPM pointer for random number generation + * + * @param[out] - pointer to a functional TPM or nullptr if no TPM found + * + * @return errlHndl_t - Null if successful, otherwise a pointer to + * the error log + */ +errlHndl_t nvdimm_getTPM(TARGETING::Target*& o_tpm); + +#endif + +/** + * @brief This function checks for valid image on the given target + * + * @param[in] i_nvdimm - nvdimm target with NV controller + * + * @param[out] o_imgValid - return true if the target has a valid image + * + * @return errlHndl_t - Null if successful, otherwise a pointer to + * the error log. + */ +errlHndl_t nvdimmValidImage(TARGETING::Target *i_nvdimm, bool &o_imgValid); + + +/** + * @brief This function grabs the current slot NVDIMM code is running + * Slot 0 is the failure slot, Slot 1 is the updateable slot + * + * @param[in] i_nvdimm - nvdimm target with NV controller + * @param[out] o_slot - 0 or 1 + * + * @return errlHndl_t - Null if successful, otherwise a pointer to + * the error log. + */ +errlHndl_t nvdimmGetRunningSlot(TARGETING::Target *i_nvdimm, uint8_t & o_slot); + } //End NVDIMM namespace diff --git a/src/usr/isteps/nvdimm/nvdimm.mk b/src/usr/isteps/nvdimm/nvdimm.mk index 397b27814..d9418b414 100644 --- a/src/usr/isteps/nvdimm/nvdimm.mk +++ b/src/usr/isteps/nvdimm/nvdimm.mk @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2018 +# Contributors Listed Below - COPYRIGHT 2018,2019 # [+] International Business Machines Corp. # # @@ -47,11 +47,14 @@ EXTRAINCDIR += ${PROCEDURE_PATH}/hwp/ffdc/ OBJS += nvdimm.o OBJS += nvdimmdd.o OBJS += errlud_nvdimm.o +OBJS += nvdimmErrorLog.o ifneq (${HOSTBOOT_RUNTIME},1) # code update path for NVDIMMs (not at RUNTIME) OBJS += nvdimm_update.o +# code update path for BPMs (not at runtime) +OBJS += bpm_update.o endif diff --git a/src/usr/isteps/nvdimm/nvdimmErrorLog.C b/src/usr/isteps/nvdimm/nvdimmErrorLog.C new file mode 100644 index 000000000..9fbd27d14 --- /dev/null +++ b/src/usr/isteps/nvdimm/nvdimmErrorLog.C @@ -0,0 +1,1317 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/isteps/nvdimm/nvdimmErrorLog.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +#include "nvdimm.H" +#include <trace/interface.H> +#include <errl/errlentry.H> +#include <errl/errlmanager.H> +#include <errl/errludtarget.H> +#include <targeting/common/commontargeting.H> +#include <targeting/common/util.H> +#include <targeting/common/utilFilter.H> +#include <fapi2.H> +#include <isteps/nvdimm/nvdimmreasoncodes.H> +#include <isteps/nvdimm/nvdimm.H> +#include "errlud_nvdimm.H" + +using namespace TARGETING; + +namespace NVDIMM +{ + +/** + * @brief Read and save various status registers needed for error log traces + * + * @param[in] i_nvdimm - nvdimm target + * + * @param[out] o_RegInfo - struct to hold register data + * + */ +void nvdimmTraceRegs(Target *i_nvdimm, nvdimm_reg_t& o_RegInfo) +{ + uint8_t l_data = 0x0; + errlHndl_t l_err = nullptr; + + // Read MODULE HEALTH register + l_err = nvdimmReadReg(i_nvdimm, MODULE_HEALTH, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + o_RegInfo.Module_Health = l_data; + + // Read MODULE HEALTH STATUS0 register + l_err = nvdimmReadReg(i_nvdimm, MODULE_HEALTH_STATUS0, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + o_RegInfo.Module_Health_Status0 = l_data; + + // Read MODULE HEALTH STATUS1 register + l_err = nvdimmReadReg(i_nvdimm, MODULE_HEALTH_STATUS1, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + o_RegInfo.Module_Health_Status1 = l_data; + + // Read CSAVE STATUS register + l_err = nvdimmReadReg(i_nvdimm, CSAVE_STATUS, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + o_RegInfo.CSave_Status = l_data; + + // Read CSAVE INFO register + l_err = nvdimmReadReg(i_nvdimm, CSAVE_INFO, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + o_RegInfo.CSave_Info = l_data; + + // Read CSAVE FAIL INFO0 register + l_err = nvdimmReadReg(i_nvdimm, CSAVE_FAIL_INFO0, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + o_RegInfo.CSave_Fail_Info0 = l_data; + + // Read CSAVE FAIL INFO1 register + l_err = nvdimmReadReg(i_nvdimm, CSAVE_FAIL_INFO1, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + o_RegInfo.CSave_Fail_Info1 = l_data; + + // Read CSAVE TIMEOUT0 register + l_err = nvdimmReadReg(i_nvdimm, CSAVE_TIMEOUT0, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + o_RegInfo.CSave_Timeout0 = l_data; + + // Read CSAVE TIMEOUT1 register + l_err = nvdimmReadReg(i_nvdimm, CSAVE_TIMEOUT1, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + o_RegInfo.CSave_Timeout1 = l_data; + + // Read ERROR THRESHOLD STATUS register + l_err = nvdimmReadReg(i_nvdimm, ERROR_THRESHOLD_STATUS, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + o_RegInfo.Error_Threshold_Status = l_data; + + // Read NVDIMM READY register + l_err = nvdimmReadReg(i_nvdimm, NVDIMM_READY, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + o_RegInfo.NVDimm_Ready = l_data; + + // Read NVDIMM CMD STATUS0 register + l_err = nvdimmReadReg(i_nvdimm, NVDIMM_CMD_STATUS0, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + o_RegInfo.NVDimm_CMD_Status0 = l_data; + + // Read ERASE STATUS register + l_err = nvdimmReadReg(i_nvdimm, ERASE_STATUS, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + o_RegInfo.Erase_Status = l_data; + + // Read ERASE FAIL INFO register + l_err = nvdimmReadReg(i_nvdimm, ERASE_FAIL_INFO, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + o_RegInfo.Erase_Fail_Info = l_data; + + // Read ERASE TIMEOUT0 register + l_err = nvdimmReadReg(i_nvdimm, ERASE_TIMEOUT0, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + o_RegInfo.Erase_Timeout0 = l_data; + + // Read ERASE TIMEOUT1 register + l_err = nvdimmReadReg(i_nvdimm, ERASE_TIMEOUT1, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + o_RegInfo.Erase_Timeout1 = l_data; + + // Read ABORT CMD TIMEOUT register + l_err = nvdimmReadReg(i_nvdimm, ABORT_CMD_TIMEOUT, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + o_RegInfo.Abort_CMD_Timeout = l_data; + + // Read SET ES POLICY STATUS register + l_err = nvdimmReadReg(i_nvdimm, SET_ES_POLICY_STATUS, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + o_RegInfo.Set_ES_Policy_Status = l_data; + + // Read RESTORE STATUS register + l_err = nvdimmReadReg(i_nvdimm, RESTORE_STATUS, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + o_RegInfo.Restore_Status = l_data; + + // Read RESTORE FAIL INFO register + l_err = nvdimmReadReg(i_nvdimm, RESTORE_FAIL_INFO, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + o_RegInfo.Restore_Fail_Info = l_data; + + // Read RESTORE TIMEOUT0 register + l_err = nvdimmReadReg(i_nvdimm, RESTORE_TIMEOUT0, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + o_RegInfo.Restore_Timeout0 = l_data; + + // Read RESTORE TIMEOUT1 register + l_err = nvdimmReadReg(i_nvdimm, RESTORE_TIMEOUT1, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + o_RegInfo.Restore_Timeout1 = l_data; + + // Read ARM STATUS register + l_err = nvdimmReadReg(i_nvdimm, ARM_STATUS, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + o_RegInfo.Arm_Status = l_data; + + // Read ARM FAIL INFO register + l_err = nvdimmReadReg(i_nvdimm, ARM_FAIL_INFO, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + o_RegInfo.Arm_Fail_Info = l_data; + + // Read ARM TIMEOUT0 register + l_err = nvdimmReadReg(i_nvdimm, ARM_TIMEOUT0, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + o_RegInfo.Arm_Timeout0 = l_data; + + // Read ARM TIMEOUT1 register + l_err = nvdimmReadReg(i_nvdimm, ARM_TIMEOUT1, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + o_RegInfo.Arm_Timeout1 = l_data; + + // Read SET EVENT NOTIFICATION STATUS register + l_err = nvdimmReadReg(i_nvdimm, SET_EVENT_NOTIFICATION_STATUS, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + o_RegInfo.Set_Event_Notification_Status = l_data; + + // Read NVDIMM Encryption Configuration and Status Register for Security Errors + l_err = nvdimmReadReg(i_nvdimm, ENCRYPTION_CONFIG_STATUS, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + o_RegInfo.Encryption_Config_Status = l_data; +} + +/** + * @brief Helper function for standard callout of an NVDIMM + * + * @param[in] i_nvdimm - nvdimm target + * + * @param[in] i_step - the nvdimm function calling the health check + * + * @param[out] o_err - error log handler to be modified + * + * @return bool - true to commit log and continue, false to return + * the error log to caller and exit. + */ +bool nvdimmCalloutDimm(Target *i_nvdimm, uint8_t i_step, errlHndl_t& o_err) +{ + bool l_continue = true; + uint8_t l_data; + errlHndl_t l_err = nullptr; + + // Check which callout check is necessary + switch(i_step) + { + // Post save errors always continue with callouts + case HEALTH_SAVE: + { + // Check to see if the nvdimm image is still valid + l_err = nvdimmValidImage(i_nvdimm, l_continue); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + + // Checkout image validity and set dimm status accordingly + if(l_continue) + { + // Set ATTR_NV_STATUS_FLAG to partially working as data may still persist + nvdimmSetStatusFlag(i_nvdimm, NSTD_ERR_VAL_SR); + + // Callout dimm but do not deconfig or gard + o_err->addHwCallout( i_nvdimm, + HWAS::SRCI_PRIORITY_LOW, + HWAS::NO_DECONFIG, + HWAS::GARD_NULL); + } + else + { + // Callout, deconfig and gard the dimm + o_err->addHwCallout( i_nvdimm, + HWAS::SRCI_PRIORITY_HIGH, + HWAS::DECONFIG, + HWAS::GARD_Fatal); + } + + break; + } + + // Post restore errors always continue with callouts + case HEALTH_RESTORE: + { + // Check restore status + l_err = nvdimmReadReg(i_nvdimm, RESTORE_STATUS, l_data); + if (l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + else if ((l_data & RSTR_SUCCESS) != RSTR_SUCCESS) + { + l_continue = false; + } + + // Check restore status and set dimm status accordingly + if(l_continue) + { + // Set ATTR_NV_STATUS_FLAG to partially working as data may still persist + nvdimmSetStatusFlag(i_nvdimm, NSTD_ERR_VAL_SR); + + // Callout dimm but do not deconfig or gard + o_err->addHwCallout( i_nvdimm, + HWAS::SRCI_PRIORITY_LOW, + HWAS::NO_DECONFIG, + HWAS::GARD_NULL); + } + else + { + // Callout, deconfig and gard the dimm + o_err->addHwCallout( i_nvdimm, + HWAS::SRCI_PRIORITY_HIGH, + HWAS::DECONFIG, + HWAS::GARD_Fatal); + } + + break; + } + + // Post ARM errors need check for arm success + case HEALTH_PRE_ARM: + { + + // Check arm status + l_err = nvdimmReadReg(i_nvdimm, ARM_STATUS, l_data); + if (l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + else if (((l_data & ARM_SUCCESS) != ARM_SUCCESS) || ((l_data & RESET_N_ARMED) != RESET_N_ARMED)) + { + l_continue = false; + } + + // Check arm status and set dimm status accordingly + if(l_continue) + { + // Set ATTR_NV_STATUS_FLAG to partially working as data may still persist + notifyNvdimmProtectionChange(i_nvdimm,NVDIMM_RISKY_HW_ERROR); + + // Callout dimm without deconfig or gard + o_err->addHwCallout( i_nvdimm, + HWAS::SRCI_PRIORITY_LOW, + HWAS::NO_DECONFIG, + HWAS::GARD_NULL); + } + else + { + // Set ATTR_NV_STATUS_FLAG to dimm diarmed + l_err = notifyNvdimmProtectionChange(i_nvdimm, NVDIMM_DISARMED); + if (l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + + // Callout and gard the dimm + o_err->addHwCallout( i_nvdimm, + HWAS::SRCI_PRIORITY_HIGH, + HWAS::NO_DECONFIG, + HWAS::GARD_Fatal); + } + + break; + } + + // Post ARM errors need check for arm success + case HEALTH_POST_ARM: + { + // Callout dimm but do not deconfig or gard + o_err->addHwCallout( i_nvdimm, + HWAS::SRCI_PRIORITY_LOW, + HWAS::NO_DECONFIG, + HWAS::GARD_NULL); + + // Set ATTR_NV_STATUS_FLAG to partially working as data may persist despite errors + notifyNvdimmProtectionChange(i_nvdimm,NVDIMM_RISKY_HW_ERROR); + + break; + } + + } + + return l_continue; +} + +/** + * @brief Helper function for BPM/Cable high, NVDIMM low callout + * + * @param[in] i_nvdimm - nvdimm target + * + * @param[in] i_step - the nvdimm function calling the health check + * + * @param[out] o_err - error log handler to be modified + * + * @return bool - true to commit log and continue, false to return + * the error log to caller and exit. + */ +bool nvdimmBPMCableCallout(Target *i_nvdimm, uint8_t i_step, errlHndl_t& o_err) +{ + bool l_continue = true; + uint8_t l_data; + errlHndl_t l_err = nullptr; + + // Check which callout check is necessary + switch(i_step) + { + // Post save errors always continue with callouts + case HEALTH_SAVE: + { + // Check to see if the nvdimm image is still valid + l_err = nvdimmValidImage(i_nvdimm, l_continue); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + + // Callout BPM and Cable but cannot deconfig or gard + o_err->addPartCallout( i_nvdimm, + HWAS::BPM_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + o_err->addPartCallout( i_nvdimm, + HWAS::BPM_CABLE_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + + // Check image validity and set dimm status accordingly + if(l_continue) + { + // Set ATTR_NV_STATUS_FLAG to partially working as data may still persist + nvdimmSetStatusFlag(i_nvdimm, NSTD_ERR_VAL_SR); + + // Callout dimm but do not deconfig or gard + o_err->addHwCallout( i_nvdimm, + HWAS::SRCI_PRIORITY_LOW, + HWAS::NO_DECONFIG, + HWAS::GARD_NULL); + } + else + { + // Callout dimm, deconfig and gard + o_err->addHwCallout( i_nvdimm, + HWAS::SRCI_PRIORITY_LOW, + HWAS::DECONFIG, + HWAS::GARD_Fatal); + } + + break; + } + + // Post restore errors always continue with callouts + case HEALTH_RESTORE: + { + // Check restore status + l_err = nvdimmReadReg(i_nvdimm, RESTORE_STATUS, l_data); + if (l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + else if ((l_data & RSTR_SUCCESS) != RSTR_SUCCESS) + { + l_continue = false; + } + + // Callout dimm but do not deconfig or gard + o_err->addPartCallout( i_nvdimm, + HWAS::BPM_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + o_err->addPartCallout( i_nvdimm, + HWAS::BPM_CABLE_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + // Callout dimm but do not deconfig or gard + o_err->addHwCallout( i_nvdimm, + HWAS::SRCI_PRIORITY_LOW, + HWAS::NO_DECONFIG, + HWAS::GARD_NULL); + + // Check restore status and set dimm status accordingly + if(l_continue) + { + // Set ATTR_NV_STATUS_FLAG to partially working as data may still persist + nvdimmSetStatusFlag(i_nvdimm, NSTD_ERR_VAL_SR); + } + + break; + } + + // Post ARM errors need check for arm success + case HEALTH_PRE_ARM: + { + // Check arm status + l_err = nvdimmReadReg(i_nvdimm, ARM_STATUS, l_data); + if (l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + else if (((l_data & ARM_SUCCESS) != ARM_SUCCESS) || ((l_data & RESET_N_ARMED) != RESET_N_ARMED)) + { + l_continue = false; + } + + // Callout BPM and Cable but cannot deconfig or gard + o_err->addPartCallout( i_nvdimm, + HWAS::BPM_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + o_err->addPartCallout( i_nvdimm, + HWAS::BPM_CABLE_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + + // Check arm status and set dimm status accordingly + if(l_continue) + { + // Set ATTR_NV_STATUS_FLAG to partially working as data may still persist + notifyNvdimmProtectionChange(i_nvdimm,NVDIMM_RISKY_HW_ERROR); + } + + // Callout dimm but do not deconfig or gard + o_err->addHwCallout( i_nvdimm, + HWAS::SRCI_PRIORITY_LOW, + HWAS::NO_DECONFIG, + HWAS::GARD_NULL); + break; + } + + // Post ARM errors need check for arm success + case HEALTH_POST_ARM: + { + // Callout dimm but do not deconfig or gard + o_err->addPartCallout( i_nvdimm, + HWAS::BPM_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + o_err->addPartCallout( i_nvdimm, + HWAS::BPM_CABLE_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + o_err->addHwCallout( i_nvdimm, + HWAS::SRCI_PRIORITY_LOW, + HWAS::NO_DECONFIG, + HWAS::GARD_NULL); + + // Set ATTR_NV_STATUS_FLAG to partially working as data may still persist + notifyNvdimmProtectionChange(i_nvdimm,NVDIMM_RISKY_HW_ERROR); + + break; + } + + } + + return l_continue; +} + +/** + * @brief Helper function for BPM high, NVDIMM low callout + * + * @param[in] i_nvdimm - nvdimm target + * + * @param[in] i_step - the nvdimm function calling the health check + * + * @param[out] o_err - error log handler to be modified + * + * @return bool - true to commit log and continue, false to return + * the error log to caller and exit. + */ +bool nvdimmBPMCallout(Target *i_nvdimm, uint8_t i_step, errlHndl_t& o_err) +{ + bool l_continue = true; + uint8_t l_data; + errlHndl_t l_err = nullptr; + + // Check which callout check is necessary + switch(i_step) + { + // Post save errors always continue with callouts + case HEALTH_SAVE: + { + // Callout BPM on high + o_err->addPartCallout( i_nvdimm, + HWAS::BPM_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + + // Callout dimm but do not deconfig or gard + o_err->addHwCallout( i_nvdimm, + HWAS::SRCI_PRIORITY_LOW, + HWAS::NO_DECONFIG, + HWAS::GARD_NULL); + + // Set ATTR_NV_STATUS_FLAG to partially working as data may still persist + nvdimmSetStatusFlag(i_nvdimm, NSTD_ERR_VAL_SR); + + break; + } + + // Post restore errors always continue with callouts + case HEALTH_RESTORE: + { + // Callout BPM on high + o_err->addPartCallout( i_nvdimm, + HWAS::BPM_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + + // Callout dimm but do not deconfig or gard + o_err->addHwCallout( i_nvdimm, + HWAS::SRCI_PRIORITY_LOW, + HWAS::NO_DECONFIG, + HWAS::GARD_NULL); + + // Set ATTR_NV_STATUS_FLAG to partially working as data may still persist + nvdimmSetStatusFlag(i_nvdimm, NSTD_ERR_VAL_SR); + + break; + } + + // Post ARM errors need check for arm success + case HEALTH_PRE_ARM: + { + // Check arm status + l_err = nvdimmReadReg(i_nvdimm, ARM_STATUS, l_data); + if (l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + else if (((l_data & ARM_SUCCESS) != ARM_SUCCESS) || ((l_data & RESET_N_ARMED) != RESET_N_ARMED)) + { + l_continue = false; + } + + // Callout BPM on high + o_err->addPartCallout( i_nvdimm, + HWAS::BPM_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + + // Callout dimm but do not deconfig or gard + o_err->addHwCallout( i_nvdimm, + HWAS::SRCI_PRIORITY_LOW, + HWAS::NO_DECONFIG, + HWAS::GARD_NULL); + + // Check arm status and set dimm status accordingly + if(l_continue) + { + // Set ATTR_NV_STATUS_FLAG to partially working as data may still persist + notifyNvdimmProtectionChange(i_nvdimm,NVDIMM_RISKY_HW_ERROR); + } + else + { + // Set ATTR_NV_STATUS_FLAG to dimm diarmed + l_err = notifyNvdimmProtectionChange(i_nvdimm, NVDIMM_DISARMED); + if (l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + } + + break; + } + + // Post ARM errors need check for arm success + case HEALTH_POST_ARM: + { + // Callout BPM on high + o_err->addPartCallout( i_nvdimm, + HWAS::BPM_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + + // Callout dimm but do not deconfig or gard + o_err->addHwCallout( i_nvdimm, + HWAS::SRCI_PRIORITY_LOW, + HWAS::NO_DECONFIG, + HWAS::GARD_NULL); + + // Set ATTR_NV_STATUS_FLAG to partially working as data may still persist + notifyNvdimmProtectionChange(i_nvdimm,NVDIMM_RISKY_HW_ERROR); + + break; + } + + } + + return l_continue; +} + +/** + * @brief Function checking the Health Status Registers for an nvdimm + * + * @param[in] i_nvdimm - nvdimm target + * + * @param[in] i_step - the nvdimm step calling the check + * + * @param[out] o_continue - bool to signal a return to caller fail + * + * @return errlHndl_t - Null if successful, otherwise a pointer to + * the error log. + */ +errlHndl_t nvdimmHealthStatusCheck(Target *i_nvdimm, uint8_t i_step, bool& o_continue) +{ + uint8_t l_data = 0x0; + errlHndl_t l_err = nullptr; + errlHndl_t l_err_t = nullptr; + nvdimm_reg_t l_RegInfo; + bool l_arm_timeout = false; + + if (i_step == HEALTH_PRE_ARM) + { + l_arm_timeout = o_continue; + } + + //Collect Register data for parsing and traces + nvdimmTraceRegs(i_nvdimm, l_RegInfo); + + // Read SET_EVENT_NOTIFICATION_STATUS register + l_err = nvdimmReadReg(i_nvdimm, SET_EVENT_NOTIFICATION_STATUS, l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + l_RegInfo.Set_Event_Notification_Status = l_data; + + // Read RESTORE STATUS register + l_err = nvdimmReadReg(i_nvdimm, RESTORE_STATUS , l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + l_RegInfo.Restore_Status = l_data; + + // Read RESTORE_FAIL_INFO register + l_err = nvdimmReadReg(i_nvdimm, RESTORE_FAIL_INFO , l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + l_RegInfo.Restore_Fail_Info = l_data; + + // Read NVDIMM_CMD_STATUS0 register + l_err = nvdimmReadReg(i_nvdimm, NVDIMM_CMD_STATUS0 , l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + l_RegInfo.NVDimm_CMD_Status0 = l_data; + + // Read ARM_STATUS register + l_err = nvdimmReadReg(i_nvdimm, ARM_STATUS , l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + l_RegInfo.Arm_Status = l_data; + + // Read SET_ES_POLICY_STATUS register + l_err = nvdimmReadReg(i_nvdimm, SET_ES_POLICY_STATUS , l_data); + if(l_err) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + l_RegInfo.Set_ES_Policy_Status = l_data; + + // Check all nvdimm deconfig cases + do + { + // Check MODULE_HEALTH_STATUS0[0] + if ((l_RegInfo.Module_Health_Status0 & VOLTAGE_REGULATOR_FAILED) == VOLTAGE_REGULATOR_FAILED) + { + /*@ + *@errortype + *@reasoncode NVDIMM_VOLTAGE_REGULATOR_FAILED + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_MODULE_HEALTH_STATUS_CHECK + *@userdata1[0:31] Target Huid + *@userdata2 <UNUSED> + *@devdesc NVDIMM failed module health status check due to + * voltage regulator failure + *@custdesc NVDIMM failed module health status check + */ + l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_MODULE_HEALTH_STATUS_CHECK, + NVDIMM_VOLTAGE_REGULATOR_FAILED, + TARGETING::get_huid(i_nvdimm), + 0x0, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + break; + } + + // Check MODULE_HEALTH_STATUS0[1] + if ((l_RegInfo.Module_Health_Status0 & VDD_LOST) == VDD_LOST) + { + /*@ + *@errortype + *@reasoncode NVDIMM_VDD_LOST + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_MODULE_HEALTH_STATUS_CHECK + *@userdata1[0:31] Target Huid + *@userdata2 <UNUSED> + *@devdesc NVDIMM failed module health status check due to + * vdd loss + *@custdesc NVDIMM failed module health status check + */ + l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_MODULE_HEALTH_STATUS_CHECK, + NVDIMM_VDD_LOST, + TARGETING::get_huid(i_nvdimm), + 0x0, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + break; + } + + // Check MODULE_HEALTH_STATUS0[2] + if ((l_RegInfo.Module_Health_Status0 & VPP_LOST) == VPP_LOST) + { + /*@ + *@errortype + *@reasoncode NVDIMM_VPP_LOST + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_MODULE_HEALTH_STATUS_CHECK + *@userdata1[0:31] Target Huid + *@userdata2 <UNUSED> + *@devdesc NVDIMM failed module health status check due to + * vpp loss + *@custdesc NVDIMM failed module health status check + */ + l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_MODULE_HEALTH_STATUS_CHECK, + NVDIMM_VPP_LOST, + TARGETING::get_huid(i_nvdimm), + 0x0, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + break; + } + + // Check MODULE_HEALTH_STATUS0[3] + if ((l_RegInfo.Module_Health_Status0 & VTT_LOST) == VTT_LOST) + { + /*@ + *@errortype + *@reasoncode NVDIMM_VTT_LOST + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_MODULE_HEALTH_STATUS_CHECK + *@userdata1[0:31] Target Huid + *@userdata2 <UNUSED> + *@devdesc NVDIMM failed module health status check due to + * vtt loss + *@custdesc NVDIMM failed module health status check + */ + l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_MODULE_HEALTH_STATUS_CHECK, + NVDIMM_VTT_LOST, + TARGETING::get_huid(i_nvdimm), + 0x0, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + break; + } + + // Check MODULE_HEALTH_STATUS0[4] + if ((l_RegInfo.Module_Health_Status0 & DRAM_NOT_SELF_REFRESH) == DRAM_NOT_SELF_REFRESH) + { + /*@ + *@errortype + *@reasoncode NVDIMM_DRAM_NOT_SELF_REFRESH + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_MODULE_HEALTH_STATUS_CHECK + *@userdata1[0:31] Target Huid + *@userdata2 <UNUSED> + *@devdesc NVDIMM failed module health status check due to + * no self refresh on the nvdimm + *@custdesc NVDIMM failed module health status check + */ + l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_MODULE_HEALTH_STATUS_CHECK, + NVDIMM_DRAM_NOT_SELF_REFRESH, + TARGETING::get_huid(i_nvdimm), + 0x0, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + break; + } + + // Check MODULE_HEALTH_STATUS0[5] + if ((l_RegInfo.Module_Health_Status0 & CONTROLLER_HARDWARE_ERROR) == CONTROLLER_HARDWARE_ERROR) + { + /*@ + *@errortype + *@reasoncode NVDIMM_CONTROLLER_HARDWARE_ERROR + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_MODULE_HEALTH_STATUS_CHECK + *@userdata1[0:31] Target Huid + *@userdata2 <UNUSED> + *@devdesc NVDIMM failed module health status check due to + * error with the hardware controller + *@custdesc NVDIMM failed module health status check + */ + l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_MODULE_HEALTH_STATUS_CHECK, + NVDIMM_CONTROLLER_HARDWARE_ERROR, + TARGETING::get_huid(i_nvdimm), + 0x0, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + break; + } + + // Check MODULE_HEALTH_STATUS0[6] + if ((l_RegInfo.Module_Health_Status0 & NVM_CONTROLLER_ERROR) == NVM_CONTROLLER_ERROR) + { + /*@ + *@errortype + *@reasoncode NVDIMM_NVM_CONTROLLER_ERROR + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_MODULE_HEALTH_STATUS_CHECK + *@userdata1[0:31] Target Huid + *@userdata2 <UNUSED> + *@devdesc NVDIMM failed module health status check due to + * error with the nvdimm controller + *@custdesc NVDIMM failed module health status check + */ + l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_MODULE_HEALTH_STATUS_CHECK, + NVDIMM_NVM_CONTROLLER_ERROR, + TARGETING::get_huid(i_nvdimm), + 0x0, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + break; + } + + + // Check MODULE_HEALTH_STATUS0[7] + if ((l_RegInfo.Module_Health_Status0 & NVM_LIFETIME_ERROR) == NVM_LIFETIME_ERROR) + { + /*@ + *@errortype + *@reasoncode NVDIMM_NVM_LIFETIME_ERROR + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_MODULE_HEALTH_STATUS_CHECK + *@userdata1[0:31] Target Huid + *@userdata2 <UNUSED> + *@devdesc NVDIMM failed module health status check due to + * an nvdimm lifetime error + *@custdesc NVDIMM failed module health status check + */ + l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_MODULE_HEALTH_STATUS_CHECK, + NVDIMM_NVM_LIFETIME_ERROR, + TARGETING::get_huid(i_nvdimm), + 0x0, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + break; + } + + // Check MODULE_HEALTH_STATUS1[1] + if ((l_RegInfo.Module_Health_Status1 & INVALID_FIRMWARE_ERROR) == INVALID_FIRMWARE_ERROR) + { + /*@ + *@errortype + *@reasoncode NVDIMM_INVALID_FIRMWARE_ERROR + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_MODULE_HEALTH_STATUS_CHECK + *@userdata1[0:31] Target Huid + *@userdata2 <UNUSED> + *@devdesc NVDIMM failed module health status check due to + * an invalid firmware image + *@custdesc NVDIMM failed module health status check + */ + l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_MODULE_HEALTH_STATUS_CHECK, + NVDIMM_INVALID_FIRMWARE_ERROR, + TARGETING::get_huid(i_nvdimm), + 0x0, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + break; + } + + // Check MODULE_HEALTH_STATUS1[2] + if ((l_RegInfo.Module_Health_Status1 & CONFIG_DATA_ERROR) == CONFIG_DATA_ERROR) + { + /*@ + *@errortype + *@reasoncode NVDIMM_CONFIG_DATA_ERROR + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_MODULE_HEALTH_STATUS_CHECK + *@userdata1[0:31] Target Huid + *@userdata2 <UNUSED> + *@devdesc NVDIMM failed module health status check due to + * invalid configuration data + *@custdesc NVDIMM failed module health status check + */ + l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_MODULE_HEALTH_STATUS_CHECK, + NVDIMM_CONFIG_DATA_ERROR, + TARGETING::get_huid(i_nvdimm), + 0x0, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + break; + } + + }while(0); + + if (l_err) + { + // Setup Trace + l_err->collectTrace( NVDIMM_COMP_NAME ); + + // Add reg traces to the error log + NVDIMM::UdNvdimmOPParms( l_RegInfo ).addToLog(l_err); + + // Callout nvdimm depending on istep call + o_continue &= nvdimmCalloutDimm(i_nvdimm, i_step, l_err); + + if(l_arm_timeout) + { + // Callout and gard the dimm + l_err->addHwCallout( i_nvdimm, + HWAS::SRCI_PRIORITY_LOW, + HWAS::NO_DECONFIG, + HWAS::GARD_Fatal); + } + } + + // Check all BPM and Cable high, nvdimm low cases + do + { + // If function calling is SAVE, ignore NOT_ENOUGH_ENERGY_FOR_CSAVE + if (i_step != HEALTH_SAVE) + { + // Check MODULE_HEALTH_STATUS1[0] + if ((l_RegInfo.Module_Health_Status1 & NOT_ENOUGH_ENERGY_FOR_CSAVE) == NOT_ENOUGH_ENERGY_FOR_CSAVE) + { + /*@ + *@errortype + *@reasoncode NVDIMM_NOT_ENOUGH_ENERGY_FOR_CSAVE + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_MODULE_HEALTH_STATUS_CHECK + *@userdata1[0:31] Target Huid + *@userdata2 <UNUSED> + *@devdesc NVDIMM failed module health status check due to + * insufficient energy for csave + *@custdesc NVDIMM failed module health status check + */ + l_err_t = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_MODULE_HEALTH_STATUS_CHECK, + NVDIMM_NOT_ENOUGH_ENERGY_FOR_CSAVE, + TARGETING::get_huid(i_nvdimm), + 0x0, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + break; + } + } + + // Check MODULE_HEALTH_STATUS1[3] + if ((l_RegInfo.Module_Health_Status1 & NO_ES_PRESENT) == NO_ES_PRESENT) + { + /*@ + *@errortype + *@reasoncode NVDIMM_NO_ES_PRESENT + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_MODULE_HEALTH_STATUS_CHECK + *@userdata1[0:31] Target Huid + *@userdata2 <UNUSED> + *@devdesc NVDIMM failed module health status check due to + * no ES active + *@custdesc NVDIMM failed module health status check + */ + l_err_t = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_MODULE_HEALTH_STATUS_CHECK, + NVDIMM_NO_ES_PRESENT, + TARGETING::get_huid(i_nvdimm), + 0x0, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + break; + } + + // Check MODULE_HEALTH_STATUS1[5] + if ((l_RegInfo.Module_Health_Status1 & ES_HARDWARE_FAILURE) == ES_HARDWARE_FAILURE) + { + /*@ + *@errortype + *@reasoncode NVDIMM_ES_HARDWARE_FAILURE + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_MODULE_HEALTH_STATUS_CHECK + *@userdata1[0:31] Target Huid + *@userdata2 <UNUSED> + *@devdesc NVDIMM failed module health status check due to + * ES hardware failure + *@custdesc NVDIMM failed module health status check + */ + l_err_t = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_MODULE_HEALTH_STATUS_CHECK, + NVDIMM_ES_HARDWARE_FAILURE, + TARGETING::get_huid(i_nvdimm), + 0x0, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + break; + } + + // Check MODULE_HEALTH_STATUS1[6] + if ((l_RegInfo.Module_Health_Status1 & ES_HEALTH_ASSESSMENT_ERROR) == ES_HEALTH_ASSESSMENT_ERROR) + { + /*@ + *@errortype + *@reasoncode NVDIMM_ES_HEALTH_ASSESSMENT_ERROR + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_MODULE_HEALTH_STATUS_CHECK + *@userdata1[0:31] Target Huid + *@userdata2 <UNUSED> + *@devdesc NVDIMM failed module health status check due to + * ES error during health assessment + *@custdesc NVDIMM failed module health status check + */ + l_err_t = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_MODULE_HEALTH_STATUS_CHECK, + NVDIMM_ES_HEALTH_ASSESSMENT_ERROR, + TARGETING::get_huid(i_nvdimm), + 0x0, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + break; + } + + }while(0); + + if (l_err_t) + { + // Setup Trace + l_err_t->collectTrace( NVDIMM_COMP_NAME ); + + // Add reg traces to the error log + NVDIMM::UdNvdimmOPParms( l_RegInfo ).addToLog(l_err_t); + + // Callout BPM, Cable, and nvdimm + o_continue &= nvdimmBPMCableCallout(i_nvdimm, i_step, l_err_t); + } + + // Check for multiple errors and commit old error + if ((l_err) && (l_err_t)) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + + // If there was a new error, save off to l_err + if (l_err_t) + { + l_err = l_err_t; + l_err_t = nullptr; + } + + // Check all BPM high, nvdimm low cases + do + { + // Check ERROR_THRESHOLD_STATUS[1] + if ((l_RegInfo.Error_Threshold_Status & ES_LIFETIME_ERROR) == ES_LIFETIME_ERROR) + { + /*@ + *@errortype + *@reasoncode NVDIMM_ES_LIFETIME_ERROR + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_MODULE_HEALTH_STATUS_CHECK + *@userdata1[0:31] Target Huid + *@userdata2 <UNUSED> + *@devdesc NVDIMM failed module health status check due to + * ES lifetime error + *@custdesc NVDIMM failed module health status check + */ + l_err_t = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_MODULE_HEALTH_STATUS_CHECK, + NVDIMM_ES_LIFETIME_ERROR, + TARGETING::get_huid(i_nvdimm), + 0x0, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + break; + } + + // Check ERROR_THRESHOLD_STATUS[2] + if ((l_RegInfo.Error_Threshold_Status & ES_TEMP_ERROR) == ES_TEMP_ERROR) + { + /*@ + *@errortype + *@reasoncode NVDIMM_ES_TEMP_ERROR + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_MODULE_HEALTH_STATUS_CHECK + *@userdata1[0:31] Target Huid + *@userdata2 <UNUSED> + *@devdesc NVDIMM failed module health status check due to + * ES temporary error + *@custdesc NVDIMM failed module health status check + */ + l_err_t = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_MODULE_HEALTH_STATUS_CHECK, + NVDIMM_ES_TEMP_ERROR, + TARGETING::get_huid(i_nvdimm), + 0x0, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + break; + } + + }while(0); + + if (l_err_t) + { + // Setup Trace + l_err_t->collectTrace( NVDIMM_COMP_NAME ); + + // Add reg traces to the error log + NVDIMM::UdNvdimmOPParms( l_RegInfo ).addToLog(l_err_t); + + // Callout nvdimm + o_continue &= nvdimmBPMCallout(i_nvdimm, i_step, l_err_t); + } + + // Check for multiple errors and commit old error + if ((l_err) && (l_err_t)) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + + // If there was a new error, save off to l_err + if (l_err_t) + { + l_err = l_err_t; + l_err_t = nullptr; + } + + // Check special pre arm case + if (i_step == HEALTH_PRE_ARM) + { + // Check ES_POLICY_NOT_SET[4] + if ((l_RegInfo.Set_ES_Policy_Status & ES_POLICY_NOT_SET) == ES_POLICY_NOT_SET) + { + /*@ + *@errortype + *@reasoncode NVDIMM_ES_POLICY_NOT_SET + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_MODULE_HEALTH_STATUS_CHECK + *@userdata1[0:31] Target Huid + *@userdata2 <UNUSED> + *@devdesc NVDIMM failed module health status check due to + * ES policy not being set during an arm + *@custdesc NVDIMM failed module health status check + */ + l_err_t = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_MODULE_HEALTH_STATUS_CHECK, + NVDIMM_ES_POLICY_NOT_SET, + TARGETING::get_huid(i_nvdimm), + 0x0, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + o_continue = false; + // Callout dimm but no deconfig and gard + l_err_t->addHwCallout( i_nvdimm, + HWAS::SRCI_PRIORITY_LOW, + HWAS::NO_DECONFIG, + HWAS::GARD_NULL); + } + } + + // Check for multiple errors and commit old error + if ((l_err) && (l_err_t)) + { + errlCommit( l_err, NVDIMM_COMP_ID ); + } + + // If there was a new error, save off to l_err + if (l_err_t) + { + l_err = l_err_t; + l_err_t = nullptr; + } + + return l_err; +} + +} // end NVDIMM namespace diff --git a/src/usr/isteps/nvdimm/nvdimmErrorLog.H b/src/usr/isteps/nvdimm/nvdimmErrorLog.H new file mode 100644 index 000000000..dae8e2f2f --- /dev/null +++ b/src/usr/isteps/nvdimm/nvdimmErrorLog.H @@ -0,0 +1,108 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/isteps/nvdimm/nvdimmErrorLog.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +#ifndef NVDIMM_ERROR_LOG_H__ +#define NVDIMM_ERROR_LOG_H__ + +#include <usr/errl/errlentry.H> +#include <targeting/common/commontargeting.H> +#include <targeting/common/util.H> +#include <targeting/common/utilFilter.H> +#include <i2c/eepromif.H> +#include <map> +#include "nvdimmdd.H" +#include "nvdimm.H" + +using namespace TARGETING; +using namespace EEPROM; + +// Trace definition +extern trace_desc_t* g_trac_nvdimm; + +namespace NVDIMM +{ + +/** + * @brief Function to read and save status registers for traces + * + * @param[in] i_nvdimm - nvdimm target with NV controller + * + * @param[out] o_RegInfo - the structure holding the register data + * + */ +void nvdimmTraceRegs(Target *i_nvdimm, nvdimm_reg_t& o_RegInfo); + +/** + * @brief Helper function for standard callout of an NVDIMM + * + * @param[in] i_nvdimm - nvdimm target + * + * @param[out] o_err - error log handler to be modified + * + * @return bool - true to commit log and continue, false to return + * the error log to caller and exit. + */ +bool nvdimmCalloutDimm(Target *i_nvdimm, uint8_t i_step, errlHndl_t& o_err); + +/** + * @brief Helper function for BPM/Cable high, NVDIMM low callout + * + * @param[in] i_nvdimm - nvdimm target + * + * @param[out] o_err - error log handler to be modified + * + * @return bool - true to commit log and continue, false to return + * the error log to caller and exit. + */ +bool nvdimmBPMCableCallout(Target *i_nvdimm, uint8_t i_step, errlHndl_t& o_err); + +/** + * @brief Helper function for BPM high, NVDIMM low callout + * + * @param[in] i_nvdimm - nvdimm target + * + * @param[out] o_err - error log handler to be modified + * + * @return bool - true to commit log and continue, false to return + * the error log to caller and exit. + */ +bool nvdimmBPMCallout(Target *i_nvdimm, uint8_t i_step, errlHndl_t& o_err); + +/** + * @brief Function checking the Health Status Registers for an nvdimm + * + * @param[in] i_nvdimm - nvdimm target + * + * @param[out] o_exit - bool to signify exit procedure + * + * @return errlHndl_t - Null if successful, otherwise a pointer to + * the error log. + */ +errlHndl_t nvdimmHealthStatusCheck(Target *i_nvdimm, uint8_t i_step, bool& o_continue); + +} //End NVDIMM namespace + + +#endif // NVDIMM_ERROR_LOG_H__ diff --git a/src/usr/isteps/nvdimm/nvdimm_update.C b/src/usr/isteps/nvdimm/nvdimm_update.C index 2e1f61c8c..6075a660f 100644 --- a/src/usr/isteps/nvdimm/nvdimm_update.C +++ b/src/usr/isteps/nvdimm/nvdimm_update.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018,2019 */ +/* Contributors Listed Below - COPYRIGHT 2018,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -26,6 +26,7 @@ #include "nvdimm.H" #include <isteps/nvdimm/nvdimm.H> #include <isteps/nvdimm/nvdimmreasoncodes.H> +#include "bpm_update.H" #include <initservice/istepdispatcherif.H> // sendProgressCode #include <util/utilmclmgr.H> // secure LID manager @@ -33,6 +34,7 @@ #include <devicefw/userif.H> #include <vpd/spdenums.H> #include <sys/time.h> +#include <vector> // Unique tracing for nvdimm update process const char NVDIMM_UPD[] = "NVDIMM_UPD"; @@ -41,7 +43,7 @@ TRAC_INIT(&g_trac_nvdimm_upd, NVDIMM_UPD, 2*KILOBYTE); // Easy macro replace for unit testing -// #define TRACUCOMP(args...) TRACFCOMP(args) +//#define TRACUCOMP(args...) TRACFCOMP(args) #define TRACUCOMP(args...) namespace NVDIMM @@ -144,8 +146,10 @@ typedef union { } nvdimm_cmd_status0_t; // A code update block is composed of this many bytes -const uint8_t BYTES_PER_BLOCK = 32; +constexpr uint8_t BYTES_PER_BLOCK = 32; +// Maximum allowed region write retries +constexpr uint8_t MAX_REGION_WRITE_RETRY_ATTEMPTS = 3; /////////////////////////////////////////////////////////////////////////////// // NVDIMM LID Image @@ -182,6 +186,7 @@ uint16_t NvdimmLidImage::getVersion() return o_version; } + const uint8_t * NvdimmLidImage::getHeaderAndSmartSignature(uint16_t & o_size) { o_size = 0; @@ -264,7 +269,10 @@ NvdimmInstalledImage::NvdimmInstalledImage(TARGETING::Target * i_nvDimm) : iv_dimm(i_nvDimm), iv_version(INVALID_VERSION), iv_manufacturer_id(INVALID_ID), iv_product_id(INVALID_ID), iv_timeout(INVALID_TIMEOUT), - iv_max_blocks_per_region(INVALID_REGION_BLOCK_SIZE) + iv_max_blocks_per_region(INVALID_REGION_BLOCK_SIZE), + iv_fw_update_mode_enabled(false), + iv_region_write_retries(0), + iv_blockSizeSupported(INVALID_BLOCK_SIZE) { // initialize to invalid values } @@ -350,12 +358,50 @@ errlHndl_t NvdimmInstalledImage::getVersion(uint16_t & o_version, return l_err; } +errlHndl_t NvdimmInstalledImage::getBlockWriteSizeSupported(uint64_t & o_blockSize) +{ + errlHndl_t l_err = nullptr; + + do { + if (iv_blockSizeSupported == INVALID_BLOCK_SIZE) + { + uint16_t version = INVALID_VERSION; + l_err = getVersion(version, 0); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm_upd, ERR_MRK"getBlockWriteSizeSupported: " + "Failed to get version for 0x%.8X NVDIMM", + TARGETING::get_huid(iv_dimm)); + break; + } + + // The block write is more prone to random system interrupt + // which does something funny to the i2c bus. + // v3.A has the timeout increased to mitigate that + if (version >= 0x3A00) + { + // version supports 32-byte block size + iv_blockSizeSupported = 32; + } + else + { + // default to word size max write + iv_blockSizeSupported = sizeof(uint16_t); + } + TRACFCOMP( g_trac_nvdimm_upd, ERR_MRK"getBlockWriteSizeSupported: " + "block size %d supported for 0x%.8X NVDIMM (version 0x%04X)", + iv_blockSizeSupported, TARGETING::get_huid(iv_dimm), + version ); + } + } while (0); + o_blockSize = iv_blockSizeSupported; + return l_err; +} errlHndl_t NvdimmInstalledImage::updateImage(NvdimmLidImage * i_lidImage) { errlHndl_t l_err = nullptr; - // need to always disable this after it gets enabled - bool l_fw_update_mode_enabled = false; + do { INITSERVICE::sendProgressCode(); //////////////////////////////////////////////////////////////////////// @@ -381,7 +427,7 @@ errlHndl_t NvdimmInstalledImage::updateImage(NvdimmLidImage * i_lidImage) TRACFCOMP(g_trac_nvdimm_upd,ERR_MRK"updateImage: " "NV controller is busy (0x%08X) for NVDIMM 0x%.8X", l_status.whole, TARGETING::get_huid(iv_dimm)); - /* + /*@ *@errortype *@moduleid UPDATE_IMAGE *@reasoncode NVDIMM_OPERATION_IN_PROGRESS @@ -398,11 +444,14 @@ errlHndl_t NvdimmInstalledImage::updateImage(NvdimmLidImage * i_lidImage) l_status.whole, ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); l_err->collectTrace( NVDIMM_COMP_NAME, 256 ); + nvdimmAddVendorLog(iv_dimm, l_err); l_err->addPartCallout( iv_dimm, HWAS::NV_CONTROLLER_PART_TYPE, HWAS::SRCI_PRIORITY_HIGH ); l_err->addProcedureCallout( HWAS::EPUB_PRC_HB_CODE, HWAS::SRCI_PRIORITY_LOW ); + nvdimmAddPage4Regs(iv_dimm,l_err); + nvdimmAddUpdateRegs(iv_dimm,l_err); break; } @@ -427,8 +476,6 @@ errlHndl_t NvdimmInstalledImage::updateImage(NvdimmLidImage * i_lidImage) TARGETING::get_huid(iv_dimm)); break; } - // Set this flag so we will disable the update mode on error - l_fw_update_mode_enabled = true; // 5. Clear the Firmware Operation status TRACUCOMP(g_trac_nvdimm_upd, "updateImage: step 5"); @@ -549,7 +596,7 @@ errlHndl_t NvdimmInstalledImage::updateImage(NvdimmLidImage * i_lidImage) "NVDIMM 0x%.8X: data checksums mismatch (calc host: 0x%X " "and nv: 0x%X) for first part (header + SMART signature)", TARGETING::get_huid(iv_dimm), hostCksm, nvCksm); - /* + /*@ *@errortype *@moduleid UPDATE_IMAGE *@reasoncode NVDIMM_CHECKSUM_ERROR @@ -571,6 +618,7 @@ errlHndl_t NvdimmInstalledImage::updateImage(NvdimmLidImage * i_lidImage) 0x0000), ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); l_err->collectTrace( NVDIMM_COMP_NAME, 256 ); + nvdimmAddVendorLog(iv_dimm, l_err); // maybe some data was altered on the NV controller l_err->addPartCallout( iv_dimm, @@ -579,6 +627,8 @@ errlHndl_t NvdimmInstalledImage::updateImage(NvdimmLidImage * i_lidImage) // possible code issue l_err->addProcedureCallout( HWAS::EPUB_PRC_HB_CODE, HWAS::SRCI_PRIORITY_LOW ); + nvdimmAddPage4Regs(iv_dimm,l_err); + nvdimmAddUpdateRegs(iv_dimm,l_err); break; } @@ -641,7 +691,6 @@ errlHndl_t NvdimmInstalledImage::updateImage(NvdimmLidImage * i_lidImage) // 12. Disable firmware update mode TRACUCOMP(g_trac_nvdimm_upd, "updateImage: step 12"); - l_fw_update_mode_enabled = false; // don't retry the disable on error l_err = changeFwUpdateMode(FW_UPDATE_MODE_DISABLED); if (l_err) { @@ -668,7 +717,7 @@ errlHndl_t NvdimmInstalledImage::updateImage(NvdimmLidImage * i_lidImage) // Reset controller to activate new firmware TRACUCOMP(g_trac_nvdimm_upd, "updateImage: resetController"); - l_err = resetController(); + l_err = nvdimmResetController(iv_dimm); if (l_err) { TRACFCOMP(g_trac_nvdimm_upd, ERR_MRK "updateImage: " @@ -701,7 +750,7 @@ errlHndl_t NvdimmInstalledImage::updateImage(NvdimmLidImage * i_lidImage) } while (0); // If update operation is aborted, we need to disable update mode - if (l_fw_update_mode_enabled) + if (iv_fw_update_mode_enabled) { TRACFCOMP(g_trac_nvdimm_upd, "updateImage: update was aborted, so disable FW_UPDATE_MODE"); errlHndl_t l_err2 = changeFwUpdateMode(FW_UPDATE_MODE_DISABLED); @@ -765,7 +814,7 @@ errlHndl_t NvdimmInstalledImage::updateImageData(NvdimmLidImage * i_lidImage) } if (fw_img_total_regions == 0) { - /* + /*@ *@errortype *@moduleid UPDATE_IMAGE_DATA *@reasoncode NVDIMM_ZERO_TOTAL_REGIONS @@ -787,6 +836,8 @@ errlHndl_t NvdimmInstalledImage::updateImageData(NvdimmLidImage * i_lidImage) 0x00000000), ERRORLOG::ErrlEntry::ADD_SW_CALLOUT ); l_err->collectTrace( NVDIMM_COMP_NAME, 256 ); + nvdimmAddPage4Regs(iv_dimm,l_err); + nvdimmAddUpdateRegs(iv_dimm,l_err); break; } @@ -812,11 +863,15 @@ errlHndl_t NvdimmInstalledImage::updateImageData(NvdimmLidImage * i_lidImage) break; } + uint8_t l_region_write_retries = 0; // local region write retry count uint16_t region = 0; while (region < fw_img_total_regions) { - if (region % 10 == 0) + if (region % 100 == 0) { + TRACFCOMP(g_trac_nvdimm_upd, + "updateImage: progress code for sending region %d", + region); INITSERVICE::sendProgressCode(); } TRACUCOMP(g_trac_nvdimm_upd, "updateImage: step 10.a - region 0x%04X", @@ -914,15 +969,17 @@ errlHndl_t NvdimmInstalledImage::updateImageData(NvdimmLidImage * i_lidImage) if (hostCksm != nvCksm) { TRACFCOMP(g_trac_nvdimm_upd, ERR_MRK"updateImageData: " - "Region %d of NVDIMM 0x%.8X: data checksums mismatch " + "Region %d out of %d on NVDIMM 0x%.8X: data checksums mismatch " "(calc host: 0x%X and nv: 0x%X)", - region, TARGETING::get_huid(iv_dimm), hostCksm, nvCksm); + region, fw_img_total_regions, + TARGETING::get_huid(iv_dimm), hostCksm, nvCksm); - /* + /*@ *@errortype *@moduleid UPDATE_IMAGE_DATA *@reasoncode NVDIMM_CHECKSUM_ERROR - *@userdata1 NVDIMM Target Huid + *@userdata1[0:31] NVDIMM Target Huid + *@userdata1[32:63] Retry count for this region *@userdata2[0:15] Host checksum calculated *@userdata2[16:31] NV checksum returned *@userdata2[32:47] size of data for checksum @@ -934,18 +991,44 @@ errlHndl_t NvdimmInstalledImage::updateImageData(NvdimmLidImage * i_lidImage) ERRORLOG::ERRL_SEV_PREDICTIVE, UPDATE_IMAGE_DATA, NVDIMM_CHECKSUM_ERROR, - TARGETING::get_huid(iv_dimm), + TWO_UINT32_TO_UINT64( + TARGETING::get_huid(iv_dimm), + l_region_write_retries), FOUR_UINT16_TO_UINT64( hostCksm, nvCksm, region, data_len), ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); - l_err->collectTrace( NVDIMM_COMP_NAME, 256 ); + nvdimmAddVendorLog(iv_dimm, l_err); l_err->addPartCallout( iv_dimm, HWAS::NV_CONTROLLER_PART_TYPE, HWAS::SRCI_PRIORITY_HIGH ); l_err->addProcedureCallout( HWAS::EPUB_PRC_HB_CODE, HWAS::SRCI_PRIORITY_LOW ); + nvdimmAddPage4Regs(iv_dimm,l_err); + nvdimmAddUpdateRegs(iv_dimm,l_err); + + // Under the total retry attempts per region? + if (l_region_write_retries < MAX_REGION_WRITE_RETRY_ATTEMPTS) + { + TRACFCOMP(g_trac_nvdimm_upd, ERR_MRK"updateImageData: " + "Region %d on NVDIMM 0x%.8X failed, retry %d", + region, TARGETING::get_huid(iv_dimm),l_region_write_retries); + l_err->collectTrace(NVDIMM_UPD, 512); + + // Change PREDICTIVE to INFORMATIONAL as this might be recoverable + l_err->setSev(ERRORLOG::ERRL_SEV_INFORMATIONAL); + + // Commit this log and retry region write + ERRORLOG::errlCommit(l_err, NVDIMM_COMP_ID); + l_err = nullptr; + + // Update total for this region + l_region_write_retries++; + // update total retries for entire NVDIMM + iv_region_write_retries++; + continue; + } break; } @@ -989,7 +1072,7 @@ errlHndl_t NvdimmInstalledImage::changeFwUpdateMode(fw_update_mode i_mode) ((i_mode == FW_UPDATE_MODE_DISABLED) && (opStatus.fw_ops_update_mode == 0))) ) { - /* + /*@ *@errortype *@moduleid CHANGE_FW_UPDATE_MODE *@reasoncode NVDIMM_UPDATE_MODE_UNCHANGED @@ -1009,11 +1092,25 @@ errlHndl_t NvdimmInstalledImage::changeFwUpdateMode(fw_update_mode i_mode) 0x00, 0x00), ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); l_err->collectTrace( NVDIMM_COMP_NAME, 256 ); + nvdimmAddVendorLog(iv_dimm, l_err); l_err->addPartCallout( iv_dimm, HWAS::NV_CONTROLLER_PART_TYPE, HWAS::SRCI_PRIORITY_HIGH ); l_err->addProcedureCallout( HWAS::EPUB_PRC_HB_CODE, HWAS::SRCI_PRIORITY_LOW ); + nvdimmAddPage4Regs(iv_dimm,l_err); + nvdimmAddUpdateRegs(iv_dimm,l_err); + } + else + { + if (opStatus.fw_ops_update_mode == 1) + { + iv_fw_update_mode_enabled = true; + } + else + { + iv_fw_update_mode_enabled = false; + } } } } @@ -1025,8 +1122,9 @@ errlHndl_t NvdimmInstalledImage::waitFwOpsBlockReceived() { errlHndl_t l_err = nullptr; - // retry for a total of 100ms - uint32_t timeout_ms_val = 100; + // retry for a total of 500ms + const uint32_t MAX_WAIT_FOR_OPS_BLOCK_RECEIVED = 500; + uint32_t timeout_ms_val = MAX_WAIT_FOR_OPS_BLOCK_RECEIVED; bool blockReceived = false; fw_ops_status_t opStatus; @@ -1042,6 +1140,7 @@ errlHndl_t NvdimmInstalledImage::waitFwOpsBlockReceived() TARGETING::get_huid(iv_dimm), timeout_ms_val); break; } + if (!opStatus.fw_ops_block_received) { // wait 1 millisecond between checking status @@ -1066,7 +1165,13 @@ errlHndl_t NvdimmInstalledImage::waitFwOpsBlockReceived() if (!blockReceived && !l_err) { - /* + TRACFCOMP(g_trac_nvdimm_upd, ERR_MRK"waitFwOpsBlockReceived: " + "NVDIMM 0x%.8X FIRMWARE_OPS_STATUS (timeout: %d ms) " + "-- Last status: 0x%02X", + TARGETING::get_huid(iv_dimm), MAX_WAIT_FOR_OPS_BLOCK_RECEIVED, + opStatus.whole); + + /*@ *@errortype *@moduleid WAIT_FW_OPS_BLOCK_RECEIVED *@reasoncode NVDIMM_BLOCK_NOT_RECEIVED @@ -1086,16 +1191,19 @@ errlHndl_t NvdimmInstalledImage::waitFwOpsBlockReceived() ( TWO_UINT8_TO_UINT16( 0x00, opStatus.whole), - 100, + MAX_WAIT_FOR_OPS_BLOCK_RECEIVED, timeout_ms_val ), ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); l_err->collectTrace(NVDIMM_COMP_NAME, 512 ); + nvdimmAddVendorLog(iv_dimm, l_err); l_err->addPartCallout( iv_dimm, HWAS::NV_CONTROLLER_PART_TYPE, HWAS::SRCI_PRIORITY_HIGH ); l_err->addProcedureCallout( HWAS::EPUB_PRC_HB_CODE, HWAS::SRCI_PRIORITY_LOW ); + nvdimmAddPage4Regs(iv_dimm,l_err); + nvdimmAddUpdateRegs(iv_dimm,l_err); } return l_err; @@ -1145,7 +1253,7 @@ errlHndl_t NvdimmInstalledImage::waitFwOpsComplete() if (!opsComplete && !l_err) { - /* + /*@ *@errortype *@moduleid WAIT_FW_OPS_COMPLETE *@reasoncode NVDIMM_FW_OPS_IN_PROGRESS_TIMEOUT @@ -1169,11 +1277,14 @@ errlHndl_t NvdimmInstalledImage::waitFwOpsComplete() ), ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); l_err->collectTrace(NVDIMM_COMP_NAME, 256 ); + nvdimmAddVendorLog(iv_dimm, l_err); l_err->addPartCallout( iv_dimm, HWAS::NV_CONTROLLER_PART_TYPE, HWAS::SRCI_PRIORITY_HIGH ); l_err->addProcedureCallout( HWAS::EPUB_PRC_HB_CODE, HWAS::SRCI_PRIORITY_LOW ); + nvdimmAddPage4Regs(iv_dimm,l_err); + nvdimmAddUpdateRegs(iv_dimm,l_err); } } return l_err; @@ -1234,6 +1345,103 @@ errlHndl_t NvdimmInstalledImage::clearFwOpsStatus() "NVDIMM 0x%.8X clear FIRMWARE_OPS_STATUS register failed", TARGETING::get_huid(iv_dimm)); } + else + { + // Verify expected bits cleared + + // Setup expected cleared status byte + fw_ops_status_t l_cleared_ops_status; + l_cleared_ops_status.whole = 0x00; + if (iv_fw_update_mode_enabled) + { + // set BIT 2 -- this should not be cleared by the command + l_cleared_ops_status.fw_ops_update_mode = 1; + } + + // Set some timeout so this doesn't cause endless loop + uint16_t timeout_val = INVALID_TIMEOUT; + l_err = getFwOpsTimeout(timeout_val); + // Note: potential error will just exit the while loop and be returned + + // convert seconds to ms value + // double the timeout to ensure enough time has elapsed for the clear + // note: doubling here instead of just doubling timeout_val since that + // variable is only a bit16 vs bit32 + uint32_t timeout_ms_val = timeout_val * 1000 * 2; + + fw_ops_status_t l_ops_status; + + while (!l_err) + { + l_err = nvdimmReadReg(iv_dimm, FIRMWARE_OPS_STATUS, l_ops_status.whole); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm_upd, ERR_MRK"clearFwOpsStatus: " + "NVDIMM 0x%.8X read FIRMWARE_OPS_STATUS register failed " + " (0x%02X)", + TARGETING::get_huid(iv_dimm), l_ops_status.whole); + break; + } + + // Exit if expected cleared status is found + if (l_ops_status.whole == l_cleared_ops_status.whole) + { + break; + } + + // wait 1 millisecond between checking status + if (timeout_ms_val > 0) + { + timeout_ms_val -= 1; + nanosleep(0, NS_PER_MSEC); + } + else + { + // timeout hit + TRACFCOMP(g_trac_nvdimm_upd, ERR_MRK"clearFwOpsStatus: " + "NVDIMM 0x%.8X FIRMWARE_OPS_STATUS register reads 0x%02X " + "instead of cleared value of 0x%02X after %lld seconds", + TARGETING::get_huid(iv_dimm), l_ops_status.whole, + l_cleared_ops_status.whole, timeout_val*2); + + /*@ + *@errortype + *@moduleid CLEAR_FW_OPS_STATUS + *@reasoncode NVDIMM_CLEAR_FW_OPS_STATUS_TIMEOUT + *@userdata1 NVDIMM Target Huid + *@userdata2[0:7] Last FIRMWARE_OPS_STATUS read + *@userdata2[8:15] Expected cleared status + *@userdata2[16:31] Reserved + *@userdata2[32:63] Timeout (seconds) + *@devdesc FIRMWARE_OPS_STATUS not cleared + *@custdesc NVDIMM not updated + */ + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_PREDICTIVE, + CLEAR_FW_OPS_STATUS, + NVDIMM_CLEAR_FW_OPS_STATUS_TIMEOUT, + TARGETING::get_huid(iv_dimm), + TWO_UINT16_ONE_UINT32_TO_UINT64 + ( + TWO_UINT8_TO_UINT16( + l_ops_status.whole, + l_cleared_ops_status.whole), + 0x0000, + timeout_val * 2 + ), + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + l_err->collectTrace(NVDIMM_COMP_NAME, 256); + l_err->addPartCallout( iv_dimm, + HWAS::NV_CONTROLLER_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH ); + l_err->addProcedureCallout( HWAS::EPUB_PRC_HB_CODE, + HWAS::SRCI_PRIORITY_LOW ); + + break; + } + } // end of while (!l_err) loop + } // end of Verify expected bits cleared + return l_err; } @@ -1317,7 +1525,7 @@ errlHndl_t NvdimmInstalledImage::byteRegionBlockTransfer(const uint8_t * i_data, } if (blocks_per_region > max_blocks_per_region) { - /* + /*@ *@errortype *@moduleid BYTE_REGION_BLOCK_TRANSFER *@reasoncode NVDIMM_DATA_SIZE_TOO_LARGE @@ -1352,7 +1560,7 @@ errlHndl_t NvdimmInstalledImage::byteRegionBlockTransfer(const uint8_t * i_data, if (i_data_size > (BYTES_PER_BLOCK*blocks_per_region)) { - /* + /*@ *@errortype *@moduleid BYTE_REGION_BLOCK_TRANSFER *@reasoncode NVDIMM_DATA_SIZE_INVALID @@ -1421,15 +1629,29 @@ errlHndl_t NvdimmInstalledImage::byteRegionBlockTransfer(const uint8_t * i_data, TRACFCOMP(g_trac_nvdimm_upd, ERR_MRK"byteRegionBlockTransfer: " "Unable to open page for BLOCK %d transfer of NVDIMM " "0x%.8X", blockNum, TARGETING::get_huid(iv_dimm)); + break; } size_t l_numBytes = BYTES_PER_BLOCK; uint8_t l_reg_addr = ADDRESS(TYPED_BLOCK_DATA_BYTE0); + + // Grab whether word or 32-byte block write is supported + uint64_t blockSizeSupported = INVALID_BLOCK_SIZE; + l_err = getBlockWriteSizeSupported(blockSizeSupported); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm_upd, ERR_MRK"byteRegionBlockTransfer: " + "Unable to grab maximum block write size for NVDIMM 0x%.8X", + TARGETING::get_huid(iv_dimm)); + break; + } + l_err = DeviceFW::deviceOp( DeviceFW::WRITE, iv_dimm, pCurrentBlockData, l_numBytes, - DEVICE_NVDIMM_ADDRESS(l_reg_addr) ); + DEVICE_NVDIMM_RAW_ADDRESS_WITH_BLOCKSIZE(l_reg_addr, blockSizeSupported) + ); if (l_err) { TRACFCOMP(g_trac_nvdimm_upd, ERR_MRK"byteRegionBlockTransfer: " @@ -1437,8 +1659,6 @@ errlHndl_t NvdimmInstalledImage::byteRegionBlockTransfer(const uint8_t * i_data, blockNum, l_reg_addr, TARGETING::get_huid(iv_dimm)); break; } - // increment to next block - pCurrentBlockData += BYTES_PER_BLOCK; // After a block has been transferred, verify that the 32-byte block // was received by polling FIRMWARE_OPS_STATUS offset for @@ -1449,10 +1669,39 @@ errlHndl_t NvdimmInstalledImage::byteRegionBlockTransfer(const uint8_t * i_data, TRACFCOMP(g_trac_nvdimm_upd, ERR_MRK"byteRegionBlockTransfer: " "Block %d read of FIRMWARE_OPS_STATUS failed on NVDIMM " " 0x%.8X", blockNum, TARGETING::get_huid(iv_dimm)); + + size_t tmpNumBytes = l_numBytes; + uint8_t tmpBuffer[tmpNumBytes]; + errlHndl_t l_err2 = DeviceFW::deviceOp( DeviceFW::READ, + iv_dimm, + tmpBuffer, + tmpNumBytes, + DEVICE_NVDIMM_ADDRESS(l_reg_addr) ); + if (l_err2) + { + TRACFCOMP(g_trac_nvdimm_upd, ERR_MRK"byteRegionBlockTransfer: " + "Block %d read from 0x%02X failed on NVDIMM 0x%.8X", + blockNum, l_reg_addr, TARGETING::get_huid(iv_dimm)); + l_err2->plid(l_err->plid()); + l_err2->collectTrace(NVDIMM_COMP_NAME); + l_err2->collectTrace(NVDIMM_UPD); + errlCommit(l_err2, NVDIMM_COMP_ID); + break; + } + else + { + TRACFBIN(g_trac_nvdimm_upd, "byteRegionBlockTransfer: Wrote block", pCurrentBlockData, l_numBytes); + TRACFBIN(g_trac_nvdimm_upd, "byteRegionBlockTransfer: Read-back block", tmpBuffer, l_numBytes); + } + break; } + // block of data successfully sent to NV controller TRACUCOMP(g_trac_nvdimm_upd,"byteRegionBlockTransfer: block 0x%02X successfully sent to NV controller", blockNum); + + // increment to next block + pCurrentBlockData += BYTES_PER_BLOCK; blockNum++; } @@ -1516,7 +1765,7 @@ errlHndl_t NvdimmInstalledImage::validateFwHeader() l_err = isFwOpsSuccess(opsSuccessful); if (!l_err && !opsSuccessful) { - /* + /*@ *@errortype *@moduleid VALIDATE_FW_HEADER *@reasoncode NVDIMM_FW_OPS_NOT_SUCCESSFUL @@ -1533,11 +1782,14 @@ errlHndl_t NvdimmInstalledImage::validateFwHeader() opsCmd.whole, ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); l_err->collectTrace(NVDIMM_COMP_NAME, 256 ); + nvdimmAddVendorLog(iv_dimm, l_err); l_err->addPartCallout( iv_dimm, HWAS::NV_CONTROLLER_PART_TYPE, HWAS::SRCI_PRIORITY_HIGH ); l_err->addProcedureCallout( HWAS::EPUB_PRC_HB_CODE, HWAS::SRCI_PRIORITY_LOW ); + nvdimmAddPage4Regs(iv_dimm,l_err); + nvdimmAddUpdateRegs(iv_dimm,l_err); } } } @@ -1565,7 +1817,7 @@ errlHndl_t NvdimmInstalledImage::commitFwRegion() l_err = isFwOpsSuccess(opsSuccessful); if (!l_err && !opsSuccessful) { - /* + /*@ *@errortype *@moduleid COMMIT_FW_REGION *@reasoncode NVDIMM_FW_OPS_NOT_SUCCESSFUL @@ -1582,11 +1834,14 @@ errlHndl_t NvdimmInstalledImage::commitFwRegion() opsCmd.whole, ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); l_err->collectTrace(NVDIMM_COMP_NAME, 256 ); + nvdimmAddVendorLog(iv_dimm, l_err); l_err->addPartCallout( iv_dimm, HWAS::NV_CONTROLLER_PART_TYPE, HWAS::SRCI_PRIORITY_HIGH ); l_err->addProcedureCallout( HWAS::EPUB_PRC_HB_CODE, HWAS::SRCI_PRIORITY_LOW ); + nvdimmAddPage4Regs(iv_dimm,l_err); + nvdimmAddUpdateRegs(iv_dimm,l_err); } } } @@ -1615,7 +1870,7 @@ errlHndl_t NvdimmInstalledImage::clearFwDataBlock() l_err = isFwOpsSuccess(ops_success); if (!l_err && !ops_success) { - /* + /*@ *@errortype *@moduleid CLEAR_FW_DATA_BLOCK *@reasoncode NVDIMM_FW_OPS_NOT_SUCCESSFUL @@ -1632,11 +1887,14 @@ errlHndl_t NvdimmInstalledImage::clearFwDataBlock() opsCmd.whole, ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); l_err->collectTrace(NVDIMM_COMP_NAME, 256 ); + nvdimmAddVendorLog(iv_dimm, l_err); l_err->addPartCallout( iv_dimm, HWAS::NV_CONTROLLER_PART_TYPE, HWAS::SRCI_PRIORITY_HIGH ); l_err->addProcedureCallout( HWAS::EPUB_PRC_HB_CODE, HWAS::SRCI_PRIORITY_LOW ); + nvdimmAddPage4Regs(iv_dimm,l_err); + nvdimmAddUpdateRegs(iv_dimm,l_err); } } } @@ -1664,7 +1922,7 @@ errlHndl_t NvdimmInstalledImage::validateFwImage() // create an error if operation not successful if (!l_err && !opsSuccessful) { - /* + /*@ *@errortype *@moduleid VALIDATE_FW_IMAGE *@reasoncode NVDIMM_FW_OPS_NOT_SUCCESSFUL @@ -1681,12 +1939,14 @@ errlHndl_t NvdimmInstalledImage::validateFwImage() opsCmd.whole, ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); l_err->collectTrace(NVDIMM_COMP_NAME, 256 ); + nvdimmAddVendorLog(iv_dimm, l_err); l_err->addPartCallout( iv_dimm, HWAS::NV_CONTROLLER_PART_TYPE, HWAS::SRCI_PRIORITY_HIGH ); l_err->addProcedureCallout( HWAS::EPUB_PRC_HB_CODE, HWAS::SRCI_PRIORITY_LOW ); - + nvdimmAddPage4Regs(iv_dimm,l_err); + nvdimmAddUpdateRegs(iv_dimm,l_err); } } } @@ -1694,41 +1954,6 @@ errlHndl_t NvdimmInstalledImage::validateFwImage() return l_err; } -errlHndl_t NvdimmInstalledImage::resetController() -{ - errlHndl_t l_err = nullptr; - - // If bit 0 is set, the module shall start a Reset Controller operation - l_err = nvdimmWriteReg(iv_dimm, NVDIMM_MGT_CMD0, 0x01); - if (l_err) - { - TRACFCOMP(g_trac_nvdimm_upd,ERR_MRK"resetController: NVDIMM 0x%.8X " - "write of 0x01 to NVDIMM_MGT_CMD0 register failed", - TARGETING::get_huid(iv_dimm)); - } - else - { - TRACUCOMP(g_trac_nvdimm_upd,"resetController: waiting 5 seconds after controller 0x%.8X reset", - TARGETING::get_huid(iv_dimm)); - - // sleep 5 seconds to allow for i2c controller to come back online - nanosleep(5,0); - - TRACUCOMP(g_trac_nvdimm_upd,"resetController: now check if NV controller is ready again", - TARGETING::get_huid(iv_dimm)); - - // Now wait until NV controller is ready again after reset - l_err = nvdimmReady(iv_dimm); - if (l_err) - { - TRACFCOMP(g_trac_nvdimm_upd,ERR_MRK"resetController: NV controller for " - "NVDIMM 0x%.8X is not reporting as ready after reset", - TARGETING::get_huid(iv_dimm)); - } - } - return l_err; -} - uint16_t NvdimmInstalledImage::crc16(const uint8_t * i_data, int i_data_size) { // From JEDEC JESD245B.01 document @@ -1769,6 +1994,9 @@ bool NvdimmsUpdate::runUpdateUsingLid(NvdimmLidImage * i_lidImage, errlHndl_t l_err = nullptr; for (auto pInstalledImage : i_list) { + TARGETING::Target * l_nvdimm = pInstalledImage->getNvdimmTarget(); + uint64_t l_nvdimm_huid = TARGETING::get_huid(l_nvdimm); + INITSERVICE::sendProgressCode(); bool updateNeeded = false; l_err = isUpdateNeeded(updateNeeded, i_lidImage, pInstalledImage); @@ -1785,14 +2013,69 @@ bool NvdimmsUpdate::runUpdateUsingLid(NvdimmLidImage * i_lidImage, } else if (updateNeeded) { + // shared trace variables + uint32_t l_installed_type = INVALID_TYPE; + l_err = pInstalledImage->getType(l_installed_type); + if (l_err) + { + // Continue updating other dimms + TRACFCOMP(g_trac_nvdimm_upd, + ERR_MRK"NvdimmsUpdate::runUpdateUsingLid() - " + "Unable to get nvdimm[0x%.8X] installed image type. " + "RC=0x%X, PLID=0x%.8X", l_nvdimm_huid, + ERRL_GETRC_SAFE(l_err), ERRL_GETPLID_SAFE(l_err)); + commitPredictiveNvdimmError(l_err); + l_err = nullptr; + continue; + } + + uint16_t l_oldVersion = INVALID_VERSION; + l_err = pInstalledImage->getVersion(l_oldVersion); + if (l_err) + { + // This shouldn't happen as getVersion should return a + // cached version + TRACFCOMP(g_trac_nvdimm_upd, + ERR_MRK"NvdimmsUpdate::runUpdateUsingLid() - " + "Failed to find current NVDIMM level of %.8X. " + "RC=0x%X, PLID=0x%.8X", l_nvdimm_huid, + ERRL_GETRC_SAFE(l_err), ERRL_GETPLID_SAFE(l_err)); + commitPredictiveNvdimmError(l_err); + l_err = nullptr; + o_no_error_found = false; + continue; + } + // perform update for this DIMM with the current LID image TRACFCOMP(g_trac_nvdimm_upd, "NvdimmsUpdate::runUpdateUsingLid() - " - "now update nvdimm[0x%.8X]", - TARGETING::get_huid(pInstalledImage->getNvdimmTarget())); + "now update nvdimm[0x%.8X]", l_nvdimm_huid); TRACFCOMP(g_trac_nvdimm_upd,"Updating with flash size: 0x%08X", i_lidImage->getFlashImageSize()); + /*@ + *@errortype INFORMATIONAL + *@reasoncode NVDIMM_START_UPDATE + *@moduleid NVDIMM_RUN_UPDATE_USING_LID + *@userdata1 NVDIMM Target Huid + *@userdata2[0:15] Old level (current) + *@userdata2[16:31] Update image level (new) + *@userdata2[32:63] Installed type (manufacturer and product) + *@devdesc Start of the NVDIMM update of this controller + *@custdesc NVDIMM update started + */ + l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_INFORMATIONAL, + NVDIMM_RUN_UPDATE_USING_LID, + NVDIMM_START_UPDATE, + l_nvdimm_huid, + TWO_UINT16_ONE_UINT32_TO_UINT64( + l_oldVersion, i_lidImage->getVersion(), + l_installed_type), + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + l_err->collectTrace(NVDIMM_UPD, 256); + ERRORLOG::errlCommit(l_err, NVDIMM_COMP_ID); + l_err = nullptr; + l_err = pInstalledImage->updateImage(i_lidImage); if (l_err) { @@ -1803,14 +2086,150 @@ bool NvdimmsUpdate::runUpdateUsingLid(NvdimmLidImage * i_lidImage, TRACFCOMP(g_trac_nvdimm_upd, ERR_MRK"NvdimmsUpdate::runUpdateUsingLid() - " "NVDIMM 0x%.8X NV controller update failed. " - "RC=0x%X, PLID=0x%.8X", - TARGETING::get_huid(pInstalledImage->getNvdimmTarget()), + "RC=0x%X, PLID=0x%.8X", l_nvdimm_huid, ERRL_GETRC_SAFE(l_err), ERRL_GETPLID_SAFE(l_err)); commitPredictiveNvdimmError(l_err); l_err = nullptr; o_no_error_found = false; + continue; + } + else + { + // successfully updated this NVDIMM + + // Note: call for version should just return a saved value + uint16_t curVersion = INVALID_VERSION; + l_err = pInstalledImage->getVersion(curVersion); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm_upd, + ERR_MRK"NvdimmsUpdate::runUpdateUsingLid() - " + "Failed to find current NVDIMM level of %.8X after " + "successful update. RC=0x%X, PLID=0x%.8X", + l_nvdimm_huid, + ERRL_GETRC_SAFE(l_err), ERRL_GETPLID_SAFE(l_err)); + commitPredictiveNvdimmError(l_err); + l_err = nullptr; + } + + /*@ + *@errortype INFORMATIONAL + *@reasoncode NVDIMM_UPDATE_COMPLETE + *@moduleid NVDIMM_RUN_UPDATE_USING_LID + *@userdata1[0:31] NVDIMM Target Huid + *@userdata1[32:63] Total region write retries + *@userdata2[0:15] Previous level + *@userdata2[16:31] Current updated level + *@userdata2[32:63] Installed type (manufacturer and product) + *@devdesc Successful update of NVDIMM code + *@custdesc NVDIMM was successfully updated + */ + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_INFORMATIONAL, + NVDIMM_RUN_UPDATE_USING_LID, + NVDIMM_UPDATE_COMPLETE, + TWO_UINT32_TO_UINT64( + l_nvdimm_huid, + pInstalledImage->getRegionWriteRetries()), + TWO_UINT16_ONE_UINT32_TO_UINT64( + l_oldVersion, curVersion, + l_installed_type), + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT ); + l_err->collectTrace(NVDIMM_UPD, 512); + ERRORLOG::errlCommit(l_err, NVDIMM_COMP_ID); } } // end of updateNeeded + + ///////////////////////////////////////////////////////////////// + // Should not exit the nvdimm update stage until each nvdimm + // is running at the lid's code level + // (or a predictive error was logged for that nvdimm) + ///////////////////////////////////////////////////////////////// + + // Check NVDIMM is at the latest level and it is running from slot 1 + uint16_t l_curVersion = INVALID_VERSION; + l_err = pInstalledImage->getVersion(l_curVersion, true); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm_upd, + ERR_MRK"NvdimmsUpdate::runUpdateUsingLid() - " + "Failed to find current level of NVDIMM %.8X. " + "RC=0x%X, PLID=0x%.8X", l_nvdimm_huid, + ERRL_GETRC_SAFE(l_err), ERRL_GETPLID_SAFE(l_err)); + commitPredictiveNvdimmError(l_err); + l_err = nullptr; + o_no_error_found = false; + continue; + } + uint8_t l_slot_running = 0; + l_err = nvdimmGetRunningSlot(l_nvdimm, l_slot_running); + if (l_err) + { + TRACFCOMP(g_trac_nvdimm_upd, + ERR_MRK"NvdimmsUpdate::runUpdateUsingLid() - " + "Failed to find running slot of NVDIMM %.8X. " + "RC=0x%X, PLID=0x%.8X", l_nvdimm_huid, + ERRL_GETRC_SAFE(l_err), ERRL_GETPLID_SAFE(l_err)); + commitPredictiveNvdimmError(l_err); + l_err = nullptr; + o_no_error_found = false; + continue; + } + + if ((l_slot_running == 0) || (l_curVersion != i_lidImage->getVersion())) + { + // Not running latest code on this NVDIMM + TRACFCOMP(g_trac_nvdimm_upd, + ERR_MRK"NvdimmsUpdate::runUpdateUsingLid() - " + "NVDIMM %.8X running from slot %d with code level " + "0x%04X (lid level: 0x%04X)", + l_nvdimm_huid, l_slot_running, l_curVersion, + i_lidImage->getVersion()); + /*@ + *@errortype + *@reasoncode NVDIMM_NOT_RUNNING_LATEST_LEVEL + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_RUN_UPDATE_USING_LID + *@userdata1 NVDIMM Target Huid + *@userdata2[0:15] NVDIMM slot + *@userdata2[16:31] slot1 version + *@userdata2[32:47] latest version from lid + *@devdesc Encountered error after update while checking + * if NVDIMM is running latest code level + *@custdesc NVDIMM not running latest firmware level + */ + l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_RUN_UPDATE_USING_LID, + NVDIMM_NOT_RUNNING_LATEST_LEVEL, + l_nvdimm_huid, + FOUR_UINT16_TO_UINT64( + l_slot_running, + l_curVersion, + i_lidImage->getVersion(), + 0x0000), + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + + l_err->collectTrace( NVDIMM_COMP_NAME ); + + // Add callout of nvdimm with no deconfig/gard + l_err->addHwCallout( l_nvdimm, + HWAS::SRCI_PRIORITY_LOW, + HWAS::NO_DECONFIG, + HWAS::GARD_NULL); + + // Maybe vendor log will tell why it isn't running latest code level + nvdimmAddVendorLog(l_nvdimm, l_err); + commitPredictiveNvdimmError(l_err); + l_err = nullptr; + o_no_error_found = false; + } + else + { + TRACFCOMP(g_trac_nvdimm_upd, + "NvdimmsUpdate::runUpdateUsingLid() - " + "NVDIMM %.8X running from slot %d with latest level 0x%04X", + l_nvdimm_huid, l_slot_running, l_curVersion); + } } return o_no_error_found; } @@ -1826,12 +2245,15 @@ bool NvdimmsUpdate::runUpdate(void) // List of each installed NVDIMM type std::vector<NvdimmInstalledImage*> v_NVDIMM_16GB_list; std::vector<NvdimmInstalledImage*> v_NVDIMM_32GB_list; + BPM::bpmList_t NVDIMM_BPM_16GB_list; + BPM::bpmList_t NVDIMM_BPM_32GB_list; // Build up installed NVDIMM image lists for (auto l_nvdimm : iv_nvdimmList) { NvdimmInstalledImage * l_installed_image = new NvdimmInstalledImage(l_nvdimm); + l_err = l_installed_image->getType(l_installed_type); if (l_err) { @@ -1843,6 +2265,10 @@ bool NvdimmsUpdate::runUpdate(void) ERRL_GETPLID_SAFE(l_err)); commitPredictiveNvdimmError(l_err); o_no_error_found = false; + + // Delete the unused NvdimmInstalledImage pointer + delete l_installed_image; + continue; } @@ -1852,6 +2278,10 @@ bool NvdimmsUpdate::runUpdate(void) "0x%.8X NVDIMM is SMART_NVDIMM_16GB_TYPE", get_huid(l_nvdimm)); v_NVDIMM_16GB_list.push_back(l_installed_image); + + BPM::Bpm l_16gbBpm(l_nvdimm); + NVDIMM_BPM_16GB_list.push_back(l_16gbBpm); + } else if (l_installed_type == SMART_NVDIMM_32GB_TYPE) { @@ -1859,6 +2289,9 @@ bool NvdimmsUpdate::runUpdate(void) "0x%.8X NVDIMM is SMART_NVDIMM_32GB_TYPE", get_huid(l_nvdimm)); v_NVDIMM_32GB_list.push_back(l_installed_image); + + BPM::Bpm l_32gbBpm(l_nvdimm); + NVDIMM_BPM_32GB_list.push_back(l_32gbBpm); } else { @@ -1866,7 +2299,7 @@ bool NvdimmsUpdate::runUpdate(void) TRACFCOMP(g_trac_nvdimm_upd, "NvdimmsUpdate::runUpdate() - unknown " "nvdimm[%X] installed type 0x%04X, skipping update", TARGETING::get_huid(l_nvdimm), l_installed_type); - /* + /*@ *@errortype *@reasoncode NVDIMM_UNSUPPORTED_NVDIMM_TYPE *@moduleid NVDIMM_RUN_UPDATE @@ -1889,36 +2322,34 @@ bool NvdimmsUpdate::runUpdate(void) ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); l_err->collectTrace(NVDIMM_COMP_NAME, 256 ); l_err->collectTrace(NVDIMM_UPD, 256); + nvdimmAddVendorLog(l_nvdimm, l_err); l_err->addPartCallout( l_nvdimm, HWAS::NV_CONTROLLER_PART_TYPE, HWAS::SRCI_PRIORITY_HIGH ); l_err->addProcedureCallout( HWAS::EPUB_PRC_HB_CODE, HWAS::SRCI_PRIORITY_LOW ); + nvdimmAddPage4Regs(l_nvdimm,l_err); + nvdimmAddUpdateRegs(l_nvdimm,l_err); ERRORLOG::errlCommit(l_err, NVDIMM_COMP_ID); + + // Delete the unused NvdimmInstalledImage object + delete l_installed_image; + continue; } } do { - // First check that updatable NVDIMMs exist on the system - if ((v_NVDIMM_16GB_list.size() == 0) && - (v_NVDIMM_32GB_list.size() == 0)) - { - TRACFCOMP(g_trac_nvdimm_upd, "NvdimmsUpdate::runUpdate() - " - "No updatable NVDIMMs present on the system"); - break; - } - - ///////////////////////// - // @todo: remove this check when SMART provides updated 32GB image - // The current 32GB image will cause the future updating to fail - if (v_NVDIMM_16GB_list.size() == 0) + // First check that updatable NVDIMMs or BPMs exist on the system + if ( (v_NVDIMM_16GB_list.size() == 0) + && (v_NVDIMM_32GB_list.size() == 0) + && (NVDIMM_BPM_16GB_list.size() == 0) + && (NVDIMM_BPM_32GB_list.size() == 0)) { TRACFCOMP(g_trac_nvdimm_upd, "NvdimmsUpdate::runUpdate() - " - "Only 16GB NVDIMM type is supported right now for update"); + "No updatable NVDIMMs or BPMs present on the system"); break; } - ///////////////////////// if (INITSERVICE::spBaseServicesEnabled()) { @@ -1935,7 +2366,15 @@ bool NvdimmsUpdate::runUpdate(void) break; } - for(const auto& lid : info.lidIds) + // Both the config and firmware images are needed to perform an + // update on a BPM. So, get pointers to each in the CompInfo + // struct's vector of LID IDs. + MCL::LidInfo * bpm_16gb_fw = nullptr; + MCL::LidInfo * bpm_16gb_config = nullptr; + MCL::LidInfo * bpm_32gb_fw = nullptr; + MCL::LidInfo * bpm_32gb_config = nullptr; + + for(auto& lid : info.lidIds) { TRACFCOMP(g_trac_nvdimm,"LID ID=0x%08X, size=%d, vAddr=%p", lid.id, lid.size, lid.vAddr); @@ -1966,6 +2405,22 @@ bool NvdimmsUpdate::runUpdate(void) v_NVDIMM_32GB_list); } } + else if (lid.id == NVDIMM_32GB_BPM_FW_LIDID) + { + bpm_32gb_fw = &lid; + } + else if (lid.id == NVDIMM_32GB_BPM_CONFIG_LIDID) + { + bpm_32gb_config = &lid; + } + else if (lid.id == NVDIMM_16GB_BPM_FW_LIDID) + { + bpm_16gb_fw = &lid; + } + else if (lid.id == NVDIMM_16GB_BPM_CONFIG_LIDID) + { + bpm_16gb_config = &lid; + } else if (lid.id != NVDIMM_SIGNATURE_LIDID) { TRACFCOMP(g_trac_nvdimm, "NvdimmsUpdate::runUpdate() - " @@ -1975,6 +2430,26 @@ bool NvdimmsUpdate::runUpdate(void) } } + // Run BPM updates on NVDIMMs + BPM::BpmFirmwareLidImage fwImage_16gb(bpm_16gb_fw->vAddr, + bpm_16gb_fw->size); + + BPM::BpmFirmwareLidImage fwImage_32gb(bpm_32gb_fw->vAddr, + bpm_32gb_fw->size); + + BPM::BpmConfigLidImage configImage_16gb(bpm_16gb_config->vAddr, + bpm_16gb_config->size); + + BPM::BpmConfigLidImage configImage_32gb(bpm_32gb_config->vAddr, + bpm_32gb_config->size); + + BPM::runBpmUpdates(&NVDIMM_BPM_16GB_list, + &NVDIMM_BPM_32GB_list, + &fwImage_16gb, + &fwImage_32gb, + &configImage_16gb, + &configImage_32gb); + // Destructor automatically unloads the NVDIMM flash binary } else @@ -1987,6 +2462,16 @@ bool NvdimmsUpdate::runUpdate(void) } } while (0); // end of flash update section + // Clean up the pointers used in v_NVDIMM_16GB_list and v_NVDIMM_32GB_list + for (const auto& pInstalledImage : v_NVDIMM_16GB_list) + { + delete pInstalledImage; + } + for (const auto& pInstalledImage : v_NVDIMM_32GB_list) + { + delete pInstalledImage; + } + return o_no_error_found; } @@ -2001,7 +2486,7 @@ errlHndl_t NvdimmsUpdate::isUpdateNeeded(bool & o_update_needed, uint32_t curType = INVALID_TYPE; do { - const TARGETING::Target * l_dimm = i_cur_image->getNvdimmTarget(); + TARGETING::Target * l_dimm = i_cur_image->getNvdimmTarget(); // check Types match (same manufacturer and product) lidType = i_lid_image->getType(); @@ -2038,7 +2523,7 @@ errlHndl_t NvdimmsUpdate::isUpdateNeeded(bool & o_update_needed, "isUpdateNeeded(): non-updatable SMART NVDIMM 0x%.8X " "(0x%04X)", TARGETING::get_huid(l_dimm), le16toh(curVersion)); - /* + /*@ *@errortype *@reasoncode NVDIMM_UPDATE_NOT_SUPPORTED *@moduleid NVDIMM_IS_UPDATE_NEEDED @@ -2046,9 +2531,9 @@ errlHndl_t NvdimmsUpdate::isUpdateNeeded(bool & o_update_needed, *@userdata1[32:63] NVDIMM Target Huid *@userdata2 NVDIMM type (manufacturer and product) *@devdesc Unable to update an NVDIMM at this code level - *@custdesc NVDIMM not updated + *@custdesc Unsupported level of NVDIMM hardware */ - l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, + l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_UNRECOVERABLE, NVDIMM_IS_UPDATE_NEEDED, NVDIMM_UPDATE_NOT_SUPPORTED, TWO_UINT32_TO_UINT64( @@ -2057,9 +2542,15 @@ errlHndl_t NvdimmsUpdate::isUpdateNeeded(bool & o_update_needed, curType, ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); l_err->collectTrace( NVDIMM_UPD, 256 ); + nvdimmAddVendorLog(const_cast<TARGETING::Target*>(l_dimm), + l_err); + l_err->addHwCallout( l_dimm, + HWAS::SRCI_PRIORITY_HIGH, + HWAS::DECONFIG, + HWAS::GARD_Fatal); l_err->addPartCallout( l_dimm, HWAS::NV_CONTROLLER_PART_TYPE, - HWAS::SRCI_PRIORITY_HIGH ); + HWAS::SRCI_PRIORITY_MED ); l_err->addProcedureCallout( HWAS::EPUB_PRC_HB_CODE, HWAS::SRCI_PRIORITY_LOW ); break; diff --git a/src/usr/isteps/nvdimm/nvdimm_update.H b/src/usr/isteps/nvdimm/nvdimm_update.H index 37153b9c2..3f71dff56 100644 --- a/src/usr/isteps/nvdimm/nvdimm_update.H +++ b/src/usr/isteps/nvdimm/nvdimm_update.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -42,6 +42,7 @@ const uint16_t INVALID_ID = 0xFFFF; const uint16_t INVALID_VERSION = 0xFFFF; const uint16_t INVALID_TIMEOUT = 0xFFFF; const uint32_t INVALID_TYPE = 0xFFFFFFFF; +const uint8_t INVALID_BLOCK_SIZE = 0x00; // Type is combination of manufacturer id and product id const uint32_t SMART_NVDIMM_16GB_TYPE = 0x01945377; @@ -56,8 +57,13 @@ const uint32_t NVDIMM_SIGNATURE_LIDID = 0x80D00025; // ignore this one const uint32_t NVDIMM_16GB_LIDID = 0x81e00640; const uint32_t NVDIMM_32GB_LIDID = 0x81e00641; +const uint32_t NVDIMM_16GB_BPM_FW_LIDID = 0x81e00642; +const uint32_t NVDIMM_16GB_BPM_CONFIG_LIDID = 0x81e00644; + +const uint32_t NVDIMM_32GB_BPM_FW_LIDID = 0x81e00643; +const uint32_t NVDIMM_32GB_BPM_CONFIG_LIDID = 0x81e00645; + -// Firmware Update Mode settings for FIRMWARE_OPS_CMD enum fw_update_mode : uint8_t { FW_UPDATE_MODE_DISABLED = 0x00, @@ -215,15 +221,40 @@ class NvdimmInstalledImage const bool i_force_recollect = false); /** + * @brief Read the current slot that is running + * @param o_slot - 0 or 1 + * @return error if read operation fails + */ + errlHndl_t getRunningSlot(uint8_t & o_slot); + + /** * @brief Accessor to grab the current NVDIMM target * @return NVDIMM target */ - const TARGETING::Target * getNvdimmTarget(void) + TARGETING::Target * getNvdimmTarget(void) { return iv_dimm; } /** + * @brief Accessor to grab the amount of retries it took to write regions + * @return Cumulative total region write retries + */ + uint8_t getRegionWriteRetries(void) + { + return iv_region_write_retries; + } + + /** + * @brief Accessor for what write size is supported for this installed nvdimm + * Prior to level 0x3A, only word size supported + * Level 0x3A and beyond support 32 byte block writes + * @param[out] maximum number of bytes allowed per write + * @return block write size supported for this current nvdimm level + */ + errlHndl_t getBlockWriteSizeSupported(uint64_t & o_blockSize); + + /** * @brief Update the current NV Controller * @param Update using this image * @return error pointer if failure to update, else nullptr @@ -250,6 +281,16 @@ class NvdimmInstalledImage // maximum blocks allowed per region (REGION_BLOCK_SIZE) uint8_t iv_max_blocks_per_region; + // set to true when doing update + bool iv_fw_update_mode_enabled; + + // retry attempts for all regions + uint8_t iv_region_write_retries; + + // what size block can be written (2 or 32 byte) + uint64_t iv_blockSizeSupported; + + // Helper functions for updating the installed lid /** * @brief Transfer a region of bytes in multiple 32-byte blocks @@ -318,13 +359,6 @@ class NvdimmInstalledImage errlHndl_t isFwOpsSuccess(bool & o_success); /** - * @brief Reset NV controller. Resets controller and waits for it to - * come back online - * @return error if reset failed, else nullptr - */ - errlHndl_t resetController(); - - /** * @brief Updates the NV controller with the lid's image data * (minus header and signature) * @param i_lidImage - lid object with image data diff --git a/src/usr/isteps/nvdimm/nvdimmdd.C b/src/usr/isteps/nvdimm/nvdimmdd.C index 730fe0271..044be454b 100755 --- a/src/usr/isteps/nvdimm/nvdimmdd.C +++ b/src/usr/isteps/nvdimm/nvdimmdd.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2019 */ +/* Contributors Listed Below - COPYRIGHT 2011,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -35,6 +35,7 @@ // Includes // ---------------------------------------------- #include <string.h> +#include <time.h> #include <sys/time.h> #include <trace/interface.H> #include <errl/errlentry.H> @@ -67,16 +68,18 @@ TRAC_INIT( & g_trac_nvdimmr, "NVDIMMR", KILOBYTE ); // Easy macro replace for unit testing -#define TRACUCOMP(args...) TRACFCOMP(args) -//#define TRACUCOMP(args...) +//#define TRACUCOMP(args...) TRACFCOMP(args) +#define TRACUCOMP(args...) // ---------------------------------------------- // Defines // ---------------------------------------------- #define MAX_BYTE_ADDR 2 #define NVDIMM_MAX_RETRIES 2 +#define MAX_READ_RETRY_SECS 30 // ---------------------------------------------- +using namespace TARGETING; namespace { @@ -95,13 +98,83 @@ static bool errorIsRetryable(uint16_t reasonCode) namespace NVDIMM { -// Register the perform Op with the routing code for DIMMs. +// Register the perform Op router with the routing code for DIMMs. DEVICE_REGISTER_ROUTE( DeviceFW::WILDCARD, DeviceFW::NVDIMM, TARGETING::TYPE_DIMM, + nvdimmPerformOpRouter ); + +// Register the perform Op with the routing code for DIMMs. +DEVICE_REGISTER_ROUTE( DeviceFW::WILDCARD, + DeviceFW::NVDIMM_RAW, + TARGETING::TYPE_DIMM, nvdimmPerformOp ); // ------------------------------------------------------------------ +// nvdimmPerformOpRouter +// ------------------------------------------------------------------ +errlHndl_t nvdimmPerformOpRouter( DeviceFW::OperationType i_opType, + TARGETING::Target * i_target, + void * io_buffer, + size_t & io_buflen, + int64_t i_accessType, + va_list i_args ) +{ + errlHndl_t l_err(nullptr); + + TRACDCOMP( g_trac_nvdimm, + ENTER_MRK"nvdimmPerformOpRouter()" ); + + // Get the NVDIMM register's address, where data will be accessed from + // Although the data is being retrieved as a 64 bit value + // it is really a 16 bit value. Data passed via an arg list + // are retrieved in 64 bit chunks. + uint16_t l_registerAddress = + static_cast<uint16_t>(va_arg(i_args, uint64_t)); + + // Get a handle to the data buffer for easy referencing + uint8_t* l_data = static_cast<uint8_t*>(io_buffer); + + TRACUCOMP(g_trac_nvdimm, INFO_MRK"nvdimmPerformOpRouter(): " + "operation type=%d, target HUID=0x%.8X, access type=%d, " + "buffer length=%d, buffer data=0x%.8X, register address=0x%.8X", + static_cast<uint64_t>(i_opType), get_huid(i_target), i_accessType, + io_buflen, *l_data, l_registerAddress); + + // Make the right read/write call based on operation type + if( i_opType == DeviceFW::READ ) + { + l_err = nvdimmReadReg( i_target, + l_registerAddress, + *l_data, + PAGE_VERIFY); + if (!l_err) + { + TRACUCOMP (g_trac_nvdimm, INFO_MRK"nvdimmPerformOpRouter(): " + "Read data(0x%X) from register(0x%X)", + *l_data, l_registerAddress); + } + } + else if( i_opType == DeviceFW::WRITE ) + { + TRACUCOMP (g_trac_nvdimm, INFO_MRK"nvdimmPerformOpRouter(): " + "Writing data(0x%X) to register(0x%X) ...", + *l_data, l_registerAddress); + + l_err = nvdimmWriteReg( i_target, + l_registerAddress, + *l_data, + PAGE_VERIFY); + } + + TRACDCOMP(g_trac_nvdimm, + EXIT_MRK"nvdimmPerformOpRouter() returning with %s", + (l_err == nullptr ? "no error, success" : "an error, failure") ); + + return l_err; +} + +// ------------------------------------------------------------------ // nvdimmPerformOp // ------------------------------------------------------------------ errlHndl_t nvdimmPerformOp( DeviceFW::OperationType i_opType, @@ -116,6 +189,7 @@ errlHndl_t nvdimmPerformOp( DeviceFW::OperationType i_opType, nvdimm_addr_t i2cInfo; i2cInfo.offset = va_arg( i_args, uint64_t ); + i2cInfo.blockSize = va_arg( i_args, uint64_t ); TRACDCOMP( g_trac_nvdimm, ENTER_MRK"nvdimmPerformOp()" ); @@ -206,7 +280,7 @@ errlHndl_t nvdimmPerformOp( DeviceFW::OperationType i_opType, l_currentOpLen = l_snglChipSize - i2cInfo.offset; } - TRACFCOMP( g_trac_nvdimm, + TRACUCOMP( g_trac_nvdimm, "nvdimmPerformOp(): i_opType=%d " "e/p/dA=%d/%d/0x%X, offset=0x%X, len=0x%X, " "snglChipKB=0x%X, chipCount=0x%X, devSizeKB=0x%X", i_opType, @@ -216,7 +290,7 @@ errlHndl_t nvdimmPerformOp( DeviceFW::OperationType i_opType, // Printing mux info separately, if combined, nothing is displayed char* l_muxPath = i2cInfo.i2cMuxPath.toString(); - TRACFCOMP(g_trac_nvdimm, "nvdimmPerformOp(): " + TRACUCOMP(g_trac_nvdimm, "nvdimmPerformOp(): " "muxSelector=0x%X, muxPath=%s", i2cInfo.i2cMuxBusSelector, l_muxPath); @@ -326,7 +400,7 @@ errlHndl_t crossesNvdimmPageBoundary( uint64_t i_offset, errlHndl_t err = nullptr; - if(i_offset >= NVDIMM_PAGE_SIZE || (i_offset+i_buflen) >= NVDIMM_PAGE_SIZE) + if(i_offset >= NVDIMM_PAGE_SIZE || (i_offset+i_buflen) > NVDIMM_PAGE_SIZE) { TRACFCOMP( g_trac_nvdimm, ERR_MRK"crossesNvdimmPageBoundary() - offset 0x%X, buflen 0x%X" @@ -425,7 +499,7 @@ errlHndl_t nvdimmRead ( TARGETING::Target * i_target, if( err ) { TRACFCOMP(g_trac_nvdimm, - "Failed reading data: original read"); + ERR_MRK"nvdimmRead(): Failed reading data: original read"); break; } @@ -462,12 +536,13 @@ errlHndl_t nvdimmReadData( TARGETING::Target * i_target, ENTER_MRK"nvdimmReadData()"); do { + timespec_t l_CurTime, l_PrevTime; + clock_gettime(CLOCK_MONOTONIC, &l_PrevTime); + int retry = 0; /************************************************************/ /* Attempt read multiple times ONLY on retryable fails */ /************************************************************/ - for (uint8_t retry = 0; - retry <= NVDIMM_MAX_RETRIES; - retry++) + do { // Only write the byte address if we have data to write if( 0 != i_byteAddressSize ) @@ -488,12 +563,10 @@ errlHndl_t nvdimmReadData( TARGETING::Target * i_target, if( l_err ) { - TRACFCOMP(g_trac_nvdimm, - ERR_MRK"nvdimmReadData(): I2C Read-Offset failed on " - "%d/%d/0x%X, aS=%d", - i_i2cInfo.port, i_i2cInfo.engine, - i_i2cInfo.devAddr, - i_byteAddressSize); + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmReadData(): " + "I2C Read-Offset failed on %d/%d/0x%X, aS=%d", + i_i2cInfo.port, i_i2cInfo.engine, + i_i2cInfo.devAddr, i_byteAddressSize); // Printing mux info separately, if combined, nothing is displayed char* l_muxPath = i_i2cInfo.i2cMuxPath.toString(); @@ -526,7 +599,7 @@ errlHndl_t nvdimmReadData( TARGETING::Target * i_target, if( l_err ) { - TRACFCOMP(g_trac_nvdimm, + TRACUCOMP(g_trac_nvdimm, ERR_MRK"nvdimmReadData(): I2C Read failed on " "%d/%d/0x%0X", i_i2cInfo.port, i_i2cInfo.engine, @@ -534,7 +607,7 @@ errlHndl_t nvdimmReadData( TARGETING::Target * i_target, // Printing mux info separately, if combined, nothing is displayed char* l_muxPath = i_i2cInfo.i2cMuxPath.toString(); - TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmReadData(): " + TRACUCOMP(g_trac_nvdimm, ERR_MRK"nvdimmReadData(): " "muxSelector=0x%X, muxPath=%s", i_i2cInfo.i2cMuxBusSelector, l_muxPath); @@ -567,64 +640,35 @@ errlHndl_t nvdimmReadData( TARGETING::Target * i_target, else // Handle retryable error { // If op will be attempted again: save log and continue - if ( retry < NVDIMM_MAX_RETRIES ) + // Only save original retryable error + if ( err_retryable == nullptr ) { - // Only save original retryable error - if ( err_retryable == nullptr ) - { - // Save original retryable error - err_retryable = l_err; - - TRACFCOMP( g_trac_nvdimm, ERR_MRK"nvdimmReadData(): " - "Retryable Error rc=0x%X, eid=0x%X, tgt=0x%X, " - "retry/MAX=%d/%d. Save error and retry", - err_retryable->reasonCode(), - err_retryable->eid(), - TARGETING::get_huid(i_target), - retry, NVDIMM_MAX_RETRIES); - - err_retryable->collectTrace(NVDIMM_COMP_NAME); - } - else - { - // Add data to original retryable error - TRACFCOMP( g_trac_nvdimm, ERR_MRK"nvdimmReadData(): " - "Another Retryable Error rc=0x%X, eid=0x%X " - "plid=0x%X, tgt=0x%X, retry/MAX=%d/%d. " - "Delete error and retry", - l_err->reasonCode(), l_err->eid(), l_err->plid(), - TARGETING::get_huid(i_target), - retry, NVDIMM_MAX_RETRIES); - - ERRORLOG::ErrlUserDetailsString( - "Another Retryable ERROR found") - .addToLog(err_retryable); - - // Delete this new retryable error - delete l_err; - l_err = nullptr; - } + // Save original retryable error + err_retryable = l_err; + + TRACUCOMP( g_trac_nvdimm, ERR_MRK"nvdimmReadData(): " + "Retryable Error rc=0x%X, eid=0x%X, tgt=0x%X, " + "retry=%d. Save error and retry", + err_retryable->reasonCode(), + err_retryable->eid(), + TARGETING::get_huid(i_target), + retry); - // continue to retry - continue; + err_retryable->collectTrace(NVDIMM_COMP_NAME); } - else // no more retries: trace and break + else { - TRACFCOMP( g_trac_nvdimm, ERR_MRK"nvdimmReadData(): " - "Error rc=0x%X, eid=%d, tgt=0x%X. No More " - "Retries (retry/MAX=%d/%d). Returning Error", - l_err->reasonCode(), l_err->eid(), - TARGETING::get_huid(i_target), - retry, NVDIMM_MAX_RETRIES); - - l_err->collectTrace(NVDIMM_COMP_NAME); - - // break from retry loop - break; + // Delete this new retryable error + delete l_err; + l_err = nullptr; } - } + } // retryable error + // update current time + clock_gettime(CLOCK_MONOTONIC, &l_CurTime); + retry++; } // end of retry loop + while( (l_CurTime.tv_sec - l_PrevTime.tv_sec) < MAX_READ_RETRY_SECS ); // Handle saved retryable error, if any if (err_retryable) @@ -641,13 +685,29 @@ errlHndl_t nvdimmReadData( TARGETING::Target * i_target, .addToLog(err_retryable); errlCommit(err_retryable, NVDIMM_COMP_ID); + + // Add trace of what operation failed for returned error + TRACFCOMP(g_trac_nvdimm, + ERR_MRK"nvdimmReadData(): I2C Read failed on " + "%d/%d/0x%0X", + i_i2cInfo.port, i_i2cInfo.engine, i_i2cInfo.devAddr ); + + // Printing mux info separately, if combined, nothing is displayed + char* l_muxPath = i_i2cInfo.i2cMuxPath.toString(); + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmReadData(): " + "muxSelector=0x%X, muxPath=%s", + i_i2cInfo.i2cMuxBusSelector, + l_muxPath); + free(l_muxPath); + l_muxPath = nullptr; } else { // Since we eventually succeeded, delete original retryable error - TRACFCOMP(g_trac_nvdimm, "nvdimmReadData(): Op successful, " - "deleting saved retryable err eid=0x%X, plid=0x%X", - err_retryable->eid(), err_retryable->plid()); + TRACUCOMP(g_trac_nvdimm, "nvdimmReadData(): Op successful, " + "after %d retries. Deleting saved retryable err eid=" + "0x%X, plid=0x%X", + retry, err_retryable->eid(), err_retryable->plid()); delete err_retryable; err_retryable = nullptr; @@ -676,8 +736,6 @@ errlHndl_t nvdimmWrite ( TARGETING::Target * i_target, size_t byteAddrSize = 0; uint8_t * newBuffer = nullptr; bool needFree = false; - uint32_t data_left = 0; - uint32_t diff_wps = 0; TRACDCOMP( g_trac_nvdimm, ENTER_MRK"nvdimmWrite()" ); @@ -742,6 +800,17 @@ errlHndl_t nvdimmWrite ( TARGETING::Target * i_target, // Setup a max-size buffer of writePageSize size_t newBufLen = i_i2cInfo.writePageSize; + + // Break data into max supported i2c transfer size, if possible + // (speeds up i2c operation) + if ( (i_i2cInfo.blockSize != 0) && + (io_buflen >= i_i2cInfo.blockSize) && + ((io_buflen % i_i2cInfo.blockSize) == 0) ) + { + newBufLen = i_i2cInfo.blockSize; + } + assert(newBufLen > 0, "Unable to allocate 0 buffer size for nvdimmWrite()"); + newBuffer = static_cast<uint8_t*>(malloc( newBufLen )); needFree = true; @@ -756,16 +825,6 @@ errlHndl_t nvdimmWrite ( TARGETING::Target * i_target, while( total_bytes_written < io_buflen ) { - // Determine how much data can be written in this loop - // Can't go over a writePageSize boundary - - // Total data left to write - data_left = io_buflen - total_bytes_written; - - // Difference to next writePageSize boundary - diff_wps = i_i2cInfo.writePageSize - - (i_i2cInfo.offset % i_i2cInfo.writePageSize); - // Add the data the user wanted to write memcpy( newBuffer, &l_data_ptr[total_bytes_written], @@ -785,15 +844,13 @@ errlHndl_t nvdimmWrite ( TARGETING::Target * i_target, } TRACUCOMP(g_trac_nvdimm,"nvdimmWrite() Loop: %d/%d/0x%X " - "writeBuflen=%d, offset=0x%X, " - "bAS=%d, diffs=%d/%d", + "writeBuflen=%d, offset=0x%X, bAS=%d", i_i2cInfo.port, i_i2cInfo.engine, i_i2cInfo.devAddr, - newBufLen, i_i2cInfo.offset, byteAddrSize, - data_left, diff_wps); + newBufLen, i_i2cInfo.offset, byteAddrSize); // Printing mux info separately, if combined, nothing is displayed char* l_muxPath = i_i2cInfo.i2cMuxPath.toString(); - TRACFCOMP(g_trac_nvdimm, "nvdimmWrite(): " + TRACUCOMP(g_trac_nvdimm, "nvdimmWrite(): " "muxSelector=0x%X, muxPath=%s", i_i2cInfo.i2cMuxBusSelector, l_muxPath); @@ -815,6 +872,14 @@ errlHndl_t nvdimmWrite ( TARGETING::Target * i_target, // for this loop TRACFCOMP(g_trac_nvdimm, "Failed writing data: original nvdimm write"); + // total writes for the data size (divide by each write size) + size_t totalWritesNeeded = io_buflen/newBufLen; + // current write number (writes done + next one) + size_t currentWrite = total_bytes_written/newBufLen + 1; + TRACFCOMP( g_trac_nvdimm,ERR_MRK"nvdimmWrite(): " + "Tried to write out %d bytes out of %d total: " + "Failed on the %d of %d writes", newBufLen, io_buflen, + currentWrite, totalWritesNeeded ); break; } @@ -842,7 +907,7 @@ errlHndl_t nvdimmWrite ( TARGETING::Target * i_target, io_buflen = total_bytes_written; - TRACSCOMP( g_trac_nvdimmr, + TRACUCOMP( g_trac_nvdimmr, "NVDIMM WRITE END : Offset %.2X : Len %d", i_i2cInfo.offset, io_buflen ); } while( 0 ); @@ -874,30 +939,70 @@ errlHndl_t nvdimmWriteData( TARGETING::Target * i_target, ENTER_MRK"nvdimmWriteData()"); errlHndl_t err = nullptr; errlHndl_t err_retryable = nullptr; + size_t data_length; + do { - /***********************************************************/ - /* Attempt write multiple times ONLY on retryable fails */ - /***********************************************************/ - for (uint8_t retry = 0; - retry <= NVDIMM_MAX_RETRIES; - retry++) - { - // Do the actual data write - err = deviceOp( DeviceFW::WRITE, - i_target, - i_dataToWrite, - i_dataLen, - DEVICE_I2C_ADDRESS_OFFSET( - i_i2cInfo.port, - i_i2cInfo.engine, - i_i2cInfo.devAddr, - i_byteAddressSize, - reinterpret_cast<uint8_t*>( - i_byteAddress), - i_i2cInfo.i2cMuxBusSelector, - &(i_i2cInfo.i2cMuxPath) )); + /***********************************************************/ + /* Attempt write multiple times ONLY on retryable fails */ + /***********************************************************/ + for ( uint8_t retry = 0; retry <= NVDIMM_MAX_RETRIES; retry++) + { + // use a temporary variable to allow retry as the + // data_length could be altered by deviceOp() failure + data_length = i_dataLen; + // Do the actual data write + if ( i_dataLen == sizeof(uint16_t) ) + { + err = deviceOp( DeviceFW::WRITE, + i_target, + i_dataToWrite, + data_length, + DeviceFW::I2C, + I2C_SMBUS_RW_W_CMD_PARAMS( + DeviceFW::I2C_SMBUS_WORD_NO_PEC, + i_i2cInfo.engine, + i_i2cInfo.port, + i_i2cInfo.devAddr, + *(reinterpret_cast<uint8_t*>(i_byteAddress) + + (i_byteAddressSize-1)), + i_i2cInfo.i2cMuxBusSelector, + &(i_i2cInfo.i2cMuxPath)) ); + } + else if ( i_dataLen == 32 ) + { + err = deviceOp( DeviceFW::WRITE, + i_target, + i_dataToWrite, + data_length, + DeviceFW::I2C, + I2C_SMBUS_RW_W_CMD_PARAMS( + DeviceFW::I2C_SMBUS_BLOCK_NO_BYTE_COUNT, + i_i2cInfo.engine, + i_i2cInfo.port, + i_i2cInfo.devAddr, + *(reinterpret_cast<uint8_t*>(i_byteAddress) + + (i_byteAddressSize-1)), + i_i2cInfo.i2cMuxBusSelector, + &(i_i2cInfo.i2cMuxPath)) ); + } + else + { + err = deviceOp( DeviceFW::WRITE, + i_target, + i_dataToWrite, + data_length, + DEVICE_I2C_ADDRESS_OFFSET( + i_i2cInfo.port, + i_i2cInfo.engine, + i_i2cInfo.devAddr, + i_byteAddressSize, + reinterpret_cast<uint8_t*>( + i_byteAddress), + i_i2cInfo.i2cMuxBusSelector, + &(i_i2cInfo.i2cMuxPath) )); + } if ( err == nullptr ) { // Operation completed successfully @@ -911,7 +1016,7 @@ errlHndl_t nvdimmWriteData( TARGETING::Target * i_target, "Write Non-Retryable fail %d/%d/0x%X, " "ldl=%d, offset=0x%X, aS=%d, retry=%d", i_i2cInfo.port, i_i2cInfo.engine, - i_i2cInfo.devAddr, i_dataLen, + i_i2cInfo.devAddr, data_length, i_i2cInfo.offset, i_i2cInfo.addrSize, retry); // Printing mux info separately, if combined, nothing is displayed @@ -930,7 +1035,7 @@ errlHndl_t nvdimmWriteData( TARGETING::Target * i_target, } else // Handle retryable error { - TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmWriteData(): I2C " + TRACUCOMP(g_trac_nvdimm, ERR_MRK"nvdimmWriteData(): I2C " "Write retryable fail %d/%d/0x%X, " "ldl=%d, offset=0x%X, aS=%d, writePageSize = %x", i_i2cInfo.port, i_i2cInfo.engine, @@ -940,7 +1045,7 @@ errlHndl_t nvdimmWriteData( TARGETING::Target * i_target, // Printing mux info separately, if combined, nothing is displayed char* l_muxPath = i_i2cInfo.i2cMuxPath.toString(); - TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmWriteData(): " + TRACUCOMP(g_trac_nvdimm, ERR_MRK"nvdimmWriteData(): " "muxSelector=0x%X, muxPath=%s", i_i2cInfo.i2cMuxBusSelector, l_muxPath); @@ -956,7 +1061,7 @@ errlHndl_t nvdimmWriteData( TARGETING::Target * i_target, // Save original retryable error err_retryable = err; - TRACFCOMP( g_trac_nvdimm, ERR_MRK"nvdimmWriteData(): " + TRACUCOMP( g_trac_nvdimm, ERR_MRK"nvdimmWriteData(): " "Error rc=0x%X, eid=0x%X plid=0x%X, " "tgt=0x%X, retry/MAX=%d/%d. Save error " "and retry", @@ -971,7 +1076,7 @@ errlHndl_t nvdimmWriteData( TARGETING::Target * i_target, else { // Add data to original retryable error - TRACFCOMP( g_trac_nvdimm, ERR_MRK"nvdimmWriteData(): " + TRACUCOMP( g_trac_nvdimm, ERR_MRK"nvdimmWriteData(): " "Another Retryable Error rc=0x%X, eid=0x%X " "plid=0x%X, tgt=0x%X, retry/MAX=%d/%d. " "Delete error and retry", @@ -1016,6 +1121,24 @@ errlHndl_t nvdimmWriteData( TARGETING::Target * i_target, { if (err) { + // Trace failure write parameters + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmWriteData(): I2C " + "Write retryable fail %d/%d/0x%X, " + "ldl=%d, offset=0x%X, aS=%d, writePageSize = %x", + i_i2cInfo.port, i_i2cInfo.engine, + i_i2cInfo.devAddr, i_dataLen, + i_i2cInfo.offset, i_i2cInfo.addrSize, + i_i2cInfo.writePageSize); + + // Printing mux info separately, if combined, nothing is displayed + char* l_muxPath = i_i2cInfo.i2cMuxPath.toString(); + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmWriteData(): " + "muxSelector=0x%X, muxPath=%s", + i_i2cInfo.i2cMuxBusSelector, + l_muxPath); + free(l_muxPath); + l_muxPath = nullptr; + // commit original retryable error with new err PLID err_retryable->plid(err->plid()); TRACFCOMP(g_trac_nvdimm, "nvdimmWriteData(): Committing saved " @@ -1031,7 +1154,7 @@ errlHndl_t nvdimmWriteData( TARGETING::Target * i_target, else { // Since we eventually succeeded, delete original retryable error - TRACFCOMP(g_trac_nvdimm, "nvdimmWriteData(): Op successful, " + TRACUCOMP(g_trac_nvdimm, "nvdimmWriteData(): Op successful, " "deleting saved retryable err eid=0x%X, plid=0x%X", err_retryable->eid(), err_retryable->plid()); @@ -1221,7 +1344,7 @@ errlHndl_t nvdimmReadAttributes ( TARGETING::Target * i_target, // Printing mux info separately, if combined, nothing is displayed char* l_muxPath = o_i2cInfo.i2cMuxPath.toString(); - TRACFCOMP(g_trac_nvdimm, "nvdimmReadAttributes(): " + TRACUCOMP(g_trac_nvdimm, "nvdimmReadAttributes(): " "muxSelector=0x%X, muxPath=%s", o_i2cInfo.i2cMuxBusSelector, l_muxPath); @@ -1481,4 +1604,175 @@ void getNVDIMMs( std::list<EEPROM::EepromInfo_t>& o_info ) o_info.size()); } +/** + * @brief Helper structure to keep track of memory ranges + */ +typedef struct memGroups_t +{ + Target* proc; + uint64_t membottom; + uint64_t memtop; + size_t group; +} memGroups_t; + +/** + * @brief Comparator for memGroups_t to allow sorting, sorts big-to-small + * @param[in] Left-side of compare + * @param[in] Right-side of compare + * @return true:left-side is bigger, false:right-side is bigger + */ +bool compare_memGroups(memGroups_t& i_ls, + memGroups_t& i_rs) +{ + return (i_ls.memtop > i_rs.memtop); +} + +/** + * @brief Check if given address is owned by nvdimms and return + * a new address that isn't if it was + */ +uint64_t get_top_addr_with_no_nvdimms( uint64_t i_topAddr ) +{ + // Default to just returning the same value we got (no nvdimms) + uint64_t o_topAddr = i_topAddr; + + // On a NVDIMM system we need to make sure that we don't + // use the NV memory for the HOMER (or other reserved + // memory). Depending on the specific memory layout + // the NV memory could be placed at the top of memory + // where we would normally land. + + // NVDIMMs are only on Nimbus systems + if( TARGETING::MODEL_NIMBUS + !=TARGETING::targetService().getProcessorModel() ) + { + return o_topAddr; + } + + // Skip all of this checking if the input value is weird + if( i_topAddr == 0 ) + { + return o_topAddr; + } + + // Build up a list of possible memory ranges + std::vector<memGroups_t> l_memGroups; + + ATTR_PROC_MEM_BASES_type l_memBases = {0}; + ATTR_PROC_MEM_SIZES_type l_memSizes = {0}; + const size_t l_numGroups = sizeof(ATTR_PROC_MEM_SIZES_type) + /sizeof(l_memSizes[0]); + + TARGETING::TargetHandleList l_procList; + TARGETING::getAllChips(l_procList, TARGETING::TYPE_PROC); + assert(l_procList.size() != 0, "Empty proc list returned!"); + for (auto l_pProc : l_procList) + { + // Get the memory group ranges under this proc + assert(l_pProc->tryGetAttr<ATTR_PROC_MEM_BASES>(l_memBases), + "Unable to get ATTR_PROC_MEM_BASES attribute"); + assert(l_pProc->tryGetAttr<ATTR_PROC_MEM_SIZES>(l_memSizes), + "Unable to get ATTR_PROC_MEM_SIZES attribute"); + + for (size_t l_grp=0; l_grp < l_numGroups; l_grp++) + { + // Non-zero size means that there is memory present + if (l_memSizes[l_grp]) + { + memGroups_t l_mg; + l_mg.proc = l_pProc; + l_mg.membottom = l_memBases[l_grp]; + l_mg.memtop = l_memBases[l_grp] + l_memSizes[l_grp]; + l_mg.group = l_grp; + l_memGroups.push_back(l_mg); + } + } + } + + + // Loop through the groups from biggest to smallest + // l_top_homer_addr should hit the biggest one first, then we'll + // find the next biggest if the first match has a nvdimm in it. + std::sort( l_memGroups.begin(), l_memGroups.end(), compare_memGroups ); + for( auto l_memGroup : l_memGroups ) + { + bool l_foundNvdimm = false; + + // Get the array of mcas/group from the attribute + // The attr contains 8 8-bit entries, one entry per group + // The bits specify which mcas are included in the group + ATTR_MSS_MEM_MC_IN_GROUP_type l_memMcGroup = {0}; + assert(l_memGroup.proc->tryGetAttr<ATTR_MSS_MEM_MC_IN_GROUP> + (l_memMcGroup), + "Unable to get ATTR_MSS_MEM_MC_IN_GROUP attribute"); + + // Get list of mcas under this proc + TargetHandleList l_mcaList; + getChildAffinityTargets( l_mcaList, + l_memGroup.proc, + CLASS_UNIT, + TYPE_MCA ); + + // Loop through the mcas on this proc + for (const auto & l_mcaTarget : l_mcaList) + { + // Get the chip unit for this mca + ATTR_CHIP_UNIT_type l_mcaUnit = 0; + l_mcaUnit = l_mcaTarget->getAttr<ATTR_CHIP_UNIT>(); + + // Check if this mca is included in the memory group + const uint8_t l_mcMask = 0x80; + if (l_memMcGroup[l_memGroup.group] & (l_mcMask >> l_mcaUnit)) + { + // Get the list of dimms under this mca + TargetHandleList l_dimmList; + getChildAffinityTargets( l_dimmList, + l_mcaTarget, + CLASS_NA, + TYPE_DIMM ); + for (const auto & l_dimmTarget : l_dimmList) + { + if( isNVDIMM(l_dimmTarget) ) + { + l_foundNvdimm = true; + break; + } + } + if( l_foundNvdimm ) { break; } + } + } // for all MCAs + + // If we didn't find a nvdimm, we have a candidate for a valid + // top address + if( l_foundNvdimm ) + { + // Check if top addr is in this group's memory range + if( (o_topAddr >= l_memGroup.membottom) && + (o_topAddr <= l_memGroup.memtop) ) + { + TRACFCOMP(g_trac_nvdimm,"get_top_addr_with_no_nvdimms> Chosen address 0x%llX has nvdimms, cannot be used", + o_topAddr); + o_topAddr = 0; + } + } + else + { + // Since we are sorted by size, this must be the + // largest group without a nvdimm + if( o_topAddr != l_memGroup.memtop ) + { + o_topAddr = l_memGroup.memtop; + TRACFCOMP(g_trac_nvdimm,"get_top_addr_with_no_nvdimms> Choosing address 0x%llX as new top", + o_topAddr); + break; + } + } + } //for all memgroups + + assert( o_topAddr != 0, "get_top_addr_with_no_nvdimms> No valid memory group found without a NVDIMM" ); + + return o_topAddr; +} + + } // end namespace NVDIMM diff --git a/src/usr/isteps/nvdimm/nvdimmdd.H b/src/usr/isteps/nvdimm/nvdimmdd.H index 4d599b38a..88bc388c0 100755 --- a/src/usr/isteps/nvdimm/nvdimmdd.H +++ b/src/usr/isteps/nvdimm/nvdimmdd.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -69,6 +69,7 @@ struct nvdimm_addr_t uint64_t devSize_KB; // in kilobytes uint64_t chipCount; // number of chips making up nvdimm device uint64_t writeCycleTime; // in milliseconds + uint8_t blockSize; // size of write block supported for this nvdimm uint8_t i2cMuxBusSelector; TARGETING::EntityPath i2cMuxPath; @@ -86,12 +87,90 @@ struct nvdimm_addr_t devSize_KB(0), chipCount(0), writeCycleTime(0), + blockSize(0), i2cMuxBusSelector(I2C_MUX::NOT_APPLICABLE), i2cMuxPath() { } }; +/** + * @brief Structure of registers for error log traces + */ +struct nvdimm_reg_t +{ + uint8_t Module_Health; + uint8_t Module_Health_Status0; + uint8_t Module_Health_Status1; + uint8_t CSave_Status; + uint8_t CSave_Info; + uint8_t CSave_Fail_Info0; + uint8_t CSave_Fail_Info1; + uint8_t CSave_Timeout0; + uint8_t CSave_Timeout1; + uint8_t Error_Threshold_Status; + uint8_t NVDimm_Ready; + uint8_t NVDimm_CMD_Status0; + uint8_t Erase_Status; + uint8_t Erase_Fail_Info; + uint8_t Erase_Timeout0; + uint8_t Erase_Timeout1; + uint8_t Abort_CMD_Timeout; + uint8_t Set_ES_Policy_Status; + uint8_t Restore_Status; + uint8_t Restore_Fail_Info; + uint8_t Restore_Timeout0; + uint8_t Restore_Timeout1; + uint8_t Arm_Status; + uint8_t Arm_Fail_Info; + uint8_t Arm_Timeout0; + uint8_t Arm_Timeout1; + uint8_t Set_Event_Notification_Status; + uint8_t Encryption_Config_Status; + + /** + * @brief Construct a default nvdimm_reg_t + */ + nvdimm_reg_t() + : Module_Health(0), + Module_Health_Status0(0), + Module_Health_Status1(0), + CSave_Status(0), + CSave_Info(0), + CSave_Fail_Info0(0), + CSave_Fail_Info1(0), + CSave_Timeout0(0), + CSave_Timeout1(0), + Error_Threshold_Status(0), + NVDimm_Ready(0), + NVDimm_CMD_Status0(0), + Erase_Status(0), + Erase_Fail_Info(0), + Erase_Timeout0(0), + Erase_Timeout1(0), + Abort_CMD_Timeout(0), + Set_ES_Policy_Status(0), + Restore_Status(0), + Restore_Fail_Info(0), + Restore_Timeout0(0), + Restore_Timeout1(0), + Arm_Status(0), + Arm_Fail_Info(0), + Arm_Timeout0(0), + Arm_Timeout1(0), + Set_Event_Notification_Status(0), + Encryption_Config_Status(0) + { + } + + /** + * @brief Default deconstructor of nvdimm_reg_t + */ + ~nvdimm_reg_t() = default; + +}; + + /* * @brief Miscellaneous enums for NVDIMM */ @@ -138,6 +217,49 @@ errlHndl_t nvdimmPerformOp( DeviceFW::OperationType i_opType, int64_t i_accessType, va_list i_args ); +/** +* +* @brief Route the read/write operator (i_opType) to the correct +* nvdimmReadReg/nvdimmWriteReg call. +* +* @details This is essentially a wrapper around the nvdimmPerformOp method +* which is called via the nvdimmReadReg/nvdimmWriteReg call. This +* ensures that the page is set correctly whenever a NVDIMM register +* is accessed. +* +* @param[in] i_opType - Operation Type - See DeviceFW::OperationType in +* driververif.H +* +* @param[in] i_target - Target device. +* +* @param[in/out] io_buffer +* INPUT: Pointer to the data that will be written to the target +* device. +* OUTPUT: Pointer to the data that was read from the target device. +* +* @param[in/out] io_buflen +* INPUT: Length of the buffer to be written to target device. +* OUTPUT: Length of buffer that was written, or length of buffer +* to be read from target device. +* +* @param [in] i_accessType - Access Type - See DeviceFW::AccessType in +* usrif.H +* +* @param [in] i_args - This is an argument list for the device driver +* framework. This argument list consists of the internal offset +* to use on the slave I2C device. +* +* @return errlHndl_t - NULL if successful, otherwise a pointer to the +* error log. +* +*/ +errlHndl_t nvdimmPerformOpRouter( DeviceFW::OperationType i_opType, + TARGETING::Target * i_target, + void * io_buffer, + size_t & io_buflen, + int64_t i_accessType, + va_list i_args ); + /* * @brief On the NV Controller, the page is selected by writing to offset * 0x00 with the page you would like to switch too. e.g. to activate diff --git a/src/usr/isteps/nvdimm/plugins/errludP_nvdimm.H b/src/usr/isteps/nvdimm/plugins/errludP_nvdimm.H index 460add6f3..fdd94e01d 100644 --- a/src/usr/isteps/nvdimm/plugins/errludP_nvdimm.H +++ b/src/usr/isteps/nvdimm/plugins/errludP_nvdimm.H @@ -7,6 +7,7 @@ /* */ /* Contributors Listed Below - COPYRIGHT 2014,2019 */ /* [+] International Business Machines Corp. */ +/* [+] YADRO */ /* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ @@ -164,6 +165,84 @@ private: UdParserNvdimmParms & operator=(const UdParserNvdimmParms&); }; +/** + * @class UdParserNvdimmOPParms + * + * Parses UdNvdimmOPParms + */ +class UdParserNvdimmOPParms : public ERRORLOG::ErrlUserDetailsParser +{ +public: + /** + * @brief Constructor + */ + UdParserNvdimmOPParms() {} + + /** + * @brief Destructor + */ + virtual ~UdParserNvdimmOPParms() = default; + + /** + * @brief Parses string user detail data from an error log + * + * @param i_version Version of the data + * @param i_parse ErrlUsrParser object for outputting information + * @param i_pBuffer Pointer to buffer containing detail data + * @param i_buflen Length of the buffer + */ + virtual void parse(errlver_t i_version, + ErrlUsrParser & i_parser, + void * i_pBuffer, + const uint32_t i_buflen) const + { + const uint8_t* l_databuf = static_cast<const uint8_t*>(i_pBuffer); + i_parser.PrintHeading("NVDIMM I2C Register Traces"); + + // Memory Layout (1 byte each) + static const char* l_registers[] = { + "MODULE_HEALTH", + "MODULE_HEALTH_STATUS0", + "MODULE_HEALTH_STATUS1", + "CSAVE_STATUS", + "CSAVE_INFO", + "CSAVE_FAIL_INFO0", + "CSAVE_FAIL_INFO1", + "CSAVE_TIMEOUT_INFO0", + "CSAVE_TIMEOUT_INFO1", + "ERROR_THRESHOLD_STATUS", + "NVDIMM_READY", + "NVDIMM_CMD_STATUS0", + "ERASE_STATUS", + "ERASE_FAIL_INFO", + "ERASE_TIMEOUT0", + "ERASE_TIMEOUT1", + "ABORT_CMD_TIMEOUT", + "SET_ES_POLICY_STATUS", + "RESTORE_STATUS", + "RESTORE_FAIL_INFO", + "RESTORE_TIMEOUT0", + "RESTORE_TIMEOUT1", + "ARM_STATUS", + "ARM_FAIL_INFO", + "ARM_TIMEOUT0", + "ARM_TIMEOUT1", + "SET_EVENT_NOTIFICATION_STATUS", + "ENCRYPTION_CONFIG_STATUS" + }; + + for (uint32_t i = 0; i < i_buflen && + i < sizeof(l_registers) / sizeof(l_registers[0]); ++i) + { + i_parser.PrintNumber(l_registers[i], "%02X", l_databuf[i]); + } + } + + // Disabled + UdParserNvdimmOPParms(const UdParserNvdimmOPParms&) = delete; + UdParserNvdimmOPParms & operator=(UdParserNvdimmOPParms &) = delete; +}; + } // end NVDIMM namespace #endif diff --git a/src/usr/isteps/nvdimm/plugins/nvdimmUdParserFactory.H b/src/usr/isteps/nvdimm/plugins/nvdimmUdParserFactory.H index b27774b13..f208ac060 100644 --- a/src/usr/isteps/nvdimm/plugins/nvdimmUdParserFactory.H +++ b/src/usr/isteps/nvdimm/plugins/nvdimmUdParserFactory.H @@ -38,14 +38,14 @@ namespace NVDIMM { registerParser<NVDIMM::UdParserNvdimmParms> (NVDIMM_UDT_PARAMETERS); + registerParser<NVDIMM::UdParserNvdimmOPParms> + (NVDIMM_OP_PARAMETERS); } - private: - - UserDetailsParserFactory(const UserDetailsParserFactory &); - UserDetailsParserFactory & operator= - (const UserDetailsParserFactory &); + UserDetailsParserFactory(const UserDetailsParserFactory &) = delete; + UserDetailsParserFactory & operator=(UserDetailsParserFactory &) = delete; }; + }; #endif diff --git a/src/usr/isteps/nvdimm/runtime/nvdimm_rt.C b/src/usr/isteps/nvdimm/runtime/nvdimm_rt.C index 267fab07c..e8ad1d9e9 100644 --- a/src/usr/isteps/nvdimm/runtime/nvdimm_rt.C +++ b/src/usr/isteps/nvdimm/runtime/nvdimm_rt.C @@ -25,446 +25,1032 @@ /** * @file nvdimm_rt.C * - * @brief NVDIMM functions only needed for runtime + * @brief NVDIMM functions only needed for runtime. These functions include + * but are not limited to arming/disarming the NVDIMM along with methods + * to poll the arming and check the status of the arming. Checking the + * error state of the NVDIMM, getting a random number with the darn + * instruction and checking the ES or NVM health status. */ + +/// BPM - Backup Power Module + #include <trace/interface.H> #include <errl/errlentry.H> #include <errl/errlmanager.H> +#include <errl/errludstring.H> #include <util/runtime/rt_fwreq_helper.H> #include <targeting/common/attributes.H> #include <targeting/common/commontargeting.H> #include <targeting/common/util.H> #include <targeting/common/utilFilter.H> -#include <usr/runtime/rt_targeting.H> +#include <targeting/runtime/rt_targeting.H> #include <runtime/interface.h> +#include <arch/ppc.H> #include <isteps/nvdimm/nvdimmreasoncodes.H> +#include "../errlud_nvdimm.H" +#include "../nvdimmErrorLog.H" #include <isteps/nvdimm/nvdimm.H> // implements some of these #include "../nvdimm.H" // for g_trac_nvdimm +#include <sys/time.h> //#define TRACUCOMP(args...) TRACFCOMP(args) #define TRACUCOMP(args...) +using namespace TARGETING; +using namespace ERRORLOG; + namespace NVDIMM { +static constexpr uint64_t DARN_ERROR_CODE = 0xFFFFFFFFFFFFFFFFull; +static constexpr uint32_t MAX_DARN_ERRORS = 10; + /** -* @brief Notify PHYP of NVDIMM OCC protection status -*/ -errlHndl_t notifyNvdimmProtectionChange(TARGETING::Target* i_target, - const nvdimm_protection_t i_state) + * @brief Check nvdimm error state + * + * @param[in] i_nvdimm - nvdimm target + * + * @return bool - true if nvdimm is in any error state, false otherwise + */ +bool nvdimmInErrorState(Target *i_nvdimm) { - errlHndl_t l_err = nullptr; + TRACUCOMP(g_trac_nvdimm, ENTER_MRK"nvdimmInErrorState() HUID[%X]",get_huid(i_nvdimm)); - // default to send a not protected status - uint64_t l_nvdimm_protection_state = - hostInterfaces::HBRT_FW_NVDIMM_NOT_PROTECTED; + uint8_t l_statusFlag = i_nvdimm->getAttr<ATTR_NV_STATUS_FLAG>(); + bool l_ret = true; - TRACFCOMP( g_trac_nvdimm, ENTER_MRK - "notifyNvdimmProtectionChange: Target huid 0x%.8X, state %d", - get_huid(i_target), i_state); - do + // Just checking bit 1 for now, need to investigate these + // Should be checking NVDIMM_ARMED instead + if ((l_statusFlag & NSTD_VAL_ERASED) == 0) { - TARGETING::TargetHandleList l_nvdimmTargetList = - TARGETING::getProcNVDIMMs(i_target); + l_ret = false; + } - // Only send command if the processor has an NVDIMM under it - if (l_nvdimmTargetList.empty()) + // Also check the encryption error status + Target* l_sys = nullptr; + targetService().getTopLevelTarget( l_sys ); + assert(l_sys, "nvdimmInErrorState: no TopLevelTarget"); + if (l_sys->getAttr<ATTR_NVDIMM_ENCRYPTION_ENABLE>()) + { + ATTR_NVDIMM_ARMED_type l_armed_state = {}; + l_armed_state = i_nvdimm->getAttr<ATTR_NVDIMM_ARMED>(); + if (l_armed_state.encryption_error_detected) { - TRACFCOMP( g_trac_nvdimm, - "notifyNvdimmProtectionChange: No NVDIMM found under processor 0x%.8X", - get_huid(i_target)); - break; + l_ret = true; } + } + + TRACUCOMP(g_trac_nvdimm, EXIT_MRK"nvdimmInErrorState() HUID[%X]",get_huid(i_nvdimm)); + return l_ret; +} + - TARGETING::ATTR_NVDIMM_ARMED_type l_nvdimm_armed_state = - i_target->getAttr<TARGETING::ATTR_NVDIMM_ARMED>(); +// This could be made a generic utility +errlHndl_t nvdimm_getDarnNumber(size_t i_genSize, uint8_t* o_genData) +{ + assert(i_genSize % sizeof(uint64_t) == 0,"nvdimm_getDarnNumber() bad i_genSize"); - // Only notify protected state if NVDIMM controllers are - // armed and no error was or is detected - if (i_state == NVDIMM::PROTECTED) + errlHndl_t l_err = nullptr; + uint64_t* l_darnData = reinterpret_cast<uint64_t*>(o_genData); + + for (uint32_t l_loop = 0; l_loop < (i_genSize / sizeof(uint64_t)); l_loop++) + { + // Darn could return an error code + uint32_t l_darnErrors = 0; + + while (l_darnErrors < MAX_DARN_ERRORS) { - // Exit without notifying phyp if in error state - if (l_nvdimm_armed_state.error_detected) + // Get a 64-bit random number with the darn instruction + l_darnData[l_loop] = getDarn(); + + if ( l_darnData[l_loop] != DARN_ERROR_CODE ) { - // State can't go to protected after error is detected break; } - // check if we need to rearm the NVDIMM(s) - else if (!l_nvdimm_armed_state.armed) - { - bool nvdimms_armed = - NVDIMM::nvdimmArm(l_nvdimmTargetList); - if (nvdimms_armed) - { - // NVDIMMs are now armed and ready for backup - l_nvdimm_armed_state.armed = 1; - i_target->setAttr<TARGETING::ATTR_NVDIMM_ARMED>(l_nvdimm_armed_state); - - l_nvdimm_protection_state = hostInterfaces::HBRT_FW_NVDIMM_PROTECTED; - } - else - { - // If nvdimm arming failed, - // do NOT post that the dimms are now protected. - - // Remember this error, only try arming once - if (!l_nvdimm_armed_state.error_detected) - { - l_nvdimm_armed_state.error_detected = 1; - i_target->setAttr<TARGETING::ATTR_NVDIMM_ARMED>(l_nvdimm_armed_state); - } - - // Exit without notifying phyp of any protection change - break; - } - } else { - // NVDIMM already armed and no error found - l_nvdimm_protection_state = hostInterfaces::HBRT_FW_NVDIMM_PROTECTED; + l_darnErrors++; } } - else if (i_state == NVDIMM::UNPROTECTED_BECAUSE_ERROR) + + if (l_darnErrors == MAX_DARN_ERRORS) { - // Remember that this NV controller has an error so - // we don't rearm this until next IPL - if (!l_nvdimm_armed_state.error_detected) - { - l_nvdimm_armed_state.error_detected = 1; - i_target->setAttr<TARGETING::ATTR_NVDIMM_ARMED>(l_nvdimm_armed_state); - } - // still notify phyp that NVDIMM is Not Protected + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimm_getDarnNumber() reached MAX_DARN_ERRORS"); + /*@ + *@errortype + *@reasoncode NVDIMM_ENCRYPTION_MAX_DARN_ERRORS + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid NVDIMM_GET_DARN_NUMBER + *@userdata1 MAX_DARN_ERRORS + *@devdesc Error using darn instruction + *@custdesc NVDIMM encryption error + */ + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_PREDICTIVE, + NVDIMM_GET_DARN_NUMBER, + NVDIMM_ENCRYPTION_MAX_DARN_ERRORS, + MAX_DARN_ERRORS, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); + + l_err->collectTrace(NVDIMM_COMP_NAME); + break; } + } + return l_err; +} - // Get the Proc Chip Id - RT_TARG::rtChipId_t l_chipId = 0; - l_err = RT_TARG::getRtTarget(i_target, l_chipId); - if(l_err) +errlHndl_t nvdimm_getRandom(uint8_t* o_genData) +{ + errlHndl_t l_err = nullptr; + uint8_t l_xtraData[ENC_KEY_SIZE] = {0}; + + do + { + // Get a random number with the darn instruction + l_err = nvdimm_getDarnNumber(ENC_KEY_SIZE, o_genData); + if (l_err) { - TRACFCOMP( g_trac_nvdimm, - ERR_MRK"notifyNvdimmProtectionChange: getRtTarget ERROR" ); break; } - // send the notification msg - if ((nullptr == g_hostInterfaces) || - (nullptr == g_hostInterfaces->firmware_request)) + // Validate and update the random number + // Retry if more randomness required + do { - TRACFCOMP( g_trac_nvdimm, ERR_MRK"notifyNvdimmProtectionChange: " - "Hypervisor firmware_request interface not linked"); + //Get replacement data + l_err = nvdimm_getDarnNumber(ENC_KEY_SIZE, l_xtraData); + if (l_err) + { + break; + } + + }while (nvdimm_keyifyRandomNumber(o_genData, l_xtraData)); + + }while (0); + + return l_err; +} + +/* + * @brief Check the ES (enery source)/backup power module(BPM) health status of + * the individual NVDIMMs supplied in list + * + * @param[in] i_nvdimmTargetList - list of NVDIMMs to check the ES health of + * + * @return false if one or more NVDIMMs fail ES health check, else true + */ +bool nvDimmEsCheckHealthStatus(const TargetHandleList &i_nvdimmTargetList) +{ + TRACFCOMP(g_trac_nvdimm, ENTER_MRK"nvDimmEsCheckHealthStatus(): " + "Target list size(%d)", i_nvdimmTargetList.size()); + + // The minimum ES lifetime value + const uint8_t ES_LIFETIME_MINIMUM_REQUIREMENT = 0x62; // > 97% + + // The ES health check status flags for the different states of an + // ES health check + const uint8_t ES_HEALTH_CHECK_IN_PROGRESS_FLAG = 0x01; // bit 0 + const uint8_t ES_HEALTH_CHECK_SUCCEEDED_FLAG = 0x02; // bit 1 + const uint8_t ES_HEALTH_CHECK_FAILED_FLAG = 0x04; // bit 2 - // need to safely convert struct type into uint32_t - union { - TARGETING::ATTR_NVDIMM_ARMED_type tNvdimmArmed; - uint32_t nvdimmArmed_int; - } armed_state_union; - armed_state_union.tNvdimmArmed = l_nvdimm_armed_state; + // Handle to catch any errors + errlHndl_t l_err(nullptr); + + // The ES health check status from an ES health check call + uint8_t l_esHealthCheck(0); + + // Status of the accumulation of all calls related to the ES health check. + // If any one call is bad/fails, then this will be false, else it stays true + bool l_didEsHealthCheckPass(true); + + // Iterate thru the NVDIMMs checking the ES health status of each one. + // Going with the assumption that the caller waited the allotted time, + // roughly 20 to 30 minutes, after the start of an IPL. + // Success case: + // * ES health check initiated at start of the IPL, caller waited the + // allotted time (20 to 30 mins) before doing a health check, health + // check returned success and the lifetime meets the minimum threshold + // for a new BPM. + // Error cases are: + // * ES health check is in progress, will assume BPM is hung + // * ES health check failed + // * ES health check succeeded but lifetime does not meet a + // certain threshold + // * If none of the above apply (success case and other error cases), + // then assume the ES health check was never initiated at the start + // of the IPL + // For each of these error cases do a predictive callout + for (auto const l_nvdimm : i_nvdimmTargetList) + { + // Retrieve the Health Check status from the BPM + TRACFCOMP(g_trac_nvdimm, INFO_MRK"nvDimmEsCheckHealthStatus(): " + "Reading NVDIMM(0x%.8X) ES health check data, " + "register ES_CMD_STATUS0(0x%.2X)", + get_huid(l_nvdimm), ES_CMD_STATUS0); + + l_err = nvdimmReadReg(l_nvdimm, ES_CMD_STATUS0, l_esHealthCheck); + + if (l_err) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvDimmEsCheckHealthStatus(): " + "NVDIMM(0x%X) failed to read the ES health check " + "data, register ES_CMD_STATUS0(0x%.2X)", + get_huid(l_nvdimm), ES_CMD_STATUS0); + + l_err->setSev(ERRORLOG::ERRL_SEV_PREDICTIVE); + l_err->collectTrace(NVDIMM_COMP_NAME); + errlCommit(l_err, NVDIMM_COMP_ID); + + // Let the caller know something went amiss + l_didEsHealthCheckPass = false; + + // Proceed to next NVDIMM, better luck next time + continue; + } + + // Trace out the returned data for inspection + TRACFCOMP(g_trac_nvdimm, INFO_MRK"nvDimmEsCheckHealthStatus(): " + "NVDIMM(0x%X) returned value(0x%.2X) from the ES health " + "check data, register ES_CMD_STATUS0(0x%.2X)", + get_huid(l_nvdimm), l_esHealthCheck, ES_CMD_STATUS0); + + if (l_esHealthCheck & ES_HEALTH_CHECK_IN_PROGRESS_FLAG) + { + TRACFCOMP( g_trac_nvdimm, ERR_MRK"nvDimmEsCheckHealthStatus(): " + "Assuming caller waited the allotted time before " + "doing an ES health check on NVDIMM(0x%.8X), the BPM " + "is hung doing the ES health check.", + get_huid(l_nvdimm) ); /*@ * @errortype - * @severity ERRL_SEV_PREDICTIVE - * @moduleid NOTIFY_NVDIMM_PROTECTION_CHG - * @reasoncode NVDIMM_NULL_FIRMWARE_REQUEST_PTR - * @userdata1 HUID of processor target - * @userdata2[0:31] Requested protection state - * @userdata2[32:63] Current armed state - * @devdesc Unable to inform PHYP of NVDIMM protection - * @custdesc Internal firmware error + * @severity ERRL_SEV_PREDICTIVE + * @moduleid NVDIMM_ES_HEALTH_CHECK + * @reasoncode NVDIMM_ES_HEALTH_CHECK_IN_PROGRESS_FAILURE + * @userdata1 HUID of NVDIMM target + * @userdata2 ES health check status + * @devdesc Assuming caller waited the allotted time before + * doing an ES health check, then the BPM is hung doing + * the ES health check. + * @custdesc NVDIMM ES health check failed. */ - l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, - NOTIFY_NVDIMM_PROTECTION_CHG, - NVDIMM_NULL_FIRMWARE_REQUEST_PTR, - get_huid(i_target), - TWO_UINT32_TO_UINT64( - l_nvdimm_protection_state, - armed_state_union.nvdimmArmed_int) - ); - - l_err->addProcedureCallout(HWAS::EPUB_PRC_PHYP_CODE, + l_err = new ErrlEntry( ERRL_SEV_PREDICTIVE, + NVDIMM_ES_HEALTH_CHECK, + NVDIMM_ES_HEALTH_CHECK_IN_PROGRESS_FAILURE, + get_huid(l_nvdimm), + l_esHealthCheck, + ErrlEntry::NO_SW_CALLOUT ); + l_err->collectTrace(NVDIMM_COMP_NAME); + nvdimmAddVendorLog(l_nvdimm, l_err); + + // Add a BPM callout + l_err->addPartCallout( l_nvdimm, + HWAS::BPM_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + nvdimmAddPage4Regs(l_nvdimm,l_err); + // Collect the error + errlCommit(l_err, NVDIMM_COMP_ID); + + // Let the caller know something went amiss + l_didEsHealthCheckPass = false; + } + else if (l_esHealthCheck & ES_HEALTH_CHECK_FAILED_FLAG) + { + TRACFCOMP( g_trac_nvdimm, ERR_MRK"nvDimmEsCheckHealthStatus(): " + "Assuming caller waited the allotted time before " + "doing an ES health check on NVDIMM(0x%.8X), the BPM " + "reported a failure.", + get_huid(l_nvdimm) ); + + /*@ + * @errortype + * @severity ERRL_SEV_PREDICTIVE + * @moduleid NVDIMM_ES_HEALTH_CHECK + * @reasoncode NVDIMM_ES_HEALTH_CHECK_REPORTED_FAILURE + * @userdata1 HUID of NVDIMM target + * @userdata2 ES health check status + * @devdesc Assuming caller waited the allotted time before + * doing an ES health check, the BPM reported a failure + * while doing an ES health check. + * @custdesc NVDIMM ES health check failed. + */ + l_err = new ErrlEntry( ERRL_SEV_PREDICTIVE, + NVDIMM_ES_HEALTH_CHECK, + NVDIMM_ES_HEALTH_CHECK_REPORTED_FAILURE, + get_huid(l_nvdimm), + l_esHealthCheck, + ErrlEntry::NO_SW_CALLOUT ); + l_err->collectTrace(NVDIMM_COMP_NAME); + nvdimmAddVendorLog(l_nvdimm, l_err); + + // Add a BPM callout + l_err->addPartCallout( l_nvdimm, + HWAS::BPM_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + nvdimmAddPage4Regs(l_nvdimm,l_err); + // Collect the error + errlCommit(l_err, NVDIMM_COMP_ID); + + // Let the caller know something went amiss + l_didEsHealthCheckPass = false; + } + else if (l_esHealthCheck & ES_HEALTH_CHECK_SUCCEEDED_FLAG) + { + TRACFCOMP(g_trac_nvdimm, INFO_MRK"nvDimmEsCheckHealthStatus(): " + "Reading NVDIMM(0x%.8X) ES lifetime data, " + "register ES_LIFETIME(0x%.2X)", + get_huid(l_nvdimm), ES_LIFETIME); + + // The lifetime percentage + uint8_t l_lifetimePercentage(0); + + // Retrieve the Lifetime Percentage from the BPM + l_err = nvdimmReadReg(l_nvdimm, ES_LIFETIME, l_lifetimePercentage); + + if (l_err) + { + TRACFCOMP( g_trac_nvdimm, ERR_MRK"nvDimmEsCheckHealthStatus(): " + "NVDIMM(0x%.8X) failed to read the " + "ES_LIFETIME(0x%.2X) data", + get_huid(l_nvdimm), + ES_LIFETIME ); + + l_err->setSev(ERRORLOG::ERRL_SEV_PREDICTIVE); + l_err->collectTrace(NVDIMM_COMP_NAME); + errlCommit(l_err, NVDIMM_COMP_ID); + + // Let the caller know something went amiss + l_didEsHealthCheckPass = false; + } + else if (l_lifetimePercentage < ES_LIFETIME_MINIMUM_REQUIREMENT) + { + TRACFCOMP( g_trac_nvdimm, ERR_MRK"nvDimmEsCheckHealthStatus(): " + "ES health check on NVDIMM(0x%.8X) succeeded but " + "the BPM's lifetime(%d) does not meet the minimum " + "requirement(%d) needed to qualify as a new BPM.", + get_huid(l_nvdimm), + l_lifetimePercentage, + ES_LIFETIME_MINIMUM_REQUIREMENT ); + + /*@ + * @errortype + * @severity ERRL_SEV_PREDICTIVE + * @moduleid NVDIMM_ES_HEALTH_CHECK + * @reasoncode NVDIMM_ES_LIFETIME_MIN_REQ_NOT_MET + * @userdata1[00:31] HUID of NVDIMM target + * @userdata1[32:63] ES health check status + * @userdata2[00:31] Retrieved lifetime percentage + * @userdata2[32:63] lifetime minimum requirement + * @devdesc ES health check succeeded but the BPM's + * lifetime does not meet the minimum + * requirement needed to qualify as a + * new BPM. + * @custdesc NVDIMM ES health check failed + */ + l_err = new ErrlEntry( ERRL_SEV_PREDICTIVE, + NVDIMM_ES_HEALTH_CHECK, + NVDIMM_ES_LIFETIME_MIN_REQ_NOT_MET, + TWO_UINT32_TO_UINT64( + get_huid(l_nvdimm), + l_esHealthCheck), + TWO_UINT32_TO_UINT64( + l_lifetimePercentage, + ES_LIFETIME_MINIMUM_REQUIREMENT), + ErrlEntry::NO_SW_CALLOUT ); + l_err->collectTrace(NVDIMM_COMP_NAME); + nvdimmAddVendorLog(l_nvdimm, l_err); + + // Add a BPM callout + l_err->addPartCallout( l_nvdimm, + HWAS::BPM_PART_TYPE, HWAS::SRCI_PRIORITY_HIGH); + nvdimmAddPage4Regs(l_nvdimm,l_err); + // Collect the error + errlCommit(l_err, NVDIMM_COMP_ID); + + // Let the caller know something went amiss + l_didEsHealthCheckPass = false; + } // end else if (l_lifetimePercentage ... + else + { + TRACFCOMP( g_trac_nvdimm, ERR_MRK"nvDimmEsCheckHealthStatus(): " + "Success: ES health check on NVDIMM(0x%.8X) " + "succeeded and the BPM's lifetime(%d) meet's the " + "minimum requirement(%d) needed to qualify as " + "a new BPM.", + get_huid(l_nvdimm), + l_lifetimePercentage, + ES_LIFETIME_MINIMUM_REQUIREMENT ); + } + } // end else if (l_esHealthCheck & ES_HEALTH_CHECK_SUCCEEDED_FLAG) + else // Assume the ES health check was never initiated at + // the start of the IPL. + { + TRACFCOMP( g_trac_nvdimm, ERR_MRK"nvDimmEsCheckHealthStatus(): " + "The ES health check on NVDIMM(0x%.8X) shows no status " + "(in progress, fail or succeed) so assuming it was " + "never initiated at the start of the IPL.", + get_huid(l_nvdimm) ); + + /*@ + * @errortype + * @severity ERRL_SEV_PREDICTIVE + * @moduleid NVDIMM_ES_HEALTH_CHECK + * @reasoncode NVDIMM_ES_HEALTH_CHECK_NEVER_INITIATED + * @userdata1 HUID of NVDIMM target + * @userdata2 ES health check status + * @devdesc The ES health check shows no status (in progress, + * fail or succeed) so assuming it was never initiated + * at the start of the IPL. + * @custdesc NVDIMM ES health check failed. + */ + l_err = new ErrlEntry( ERRL_SEV_PREDICTIVE, + NVDIMM_ES_HEALTH_CHECK, + NVDIMM_ES_HEALTH_CHECK_NEVER_INITIATED, + get_huid(l_nvdimm), + l_esHealthCheck, + ErrlEntry::NO_SW_CALLOUT ); + l_err->collectTrace(NVDIMM_COMP_NAME); + nvdimmAddVendorLog(l_nvdimm, l_err); - break; + // Add a BPM callout + l_err->addPartCallout( l_nvdimm, + HWAS::BPM_PART_TYPE, + HWAS::SRCI_PRIORITY_HIGH); + nvdimmAddPage4Regs(l_nvdimm,l_err); + // Collect the error + errlCommit(l_err, NVDIMM_COMP_ID); + + // Let the caller know something went amiss + l_didEsHealthCheckPass = false; } + } // end for (auto const l_nvdimm : i_nvdimmTargetList) - TRACFCOMP( g_trac_nvdimm, - "notifyNvdimmProtectionChange: 0x%.8X processor NVDIMMS are " - "%s protected (current armed_state: 0x%02X)", - get_huid(i_target), - (l_nvdimm_protection_state == hostInterfaces::HBRT_FW_NVDIMM_PROTECTED)?"now":"NOT", - l_nvdimm_armed_state ); - - // Create the firmware_request request struct to send data - hostInterfaces::hbrt_fw_msg l_req_fw_msg; - memset(&l_req_fw_msg, 0, sizeof(l_req_fw_msg)); // clear it all - - // actual msg size (one type of hbrt_fw_msg) - uint64_t l_req_fw_msg_size = hostInterfaces::HBRT_FW_MSG_BASE_SIZE + - sizeof(l_req_fw_msg.nvdimm_protection_state); - - // Populate the firmware_request request struct with given data - l_req_fw_msg.io_type = - hostInterfaces::HBRT_FW_MSG_TYPE_NVDIMM_PROTECTION; - l_req_fw_msg.nvdimm_protection_state.i_procId = l_chipId; - l_req_fw_msg.nvdimm_protection_state.i_state = - l_nvdimm_protection_state; - - // Create the firmware_request response struct to receive data - hostInterfaces::hbrt_fw_msg l_resp_fw_msg; - uint64_t l_resp_fw_msg_size = sizeof(l_resp_fw_msg); - memset(&l_resp_fw_msg, 0, l_resp_fw_msg_size); - - // Make the firmware_request call - l_err = firmware_request_helper(l_req_fw_msg_size, - &l_req_fw_msg, - &l_resp_fw_msg_size, - &l_resp_fw_msg); - - } while (0); - - TRACFCOMP( g_trac_nvdimm, - EXIT_MRK "notifyNvdimmProtectionChange(%.8X, %d) - ERRL %.8X:%.4X", - get_huid(i_target), i_state, - ERRL_GETEID_SAFE(l_err), ERRL_GETRC_SAFE(l_err) ); + // Should not have any uncommitted errors + assert(l_err == NULL, "nvDimmEsCheckHealthStatus() - unexpected " + "uncommitted error found" ); - return l_err; -} + TRACFCOMP(g_trac_nvdimm, EXIT_MRK"nvDimmEsCheckHealthStatus(): " + "Returning %s", l_didEsHealthCheckPass == true ? "true" : "false"); + + return l_didEsHealthCheckPass; +} // end nvDimmEsCheckHealthStatus /** - * @brief This function polls the command status register for arm completion - * (does not indicate success or fail) + * @brief A wrapper around the call to nvDimmEsCheckHealthStatus * - * @param[in] i_nvdimm - nvdimm target with NV controller + * @see nvDimmEsCheckHealthStatus for more details * - * @param[out] o_poll - total polled time in ms - * - * @return errlHndl_t - Null if successful, otherwise a pointer to - * the error log. + * @return false if one or more NVDIMMs fail an ES health check, else true */ -errlHndl_t nvdimmPollArmDone(TARGETING::Target* i_nvdimm, - uint32_t &o_poll) +bool nvDimmEsCheckHealthStatusOnSystem() { - TRACUCOMP(g_trac_nvdimm, ENTER_MRK"nvdimmPollArmDone() nvdimm[%X]", TARGETING::get_huid(i_nvdimm) ); + TRACFCOMP(g_trac_nvdimm, ENTER_MRK"nvDimmEsCheckHealthStatusOnSystem()"); - errlHndl_t l_err = nullptr; + // Get the list of NVDIMM Targets from the system + TargetHandleList l_nvDimmTargetList; + nvdimm_getNvdimmList(l_nvDimmTargetList); - l_err = nvdimmPollStatus ( i_nvdimm, ARM, o_poll); + // Return status of doing a check health status + bool l_didEsHealthCheckPass = nvDimmEsCheckHealthStatus(l_nvDimmTargetList); - TRACUCOMP(g_trac_nvdimm, EXIT_MRK"nvdimmPollArmDone() nvdimm[%X]", - TARGETING::get_huid(i_nvdimm)); + TRACFCOMP(g_trac_nvdimm, EXIT_MRK"nvDimmEsCheckHealthStatusOnSystem(): " + "Returning %s", l_didEsHealthCheckPass == true ? "true" : "false" ); - return l_err; -} + return l_didEsHealthCheckPass; +} // end nvDimmCheckHealthStatusOnSystem -/** - * @brief This function checks the arm status register to make sure - * the trigger has been armed to ddr_reset_n +/* + * @brief Check the bad flash block percentage against a given maximum allowed. * - * @param[in] i_nvdimm - nvdimm target with NV controller + * @details This returns a tristate - 1 pass, 2 different fails + * If true is returned, then the check passed and + * o_badFlashBlockPercentage will contain what the retrieved + * flash block percentage is. + * If false is returned and the o_badFlashBlockPercentage is zero, then + * the check failed because of a register read fail + * If false is returned and the o_badFlashBlockPercentage is not zero, + * then the check failed because the retrieved bad flash block + * percentage exceeds the given maximum allowed * - * @return errlHndl_t - Null if successful, otherwise a pointer to - * the error log. + * @param[in] i_nvDimm - The NVDIMM to check + * @param[in] i_maxPercentageAllowed - The maximum percentage of bad flash + * block allowed + * @param[out] o_badFlashBlockPercentage - The retrieved bad flash block + * percentage from i_nvDimm, if no + * register read error. + * + * @return false if check failed or register read failed, else true */ -errlHndl_t nvdimmCheckArmSuccess(TARGETING::Target *i_nvdimm) +bool nvDimmCheckBadFlashBlockPercentage(TargetHandle_t i_nvDimm, + const uint8_t i_maxPercentageAllowed, + uint8_t &o_badFlashBlockPercentage) { - TRACUCOMP(g_trac_nvdimm, ENTER_MRK"nvdimmCheckArmSuccess() nvdimm[%X]", - TARGETING::get_huid(i_nvdimm)); + // Cache the HUID of the NVDIMM + uint32_t l_nvDimmHuid = get_huid( i_nvDimm ); - errlHndl_t l_err = nullptr; - uint8_t l_data = 0; + TRACFCOMP(g_trac_nvdimm, ENTER_MRK"nvDimmCheckBadFlashBlockPercentage(): " + "NVDIMM(0x%.4X), max bad flash blocks allowed(%d)", + l_nvDimmHuid, + i_maxPercentageAllowed); + + // The status of the check on the bad block percentage + bool l_didBadFlashBlockPercentageCheckPass(true); + + // The retrieved flash block percentage from register, initialize to zero + o_badFlashBlockPercentage = 0; + + // Handle to catch any errors + errlHndl_t l_err(nullptr); + + // Retrieve the percentage of bad blocks and validate + TRACDCOMP(g_trac_nvdimm, INFO_MRK"nvDimmCheckBadFlashBlockPercentage(): " + "Reading NVDIMM(0x%.8X) percentage of bad blocks from " + "register FLASH_BAD_BLK_PCT(0x%.4X)", + l_nvDimmHuid, FLASH_BAD_BLK_PCT); - l_err = nvdimmReadReg(i_nvdimm, ARM_STATUS, l_data); + l_err = nvdimmReadReg(i_nvDimm, + FLASH_BAD_BLK_PCT, + o_badFlashBlockPercentage); if (l_err) { - TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmCheckArmSuccess() nvdimm[%X]" - "failed to read arm status reg!",TARGETING::get_huid(i_nvdimm)); + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvDimmCheckBadFlashBlockPercentage(): " + "FAIL: NVDIMM(0x%.8X) failed to read the percentage of " + "bad blocks from register FLASH_BAD_BLK_PCT(0x%.4X), " + "marking as a fail", + l_nvDimmHuid, FLASH_BAD_BLK_PCT); + + l_err->setSev(ERRORLOG::ERRL_SEV_PREDICTIVE); + l_err->collectTrace(NVDIMM_COMP_NAME); + errlCommit(l_err, NVDIMM_COMP_ID); + + // Set up the fail state, so caller can determine that the fail was + // due to a register read error + l_didBadFlashBlockPercentageCheckPass = false; + o_badFlashBlockPercentage = 0; } - else if ((l_data & ARM_SUCCESS) != ARM_SUCCESS) + else { + // Trace out the returned data for inspection + TRACDCOMP(g_trac_nvdimm, INFO_MRK"nvDimmCheckBadFlashBlockPercentage(): " + "NVDIMM(0x%.8X) returned value (%d) from the " + "percentage of bad blocks, register " + "FLASH_BAD_BLK_PCT(0x%.4X)", + l_nvDimmHuid, + o_badFlashBlockPercentage, + FLASH_BAD_BLK_PCT); - TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmCheckArmSuccess() nvdimm[%X]" - "failed to arm!",TARGETING::get_huid(i_nvdimm)); - /*@ - *@errortype - *@reasoncode NVDIMM_ARM_FAILED - *@severity ERRORLOG_SEV_PREDICTIVE - *@moduleid NVDIMM_SET_ARM - *@userdata1[0:31] Related ops (0xff = NA) - *@userdata1[32:63] Target Huid - *@userdata2 <UNUSED> - *@devdesc Encountered error arming the catastrophic save - * trigger on NVDIMM. Make sure an energy source - * is connected to the NVDIMM and the ES policy - * is set properly - *@custdesc NVDIMM encountered error arming save trigger - */ - l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_PREDICTIVE, - NVDIMM_SET_ARM, - NVDIMM_ARM_FAILED, - TWO_UINT32_TO_UINT64(ARM, TARGETING::get_huid(i_nvdimm)), - 0x0, - ERRORLOG::ErrlEntry::NO_SW_CALLOUT ); - - l_err->collectTrace(NVDIMM_COMP_NAME, 256 ); - - // Failure to arm could mean internal NV controller error or - // even error on the battery pack. NVDIMM will lose persistency - // if failed to arm trigger - l_err->addPartCallout( i_nvdimm, - HWAS::NV_CONTROLLER_PART_TYPE, - HWAS::SRCI_PRIORITY_HIGH); - l_err->addPartCallout( i_nvdimm, - HWAS::BPM_PART_TYPE, - HWAS::SRCI_PRIORITY_MED); - l_err->addPartCallout( i_nvdimm, - HWAS::BPM_CABLE_PART_TYPE, - HWAS::SRCI_PRIORITY_MED); - } + // Check to see if the bad flash block percentage + // exceeds maximum allowed. + if (o_badFlashBlockPercentage > i_maxPercentageAllowed) + { + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvDimmCheckBadFlashBlockPercentage(): " + "FAIL: For NVDIMM (0x%.8X), the percentage of bad " + "flash blocks (%d), read from register " + "FLASH_BAD_BLK_PCT(0x%.4X), exceeds the maximum " + "percentage of bad flash blocks allowed (%d), marking " + "this as a fail", + l_nvDimmHuid, + o_badFlashBlockPercentage, + FLASH_BAD_BLK_PCT, + i_maxPercentageAllowed); - TRACUCOMP(g_trac_nvdimm, EXIT_MRK"nvdimmCheckArmSuccess() nvdimm[%X] ret[%X]", - TARGETING::get_huid(i_nvdimm), l_data); + // Set up the fail state, so caller can determine that the fail was + // due to percentage exceeding the max percentage allowed. + // Note: Leave the value in o_badFlashBlockPercentage so caller + // can inspect, if they wish + l_didBadFlashBlockPercentageCheckPass = false; + } + else + { + TRACFCOMP(g_trac_nvdimm, INFO_MRK"nvDimmCheckBadFlashBlockPercentage(): " + "SUCCESS: For NVDIMM (0x%.8X), the percentage of bad " + "flash blocks (%d) is less than or meets the maximum " + "percentage of bad flash blocks allowed (%d), " + "marking this as a pass", + l_nvDimmHuid, + o_badFlashBlockPercentage, + i_maxPercentageAllowed); - return l_err; + // Set up the pass state + // Note: Leave the value in o_badFlashBlockPercentage so caller + // can inspect, if they wish + l_didBadFlashBlockPercentageCheckPass = true; + } // end if (l_badFlashBlockPercentage > i_maxPercentageAllowed) + } // end if (l_err) ... else + + TRACFCOMP(g_trac_nvdimm, EXIT_MRK"nvDimmCheckBadFlashBlockPercentage(): " + "Returning %s", + l_didBadFlashBlockPercentageCheckPass == true ? "true" : "false" ); + + return l_didBadFlashBlockPercentageCheckPass; } -bool nvdimmArm(TARGETING::TargetHandleList &i_nvdimmTargetList) +/* + * @brief Check the flash error count against a given maximum allowed. + * + * @details This returns a tristate - 1 pass, 2 different fails + * If true is returned, then the check passed and + * o_readFlashErrorCount will contain what the retrieved + * flash error count is. + * If false is returned and the o_readFlashErrorCount is zero, then + * the check failed because of a register read fail + * If false is returned and the o_readFlashErrorCount is not zero, + * then the check failed because the retrieved flash error + * count exceeds the given maximum allowed + * + * @param[in] i_nvDimm - The NVDIMM to check + * @param[in] i_maxFlashErrorsAllowed - The maximum number of flash errors + * allowed + * @param[out] o_readFlashErrorCount - The retrieved bad flash error + * count from i_nvDimm, if no + * register read error. + * + * @return false if check failed or register read failed, else true + */ +bool nvDimmCheckFlashErrorCount(TargetHandle_t i_nvDimm, + const uint32_t i_maxFlashErrorsAllowed, + uint32_t &o_readFlashErrorCount) { - bool o_arm_successful = true; + // Cache the HUID of the NVDIMM + uint32_t l_nvDimmHuid = get_huid( i_nvDimm ); - TRACFCOMP(g_trac_nvdimm, ENTER_MRK"nvdimmArm() %d", - i_nvdimmTargetList.size()); + TRACFCOMP(g_trac_nvdimm, ENTER_MRK"nvDimmCheckFlashErrorCount(): " + "NVDIMM(0x%.4X), max flash errors allowed(%d)", + l_nvDimmHuid, + i_maxFlashErrorsAllowed); - errlHndl_t l_err = nullptr; + // The status of the check on the flash error count + bool l_didFlashErrorCountCheckPass(true); - for (auto const l_nvdimm : i_nvdimmTargetList) + // The retrieved flash error count from register, initialize to zero + o_readFlashErrorCount = 0; + + // Handle to catch any errors + errlHndl_t l_err(nullptr); + + // The retrieved flash error count from a register + uint8_t l_readFlashErrorCountByte(0); + + // Read the flash error count registers starting from MSB to LSB + for (int16_t l_flashErrorRegister = FLASH_ERROR_COUNT2; + l_flashErrorRegister >= FLASH_ERROR_COUNT0; + --l_flashErrorRegister) { - // skip if the nvdimm is in error state - if (NVDIMM::nvdimmInErrorState(l_nvdimm)) - { - // error state means arming not successful - o_arm_successful = false; - continue; - } + // Reset this for every iteration, may be redundant + l_readFlashErrorCountByte = 0; + + TRACDCOMP(g_trac_nvdimm, INFO_MRK"nvDimmCheckFlashErrorCount(): " + "Reading NVDIMM(0x%.8X) flash error count from " + "register FLASH_ERROR_COUNT(0x%.4X)", + l_nvDimmHuid, l_flashErrorRegister); + + l_err = nvdimmReadReg(i_nvDimm, + static_cast<i2cReg >(l_flashErrorRegister), + l_readFlashErrorCountByte); - l_err = nvdimmSetESPolicy(l_nvdimm); if (l_err) { - o_arm_successful = false; - nvdimmSetStatusFlag(l_nvdimm, NSTD_ERR_NOBKUP); + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvDimmCheckFlashErrorCount(): " + "FAIL: NVDIMM(0x%.8X) failed to read flash error " + "count from register FLASH_ERROR_COUNT(0x%.4X) " + "marking as a fail", + l_nvDimmHuid, l_flashErrorRegister); - // Committing the error as we don't want this to interrupt - // the boot. This will notify the user that action is needed - // on this module l_err->setSev(ERRORLOG::ERRL_SEV_PREDICTIVE); - l_err->collectTrace(NVDIMM_COMP_NAME, 1024); - errlCommit( l_err, NVDIMM_COMP_ID ); - continue; + l_err->collectTrace(NVDIMM_COMP_NAME); + errlCommit(l_err, NVDIMM_COMP_ID); + + // Set up the fail state, so caller can determine that the fail was + // due to a register read error + l_didFlashErrorCountCheckPass = false; + o_readFlashErrorCount = 0; + + break; } - l_err = NVDIMM::nvdimmChangeArmState(l_nvdimm, ARM_TRIGGER); - // If we run into any error here we will just - // commit the error log and move on. Let the - // system continue to boot and let the user - // salvage the data - if (l_err) + // If we get here, then the read was successful + // Append the read flash error count byte to the LSB of the + // aggregated flash error count bytes. + o_readFlashErrorCount = (o_readFlashErrorCount << 8) | + l_readFlashErrorCountByte; + + TRACDCOMP(g_trac_nvdimm, INFO_MRK"nvDimmCheckFlashErrorCount(): " + "NVDIMM(0x%.8X) returned value (0x%.2X) from the " + "partial flash error count, register " + "FLASH_ERROR_COUNT(0x%.4X)", + l_nvDimmHuid, + l_readFlashErrorCountByte, + l_flashErrorRegister); + + } // end for (int16_t l_flashErrorRegister = FLASH_ERROR_COUNT2; ... + + // If o_readFlashErrorCount is not zero, then register read was successful + if (o_readFlashErrorCount) + { + TRACDCOMP(g_trac_nvdimm, INFO_MRK"nvDimmCheckFlashErrorCount(): " + "NVDIMM(0x%.8X) flash error count = %d ", + l_nvDimmHuid, o_readFlashErrorCount); + + // Check the validity of the flash error count + if (o_readFlashErrorCount > i_maxFlashErrorsAllowed) { - NVDIMM::nvdimmSetStatusFlag(l_nvdimm, NVDIMM::NSTD_ERR_NOBKUP); - // Committing the error as we don't want this to interrupt - // the boot. This will notify the user that action is needed - // on this module - l_err->setSev(ERRORLOG::ERRL_SEV_PREDICTIVE); - l_err->collectTrace(NVDIMM_COMP_NAME, 1024); - errlCommit( l_err, NVDIMM_COMP_ID ); - o_arm_successful = false; - continue; + TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvDimmCheckFlashErrorCount(): " + "FAIL: For NVDIMM (0x%.8X), the flash error count (%d), " + "read from registers FLASH_ERROR_COUNT0(0x%.4X), " + "FLASH_ERROR_COUNT1(0x%.4X) and FLASH_ERROR_COUNT2(0x%.4X), " + "exceeds the maximum number of flash " + "errors allowed (%d), marking this as a fail", + l_nvDimmHuid, + o_readFlashErrorCount, + FLASH_ERROR_COUNT0, + FLASH_ERROR_COUNT1, + FLASH_ERROR_COUNT2, + i_maxFlashErrorsAllowed); + + // Set up the fail state, so caller can determine that the fail was + // due to error count exceeding the max errors allowed. + // Note: Leave the value in o_readFlashErrorCount so caller + // can inspect, if they wish + l_didFlashErrorCountCheckPass = false; } + else + { + TRACFCOMP(g_trac_nvdimm, INFO_MRK"nvDimmCheckFlashErrorCount(): " + "SUCCESS: For NVDIMM(0x%.8X), the flash error counts " + "(%d) is less than or meets the maximum number of " + "errors allowed (%d), marking this as a pass", + l_nvDimmHuid, + o_readFlashErrorCount, + i_maxFlashErrorsAllowed); - // Arm happens one module at a time. No need to set any offset on the counter - uint32_t l_poll = 0; - l_err = nvdimmPollArmDone(l_nvdimm, l_poll); - if (l_err) + // Set up the pass state + // Note: Leave the value in o_readFlashErrorCount so caller + // can inspect, if they wish + l_didFlashErrorCountCheckPass = true; + } + } // end if (o_readFlashErrorCount) + + TRACFCOMP(g_trac_nvdimm, EXIT_MRK"nvDimmCheckFlashErrorCount(): " + "Returning %s", + l_didFlashErrorCountCheckPass == true ? "true" : "false" ); + + return l_didFlashErrorCountCheckPass; +} + +/* + * @brief Check the NVM (non-volatile memory)/flash health of the individual + * NVDIMMs supplied in list. + * + * @param[in] i_nvdimmTargetList - list of NVDIMMs to check the health of flash + * + * @return false if one or more NVDIMMs fail NVM health check, else true + */ +bool nvDimmNvmCheckHealthStatus(const TargetHandleList &i_nvDimmTargetList) +{ + TRACFCOMP(g_trac_nvdimm, ENTER_MRK"nvDimmNvmCheckHealthStatus(): " + "Target list size(%d)", i_nvDimmTargetList.size()); + + // The following maximums are the same values used by SMART's + // manufacturing and recommended that we use. + // The maximum percentage of bad flash blocks + // Fail if over 19% of bad flash blocks is encountered + const uint8_t MAXIMUM_PERCENTAGE_OF_BAD_FLASH_BLOCKS_ALLOWED = 19; + // The maximum number of flash memory errors allowed + // Fail if over 300 flash memory errors is encountered + const uint32_t MAXIMUM_NUMBER_OF_FLASH_MEMORY_ERRORS_ALLOWED = 300; + + // Status of the accumulation of all calls related to the NVM health check. + // If any one call is bad/fails, then this will be false, else it stays true + bool l_didNvmHealthCheckPass(true); + + // Handle to catch any errors + errlHndl_t l_err(nullptr); + + // The retrieved flash block percentage from register + uint8_t l_badFlashBlockPercentage(0); + // The retrieved flash error count from register + uint32_t l_flashErrorCount(0); + + // The status of the checks on the percentage of bad blocks and + // flash error count + // Default to true + bool l_badFlashBlockPercentageCheckPassed(true); + bool l_flashErrorCountCheckPassed(true); + + // Iterate thru the supplied NVDIMMs checking the health of the NVM + for (auto const l_nvDimm : i_nvDimmTargetList) + { + // Cache the HUID of the NVDIMM + uint32_t l_nvDimmHuid = get_huid( l_nvDimm ); + + // Reset these for every NVDIMM that is checked + l_badFlashBlockPercentage = 0; + l_flashErrorCount = 0; + l_badFlashBlockPercentageCheckPassed = true; + l_flashErrorCountCheckPassed = true; + + // Check the validity of bad flash block percentage + if (!nvDimmCheckBadFlashBlockPercentage( + l_nvDimm, + MAXIMUM_PERCENTAGE_OF_BAD_FLASH_BLOCKS_ALLOWED, + l_badFlashBlockPercentage)) { - NVDIMM::nvdimmSetStatusFlag(l_nvdimm, NVDIMM::NSTD_ERR_NOBKUP); - // Committing the error as we don't want this to interrupt - // the boot. This will notify the user that action is needed - // on this module - l_err->setSev(ERRORLOG::ERRL_SEV_PREDICTIVE); - l_err->collectTrace(NVDIMM_COMP_NAME, 1024); - errlCommit( l_err, NVDIMM_COMP_ID ); - o_arm_successful = false; - continue; + // Set this to false to indicate that the overall check on the + // NVDIMMs had at least one failure + l_didNvmHealthCheckPass = false; + + // If no data in the variable l_badFlashBlockPercentage, then + // this is a read register fail. Move onto the next NVDIMM + // this is a dud + if (!l_badFlashBlockPercentage) + { + continue; + } + + // Set the check to false, to facilitate error reporting + l_badFlashBlockPercentageCheckPassed = false; } - l_err = nvdimmCheckArmSuccess(l_nvdimm); - if (l_err) + // Check the validity of the flash error count + if (!nvDimmCheckFlashErrorCount( + l_nvDimm, + MAXIMUM_NUMBER_OF_FLASH_MEMORY_ERRORS_ALLOWED, + l_flashErrorCount)) { - NVDIMM::nvdimmSetStatusFlag(l_nvdimm, NVDIMM::NSTD_ERR_NOBKUP); - // Committing the error as we don't want this to interrupt - // the boot. This will notify the user that action is needed - // on this module - l_err->setSev(ERRORLOG::ERRL_SEV_PREDICTIVE); - l_err->collectTrace(NVDIMM_COMP_NAME, 1024); - errlCommit( l_err, NVDIMM_COMP_ID ); - o_arm_successful = false; - continue; + // Set this to false to indicate that the overall check on the + // NVDIMMs had at least one failure + l_didNvmHealthCheckPass = false; + + // If no data in the variable l_flashErrorCount, then + // this is a read register fail. Move onto the next NVDIMM + // this is a dud + if (!l_flashErrorCount) + { + continue; + } + + // Set the check to false, to facilitate error reporting + l_flashErrorCountCheckPassed = false; } - // After arming the trigger, erase the image to prevent the possible - // stale image getting the restored on the next boot in case of failed - // save. - l_err = nvdimmEraseNF(l_nvdimm); - if (l_err) + /// Now we assess the health of the flash based on data gathered above + if ( !l_badFlashBlockPercentageCheckPassed || + !l_flashErrorCountCheckPassed ) { - NVDIMM::nvdimmSetStatusFlag(l_nvdimm, NVDIMM::NSTD_ERR_NOBKUP); - // Committing the error as we don't want this to interrupt - // the boot. This will notify the user that action is needed - // on this module - l_err->setSev(ERRORLOG::ERRL_SEV_PREDICTIVE); - l_err->collectTrace(NVDIMM_COMP_NAME, 1024); - errlCommit( l_err, NVDIMM_COMP_ID ); - o_arm_successful = false; + // First set the NVDIMM HUID to the first 32 bits of user data 1 + uint64_t l_badFlashBlockPercentageUserData1 = + TWO_UINT32_TO_UINT64(l_nvDimmHuid, 0); - // If the erase failed let's disarm the trigger - l_err = nvdimmChangeArmState(l_nvdimm, DISARM_TRIGGER); - if (l_err) + // If an issue with the bad flash block percentage, then append + // data to user data 1 + if (!l_badFlashBlockPercentageCheckPassed && + l_badFlashBlockPercentage) { - TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmArm() nvdimm[%X], error disarming the nvdimm!", - TARGETING::get_huid(l_nvdimm)); - l_err->setSev(ERRORLOG::ERRL_SEV_PREDICTIVE); - l_err->collectTrace(NVDIMM_COMP_NAME, 1024); - errlCommit(l_err, NVDIMM_COMP_ID); + // Setting the HUID here is redundant but easier than trying to + // do some clever code that will set the HUID for user data 1 + // when this path is not taken, but the next check on the flash + // error count is taken + l_badFlashBlockPercentageUserData1 = + TWO_UINT32_TO_UINT64(l_nvDimmHuid, + TWO_UINT16_TO_UINT32( + l_badFlashBlockPercentage, + MAXIMUM_PERCENTAGE_OF_BAD_FLASH_BLOCKS_ALLOWED)); } - continue; + // If an issue with the flash error count, then set user + // data 2 to contain the flash error count value + uint64_t l_flashErrorCountUserData2(0); + if (!l_flashErrorCountCheckPassed && + l_flashErrorCount) + { + l_flashErrorCountUserData2 = + TWO_UINT32_TO_UINT64(l_flashErrorCount, + MAXIMUM_NUMBER_OF_FLASH_MEMORY_ERRORS_ALLOWED); + } + + /*@ + * @errortype + * @severity ERRL_SEV_PREDICTIVE + * @moduleid NVDIMM_NVM_HEALTH_CHECK + * @reasoncode NVDIMM_NVM_HEALTH_CHECK_FAILED + * @userdata1[0:31] HUID of NVDIMM target + * @userdata1[32:47] The retrieved bad flash block percentage, + * if error with, else 0 + * @userdata1[48:63] The maximum percentage of bad flash blocks + * allowed, if bad flash block percentage + * exceeds this maximum, else 0 + * @userdata2[0:31] The retrieved flash error count, + * if error with, else 0 + * @userdata2[32:63] The maximum number of flash errors + * allowed, if flash error exceeds this + * maximum, else 0 + * @devdesc Either the NVDIMM NVM bad flash block + * percentage exceeded the maximum percentage + * allowed or the NVDIMM NVM number of flash + * error exceeds the maximum count allowed + * or both. + * @custdesc NVDIMM NVM health check failed. + */ + l_err = new ErrlEntry( ERRL_SEV_PREDICTIVE, + NVDIMM_NVM_HEALTH_CHECK, + NVDIMM_NVM_HEALTH_CHECK_FAILED, + l_badFlashBlockPercentageUserData1, + l_flashErrorCountUserData2, + ErrlEntry::NO_SW_CALLOUT ); + + l_err->collectTrace(NVDIMM_COMP_NAME); + nvdimmAddVendorLog(l_nvDimm, l_err); + + // Add a DIMM callout + l_err->addHwCallout( l_nvDimm, + HWAS::SRCI_PRIORITY_HIGH, + HWAS::NO_DECONFIG, + HWAS::GARD_NULL ); + + // Collect the error + errlCommit(l_err, NVDIMM_COMP_ID); + + // Let the caller know something went amiss + l_didNvmHealthCheckPass = false; } - } + else + { + // This NVDIMM passed the NVM health check + TRACFCOMP(g_trac_nvdimm, INFO_MRK"nvDimmNvmCheckHealthStatus(): " + "Success: NVDIMM (0x%.8X) passed the NVM health check.", + l_nvDimmHuid); + } // end if ( !l_badFlashBlockPercentageCheckPassed .. else + } // end for (auto const l_nvdimm : i_nvdimmTargetList) - TRACFCOMP(g_trac_nvdimm, EXIT_MRK"nvdimmArm() returning %d", - o_arm_successful); - return o_arm_successful; -} + // Should not have any uncommitted errors + assert(l_err == NULL, "nvDimmNvmCheckHealthStatus() - unexpected " + "uncommitted error found"); + + TRACFCOMP(g_trac_nvdimm,EXIT_MRK"nvDimmNvmCheckHealthStatus(): Returning %s", + l_didNvmHealthCheckPass == true ? "true" : "false" ); + + return l_didNvmHealthCheckPass; +} // end nvDimmNvmCheckHealthStatus /** - * @brief Check nvdimm error state + * @brief A wrapper around the call to nvDimmNvmCheckHealthStatus * - * @param[in] i_nvdimm - nvdimm target + * @see nvDimmNvmCheckHealthStatus for more details * - * @return bool - true if nvdimm is in any error state, false otherwise + * @return false if one or more NVDIMMs fail an NVM health check, else true */ -bool nvdimmInErrorState(TARGETING::Target *i_nvdimm) +bool nvDimmNvmCheckHealthStatusOnSystem() { - TRACUCOMP(g_trac_nvdimm, ENTER_MRK"nvdimmInErrorState() HUID[%X]",TARGETING::get_huid(i_nvdimm)); + TRACFCOMP(g_trac_nvdimm, ENTER_MRK"nvDimmNvmCheckHealthStatusOnSystem()"); - uint8_t l_statusFlag = i_nvdimm->getAttr<TARGETING::ATTR_NV_STATUS_FLAG>(); - bool l_ret = true; + // Get the list of NVDIMM Targets from the system + TargetHandleList l_nvDimmTargetList; + nvdimm_getNvdimmList(l_nvDimmTargetList); - if ((l_statusFlag & NSTD_ERR) == 0) - l_ret = false; + // Return status of doing a check health status + bool l_didNvmHealthCheckPass = nvDimmNvmCheckHealthStatus(l_nvDimmTargetList); - TRACUCOMP(g_trac_nvdimm, EXIT_MRK"nvdimmInErrorState() HUID[%X]",TARGETING::get_huid(i_nvdimm)); - return l_ret; + TRACFCOMP(g_trac_nvdimm, EXIT_MRK"nvDimmNvmCheckHealthStatusOnSystem(): " + "Returning %s", l_didNvmHealthCheckPass == true ? "true" : "false" ); + + return l_didNvmHealthCheckPass; +} // end nvDimmCheckHealthStatusOnSystem + + +/** + * @brief Send NV_STATUS to host + */ +void nvdimmSendNvStatus() +{ + // Send NV_STATUS for all nvdimms + TargetHandleList l_nvdimmTargetList; + nvdimm_getNvdimmList(l_nvdimmTargetList); + for (const auto & l_nvdimm : l_nvdimmTargetList) + { + errlHndl_t l_err = nullptr; + l_err = notifyNvdimmProtectionChange(l_nvdimm,SEND_NV_STATUS); + if (l_err) + { + errlCommit(l_err, NVDIMM_COMP_ID); + } + } } + +struct registerNvdimmRt +{ + registerNvdimmRt() + { + // Register function to call at end of RT init + postInitCalls_t * rt_post = getPostInitCalls(); + rt_post->callSendNvStatus = &nvdimmSendNvStatus; + } +}; + +registerNvdimmRt g_registerNvdimmRt; + } // end NVDIMM namespace diff --git a/src/usr/isteps/openpower_vddr.C b/src/usr/isteps/openpower_vddr.C index e05c1fd1d..9fdfe19e3 100644 --- a/src/usr/isteps/openpower_vddr.C +++ b/src/usr/isteps/openpower_vddr.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014,2016 */ +/* Contributors Listed Below - COPYRIGHT 2014,2019 */ /* [+] Google Inc. */ /* [+] International Business Machines Corp. */ /* */ @@ -27,7 +27,6 @@ // VDDR is enabled/disabled via a GPIO on the hammock card. // A separate GPIO selects between 1.35V and 1.25V output from the VR. -#include <config.h> #include "platform_vddr.H" diff --git a/src/usr/isteps/pm/occCheckstop.C b/src/usr/isteps/pm/occCheckstop.C index 44b7296f0..a9154e2c6 100644 --- a/src/usr/isteps/pm/occCheckstop.C +++ b/src/usr/isteps/pm/occCheckstop.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2018 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -59,6 +59,7 @@ #include <pnorif.H> #include <pnor_const.H> #include <utillidmgr.H> +#include <secureboot/smf_utils.H> #ifdef CONFIG_ENABLE_CHECKSTOP_ANALYSIS #include <diag/prdf/prdfWriteHomerFirData.H> @@ -476,6 +477,16 @@ namespace HBOCC l_errl = PRDF::writeHomerFirData( config_data->firdataConfig, sizeof(config_data->firdataConfig), i_curHw); + + if (SECUREBOOT::SMF::isSmfEnabled()) + { + config_data->smfMode = SMF_MODE_ENABLED; + } + else + { + config_data->smfMode = SMF_MODE_DISABLED; + } + if (l_errl) { TRACFCOMP( g_fapiImpTd, diff --git a/src/usr/isteps/pm/pm_common.C b/src/usr/isteps/pm/pm_common.C index 376ec0278..a4c197621 100644 --- a/src/usr/isteps/pm/pm_common.C +++ b/src/usr/isteps/pm/pm_common.C @@ -82,6 +82,7 @@ #include <p9_stop_api.H> #include <scom/scomif.H> #include <p9_quad_scom_addresses.H> +#include <secureboot/smf_utils.H> #ifdef CONFIG_ENABLE_CHECKSTOP_ANALYSIS @@ -242,6 +243,15 @@ namespace HBPM l_config_data->firMaster = 0; #endif + if (SECUREBOOT::SMF::isSmfEnabled()) + { + l_config_data->smfMode = SMF_MODE_ENABLED; + } + else + { + l_config_data->smfMode = SMF_MODE_DISABLED; + } + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, EXIT_MRK"loadHostDataToHomer: RC=0x%X, PLID=0x%lX", ERRL_GETRC_SAFE(l_errl), ERRL_GETPLID_SAFE(l_errl) ); @@ -275,9 +285,23 @@ namespace HBPM do { - bool l_isNimbus = (i_target->getAttr<ATTR_MODEL>() == MODEL_NIMBUS); - uint32_t l_lidId = (l_isNimbus) ? Util::NIMBUS_HCODE_LIDID - : Util::CUMULUS_HCODE_LIDID; + uint32_t l_lidId = 0; + auto l_model = i_target->getAttr<ATTR_MODEL>(); + switch( l_model ) + { + case(MODEL_AXONE): + // Axone just reuses the Nimbus LIDID since it is only + // used to lookup a common partition in PNOR + case(MODEL_NIMBUS): + l_lidId = Util::NIMBUS_HCODE_LIDID; + break; + case(MODEL_CUMULUS): + l_lidId = Util::CUMULUS_HCODE_LIDID; + break; + default: + assert(false,"Unsupported proc type"); + } + if(g_pHcodeLidMgr.get() == nullptr) { g_pHcodeLidMgr = std::shared_ptr<UtilLidMgr> @@ -1005,7 +1029,7 @@ namespace HBPM #if defined(__HOSTBOOT_RUNTIME) && defined(CONFIG_NVDIMM) // Notify PHYP that NVDIMMs are not protected from power off event - l_errl = NVDIMM::notifyNvdimmProtectionChange(i_target, NVDIMM::NOT_PROTECTED); + l_errl = NVDIMM::notifyNvdimmProtectionChange(i_target, NVDIMM::OCC_INACTIVE); if (l_errl) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, diff --git a/src/usr/isteps/pm/pm_common.H b/src/usr/isteps/pm/pm_common.H index 6d167dbda..c8354e5d0 100644 --- a/src/usr/isteps/pm/pm_common.H +++ b/src/usr/isteps/pm/pm_common.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -48,6 +48,10 @@ namespace HBPM NOT_FIR_MASTER = 0x00000000, IS_FIR_MASTER = 0x00000001, + // SMF Mode + SMF_MODE_DISABLED = 0x00000000, + SMF_MODE_ENABLED = 0x00000001, + // Mask off bit zero PHYSICAL_ADDR_MASK = 0x7FFFFFFFFFFFFFFF, VER_EYECATCH = 0x56455253494F4E00, //'VERSION\0' diff --git a/src/usr/isteps/pm/runtime/rt_pm.C b/src/usr/isteps/pm/runtime/rt_pm.C index 7ee9e0924..58930bc67 100644 --- a/src/usr/isteps/pm/runtime/rt_pm.C +++ b/src/usr/isteps/pm/runtime/rt_pm.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2019 */ +/* Contributors Listed Below - COPYRIGHT 2016,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -37,7 +37,6 @@ #include <runtime/interface.h> // g_hostInterfaces #include <runtime/rt_fwreq_helper.H> // firmware_request_helper -#include <runtime/rt_targeting.H> #include <runtime/runtime_reasoncodes.H> #include <initservice/isteps_trace.H> @@ -46,6 +45,7 @@ #include <targeting/common/util.H> #include <targeting/common/utilFilter.H> #include <targeting/common/targetservice.H> +#include <targeting/runtime/rt_targeting.H> #include <scom/scomif.H> #include <scom/wakeup.H> @@ -400,9 +400,9 @@ namespace RTPM } // Get the Proc Chip Id - RT_TARG::rtChipId_t l_chipId = 0; + TARGETING::rtChipId_t l_chipId = 0; - l_err = RT_TARG::getRtTarget(l_pChipTarget, l_chipId); + l_err = TARGETING::getRtTarget(l_pChipTarget, l_chipId); if(l_err) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, diff --git a/src/usr/isteps/pm/runtime/test/firmwareRequestTest.H b/src/usr/isteps/pm/runtime/test/firmwareRequestTest.H index bf1e28c06..3b6a1a7ac 100644 --- a/src/usr/isteps/pm/runtime/test/firmwareRequestTest.H +++ b/src/usr/isteps/pm/runtime/test/firmwareRequestTest.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014,2018 */ +/* Contributors Listed Below - COPYRIGHT 2014,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -23,31 +23,96 @@ /* */ /* IBM_PROLOG_END_TAG */ -#include <cxxtest/TestSuite.H> -#include <runtime/interface.h> -#include <runtime/hbrt_utilities.H> -#include <errl/hberrltypes.H> -#include <string.h> +#include <cxxtest/TestSuite.H> // CxxTest::TestSuite +#include <runtime/interface.h> // g_hostInterfaces, etc +#include <runtime/hbrt_utilities.H> // createGenericFspMsg +#include <vector> -extern trace_desc_t* g_trac_pnor; +extern trace_desc_t* g_trac_test; class FirmwareRequestTest : public CxxTest::TestSuite { public: + + /** + * @brief: testFirmwareRequestHcodeUpdate + * test the firmware_request's Send Attributes + */ + void testFirmwareRequestSendAttributes (void) + { + TRACFCOMP(g_trac_test, ENTER_MRK + "FirmwareRequestTest::testFirmwareRequestSendAttributes" ); + + if (g_hostInterfaces == NULL || + g_hostInterfaces->firmware_request == NULL) + { + TS_FAIL("FirmwareRequestTest::testFirmwareRequestSendAttributes: " + "Hypervisor firmware_request interface not linked"); + } + else + { + std::vector<TARGETING::AttributeTank::Attribute> l_attributeList; + + uint32_t l_dataSize(0); + + // Test 1: Create a default attribute and add to list + TARGETING::AttributeTank::Attribute l_attribute; + l_attributeList.push_back(l_attribute); + l_dataSize += l_attribute.getSize(); + sendAttributes(l_attributeList); + + // Test 2: Modify some of the Attributes data and add to list + l_attribute.setId(0x1001); + l_attribute.setTargetType(0x2002); + l_attribute.setPosition(0x3003); + l_attribute.setUnitPosition(0x4); + l_attribute.setNode(0x5); + l_attribute.setFlags(0x6); + l_attributeList.push_back(l_attribute); + l_dataSize += l_attribute.getSize(); + sendAttributes(l_attributeList); + + // Create a buffer to be used to update Value in the Attribute + uint32_t l_bufferSize(3); + uint8_t l_buffer[l_bufferSize]; + l_buffer[0] = 0xAA; + l_buffer[1] = 0xBB; + l_buffer[2] = 0xCC; + + // Test 3: Update the Attribute Values in the Attribute + // and add to list + l_attribute.setValue(l_buffer, 1); + l_attributeList.push_back(l_attribute); + l_dataSize += l_attribute.getSize(); + sendAttributes(l_attributeList); + + // Test 4: Update the Attribute Values in the Attribute + // and add to list + l_buffer[0] = 0xDD; + l_attribute.setValue(l_buffer, l_bufferSize); + l_attributeList.push_back(l_attribute); + l_dataSize += l_attribute.getSize(); + sendAttributes(l_attributeList); + } + + TRACFCOMP(g_trac_test, EXIT_MRK + "FirmwareRequestTest::testFirmwareRequestSendAttributes"); + } + /** * @brief: testFirmwareRequestHcodeUpdate * test the firmware_request's HCODE update call */ void testFirmwareRequestHcodeUpdate (void) { - TRACFCOMP(g_trac_pnor, ENTER_MRK + TRACFCOMP(g_trac_test, ENTER_MRK "FirmwareRequestTest::testFirmwareRequestHcodeUpdate"); if (g_hostInterfaces == NULL || g_hostInterfaces->firmware_request == NULL) { - TS_FAIL("FirmwareRequestTest::testFirmwareRequestHcodeUpdate: " - "Hypervisor firmware_request interface not linked"); + TS_FAIL("FirmwareRequestTest::testFirmwareRequestHcodeUpdate: " + "Hypervisor firmware_request interface not linked"); } else { @@ -62,14 +127,14 @@ class FirmwareRequestTest : public CxxTest::TestSuite l_req_fw_msg.req_hcode_update.i_scomAddr = 0x400; l_req_fw_msg.req_hcode_update.i_scomData = 0x500; - hostInterfaces::hbrt_fw_msg l_resp_fw_msg; - size_t l_resp_fw_msg_size = sizeof(l_resp_fw_msg); + size_t l_resp_fw_msg_size = hostInterfaces::HBRT_FW_MSG_BASE_SIZE + + sizeof(l_resp_fw_msg); size_t rc = g_hostInterfaces->firmware_request( sizeof(l_req_fw_msg), &l_req_fw_msg, &l_resp_fw_msg_size, &l_resp_fw_msg); - TRACFCOMP(g_trac_pnor, + TRACDCOMP(g_trac_test, "FirmwareRequestTest::testFirmwareRequestHcodeUpdate: " "rc:%d, type:%d, resp:%d", rc, l_resp_fw_msg.io_type, @@ -97,9 +162,8 @@ class FirmwareRequestTest : public CxxTest::TestSuite "received incorrect resp"); } } // end else - TRACFCOMP(g_trac_pnor, EXIT_MRK + TRACFCOMP(g_trac_test, EXIT_MRK "FirmwareRequestTest::testFirmwareRequestHcodeUpdate"); - } // end testFirmwareRequestHcodeUpdate /** @@ -108,7 +172,7 @@ class FirmwareRequestTest : public CxxTest::TestSuite */ void testFirmwareRequestErrLogToFsp (void) { - TRACFCOMP(g_trac_pnor, ENTER_MRK + TRACFCOMP(g_trac_test, ENTER_MRK "FirmwareRequestTest::testFirmwareRequestErrLogToFsp"); if (g_hostInterfaces == NULL || @@ -128,12 +192,13 @@ class FirmwareRequestTest : public CxxTest::TestSuite l_req_fw_msg.error_log.i_data = 0xAA; hostInterfaces::hbrt_fw_msg l_resp_fw_msg; - size_t l_resp_fw_msg_size = sizeof(l_resp_fw_msg); + size_t l_resp_fw_msg_size = hostInterfaces::HBRT_FW_MSG_BASE_SIZE + + sizeof(l_resp_fw_msg); size_t rc = g_hostInterfaces->firmware_request( sizeof(l_req_fw_msg), &l_req_fw_msg, &l_resp_fw_msg_size, &l_resp_fw_msg); - TRACFCOMP(g_trac_pnor, + TRACDCOMP(g_trac_test, "FirmwareRequestTest::testFirmwareRequestErrLogToFsp: " "rc:%d, type:%d, resp:%d", rc, l_resp_fw_msg.io_type, @@ -161,29 +226,29 @@ class FirmwareRequestTest : public CxxTest::TestSuite "received incorrect resp"); } } // end else - TRACFCOMP(g_trac_pnor, EXIT_MRK + TRACFCOMP(g_trac_test, EXIT_MRK "FirmwareRequestTest::testFirmwareRequestErrLogToFsp"); } // end testFirmwareRequestErrLogToFsp /** - * @brief: testFirmwareRequestHbrtToFsp - * test the firmware_request's HBRT to FSP call + * @brief: testFirmwareRequestSbeRetry + * test the firmware_request's SBE retry */ - void testFirmwareRequestHbrtToFsp (void) + void testFirmwareRequestSbeRetry (void) { - TRACFCOMP(g_trac_pnor, ENTER_MRK - "FirmwareRequestTest::testFirmwareRequestHbrtToFsp"); + TRACFCOMP(g_trac_test, ENTER_MRK + "FirmwareRequestTest::testFirmwareRequestSbeRetry"); if (g_hostInterfaces == NULL || g_hostInterfaces->firmware_request == NULL) { - TS_FAIL("FirmwareRequestTest::testFirmwareRequestHbrtToFsp: " + TS_FAIL("FirmwareRequestTest::testFirmwareRequestSbeRetry: " "Hypervisor firmware_request interface not linked"); } else { - // Test HBRT to FSP + // Test Request SBE Retry // Handles to the firmware messages hostInterfaces::hbrt_fw_msg *l_req_fw_msg = nullptr; @@ -204,7 +269,7 @@ class FirmwareRequestTest : public CxxTest::TestSuite // Populate the firmware_request request struct with given data l_req_fw_msg->generic_msg.msgq = 0x300; l_req_fw_msg->generic_msg.msgType = - GenericFspMboxMessage_t::MSG_DECONFIG_TARGET; + GenericFspMboxMessage_t::MSG_SBE_ERROR; // Create a useful struct to populate the generic_msg::data field // Setting the PLID and userData @@ -217,26 +282,26 @@ class FirmwareRequestTest : public CxxTest::TestSuite if (l_req_fw_msg->generic_msg.magic != GenericFspMboxMessage_t::MAGIC_NUMBER) { - TS_FAIL("FirmwareRequestTest::testFirmwareRequestHbrtToFsp: " + TS_FAIL("FirmwareRequestTest::testFirmwareRequestSbeRetry: " "magic was not properly initialized"); } if (l_req_fw_msg->generic_msg.dataSize != l_fsp_data_size) { - TS_FAIL("FirmwareRequestTest::testFirmwareRequestHbrtToFsp: " + TS_FAIL("FirmwareRequestTest::testFirmwareRequestSbeRetry: " "dataSize was not properly initialized"); } if (l_req_fw_msg->generic_msg.structVer != GenericFspMboxMessage_t::STRUCT_VERSION_LATEST) { - TS_FAIL("FirmwareRequestTest::testFirmwareRequestHbrtToFsp: " + TS_FAIL("FirmwareRequestTest::testFirmwareRequestSbeRetry: " "structVer was not properly initialized"); } if (l_req_fw_msg->generic_msg.seqnum != SeqId_t::getCurrentSeqId()) { - TS_FAIL("FirmwareRequestTest::testFirmwareRequestHbrtToFsp: " + TS_FAIL("FirmwareRequestTest::testFirmwareRequestSbeRetry: " "seqnum was not properly initialized"); } @@ -245,23 +310,27 @@ class FirmwareRequestTest : public CxxTest::TestSuite l_req_fw_msg->generic_msg.dataSize = l_fsp_data_size; l_req_fw_msg->generic_msg.structVer = 0x20; l_req_fw_msg->generic_msg.seqnum = 0x300; - l_req_fw_msg->generic_msg.msgq = 0x400; - l_req_fw_msg->generic_msg.msgType = 0x500; l_req_fw_msg->generic_msg.__req = GenericFspMboxMessage_t::REQUEST; l_req_fw_msg->generic_msg.__onlyError = GenericFspMboxMessage_t::ERROR_ONLY; - TRACFCOMP(g_trac_pnor, - "FirmwareRequestTest::testFirmwareRequestHbrtToFsp req: " - "type:%d, magic:0x%.8X, dataSize:%d, structVer:0x%.8X, " - "seqnum:%.8X, msgq:0x%.8X, msgType:0x%.8X, __req:%d, " - "__onlyError:%d, data:0x%.8X, plid:0x%.8X, huid:0x%.8X", + TRACDCOMP(g_trac_test, + "FirmwareRequestTest::testFirmwareRequestSbeRetry " + "Request data set 1/2: " + "type:%d, magic:0x%.8X, dataSize:%d, " + "structVer:0x%.8X,seqnum:%.8X, msgq:0x%.8X", l_req_fw_msg->io_type, l_req_fw_msg->generic_msg.magic, l_req_fw_msg->generic_msg.dataSize, l_req_fw_msg->generic_msg.structVer, l_req_fw_msg->generic_msg.seqnum, - l_req_fw_msg->generic_msg.msgq, + l_req_fw_msg->generic_msg.msgq); + + TRACDCOMP(g_trac_test, + "FirmwareRequestTest::testFirmwareRequestSbeRetry " + "Request data set 2/2: " + "msgType:0x%.8X, __req:%d, __onlyError:%d, " + "data:0x%.8X, plid:0x%.8X, huid:0x%.8X", l_req_fw_msg->generic_msg.msgType, l_req_fw_msg->generic_msg.__req, l_req_fw_msg->generic_msg.__onlyError, @@ -269,23 +338,29 @@ class FirmwareRequestTest : public CxxTest::TestSuite l_req_fw_msg->generic_msg.data >> 32, 0x0000FFFF & l_req_fw_msg->generic_msg.data); + size_t rc = g_hostInterfaces->firmware_request(l_req_fw_msg_size, l_req_fw_msg, &l_resp_fw_msg_size, l_resp_fw_msg); - TRACFCOMP(g_trac_pnor, - "FirmwareRequestTest::testFirmwareRequestHbrtToFsp resp: " - "type:%d, magic:0x%.8X, dataSize:%d, structVer:0x%.8X, " - "seqnum:%.8X, msgq:0x%.8X, msgType:0x%.8X, __req:%d, " - "__onlyError:%d, data:0x%.8X, plid:0x%.8X, huid:0x%.8X, " - "rc=%d", + TRACDCOMP(g_trac_test, + "FirmwareRequestTest::testFirmwareRequestSbeRetry " + "Response data set 1/2: " + "type:%d, magic:0x%.8X, dataSize:%d, " + "structVer:0x%.8X, seqnum:%.8X, msgq:0x%.8X", l_resp_fw_msg->io_type, l_resp_fw_msg->generic_msg.magic, l_resp_fw_msg->generic_msg.dataSize, l_resp_fw_msg->generic_msg.structVer, l_resp_fw_msg->generic_msg.seqnum, - l_resp_fw_msg->generic_msg.msgq, + l_resp_fw_msg->generic_msg.msgq); + + TRACDCOMP(g_trac_test, + "FirmwareRequestTest::testFirmwareRequestSbeRetry " + "Response data set 2/2: " + "msgType:0x%.8X, __req:%d, __onlyError:%d, " + "data:0x%.8X, plid:0x%.8X, huid:0x%.8X, rc=%d", l_resp_fw_msg->generic_msg.msgType, l_resp_fw_msg->generic_msg.__req, l_resp_fw_msg->generic_msg.__onlyError, @@ -294,9 +369,10 @@ class FirmwareRequestTest : public CxxTest::TestSuite 0x0000FFFF & l_resp_fw_msg->generic_msg.data, rc); + if (rc != 5) { - TS_FAIL("FirmwareRequestTest::testFirmwareRequestHbrtToFsp: " + TS_FAIL("FirmwareRequestTest::testFirmwareRequestSbeRetry: " "firmware_request - HBRT to FSP failed - " "returned wrong value"); } @@ -304,7 +380,7 @@ class FirmwareRequestTest : public CxxTest::TestSuite if (l_resp_fw_msg->io_type != hostInterfaces::HBRT_FW_MSG_HBRT_FSP_RESP) { - TS_FAIL("FirmwareRequestTest::testFirmwareRequestHbrtToFsp: " + TS_FAIL("FirmwareRequestTest::testFirmwareRequestSbeRetry: " "firmware_request - HBRT to FSP failed - " "received incorrect msg_type"); } @@ -312,56 +388,56 @@ class FirmwareRequestTest : public CxxTest::TestSuite if (l_resp_fw_msg->generic_msg.magic != GenericFspMboxMessage_t::MAGIC_NUMBER) { - TS_FAIL("FirmwareRequestTest::testFirmwareRequestHbrtToFsp: " + TS_FAIL("FirmwareRequestTest::testFirmwareRequestSbeRetry: " "firmware_request - HBRT to FSP failed - " "received incorrect magic"); } if (l_resp_fw_msg->generic_msg.dataSize != 32) { - TS_FAIL("FirmwareRequestTest::testFirmwareRequestHbrtToFsp: " + TS_FAIL("FirmwareRequestTest::testFirmwareRequestSbeRetry: " "firmware_request - HBRT to FSP failed - " "received incorrect datSize"); } if (l_resp_fw_msg->generic_msg.structVer != 0x020) { - TS_FAIL("FirmwareRequestTest::testFirmwareRequestHbrtToFsp: " + TS_FAIL("FirmwareRequestTest::testFirmwareRequestSbeRetry: " "firmware_request - HBRT to FSP failed - " "received incorrect structVer"); } if (l_resp_fw_msg->generic_msg.seqnum != 0x301) { - TS_FAIL("FirmwareRequestTest::testFirmwareRequestHbrtToFsp: " + TS_FAIL("FirmwareRequestTest::testFirmwareRequestSbeRetry: " "firmware_request - HBRT to FSP failed - " "received incorrect seqnum"); } - if (l_resp_fw_msg->generic_msg.msgq != 0x400) + if (l_resp_fw_msg->generic_msg.msgq != 0x300) { - TS_FAIL("FirmwareRequestTest::testFirmwareRequestHbrtToFsp: " + TS_FAIL("FirmwareRequestTest::testFirmwareRequestSbeRetry: " "firmware_request - HBRT to FSP failed - " "received incorrect msgq"); } - - if (l_resp_fw_msg->generic_msg.msgType != 0x500) + if (l_resp_fw_msg->generic_msg.msgType != + GenericFspMboxMessage_t::MSG_SBE_ERROR) { - TS_FAIL("FirmwareRequestTest::testFirmwareRequestHbrtToFsp: " + TS_FAIL("FirmwareRequestTest::testFirmwareRequestSbeRetry: " "firmware_request - HBRT to FSP failed - " "received incorrect msgType"); } if (l_resp_fw_msg->generic_msg.data >> 32 != 0x60) { - TS_FAIL("FirmwareRequestTest::testFirmwareRequestHbrtToFsp: " + TS_FAIL("FirmwareRequestTest::testFirmwareRequestSbeRetry: " "firmware_request - HBRT to FSP failed - " "received incorrect errPlid"); } if ((0x0000FFFF & l_resp_fw_msg->generic_msg.data) != 0x70) { - TS_FAIL("FirmwareRequestTest::testFirmwareRequestHbrtToFsp: " + TS_FAIL("FirmwareRequestTest::testFirmwareRequestSbeRetry: " "firmware_request - HBRT to FSP failed - " "received incorrect huid"); } @@ -370,8 +446,8 @@ class FirmwareRequestTest : public CxxTest::TestSuite delete[] l_resp_fw_msg; l_req_fw_msg = l_resp_fw_msg = nullptr; } - TRACFCOMP(g_trac_pnor, EXIT_MRK - "FirmwareRequestTest::testFirmwareRequestHbrtToFsp"); + TRACFCOMP(g_trac_test, EXIT_MRK + "FirmwareRequestTest::testFirmwareRequestSbeRetry"); - } // end testFirmwareRequestHbrtToFsp + } // end testFirmwareRequestSbeRetry }; // end class FirmwareRequestTest diff --git a/src/usr/isteps/pm/runtime/test/pmtestRt.H b/src/usr/isteps/pm/runtime/test/pmtestRt.H index 1c29f7ab8..235cb8cec 100644 --- a/src/usr/isteps/pm/runtime/test/pmtestRt.H +++ b/src/usr/isteps/pm/runtime/test/pmtestRt.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017,2018 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -33,7 +33,7 @@ #include <cxxtest/TestSuite.H> #include <runtime/interface.h> -#include <runtime/rt_targeting.H> +#include <targeting/runtime/rt_targeting.H> #include <targeting/common/utilFilter.H> #include <errl/errlmanager.H> #include <devicefw/userif.H> diff --git a/src/usr/isteps/tod/runtime/rt_todintf.C b/src/usr/isteps/tod/runtime/rt_todintf.C index 180049d18..e5c537cd3 100644 --- a/src/usr/isteps/tod/runtime/rt_todintf.C +++ b/src/usr/isteps/tod/runtime/rt_todintf.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014,2017 */ +/* Contributors Listed Below - COPYRIGHT 2014,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -31,7 +31,7 @@ #include <runtime/interface.h> // g_hostInterfaces #include <util/runtime/rt_fwreq_helper.H> // firmware_request_helper #include <tod_init_reasoncodes.H> // TOD_RT_TOPOLOGY_RESET_BACKUP, etc -#include <errlmanager_common.C> // errlCommit +#include <errl/errlentry.H> using namespace ERRORLOG; diff --git a/src/usr/isteps/ucd/updateUcdFlash.C b/src/usr/isteps/ucd/updateUcdFlash.C index 5a261c57f..2a8b117bf 100644 --- a/src/usr/isteps/ucd/updateUcdFlash.C +++ b/src/usr/isteps/ucd/updateUcdFlash.C @@ -23,7 +23,6 @@ /* */ /* IBM_PROLOG_END_TAG */ -#include <config.h> #include <isteps/ucd/updateUcdFlash.H> #include <ucd/ucd_reasoncodes.H> #include <devicefw/driverif.H> diff --git a/src/usr/lpc/lpcdd.C b/src/usr/lpc/lpcdd.C index c5691d7b9..48fd7a1b8 100644 --- a/src/usr/lpc/lpcdd.C +++ b/src/usr/lpc/lpcdd.C @@ -48,7 +48,6 @@ #include <kernel/bltohbdatamgr.H> #include <errl/errludlogregister.H> #include <initservice/taskargs.H> -#include <config.h> #include <arch/memorymap.H> #include <util/misc.H> #include <errl/errlreasoncodes.H> diff --git a/src/usr/makefile b/src/usr/makefile index 5f4e94cf3..4566d6941 100644 --- a/src/usr/makefile +++ b/src/usr/makefile @@ -38,6 +38,7 @@ SUBDIRS += errl.d SUBDIRS += errldisplay.d SUBDIRS += expaccess.d SUBDIRS += fapi2.d +SUBDIRS += fapiwrap.d SUBDIRS += fsi.d SUBDIRS += fsiscom.d SUBDIRS += gpio.d diff --git a/src/usr/mbox/mailboxsp.C b/src/usr/mbox/mailboxsp.C index 7ce3b9e25..a25922f56 100644 --- a/src/usr/mbox/mailboxsp.C +++ b/src/usr/mbox/mailboxsp.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2018 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] Google Inc. */ /* [+] International Business Machines Corp. */ /* */ @@ -31,7 +31,6 @@ #include "mailboxsp.H" #include "mboxdd.H" #include "ipcSp.H" -#include <config.h> #include <sys/task.h> #include <initservice/taskargs.H> #include <initservice/initserviceif.H> diff --git a/src/usr/mmio/makefile b/src/usr/mmio/makefile index cea686f85..2cc5fd76a 100644 --- a/src/usr/mmio/makefile +++ b/src/usr/mmio/makefile @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2013,2018 +# Contributors Listed Below - COPYRIGHT 2013,2019 # [+] International Business Machines Corp. # # @@ -25,12 +25,22 @@ ROOTPATH = ../../.. MODULE = mmio +SUBDIRS += test.d +SUBDIRS += runtime.d + EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/common/include/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/procedures/hwp/ffdc/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/ +EXTRAINCDIR += ${ROOTPATH}/src/import/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/utils/imageProcs/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/explorer/common/include/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/explorer/procedures/hwp/memory/ EXTRAINCDIR += ${ROOTPATH}/src/import/hwpf/fapi2/include/ EXTRAINCDIR += ${ROOTPATH}/src/include/usr/fapi2/ #include unique object modules OBJS += mmio.o +OBJS += mmio_explorer.o VPATH += .. include $(ROOTPATH)/config.mk diff --git a/src/usr/mmio/mmio.C b/src/usr/mmio/mmio.C index 1b84660f8..ff7eec661 100644 --- a/src/usr/mmio/mmio.C +++ b/src/usr/mmio/mmio.C @@ -27,6 +27,7 @@ #include <errl/errlentry.H> #include <errl/errlmanager.H> #include <errl/errludtarget.H> +#include <errl/errludlogregister.H> #include <targeting/common/predicates/predicates.H> #include <targeting/common/utilFilter.H> #include <targeting/common/targetservice.H> @@ -41,30 +42,48 @@ #include <p9a_mc_scom_addresses_fld.H> #include <error_info_defs.H> +#include "mmio_explorer.H" +#include <utils/chipids.H> + // Trace definition trace_desc_t* g_trac_mmio = NULL; TRAC_INIT(&g_trac_mmio, MMIO_COMP_NAME, 2*KILOBYTE, TRACE::BUFFER_SLOW); #define OMI_PER_MC 8 +using namespace TARGETING; + namespace MMIO { +// TODO RTC 201493 - Remove these consts once HW group has defined them. +static const uint8_t P9A_MC_DSTLFIR_SUBCHANNEL_A_FAIL_ACTION = 20; +static const uint8_t P9A_MC_DSTLFIR_SUBCHANNEL_B_FAIL_ACTION = 21; + // Helper function declarations (definitions at the bottom of this file) static -TARGETING::TargetHandle_t getParentProc(TARGETING::TargetHandle_t i_target); +TargetHandle_t getParentProc(TargetHandle_t i_ocmbTarget); static -errlHndl_t getProcScom(TARGETING::TargetHandle_t i_target, +errlHndl_t getProcScom(TargetHandle_t i_ocmbTarget, uint64_t i_scomAddr, uint64_t &o_scomData); -static -errlHndl_t setProcScom(TARGETING::TargetHandle_t i_target, + +// NOTE: removed static qualifier to prevent compiler from complaining about +// the function not being used. +errlHndl_t setProcScom(TargetHandle_t i_ocmbTarget, uint64_t i_scomAddr, uint64_t i_scomData); static void *mmio_memcpy(void *vdest, const void *vsrc, size_t len); +/******************************************************************************* + * + * @brief Setup the MMIO BAR registers for all OCMB chips in the system + * + * @return nullptr on success, failure otherwise. + * + */ errlHndl_t mmioSetup() { errlHndl_t l_err = nullptr; @@ -77,39 +96,50 @@ errlHndl_t mmioSetup() // // loop through all the Memory Channels (MC Targets) // call allocate of 32 GB virtual memory space with mmio_dev_map() for each MC - TARGETING::TargetHandleList l_mcTargetList; - getAllChiplets(l_mcTargetList, TARGETING::TYPE_MC); + TargetHandleList l_mcTargetList; + getAllChiplets(l_mcTargetList, TYPE_MC); for (auto & l_mcTarget: l_mcTargetList) { uint32_t l_mcChipUnit = - l_mcTarget->getAttr<TARGETING::ATTR_CHIP_UNIT>(); + l_mcTarget->getAttr<ATTR_CHIP_UNIT>(); - // Get the base BAR address for OpenCapi Memory Interfaces (OMIs) of the this Memory Channel (MC) + // Get the base BAR address for OpenCapi Memory Interfaces (OMIs) of this Memory Controller (MC) auto l_omiBaseAddr = - l_mcTarget->getAttr<TARGETING::ATTR_OMI_INBAND_BAR_BASE_ADDR_OFFSET>(); - - // Apply the MMIO base offset so we get the real address - uint64_t l_realAddr = ( l_omiBaseAddr | MMIO_BASE ); - - // Map the device with a kernal call, each device, the MC, is 32 GB + l_mcTarget->getAttr<ATTR_OMI_INBAND_BAR_BASE_ADDR_OFFSET>(); + + // Build up the full address with group/chip address considerations + auto l_procType = TARGETING::TYPE_PROC; + TARGETING::Target* l_parentChip = getParent(l_mcTarget, l_procType); + uint8_t l_groupId = + l_parentChip->getAttr<ATTR_PROC_EFF_FABRIC_GROUP_ID>(); + uint8_t l_chipId = + l_parentChip->getAttr<ATTR_PROC_EFF_FABRIC_CHIP_ID>(); + uint64_t l_realAddr = computeMemoryMapOffset( MMIO_BASE, + l_groupId, + l_chipId ); + + // Apply the MMIO base offset so we get the final address + l_realAddr += l_omiBaseAddr; + + // Map the device with a kernel call, each device, the MC, is 32 GB uint64_t l_virtAddr = reinterpret_cast<uint64_t> (mmio_dev_map(reinterpret_cast<void *>(l_realAddr), THIRTYTWO_GB)); - TRACFCOMP ( g_trac_mmio, "MC%.02x (0x%.08X) MMIO BAR PHYSICAL ADDR = 0x%lx VIRTUAL ADDR = 0x%lx" , - l_mcChipUnit ? 0x23 : 0x01, TARGETING::get_huid(l_mcTarget), + TRACFCOMP ( g_trac_mmio, "MC%.02X (0x%.08X) MMIO BAR PHYSICAL ADDR = 0x%lX VIRTUAL ADDR = 0x%lX" , + l_mcChipUnit ? 0x23 : 0x01, get_huid(l_mcTarget), l_realAddr, l_virtAddr); // set VM_ADDR on each OCMB - TARGETING::TargetHandleList l_omiTargetList; - getChildChiplets(l_omiTargetList, l_mcTarget, TARGETING::TYPE_OMI); + TargetHandleList l_omiTargetList; + getChildChiplets(l_omiTargetList, l_mcTarget, TYPE_OMI); for (auto & l_omiTarget: l_omiTargetList) { // ATTR_CHIP_UNIT is relative to other OMI under this PROC uint32_t l_omiChipUnit = - l_omiTarget->getAttr<TARGETING::ATTR_CHIP_UNIT>(); + l_omiTarget->getAttr<ATTR_CHIP_UNIT>(); // Get the OMI position relative to other OMIs under its parent MC chiplet uint32_t l_omiPosRelativeToMc = l_omiChipUnit % OMI_PER_MC; @@ -123,10 +153,10 @@ errlHndl_t mmioSetup() // paired OCMB spaces get interleaved as follows : // ocmb | BAR ATTRIBUTE | Type | Base reg - end addr | size | sub-ch // +-----+--------------------+------+-----------------------------------------+------+------- - // ocmb0 | 0x0006030200000000 | cnfg | 0x0006030200000000 - 0x000603027FFFFFFF | 2GB | 0 - // ocmb1 | 0x0006030280000000 | cnfg | 0x0006030280000000 - 0x00060302FFFFFFFF | 2GB | 1 - // ocmb0 | N/A | mmio | 0x0006030300000000 - 0x000603037FFFFFFF | 2GB | 0 - // ocmb1 | N/A | mmio | 0x0006030380000000 - 0x00060303FFFFFFFF | 2GB | 1 + // ocmb0 | 0xYYYYYYY000000000 | cnfg | 0xYYYYYYY000000000 - 0xYYYYYYY07FFFFFFF | 2GB | 0 + // ocmb1 | 0xYYYYYYY080000000 | cnfg | 0xYYYYYYY080000000 - 0xYYYYYYY0FFFFFFFF | 2GB | 1 + // ocmb0 | N/A | mmio | 0xYYYYYYY100000000 - 0xYYYYYYY17FFFFFFF | 2GB | 0 + // ocmb1 | N/A | mmio | 0xYYYYYYY180000000 - 0xYYYYYYY1FFFFFFFF | 2GB | 1 // +-----+--------------------+------+-----------------------------------------+------+------- // Calculate CNFG space BAR to write to OCMB attribute @@ -136,14 +166,16 @@ errlHndl_t mmioSetup() // Calculated real address for this OMI is (BAR from MC attribute) + (currentOmiOffset) uint64_t l_calulatedRealAddr = l_omiBaseAddr + l_currentOmiOffset; - // Grab bar value from attribute to verify it matches our calculations - auto l_omiBarAttrVal = l_omiTarget->getAttr<TARGETING::ATTR_OMI_INBAND_BAR_BASE_ADDR_OFFSET>(); + // Grab bar value from attribute to verify it matches + // our calculations + auto l_omiBarAttrVal = l_omiTarget-> + getAttr<ATTR_OMI_INBAND_BAR_BASE_ADDR_OFFSET>(); if(l_omiBarAttrVal != l_calulatedRealAddr) { TRACFCOMP(g_trac_mmio, "Discrepancy found between calculated OMI MMIO bar offset and what we found in ATTR_OMI_INBAND_BAR_BASE_ADDR_OFFSET"); - TRACFCOMP(g_trac_mmio, "Calculated Offset: 0x%lx, Attribute Value : 0x%lx", l_calulatedRealAddr, l_omiBarAttrVal); + TRACFCOMP(g_trac_mmio, "Calculated Offset: 0x%lX, Attribute Value : 0x%lX", l_calulatedRealAddr, l_omiBarAttrVal); /*@ * @errortype ERRORLOG::ERRL_SEV_UNRECOVERABLE @@ -151,7 +183,7 @@ errlHndl_t mmioSetup() * @reasoncode MMIO::RC_BAR_OFFSET_MISMATCH * @userdata1 Calculated Bar Offset * @userdata2 Bar offset from attribute - * @devdesc mmioSetup> Mismatch between calculated map value + * @devdesc Mismatch between calculated map value * and what is in attribute xml * @custdesc Unexpected memory subsystem firmware error. */ @@ -172,16 +204,21 @@ errlHndl_t mmioSetup() uint64_t l_currentOmiVirtAddr = l_virtAddr + l_currentOmiOffset; // set VM_ADDR the associated OCMB - TARGETING::TargetHandleList l_ocmbTargetList; + TargetHandleList l_ocmbTargetList; getChildAffinityTargets(l_ocmbTargetList, l_omiTarget, - TARGETING::CLASS_CHIP, TARGETING::TYPE_OCMB_CHIP); + CLASS_CHIP, TYPE_OCMB_CHIP); assert(l_ocmbTargetList.size() == 1 , "OCMB chips list found for a given OMI != 1 as expected"); - TRACFCOMP(g_trac_mmio, "Setting HUID 0x%.08X MMIO vm addr to be 0x%lx , real address is 0x%lx", TARGETING::get_huid(l_ocmbTargetList[0]), - l_currentOmiVirtAddr, l_calulatedRealAddr | MMIO_BASE ); + TRACFCOMP(g_trac_mmio, + "Setting HUID 0x%.08X MMIO vm addr to be 0x%lX, real" + " address is 0x%lX", + get_huid(l_ocmbTargetList[0]), + l_currentOmiVirtAddr, + l_calulatedRealAddr | MMIO_BASE ); - l_ocmbTargetList[0]->setAttr<TARGETING::ATTR_MMIO_VM_ADDR>(l_currentOmiVirtAddr); + l_ocmbTargetList[0]-> + setAttr<ATTR_MMIO_VM_ADDR>(l_currentOmiVirtAddr); } } } while(0); @@ -194,42 +231,372 @@ errlHndl_t mmioSetup() // Direct OCMB reads and writes to the device's memory mapped memory. DEVICE_REGISTER_ROUTE(DeviceFW::WILDCARD, DeviceFW::MMIO, - TARGETING::TYPE_OCMB_CHIP, + TYPE_OCMB_CHIP, ocmbMmioPerformOp); -errlHndl_t ocmbMmioPerformOp(DeviceFW::OperationType i_opType, - TARGETING::TargetHandle_t i_target, - void* io_buffer, - size_t& io_buflen, - int64_t i_accessType, - va_list i_args) +/******************************************************************************* + * + * @brief Switch to using I2C instead of MMIO SCOMs for an OCMB + * + * @param[in] i_ocmbTarget Which OCMB to switch to using I2C + * + */ +void disableInbandScomsOcmb(const TargetHandle_t i_ocmbTarget) { - errlHndl_t l_err = nullptr; - uint64_t l_offset = va_arg(i_args, uint64_t); - uint64_t l_accessLimit = va_arg(i_args, uint64_t); + mutex_t* l_mutex = NULL; - TRACDCOMP(g_trac_mmio, ENTER_MRK"ocmbMmioPerformOp"); - TRACDCOMP(g_trac_mmio, INFO_MRK"op=%d, target=0x%.8X", - i_opType, TARGETING::get_huid(i_target)); - TRACDCOMP(g_trac_mmio, INFO_MRK"buffer=%p, length=%d, accessType=%ld", - io_buffer, io_buflen, i_accessType); - TRACDCOMP(g_trac_mmio, INFO_MRK"offset=0x%lX, accessLimit=%ld", - l_offset, l_accessLimit); + TRACFCOMP(g_trac_mmio, + "disableInbandScomsOcmb: switching to use I2C on OCMB 0x%08x", + get_huid(i_ocmbTarget)); - do + //don't mess with attributes without the mutex (just to be safe) + l_mutex = i_ocmbTarget->getHbMutexAttr<ATTR_IBSCOM_MUTEX>(); + mutex_lock(l_mutex); + + ScomSwitches l_switches = i_ocmbTarget->getAttr<ATTR_SCOM_SWITCHES>(); + l_switches.useInbandScom = 0; + l_switches.useI2cScom = 1; + + // Modify attribute + i_ocmbTarget->setAttr<ATTR_SCOM_SWITCHES>(l_switches); + mutex_unlock(l_mutex); +} + +/******************************************************************************* + * + * @brief Determine if we are on sub-channel A (OMI-0) or not. + * + * @param[in] Which OCMB target to query + * + * @return True if the OCMB target is on sub-channel A (OMI-0). False + * Otherwise. + * + */ +bool isSubChannelA(const TargetHandle_t i_ocmbTarget) +{ + const auto l_parentOMI = getImmediateParentByAffinity(i_ocmbTarget); + return (l_parentOMI->getAttr<ATTR_REL_POS>() == 0); +} + +/******************************************************************************* + * + * @brief Adds default callouts to error log for when further isolation + * cannot be performed. + * + * @param[in] Error log to add callouts to. + * @param[in] OCMB target to callout + * + */ +void addDefaultCallouts(errlHndl_t i_err, + const TargetHandle_t i_ocmbTarget) +{ + // Add OCMB as high priority + i_err->addHwCallout(i_ocmbTarget, + HWAS::SRCI_PRIORITY_HIGH, + HWAS::DECONFIG, + HWAS::GARD_NULL); + + // Add OMI bus + i_err->addHwCallout(getImmediateParentByAffinity(i_ocmbTarget), + HWAS::SRCI_PRIORITY_MED, + HWAS::DECONFIG, + HWAS::GARD_NULL); + + // Add code as low priority callout + i_err->addProcedureCallout(HWAS::EPUB_PRC_HB_CODE, + HWAS::SRCI_PRIORITY_LOW); +} + +/******************************************************************************* + * + * @brief Determine if the OCMB detected a failure on a specific MMIO + * transaction to the specified OCMB target. + * + * @param[in] i_ocmbTarget Handle for the target OCMB chip. + * @param[in] i_va Virtual address of the transaction to check + * @param[in] i_accessLimit The byte range of the transaction + * @param[in] i_offset The offset from the base address of the OCMB chip + * @param[in] i_opType The operation type (read or write) + * @param[out] o_errorAddressMatches Set to true if the OCMB chip detected a + * failure on our transaction. + * @param[out] o_errorAddressIsZero Set to true if no error has been detected + * yet. + * @return nullptr on succesful read of OCMB error status, non-null otherwise. + * + */ +errlHndl_t checkOcmbError(const TargetHandle_t i_ocmbTarget, + const uint64_t i_va, + const uint64_t i_accessLimit, + const uint64_t i_offset, + DeviceFW::OperationType i_opType, + bool& o_errorAddressMatches, + bool& o_errorAddressIsZero) +{ + errlHndl_t l_err = nullptr; + const auto l_ocmbChipId = i_ocmbTarget->getAttr<TARGETING::ATTR_CHIP_ID>(); + switch(l_ocmbChipId) { - uint64_t l_addr = i_target->getAttr<TARGETING::ATTR_MMIO_VM_ADDR>(); + case POWER_CHIPID::EXPLORER_16: + case POWER_CHIPID::GEMINI_16: + l_err = MMIOEXP::checkExpError(i_ocmbTarget, + i_va, + i_accessLimit, + i_offset, + i_opType, + o_errorAddressMatches, + o_errorAddressIsZero); + break; - TRACDCOMP(g_trac_mmio, INFO_MRK"MMIO Op l_addr=0x%lX ", l_addr); + default: + // Should never get here, but just in case... + TRACFCOMP(g_trac_mmio, ERR_MRK + "checkOcmbError: Unsupported chip ID[0x%08x] on OCMB[0x%08x]", + l_ocmbChipId, get_huid(i_ocmbTarget)); + /*@ + * @errortype + * @moduleid MMIO::MOD_CHECK_OCMB_ERROR + * @reasoncode MMIO::RC_UNSUPPORTED_CHIPID + * @userdata1 OCMB HUID + * @userdata2 OCMB chip ID + * @devdesc A MMIO operation was attempted + * on an unsupported OCMB chip. + * @custdesc Unexpected memory subsystem firmware error. + */ + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + MMIO::MOD_CHECK_OCMB_ERROR, + MMIO::RC_UNSUPPORTED_CHIPID, + get_huid(i_ocmbTarget), + l_ocmbChipId, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + break; + } + return l_err; +} + +/******************************************************************************* + * + * @brief Collect additional failure data from the target OCMB chip and add + * appropriate FRU/Procedure callouts. + * + * @note Must call checkOcmbError to determine that a transaction failed before + * calling this function. + * + * @param[in] i_ocmbTarget Handle of OCMB to collect extra FFDC from + * @param[in] i_offset The offset of the transaction address + * on the OCMB chip. + * @param[in] i_opType The operation type (read or write) + * @param[in] i_err The error log for adding callouts/FFDC + * + */ +void determineCallouts(const TargetHandle_t i_ocmbTarget, + const uint64_t i_offset, + DeviceFW::OperationType i_opType, + errlHndl_t i_err) +{ + bool l_fwFailure = false; + errlHndl_t l_err = nullptr; + + const auto l_ocmbChipId = i_ocmbTarget->getAttr<TARGETING::ATTR_CHIP_ID>(); + switch(l_ocmbChipId) + { + case POWER_CHIPID::EXPLORER_16: + case POWER_CHIPID::GEMINI_16: + l_err = MMIOEXP::determineExpCallouts(i_ocmbTarget, + i_offset, + i_opType, + i_err, + l_fwFailure); + break; + default: + // Should never get here, but just in case... + TRACFCOMP(g_trac_mmio, ERR_MRK + "determineCallouts: Unsupported chip ID[0x%08x] on OCMB[0x%08x]", + l_ocmbChipId, get_huid(i_ocmbTarget)); + /*@ + * @errortype + * @moduleid MMIO::MOD_DETERMINE_CALLOUTS + * @reasoncode MMIO::RC_UNSUPPORTED_CHIPID + * @userdata1 OCMB HUID + * @userdata2 OCMB chip ID + * @devdesc A MMIO operation was attempted + * on an unsupported OCMB chip. + * @custdesc Unexpected memory subsystem firmware error. + */ + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + MMIO::MOD_DETERMINE_CALLOUTS, + MMIO::RC_UNSUPPORTED_CHIPID, + get_huid(i_ocmbTarget), + l_ocmbChipId, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + break; + } + if(l_err) + { + TRACFCOMP(g_trac_mmio, + "determineCallouts: Couldn't isolate failure on" + " OCMB[0x%08x]", + get_huid(i_ocmbTarget)); + + // This error is secondary to the actual error. Log as informational + // and add default callouts + l_err->setSev(ERRORLOG::ERRL_SEV_INFORMATIONAL); + l_err->plid(i_err->plid()); + ERRORLOG::errlCommit(l_err, MMIO_COMP_ID); + addDefaultCallouts(i_err, i_ocmbTarget); + } + else + { + if(l_fwFailure) + { + TRACFCOMP(g_trac_mmio, + "determineCallouts: firmware error detected on" + " OCMB[0x%08x]", + get_huid(i_ocmbTarget)); + + // Add HB code as high priority callout + i_err->addProcedureCallout(HWAS::EPUB_PRC_HB_CODE, + HWAS::SRCI_PRIORITY_HIGH); + } + else + { + TRACFCOMP(g_trac_mmio, + "determineCallouts: hardware error detected on" + " OCMB[0x%08x]", + get_huid(i_ocmbTarget)); + + // Add OCMB as high priority callout + i_err->addHwCallout(i_ocmbTarget, + HWAS::SRCI_PRIORITY_HIGH, + HWAS::DECONFIG, + HWAS::GARD_NULL); + } + } +} - if (l_addr == 0) +/******************************************************************************* + * + * @brief Checks for a channel failure + * + * @param[in] i_ocmbTarget The OCMB to check for a channel failure + * @param[out] o_checkstopExists true if channel failed, false otherwise. + * + * @return nullptr if we were able to read the status. Non-nullptr if there + * was a SCOM failure in reading status. + */ +errlHndl_t checkChannelCheckstop(const TargetHandle_t i_ocmbTarget, + bool& o_checkstopExists) +{ + bool l_checkstopExists = false; + uint64_t l_scom_data = 0; + uint64_t l_scom_mask = 0; + + auto l_err = getProcScom(i_ocmbTarget, + P9A_MCC_DSTLFIR, + l_scom_data); + if (l_err) + { + TRACFCOMP(g_trac_mmio, ERR_MRK + "checkChannelCheckstop: getscom(P9A_MCC_DSTLFIR) failed" + " on OCMB[0x%08x]", get_huid(i_ocmbTarget)); + } + else + { + // Check for channel checkstop on our sub-channel + l_scom_mask = (isSubChannelA(i_ocmbTarget))? + (1ull << P9A_MC_DSTLFIR_SUBCHANNEL_A_FAIL_ACTION): + (1ull << P9A_MC_DSTLFIR_SUBCHANNEL_B_FAIL_ACTION); + if (l_scom_data & l_scom_mask) { + // A channel checkstop has occurred. (our bus is down) TRACFCOMP(g_trac_mmio, ERR_MRK - "ocmbMmioPerformOp: MMIO has not been initialized!"); + "checkChannelCheckstop: there was a channel checkstop on" + " OCMB[0x%08x], P9A_MCC_DSTLFIR=0x%llX", + get_huid(i_ocmbTarget), l_scom_data); + l_checkstopExists = true; + } + } + o_checkstopExists = l_checkstopExists; + return l_err; +} + +/******************************************************************************* + * + * @brief Validates input parameters and state for an OCMB MMIO operation + * + * @param[in] i_opType Operation type, see DeviceFW::OperationType + * in driverif.H + * @param[in] i_ocmbTarget inband scom target + * @param[in] i_buffer pointer to read/write buffer + * @param[in] i_buflen size of i_buffer (in bytes) + * @param[in] i_addr The base virtual address of the the OCMB MMIO space + * @param[in] i_offset The offset of the config reg, scom reg, MSCC reg or + * SRAM to be accessed. + * @param[in/out] io_accessLimit The number of bytes to read/write per MMIO + * transaction. Will be set to i_buflen if + * io_accessLimit is zero. + * + * @return nullptr on success, failure otherwise. + */ +errlHndl_t validateOcmbMmioOp(DeviceFW::OperationType i_opType, + const TargetHandle_t i_ocmbTarget, + void* i_buffer, + size_t i_buflen, + const uint64_t i_addr, + const uint64_t i_offset, + uint64_t& io_accessLimit) +{ + errlHndl_t l_err = nullptr; + + do + { + // Check that this is a supported OCMB chip + const auto l_ocmbChipId = + i_ocmbTarget->getAttr<TARGETING::ATTR_CHIP_ID>(); + switch(l_ocmbChipId) + { + case POWER_CHIPID::EXPLORER_16: + case POWER_CHIPID::GEMINI_16: + break; + default: + TRACFCOMP(g_trac_mmio, ERR_MRK + "validateOcmbMmioOp: Unsupported chip ID[0x%08x] " + "on OCMB[0x%08x]", + l_ocmbChipId, get_huid(i_ocmbTarget)); /*@ * @errortype - * @moduleid MMIO::MOD_MMIO_PERFORM_OP + * @moduleid MMIO::MOD_VALIDATE_OCMB_MMIO_OP + * @reasoncode MMIO::RC_UNSUPPORTED_CHIPID + * @userdata1 OCMB HUID + * @userdata2 OCMB chip ID + * @devdesc A MMIO operation was attempted + * on an unsupported OCMB chip. + * @custdesc Unexpected memory subsystem firmware error. + */ + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + MMIO::MOD_VALIDATE_OCMB_MMIO_OP, + MMIO::RC_UNSUPPORTED_CHIPID, + get_huid(i_ocmbTarget), + l_ocmbChipId, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + break; + } + if(l_err) + { + break; + } + + if (i_addr == 0) + { + TRACFCOMP(g_trac_mmio, ERR_MRK + "validateOcmbMmioOp: MMIO has not been initialized!"); + + /*@ + * @errortype + * @moduleid MMIO::MOD_VALIDATE_OCMB_MMIO_OP * @reasoncode MMIO::RC_INVALID_SETUP * @userdata1[0:31] Target huid * @userdata1[32:63] Data Offset, if >= 4GB then subtract 2GB @@ -237,35 +604,35 @@ errlHndl_t ocmbMmioPerformOp(DeviceFW::OperationType i_opType, * @userdata2[0:0] Operation Type * @userdata2[28:31] Access Limit * @userdata2[32:63] Buffer Length - * @devdesc mmioPerformOp> A MMIO operation was attempted + * @devdesc A MMIO operation was attempted * before MMIO was initialized. * @custdesc Unexpected memory subsystem firmware error. */ l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_UNRECOVERABLE, - MMIO::MOD_MMIO_PERFORM_OP, + MMIO::MOD_VALIDATE_OCMB_MMIO_OP, MMIO::RC_INVALID_SETUP, TWO_UINT32_TO_UINT64( - i_target->getAttr<TARGETING::ATTR_HUID>(), - (l_offset < (4 * GIGABYTE)) ? - (l_offset) : - (l_offset - (2 * GIGABYTE))), + get_huid(i_ocmbTarget), + (i_offset < (4 * GIGABYTE)) ? + (i_offset) : + (i_offset - (2 * GIGABYTE))), TWO_UINT32_TO_UINT64( - (i_opType << 31) | l_accessLimit, - io_buflen), + (i_opType << 31) | io_accessLimit, + i_buflen), ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); break; } - if (io_buffer == nullptr) + if (i_buffer == nullptr) { TRACFCOMP(g_trac_mmio, ERR_MRK - "ocmbMmioPerformOp: buffer is invalid!"); + "validateOcmbMmioOp: buffer is invalid!"); /*@ * @errortype - * @moduleid MMIO::MOD_MMIO_PERFORM_OP + * @moduleid MMIO::MOD_VALIDATE_OCMB_MMIO_OP * @reasoncode MMIO::RC_INVALID_BUFFER * @userdata1[0:31] Target huid * @userdata1[32:63] Data Offset, if >= 4GB then subtract 2GB @@ -273,41 +640,41 @@ errlHndl_t ocmbMmioPerformOp(DeviceFW::OperationType i_opType, * @userdata2[0:0] Operation Type * @userdata2[28:31] Access Limit * @userdata2[32:63] Buffer Length - * @devdesc mmioPerformOp> Invalid data buffer for a MMIO + * @devdesc Invalid data buffer for a MMIO * operation. * @custdesc Unexpected memory subsystem firmware error. */ l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_UNRECOVERABLE, - MMIO::MOD_MMIO_PERFORM_OP, + MMIO::MOD_VALIDATE_OCMB_MMIO_OP, MMIO::RC_INVALID_BUFFER, TWO_UINT32_TO_UINT64( - i_target->getAttr<TARGETING::ATTR_HUID>(), - (l_offset < (4 * GIGABYTE)) ? - (l_offset) : - (l_offset - (2 * GIGABYTE))), + get_huid(i_ocmbTarget), + (i_offset < (4 * GIGABYTE)) ? + (i_offset) : + (i_offset - (2 * GIGABYTE))), TWO_UINT32_TO_UINT64( - (i_opType << 31) | l_accessLimit, - io_buflen), + (i_opType << 31) | io_accessLimit, + i_buflen), ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); break; } - switch (l_accessLimit) { + switch (io_accessLimit) { case 0: - l_accessLimit = io_buflen; // no access size restriction + io_accessLimit = i_buflen; // no access size restriction case 4: case 8: break; // expected values default: TRACFCOMP(g_trac_mmio, ERR_MRK - "ocmbMmioPerformOp: accessLimit(%ld) should be 0, 4 or 8!!!", - l_accessLimit); + "validateOcmbMmioOp: accessLimit(%ld) should be 0, 4 or 8!!!", + io_accessLimit); /*@ * @errortype - * @moduleid MMIO::MOD_MMIO_PERFORM_OP + * @moduleid MMIO::MOD_VALIDATE_OCMB_MMIO_OP * @reasoncode MMIO::RC_INVALID_ACCESS_LIMIT * @userdata1[0:31] Target huid * @userdata1[32:63] Data Offset, if >= 4GB then subtract 2GB @@ -315,22 +682,22 @@ errlHndl_t ocmbMmioPerformOp(DeviceFW::OperationType i_opType, * @userdata2[0:0] Operation Type * @userdata2[28:31] Access Limit * @userdata2[32:63] Buffer Length - * @devdesc mmioPerformOp> Specified access limit was + * @devdesc Specified access limit was * invalid for a MMIO operation. * @custdesc Unexpected memory subsystem firmware error. */ l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_UNRECOVERABLE, - MMIO::MOD_MMIO_PERFORM_OP, + MMIO::MOD_VALIDATE_OCMB_MMIO_OP, MMIO::RC_INVALID_ACCESS_LIMIT, TWO_UINT32_TO_UINT64( - i_target->getAttr<TARGETING::ATTR_HUID>(), - (l_offset < (4 * GIGABYTE)) ? - (l_offset) : - (l_offset - (2 * GIGABYTE))), + get_huid(i_ocmbTarget), + (i_offset < (4 * GIGABYTE)) ? + (i_offset) : + (i_offset - (2 * GIGABYTE))), TWO_UINT32_TO_UINT64( - (i_opType << 31) | l_accessLimit, - io_buflen), + (i_opType << 31) | io_accessLimit, + i_buflen), ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); break; } @@ -340,16 +707,16 @@ errlHndl_t ocmbMmioPerformOp(DeviceFW::OperationType i_opType, break; } - if (io_buflen < l_accessLimit) + if (i_buflen < io_accessLimit) { TRACFCOMP(g_trac_mmio, ERR_MRK - "ocmbMmioPerformOp: buffer is too small for the" + "validateOcmbMmioOp: buffer is too small for the" " request, buflen=%d, accessLimit=%ld", - io_buflen, l_accessLimit); + i_buflen, io_accessLimit); /*@ * @errortype - * @moduleid MMIO::MOD_MMIO_PERFORM_OP + * @moduleid MMIO::MOD_VALIDATE_OCMB_MMIO_OP * @reasoncode MMIO::RC_INSUFFICIENT_BUFFER * @userdata1[0:31] Target huid * @userdata1[32:63] Data Offset, if >= 4GB then subtract 2GB @@ -357,38 +724,38 @@ errlHndl_t ocmbMmioPerformOp(DeviceFW::OperationType i_opType, * @userdata2[0:0] Operation Type * @userdata2[28:31] Access Limit * @userdata2[32:63] Buffer Length - * @devdesc mmioPerformOp> Data buffer too small for a + * @devdesc Data buffer too small for a * MMIO operation. * @custdesc Unexpected memory subsystem firmware error. */ l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_UNRECOVERABLE, - MMIO::MOD_MMIO_PERFORM_OP, + MMIO::MOD_VALIDATE_OCMB_MMIO_OP, MMIO::RC_INSUFFICIENT_BUFFER, TWO_UINT32_TO_UINT64( - i_target->getAttr<TARGETING::ATTR_HUID>(), - (l_offset < (4 * GIGABYTE)) ? - (l_offset) : - (l_offset - (2 * GIGABYTE))), + get_huid(i_ocmbTarget), + (i_offset < (4 * GIGABYTE)) ? + (i_offset) : + (i_offset - (2 * GIGABYTE))), TWO_UINT32_TO_UINT64( - (i_opType << 31) | l_accessLimit, - io_buflen), + (i_opType << 31) | io_accessLimit, + i_buflen), ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); break; } - if (io_buflen % l_accessLimit) + if (i_buflen % io_accessLimit) { TRACFCOMP(g_trac_mmio, ERR_MRK - "ocmbMmioPerformOp: buffer length must be a" + "validateOcmbMmioOp: buffer length must be a" " multiple of the access limit," " buflen=%d, accessLimit=%ld", - io_buflen, l_accessLimit); + i_buflen, io_accessLimit); /*@ * @errortype - * @moduleid MMIO::MOD_MMIO_PERFORM_OP + * @moduleid MMIO::MOD_VALIDATE_OCMB_MMIO_OP * @reasoncode MMIO::RC_INCORRECT_BUFFER_LENGTH * @userdata1[0:31] Target huid * @userdata1[32:63] Data Offset, if >= 4GB then subtract 2GB @@ -396,38 +763,37 @@ errlHndl_t ocmbMmioPerformOp(DeviceFW::OperationType i_opType, * @userdata2[0:0] Operation Type * @userdata2[28:31] Access Limit * @userdata2[32:63] Buffer Length - * @devdesc mmioPerformOp> Buffer length not a multiple - * of access limit. + * @devdesc Buffer length not a multiple of access limit. * @custdesc Unexpected memory subsystem firmware error. */ l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_UNRECOVERABLE, - MMIO::MOD_MMIO_PERFORM_OP, + MMIO::MOD_VALIDATE_OCMB_MMIO_OP, MMIO::RC_INCORRECT_BUFFER_LENGTH, TWO_UINT32_TO_UINT64( - i_target->getAttr<TARGETING::ATTR_HUID>(), - (l_offset < (4 * GIGABYTE)) ? - (l_offset) : - (l_offset - (2 * GIGABYTE))), + get_huid(i_ocmbTarget), + (i_offset < (4 * GIGABYTE)) ? + (i_offset) : + (i_offset - (2 * GIGABYTE))), TWO_UINT32_TO_UINT64( - (i_opType << 31) | l_accessLimit, - io_buflen), + (i_opType << 31) | io_accessLimit, + i_buflen), ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); break; } - if (!(((l_offset >= 0) && (l_offset < (2 * GIGABYTE))) || - ((l_offset >= (4 * GIGABYTE)) && (l_offset < (6 * GIGABYTE))))) + if (!(((i_offset >= 0) && (i_offset < (2 * GIGABYTE))) || + ((i_offset >= (4 * GIGABYTE)) && (i_offset < (6 * GIGABYTE))))) { TRACFCOMP(g_trac_mmio, ERR_MRK - "ocmbMmioPerformOp: offset(0x%lX) must be" + "validateOcmbMmioOp: offset(0x%lX) must be" " either 0-2G or 4G-6G!", - l_offset); + i_offset); /*@ * @errortype - * @moduleid MMIO::MOD_MMIO_PERFORM_OP + * @moduleid MMIO::MOD_VALIDATE_OCMB_MMIO_OP * @reasoncode MMIO::RC_INVALID_OFFSET * @userdata1[0:31] Target huid * @userdata1[32:63] Data Offset, if >= 4GB then subtract 2GB @@ -435,38 +801,38 @@ errlHndl_t ocmbMmioPerformOp(DeviceFW::OperationType i_opType, * @userdata2[0:0] Operation Type * @userdata2[28:31] Access Limit * @userdata2[32:63] Buffer Length - * @devdesc mmioPerformOp> Invalid offset, requested + * @devdesc Invalid offset, requested * address was out of range for a MMIO operation. * @custdesc Unexpected memory subsystem firmware error. */ l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_UNRECOVERABLE, - MMIO::MOD_MMIO_PERFORM_OP, + MMIO::MOD_VALIDATE_OCMB_MMIO_OP, MMIO::RC_INVALID_OFFSET, TWO_UINT32_TO_UINT64( - i_target->getAttr<TARGETING::ATTR_HUID>(), - (l_offset < (4 * GIGABYTE)) ? - (l_offset) : - (l_offset - (2 * GIGABYTE))), + get_huid(i_ocmbTarget), + (i_offset < (4 * GIGABYTE)) ? + (i_offset) : + (i_offset - (2 * GIGABYTE))), TWO_UINT32_TO_UINT64( - (i_opType << 31) | l_accessLimit, - io_buflen), + (i_opType << 31) | io_accessLimit, + i_buflen), ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); break; } - if ( ((l_accessLimit == 4) || (l_accessLimit == 8)) && - ((l_offset % l_accessLimit) != 0) ) + if ( ((io_accessLimit == 4) || (io_accessLimit == 8)) && + ((i_offset % io_accessLimit) != 0) ) { TRACFCOMP(g_trac_mmio, ERR_MRK - "ocmbMmioPerformOp: offset must be aligned with access limit," + "validateOcmbMmioOp: offset must be aligned with access limit," " offset=0x%lX, accessLimit=%ld", - l_offset, l_accessLimit); + i_offset, io_accessLimit); /*@ * @errortype - * @moduleid MMIO::MOD_MMIO_PERFORM_OP + * @moduleid MMIO::MOD_VALIDATE_OCMB_MMIO_OP * @reasoncode MMIO::RC_INVALID_OFFSET_ALIGNMENT * @userdata1[0:31] Target huid * @userdata1[32:63] Data Offset, if >= 4GB then subtract 2GB @@ -474,73 +840,141 @@ errlHndl_t ocmbMmioPerformOp(DeviceFW::OperationType i_opType, * @userdata2[0:0] Operation Type * @userdata2[28:31] Access Limit * @userdata2[32:63] Buffer Length - * @devdesc mmioPerformOp> Requested MMIO address was not + * @devdesc Requested MMIO address was not * aligned properly for the associated device. * @custdesc Unexpected memory subsystem firmware error. */ l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_UNRECOVERABLE, - MMIO::MOD_MMIO_PERFORM_OP, + MMIO::MOD_VALIDATE_OCMB_MMIO_OP, MMIO::RC_INVALID_OFFSET_ALIGNMENT, TWO_UINT32_TO_UINT64( - i_target->getAttr<TARGETING::ATTR_HUID>(), - (l_offset < (4 * GIGABYTE)) ? - (l_offset) : - (l_offset - (2 * GIGABYTE))), + get_huid(i_ocmbTarget), + (i_offset < (4 * GIGABYTE)) ? + (i_offset) : + (i_offset - (2 * GIGABYTE))), TWO_UINT32_TO_UINT64( - (i_opType << 31) | l_accessLimit, - io_buflen), + (i_opType << 31) | io_accessLimit, + i_buflen), ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); break; } + }while(0); + return l_err; +} - // TODO RTC 201493 - Remove these consts once HW group has defined them. - static const uint8_t P9A_MC_DSTLFIR_SUBCHANNEL_A_FAIL_ACTION = 20; - static const uint8_t P9A_MC_DSTLFIR_SUBCHANNEL_B_FAIL_ACTION = 21; + +/******************************************************************************* + * + * See comments in header file + * + */ +errlHndl_t ocmbMmioPerformOp(DeviceFW::OperationType i_opType, + TargetHandle_t i_ocmbTarget, + void* io_buffer, + size_t& io_buflen, + int64_t i_accessType, + va_list i_args) +{ + errlHndl_t l_err = nullptr; + uint64_t l_offset = va_arg(i_args, uint64_t); + uint64_t l_accessLimit = va_arg(i_args, uint64_t); + bool invalidParmError = false; + + TRACDCOMP(g_trac_mmio, ENTER_MRK"ocmbMmioPerformOp"); + TRACDCOMP(g_trac_mmio, INFO_MRK"op=%d, target=0x%.8X", + i_opType, get_huid(i_ocmbTarget)); + TRACDCOMP(g_trac_mmio, INFO_MRK"buffer=%p, length=%d, accessType=%ld", + io_buffer, io_buflen, i_accessType); + TRACDCOMP(g_trac_mmio, INFO_MRK"offset=0x%lX, accessLimit=%ld", + l_offset, l_accessLimit); + + do + { + uint64_t l_addr = i_ocmbTarget->getAttr<ATTR_MMIO_VM_ADDR>(); + + TRACDCOMP(g_trac_mmio, INFO_MRK"MMIO Op l_addr=0x%lX ", l_addr); + + // Validate parameters for MMIO operation + l_err = validateOcmbMmioOp(i_opType, + i_ocmbTarget, + io_buffer, + io_buflen, + l_addr, + l_offset, + l_accessLimit); + if(l_err) + { + invalidParmError = true; + break; + } // read or write io_buflen bytes, l_accessLimit bytes at a time - uint8_t *mm_ptr = reinterpret_cast<uint8_t *>(l_addr + l_offset); - uint8_t *io_ptr = reinterpret_cast<uint8_t *>(io_buffer); - size_t bytes_read_or_written = 0; - for (size_t i = 0;i < io_buflen;i += l_accessLimit) + uint8_t* l_mmPtr = reinterpret_cast<uint8_t *>(l_addr + l_offset); + uint8_t* l_ioPtr = reinterpret_cast<uint8_t *>(io_buffer); + size_t l_bytesCopied = 0; + for (;l_bytesCopied < io_buflen; l_bytesCopied += l_accessLimit) { if (i_opType == DeviceFW::READ) { - mmio_memcpy(io_ptr + i, mm_ptr + i, l_accessLimit); + // Perform requested MMIO read + mmio_memcpy(l_ioPtr + l_bytesCopied, + l_mmPtr + l_bytesCopied, + l_accessLimit); eieio(); - if (!memcmp(io_ptr + i, + + // If there was a UE detected by the processor, a Load UE + // exception will be raised. Kernel code will detect + // that the exception occurred during an OCMB read and + // will write a unique pattern, MMIO_OCMB_UE_DETECTED, into + // the read buffer so that we can quickly know that the MMIO + // read failed. + if (memcmp(l_ioPtr + l_bytesCopied, &MMIO_OCMB_UE_DETECTED, sizeof(MMIO_OCMB_UE_DETECTED))) { - uint64_t scom_data = 0; - uint64_t scom_mask = 0; + //No read failure detected. Keep going. + continue; + } - TRACFCOMP(g_trac_mmio, ERR_MRK - "ocmbMmioPerformOp: unable to complete" - " MMIO read, SUE detected"); + //MMIO Read failed! + TRACFCOMP(g_trac_mmio, ERR_MRK + "ocmbMmioPerformOp: unable to complete" + " MMIO read of offset 0x%08x from OCMB 0x%08x", + l_offset, get_huid(i_ocmbTarget)); + + // Check for channel checkstops (this reads a processor reg) + bool l_checkstopExists = false; + l_err = checkChannelCheckstop(i_ocmbTarget, l_checkstopExists); + if(l_err) + { + // Couldn't deterimine if checkstop exists. + break; + } + if(l_checkstopExists) + { /*@ * @errortype * @moduleid MMIO::MOD_MMIO_PERFORM_OP - * @reasoncode MMIO::RC_BAD_MMIO_READ + * @reasoncode MMIO::RC_MMIO_CHAN_CHECKSTOP * @userdata1[0:31] Target huid * @userdata1[32:63] Data Offset, if >= 4GB then subtract * 2GB (allows offsets to fit in 32 bits) * @userdata2[0:0] Operation Type * @userdata2[28:31] Access Limit * @userdata2[32:63] Buffer Length - * @devdesc mmioPerformOp> MMIO read of an OCMB - * failed. - * @custdesc Unexpected memory subsystem firmware - * error. + * @devdesc OCMB MMIO read failed due to + * channel checkstop + * @custdesc Unexpected memory subsystem error. */ l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_UNRECOVERABLE, - MMIO::MOD_MMIO_PERFORM_OP, + MMIO::MOD_MMIO_CHAN_CHECKSTOP, MMIO::RC_BAD_MMIO_READ, TWO_UINT32_TO_UINT64( - i_target->getAttr<TARGETING::ATTR_HUID>(), + get_huid(i_ocmbTarget), (l_offset < (4 * GIGABYTE)) ? (l_offset) : (l_offset - (2 * GIGABYTE))), @@ -548,198 +982,286 @@ errlHndl_t ocmbMmioPerformOp(DeviceFW::OperationType i_opType, (i_opType << 31) | l_accessLimit, io_buflen), ERRORLOG::ErrlEntry::NO_SW_CALLOUT); - // add OCMB to error log - l_err->addHwCallout(i_target, - HWAS::SRCI_PRIORITY_HIGH, - HWAS::DECONFIG, - HWAS::GARD_NULL); - l_err->addProcedureCallout(HWAS::EPUB_PRC_HB_CODE, - HWAS::SRCI_PRIORITY_LOW); - const auto plid = l_err->plid(); - - auto l_err2 = getProcScom(i_target, - P9A_MCC_USTLFIR, - scom_data); - if (l_err2) - { - l_err2->plid(plid); - errlCommit(l_err2, MMIO_COMP_ID); - } - else - { - scom_mask = (1ull << P9A_MC_USTLFIR_CHANA_BAD_DATA) | - (1ull << P9A_MC_USTLFIR_CHANB_BAD_DATA); - if (scom_data & scom_mask) - { - // TODO RTC 201588 - Error checking on Explorer side - TRACFCOMP(g_trac_mmio, ERR_MRK - "ocmbMmioPerformOp: there was an error on" - " the Explorer side, P9A_MCC_USTLFIR=0x%lX", - scom_data); - - // Clear FIR bits - scom_data &= ~scom_mask; - l_err2 = setProcScom(i_target, - P9A_MCC_USTLFIR, - scom_data); - if (l_err2) - { - l_err2->plid(plid); - errlCommit(l_err2, MMIO_COMP_ID); - } - } - } - l_err2 = getProcScom(i_target, - P9A_MCC_DSTLFIR, - scom_data); - if (l_err2) - { - l_err2->plid(plid); - errlCommit(l_err2, MMIO_COMP_ID); - } - else + addDefaultCallouts(l_err, i_ocmbTarget); + + // Switch to I2C to allow collection of registers on + // OCMB. + disableInbandScomsOcmb(i_ocmbTarget); + + // TODO RTC 201778 - Channel fail handling for Explorer + // dump some registers to the error log here? + + // Look for a better PRD error + // + // TODO RTC 92971 + // There is a potential deadlock if we call PRD here since + // we could recursively call PRD and they are locking a + // mutex. Skip this call for now. + // + //errlHndl_t l_prd_err = ATTN::checkForIplAttentions(); + errlHndl_t l_prd_err = NULL; + if(l_prd_err) { - scom_mask = - (1ull << P9A_MC_DSTLFIR_SUBCHANNEL_A_FAIL_ACTION) | - (1ull << P9A_MC_DSTLFIR_SUBCHANNEL_B_FAIL_ACTION); - if (scom_data & scom_mask) - { - // A channel checkstop has occurred. - // TODO RTC 201778 - Channel Fail Handling for - // Explorer - TRACFCOMP(g_trac_mmio, ERR_MRK - "ocmbMmioPerformOp: there was an error on" - " the Explorer channel, P9A_MCC_DSTLFIR=0x%lX", - scom_data); - } + TRACFCOMP(g_trac_mmio, + ERR_MRK"Error from checkForIplAttentions: " + "PLID=%X", + l_prd_err->plid()); + + //connect up the plids + l_err->plid(l_prd_err->plid()); + + //commit my log as info because PRD's log is better + l_err->setSev(ERRORLOG::ERRL_SEV_INFORMATIONAL); + ERRORLOG::errlCommit(l_err, MMIO_COMP_ID); + l_err = l_prd_err; } break; } + + /*@ + * @errortype + * @moduleid MMIO::MOD_MMIO_PERFORM_OP + * @reasoncode MMIO::RC_BAD_MMIO_READ + * @userdata1[0:31] Target huid + * @userdata1[32:63] Data Offset, if >= 4GB then subtract + * 2GB (allows offsets to fit in 32 bits) + * @userdata2[0:0] Operation Type + * @userdata2[28:31] Access Limit + * @userdata2[32:63] Buffer Length + * @devdesc OCMB MMIO read failed + * @custdesc Unexpected memory subsystem firmware + * error. + */ + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + MMIO::MOD_MMIO_PERFORM_OP, + MMIO::RC_BAD_MMIO_READ, + TWO_UINT32_TO_UINT64( + get_huid(i_ocmbTarget), + (l_offset < (4 * GIGABYTE)) ? + (l_offset) : + (l_offset - (2 * GIGABYTE))), + TWO_UINT32_TO_UINT64( + (i_opType << 31) | l_accessLimit, + io_buflen), + ERRORLOG::ErrlEntry::NO_SW_CALLOUT); + + // NOTE: Explorer error regs cannot be cleared without resetting + // the chip. Error regs may contain failure data from + // previous write transaction. + // + // Check if OCMB has failure data for this transaction. + bool l_errorAddressMatches = false; + bool l_errorAddressIsZero = false; + auto l_err2 = checkOcmbError( + i_ocmbTarget, + reinterpret_cast<uint64_t>(l_mmPtr + + l_bytesCopied), + l_accessLimit, + l_offset, + i_opType, + l_errorAddressMatches, + l_errorAddressIsZero); + if (l_err2) + { + // Failed to read ocmb status register after + // we just determined that there was not + // a channel checkstop? Commit this error + // as informational and add default callouts + // to l_err. + l_err2->plid(l_err->plid()); + ERRORLOG::errlCommit(l_err2, MMIO_COMP_ID); + addDefaultCallouts(l_err, i_ocmbTarget); + break; + } + else if(l_errorAddressMatches) + { + // Read additional OCMB regs to determine if this was + // a HW or SW error. + determineCallouts(i_ocmbTarget, l_offset, i_opType, l_err); + break; + } + else if(l_errorAddressIsZero) + { + // P9A disagrees with OCMB? + TRACFCOMP(g_trac_mmio, + "ocmbMmioPerformOp(read): No Error found on OCMB??" + " 0x%08x", get_huid(i_ocmbTarget)); + addDefaultCallouts(l_err, i_ocmbTarget); + break; + } + + // Address does not match ours and is not zero. + // This was probably caused by an MMIO write failure + // doing an MMIO read to detect if the MMIO write + // was successful or not. + TRACFCOMP(g_trac_mmio, + "ocmbMmioPerformOp(read): Previous error detected on" + " OCMB 0x%08x", get_huid(i_ocmbTarget)); + break; } - else if (i_opType == DeviceFW::WRITE) + else // i_opType == DeviceFW::WRITE { - mmio_memcpy(mm_ptr + i, io_ptr + i, l_accessLimit); + // Perform the MMIO write + mmio_memcpy(l_mmPtr + l_bytesCopied, + l_ioPtr + l_bytesCopied, + l_accessLimit); eieio(); - // TODO RTC 201901 - find a better OCMB register to read, should - // be able to optimize error handling. - - // do a read on the OCMB after writing to it, since writes and - // reads are sequential, the read won't complete until after the - // write. - uint64_t scom_addr = (4 * GIGABYTE) + 4; // RTC 201901 - uint8_t l_ocmbReg[8] = {0}; - - mmio_memcpy(l_ocmbReg, mm_ptr + scom_addr, sizeof(l_ocmbReg)); - eieio(); - if (!memcmp(io_ptr + i, - &MMIO_OCMB_UE_DETECTED, - sizeof(MMIO_OCMB_UE_DETECTED))) + // MMIO write failures will not cause an exception + // to be raised on the host processor. Instead, code + // needs to check a register on the OCMB to determine + // if a specific write failed. + bool l_errorAddressMatches = false; + bool l_errorAddressIsZero = false; + l_err = checkOcmbError( + i_ocmbTarget, + reinterpret_cast<uint64_t>(l_mmPtr + + l_bytesCopied), + l_accessLimit, + l_offset, + i_opType, + l_errorAddressMatches, + l_errorAddressIsZero); + + // Check that we were able to read the error register + // and that it doesn't contain our address. + if(!l_err && !l_errorAddressMatches) { - uint64_t scom_data = 0; - uint64_t scom_mask = 0; + // No errors detected. Keep going. + continue; + } - TRACFCOMP(g_trac_mmio, ERR_MRK - "ocmbMmioPerformOp: unable to complete MMIO" - " write, SUE detected"); + // At this point, we know that the write or status read failed. + // Go ahead and create a basic MMIO Write error log. + TRACFCOMP(g_trac_mmio, ERR_MRK + "ocmbMmioPerformOp: unable to complete" + " MMIO write to offset 0x%08x on OCMB 0x%08x", + l_offset, get_huid(i_ocmbTarget)); - /*@ - * @errortype - * @moduleid MMIO::MOD_MMIO_PERFORM_OP - * @reasoncode MMIO::RC_BAD_MMIO_WRITE - * @userdata1[0:31] Target huid - * @userdata1[32:63] Data Offset, if >= 4GB then subtract - * 2GB (allows offsets to fit in 32 bits) - * @userdata2[0:0] Operation Type - * @userdata2[28:31] Access Limit - * @userdata2[32:63] Buffer Length - * @devdesc mmioPerformOp> MMIO write of an OCMB - * failed. - * @custdesc Unexpected memory subsystem firmware - * error. - */ - l_err = new ERRORLOG::ErrlEntry( - ERRORLOG::ERRL_SEV_UNRECOVERABLE, - MMIO::MOD_MMIO_PERFORM_OP, - MMIO::RC_BAD_MMIO_WRITE, - TWO_UINT32_TO_UINT64( - i_target->getAttr<TARGETING::ATTR_HUID>(), - (l_offset < (4 * GIGABYTE)) ? - (l_offset) : - (l_offset - (2 * GIGABYTE))), - TWO_UINT32_TO_UINT64( - (i_opType << 31) | l_accessLimit, - io_buflen), - ERRORLOG::ErrlEntry::NO_SW_CALLOUT); - // add OCMB to error log - l_err->addHwCallout(i_target, - HWAS::SRCI_PRIORITY_HIGH, - HWAS::DECONFIG, - HWAS::GARD_NULL); - l_err->addProcedureCallout(HWAS::EPUB_PRC_HB_CODE, - HWAS::SRCI_PRIORITY_LOW); - const auto plid = l_err->plid(); - - auto l_err2 = getProcScom(i_target, - P9A_MCC_DSTLFIR, - scom_data); - if (l_err2) + /*@ + * @errortype + * @moduleid MMIO::MOD_MMIO_PERFORM_OP + * @reasoncode MMIO::RC_BAD_MMIO_WRITE + * @userdata1[0:31] Target huid + * @userdata1[32:63] Data Offset, if >= 4GB then subtract + * 2GB (allows offsets to fit in 32 bits) + * @userdata2[0:0] Operation Type + * @userdata2[28:31] Access Limit + * @userdata2[32:63] Buffer Length + * @devdesc OCMB MMIO write failed + * @custdesc Unexpected memory subsystem firmware + * error. + */ + auto l_writeErr = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + MMIO::MOD_MMIO_PERFORM_OP, + MMIO::RC_BAD_MMIO_WRITE, + TWO_UINT32_TO_UINT64( + get_huid(i_ocmbTarget), + (l_offset < (4 * GIGABYTE)) ? + (l_offset) : + (l_offset - (2 * GIGABYTE))), + TWO_UINT32_TO_UINT64( + (i_opType << 31) | l_accessLimit, + io_buflen), + ERRORLOG::ErrlEntry::NO_SW_CALLOUT); + + // Check if the register read failed + if(l_err) + { + // We were not able to read the error register on the + // OCMB. The most likely scenario here is that there + // was a HW failure (possibly a channel checkstop). + // + // NOTE: If we only logged this error as-is and no + // other error, we wouldn't know that the read was + // a result of a write. Instead, log both errors + // and set the PLID's to be the same. + TRACFCOMP(g_trac_mmio, + "ocmbMmioPerformOp(write): Fail to read status on" + " OCMB 0x%08x", get_huid(i_ocmbTarget)); + l_writeErr->plid(l_err->plid()); + + // Set severity of write error to match the read + // error if there is a channel checkstop. + bool l_checkstopExists = false; + errlHndl_t l_xstopErr = nullptr; + l_xstopErr = checkChannelCheckstop(i_ocmbTarget, + l_checkstopExists); + if(l_xstopErr) { - l_err2->plid(plid); - errlCommit(l_err2, MMIO_COMP_ID); + // Couldn't deterimine if checkstop exists. + // Commit the xstop error and assume no checkstop. + l_xstopErr->collectTrace(MMIO_COMP_NAME); + ERRORLOG::errlCommit(l_xstopErr, MMIO_COMP_ID); } - else + if(l_checkstopExists) { - scom_mask = - (1ull << P9A_MC_DSTLFIR_SUBCHANNEL_A_FAIL_ACTION) | - (1ull << P9A_MC_DSTLFIR_SUBCHANNEL_B_FAIL_ACTION); - if (scom_data & scom_mask) - { - // A channel checkstop has occurred. - // TODO RTC 201778 - Channel Fail Handling for - // Explorer - TRACFCOMP(g_trac_mmio, ERR_MRK - "ocmbMmioPerformOp: there was an error on" - " the Explorer channel, P9A_MCC_DSTLFIR=0x%lX", - scom_data); - } + l_writeErr->setSev(l_err->sev()); } - + ERRORLOG::errlCommit(l_err, MMIO_COMP_ID); + l_err = l_writeErr; break; } - } - bytes_read_or_written += l_accessLimit; - } + l_err = l_writeErr; + l_writeErr = nullptr; + + // At this point, we were able to read the error register + // and determined that it matched the address of our + // transaction. No need to check for a channel checkstop + // on the write operation since we already did that in the + // read path when we tried to read the OCMB status register. - io_buflen = bytes_read_or_written; + // Read additional OCMB regs to determine if this was + // a HW or SW error. + determineCallouts(i_ocmbTarget, l_offset, i_opType, l_err); + break; + } // end of write block + + } // end of for loop + + io_buflen = l_bytesCopied; } while(0); if (l_err) { + // Only disable if HW error, not for user parameter failures + if (!invalidParmError) + { + // Switch over to using I2C to prevent further MMIO access + // to this OCMB (error regs cannot be cleared on Explorer). + disableInbandScomsOcmb(i_ocmbTarget); + } + l_err->collectTrace(MMIO_COMP_NAME); } - TRACDCOMP(g_trac_mmio, EXIT_MRK"mmioPerformOp"); + TRACDCOMP(g_trac_mmio, EXIT_MRK"ocmbMmioPerformOp"); return l_err; } +/******************************************************************************* + * + * @brief Finds the processor connected to the target OCMB chip. + * + */ static -TARGETING::TargetHandle_t getParentProc(TARGETING::TargetHandle_t i_target) +TargetHandle_t getParentProc( + const TargetHandle_t i_ocmbTarget) { - TARGETING::TargetHandle_t proc = nullptr; - TARGETING::TargetHandleList list; - TARGETING::PredicateCTM pred(TARGETING::CLASS_CHIP, - TARGETING::TYPE_PROC); - - TARGETING::targetService().getAssociated( - list, - i_target, - TARGETING::TargetService::PARENT_BY_AFFINITY, - TARGETING::TargetService::ALL, + TargetHandle_t proc = nullptr; + TargetHandleList list; + PredicateCTM pred(CLASS_CHIP, TYPE_PROC); + + targetService().getAssociated( list, + i_ocmbTarget, + TargetService::PARENT_BY_AFFINITY, + TargetService::ALL, &pred); if (list.size() == 1) @@ -750,19 +1272,25 @@ TARGETING::TargetHandle_t getParentProc(TARGETING::TargetHandle_t i_target) return proc; } +/******************************************************************************* + * + * @brief Reads a scom register on the processor connected to the target OCMB + * chip. + * + */ static -errlHndl_t getProcScom(TARGETING::TargetHandle_t i_target, +errlHndl_t getProcScom(const TargetHandle_t i_ocmbTarget, uint64_t i_scomAddr, uint64_t &o_scomData) { errlHndl_t l_err = nullptr; - auto proc = getParentProc(i_target); + auto proc = getParentProc(i_ocmbTarget); if (proc == nullptr) { TRACFCOMP(g_trac_mmio, ERR_MRK "getProcScom: Unable to find parent processor for target(0x%X)", - i_target->getAttr<TARGETING::ATTR_HUID>()); + get_huid(i_ocmbTarget)); /*@ * @errortype @@ -770,14 +1298,14 @@ errlHndl_t getProcScom(TARGETING::TargetHandle_t i_target, * @reasoncode MMIO::RC_PROC_NOT_FOUND * @userdata1 Target huid * @userdata2 SCOM address - * @devdesc getProcScom> Unable to find parent processor for target. + * @devdesc Unable to find parent processor for target. * @custdesc Unexpected memory subsystem firmware error. */ l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_UNRECOVERABLE, MMIO::MOD_MMIO_GET_PROC_SCOM, MMIO::RC_PROC_NOT_FOUND, - i_target->getAttr<TARGETING::ATTR_HUID>(), + get_huid(i_ocmbTarget), i_scomAddr, ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); } @@ -794,19 +1322,26 @@ errlHndl_t getProcScom(TARGETING::TargetHandle_t i_target, return l_err; } -static -errlHndl_t setProcScom(TARGETING::TargetHandle_t i_target, +/******************************************************************************* + * + * @brief Writes a scom register on the processor connected to the target OCMB + * chip. + * + */ +// NOTE: removed static qualifier to prevent compiler from complaining about +// the function not being used. +errlHndl_t setProcScom(const TargetHandle_t i_ocmbTarget, uint64_t i_scomAddr, uint64_t i_scomData) { errlHndl_t l_err = nullptr; - auto proc = getParentProc(i_target); + auto proc = getParentProc(i_ocmbTarget); if (proc == nullptr) { TRACFCOMP(g_trac_mmio, ERR_MRK "setProcScom: Unable to find parent processor for target(0x%X)", - i_target->getAttr<TARGETING::ATTR_HUID>()); + get_huid(i_ocmbTarget)); /*@ * @errortype @@ -814,14 +1349,14 @@ errlHndl_t setProcScom(TARGETING::TargetHandle_t i_target, * @reasoncode MMIO::RC_PROC_NOT_FOUND * @userdata1 Target huid * @userdata2 SCOM address - * @devdesc setProcScom> Unable to find parent processor for target. + * @devdesc Unable to find parent processor for target. * @custdesc Unexpected memory subsystem firmware error. */ l_err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_UNRECOVERABLE, MMIO::MOD_MMIO_SET_PROC_SCOM, MMIO::RC_PROC_NOT_FOUND, - i_target->getAttr<TARGETING::ATTR_HUID>(), + get_huid(i_ocmbTarget), i_scomAddr, ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); } @@ -838,6 +1373,13 @@ errlHndl_t setProcScom(TARGETING::TargetHandle_t i_target, return l_err; } + +/******************************************************************************* + * + * @brief Copies len bytes of data from location pointed to by vsrc to location + * pointed to by vdest. + * + */ static void *mmio_memcpy(void *vdest, const void *vsrc, size_t len) { diff --git a/src/usr/mmio/mmio.H b/src/usr/mmio/mmio.H index d69ade6f7..96ea25e8d 100644 --- a/src/usr/mmio/mmio.H +++ b/src/usr/mmio/mmio.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -25,6 +25,10 @@ #ifndef __MMIO_H #define __MMIO_H +#include <errl/errlentry.H> +#include <devicefw/driverif.H> +#include <targeting/common/target.H> + /** @file mmio.H * @brief Provides interface to perform MMIO operations to Explorer chips * */ diff --git a/src/usr/mmio/mmio_explorer.C b/src/usr/mmio/mmio_explorer.C new file mode 100644 index 000000000..9565c8341 --- /dev/null +++ b/src/usr/mmio/mmio_explorer.C @@ -0,0 +1,474 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/mmio/mmio_explorer.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#include <devicefw/driverif.H> +#include <errl/errlentry.H> +#include <errl/errlmanager.H> +#include <errl/errludtarget.H> +#include <errl/errludlogregister.H> +#include <explorer_scom_addresses.H> +#include <lib/inband/exp_inband.H> +#include <mmio/mmio_reasoncodes.H> + +// Trace definition +extern trace_desc_t* g_trac_mmio; + +using namespace TARGETING; + +namespace MMIOEXP +{ + +#define MMIOEXP_SCOM2OFFSET(_SCOM_ADDR) \ + (mss::exp::ib::EXPLR_IB_MMIO_OFFSET | (_SCOM_ADDR << 3)) + +/** + * @brief Possible Open CAPI response codes for config operations + */ +enum +{ + OCAPI_RETRY_REQUEST = 0x2, + OCAPI_DATA_ERROR = 0x8, + OCAPI_UNSUPPORTED_OP_LENGTH = 0x9, + OCAPI_BAD_ADDRESS = 0xB, + OCAPI_FAILED = 0xE, +}; + +/** + * @brief Possible PCB error codes for non-config operations + */ +enum +{ + PCB_OK = 0x0, + PCB_INVALID_ADDRESS = 0x4, + PCB_PARITY_ERROR = 0x6, + PCB_TIMEOUT = 0x7, +}; + +/** + * @brief bit-field definitions for MCFGERR register + */ +typedef union mcfgerrReg +{ + struct + { + uint64_t reserved :16; + uint64_t resp_code :4; + uint64_t bdi :1; + uint64_t error_type :3; + uint64_t device :5; + uint64_t function :3; + uint64_t dev_func_mismatch :1; + uint64_t detect_bad_op :1; + uint64_t tbit_is_1 :1; + uint64_t data_is_bad :1; + uint64_t pl_is_invalid :1; + uint64_t bad_op_or_align :1; + uint64_t addr_no_implemented:1; + uint64_t rdata_vld :1; + uint64_t tbit :1; + uint64_t plen :3; + uint64_t portnun :2; + uint64_t dl :2; + uint64_t capptag :16; + }; + uint64_t word64; +}mcfgerrReg_t; + +/** + * @brief bit-field definitions for GIF2PCB_ERROR register + */ +typedef union gif2pcbErrorReg +{ + struct + { + uint64_t parity_error_rsp_info :1; + uint64_t parity_error_rsp_data_0 :1; + uint64_t parity_error_rsp_data_1 :1; + uint64_t parity_error_rsp_data_2 :1; + uint64_t parity_error_rsp_data_3 :1; + uint64_t timeout_error :1; + uint64_t int_addr_access_error :1; + uint64_t invalid_access :1; + uint64_t pcb_err_code :3; + uint64_t axi_read_addr_parity_error :1; + uint64_t axi_write_addr_parity_error :1; + uint64_t axi_write_data_parity_error_31_24 :1; + uint64_t axi_write_data_parity_error_23_16 :1; + uint64_t axi_write_data_parity_error_15_8 :1; + uint64_t axi_write_data_parity_error_7_0 :1; + uint64_t pib2gif_parity_error :1; + uint64_t reserved :46; + }; + struct + { + uint64_t used_bits :18; + uint64_t unused_bits :46; + }; + uint64_t word64; +}gif2pcbErrorReg_t; + +/** + * @brief bit-field definitions for PIB2GIF_ERROR register + */ +typedef union pib2gifErrorReg +{ + struct + { + uint64_t parity_error_req_data_0:1; + uint64_t parity_error_req_data_1:1; + uint64_t parity_error_req_data_2:1; + uint64_t parity_error_req_data_3:1; + uint64_t parity_error_req_addr_0:1; + uint64_t parity_error_req_addr_1:1; + uint64_t parity_error_req_ctrl:1; + uint64_t timeout_error:1; + uint64_t int_addr_access_error:1; + uint64_t parity_error_on_fsm:1; + uint64_t parity_error_on_reg0:1; + uint64_t parity_error_on_reg1:1; + uint64_t parity_error_on_reg2:1; + uint64_t parity_error_on_reg3:1; + uint64_t parity_error_on_reg4:1; + uint64_t parity_error_on_reg5:1; + uint64_t invalid_address_error:1; + uint64_t reserved1:15; + uint64_t gif2pcb_error:18; + uint64_t reserved2:14; + }; + uint64_t word64; +}pib2gifErrorReg_t; + +// Explorer MMIO addresses only have 35 bits +constexpr uint64_t MASK_35BITS = 0x7FFFFFFFFull; + + +/******************************************************************************* + * + * See header file for comments + */ +errlHndl_t checkExpError(const TargetHandle_t i_expTarget, + const uint64_t i_va, + const uint64_t i_accessLimit, + const uint64_t i_offset, + DeviceFW::OperationType i_opType, + bool& o_errorAddressMatches, + bool& o_errorAddressIsZero) +{ + errlHndl_t l_err = nullptr; + uint64_t l_errAddr = 0; + bool l_errorAddressMatches = false; + bool l_errorAddressIsZero = false; + const char* l_regStr = nullptr; + + // NOTE: mmio_memcpy could be doing multiple transactions. This means + // we need to test the explorer error address register against a + // range of values instead of a single value. + // NOTE: Explorer only uses the low 35 bits of the address for MMIO access + const uint64_t l_mmioAddr35Lo = i_va & MASK_35BITS; + const uint64_t l_mmioAddr35Hi = (i_va + i_accessLimit) & MASK_35BITS; + + do + { + // For access to CONFIG space, the MCFGERRA scom register + // contains the first failing address. + if(i_offset < mss::exp::ib::EXPLR_IB_MMIO_OFFSET) + { + auto l_reqSize = sizeof(l_errAddr); + l_err = DeviceFW::deviceRead( + i_expTarget, + &l_errAddr, + l_reqSize, + DEVICE_SCOM_ADDRESS(EXPLR_MMIO_MCFGERRA)); + if(l_err) + { + TRACFCOMP(g_trac_mmio, ERR_MRK + "checkExpError: getscom(MCFGERRA) failed." + " huid[0x%08x]", get_huid(i_expTarget)); + break; + } + l_regStr = "MCFGERRA"; + } + // Otherwise, we are accessing a non-config address and, if there + // is a failure, the MMIO address will show up in the lower 35 bits of + // the MMIOERR register + else + { + // If the transaction was a read to this error register then + // we already know that it failed. Don't keep trying to + // read it or we could end up in a recursive loop. + if((i_opType == DeviceFW::READ) && + (i_offset == MMIOEXP_SCOM2OFFSET(EXPLR_MMIO_MMIOERR))) + { + break; + } + auto l_reqSize = sizeof(l_errAddr); + l_err = DeviceFW::deviceRead( + i_expTarget, + &l_errAddr, + l_reqSize, + DEVICE_SCOM_ADDRESS(EXPLR_MMIO_MMIOERR)); + if(l_err) + { + TRACFCOMP(g_trac_mmio, ERR_MRK + "checkExpError: getscom(MMIOERR) failed." + " huid[0x%08x]", get_huid(i_expTarget)); + break; + } + l_regStr = "MMIOERR"; + } + + // Check if error address from explorer is zero, meaning that + // explorer did not detect an error. + if(l_errAddr == 0) + { + l_errorAddressIsZero = true; + } + + // Check if 35-bit error address is outside our transaction + // access range + const uint64_t l_errAddr35 = l_errAddr & MASK_35BITS; + if((l_errAddr35 < l_mmioAddr35Lo) || + (l_errAddr35 >= l_mmioAddr35Hi)) + { + TRACDCOMP(g_trac_mmio, + "checkExpError: %s: 0x%09llx is not between 0x%09llx and" + " 0x%09llx on huid[0x%08x]", + l_regStr, l_errAddr, l_mmioAddr35Lo, + l_mmioAddr35Hi, get_huid(i_expTarget)); + // Error address is outside our transaction range so this error + // was not caused by our transaction. + break; + } + + TRACFCOMP(g_trac_mmio, ERR_MRK + "checkExpError: %s: 0x%09llx is between 0x%09llx and" + " 0x%09llx on huid[0x%08x]", + l_regStr, l_errAddr35, l_mmioAddr35Lo, + l_mmioAddr35Hi, get_huid(i_expTarget)); + l_errorAddressMatches = true; + + // NOTE: These registers cannot be cleared without resetting the chip. + + }while(0); + + o_errorAddressMatches = l_errorAddressMatches; + o_errorAddressIsZero = l_errorAddressIsZero; + return l_err; +} + +/******************************************************************************* + * + * See header file for comments + */ +errlHndl_t determineExpCallouts(const TargetHandle_t i_expTarget, + const uint64_t i_offset, + DeviceFW::OperationType i_opType, + errlHndl_t i_err, + bool& o_fwFailure) +{ + bool l_fwFailure = false; //default to a hw failure + errlHndl_t l_err = nullptr; + size_t l_reqSize = 0; + ERRORLOG::ErrlUserDetailsLogRegister l_regDump(i_expTarget); + + do + { + // If the transaction was a read to any of these error registers, + // that we're about to read then we know that it already failed. + // Don't keep trying to read it or we could end up in a recursive + // loop. + if(i_opType == DeviceFW::READ) + { + switch(i_offset) + { + case MMIOEXP_SCOM2OFFSET(EXPLR_MMIO_MCFGERR): + case MMIOEXP_SCOM2OFFSET(EXPLR_MMIO_MCFGERRA): + case MMIOEXP_SCOM2OFFSET(EXPLR_MMIO_MMIOERR): + case MMIOEXP_SCOM2OFFSET(EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG): + case MMIOEXP_SCOM2OFFSET(EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG): + case MMIOEXP_SCOM2OFFSET(EXPLR_MMIO_MFIR): + case MMIOEXP_SCOM2OFFSET(EXPLR_MMIO_MFIRWOF): + TRACFCOMP(g_trac_mmio, + "determineExpCallouts: recursive loop detected:" + " OCMB[0x%08x] offset[0x%016llx]", + TARGETING::get_huid(i_expTarget), i_offset); + /*@ + * @errortype + * @moduleid MMIO::MOD_DETERMINE_EXP_CALLOUTS + * @reasoncode MMIO::RC_BAD_MMIO_READ + * @userdata1 OCMB huid + * @userdata2 Address offset + * @devdesc OCMB MMIO read failed + * @custdesc Unexpected memory subsystem firmware + * error. + */ + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + MMIO::MOD_DETERMINE_EXP_CALLOUTS, + MMIO::RC_BAD_MMIO_READ, + TARGETING::get_huid(i_expTarget), + i_offset, + ERRORLOG::ErrlEntry::NO_SW_CALLOUT); + break; + + default: + break; + } + if(l_err) + { + break; + } + } + + // Check if this is an access to config space + if(i_offset < mss::exp::ib::EXPLR_IB_MMIO_OFFSET) + { + mcfgerrReg_t l_reg; + + TRACFCOMP(g_trac_mmio, + "determineExpCallouts: getting callouts for failed config" + " space transaction on OCMB[0x%08x]", get_huid(i_expTarget)); + + // Read the Explorer MCFGERR register + // NOTE: This register is not clearable + l_reqSize = sizeof(l_reg.word64); + l_err = DeviceFW::deviceRead( + i_expTarget, + &l_reg.word64, + l_reqSize, + DEVICE_SCOM_ADDRESS(EXPLR_MMIO_MCFGERR)); + if(l_err) + { + TRACFCOMP(g_trac_mmio, ERR_MRK + "determineExpCallouts: getscom(MCFGERR) failed" + " on OCMB[0x%08x]", get_huid(i_expTarget)); + break; + } + + TRACFCOMP(g_trac_mmio, + "determineExpCallouts: MCFGERR: 0x%016llx on" + " OCMB[0x%08x]", l_reg.word64, get_huid(i_expTarget)); + + // Extract the OCAPI response code from the register + switch(l_reg.resp_code) + { + // Firmware Errors + case OCAPI_UNSUPPORTED_OP_LENGTH: + case OCAPI_BAD_ADDRESS: + l_fwFailure = true; + break; + + // This one could be caused by a bad address (FW) if there is + // a device/function mismatch. Otherwise, it's bad HW. + case OCAPI_FAILED: + if(l_reg.dev_func_mismatch) + { + l_fwFailure = true; + break; + } + break; + + // Everything else is HW failure + default: + break; + } + + // Dump some regs specific to config failures + l_regDump.addDataBuffer(&l_reg.word64, sizeof(l_reg.word64), + DEVICE_SCOM_ADDRESS(EXPLR_MMIO_MCFGERR)); + l_regDump.addData(DEVICE_SCOM_ADDRESS(EXPLR_MMIO_MCFGERRA)); + break; + } + + // We were accessing a SCOM reg, MSCC reg, or SRAM + + pib2gifErrorReg_t l_pib2gif; + gif2pcbErrorReg_t l_gif2pcb; + + TRACFCOMP(g_trac_mmio, + "determineExpCallouts: getting callouts for failed MMIO space" + " transaction on OCMB[0x%08x]", get_huid(i_expTarget)); + + // Read the PIB2GIF error reg + // NOTE: This register is ONLY accessible through MMIO path, not I2C. + l_reqSize = sizeof(l_pib2gif.word64); + l_err = DeviceFW::deviceRead( + i_expTarget, + &l_pib2gif.word64, + l_reqSize, + DEVICE_SCOM_ADDRESS(EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG)); + if(l_err) + { + TRACFCOMP(g_trac_mmio, ERR_MRK + "determineExpCallouts: getscom(PIB2GIF_ERROR_REG) failed" + " on OCMB[0x%08x]", get_huid(i_expTarget)); + break; + } + + TRACFCOMP(g_trac_mmio, + "determineExpCallouts: PIB2GIF_ERROR_REG: 0x%016llx" + " on OCMB[0x%08x]", l_pib2gif.word64, get_huid(i_expTarget)); + + // The pib2gif error register contains a copy of the gif2pcb error reg. + // No need to read it again, just copy it into our struct. + l_gif2pcb.word64 = 0; + l_gif2pcb.used_bits = l_pib2gif.gif2pcb_error; + + TRACFCOMP(g_trac_mmio, + "determineExpCallouts: GIF2PCB_ERROR_REG: 0x%016llx" + " on OCMB[0x%08x]", l_gif2pcb.word64, get_huid(i_expTarget)); + + // Check for software errors + if((l_pib2gif.invalid_address_error) || + (l_gif2pcb.invalid_access) || + (l_gif2pcb.pcb_err_code == PCB_INVALID_ADDRESS)) + { + l_fwFailure = true; + } + + // dump some regs specific to MMIO failures + l_regDump.addDataBuffer(&l_pib2gif.word64, sizeof(l_pib2gif.word64), + DEVICE_SCOM_ADDRESS(EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG)); + l_regDump.addData( + DEVICE_SCOM_ADDRESS(EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG)); + l_regDump.addData(DEVICE_SCOM_ADDRESS(EXPLR_MMIO_MMIOERR)); + break; + }while(0); + + if(!l_err) + { + // Dump some registers common to both types of transaction types + l_regDump.addData(DEVICE_SCOM_ADDRESS(EXPLR_MMIO_MFIR)); + l_regDump.addData(DEVICE_SCOM_ADDRESS(EXPLR_MMIO_MFIRWOF)); + + // Add our register dump to the error log. + l_regDump.addToLog(i_err); + } + + // Notify caller of HW or FW failure + o_fwFailure = l_fwFailure; + return l_err; +} + +}; // End MMIOEXP namespace diff --git a/src/usr/mmio/mmio_explorer.H b/src/usr/mmio/mmio_explorer.H new file mode 100644 index 000000000..a7b6b1d04 --- /dev/null +++ b/src/usr/mmio/mmio_explorer.H @@ -0,0 +1,90 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/mmio/mmio_explorer.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef __MMIO_EXPLORER_H +#define __MMIO_EXPLORER_H + +/** @file mmio_explorer.H + * @brief Provides interface to perform Explorer MMIO operations + */ + +#include <errl/errlentry.H> +#include <targeting/common/target.H> + +namespace MMIOEXP +{ + +/** + * + * @brief Determine if the OCMB detected a failure on a specific MMIO + * transaction to the specified OCMB target. + * + * @param[in] i_expTarget Handle for the target OCMB chip. + * @param[in] i_va Virtual address of the transaction to check + * @param[in] i_accessLimit The byte range of the transaction + * @param[in] i_offset The offset of the config reg, scom reg, MSCC reg or + * SRAM to be accessed on the explorer chip. + * @param[in] i_opType The operation type (read or write) + * @param[out] o_errorAddressMatches Set to true if the OCMB chip detected a + * failure on our transaction. + * @param[out] o_errorAddressIsZero Set to true if no error has been detected + * yet. + * @return nullptr on succesful read of OCMB error status, non-null otherwise. + * + */ +errlHndl_t checkExpError(const TARGETING::TargetHandle_t i_expTarget, + const uint64_t i_va, + const uint64_t i_accessLimit, + const uint64_t i_offset, + DeviceFW::OperationType i_opType, + bool& o_errorAddressMatches, + bool& o_errorAddressIsZero); + +/** + * + * @brief Collect additional failure data from the target explorer chip and add + * appropriate FRU/Procedure callouts. + * + * @note Must call checkExpError to determine that a transaction failed before + * calling this function. + * + * @param[in] i_expTarget Handle of explorer to collect extra FFDC from + * @param[in] i_offset The offset of the config reg, scom reg, MSCC reg or + * SRAM that was accessed on the explorer chip. + * @param[in] i_opType The operation type (read or write) + * @param[in] i_err There error log for adding additional FFDC + * @param[out] o_fwFailure The failure was a firmware failure if true, + * otherwise, it was a hardware failure. + * + * @return non-nullptr if unable to determine failure type, nullptr otherwise. + */ +errlHndl_t determineExpCallouts(const TARGETING::TargetHandle_t i_expTarget, + const uint64_t i_offset, + DeviceFW::OperationType i_opType, + errlHndl_t i_err, + bool& o_fwFailure); + +}; // End MMIOEXP namespace + +#endif diff --git a/src/usr/mmio/runtime/makefile b/src/usr/mmio/runtime/makefile new file mode 100644 index 000000000..c61c68c39 --- /dev/null +++ b/src/usr/mmio/runtime/makefile @@ -0,0 +1,33 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/mmio/runtime/makefile $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2019 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +HOSTBOOT_RUNTIME = 1 +ROOTPATH = ../../../.. +MODULE = mmio_rt + +#include unique object modules +OBJS += rt_mmio.o + +VPATH += .. +include $(ROOTPATH)/config.mk diff --git a/src/usr/mmio/runtime/rt_mmio.C b/src/usr/mmio/runtime/rt_mmio.C new file mode 100644 index 000000000..620dff855 --- /dev/null +++ b/src/usr/mmio/runtime/rt_mmio.C @@ -0,0 +1,108 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/mmio/runtime/rt_mmio.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +// @file src/usr/mmio/runtime/rt_mmio.C +// @brief Runtime mmio operations -- particularly for scom operations + +#include "../mmio.H" +#include <scom/runtime/rt_scomif.H> +#include <devicefw/driverif.H> +#include <errl/errlentry.H> +#include <limits.h> +#include <usr/mmio/mmio_reasoncodes.H> + +// Trace definition +trace_desc_t* g_trac_mmio = NULL; +TRAC_INIT(&g_trac_mmio, MMIO_COMP_NAME, 2*KILOBYTE, TRACE::BUFFER_SLOW); + +//#define TRACUCOMP(args...) TRACFCOMP(args) +#define TRACUCOMP(args...) + +namespace MMIO +{ +// Direct OCMB reads and writes to the device's memory mapped memory. +DEVICE_REGISTER_ROUTE(DeviceFW::WILDCARD, + DeviceFW::MMIO, + TARGETING::TYPE_OCMB_CHIP, + ocmbMmioPerformOp); + +/******************************************************************************* + * + * See comments in header file + * + */ +errlHndl_t ocmbMmioPerformOp(DeviceFW::OperationType i_opType, + TARGETING::TargetHandle_t i_ocmbTarget, + void* io_buffer, + size_t& io_buflen, + int64_t i_accessType, + va_list i_args) +{ + errlHndl_t l_err = nullptr; + uint64_t l_offset = va_arg(i_args, uint64_t); + + TRACUCOMP(g_trac_mmio, ENTER_MRK"runtime ocmbMmioPerformOp"); + TRACUCOMP(g_trac_mmio, INFO_MRK"op=%d, target=0x%.8X", + i_opType, TARGETING::get_huid(i_ocmbTarget)); + TRACUCOMP(g_trac_mmio, INFO_MRK"buffer=%p, length=%d, accessType=%ld", + io_buffer, io_buflen, i_accessType); + TRACUCOMP(g_trac_mmio, INFO_MRK"offset=0x%lX", l_offset); + + // Verify offset is within scom mmio range + if ( (l_offset >= (4 * GIGABYTE)) && (l_offset < (6 * GIGABYTE)) ) + { + // send message to hypervisor level to do the mmio operation + l_err = SCOM::sendScomToHyp(i_opType, i_ocmbTarget, + l_offset, io_buffer); + } + else + { + // Only Scom range is supported for MMIO runtime context + /*@ + * @errortype + * @moduleid MMIO::RT_OCMB_MMIO_PERFORM_OP + * @reasoncode MMIO::RC_INVALID_OFFSET + * @userdata1[0:31] Target huid + * @userdata1[32:63] Data Offset + * @userdata2[0:31] Operation Type + * @userdata2[32:63] Buffer Length + * @devdesc Invalid offset, requested + * address was out of range for a MMIO operation. + * @custdesc Unexpected memory subsystem firmware error. + */ + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + MMIO::RT_OCMB_MMIO_PERFORM_OP, + MMIO::RC_INVALID_OFFSET, + TWO_UINT32_TO_UINT64( + TARGETING::get_huid(i_ocmbTarget), + l_offset), + TWO_UINT32_TO_UINT64(i_opType, io_buflen), + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + } + + return l_err; +} + +}; // end namespace MMIO diff --git a/src/usr/mmio/test/makefile b/src/usr/mmio/test/makefile index 133f3ca44..3a9af5d71 100644 --- a/src/usr/mmio/test/makefile +++ b/src/usr/mmio/test/makefile @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2011,2018 +# Contributors Listed Below - COPYRIGHT 2011,2019 # [+] International Business Machines Corp. # # @@ -25,6 +25,11 @@ ROOTPATH = ../../../.. MODULE = testmmio + +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/explorer/common/include/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/ +EXTRAINCDIR += ${ROOTPATH}/src/usr/expaccess/ + TESTS = *.H diff --git a/src/usr/mmio/test/mmiotest.H b/src/usr/mmio/test/mmiotest.H index f7abd7816..984e94925 100644 --- a/src/usr/mmio/test/mmiotest.H +++ b/src/usr/mmio/test/mmiotest.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2018 */ +/* Contributors Listed Below - COPYRIGHT 2011,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,83 +27,238 @@ #include <errl/errlentry.H> #include <limits.h> #include <devicefw/driverif.H> -#include <mmio/mmio.H> +#include "../mmio.H" +#include <targeting/common/utilFilter.H> +#include <explorer_scom_addresses.H> +#include <exp_oc_regs.H> +#include <sys/mmio.h> +#include <utils/chipids.H> +#include <test/exptest_utils.H> -extern trace_desc_t* g_trac_mmio; +#define SCOM2MMIO_ADDR(_ADDR) (EXPLR_IB_MMIO_OFFSET | (_ADDR << 3)) +#define CNFG2MMIO_ADDR(_ADDR) (EXPLR_IB_CONFIG_OFFSET | _ADDR) +#define BYTESWAP64(_DATA) (__builtin_bswap64(_DATA)) + +static const uint64_t EXPLR_IB_CONFIG_OFFSET = 0x0000000000000000ull; +static const uint64_t EXPLR_IB_MMIO_OFFSET = 0x0000000100000000ull; // 4GB + +// NOTE: changing this address requires changes +// to src/build/simics/standalone.simics +static const uint64_t EXPLR_INVALID_SCOM_ADDR = + EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_0; + +using namespace TARGETING; class MmioTest : public CxxTest::TestSuite { public: /** - * @brief Test valid MMIO calls + * @brief Test MMIO calls */ - void test_Valid(void) + void testExplrMMIO(void) { - TRACFCOMP( g_trac_mmio, "MmioTest::test_Valid> Start" ); + TS_INFO("testExplrMMIO> Start" ); - uint64_t fails = 0; - uint64_t total = 0; errlHndl_t l_err = nullptr; - uint64_t regdata = 0; - size_t op_size = sizeof(uint64_t); - -// TODO RTC 202533 - enable this test once the Axone model is IPLing -// successfully in Simics. -#if 0 - // Get OCMB target, return if there is no OCMB - TARGETING::TargetHandle_t ocmb_target = nullptr; - TARGETING::TargetHandleList ocmb_target_list; - getAllChips(ocmb_target_list, TARGETING::TYPE_OCMB_CHIP); - if (ocmb_target_list.size() == 0) + uint32_t regdata4 = 0; + size_t op_size = 0; + uint64_t l_buffer64; + + // Needed since the device operations could be using inband communication in error path + HB_MUTEX_SERIALIZE_TEST_LOCK_ATTR l_mutex = exptest::getTestMutex(); + if (l_mutex == nullptr) { - TRACFCOMP(g_trac_fsiscom, "MmioTest::test_Valid> Target is NULL"); - TS_INFO("MmioTest::test_Valid> Target is NULL"); + TS_FAIL("testExplrMMIO: unable to get test mutex"); return; } - ocmb_target = ocmb_target_list[0]; - - // read - ++total; - l_err = MMIO::mmioPerformOp( - DeviceFW::READ, - ocmb_target, - ®data, - op_size, - 0x0, - op_size); - if(l_err != nullptr) - { - TRACFCOMP(g_trac_mmio, - "MmioTest::test_Valid> Error for read, RC=0x%04X", - ERRL_GETRC_SAFE(l_err)); - TS_FAIL("MmioTest::test_Valid> Error for read, RC=0x%04X", - ERRL_GETRC_SAFE(l_err)); - ++fails; - errlCommit(l_err, MMIO_COMP_ID); - } - // write - ++total; - l_err = MMIO::mmioPerformOp( - DeviceFW::WRITE, - ocmb_target, - ®data, - op_size, - 0x08, - op_size); - if(l_err != nullptr) + // >> atomic section + mutex_lock(l_mutex); + + TargetHandle_t explr_target = nullptr; + + do { + + // Get OCMB target, return if there is no OCMB + TargetHandleList ocmb_target_list; + getAllChips(ocmb_target_list, TYPE_OCMB_CHIP); + if (ocmb_target_list.size() == 0) + { + TS_INFO("testExplrMMIO> No OCMB targets found. Exiting."); + break; + } + explr_target = ocmb_target_list[0]; + if(explr_target->getAttr<ATTR_CHIP_ID>() != + POWER_CHIPID::EXPLORER_16) + { + TS_INFO("testExplrMMIO> No explorer targets found. Exiting."); + break; + } + + // Make sure we're using MMIO to this explorer chip + exptest::enableInbandScomsOcmb(explr_target); + + // valid read from config space register + op_size = sizeof(regdata4); + l_err = DeviceFW::deviceRead( + explr_target, + ®data4, + op_size, + DEVICE_MMIO_ADDRESS( + CNFG2MMIO_ADDR(EXPLR_OC_O0MBIT_O0DID_LSB), + op_size)); + + if(l_err != nullptr) + { + errlCommit(l_err, CXXTEST_COMP_ID); + TS_FAIL("testExplrMMIO> Error for config read, RC=0x%04X", + ERRL_GETRC_SAFE(l_err)); + } + + // valid write to config space register + op_size = sizeof(regdata4); + l_err = DeviceFW::deviceWrite( + explr_target, + ®data4, + op_size, + DEVICE_MMIO_ADDRESS( + CNFG2MMIO_ADDR(EXPLR_OC_O0CCD_LSB), + op_size)); + if(l_err != nullptr) + { + errlCommit(l_err, CXXTEST_COMP_ID); + TS_FAIL("testExplrMMIO> Error for config write, RC=0x%04X", + ERRL_GETRC_SAFE(l_err)); + } + + // 1st valid write to SCOM register (also sets up + // tests for forcing HW read/write failures) + // Set the PCB error bits (8:10) to binary 100, which means + // 'invalid address' + // NOTE: must byteswap to little endian before writing + uint64_t GIF2PCB_INVALID_SCOM_ADDR_ERROR = 0x0080000000000000ull; + l_buffer64 = BYTESWAP64(GIF2PCB_INVALID_SCOM_ADDR_ERROR); + op_size = sizeof(l_buffer64); + l_err = DeviceFW::deviceWrite( + explr_target, + &l_buffer64, + op_size, + DEVICE_MMIO_ADDRESS( + SCOM2MMIO_ADDR( + EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG), + op_size)); + + if(l_err != nullptr) + { + errlCommit(l_err, CXXTEST_COMP_ID); + TS_FAIL("testExplrMMIO> Error for gif2pcb write, RC=0x%04X", + ERRL_GETRC_SAFE(l_err)); + break; + } + + // 2nd valid write to SCOM register (also sets up + // tests for forcing HW read/write failures) + // This register should contain a copy of the GIF2PCB error register + // starting at bit 32 + // NOTE: must byteswap to little endian before writing data + uint64_t PIB2GIF_INVALID_SCOM_ADDR_ERROR = + 0x0000000000000000ull | + ((GIF2PCB_INVALID_SCOM_ADDR_ERROR & + 0xffffc00000000000ull) >> 32); + l_buffer64 = BYTESWAP64(PIB2GIF_INVALID_SCOM_ADDR_ERROR); + op_size = sizeof(l_buffer64); + l_err = DeviceFW::deviceWrite( + explr_target, + &l_buffer64, + op_size, + DEVICE_MMIO_ADDRESS( + SCOM2MMIO_ADDR( + EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG), + op_size)); + + if(l_err != nullptr) + { + errlCommit(l_err, CXXTEST_COMP_ID); + TS_FAIL("testExplrMMIO> Error for pib2gif write, RC=0x%04X", + ERRL_GETRC_SAFE(l_err)); + break; + } + + // Write to an "invalid" scom address. Should + // return with failure (now that we've set up the error regs). + // NOTE: Also, writing MMIO_OCMB_UE_DETECTED to this register + // sets up the following read to the same register + // to fail. + l_buffer64 = MMIO_OCMB_UE_DETECTED; + op_size = sizeof(l_buffer64); + l_err = DeviceFW::deviceWrite( + explr_target, + &l_buffer64, + op_size, + DEVICE_MMIO_ADDRESS( + SCOM2MMIO_ADDR(EXPLR_INVALID_SCOM_ADDR), + op_size)); + if(l_err == nullptr) + { + ScomSwitches l_switches = + explr_target->getAttr<ATTR_SCOM_SWITCHES>(); + TS_INFO("testExplrMMIO: Current SCOM mode: %s", + (l_switches.useInbandScom)? "MMIO": "I2C"); + TS_FAIL("testExplrMMIO> " + "did not recieve expected failure on mmio write"); + break; + } + else + { + TS_INFO("testExplrMMIO> " + "received expected failure on mmio write"); + errlCommit(l_err, CXXTEST_COMP_ID); + } + + // Re-enable inband scoms after failure disables it + exptest::enableInbandScomsOcmb(explr_target); + + // Read from an "invalid" scom address. Should + // return with failure (now that we've set up the error regs). + op_size = sizeof(l_buffer64); + l_err = DeviceFW::deviceRead( + explr_target, + &l_buffer64, + op_size, + DEVICE_MMIO_ADDRESS( + SCOM2MMIO_ADDR(EXPLR_INVALID_SCOM_ADDR), + op_size)); + + if(l_err == nullptr) + { + ScomSwitches l_switches = + explr_target->getAttr<ATTR_SCOM_SWITCHES>(); + TS_INFO("testExplrMMIO> " + "data read from invalid address: 0x%016llx", + l_buffer64); + TS_INFO("testExplrMMIO: Current SCOM mode: %s", + (l_switches.useInbandScom)? "MMIO": "I2C"); + TS_FAIL("testExplrMMIO> " + "did not recieve expected failure on mmio read"); + } + else + { + TS_INFO("testExplrMMIO> " + "received expected failure on mmio read"); + errlCommit(l_err, CXXTEST_COMP_ID); + } + + } while (0); + + // Re-enable inband scoms after failure disables it + if(explr_target != nullptr) { - TRACFCOMP(g_trac_mmio, - "MmioTest::test_Valid> Error for write, RC=0x%04X", - ERRL_GETRC_SAFE(l_err)); - TS_FAIL("MmioTest::test_Valid> Error for write, RC=0x%04X", - ERRL_GETRC_SAFE(l_err)); - ++fails; - errlCommit(l_err, MMIO_COMP_ID); + exptest::enableInbandScomsOcmb(explr_target); } -#endif - TRACFCOMP(g_trac_mmio, "Mmio::test_Valid> %d/%d fails", fails, total); + // << atomic section + mutex_unlock(l_mutex); + TS_INFO("testExplrMMIO> Done"); }; }; diff --git a/src/usr/pnor/ast_mboxdd.C b/src/usr/pnor/ast_mboxdd.C index 5b6e58300..9a7c45e9b 100644 --- a/src/usr/pnor/ast_mboxdd.C +++ b/src/usr/pnor/ast_mboxdd.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2018 */ +/* Contributors Listed Below - COPYRIGHT 2011,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -51,7 +51,6 @@ #include <initservice/initserviceif.H> #include <util/align.H> #include <lpc/lpcif.H> -#include <config.h> // Initialized in pnorrp.C extern trace_desc_t* g_trac_pnor; diff --git a/src/usr/pnor/ast_mboxdd.H b/src/usr/pnor/ast_mboxdd.H index 2d1aa48ad..44c745cab 100644 --- a/src/usr/pnor/ast_mboxdd.H +++ b/src/usr/pnor/ast_mboxdd.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2017 */ +/* Contributors Listed Below - COPYRIGHT 2011,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -26,7 +26,6 @@ #define __AST_MBOXDD_H #include <limits.h> -#include <config.h> /** @file ast_mboxdd.H * @brief Provides the interfaces Aspeed MBOX hardware diff --git a/src/usr/pnor/norflash.H b/src/usr/pnor/norflash.H index 29ac2f8f0..e7e61f389 100644 --- a/src/usr/pnor/norflash.H +++ b/src/usr/pnor/norflash.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014,2016 */ +/* Contributors Listed Below - COPYRIGHT 2014,2019 */ /* [+] Google Inc. */ /* [+] International Business Machines Corp. */ /* */ @@ -25,7 +25,6 @@ /* IBM_PROLOG_END_TAG */ #ifndef __PNOR_NORFLASH_H #define __PNOR_NORFLASH_H -#include <config.h> #include <errl/errlentry.H> class SfcDD; diff --git a/src/usr/pnor/pnor_common.C b/src/usr/pnor/pnor_common.C index 3b642a6e6..41f17ff7e 100644 --- a/src/usr/pnor/pnor_common.C +++ b/src/usr/pnor/pnor_common.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014,2018 */ +/* Contributors Listed Below - COPYRIGHT 2014,2019 */ /* [+] Google Inc. */ /* [+] International Business Machines Corp. */ /* */ @@ -34,7 +34,6 @@ #include <initservice/initserviceif.H> #include <util/align.H> #include <errl/errlmanager.H> -#include <config.h> // @FIXME RTC 132398 #include <secureboot/trustedbootif.H> #include <devicefw/driverif.H> @@ -144,12 +143,16 @@ errlHndl_t PNOR::parseTOC( uint8_t* i_tocBuffer,SectionData_t * o_TOC, // Zero out my table PNOR::initializeSections(o_TOC); - uint32_t l_errCode = 0; - ffs_hdr* l_ffs_hdr = NULL; + uint32_t l_errCode(0); + ffs_hdr* l_ffs_hdr(reinterpret_cast<ffs_hdr*>(i_tocBuffer)); TRACDCOMP(g_trac_pnor, "PNOR::parseTOC verifying TOC"); + if (!l_ffs_hdr) + { + l_errCode = PNOR::BUFF_IS_NULL; + l_ffs_hdr = nullptr; + } - PNOR::checkForNullBuffer(i_tocBuffer, l_errCode, l_ffs_hdr); //Check if the buffer is null if(l_errCode != NO_ERROR) { @@ -160,16 +163,16 @@ errlHndl_t PNOR::parseTOC( uint8_t* i_tocBuffer,SectionData_t * o_TOC, "Null TOC Buffer found while checking TOC" " during pnor initialization"); /*@ - * @errortype - * @moduleid PNOR::MOD_PNORRP_READTOC - * @reasoncode PNOR::RC_NULL_TOC_BUFFER - * @userdata1 Address of toc buffer - * @userdata2 Error code - * @devdesc Expected buffer to have contents of TOC, - * instead was NULL - * @custdesc A problem occurred while reading - * Processor NOR flash partition table - */ + * @errortype + * @moduleid PNOR::MOD_PNORRP_READTOC + * @reasoncode PNOR::RC_NULL_TOC_BUFFER + * @userdata1 Address of toc buffer + * @userdata2 Error code + * @devdesc Expected buffer to have contents of TOC, + * instead was NULL + * @custdesc A problem occurred while reading + * Processor NOR flash partition table + */ l_errhdl = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_UNRECOVERABLE, PNOR::MOD_PNORRP_READTOC, @@ -197,15 +200,16 @@ errlHndl_t PNOR::parseTOC( uint8_t* i_tocBuffer,SectionData_t * o_TOC, "PNOR::parseTOC Found checksum error in TOC's header" " during pnor initialization"); - /* @errortype - * @moduleid PNOR::MOD_PNORRP_READTOC - * @reasoncode PNOR::RC_TOC_HDR_CHECKSUM_ERR - * @userdata1 Address of toc buffer - * @userdata2 Error Code - * @devdesc Hdr of TOC of PNOR failed checksum - * @custdesc A problem occurred while reading - * Processor NOR flash partition table - */ + /*@ + * @errortype + * @moduleid PNOR::MOD_PNORRP_READTOC + * @reasoncode PNOR::RC_TOC_HDR_CHECKSUM_ERR + * @userdata1 Address of toc buffer + * @userdata2 Error Code + * @devdesc Hdr of TOC of PNOR failed checksum + * @custdesc A problem occurred while reading + * Processor NOR flash partition table + */ l_errhdl = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_UNRECOVERABLE, PNOR::MOD_PNORRP_READTOC, @@ -230,15 +234,16 @@ errlHndl_t PNOR::parseTOC( uint8_t* i_tocBuffer,SectionData_t * o_TOC, assert(i_pnorInitialized, "PNOR::parseTOC Error found parsing hdr of TOC" " during pnor initialization"); - /* @errortype - * @moduleid PNOR::MOD_PNORRP_READTOC - * @reasoncode PNOR::RC_BAD_TOC_HEADER - * @userdata1 Address of toc buffer - * @userdata2 Error Code - * @devdesc Hdr of TOC of PNOR failed series of tests - * @custdesc A problem occurred while reading - * Processor NOR flash partition table - */ + /*@ + * @errortype + * @moduleid PNOR::MOD_PNORRP_READTOC + * @reasoncode PNOR::RC_BAD_TOC_HEADER + * @userdata1 Address of toc buffer + * @userdata2 Error Code + * @devdesc Hdr of TOC of PNOR failed series of tests + * @custdesc A problem occurred while reading + * Processor NOR flash partition table + */ l_errhdl = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_UNRECOVERABLE, PNOR::MOD_PNORRP_READTOC, @@ -276,15 +281,16 @@ errlHndl_t PNOR::parseTOC( uint8_t* i_tocBuffer,SectionData_t * o_TOC, "PNOR::parseTOC parseEntries returned an error code" " during pnor initialization"); - /* @errortype - * @moduleid PNOR::MOD_PNORRP_READTOC - * @reasoncode PNOR::RC_PNOR_PARSE_ENTRIES_ERR - * @userdata1 Address of toc buffer - * @userdata2 Error Code - * @devdesc Error while parsing pnor TOC entries - * @custdesc A problem occurred while reading - * Processor NOR flash partition table - */ + /*@ + * @errortype + * @moduleid PNOR::MOD_PNORRP_READTOC + * @reasoncode PNOR::RC_PNOR_PARSE_ENTRIES_ERR + * @userdata1 Address of toc buffer + * @userdata2 Error Code + * @devdesc Error while parsing pnor TOC entries + * @custdesc A problem occurred while reading + * Processor NOR flash partition table + */ l_errhdl = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_UNRECOVERABLE, PNOR::MOD_PNORRP_READTOC, diff --git a/src/usr/pnor/pnor_ipmidd.C b/src/usr/pnor/pnor_ipmidd.C index 078195dad..43df5adfe 100644 --- a/src/usr/pnor/pnor_ipmidd.C +++ b/src/usr/pnor/pnor_ipmidd.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -58,7 +58,6 @@ #include <initservice/initserviceif.H> #include <util/align.H> #include <lpc/lpcif.H> -#include <config.h> #include "sfcdd.H" #include <ipmi/ipmiif.H> diff --git a/src/usr/pnor/pnor_ipmidd.H b/src/usr/pnor/pnor_ipmidd.H index fc843db6a..5c99607fe 100644 --- a/src/usr/pnor/pnor_ipmidd.H +++ b/src/usr/pnor/pnor_ipmidd.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -31,7 +31,6 @@ */ #include <limits.h> -#include <config.h> #include "pnorif.H" diff --git a/src/usr/pnor/pnor_mboxdd.C b/src/usr/pnor/pnor_mboxdd.C index a156ffb8f..92819143d 100644 --- a/src/usr/pnor/pnor_mboxdd.C +++ b/src/usr/pnor/pnor_mboxdd.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2018 */ +/* Contributors Listed Below - COPYRIGHT 2011,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -54,7 +54,6 @@ #include <initservice/initserviceif.H> #include <util/align.H> #include <lpc/lpcif.H> -#include <config.h> #include "sfcdd.H" // Initialized in pnorrp.C diff --git a/src/usr/pnor/pnor_mboxdd.H b/src/usr/pnor/pnor_mboxdd.H index 16105efe2..6095dce35 100644 --- a/src/usr/pnor/pnor_mboxdd.H +++ b/src/usr/pnor/pnor_mboxdd.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2018 */ +/* Contributors Listed Below - COPYRIGHT 2011,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -26,7 +26,6 @@ #define __PNOR_MBOXDD_H #include <limits.h> -#include <config.h> #include "pnorif.H" namespace PNOR diff --git a/src/usr/pnor/pnor_sfcdd.C b/src/usr/pnor/pnor_sfcdd.C index fe3f0cbae..9acea977b 100644 --- a/src/usr/pnor/pnor_sfcdd.C +++ b/src/usr/pnor/pnor_sfcdd.C @@ -53,7 +53,6 @@ #include <initservice/initserviceif.H> #include <util/align.H> #include <lpc/lpcif.H> -#include <config.h> #include "sfcdd.H" /*****************************************************************************/ @@ -251,7 +250,7 @@ errlHndl_t PnorSfcDD::writeFlash(void* i_buffer, size_t& io_buflen, uint64_t i_address) { - TRACFCOMP(g_trac_pnor, ENTER_MRK"PnorSfcDD::writeFlash(i_address=0x%llx)> ", i_address); + TRACDCOMP(g_trac_pnor, ENTER_MRK"PnorSfcDD::writeFlash(i_address=0x%llx)> ", i_address); errlHndl_t l_err = NULL; do{ @@ -339,7 +338,7 @@ errlHndl_t PnorSfcDD::writeFlash(void* i_buffer, { io_buflen = 0; } - TRACFCOMP(g_trac_pnor,EXIT_MRK"PnorSfcDD::writeFlash(i_address=0x%llx)> io_buflen=%.8X", i_address, io_buflen); + TRACDCOMP(g_trac_pnor,EXIT_MRK"PnorSfcDD::writeFlash(i_address=0x%llx)> io_buflen=%.8X", i_address, io_buflen); return l_err; } diff --git a/src/usr/pnor/pnor_sfcdd.H b/src/usr/pnor/pnor_sfcdd.H index bfd3140a7..ba7f0aa0d 100644 --- a/src/usr/pnor/pnor_sfcdd.H +++ b/src/usr/pnor/pnor_sfcdd.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2018 */ +/* Contributors Listed Below - COPYRIGHT 2011,2019 */ /* [+] Google Inc. */ /* [+] International Business Machines Corp. */ /* */ @@ -27,7 +27,6 @@ #define __PNOR_PNORDD_H #include <limits.h> -#include <config.h> #include <pnor/pnor_const.H> namespace PNOR { class UdPnorDDParms; } diff --git a/src/usr/pnor/pnor_utils.C b/src/usr/pnor/pnor_utils.C index cd7c9f98f..83ff90450 100644 --- a/src/usr/pnor/pnor_utils.C +++ b/src/usr/pnor/pnor_utils.C @@ -53,7 +53,6 @@ extern trace_desc_t* g_trac_pnor; #include "common/ffs_hb.H" #include <util/align.H> -#include <config.h> #include <securerom/ROM.H> #include <pnor/pnorif.H> @@ -110,30 +109,6 @@ void PNOR::initializeSections(PNOR::SectionData_t io_toc[NUM_SECTIONS]) } } - - -/** - * @brief Ensure the buffer is not NULL, if it is, then return - * the appropriate err code from the o_errCode param. - * if the buffer is not NULL then cast it to a ffs_hdr - * and return that out through the respective o_param - */ -void PNOR::checkForNullBuffer(uint8_t* i_tocBuffer, - uint32_t& o_errCode, - ffs_hdr*& o_ffs_hdr) -{ - if(!i_tocBuffer) - { - o_errCode |= BUFF_IS_NULL; - o_ffs_hdr = NULL; - } - else - { - o_ffs_hdr = (ffs_hdr*)i_tocBuffer; - } -} - - /** * @brief Perform a series of checks on the header of the table of contents * These checks include: looking for valid magic #, valid block size, @@ -369,6 +344,7 @@ bool PNOR::isEnforcedSecureSection(const uint32_t i_section) i_section == HB_DATA || i_section == SBE_IPL || i_section == PAYLOAD || + i_section == BOOTKERNEL || i_section == SBKT || i_section == OCC || i_section == HCODE || @@ -378,7 +354,8 @@ bool PNOR::isEnforcedSecureSection(const uint32_t i_section) i_section == MEMD || i_section == CAPP || i_section == TESTLOAD || - i_section == VERSION; + i_section == VERSION || + i_section == OCMBFW; #endif #else return false; @@ -415,7 +392,6 @@ const char * PNOR::SectionIdToString( uint32_t i_secIdIndex ) "part", /**< PNOR::TOC : Table of Contents */ #ifndef BOOTLOADER "HBI", /**< PNOR::HB_EXT_CODE : Hostboot Extended Image */ - "GLOBAL", /**< PNOR::GLOBAL_DATA : Global Data */ #endif "HBB", /**< PNOR::HB_BASE_CODE : Hostboot Base Image */ #ifndef BOOTLOADER @@ -451,6 +427,7 @@ const char * PNOR::SectionIdToString( uint32_t i_secIdIndex ) "HDAT", /**< PNOR::HDAT : Hdat Data */ "EECACHE", /**< PNOR::EECACHE : Cached data from various EEPROMs */ "OCMBFW", /**< PNOR::OCMBFW : OCMB image */ + "BOOTKERNEL", /**< PNOR::BOOTKERNEL : OPAL == petitboot,PHYP == PowerVM */ #endif }; diff --git a/src/usr/pnor/pnor_utils.H b/src/usr/pnor/pnor_utils.H index 53a402f97..d529c8c6c 100644 --- a/src/usr/pnor/pnor_utils.H +++ b/src/usr/pnor/pnor_utils.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2018 */ +/* Contributors Listed Below - COPYRIGHT 2011,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -29,7 +29,6 @@ #include <pnor/pnor_const.H> #include "limits.h" #include "ffs.h" -#include <config.h> #ifndef BOOTLOADER #include <errl/errlentry.H> diff --git a/src/usr/pnor/pnorrp.C b/src/usr/pnor/pnorrp.C index af6ccf3fa..fa35be627 100644 --- a/src/usr/pnor/pnorrp.C +++ b/src/usr/pnor/pnorrp.C @@ -44,7 +44,6 @@ #include <kernel/console.H> #include <endian.h> #include <util/align.H> -#include <config.h> #include <pnor/pnorif.H> #include "pnor_common.H" #include <hwas/common/hwasCallout.H> @@ -214,6 +213,13 @@ void PnorRP::init( errlHndl_t &io_rtaskRetErrl ) #ifdef CONFIG_SECUREBOOT // Extend the base image to the TPM, regardless of how it was obtained l_errl = TRUSTEDBOOT::extendBaseImage(); + + // Cache the VERSION partition data for future use by the errl commit + // code. + if(!l_errl) + { + l_errl = ERRORLOG::cacheVersionPartition(); + } #endif #endif } @@ -522,6 +528,7 @@ errlHndl_t PnorRP::getSectionInfo( PNOR::SectionId i_section, #ifdef CONFIG_SECUREBOOT o_info.secure = iv_TOC[id].secure; + o_info.size = iv_TOC[id].size; o_info.secureProtectedPayloadSize = 0; // for non secure sections // the protected payload size // defaults to zero @@ -591,6 +598,17 @@ errlHndl_t PnorRP::getSectionInfo( PNOR::SectionId i_section, // was done previously in pnor_common.C o_info.size -= PAGESIZE; + // Need to change size to accommodate for hash table + if (l_conHdr.sb_flags()->sw_hash) + { + o_info.vaddr += payloadTextSize; + // Hash page table needs to use containerSize as the base + // and subtract off header and hash table size + o_info.size = l_conHdr.totalContainerSize() - PAGE_SIZE - + payloadTextSize; + o_info.hasHashTable = true; + } + // cache the value in SectionInfo struct so that we can // parse the container header less often o_info.secureProtectedPayloadSize = payloadTextSize; @@ -598,11 +616,11 @@ errlHndl_t PnorRP::getSectionInfo( PNOR::SectionId i_section, else #endif { + o_info.size = iv_TOC[id].size; o_info.vaddr = iv_TOC[id].virtAddr; } o_info.flashAddr = iv_TOC[id].flashAddr; - o_info.size = iv_TOC[id].size; o_info.eccProtected = ((iv_TOC[id].integrity & FFS_INTEG_ECC_PROTECT) != 0) ? true : false; o_info.sha512Version = ((iv_TOC[id].version & FFS_VERS_SHA512) diff --git a/src/usr/pnor/pnorrp.H b/src/usr/pnor/pnorrp.H index 1fe3c088c..650b62126 100644 --- a/src/usr/pnor/pnorrp.H +++ b/src/usr/pnor/pnorrp.H @@ -34,7 +34,6 @@ #include <map> #include "pnor_common.H" #include "ffs.h" -#include <config.h> #include "pnor_utils.H" /** diff --git a/src/usr/pnor/runtime/rt_pnor.C b/src/usr/pnor/runtime/rt_pnor.C index f3e969f2e..0d40a60c3 100644 --- a/src/usr/pnor/runtime/rt_pnor.C +++ b/src/usr/pnor/runtime/rt_pnor.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014,2018 */ +/* Contributors Listed Below - COPYRIGHT 2014,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -29,7 +29,7 @@ #include <initservice/taskargs.H> #include <initservice/initserviceif.H> -#include <runtime/rt_targeting.H> +#include <targeting/runtime/rt_targeting.H> #include <runtime/interface.h> // g_hostInterfaces, postInitCalls_t #include <pnor/pnorif.H> @@ -42,7 +42,6 @@ #include <util/align.H> #include <runtime/customize_attrs_for_payload.H> #include <securerom/ROM.H> -#include <config.h> #include "../pnor_utils.H" #include <runtime/common/runtime_utils.H> @@ -924,7 +923,7 @@ errlHndl_t RtPnor::getMasterProcId() TRACFCOMP(g_trac_pnor, "RtPnor::getMasterProcId: queryMasterProcChipTargetHandle failed"); break; } - l_err = RT_TARG::getRtTarget(l_masterProc, iv_masterProcId); + l_err = TARGETING::getRtTarget(l_masterProc, iv_masterProcId); if (l_err) { TRACFCOMP(g_trac_pnor, "RtPnor::getMasterProcId: getRtTarget failed for master proc"); diff --git a/src/usr/pnor/sfc_ast2400.H b/src/usr/pnor/sfc_ast2400.H index c83db94c0..937435332 100644 --- a/src/usr/pnor/sfc_ast2400.H +++ b/src/usr/pnor/sfc_ast2400.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014,2016 */ +/* Contributors Listed Below - COPYRIGHT 2014,2019 */ /* [+] Google Inc. */ /* [+] International Business Machines Corp. */ /* */ @@ -31,7 +31,6 @@ #include <errl/errlentry.H> #include "sfcdd.H" #include "sfc_ast2X00.H" -#include <config.h> /** @file sfc_ast2400.H * @brief Provides the logic to access and configure the diff --git a/src/usr/pnor/sfc_ast2500.H b/src/usr/pnor/sfc_ast2500.H index 73f07c58a..83607a5b9 100644 --- a/src/usr/pnor/sfc_ast2500.H +++ b/src/usr/pnor/sfc_ast2500.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -30,7 +30,6 @@ #include <errl/errlentry.H> #include "sfcdd.H" #include "sfc_ast2X00.H" -#include <config.h> /** @file sfc_ast2500.H * @brief Provides the logic to access and configure the diff --git a/src/usr/pnor/sfc_ast2X00.H b/src/usr/pnor/sfc_ast2X00.H index 2847b75d3..aceed1c30 100644 --- a/src/usr/pnor/sfc_ast2X00.H +++ b/src/usr/pnor/sfc_ast2X00.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -29,7 +29,6 @@ #include <targeting/common/targetservice.H> #include <errl/errlentry.H> #include "sfcdd.H" -#include <config.h> /** @file sfc_ast2X00.H * @brief Provides the base logic to access and configure the diff --git a/src/usr/pnor/spnorrp.C b/src/usr/pnor/spnorrp.C index 5b1ef5b03..fe2998756 100644 --- a/src/usr/pnor/spnorrp.C +++ b/src/usr/pnor/spnorrp.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2018 */ +/* Contributors Listed Below - COPYRIGHT 2011,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -33,7 +33,6 @@ #include <sys/mm.h> #include <errno.h> #include <util/align.H> -#include <config.h> #include "pnor_common.H" #include <console/consoleif.H> #include <secureboot/service.H> @@ -41,6 +40,7 @@ #include <secureboot/trustedbootif.H> #include <secureboot/header.H> #include <sys/task.h> +#include <arch/ppc.H> extern trace_desc_t* g_trac_pnor; @@ -363,6 +363,15 @@ uint64_t SPnorRP::verifySections(SectionId i_id, PNOR::SectionIdToString(i_id)); } + // If hash table exists, need to adjust sizes + if (l_info.hasHashTable) + { + io_rec->hasHashTable = true; + l_info.vaddr -= l_info.secureProtectedPayloadSize; + l_info.size += l_info.secureProtectedPayloadSize; + io_rec->hashTableVaddr = l_info.vaddr; + } + l_info.vaddr -= PAGESIZE; // back up a page to expose the secure header l_info.size += PAGESIZE; // add a page to size to account for the header @@ -643,13 +652,23 @@ uint64_t SPnorRP::verifySections(SectionId i_id, SHA512_DIGEST_LENGTH); } - // set permissions on the secured pages to writable + // set permissions to be writable + // in the case of HPT this is the header + HPT + // in the case of no HPT this is the header + text region l_errhdl = setPermission(io_rec->secAddr, l_protectedSizeWithHdr, WRITABLE); - if(l_errhdl) + if (l_errhdl) { - TRACFCOMP(g_trac_pnor,"SPnorRP::verifySections set permissions " - "failed on text section"); + if (l_info.hasHashTable) + { + TRACFCOMP(g_trac_pnor, ERR_MRK"SPnorRP::verifySections set permissions " + "failed on header + hash page table"); + } + else + { + TRACFCOMP(g_trac_pnor, ERR_MRK"SPnorRP::verifySections set permissions " + "failed on header + text section"); + } break; } @@ -691,10 +710,18 @@ uint64_t SPnorRP::verifySections(SectionId i_id, break; } - - l_errhdl = setPermission(io_rec->secAddr + l_protectedSizeWithHdr, - unprotectedPayloadSize, - WRITABLE | WRITE_TRACKED); + if (l_info.hasHashTable) + { + l_errhdl = setPermission(io_rec->secAddr + l_protectedSizeWithHdr, + unprotectedPayloadSize, + READ_ONLY); + } + else + { + l_errhdl = setPermission(io_rec->secAddr + l_protectedSizeWithHdr, + unprotectedPayloadSize, + WRITABLE | WRITE_TRACKED); + } if(l_errhdl) { TRACFCOMP(g_trac_pnor,"SPnorRP::verifySections set permissions " @@ -704,8 +731,11 @@ uint64_t SPnorRP::verifySections(SectionId i_id, // Register the write tracked memory range to be flushed on // shutdown. - INITSERVICE::registerBlock(io_rec->secAddr + l_protectedSizeWithHdr, - unprotectedPayloadSize, SPNOR_PRIORITY); + if (!l_info.hasHashTable) + { + INITSERVICE::registerBlock(io_rec->secAddr + l_protectedSizeWithHdr, + unprotectedPayloadSize, SPNOR_PRIORITY); + } } else { @@ -738,6 +768,83 @@ uint64_t SPnorRP::verifySections(SectionId i_id, return l_rc; } +int64_t getHashPageTableIndex(const int64_t i_vaddr) +{ + return (i_vaddr / static_cast<int64_t>(PAGE_SIZE)) + 1; +} + + +PAGE_TABLE_ENTRY_t* getHashPageTableEntry(const int64_t i_vaddr, + const uint64_t i_hash_vaddr) +{ + int64_t l_index = getHashPageTableIndex(i_vaddr); + int64_t l_offset = l_index * HASH_PAGE_TABLE_ENTRY_SIZE; + + // l_offset is the offset for the start of the hash page table + // i_hash_vaddr is the vaddr for the start of the hash in SECURE + // subtract off DELTA of 3GB to get into TEMP space + return reinterpret_cast<PAGE_TABLE_ENTRY_t*>(l_offset + i_hash_vaddr - + VMM_VADDR_SPNOR_DELTA); +} + +errlHndl_t verify_page(const int64_t i_offset_vaddr, const uint64_t i_hash_vaddr, + const uint64_t i_hash_size) +{ + errlHndl_t l_errl = nullptr; + + // Get current hash page table entry in TEMP space + PAGE_TABLE_ENTRY_t* l_pageTableEntry = + getHashPageTableEntry(i_offset_vaddr, i_hash_vaddr); + + // Get previous hash page table entry in TEMP space + PAGE_TABLE_ENTRY_t* l_prevPageTableEntry = + getHashPageTableEntry(i_offset_vaddr - PAGE_SIZE, i_hash_vaddr); + + // Concatenate previous hash with current page data + std::vector< std::pair<void*,size_t> > l_blobs; + l_blobs.push_back(std::make_pair<void*,size_t>(l_prevPageTableEntry, + HASH_PAGE_TABLE_ENTRY_SIZE)); + + // To get to PNOR space, we have the address of the hash in SECURE space and + // we add hash table size to get passed the hash page table. Then we add + // i_offset_vaddr, the offset of the requested vaddr, to end up at the + // requested vaddr in SECURE space. Finally we subtract off 2 DELTAS of + // 3GB each to get to the requested vaddr in PNOR space + l_blobs.push_back(std::make_pair<void*,size_t>( + reinterpret_cast<void*>(i_offset_vaddr + + i_hash_vaddr + i_hash_size - + 2 * VMM_VADDR_SPNOR_DELTA), + PAGE_SIZE)); + SHA512_t l_curPageHash = {0}; + SECUREBOOT::hashConcatBlobs(l_blobs, l_curPageHash); + + // Compare existing hash page table entry with the derived one. + if (memcmp(l_pageTableEntry,l_curPageHash,HASH_PAGE_TABLE_ENTRY_SIZE) != 0) + { + TRACFCOMP(g_trac_pnor, "ERROR:>PNOR::verify_page secureboot verify fail on vaddr 0x%016llX", + i_hash_vaddr + i_hash_size + i_offset_vaddr); + /*@ + * @severity ERRL_SEV_CRITICAL_SYS_TERM + * @moduleid MOD_SPNORRP_VERIFY_PAGE + * @reasoncode RC_VERIFY_PAGE_FAILED + * @userdata1 Kernel RC + * @userdata2 Virtual address accessed + * + * @devdesc Secureboot page verify failure + * @custdesc Corrupted flash image or firmware error during system boot + */ + l_errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_CRITICAL_SYS_TERM, + MOD_SPNORRP_VERIFY_PAGE, + RC_VERIFY_PAGE_FAILED, + TO_UINT64(EACCES), + i_offset_vaddr, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + l_errl->collectTrace(PNOR_COMP_NAME); + l_errl->collectTrace(SECURE_COMP_NAME); + } + return l_errl; +} + /** @@ -769,6 +876,7 @@ void SPnorRP::waitForMessage() // data[0] = virtual address requested // data[1] = address to place contents + uint64_t requested_vaddr = message->data[0]; eff_addr = reinterpret_cast<uint8_t*>(message->data[0]); user_addr = reinterpret_cast<uint8_t*>(message->data[1]); @@ -819,10 +927,34 @@ void SPnorRP::waitForMessage() TRACDCOMP( g_trac_pnor, "SPnorRP::waitForMessage got a" " request to read from secure space - " "message : user_addr=%p, eff_addr=%p, msgtype=%d, " - "textSize=0x%.16llX secAddr0x%.16llX", user_addr, + "textSize=0x%.16llX secAddr=0x%.16llX", user_addr, eff_addr, message->type, l_rec.textSize, l_rec.secAddr); + // If record has an associated hash page table, then we + // want to verify the page with the hash table in temp + if (SECUREBOOT::enabled() && l_rec.hasHashTable) + { + // Pass in the offset of just the data + int64_t offset_vaddr = requested_vaddr - + l_rec.hashTableVaddr - l_rec.textSize; + + // There is no hash table entry when we try to + // verify the header + if (offset_vaddr >= 0) { + l_errhdl = verify_page(offset_vaddr, + l_rec.hashTableVaddr, + l_rec.textSize); + } + + if (l_errhdl) + { + SECUREBOOT::handleSecurebootFailure(l_errhdl, false, true); + status_rc = -EFAULT; + break; + } + } + // determine the source of the data depending on // whether it is part of the secure payload. // by the way, this if could be removed to make this @@ -843,8 +975,8 @@ void SPnorRP::waitForMessage() // if the page came from temp space then free up // the temp page now that we're done with it // NOTE: secAddr points to Secure Header - if (eff_addr < ( (l_rec.secAddr + PAGESIZE) + - l_rec.textSize)) + if (!l_rec.hasHashTable && (eff_addr < ( (l_rec.secAddr + PAGESIZE) + + l_rec.textSize))) { mm_remove_pages(RELEASE, eff_addr - delta, PAGESIZE); @@ -924,7 +1056,6 @@ void SPnorRP::waitForMessage() // cache the record to use fields later as hints l_rec = *l_record; - } while (0); } break; @@ -936,7 +1067,7 @@ void SPnorRP::waitForMessage() do { // Disallow unload of HBB, HBI and Targeting if (l_id == HB_BASE_CODE || - l_id == HB_EXT_CODE || + l_id == HB_EXT_CODE || l_id == HB_DATA) { TRACFCOMP( g_trac_pnor, ERR_MRK"SPnorRP::waitForMessage> Secure unload of HBB, HBI, and targeting is not allowed secId=%d", l_id); @@ -998,7 +1129,7 @@ void SPnorRP::waitForMessage() size_t l_sizeWithHdr = PAGESIZE + l_rec->textSize; // if the section has an unsecured portion - if (l_sizeWithHdr != l_rec->infoSize) + if (l_sizeWithHdr != l_rec->infoSize && !l_rec->hasHashTable) { TRACFCOMP( g_trac_pnor, ERR_MRK"SPnorRP::waitForMessage> Attempting to unload an unsupported section: 0x%X textsize+hdr: 0x%llX infosize: 0x%llX (the two sizes must be equal)", l_id, l_sizeWithHdr, l_rec->infoSize); /*@ @@ -1031,6 +1162,40 @@ void SPnorRP::waitForMessage() } TRACDCOMP(g_trac_pnor,"Completely unloading %s", PNOR::SectionIdToString(l_id)); + if (l_rec->hasHashTable) + { + // remove unprotected pages + l_errhdl = removePages(l_rec->secAddr + PAGE_SIZE + l_rec->textSize, + l_rec->infoSize - PAGE_SIZE - l_rec->textSize); + if (l_errhdl) + { + TRACFCOMP(g_trac_pnor, + ERR_MRK"SPnorRP::waitForMessage> " + "removePages failed for address " + "0x%11X of length 0x%11X", + l_rec->secAddr + PAGE_SIZE + l_rec->textSize, + l_rec->infoSize - PAGE_SIZE - l_rec->textSize); + status_rc = -EFAULT; + break; + } + + l_errhdl = setPermission(l_rec->secAddr + PAGE_SIZE + l_rec->textSize, + l_rec->infoSize - PAGE_SIZE - l_rec->textSize, + NO_ACCESS); + if (l_errhdl) + { + TRACFCOMP(g_trac_pnor, + ERR_MRK"SPnorRP::waitForMessage> " + "setPermission failed for address " + "0x%11X of length 0x%11X", + l_rec->secAddr + PAGE_SIZE + l_rec->textSize, + l_rec->infoSize - PAGE_SIZE - l_rec->textSize); + + status_rc = -EFAULT; + break; + } + } + l_errhdl = removePages(l_rec->secAddr, l_sizeWithHdr); if (l_errhdl) @@ -1039,21 +1204,21 @@ void SPnorRP::waitForMessage() ERR_MRK"SPnorRP::waitForMessage> " "removePages failed for address " "0x%llX of length 0x%llX", l_rec->secAddr, - l_sizeWithHdr); + l_sizeWithHdr); status_rc = -EFAULT; break; } l_errhdl = setPermission(l_rec->secAddr, - l_sizeWithHdr, - NO_ACCESS); + l_sizeWithHdr, + NO_ACCESS); if (l_errhdl) { TRACFCOMP( g_trac_pnor, ERR_MRK"SPnorRP::waitForMessage> " "setPermission failed for address " "0x%llX of length 0x%llX", l_rec->secAddr, - l_sizeWithHdr); + l_sizeWithHdr); status_rc = -EFAULT; break; @@ -1067,7 +1232,7 @@ void SPnorRP::waitForMessage() l_sizeWithHdr); if (l_errhdl) { - TRACFCOMP( g_trac_pnor, + TRACFCOMP(g_trac_pnor, ERR_MRK"SPnorRP::waitForMessage> " "removePages failed for address " "0x%llX of length 0x%llX", l_tempAddr, @@ -1083,16 +1248,15 @@ void SPnorRP::waitForMessage() l_sizeWithHdr); l_errhdl = setPermission(l_tempAddr, - l_sizeWithHdr, - NO_ACCESS); + l_sizeWithHdr, + NO_ACCESS); if (l_errhdl) { - TRACFCOMP( g_trac_pnor, + TRACFCOMP(g_trac_pnor, ERR_MRK"SPnorRP::waitForMessage> " "setPermission failed for address " "0x%llX of length 0x%llX", l_tempAddr, l_sizeWithHdr); - status_rc = -EFAULT; break; } diff --git a/src/usr/pnor/spnorrp.H b/src/usr/pnor/spnorrp.H index 11da539ef..daaa3ffb7 100644 --- a/src/usr/pnor/spnorrp.H +++ b/src/usr/pnor/spnorrp.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2017 */ +/* Contributors Listed Below - COPYRIGHT 2011,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -33,7 +33,6 @@ #include <map> #include "pnor_common.H" #include "ffs.h" -#include <config.h> #include <securerom/ROM.H> namespace SECUREBOOT @@ -113,13 +112,16 @@ class SPnorRP * Keep track of secured payload size and secure section addresses */ struct LoadRecord{ - uint8_t* secAddr; - size_t textSize; - size_t infoSize; + uint8_t* secAddr; // virtual address of the start of the record + uint64_t hashTableVaddr; // virtual address of the hash table (if it exists) + size_t textSize; // size of the protected payload, not including header + size_t infoSize; // size of the entire partition size_t refCount; + bool hasHashTable; // indicates if the record has a hash table + SHA512_t payloadTextHash; LoadRecord() - :secAddr(nullptr), textSize(0), infoSize(0), refCount(0) + :secAddr(nullptr), hashTableVaddr(0), textSize(0), infoSize(0), refCount(0), hasHashTable(false) { memset(&payloadTextHash[0], 0, SHA512_DIGEST_LENGTH); } diff --git a/src/usr/pnor/test/pnorrptest.H b/src/usr/pnor/test/pnorrptest.H index 9d9dd95c1..54ed5f1cc 100644 --- a/src/usr/pnor/test/pnorrptest.H +++ b/src/usr/pnor/test/pnorrptest.H @@ -42,7 +42,6 @@ #include <sys/task.h> #include <targeting/common/targetservice.H> #include <devicefw/userif.H> -#include <config.h> #include <pnor/ecc.H> #include "../pnorrp.H" #include "../pnor_common.H" @@ -90,11 +89,13 @@ class PnorRpTest : public CxxTest::TestSuite continue; } - if(( testSections[idx] == PNOR::DIMM_JEDEC_VPD ) && + if(( testSections[idx] == PNOR::DIMM_JEDEC_VPD || + testSections[idx] == PNOR::MODULE_VPD) && ( TARGETING::MODEL_AXONE == TARGETING::targetService().getProcessorModel() )) { - TRACFCOMP(g_trac_pnor, "PnorRpTest::test_sectionInfo> Skipping non-existent DIMM_JEDEC_VPD section for Axone"); + TRACFCOMP(g_trac_pnor, "PnorRpTest::test_sectionInfo> " + "Skipping non-existent MODULE_VPD and DIMM_JEDEC_VPD section for Axone"); continue; } diff --git a/src/usr/pnor/test/pnorutilsTest.H b/src/usr/pnor/test/pnorutilsTest.H index a2258c622..b273665c7 100644 --- a/src/usr/pnor/test/pnorutilsTest.H +++ b/src/usr/pnor/test/pnorutilsTest.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014,2017 */ +/* Contributors Listed Below - COPYRIGHT 2014,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -62,7 +62,7 @@ class pnorutilsTest : public CxxTest::TestSuite l_tocBuffer[17] = 0x41; ffs_hdr* l_ffs_hdr = NULL; - PNOR::checkForNullBuffer(l_tocBuffer, l_errCode, l_ffs_hdr); + checkForNullBuffer(l_tocBuffer, l_errCode, l_ffs_hdr); PNOR::checkHeader(l_ffs_hdr, l_errCode); if((l_errCode & PNOR::INVALID_MAGIC) == PNOR::INVALID_MAGIC) @@ -92,7 +92,7 @@ class pnorutilsTest : public CxxTest::TestSuite l_tocBuffer[7] = 0x0; ffs_hdr* l_ffs_hdr = NULL; - PNOR::checkForNullBuffer(l_tocBuffer, l_errCode, l_ffs_hdr); + checkForNullBuffer(l_tocBuffer, l_errCode, l_ffs_hdr); PNOR::checkHeader(l_ffs_hdr, l_errCode); @@ -122,7 +122,7 @@ class pnorutilsTest : public CxxTest::TestSuite l_tocBuffer[31] = 0x80; ffs_hdr* l_ffs_hdr = NULL; - PNOR::checkForNullBuffer(l_tocBuffer, l_errCode, l_ffs_hdr); + checkForNullBuffer(l_tocBuffer, l_errCode, l_ffs_hdr); PNOR::checkHeader(l_ffs_hdr, l_errCode); @@ -153,7 +153,7 @@ class pnorutilsTest : public CxxTest::TestSuite l_tocBuffer[35] = 0x12; ffs_hdr* l_ffs_hdr = NULL; - PNOR::checkForNullBuffer(l_tocBuffer, l_errCode, l_ffs_hdr); + checkForNullBuffer(l_tocBuffer, l_errCode, l_ffs_hdr); PNOR::checkHeader(l_ffs_hdr, l_errCode); @@ -183,7 +183,7 @@ class pnorutilsTest : public CxxTest::TestSuite l_tocBuffer[38] = 0x10; ffs_hdr* l_ffs_hdr = NULL; - PNOR::checkForNullBuffer(l_tocBuffer, l_errCode, l_ffs_hdr); + checkForNullBuffer(l_tocBuffer, l_errCode, l_ffs_hdr); PNOR::checkHeader(l_ffs_hdr, l_errCode); @@ -213,7 +213,7 @@ class pnorutilsTest : public CxxTest::TestSuite l_tocBuffer[42] = 0x40; ffs_hdr* l_ffs_hdr = NULL; - PNOR::checkForNullBuffer(l_tocBuffer, l_errCode, l_ffs_hdr); + checkForNullBuffer(l_tocBuffer, l_errCode, l_ffs_hdr); PNOR::checkHeader(l_ffs_hdr, l_errCode); @@ -246,7 +246,7 @@ class pnorutilsTest : public CxxTest::TestSuite l_tocBuffer[39] = 0x33; ffs_hdr* l_ffs_hdr = NULL; - PNOR::checkForNullBuffer(l_tocBuffer, l_errCode, l_ffs_hdr); + checkForNullBuffer(l_tocBuffer, l_errCode, l_ffs_hdr); PNOR::checkHeader(l_ffs_hdr, l_errCode); @@ -276,7 +276,7 @@ class pnorutilsTest : public CxxTest::TestSuite l_tocBuffer[208] = 0xFF; PNOR::SectionData_t l_TOC[PNOR::NUM_SECTIONS]; ffs_hdr* l_ffs_hdr = NULL; - PNOR::checkForNullBuffer(l_tocBuffer, l_errCode, l_ffs_hdr); + checkForNullBuffer(l_tocBuffer, l_errCode, l_ffs_hdr); PNOR::checkHeader(l_ffs_hdr, l_errCode); //parse through the entries and check for any errors ffs_entry* l_err_entry = NULL; @@ -317,7 +317,7 @@ class pnorutilsTest : public CxxTest::TestSuite PNOR::SectionData_t l_TOC[PNOR::NUM_SECTIONS]; ffs_hdr* l_ffs_hdr = NULL; - PNOR::checkForNullBuffer(l_tocBuffer, l_errCode, l_ffs_hdr); + checkForNullBuffer(l_tocBuffer, l_errCode, l_ffs_hdr); PNOR::checkHeader(l_ffs_hdr, l_errCode); //parse through the entries and check for any errors ffs_entry* l_err_entry = NULL; @@ -336,6 +336,29 @@ class pnorutilsTest : public CxxTest::TestSuite TRACFCOMP(g_trac_pnor, "pnorutilsTest::test_entryExtendsBeyondFlash: complete, Failed = %d", l_failed); } + + private: + + /** + * @brief Ensure the buffer is not NULL, if it is, then return + * the appropriate err code from the o_errCode param. + * If the buffer is not NULL then cast it to a ffs_hdr + * and return that out through the o_ffs_hdr param. + */ + void checkForNullBuffer(uint8_t* i_tocBuffer, + uint32_t& o_errCode, + ffs_hdr*& o_ffs_hdr) + { + if(!i_tocBuffer) + { + o_errCode |= PNOR::BUFF_IS_NULL; + o_ffs_hdr = NULL; + } + else + { + o_ffs_hdr = reinterpret_cast<ffs_hdr*>(i_tocBuffer); + } + } }; #endif diff --git a/src/usr/runtime/customize_attrs_for_payload.C b/src/usr/runtime/customize_attrs_for_payload.C index 1846512b7..273596b12 100644 --- a/src/usr/runtime/customize_attrs_for_payload.C +++ b/src/usr/runtime/customize_attrs_for_payload.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2018 */ +/* Contributors Listed Below - COPYRIGHT 2012,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -36,10 +36,10 @@ #include <targeting/common/target.H> #include <targeting/common/targetservice.H> #include <targeting/common/utilFilter.H> +#include <targeting/runtime/rt_targeting.H> #include <runtime/runtime_reasoncodes.H> #include <runtime/runtime.H> #include <errl/errlmanager.H> -#include <runtime/rt_targeting.H> #include <arch/pirformat.H> #include <targeting/common/util.H> #include <errl/errludtarget.H> @@ -78,7 +78,8 @@ errlHndl_t createProcNotFoundError( * @reasoncode RUNTIME::RT_NO_PROC_TARGET * @userdata1 Input targeting target's HUID * @devdesc No processor targeting target was found for the given - * targeting target + * targeting target + * @custdesc Unexpected internal firmware error */ pError = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_INFORMATIONAL, @@ -86,7 +87,7 @@ errlHndl_t createProcNotFoundError( RUNTIME::RT_NO_PROC_TARGET, huid, 0, - true); + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); ERRORLOG::ErrlUserDetailsTarget(i_pTarget,"Targeting target"). addToLog(pError); @@ -109,7 +110,7 @@ errlHndl_t createProcNotFoundError( */ errlHndl_t computeNonPhypRtTarget( const TARGETING::Target* i_pTarget, - RT_TARG::rtChipId_t& o_rtTargetId) + TARGETING::rtChipId_t& o_rtTargetId) { assert(i_pTarget != NULL); @@ -165,6 +166,7 @@ errlHndl_t computeNonPhypRtTarget( * @userdata1 MEMBUF targeting target's HUID * @devdesc No associated DMI targeting target(s) found for * given MEMBUF targeting target + * @custdesc Unexpected internal firmware error */ pError = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_INFORMATIONAL, @@ -172,7 +174,7 @@ errlHndl_t computeNonPhypRtTarget( RUNTIME::RT_UNIT_TARGET_NOT_FOUND, huid, 0, - true); + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); ERRORLOG::ErrlUserDetailsTarget(i_pTarget,"Targeting Target"). addToLog(pError); @@ -229,6 +231,80 @@ errlHndl_t computeNonPhypRtTarget( o_rtTargetId = PIR_t::createCoreId(o_rtTargetId,pos); o_rtTargetId |= HBRT_CORE_TYPE; } + else if( targetingTargetType == TARGETING::TYPE_OCMB_CHIP) + { + // OCMB (This layout mimics MEMBUF) + // 0b1000.0000.0000.0000.0000.0GGG.GCCC.UUUU + // where GGGG is group, CCC is chip, UUUU is OMI chip unit + // + TARGETING::TargetHandleList targetList; + + getParentAffinityTargets(targetList, + i_pTarget, + TARGETING::CLASS_UNIT, + TARGETING::TYPE_OMI, + TARGETING::UTIL_FILTER_ALL); + + if( targetList.empty() ) + { + auto huid = get_huid(i_pTarget); + TRACFCOMP(g_trac_runtime, ERR_MRK + "No associated OMI targeting target(s) found for OCMB_CHIP " + "targeting target with HUID of 0x%08X", + huid); + /*@ + * @error + * @moduleid RUNTIME::MOD_CUST_COMP_NON_PHYP_RT_TARGET + * @reasoncode RUNTIME::RT_NO_OMI_TARGET_FOUND + * @userdata1 OCMB targeting target's HUID + * @devdesc No associated OMI targeting target(s) found for + * given OCMB targeting target + * @custdesc Unexpected internal firmware error + */ + pError = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_INFORMATIONAL, + RUNTIME::MOD_CUST_COMP_NON_PHYP_RT_TARGET, + RUNTIME::RT_NO_OMI_TARGET_FOUND, + huid, + 0, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + + ERRORLOG::ErrlUserDetailsTarget(i_pTarget,"Targeting Target"). + addToLog(pError); + + break; + } + + auto target = targetList[0]; + auto pos = target->getAttr<TARGETING::ATTR_CHIP_UNIT>(); + + targetList.clear(); + getParentAffinityTargets(targetList, + target, + TARGETING::CLASS_CHIP, + TARGETING::TYPE_PROC, + TARGETING::UTIL_FILTER_ALL); + + if(targetList.empty()) + { + pError = createProcNotFoundError(target); + break; + } + + auto procTarget = targetList[0]; + pError = computeNonPhypRtTarget(procTarget, o_rtTargetId); + if(pError) + { + break; + } + + // GGGG = 0 by default, CCC = o_rtTargetId, UUUU = pos + // HBRT_MEMBUF_TYPE distinguishes this target as a MEMBUF/OCMB + // Reusing MEMBUF for OCMB type as the two can't coexist + o_rtTargetId = (o_rtTargetId << RT_TARG::MEMBUF_ID_SHIFT); + o_rtTargetId += pos; // OMI chip unit acts as unique target position + o_rtTargetId |= HBRT_MEMBUF_TYPE; + } else { auto huid = get_huid(i_pTarget); @@ -246,6 +322,7 @@ errlHndl_t computeNonPhypRtTarget( * @userdata2 Targeting target's type * @devdesc The targeting type of the input targeting target is * not supported by runtime code + * @custdesc Unexpected internal firmware error */ pError = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_INFORMATIONAL, @@ -253,7 +330,7 @@ errlHndl_t computeNonPhypRtTarget( RUNTIME::RT_TARGET_TYPE_NOT_SUPPORTED, huid, targetingTargetType, - true); + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); ERRORLOG::ErrlUserDetailsTarget(i_pTarget,"Targeting Target"). addToLog(pError); @@ -277,7 +354,7 @@ errlHndl_t computeNonPhypRtTarget( */ errlHndl_t getRtTypeForTarget( const TARGETING::Target* i_pTarget, - RT_TARG::rtChipId_t& o_rtType) + TARGETING::rtChipId_t& o_rtType) { assert(i_pTarget != NULL); @@ -305,6 +382,10 @@ errlHndl_t getRtTypeForTarget( case TARGETING::TYPE_CORE: rtType = HBRT_CORE_TYPE; break; + case TARGETING::TYPE_OCMB_CHIP: + // reusing MEMBUF type as it is not present + rtType = HBRT_MEMBUF_TYPE; + break; default: found = false; break; @@ -325,6 +406,7 @@ errlHndl_t getRtTypeForTarget( * @userdata1 Target's HUID * @userdata2 Target's targeting type * @devdesc Targeting target's type not supported by runtime code + * @custdesc Unexpected internal firmware error */ pError = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_INFORMATIONAL, @@ -332,7 +414,7 @@ errlHndl_t getRtTypeForTarget( RUNTIME::RT_TARGET_TYPE_NOT_SUPPORTED, huid, targetingTargetType, - true); + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); ERRORLOG::ErrlUserDetailsTarget(i_pTarget,"Targeting Target"). addToLog(pError); @@ -355,13 +437,15 @@ errlHndl_t configureHbrtHypIds(const bool i_configForPhyp) TARGETING::CLASS_CHIP, TARGETING::TYPE_MEMBUF); TARGETING::PredicateCTM isaCore( TARGETING::CLASS_UNIT, TARGETING::TYPE_CORE); - TARGETING::PredicatePostfixExpr isaProcMembufOrCore; - isaProcMembufOrCore.push(&isaProc).push(&isaMembuf).Or() - .push(&isaCore).Or(); + TARGETING::PredicateCTM isanOcmbChip( + TARGETING::CLASS_CHIP, TARGETING::TYPE_OCMB_CHIP); + TARGETING::PredicatePostfixExpr isaProcMembufCoreorOcmb; + isaProcMembufCoreorOcmb.push(&isaProc).push(&isaMembuf).Or() + .push(&isaCore).Or().push(&isanOcmbChip).Or(); TARGETING::TargetRangeFilter pIt( TARGETING::targetService().begin(), TARGETING::targetService().end(), - &isaProcMembufOrCore); + &isaProcMembufCoreorOcmb); for (; pIt; ++pIt) { auto hbrtHypId = HBRT_HYP_ID_UNKNOWN; @@ -376,61 +460,128 @@ errlHndl_t configureHbrtHypIds(const bool i_configForPhyp) break; } - if( (*pIt)->getAttr<TARGETING::ATTR_TYPE>() - == TARGETING::TYPE_CORE) + switch ((*pIt)->getAttr<TARGETING::ATTR_TYPE>()) { - if(TARGETING::is_fused_mode()) + case TARGETING::TYPE_CORE: { - // If we're in fused core mode, all core ID's must - // match that of the parent EX - auto type = TARGETING::TYPE_EX; - const TARGETING::Target* pEx = - TARGETING::getParent(*pIt,type); - - // If this fails, everything is already hosed - assert(pEx != NULL); - - hbrtHypId = (pEx)->getAttr<TARGETING::ATTR_ORDINAL_ID>(); - }else + if(TARGETING::is_fused_mode()) + { + // If we're in fused core mode, all core ID's must + // match that of the parent EX + auto type = TARGETING::TYPE_EX; + const TARGETING::Target* pEx = + TARGETING::getParent(*pIt,type); + + // If this fails, everything is already hosed + assert(pEx != NULL); + + hbrtHypId = (pEx)->getAttr<TARGETING::ATTR_ORDINAL_ID>(); + } + else + { + hbrtHypId = (*pIt)->getAttr<TARGETING::ATTR_ORDINAL_ID>(); + } + break; + } + case TARGETING::TYPE_MEMBUF: + { + //MEMBUF + // 0b1000.0000.0000.0000.0000.0PPP.PPPP.MMMM + // where PP is the parent proc's id, MMMM is memory channel + // + TARGETING::TargetHandleList targetList; + + getParentAffinityTargets(targetList, + (*pIt), + TARGETING::CLASS_UNIT, + TARGETING::TYPE_DMI, false); + assert( !targetList.empty() ); + + auto dmi_target = targetList[0]; + auto pos = dmi_target->getAttr<TARGETING::ATTR_CHIP_UNIT>(); + + targetList.clear(); + getParentAffinityTargets(targetList, + dmi_target, + TARGETING::CLASS_CHIP, + TARGETING::TYPE_PROC, false); + assert( !targetList.empty() ); + + auto procTarget = targetList[0]; + hbrtHypId = procTarget->getAttr<TARGETING::ATTR_ORDINAL_ID>(); + hbrtHypId = (hbrtHypId << RT_TARG::MEMBUF_ID_SHIFT); + hbrtHypId += pos; + break; + } + case TARGETING::TYPE_OCMB_CHIP: + { + TRACDCOMP( g_trac_runtime, "configureHbrtHypIds> " + "Set ATTR_HBRT_HYP_ID attribute for OCMB target " + "with HUID of 0x%08X", TARGETING::get_huid(*pIt)); + + // TYPE_OCMB_CHIP (mimics MEMBUF layout) + // 0b1000.0000.0000.0000.0000.0PPP.PPPP.UUUU + // where PP is the parent proc's id, UUUU is OMI chip unit + // + TARGETING::TargetHandleList targetList; + + getParentAffinityTargets(targetList, + (*pIt), + TARGETING::CLASS_UNIT, + TARGETING::TYPE_OMI, false); + assert( !targetList.empty() ); + + auto omi_target = targetList[0]; + auto pos = omi_target->getAttr<TARGETING::ATTR_CHIP_UNIT>(); + + targetList.clear(); + getParentAffinityTargets(targetList, + omi_target, + TARGETING::CLASS_CHIP, + TARGETING::TYPE_PROC, false); + assert( !targetList.empty() ); + + auto procTarget = targetList[0]; + // Reusing MEMBUF for OCMB Chip communication + hbrtHypId = procTarget->getAttr<TARGETING::ATTR_ORDINAL_ID>(); + hbrtHypId = (hbrtHypId << RT_TARG::MEMBUF_ID_SHIFT); + hbrtHypId += pos; // Add OMI chip unit to end + break; + } + case TARGETING::TYPE_PROC: { hbrtHypId = (*pIt)->getAttr<TARGETING::ATTR_ORDINAL_ID>(); + break; } - } - else if( (*pIt)->getAttr<TARGETING::ATTR_TYPE>() - == TARGETING::TYPE_MEMBUF ) - { - //MEMBUF - // 0b1000.0000.0000.0000.0000.0PPP.PPPP.MMMM - // where PP is the parent proc's id, MMMM is memory channel - // - TARGETING::TargetHandleList targetList; - - getParentAffinityTargets(targetList, - (*pIt), - TARGETING::CLASS_UNIT, - TARGETING::TYPE_DMI, false); - assert( !targetList.empty() ); - - auto dmi_target = targetList[0]; - auto pos = dmi_target->getAttr<TARGETING::ATTR_CHIP_UNIT>(); - - targetList.clear(); - getParentAffinityTargets(targetList, - dmi_target, - TARGETING::CLASS_CHIP, - TARGETING::TYPE_PROC, false); - assert( !targetList.empty() ); - - auto procTarget = targetList[0]; - hbrtHypId = procTarget->getAttr<TARGETING::ATTR_ORDINAL_ID>(); - hbrtHypId = (hbrtHypId << RT_TARG::MEMBUF_ID_SHIFT); - hbrtHypId += pos; - } - else // just PROC - { - hbrtHypId = (*pIt)->getAttr<TARGETING::ATTR_ORDINAL_ID>(); - } - + default: + { + auto huid = get_huid(*pIt); + auto targetType = (*pIt)->getAttr<TARGETING::ATTR_TYPE>(); + TRACFCOMP(g_trac_runtime, ERR_MRK + "configureHbrtHypIds> 0x%08X is not a supported type. " + "HUID: 0x%08X", targetType, huid); + /*@ + * @errortype + * @moduleid RUNTIME::MOD_CONFIGURE_HBRT_HYP_IDS + * @reasoncode RUNTIME::RT_TARGET_TYPE_NOT_SUPPORTED + * @userdata1 Target's HUID + * @userdata2 Target's targeting type + * @devdesc Targeting target's type not supported by runtime code + * @custdesc Unexpected internal firmware error + */ + pError = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_INFORMATIONAL, + RUNTIME::MOD_CONFIGURE_HBRT_HYP_IDS, + RUNTIME::RT_TARGET_TYPE_NOT_SUPPORTED, + huid, + targetType, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + + ERRORLOG::ErrlUserDetailsTarget(*pIt,"Targeting Target"). + addToLog(pError); + break; + } + } // end of ATTR_TYPE switch hbrtHypId |= rtType; } else @@ -442,6 +593,12 @@ errlHndl_t configureHbrtHypIds(const bool i_configForPhyp) } } + // Only set HBRT_HYP_ID attribute if no error found + if (pError) + { + break; + } + (*pIt)->setAttr<TARGETING::ATTR_HBRT_HYP_ID>(hbrtHypId); TRACDCOMP( g_trac_runtime, "configureHbrtHypIds> " "Set ATTR_HBRT_HYP_ID attribute to 0x%016llX on targeting target " diff --git a/src/usr/runtime/hdatstructs.H b/src/usr/runtime/hdatstructs.H index 94f4c1b71..46cde05f7 100644 --- a/src/usr/runtime/hdatstructs.H +++ b/src/usr/runtime/hdatstructs.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2018 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -453,7 +453,10 @@ typedef struct sysSecSets // NOTE: This bit is labeled "Platform Security Overrides Allowed" // in the section 6.1.1 of HDAT spec. uint16_t sbeSecBackdoor : 1; - uint16_t reserved : 13; + + // bit 3: "System Physical Presence has been asserted" + uint16_t physicalPresenceAsserted : 1; + uint16_t reserved : 12; } SysSecSets; #endif diff --git a/src/usr/runtime/populate_hbruntime.C b/src/usr/runtime/populate_hbruntime.C index 371c3bee8..5ead63b3e 100644 --- a/src/usr/runtime/populate_hbruntime.C +++ b/src/usr/runtime/populate_hbruntime.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2019 */ +/* Contributors Listed Below - COPYRIGHT 2016,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -56,7 +56,6 @@ #include <secureboot/trustedbootif.H> #include <secureboot/service.H> #include <hdat/hdat.H> -#include <config.h> #include "../hdat/hdattpmdata.H" #include "../hdat/hdatpcrd.H" #include "../secureboot/trusted/tpmLogMgr.H" @@ -854,9 +853,18 @@ errlHndl_t fill_RsvMem_hbData(uint64_t & io_start_address, } #ifdef CONFIG_SECUREBOOT - memcpy(reinterpret_cast<uint8_t*>(l_prevDataAddr), - reinterpret_cast<uint8_t *>(l_memd_info.vaddr), - l_memd_info.secureProtectedPayloadSize); + if (l_memd_info.hasHashTable) + { + memcpy(reinterpret_cast<uint8_t*>(l_prevDataAddr), + reinterpret_cast<uint8_t *>(l_memd_info.vaddr), + l_memd_info.size); + } + else + { + memcpy(reinterpret_cast<uint8_t*>(l_prevDataAddr), + reinterpret_cast<uint8_t *>(l_memd_info.vaddr), + l_memd_info.secureProtectedPayloadSize); + } #else memcpy(reinterpret_cast<uint8_t*>(l_prevDataAddr), reinterpret_cast<uint8_t *>(l_memd_info.vaddr), @@ -905,10 +913,15 @@ errlHndl_t fill_RsvMem_hbData(uint64_t & io_start_address, l_elog->collectTrace(RUNTIME_COMP_NAME); break; } + // break out of for-loop if + if(l_elog) + { + break; + } i++; } - // exit if we hit an error + // break out of do-while if we hit an error if(l_elog) { break; @@ -1009,7 +1022,16 @@ errlHndl_t hbResvLoadSecureSection (const PNOR::SectionId i_sec, if (i_secHdrExpected) { // If section is signed, only the protected size was loaded into memory - l_imgSize = l_info.secureProtectedPayloadSize; + if (!l_info.hasHashTable) + { + l_imgSize = l_info.secureProtectedPayloadSize; + } + else + { + // Need to expose header and hash table + l_pnorVaddr -= l_info.secureProtectedPayloadSize; + l_imgSize += l_info.secureProtectedPayloadSize; + } // Include secure header // NOTE: we do not preserve the header in virtual memory when SB // is compiled out. So "-PAGESIZE" only works when SB is compiled in @@ -1257,51 +1279,10 @@ errlHndl_t populate_HbRsvMem(uint64_t i_nodeId, bool i_master_node) break; } - //////////////////////////////////////////////////////////////////// - // Set the Architected Reserve area in OPAL and pass it down to SBE - uint64_t l_memBase = l_topMemAddr - - VMM_ALL_HOMER_OCC_MEMORY_SIZE - - VMM_ARCH_REG_DATA_SIZE_ALL_PROC; - - l_elog = setNextHbRsvMemEntry(HDAT::RHB_TYPE_HBRT, - i_nodeId, - l_memBase, - VMM_ARCH_REG_DATA_SIZE_ALL_PROC, - HBRT_RSVD_MEM__ARCH_REG); - if(l_elog) - { - break; - } - // Loop through all functional Procs - for (const auto & l_procChip: l_procChips) - { - uint32_t l_procNum = - l_procChip->getAttr<TARGETING::ATTR_POSITION>(); - l_homerAddr = l_memBase + - (l_procNum * VMM_ARCH_REG_DATA_PER_PROC_SIZE); - - //Pass start address down to SBE via chipop - l_elog = SBEIO::sendPsuStashKeyAddrRequest( - SBEIO::ARCH_REG_DATA_ADDR, - l_homerAddr, - l_procChip); - if (l_elog) - { - TRACFCOMP( g_trac_runtime, "sendPsuStashKeyAddrRequest " - "failed for target: %x",TARGETING::get_huid(l_procChip)); - break; - } - } - - if(l_elog) - { - break; - } - //////////////////////////////////////////////////////////////////// - #ifdef CONFIG_START_OCC_DURING_BOOT /////////////////////////////////////////////////// // OCC Common entry + /////////////////////////////////////////////////// if( !(TARGETING::is_phyp_load()) ) { TARGETING::Target * l_sys = nullptr; @@ -1324,6 +1305,69 @@ errlHndl_t populate_HbRsvMem(uint64_t i_nodeId, bool i_master_node) #endif } + /////////////////////////////////////////////////// + // Set the SBE Architected Dump area + // Note that this is right after HOMER areas + // PHYP goes up, OPAL goes down. Save this away + // Into targeting so dumpCollect can find later + // on the MPIPL + // + // Note that this works for PHYP multinode (as it + // grabs location from HRMOR), but OPAL only + // supports a single node style system (absolute + // address) + ////////////////////////////////////////////////// + uint64_t l_archAddr = 0; + if(TARGETING::is_phyp_load()) + { + l_archAddr = cpu_spr_value(CPU_SPR_HRMOR) + + l_mirrorBase + + VMM_ARCH_REG_DATA_START_OFFSET; + } + else if(TARGETING::is_sapphire_load()) + { + l_archAddr = l_topMemAddr + - VMM_ALL_HOMER_OCC_MEMORY_SIZE + - VMM_ARCH_REG_DATA_SIZE_ALL_PROC; + } + l_sys->setAttr<TARGETING::ATTR_SBE_ARCH_DUMP_ADDR>(l_archAddr); + + // SBE Architected Dump area is a single chunk of data + // to OPAL/PHYP -- so reserve once, but need to inform + // individual SBEs of their location + l_elog = setNextHbRsvMemEntry(HDAT::RHB_TYPE_HBRT, + i_nodeId, + l_archAddr, + VMM_ARCH_REG_DATA_SIZE_ALL_PROC, + HBRT_RSVD_MEM__ARCH_REG); + if(l_elog) + { + break; + } + + // Loop through all functional Procs + uint32_t l_procNum = 0; + for (const auto & l_procChip: l_procChips) + { + uint64_t l_addr = l_archAddr + + (l_procNum++ * VMM_ARCH_REG_DATA_PER_PROC_SIZE); + + //Pass start address down to SBE via chipop + l_elog = SBEIO::sendPsuStashKeyAddrRequest( + SBEIO::ARCH_REG_DATA_ADDR, + l_addr, + l_procChip); + if (l_elog) + { + TRACFCOMP( g_trac_runtime, "Arch dump sendPsuStashKeyAddrRequest " + "failed for target: %x",TARGETING::get_huid(l_procChip)); + break; + } + } + if(l_elog) + { + break; + } //////////////////////////////////////////////////// // HB Data area @@ -1856,6 +1900,13 @@ errlHndl_t populate_hbSecurebootData ( void ) // populate security override setting l_sysSecSets->sbeSecBackdoor = SECUREBOOT::getSbeSecurityBackdoor(); + // populate "System Physical Presence has been asserted" + TARGETING::Target* sys = nullptr; + TARGETING::targetService().getTopLevelTarget( sys ); + assert(sys != nullptr, "populate_hbSecurebootData() - Could not obtain top level target"); + l_sysSecSets->physicalPresenceAsserted = + sys->getAttr<TARGETING::ATTR_PHYS_PRES_ASSERTED>(); + // populate TPM config bits in hdat bool tpmRequired = false; #ifdef CONFIG_TPMDD @@ -2863,6 +2914,12 @@ errlHndl_t populate_hbTpmInfo() // if single node system if (!hb_images) { + // TODO RTC: 214260 Remove workaround skipping the population + // of the TPM info for runtime on single node on Axone systems + #ifdef CONFIG_AXONE_BRING_UP + TRACFCOMP( g_trac_runtime, "SKIPPING populate_hbTpmInfo: Single node system"); + break; + #endif TRACDCOMP( g_trac_runtime, "populate_hbTpmInfo: Single node system"); l_elog = populate_TpmInfoByNode(0); // 0 for single node if(l_elog != nullptr) diff --git a/src/usr/runtime/test/makefile b/src/usr/runtime/test/makefile index ec316244f..fbba18a7d 100644 --- a/src/usr/runtime/test/makefile +++ b/src/usr/runtime/test/makefile @@ -24,7 +24,7 @@ # IBM_PROLOG_END_TAG ROOTPATH = ../../../.. MODULE = testruntime -TESTS += $(if $(or $(CONFIG_EARLY_TESTCASES),${CONFIG_AXONE_BRING_UP}) ,,testpreverifiedlidmgr.H) +TESTS += $(if $(CONFIG_EARLY_TESTCASES) ,,testpreverifiedlidmgr.H) TESTS += test_checkHbResMemLimit.H #@TODO RTC 132750 #TESTS += hdatservicetest.H diff --git a/src/usr/runtime/test/testpreverifiedlidmgr.H b/src/usr/runtime/test/testpreverifiedlidmgr.H index 7b47bf98f..955550c8b 100644 --- a/src/usr/runtime/test/testpreverifiedlidmgr.H +++ b/src/usr/runtime/test/testpreverifiedlidmgr.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -118,12 +118,12 @@ class PreVerifiedLidMgrTest : public CxxTest::TestSuite // RINGOVD not permitted in secure mode. Meaning the Header and // Content lid will be missing. l_expectedLids -= 2; - - // VERSION is only an OpenPOWER partition so we need to adjust for - // it here since it doesn't exist for standalone. - l_expectedLids -= 2; } + // VERSION is only an OpenPOWER partition so we need to adjust for + // it here since it doesn't exist for standalone. + l_expectedLids -= 2; + // Ensure the expected number of lids were loaded. if (l_preVerLidMgr.cv_lidsLoaded.size() != l_expectedLids) { diff --git a/src/usr/sbe/sbe_update.C b/src/usr/sbe/sbe_update.C index ef222e04d..ccbbe2480 100644 --- a/src/usr/sbe/sbe_update.C +++ b/src/usr/sbe/sbe_update.C @@ -52,7 +52,6 @@ #include <hwas/common/hwas.H> #include <initservice/initserviceif.H> #include <console/consoleif.H> -#include <config.h> #include <sbe/sbeif.H> #include <sbeio/sbeioif.H> #include <sbe/sbereasoncodes.H> @@ -1204,74 +1203,80 @@ namespace SBE procIOMask ); // Bits(8:31) = EC00:EC23 // Check for no error and use of input cores - if ( (NULL == err) && (procIOMask == coreMask)) + if (nullptr == err) { - // Procedure was successful - procedure_success = true; - - o_actImgSize = static_cast<size_t>(tmpImgSize); - - TRACUCOMP( g_trac_sbe, "procCustomizeSbeImg(): " - "p9_xip_customize success=%d, procIOMask=0x%X " - "o_actImgSize=0x%X", - procedure_success, procIOMask, o_actImgSize); - - // exit inner loop - break; - } - // Check if p9_xip_customize returned a different core mask - else if ( procIOMask != coreMask ) - { - // A different core mask is returned from p9_xip_customize - // when the cores sent in couldn't fit, but possibly - // a different procIOMask would work + // FAPI_INVOKE_HWP returned with no error, check input cores + if (procIOMask == coreMask) + { + // Procedure was successful + procedure_success = true; - TRACFCOMP( g_trac_sbe, - ERR_MRK"procCustomizeSbeImg(): FAPI_INVOKE_HWP(" - "p9_xip_customize) returned rc=0x%X, " - "XIPC_IMAGE_WOULD_OVERFLOW-Retry " - "MaxCores=0x%.8X. HUID=0x%X. coreMask=0x%.8X, " - "procIOMask=0x%.8X. coreCount=%d", - ERRL_GETRC_SAFE(err), maxCores, - TARGETING::get_huid(i_target), - coreMask, procIOMask, coreCount); + o_actImgSize = static_cast<size_t>(tmpImgSize); - // Setup for next loop - update coreMask - err = selectBestCores(i_target, - --coreCount, - coreMask); + TRACUCOMP( g_trac_sbe, "procCustomizeSbeImg(): " + "p9_xip_customize success=%d, procIOMask=0x%X " + "o_actImgSize=0x%X", + procedure_success, procIOMask, o_actImgSize); - if ( err ) - { - TRACFCOMP(g_trac_sbe, - ERR_MRK"procCustomizeSbeImg() - " - "selectBestCores() failed rc=0x%X. " - "coreCount=0x%.8X. HUID=0x%X. Aborting " - "Customization of SBE Image", - err->reasonCode(), coreCount, - TARGETING::get_huid(i_target)); - - // break from inner while loop + // exit inner loop break; - } + } // end if (procIOMask == coreMask) + // p9_xip_customize returned a different core mask: + // procIOMask != coreMask + else + { + // A different core mask is returned from + // p9_xip_customize, when the cores sent in couldn't + // fit, but possibly a different procIOMask would work - TRACFCOMP( g_trac_sbe, "procCustomizeSbeImg(): for " - "next loop: coreMask=0x%.8X, coreCount=%d", - coreMask, coreCount); + TRACFCOMP( g_trac_sbe, + ERR_MRK"procCustomizeSbeImg(): FAPI_INVOKE_HWP(" + "p9_xip_customize) returned rc=0x%X, " + "XIPC_IMAGE_WOULD_OVERFLOW-Retry " + "MaxCores=0x%.8X. HUID=0x%X. coreMask=0x%.8X, " + "procIOMask=0x%.8X. coreCount=%d", + ERRL_GETRC_SAFE(err), maxCores, + TARGETING::get_huid(i_target), + coreMask, procIOMask, coreCount); + + // Setup for next loop - update coreMask + err = selectBestCores(i_target, + --coreCount, + coreMask); + + if ( err ) + { + TRACFCOMP(g_trac_sbe, + ERR_MRK"procCustomizeSbeImg() - " + "selectBestCores() failed rc=0x%X. " + "coreCount=0x%.8X. HUID=0x%X. Aborting " + "Customization of SBE Image", + err->reasonCode(), coreCount, + TARGETING::get_huid(i_target)); + + // break from inner while loop + break; + } - // Check if loop will execute again - // Clean up some data if it will - if( coreCount >= min_cores ) - { - // Reset size and clear image buffer - tmpImgSize = static_cast<uint32_t>(i_maxImgSize); - memset ( io_imgPtr, - 0, - tmpImgSize); - } + TRACFCOMP( g_trac_sbe, "procCustomizeSbeImg(): for " + "next loop: coreMask=0x%.8X, coreCount=%d", + coreMask, coreCount); + + // Check if loop will execute again + // Clean up some data if it will + if( coreCount >= min_cores ) + { + // Reset size and clear image buffer + tmpImgSize = static_cast<uint32_t>(i_maxImgSize); + memset ( io_imgPtr, + 0, + tmpImgSize); + } + } // end if (procIOMask == coreMask) ... else ... // No break - keep looping - } + + } // end if (nullptr == err) else { // Unexpected return code - create err and fail @@ -1292,7 +1297,7 @@ namespace SBE // break from inner while loop break; - } + } // end if (nullptr == err) ... else ... } // end of inner while loop if(err) diff --git a/src/usr/sbe/test/sbeupdatetest.H b/src/usr/sbe/test/sbeupdatetest.H index cf482c053..e8c508414 100644 --- a/src/usr/sbe/test/sbeupdatetest.H +++ b/src/usr/sbe/test/sbeupdatetest.H @@ -38,7 +38,6 @@ #include <devicefw/driverif.H> #include <vfs/vfs.H> #include <targeting/common/utilFilter.H> -#include <config.h> #include <sbe/sbeif.H> #include <sbe/sbe_update.H> #include <secureboot/service.H> diff --git a/src/usr/sbeio/runtime/makefile b/src/usr/sbeio/runtime/makefile index 37792b554..e50153946 100644 --- a/src/usr/sbeio/runtime/makefile +++ b/src/usr/sbeio/runtime/makefile @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2017,2018 +# Contributors Listed Below - COPYRIGHT 2017,2019 # [+] International Business Machines Corp. # # @@ -37,6 +37,7 @@ include ../common/common.mk ## Objects unique to HBRT OBJS += rt_sbeio.o OBJS += sbeio_attr_override.o +OBJS += sbeio_nvdimm_operation.o OBJS += sbeio_vital_attn.o ## sbeio_rt's sub directories diff --git a/src/usr/sbeio/runtime/rt_sbeio.C b/src/usr/sbeio/runtime/rt_sbeio.C index 3aed96db6..1c95596a5 100644 --- a/src/usr/sbeio/runtime/rt_sbeio.C +++ b/src/usr/sbeio/runtime/rt_sbeio.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017,2018 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -29,6 +29,7 @@ #include <sys/misc.h> #include <sbeio/runtime/sbe_msg_passing.H> #include <sbeio/runtime/sbeio_attr_override.H> +#include <sbeio/runtime/sbeio_nvdimm_operation.H> #include <sbeio/sbeioreasoncodes.H> #include <errno.h> #include <errl/errlentry.H> @@ -40,7 +41,7 @@ #include <targeting/common/target.H> #include <targeting/common/commontargeting.H> #include <targeting/common/utilFilter.H> -#include <runtime/rt_targeting.H> +#include <targeting/runtime/rt_targeting.H> using namespace TARGETING; @@ -782,6 +783,10 @@ namespace RT_SBEIO #endif SBE_MSG::setProcessCmdFunction(PASSTHRU_HBRT_OVERRIDE_ATTR, sbeApplyAttrOverrides); +#ifdef CONFIG_NVDIMM + SBE_MSG::setProcessCmdFunction(PASSTHRU_HBRT_NVDIMM_OP, + sbeNvdimmOperation); +#endif } }; diff --git a/src/usr/sbeio/runtime/sbeio_nvdimm_operation.C b/src/usr/sbeio/runtime/sbeio_nvdimm_operation.C new file mode 100644 index 000000000..f41cd01a5 --- /dev/null +++ b/src/usr/sbeio/runtime/sbeio_nvdimm_operation.C @@ -0,0 +1,64 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/sbeio/runtime/sbeio_nvdimm_operation.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#include <sbeio/runtime/sbeio_nvdimm_operation.H> + +#include <runtime/interface.h> +#include <util/runtime/rt_fwnotify.H> +#include <sbeio/sbeioreasoncodes.H> +#include <errl/errlentry.H> + +extern trace_desc_t* g_trac_sbeio; + +using namespace ERRORLOG; + +namespace SBE_MSG +{ + +//------------------------------------------------------------------------- +errlHndl_t sbeNvdimmOperation( TARGETING::TargetHandle_t i_procTgt, + uint32_t i_reqDataSize, + uint8_t * i_reqData, + uint32_t * o_rspStatus, + uint32_t * o_rspDataSize, + uint8_t * o_rspData ) +{ + errlHndl_t errl{}; + + do + { + *o_rspDataSize = 0; //No return data + o_rspData = nullptr; + + // doNvDimmOperation will take care of handling errors it encounters. + hostInterfaces::nvdimm_operation_t* l_nvdimmOp = + reinterpret_cast<hostInterfaces::nvdimm_operation_t*>(i_reqData); + *o_rspStatus = doNvDimmOperation(*l_nvdimmOp); + } + while(0); + + return errl; +} + +}//End namespace diff --git a/src/usr/sbeio/runtime/test/sbeioAttrOverrideTests.H b/src/usr/sbeio/runtime/test/sbeioAttrOverrideTests.H index d99acfe8b..5c58078c5 100644 --- a/src/usr/sbeio/runtime/test/sbeioAttrOverrideTests.H +++ b/src/usr/sbeio/runtime/test/sbeioAttrOverrideTests.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ +/* Contributors Listed Below - COPYRIGHT 2017,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,7 +27,6 @@ #include <cxxtest/TestSuite.H> #include <runtime/interface.h> -#include <runtime/rt_targeting.H> #include <sbeio/runtime/sbe_msg_passing.H> #include <sbeio/sbeioreasoncodes.H> #include <secureboot/service.H> @@ -35,6 +34,7 @@ #include <targeting/common/target.H> #include <targeting/common/targetservice.H> #include <targeting/common/utilFilter.H> +#include <targeting/runtime/rt_targeting.H> #include <errl/errlmanager.H> #include <devicefw/userif.H> @@ -173,8 +173,8 @@ public: } l_proc = procList[0]; - RT_TARG::rtChipId_t l_chipId = 0; - errlHndl_t l_err = RT_TARG::getRtTarget(l_proc, l_chipId); + TARGETING::rtChipId_t l_chipId = 0; + errlHndl_t l_err = TARGETING::getRtTarget(l_proc, l_chipId); if(nullptr != l_err) { diff --git a/src/usr/sbeio/runtime/test/sbeiotestRt.H b/src/usr/sbeio/runtime/test/sbeiotestRt.H index a2a4b1996..c91a663bb 100644 --- a/src/usr/sbeio/runtime/test/sbeiotestRt.H +++ b/src/usr/sbeio/runtime/test/sbeiotestRt.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017,2018 */ +/* Contributors Listed Below - COPYRIGHT 2017,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -35,7 +35,7 @@ #include <runtime/interface.h> #include <sbeio/runtime/sbe_msg_passing.H> #include <sbeio/sbeioreasoncodes.H> -#include <runtime/rt_targeting.H> +#include <targeting/runtime/rt_targeting.H> #include <targeting/common/attributes.H> #include <targeting/common/utilFilter.H> #include <errl/errlmanager.H> @@ -88,7 +88,7 @@ class SbeMessagePassingRtTest : public CxxTest::TestSuite */ int initSbeMessagePassing(sbeMessage_t& o_request, sbeMessage_t& o_expected_response, - RT_TARG::rtChipId_t& o_chipId, + TARGETING::rtChipId_t& o_chipId, uint64_t& o_sbeCommAddr, runtimeInterfaces_t **o_rt_intf) { @@ -142,8 +142,8 @@ class SbeMessagePassingRtTest : public CxxTest::TestSuite TargetHandle_t proc = procList[0]; // Get the chip ID for the proc - RT_TARG::rtChipId_t o_chipId = 0; - errlHndl_t err = RT_TARG::getRtTarget(proc, o_chipId); + TARGETING::rtChipId_t o_chipId = 0; + errlHndl_t err = TARGETING::getRtTarget(proc, o_chipId); if(nullptr != err) { rc = -1; @@ -311,7 +311,7 @@ class SbeMessagePassingRtTest : public CxxTest::TestSuite * * @return Return Code O if Successful, otherwise not 0. */ - int checkResetSbeMessagePassingCFAM(RT_TARG::rtChipId_t i_procChipId, + int checkResetSbeMessagePassingCFAM(TARGETING::rtChipId_t i_procChipId, uint32_t i_checkMask = SBE_MSG_MASK) { // Test check / reset CFAM entry @@ -402,7 +402,7 @@ class SbeMessagePassingRtTest : public CxxTest::TestSuite "testSbeMessagePassingVersions"); sbeMessage_t l_request; sbeMessage_t l_expected_response; - RT_TARG::rtChipId_t chipId = 0; + TARGETING::rtChipId_t chipId = 0; uint64_t l_sbeCommAddr = 0; runtimeInterfaces_t *rt_intf = nullptr; @@ -501,7 +501,7 @@ class SbeMessagePassingRtTest : public CxxTest::TestSuite sbeMessage_t l_request; sbeMessage_t l_expected_response; - RT_TARG::rtChipId_t chipId = 0; + TARGETING::rtChipId_t chipId = 0; uint64_t l_sbeCommAddr = 0; runtimeInterfaces_t *rt_intf = nullptr; @@ -567,7 +567,7 @@ class SbeMessagePassingRtTest : public CxxTest::TestSuite sbeMessage_t l_request; sbeMessage_t l_expected_response; - RT_TARG::rtChipId_t chipId = 0; + TARGETING::rtChipId_t chipId = 0; uint64_t l_sbeCommAddr = 0; runtimeInterfaces_t *rt_intf = nullptr; @@ -741,7 +741,7 @@ class SbeMessagePassingRtTest : public CxxTest::TestSuite sbeMessage_t l_request; sbeMessage_t l_expected_response; - RT_TARG::rtChipId_t chipId = 0; + TARGETING::rtChipId_t chipId = 0; uint64_t l_sbeCommAddr = 0; runtimeInterfaces_t *rt_intf = nullptr; @@ -832,7 +832,7 @@ class SbeMessagePassingRtTest : public CxxTest::TestSuite sbeMessage_t l_request; sbeMessage_t l_expected_response; - RT_TARG::rtChipId_t chipId = 0; + TARGETING::rtChipId_t chipId = 0; uint64_t l_sbeCommAddr = 0; runtimeInterfaces_t *rt_intf = nullptr; @@ -984,7 +984,7 @@ class SbeMessagePassingRtTest : public CxxTest::TestSuite sbeMessage_t l_request; sbeMessage_t l_expected_response; - RT_TARG::rtChipId_t chipId = 0; + TARGETING::rtChipId_t chipId = 0; uint64_t l_sbeCommAddr = 0; runtimeInterfaces_t *rt_intf = nullptr; @@ -1142,7 +1142,7 @@ class SbeMessagePassingRtTest : public CxxTest::TestSuite sbeMessage_t l_request; sbeMessage_t l_expected_response; uint32_t l_hdrsSize = sizeof(sbeHeader_t) + sizeof(cmdHeader_t); - RT_TARG::rtChipId_t chipId = 0; + TARGETING::rtChipId_t chipId = 0; uint64_t l_sbeCommAddr = 0; runtimeInterfaces_t *rt_intf = nullptr; diff --git a/src/usr/sbeio/sbe_continueMpipl.C b/src/usr/sbeio/sbe_continueMpipl.C index d791fce1a..ce2c584cc 100644 --- a/src/usr/sbeio/sbe_continueMpipl.C +++ b/src/usr/sbeio/sbe_continueMpipl.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2017 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -28,7 +28,6 @@ procs in the system. */ -#include <config.h> #include <trace/interface.H> #include <errl/errlmanager.H> #include <sbeio/sbeioif.H> diff --git a/src/usr/sbeio/sbe_coreStateControl.C b/src/usr/sbeio/sbe_coreStateControl.C index 6c102d755..cf912e7b8 100644 --- a/src/usr/sbeio/sbe_coreStateControl.C +++ b/src/usr/sbeio/sbe_coreStateControl.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2017 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,7 +27,6 @@ * @brief Core State Control Messages to control the deadmap loop */ -#include <config.h> #include <trace/interface.H> #include <errl/errlmanager.H> #include <sbeio/sbeioif.H> diff --git a/src/usr/sbeio/sbe_getSBEFFDC.C b/src/usr/sbeio/sbe_getSBEFFDC.C index 2ccd6451c..d77d6e40d 100644 --- a/src/usr/sbeio/sbe_getSBEFFDC.C +++ b/src/usr/sbeio/sbe_getSBEFFDC.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,7 +27,6 @@ * @brief Get SBE FFDC. */ -#include <config.h> #include <trace/interface.H> #include <errl/errlmanager.H> #include "sbe_fifodd.H" diff --git a/src/usr/sbeio/sbe_memRegionMgr.C b/src/usr/sbeio/sbe_memRegionMgr.C index a5692549d..790924812 100644 --- a/src/usr/sbeio/sbe_memRegionMgr.C +++ b/src/usr/sbeio/sbe_memRegionMgr.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017,2018 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,7 +27,6 @@ * @brief Opens and Closes Unsecure Memory Regions via the SBE */ -#include <config.h> #include <trace/interface.H> #include <errl/errlmanager.H> #include <sbeio/sbeioif.H> diff --git a/src/usr/sbeio/sbe_psuQuiesce.C b/src/usr/sbeio/sbe_psuQuiesce.C index a10f5e8c3..7e1ced443 100644 --- a/src/usr/sbeio/sbe_psuQuiesce.C +++ b/src/usr/sbeio/sbe_psuQuiesce.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2018 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,7 +27,6 @@ * @brief Send command to quiesce the SBE */ -#include <config.h> #include <trace/interface.H> #include <errl/errlmanager.H> #include <sbeio/sbeioif.H> diff --git a/src/usr/sbeio/sbe_psuReadSeeprom.C b/src/usr/sbeio/sbe_psuReadSeeprom.C index bb8171716..5ccb87bca 100644 --- a/src/usr/sbeio/sbe_psuReadSeeprom.C +++ b/src/usr/sbeio/sbe_psuReadSeeprom.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2018 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,7 +27,6 @@ * @brief Send command to request Seeprom read on SBE */ -#include <config.h> #include <trace/interface.H> #include <errl/errlmanager.H> #include <sbeio/sbeioif.H> diff --git a/src/usr/sbeio/sbe_secureHwp.C b/src/usr/sbeio/sbe_secureHwp.C index 246935e78..b115f3533 100644 --- a/src/usr/sbeio/sbe_secureHwp.C +++ b/src/usr/sbeio/sbe_secureHwp.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2018 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,7 +27,6 @@ * @brief Send request to perform a HWP securely on SBE */ -#include <config.h> #include <trace/interface.H> #include <errl/errlmanager.H> #include <sbeio/sbeioif.H> diff --git a/src/usr/sbeio/sbe_securityListBinDump.C b/src/usr/sbeio/sbe_securityListBinDump.C index 973d48046..b2c0f70d9 100644 --- a/src/usr/sbeio/sbe_securityListBinDump.C +++ b/src/usr/sbeio/sbe_securityListBinDump.C @@ -28,7 +28,6 @@ * for the whitelist/blacklist algorithm. */ -#include <config.h> #include <trace/interface.H> #include <errl/errlmanager.H> #include <sbeio/sbeioif.H> diff --git a/src/usr/sbeio/sbe_setFFDCAddr.C b/src/usr/sbeio/sbe_setFFDCAddr.C index 5988336f9..526b3224d 100644 --- a/src/usr/sbeio/sbe_setFFDCAddr.C +++ b/src/usr/sbeio/sbe_setFFDCAddr.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -28,7 +28,6 @@ procs in the system. */ -#include <config.h> #include <trace/interface.H> #include <errl/errlmanager.H> #include <sbeio/sbeioif.H> diff --git a/src/usr/sbeio/sbe_stashKeyAddr.C b/src/usr/sbeio/sbe_stashKeyAddr.C index 8ce3e6833..6ad410b2a 100644 --- a/src/usr/sbeio/sbe_stashKeyAddr.C +++ b/src/usr/sbeio/sbe_stashKeyAddr.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2017 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,7 +27,6 @@ * @brief Send command to stash key-value pair in the SBE */ -#include <config.h> #include <trace/interface.H> #include <errl/errlmanager.H> #include <sbeio/sbeioif.H> diff --git a/src/usr/sbeio/sbe_systemConfig.C b/src/usr/sbeio/sbe_systemConfig.C index 1b0409b2b..c5733429c 100644 --- a/src/usr/sbeio/sbe_systemConfig.C +++ b/src/usr/sbeio/sbe_systemConfig.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2017 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -28,7 +28,6 @@ procs in the system. */ -#include <config.h> #include <trace/interface.H> #include <errl/errlmanager.H> #include <sbeio/sbeioif.H> diff --git a/src/usr/sbeio/test/sbe_getsbeffdctest.H b/src/usr/sbeio/test/sbe_getsbeffdctest.H index 431d81696..100c8254f 100644 --- a/src/usr/sbeio/test/sbe_getsbeffdctest.H +++ b/src/usr/sbeio/test/sbe_getsbeffdctest.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -103,6 +103,14 @@ class GetSBEFFDCTest : public CxxTest::TestSuite continue; } + //TODO RTC:214913 -- Need to debug errors associated with + // this testcase being executed + if (1) + { + TS_TRACE("getSBEFFDCTest: Skipping testing because it doesn't work "); + continue; + } + l_errl = SBEIO::getFifoSBEFFDC(l_cpu_target, l_pFifoResponse, l_responseSize); diff --git a/src/usr/sbeio/test/sbe_retry_handler_test.H b/src/usr/sbeio/test/sbe_retry_handler_test.H index 9a3719895..56a721972 100644 --- a/src/usr/sbeio/test/sbe_retry_handler_test.H +++ b/src/usr/sbeio/test/sbe_retry_handler_test.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017,2018 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -78,6 +78,8 @@ class SbeRetryHandlerTest : public CxxTest::TestSuite // we are just looking at Slave SBE's continue; } + /* TODO RTC:214913 -- Re-enable/Fixup as in its current state + it causes an infinite loop SbeRetryHandler l_SBEobj = SbeRetryHandler( SbeRetryHandler::SBE_MODE_OF_OPERATION::ATTEMPT_REBOOT); @@ -85,6 +87,7 @@ class SbeRetryHandlerTest : public CxxTest::TestSuite SBE_TRACF_RHT("testSBEReturns: returned from main_sbe_handler " "SUCCESS"); + **/ } } @@ -117,6 +120,9 @@ class SbeRetryHandlerTest : public CxxTest::TestSuite // we are just looking at Slave SBE's continue; } + /* TODO RTC:214913 -- Re-enable/Fixup as in its current state + it causes an infinite loop + SbeRetryHandler l_SBEobj = SbeRetryHandler( SbeRetryHandler::SBE_MODE_OF_OPERATION::ATTEMPT_REBOOT); @@ -136,6 +142,7 @@ class SbeRetryHandlerTest : public CxxTest::TestSuite "that the SBE started is false, then the SBE attribute " "also needs to be false"); } + **/ } } diff --git a/src/usr/scom/handleSpecialWakeup.C b/src/usr/scom/handleSpecialWakeup.C index 07bab3a1b..e202e9bdb 100644 --- a/src/usr/scom/handleSpecialWakeup.C +++ b/src/usr/scom/handleSpecialWakeup.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -37,7 +37,7 @@ #include <initservice/initserviceif.H> #ifdef __HOSTBOOT_RUNTIME -#include <runtime/rt_targeting.H> +#include <targeting/runtime/rt_targeting.H> #include <runtime/interface.h> #endif // __HOSTBOOT_RUNTIME @@ -156,8 +156,8 @@ errlHndl_t callWakeupHyp(TARGETING::Target* i_target, ++pCore_it ) { // Runtime target id - RT_TARG::rtChipId_t rtTargetId = 0; - l_errl = RT_TARG::getRtTarget(*pCore_it, rtTargetId); + TARGETING::rtChipId_t rtTargetId = 0; + l_errl = TARGETING::getRtTarget(*pCore_it, rtTargetId); if(l_errl) { break; diff --git a/src/usr/scom/runtime/rt_scom.C b/src/usr/scom/runtime/rt_scom.C index a27dfe81e..4507b435f 100644 --- a/src/usr/scom/runtime/rt_scom.C +++ b/src/usr/scom/runtime/rt_scom.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2018 */ +/* Contributors Listed Below - COPYRIGHT 2013,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -30,7 +30,7 @@ #include <scom/scomif.H> #include <scom/runtime/rt_scomif.H> #include <runtime/interface.h> -#include <runtime/rt_targeting.H> +#include <targeting/runtime/rt_targeting.H> #include <xscom/piberror.H> #include <runtime/hbrt_utilities.H> @@ -169,9 +169,9 @@ errlHndl_t sendScomToHyp(DeviceFW::OperationType i_opType, do { // Convert target to something Sapphire understands - RT_TARG::rtChipId_t proc_id = 0; - l_err = RT_TARG::getRtTarget(i_target, - proc_id); + TARGETING::rtChipId_t target_id = 0; + l_err = TARGETING::getRtTarget(i_target, + target_id); if(l_err) { break; @@ -185,7 +185,7 @@ errlHndl_t sendScomToHyp(DeviceFW::OperationType i_opType, if(i_opType == DeviceFW::READ) { l_hostRC = - g_hostInterfaces->scom_read(proc_id, + g_hostInterfaces->scom_read(target_id, i_scomAddr, io_buffer ); @@ -193,7 +193,7 @@ errlHndl_t sendScomToHyp(DeviceFW::OperationType i_opType, else if (i_opType == DeviceFW::WRITE) { l_hostRC = - g_hostInterfaces->scom_write(proc_id, + g_hostInterfaces->scom_write(target_id, i_scomAddr, io_buffer ); @@ -203,8 +203,8 @@ errlHndl_t sendScomToHyp(DeviceFW::OperationType i_opType, { TRACFCOMP(g_trac_scom,ERR_MRK "Hypervisor scom read/write failed. " - "rc 0x%X target 0x%llX proc_id 0x%llX addr 0x%llX r/w %d", - l_hostRC, get_huid(i_target), proc_id, i_scomAddr, i_opType); + "rc 0x%X target 0x%llX target_id 0x%llX addr 0x%llX r/w %d", + l_hostRC, get_huid(i_target), target_id, i_scomAddr, i_opType); // Use an unused bit in the 64-bit scom range to indicate // read/write. Cannot use bit0 since that is part of an diff --git a/src/usr/scom/runtime/test/testscom_rt.H b/src/usr/scom/runtime/test/testscom_rt.H index f0a14fe1b..e39d06d96 100644 --- a/src/usr/scom/runtime/test/testscom_rt.H +++ b/src/usr/scom/runtime/test/testscom_rt.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2018 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -1242,29 +1242,6 @@ public: TS_FAIL( "ScomTest::test__MultiChipScomWrite_proc> ERROR : Data mismatch between read and expected data" ); fails++; } - - // Read the data back using FSIscom to make sure the data is the same. - l_err = deviceOp( DeviceFW::READ, - test_data[x].target, - &(read_data[x]), - op_size, - DEVICE_FSISCOM_ADDRESS(test_data[x].addr) ); - - - if( l_err ) - { - TRACFCOMP(g_trac_scom, "ScomTest::test__MultiChipScomWrite_proc> [%d] FSISCOM Read: Error from device : addr=0x%X, RC=%X", x, test_data[x].addr, l_err->reasonCode() ); - TS_FAIL( "ScomTest::test__MultiChipScomWrite_proc> ERROR : Unexpected error log from write1" ); - fails++; - errlCommit(l_err,SCOM_COMP_ID); - } - else if(read_data[x] != test_data[x].data) - { - TRACFCOMP(g_trac_scom, "ScomTest::test__MultiChipScomWrite_proc> [%d] FSISCOM Read: Data mismatch : addr=0x%X, read_data=0x%llx, write_data=0x%llx", x, test_data[x].addr, read_data[x], test_data[x].data); - TS_FAIL( "ScomTest::test__MultiChipScomWrite_proc> ERROR : Data mismatch between read and expected data" ); - fails++; - } - } TRACFCOMP( g_trac_scom, "ScomTest::test__MultiChipScomWrite_proc> %d/%d fails", fails, total ); diff --git a/src/usr/scom/scom.C b/src/usr/scom/scom.C index 22567fb49..d8d696c52 100644 --- a/src/usr/scom/scom.C +++ b/src/usr/scom/scom.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2018 */ +/* Contributors Listed Below - COPYRIGHT 2011,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -50,7 +50,6 @@ #include <targeting/common/utilFilter.H> #include <targeting/namedtarget.H> -#include <config.h> #ifndef __HOSTBOOT_RUNTIME #ifdef CONFIG_SECUREBOOT diff --git a/src/usr/scom/scomtrans.C b/src/usr/scom/scomtrans.C index bb5d8b282..6f0275e33 100644 --- a/src/usr/scom/scomtrans.C +++ b/src/usr/scom/scomtrans.C @@ -187,6 +187,16 @@ DEVICE_REGISTER_ROUTE(DeviceFW::WILDCARD, TARGETING::TYPE_OMI, startScomProcess); +DEVICE_REGISTER_ROUTE(DeviceFW::WILDCARD, + DeviceFW::SCOM, + TARGETING::TYPE_NPU, + startScomProcess); + +DEVICE_REGISTER_ROUTE(DeviceFW::WILDCARD, + DeviceFW::SCOM, + TARGETING::TYPE_MEM_PORT, + startScomProcess); + ////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////// errlHndl_t startScomProcess(DeviceFW::OperationType i_opType, @@ -296,9 +306,10 @@ errlHndl_t scomTranslate(TARGETING::Target * &i_target, // Get the type attribute. TARGETING::TYPE l_type = i_target->getAttr<TARGETING::ATTR_TYPE>(); - centaurChipUnits_t l_chipUnit = CENTAUR_CHIP; + centaurChipUnits_t l_cenChipUnit = CENTAUR_CHIP; + p9ChipUnits_t l_p9ChipUnit = NONE; - if(false == getChipUnitCentaur(l_type,l_chipUnit)) + if(false == getChipUnitCentaur(l_type,l_cenChipUnit)) { l_err = centaur_translation(i_target, l_type, @@ -306,14 +317,21 @@ errlHndl_t scomTranslate(TARGETING::Target * &i_target, i_opMode); o_needsWakeup = false; } - else + else if(false == getChipUnitP9(l_type,l_p9ChipUnit)) { l_err = p9_translation(i_target, - l_type, - io_addr, - o_needsWakeup, - i_opMode); + l_type, + io_addr, + o_needsWakeup, + i_opMode); + } + else + { + // The only type leftover should be mem_port, and there is + // no translation required for that + assert( TARGETING::TYPE_MEM_PORT == l_type ); } + return l_err; } @@ -960,6 +978,11 @@ bool getChipUnitP9 (TARGETING::TYPE i_type, o_chipUnit = PU_OMIC_CHIPUNIT; break; } + case(TARGETING::TYPE_NPU) : + { + o_chipUnit = PU_NPU_CHIPUNIT; + break; + } default: { l_isError = true; diff --git a/src/usr/scom/test/scomtest.H b/src/usr/scom/test/scomtest.H index 87444367b..0ad82d625 100644 --- a/src/usr/scom/test/scomtest.H +++ b/src/usr/scom/test/scomtest.H @@ -39,7 +39,6 @@ #include <targeting/common/util.H> #include <targeting/common/utilFilter.H> #include <scom/scomif.H> -#include <config.h> #include <devicefw/driverif.H> @@ -449,9 +448,7 @@ public: { scom_targets[myPROC0], 0x80000C010D010C3F ,0x1234432112344321, false, TARGETING::MODEL_POWER9 }, { scom_targets[myPROC0], 0x80000C0107011C3F, 0x123443211234ABAB, false, TARGETING::MODEL_NIMBUS }, { scom_targets[myPROC0], 0x80000C0107011C3F, 0x123443211234ABAB, false, TARGETING::MODEL_CUMULUS }, -#ifndef CONFIG_AXONE_BRING_UP { scom_targets[myPROC0], 0x800040000701103F, 0x123443211234ABAB, false, TARGETING::MODEL_AXONE }, -#endif { scom_targets[myPROC0], 0x8FFFFFFFFFFFFFFF, 0x123443211234ABAB, true, TARGETING::MODEL_POWER9 }, }; const uint64_t NUM_ADDRS = sizeof(test_data)/sizeof(test_data[0]); @@ -1190,10 +1187,8 @@ public: { scom_targets[myMC1],0x07010008, 0x08010008, false, TARGETING::MODEL_AXONE}, { scom_targets[myMC0],0x0FFFFFFF, 0x0FFFFFFF, true, TARGETING::MODEL_AXONE}, { scom_targets[myMC1],0x0FFFFFFF, 0x0FFFFFFF, true, TARGETING::MODEL_AXONE}, -#ifndef CONFIG_AXONE_BRING_UP - { scom_targets[myMI0],0x02010803, 0x02010803, false, TARGETING::MODEL_AXONE}, - { scom_targets[myMI3],0x02010803, 0x03010803, false, TARGETING::MODEL_AXONE}, -#endif + { scom_targets[myMI0],0x05010810, 0x05010810, false, TARGETING::MODEL_AXONE}, + { scom_targets[myMI3],0x05010810, 0x06010810, false, TARGETING::MODEL_AXONE}, { scom_targets[myMI0],0x0FFFFFFF, 0x0FFFFFFF, true, TARGETING::MODEL_AXONE}, { scom_targets[myMI3],0x0FFFFFFF, 0x0FFFFFFF, true, TARGETING::MODEL_AXONE}, { scom_targets[myMCC0],0x07010900, 0x07010900, false, TARGETING::MODEL_AXONE}, diff --git a/src/usr/secureboot/HBconfig b/src/usr/secureboot/HBconfig index af987887c..4f1a179b4 100644 --- a/src/usr/secureboot/HBconfig +++ b/src/usr/secureboot/HBconfig @@ -22,3 +22,17 @@ config TPM_NVIDX_VALIDATE depends on TPMDD help Validate TPM MFG NV Index Provisioning during IPL + +config PHYS_PRES_PWR_BUTTON + default n + depends on !PHYS_PRES_JUMPER + help + Support asserting Physical Presence via pushing the Power Button + on the system + +config PHYS_PRES_JUMPER + default n + depends on !PHYS_PRES_PRW_BUTTON + help + Support asserting Physical Presence via a jumper on the TPM Card + Currently not supported. diff --git a/src/usr/secureboot/README.md b/src/usr/secureboot/README.md new file mode 100644 index 000000000..979cada54 --- /dev/null +++ b/src/usr/secureboot/README.md @@ -0,0 +1,64 @@ +# Secureboot Services in Hostboot +Hostboot provides multiple services to help secure the system and + ensure that only 'trusted' code is running on it. The multiple sub-directories + implement the various interfaces defined in the + [src/include/usr/secureboot/](../../include/usr/secureboot/) directory. + +## Directories +* __base__ + * The modules here define the core secureboot support: **defining and + implementing interfaces to retrieve the security state of the system** + * The directory is called 'base' because its contents are included in the + Hostboot Base Image (HBB) partition + * See [base/README.md](base/README.md) for more details + +* __common__ + * The modules here provide common support like tracing, error callouts, + definitions of the secure "container" header, etc, that is used by the + secureboot modules in the peer directories + * See [common/README.md](common/README.md) for more details + +* __ext__ + * The modules here provide some additional secureboot capabilities that are + beyond the core secureboot functionality found in the "base" directory + * This directory is called 'ext' because its contents are included in the + Hostboot Extended Image (HBI) + * Any module here can call into the Hostboot Base Image (ie the 'base' code + in the HBB partition)), but Hostboot Base Image modules cannot call into + these extended image modules + * See [ext/README.md](ext/README.md) for more details + +* __node_comm__ + * The modules here implement a node-to-node communication protocol that is + used on multinode systems to share secureboot data between the nodes + * See [node_comm/README.md](node_comm/README.md) for more details + +* __runtime__ + * The modules here implement a small subset of secureboot code that is used by + Hostboot runtime services. + * See [runtime/README.md](runtime/README.md) for more details + +* __smf__ + * The modules here distribute different amounts of Secure SMF memory between + the available processors on the system based on a user-configurable petitboot + setting + * If we ever supported this on P9 FSP-based systems, the SMF memory amount + would be passed from the FSP to Hostboot using attributes. + * See [smf/README.md](smf/README.md) for more details + +* __trusted__ + * The modules here define the trusted boot support which uses TPMs (Trusted + Platform Modules) to track what code is running on the system + * See [trusted/README.md](trusted/README.md) for more details + +## Other Files +* __HBconfig__ + * Standard HBconfig file that defines secureboot- and trustedboot-related + Hostboot compile variables + +* __makefile__ + * Standard Hostboot makefile + +* __[README.md](./README.md)__ + * This file + diff --git a/src/usr/secureboot/base/README.md b/src/usr/secureboot/base/README.md new file mode 100644 index 000000000..e761c1f2f --- /dev/null +++ b/src/usr/secureboot/base/README.md @@ -0,0 +1,60 @@ +# **'base'** Secureboot Services in Hostboot +This directory implements the core of the secureboot-related functionality + that Hostboot provides. +It is available in the Hostboot Base Image (ie the HBB partition) and all + non-runtime Hostboot code can invoke functions provided by it. + +## Key Points +* The **libsecureboot_base.so** module created here is available in Hostboot's + base image and is used to securely bringup the rest of the Hostboot. +* It implements the functions in these header files: + * [service.H](../../../include/usr/secureboot/service.H) + * [settings.H](../../../include/usr/secureboot/settings.H) +* It is used to tell if security is enabled at the system or processor level +* It is used to determine the state of the secureboot jumper on the different + processors +* It provides the interface into the SecureRom to verify code packages run + on the system + +## Files + +* __header.C__ + * Implements functions related to loading and retrieving the + Hostboot Base header from Hostboot Base (HBB) PNOR partition + +* __makefile__ + * Standard Hostboot makefile + +* __purge.H__ + * Defines a special purge function + +* __[README.md](./README.md)__ + * This file + +* __securerommgr.C, securerommgr.H__ + * Defines and implements the SecureRomManager class and its member functions + * These functions call into the securerom and takes advantage of + its functionality + +* __service.C__ + * Retrieves the secureboot registers on the processors in the system + * These functions are then used to add information to errorlogs and traces + * Initliaizes the SecureRomManager class + * Function to handle special secureboot failures + * Retrieves some global secureboot settings taken from Hostboot's bootloader + * NOTE: Functions in this file call into functions in settings.C when + appropriate + +* __settings.C__ + * Gets and Sets the two primary Secureboot-related SCOM registers: + * ProcSecurity (aka Proc Security Switch) + * ProcCbsControl + * Also applies knowledge of key bits of these two registers, like returning + if a processor is set in 'secureboot enabled mode' and what the state of its + secureboot jumper is + + +## sub-directories +* __test__ + * Standard Hostboot test directory that implements CXX Unit Tests + diff --git a/src/usr/secureboot/base/securerommgr.C b/src/usr/secureboot/base/securerommgr.C index 17becb6b6..c9e6789cd 100644 --- a/src/usr/secureboot/base/securerommgr.C +++ b/src/usr/secureboot/base/securerommgr.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2018 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -39,7 +39,6 @@ #include "securerommgr.H" #include <secureboot/settings.H> -#include <config.h> #include <console/consoleif.H> #include <secureboot/containerheader.H> #include "../common/errlud_secure.H" diff --git a/src/usr/secureboot/base/service.C b/src/usr/secureboot/base/service.C index 4f115c219..ad6ec691c 100644 --- a/src/usr/secureboot/base/service.C +++ b/src/usr/secureboot/base/service.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2018 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,7 +27,6 @@ #include <sys/mm.h> #include <util/singleton.H> #include <secureboot/secure_reasoncodes.H> -#include <config.h> #include <devicefw/userif.H> #include <targeting/common/utilFilter.H> #include <targeting/common/targetservice.H> diff --git a/src/usr/secureboot/base/settings.C b/src/usr/secureboot/base/settings.C index 2ecf45b4a..ec873c47c 100644 --- a/src/usr/secureboot/base/settings.C +++ b/src/usr/secureboot/base/settings.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2018 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -31,7 +31,6 @@ #include <targeting/common/target.H> #include <initservice/initserviceif.H> #include <secureboot/settings.H> -#include <config.h> #include <console/consoleif.H> #include <kernel/console.H> diff --git a/src/usr/secureboot/common/README.md b/src/usr/secureboot/common/README.md new file mode 100644 index 000000000..56ff15953 --- /dev/null +++ b/src/usr/secureboot/common/README.md @@ -0,0 +1,33 @@ +# **'common'** Secureboot Services in Hostboot +This directory implements utility functions for tracing and error logging + that other secureboot modules in the peer directories can use. +For example, the secureboot_base, secureboot_rt (runtime), secureboot_trusted, +secureboot_ext, and node_comm modules use these functions. + +## Files + +* __common.mk__ + * Makefile that other makefiles can call to include the generated .o files + +* __containerheader.C__ + * Implements the ContainerHeader class's member functions + * Functions are defined in + [containerheader.H](../../../include/usr/secureboot/containerheader.H) + +* __errlud_secure.C, errlud_secure.H__ + * These files define and implement custom error log user detail sections to + capture security information on the system + +* __[README.md](./README.md)__ + * This file + +* __securetrace.C, securetrace.H__ + * Defines and implements standard Hostboot trace descriptors for the + secureboot component + +## sub-directories +* __plugins__ + * Standard Hostboot 'plugins' directory where the errorlog parser finds the + information to properly parse the custom error log user detail sections + defined in errlud_secure.H + diff --git a/src/usr/secureboot/common/containerheader.C b/src/usr/secureboot/common/containerheader.C index 53baa5afc..28c2c551f 100644 --- a/src/usr/secureboot/common/containerheader.C +++ b/src/usr/secureboot/common/containerheader.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -514,6 +514,7 @@ void ContainerHeader::parseFlags() & LAB_OVERRIDE_FLAG); iv_sbFlags.hw_key_transition =( iv_headerInfo.hw_prefix_hdr.flags & KEY_TRANSITION_FLAG); + iv_sbFlags.sw_hash = iv_headerInfo.sw_hdr.flags & HASH_PAGE_TABLE_FLAG; } #ifndef __HOSTBOOT_RUNTIME diff --git a/src/usr/secureboot/ext/README.md b/src/usr/secureboot/ext/README.md new file mode 100644 index 000000000..797905b0d --- /dev/null +++ b/src/usr/secureboot/ext/README.md @@ -0,0 +1,24 @@ +# **'ext'** Secureboot Services in Hostboot +This directory implements additional (or 'extended') secureboot functionality + that is not considered part of the 'base' secureboot support. + +## Files + +* __makefile__ + * Standard Hostboot makefile + +* __phys_presence.C__ + * Implements the 'physical presence'-related functions, which are used to + assert that a system owner is physically present at the site of a system. + * This is done by using GPIO devices on the system's power button to + capture that the button was physically pressed. + * Functions are defined in + [phys_presence_if.H](../../../include/usr/secureboot/phys_presence_if.H) + +* __[README.md](./README.md)__ + * This file + +* __service_ext.C__ + * Implements some additional (or 'extended') functionality as defined in + [service_ext.H](../../../include/usr/secureboot/service_ext.H) + diff --git a/src/usr/secureboot/ext/drtm.C b/src/usr/secureboot/ext/drtm.C index bec207b7d..c897f0749 100644 --- a/src/usr/secureboot/ext/drtm.C +++ b/src/usr/secureboot/ext/drtm.C @@ -24,7 +24,6 @@ /* IBM_PROLOG_END_TAG */ #include <stdint.h> -#include <config.h> #include <builtins.h> #include <limits.h> #include <string.h> diff --git a/src/usr/secureboot/ext/makefile b/src/usr/secureboot/ext/makefile index 9b5adeaf7..d573515c6 100644 --- a/src/usr/secureboot/ext/makefile +++ b/src/usr/secureboot/ext/makefile @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2013,2018 +# Contributors Listed Below - COPYRIGHT 2013,2019 # [+] International Business Machines Corp. # # @@ -30,6 +30,7 @@ PERV_HWP_PATH = $(ROOTPATH)/src/import/chips/p9/procedures/hwp/perv OBJS += $(if $(CONFIG_DRTM),drtm.o) OBJS += $(if $(CONFIG_SECUREBOOT), service_ext.o) +OBJS += $(if $(CONFIG_PHYS_PRES_PWR_BUTTON), phys_presence.o) VPATH += $(PERV_HWP_PATH) diff --git a/src/usr/secureboot/ext/phys_presence.C b/src/usr/secureboot/ext/phys_presence.C new file mode 100644 index 000000000..a9e0231bf --- /dev/null +++ b/src/usr/secureboot/ext/phys_presence.C @@ -0,0 +1,479 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/secureboot/ext/phys_presence.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/** + * @file phys_presence.C + * + * @brief Implements Interfaces to Detect and Open Physical Presence Windows + * + */ + +#include <config.h> +#include <targeting/common/util.H> +#include <targeting/common/target.H> +#include <errl/errlentry.H> +#include <errl/errlmanager.H> +#include <errl/errludtarget.H> +#include <devicefw/driverif.H> +#include <console/consoleif.H> +#include <util/misc.H> +#include <initservice/initserviceif.H> +#include <initservice/istepdispatcherif.H> +#include <secureboot/secure_reasoncodes.H> +#include <secureboot/phys_presence_if.H> +#include "../common/securetrace.H" +#include <gpio/gpioif.H> + +using namespace TARGETING; +using namespace GPIO; + +namespace SECUREBOOT +{ + +errlHndl_t detectPhysPresence(void) +{ + errlHndl_t err = nullptr; + + SB_ENTER("detectPhysPresence"); + + // Not supported in simics + if (Util::isSimicsRunning()) + { + SB_ERR("detectPhysPresence: Skipping as not supported in simics"); + + // Normally don't have multiple return statements, but + // this solves having 2 do-while loops + return err; + } + + // Declare local variables here as there might be an operation + // after the do-while() loop + Target * mproc = nullptr; + uint8_t led_data = 0; + ATTR_GPIO_INFO_PHYS_PRES_type gpioInfo = {}; + uint8_t led_window_open = 0; + uint8_t led_phys_pres_asserted = 0; + bool is_window_open = false; + bool is_phys_pres_asserted = false; + + // Get the attributes associated with Physical Presence + TargetService& tS = targetService(); + Target* sys = nullptr; + (void) tS.getTopLevelTarget( sys ); + assert(sys, "detectPhysPresence: system target is nullptr"); + + do + { + uint8_t attr_open_window = + sys->getAttr<ATTR_PHYS_PRES_REQUEST_OPEN_WINDOW>(); + + uint8_t attr_fake_assert = sys->getAttr<ATTR_PHYS_PRES_FAKE_ASSERT>(); + // NOTE: Using attributes to request opening the physical presence window + // and/or fake the assertion of physical presence is only for testing + // purposes. Both attributes will default to 'no' and cannot be changed + // when security is enabled in a production driver since attribute + // overrides are not allowed in that scenario. + SB_INF("detectPhysPresence: attr_open_window=%d (0x%X), " + "attr_fake_assert=%d (0x%X)", + attr_open_window, attr_open_window, + attr_fake_assert, attr_fake_assert); + + // The PCA9551 device that controls the "window open" and + // "physical presence asserted" logic is connected to the master processor + err = targetService().queryMasterProcChipTargetHandle(mproc); + if(err) + { + SB_ERR("detectPhysPresence: call to queryMasterProcChipTargetHandle " + "failed. err_plid=0x%X, err_rc=0x%X", + ERRL_GETPLID_SAFE(err), + ERRL_GETRC_SAFE(err)); + + err->collectTrace(SECURE_COMP_NAME); + break; + } + + // Get the attribute with the needed GPIO information + if (mproc->tryGetAttr<ATTR_GPIO_INFO_PHYS_PRES>(gpioInfo)) + { + SB_INF("detectPhysPresence: gpioInfo: e%d/p%d/devAddr=0x%X, " + "windowOpenPin=%d, physPresPin=%d", + gpioInfo.engine, gpioInfo.port, gpioInfo.devAddr, + gpioInfo.windowOpenPin, gpioInfo.physicalPresencePin); + } + else + { + SB_ERR("detectPhysPresence: couldn't find GPIO_INFO_PHYS_PRES " + "on mproc 0x%.08X", get_huid(mproc)); + + /*@ + * @errortype + * @reasoncode RC_PHYS_PRES_ATTR_NOT_FOUND + * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE + * @moduleid MOD_PHYS_PRES_DETECT + * @userdata1 HUID of Master Processor Target + * @userdata2 ATTR_GPIO_INFO_PHYS_PRES hash value + * @devdesc Master processor target did not have + * ATTR_GPIO_INFO_PHYS_PRES associated with it + * @custdesc A problem occurred during the IPL + * of the system. + */ + err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE, + MOD_PHYS_PRES_DETECT, + RC_PHYS_PRES_ATTR_NOT_FOUND, + get_huid(mproc), + ATTR_GPIO_INFO_PHYS_PRES, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + + err->collectTrace( SECURE_COMP_NAME ); + break; + } + + // Get "window open" and "physical presence asserted" LEDs/Pins + led_window_open = PCA9551_LED0 << gpioInfo.windowOpenPin; + led_phys_pres_asserted = PCA9551_LED0 << gpioInfo.physicalPresencePin; + + // Read PCA9551 INPUT Register to get LED Values + led_data = 0; + err = gpioPca9551GetLeds(mproc, led_data); + if(err) + { + SB_ERR("detectPhysPresence: Reading LEDs failed"); + break; + } + + // Look for "window open" and "physical presence asserted" + // LEDs/PINs represent "WINDOW_OPEN_N" and "PHYS_PRESENCE_N" so need + // to invert their values to get their true meaning + is_window_open = ! (led_window_open & led_data); + + // Only care if its asserted if the window is open + // (technically it's not supposed to be asserted unless the window is open) + is_phys_pres_asserted = is_window_open && + (! (led_phys_pres_asserted & led_data)); + + + // Look for special case to fake assertion + if ((is_window_open == true ) && + (is_phys_pres_asserted == false) && + (attr_fake_assert != 0 )) + { + is_phys_pres_asserted = true; + SB_INF("detectPhysPresence: FAKING Physical Assertion: " + "is_WO=%d, is_PPA=%d, attr_FA=0x%X", + is_window_open, is_phys_pres_asserted, + attr_fake_assert); + + // Write the attribute so faking the assert only happens once + sys->setAttr<ATTR_PHYS_PRES_FAKE_ASSERT>(0x00); + } + + SB_INF("detectPhysPresence: LEDs=0x%.2X, led_WO=0x%X, led_PPA=0x%X, " + "attrWO=0x%X, attr_FA=0x%X, is_WO=%d, is_PPA=%d", + led_data, led_window_open, led_phys_pres_asserted, + attr_open_window, attr_fake_assert, + is_window_open, is_phys_pres_asserted); + + } while(0); + + // Regardless of any previous error, attempt to close the window here + // if it was already opened + if (is_window_open == true) + { + errlHndl_t err_close = nullptr; + err_close = gpioPca9551SetLed(mproc, + static_cast<GPIO::PCA9551_LEDS_t> + (led_window_open), + PCA9551_OUTPUT_HIGH_IMPEDANCE, + led_data); + + if (err_close == nullptr) + { + // Verify that window was closed + // LEDs/PIN represents "WINDOW_OPEN_N" so looking for a "1" in + // that position + if (!(led_data & led_window_open)) + { + SB_ERR("detectPhysPresence: Closed Window LEDs = 0x%.2X " + "indicated that LED %d is showing window is still open", + led_data, led_window_open); + + /*@ + * @errortype + * @reasoncode RC_PHYS_PRES_WINDOW_NOT_CLOSED + * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE + * @moduleid MOD_PHYS_PRES_DETECT + * @userdata1 HUID of Master Processor Target + * @userdata2[0:31] LED Data from PCA9551 + * @userdata[32:63] LED Windoow Open LED (aka PIN) + * @devdesc Attempt to close physical presence window + * did not close the window + * @custdesc A problem occurred during the IPL + * of the system. + */ + err_close = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + MOD_PHYS_PRES_DETECT, + RC_PHYS_PRES_WINDOW_NOT_CLOSED, + get_huid(mproc), + TWO_UINT32_TO_UINT64( + led_data, + led_window_open), + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + } + else + { + SB_INF("detectPhysPresence: Closed Window LEDs = 0x%.2X", + led_data); + } + + } + + if (err_close) + { + if (err) + { + // commit new erro with PLID or original err + err_close->plid(err->plid()); + SB_ERR("detectPhysPresence: Error in closing window. " + "Committing err_close eid=0x%X " + "with plid of original err: 0x%X", + err_close->eid(), err_close->plid()); + + err_close->collectTrace( SECURE_COMP_NAME ); + errlCommit(err_close, SECURE_COMP_ID); + } + else + { + SB_ERR("detectPhysPresence: Error in closing window. " + "err_close eid=0x%X plid=0x%X", + err_close->eid(), err_close->plid()); + err_close->collectTrace( SECURE_COMP_NAME ); + err = err_close; + err_close = nullptr; + } + } + } // end of 'must close window' + + if (err == nullptr) + { + // If no error, including in closing the window, then write attribute + // for Physical Presence Assertion + sys->setAttr<ATTR_PHYS_PRES_ASSERTED>(is_phys_pres_asserted); + } + + SB_EXIT("detectPhysPresence: err rc=0x%X", + ERRL_GETRC_SAFE(err)); + + return err; +} + +errlHndl_t handlePhysPresenceWindow(void) +{ + errlHndl_t err = nullptr; + + SB_ENTER("handlePhysPresenceWindow"); + + // Declare local variables here as there might be an operation + // after the do-while() loop + Target * mproc = nullptr; + uint8_t led_data = 0; + ATTR_GPIO_INFO_PHYS_PRES_type gpioInfo = {}; + uint8_t led_window_open = 0; + bool is_window_open = false; + + do + { + + // Not supported in simics + if (Util::isSimicsRunning()) + { + SB_INF("handlePhysPresenceWindow: Skipping as not supported in simics"); + break; + } + + // Get the attributes associated with Physical Presence + TargetService& tS = targetService(); + Target* sys = nullptr; + (void) tS.getTopLevelTarget( sys ); + assert(sys, "handlePhysPresenceWindow: system target is nullptr"); + + // NOTE: Using attributes to request opening the physical presence window + // and/or fake the assertion of physical presence is only for testing + // purposes. Both attributes will default to 'no' and cannot be changed + // when security is enabled in a production driver since attribute + // overrides are not allowed in that scenario. + uint8_t attr_open_window = + sys->getAttr<ATTR_PHYS_PRES_REQUEST_OPEN_WINDOW>(); + uint8_t attr_phys_pres_asserted = sys->getAttr<ATTR_PHYS_PRES_ASSERTED>(); + + if (attr_open_window == 0) + { + SB_INF("handlePhysPresenceWindow: attr_open_window=0x%.2X: " + "no need to open window (attr_phys_pres_asserted=0x%.2X)", + attr_open_window, attr_phys_pres_asserted); + break; + } + // This solves the issue of using attribute overrides to open the window, + // as they don't always get cleared on re-IPLs and attr_open_window might + // still != 0 + else if (attr_phys_pres_asserted != 0) + { + SB_INF("handlePhysPresenceWindow: attr_open_window=0x%.2X, but " + "attr_phys_pres_asserted=0x%.2X, so no need to open window. " + "Clearing open window request", + attr_open_window, attr_phys_pres_asserted); + + // Close request to open the window + sys->setAttr<ATTR_PHYS_PRES_REQUEST_OPEN_WINDOW>(0x00); + break; + } + else + { + SB_INF("handlePhysPresenceWindow: attr_open_window=0x%.2X, " + "attr_phys_pres_asserted=0x%.2X: " + "Will Open Window To Detect Physical Presence", + attr_open_window, attr_phys_pres_asserted); + } + + // The PCA9551 device that controls the "window open" and + // "physical presence asserted" logic is connected to the master processor + err = targetService().queryMasterProcChipTargetHandle(mproc); + if(err) + { + SB_ERR("handlePhysPresenceWindow: call to queryMasterProcChipTargetHandle " + "failed. err_plid=0x%X, err_rc=0x%X", + ERRL_GETPLID_SAFE(err), + ERRL_GETRC_SAFE(err)); + + err->collectTrace(SECURE_COMP_NAME); + break; + } + + // Get "window open" LED/Pin + led_window_open = PCA9551_LED0 << gpioInfo.windowOpenPin; + + + // Open The Window + led_data=0; // For INPUT register read-back + err = gpioPca9551SetLed(mproc, + static_cast<GPIO::PCA9551_LEDS_t> + (led_window_open), + PCA9551_OUTPUT_LOW, + led_data); + + // Verify that the "window open" LED is set + // LEDs/PINs represent "WINDOW_OPEN_N" and "PHYS_PRESENCE_N" so need + // to invert their values to get their true meaning + is_window_open = ! (led_window_open & led_data); + if (is_window_open == true) + { + SB_INF("handlePhysPresenceWindow: Window is Opened: " + "led_window_open=0x%X, led_data=0x%.2X", + led_window_open, led_data); + } + else + { + SB_ERR("handlePhysPresenceWindow: ERROR: Window is NOT Opened: " + "led_window_open=0x%X, led_data=0x%.2X", + led_window_open, led_data); + + /*@ + * @errortype + * @reasoncode RC_PHYS_PRES_WINDOW_NOT_OPENED + * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE + * @moduleid MOD_PHYS_PRES_OPEN_WINDOW + * @userdata1 HUID of Master Processor Target + * @userdata2[0:31] LED Data from PCA9551 + * @userdata2[32:63] LED Windoow Open LED (aka PIN) + * @devdesc Attempt to open physical presence window + * did not close the window + * @custdesc A problem occurred during the IPL + * of the system. + */ + err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + MOD_PHYS_PRES_OPEN_WINDOW, + RC_PHYS_PRES_WINDOW_NOT_OPENED, + get_huid(mproc), + TWO_UINT32_TO_UINT64( + led_data, + led_window_open), + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + + err->collectTrace( SECURE_COMP_NAME ); + break; + } + + // Close request to open the window and sync attributes + sys->setAttr<ATTR_PHYS_PRES_REQUEST_OPEN_WINDOW>(0x00); + + if(INITSERVICE::spBaseServicesEnabled()) + { + // Sync all attributes to FSP before powering off + err = TARGETING::AttrRP::syncAllAttributesToFsp(); + if( err ) + { + // Failed to sync all attributes to FSP; this is not + // necessarily fatal. The power off will continue, + // but this issue will be logged. + SB_ERR("handlePhysPresenceWindow: Error syncing " + "attributes to FSP, RC=0x%04X, PLID=0x%08X", + ERRL_GETRC_SAFE(err), + ERRL_GETPLID_SAFE(err)); + errlCommit(err,SECURE_COMP_ID ); + } + } + + // Alert the users that the system will power off +#ifdef CONFIG_CONSOLE + CONSOLE::displayf(SECURE_COMP_NAME, "Opened Physical Presence Detection Window\n"); + CONSOLE::displayf(SECURE_COMP_NAME, "System Will Power Off and Wait For Manual Power On\n"); + CONSOLE::flush(); +#endif + + // Power Off the System +#ifdef CONFIG_BMC_IPMI + // Initiate a graceful power off + SB_INF("handlePhysPresenceWindow: Opened Physical Presence Detection Window. " + "System Will Power Off and Wait For Manual Power On. " + "Requesting power off"); + INITSERVICE::requestPowerOff(); +#else //non-IPMI + SB_INF("handlePhysPresenceWindow: Opened Physical Presence Detection Window. " + "Calling INITSERVICE::doShutdown() with " + "RC_PHYS_PRES_WINDOW_OPENED_SHUTDOWN = 0x%08X", + RC_PHYS_PRES_WINDOW_OPENED_SHUTDOWN); + INITSERVICE::doShutdown(RC_PHYS_PRES_WINDOW_OPENED_SHUTDOWN); +#endif + + + } while (0); + + SB_EXIT("handlePhysPresenceWindow: err_rc=0x%X", + ERRL_GETRC_SAFE(err)); + + return err; +} + +} // namespace SECUREBOOT diff --git a/src/usr/secureboot/ext/service_ext.C b/src/usr/secureboot/ext/service_ext.C index 1f8595a71..b9050af43 100644 --- a/src/usr/secureboot/ext/service_ext.C +++ b/src/usr/secureboot/ext/service_ext.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -36,7 +36,6 @@ #include <fapi2/plat_hwp_invoker.H> #include <p9_update_security_ctrl.H> -#include <config.h> namespace SECUREBOOT { @@ -69,7 +68,7 @@ void lockAbusSecMailboxes() ERRORLOG::ErrlUserDetailsTarget(*l_pProc).addToLog(l_errl); ERRORLOG::errlCommit(l_errl, SECURE_COMP_ID); - /* + /*@ * @errortype * @reasoncode RC_LOCK_MAILBOXES_FAILED * @moduleid MOD_LOCK_ABUS_SEC_MAILBOXES diff --git a/src/usr/secureboot/node_comm/README.md b/src/usr/secureboot/node_comm/README.md new file mode 100644 index 000000000..0def94860 --- /dev/null +++ b/src/usr/secureboot/node_comm/README.md @@ -0,0 +1,97 @@ +# **'node\_comm'** Secureboot Services in Hostboot +This directory implements the Hostboot functions necessary to create a + secure channel between nodes using a series of a-bus mailbox registers + enabled after a-bus training but before the iovalid drop. +This secure channel is used in a multi-node evironment for nodes to exchange + cryptographic material that can later be used for internode authentication + higher up the firmware stack. + +## Key Points +* This code implements device driver-like functionality to send messages + across the a-bus connection from one node to another + * This functionality is based on a-bus mailbox registers which are used to + detect incoming messages, retrieve data, and send data messages to/from + specific nodes +* This code establishes a master node which then starts the process of exchanging + information with each of the other slave nodes +* The files are built into libnode_comm.so +* This module implements the interfaces defined in + [nodecommif.H](../../../include/usr/secureboot/nodecommif.H) +* NOTE: The P9 code references "OBUS" a lot which is the specific processor + chiplet that the a-bus messaging system runs through. + +## Algorithm +* First, each node does the following: + * Determine the nodes in the system + * Determine the master processor of this node + * Determine the a-bus connection to its master processor peers on the + other nodes + +* ***The Master Processor on Master Node*** does the following + (see node_comm_exchange.C's nodeCommAbusExchangeMaster()): + * **Loop 1:** Exchange SBID/nonces between Master and each of the Slave Nodes + * Generate SBID/nonce and send to slave node + * Look for return SBID/nonce from the slave + * **Loop 2:** Master Node requests quotes from each Slave Node + * Generate and send Quote Request to a slave + * Look for Quote Response from the slave node + * Process the Quote Response that was returned from the slave node + * NOTE: + * Nonces are encoded 64-bytes of data: part random number, part node ID + * Quotes are a form of attestation between two TPMs on the system. See + TrustedComputingGroup.org's Trusted Platform Module Library Specification, + Family "2.0" for more details. + +* ***The Master Processor on each Slave Node*** does the following + (see node_comm_exchange.C's nodeCommAbusExchangeSlave()): + + * Wait for SBID/nonce from the master node + * Send a SBID/nonce back to the master node + * Wait for Quote Request from master node + * Generate the Quote Response + * Send the Quote Response to the master node + + +* NOTE: Generating the SBID/Nonces, Quote Requests, and Quote Responses above + all require interacting with the TPMs on the different nodes in specific + ways + * The devil is truly in the details, and the details can be found in the + supporting functions of node_comm_exchange.C +* NOTE: In the event that one node fails in this process there will be an + attempt to poison the TPMs on that node and move on in most cases. This is + to prevent an entire system from failing to boot with one bad node. + +## Files + +* __makefile__ + * Standard Hostboot makefile + +* __node_comm.C, node_comm.H__ + * The majority of the sub-functions used to implement the algorithm are + defined and implemented here, including the a-bus mapping details between + the nodes + +* __node_comm_dd.C, node_comm_dd.H__ + * Defines and implements the "NODECOMM" device driver that interacts directly + with the a-bus mailbox registers + +* __node_comm_exchange.C__ + * The core of this module - the primary function nodeCommAbusExchange() + is implemented here and shows the high-level data flow between the nodes + * The procedure for the master node is defined in nodeCommAbusExchangeMaster() + * The procedure for the slave nodes is defiend in nodeCommAbusExchangeSlave() + * The interactions with the TPM - generating and logging SBID/Nonces, Quote + Requests, Quote Responses - are all in this file + +* __node_comm_test.C__ + * Implements the proof-of-concept "nodeCommXbus2ProcTest" test to transfer + data across the x-bus between processors using a similar method to the a-bus + mechanism + +* __node_comm_transfer.C, node_comm_transfer.H__ + * Defines and implements the different types of messages that can be sent + between the nodes, including the actual send and receive functions + +* __[README.md](./README.md)__ + * This file + diff --git a/src/usr/secureboot/node_comm/node_comm.H b/src/usr/secureboot/node_comm/node_comm.H index e44893683..227d53ac2 100644 --- a/src/usr/secureboot/node_comm/node_comm.H +++ b/src/usr/secureboot/node_comm/node_comm.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -28,11 +28,10 @@ // ---------------------------------------------- // Includes // ---------------------------------------------- -#include <config.h> #include <time.h> #include <devicefw/userif.H> #include <trace/interface.H> -#include <scom/centaurScomCache.H> // for TRACE_ERR_FMT, TRACE_ERR_ARGS +#include <errl/errlentry.H> // for TRACE_ERR_FMT, TRACE_ERR_ARGS #include <secureboot/nodecommif.H> #include "../trusted/trustedboot.H" #include <secureboot/trustedbootif.H> diff --git a/src/usr/secureboot/node_comm/node_comm_dd.H b/src/usr/secureboot/node_comm/node_comm_dd.H index 212ab24df..f8b057bcd 100644 --- a/src/usr/secureboot/node_comm/node_comm_dd.H +++ b/src/usr/secureboot/node_comm/node_comm_dd.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -28,7 +28,6 @@ // ---------------------------------------------- // Includes // ---------------------------------------------- -#include <config.h> #include <devicefw/userif.H> #include <secureboot/nodecommif.H> diff --git a/src/usr/secureboot/node_comm/node_comm_exchange.C b/src/usr/secureboot/node_comm/node_comm_exchange.C index ff8ff8a31..ccbd973d3 100644 --- a/src/usr/secureboot/node_comm/node_comm_exchange.C +++ b/src/usr/secureboot/node_comm/node_comm_exchange.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -51,7 +51,6 @@ #include <targeting/targplatutil.H> #include <sys/internode.h> #include <util/misc.H> -#include <config.h> #include "node_comm.H" #include "node_comm_transfer.H" @@ -133,6 +132,7 @@ errlHndl_t nodeCommAbusGetRandom(uint64_t & o_nonce) { errlHndl_t err = nullptr; o_nonce = NODE_COMM_DEFAULT_NONCE; +#ifdef CONFIG_TPMDD Target* tpm_tgt = nullptr; TRACUCOMP(g_trac_nc,ENTER_MRK"nodeCommAbusGetRandom:"); @@ -144,9 +144,7 @@ errlHndl_t nodeCommAbusGetRandom(uint64_t & o_nonce) // This function call requires the CONFIG check for compilation purposes, // but no extra error handling is needed as it should not have gotten this // far if CONFIG_TPMDD wasn't set -#ifdef CONFIG_TPMDD TRUSTEDBOOT::getPrimaryTpm(tpm_tgt); -#endif HwasState hwasState{}; if(tpm_tgt) { @@ -192,11 +190,9 @@ errlHndl_t nodeCommAbusGetRandom(uint64_t & o_nonce) // This function call requires the CONFIG check for compilation purposes, // but no extra error handling is needed as it should not have gotten this // far if CONFIG_TPMDD wasn't set -#ifdef CONFIG_TPMDD err = TRUSTEDBOOT::GetRandom(tpm_tgt, sizeof(o_nonce), reinterpret_cast<uint8_t*>(&o_nonce)); -#endif if (err) { // Reset just to make sure above call didn't change it @@ -208,18 +204,30 @@ errlHndl_t nodeCommAbusGetRandom(uint64_t & o_nonce) get_huid(tpm_tgt), TRACE_ERR_ARGS(err), o_nonce); - // err commited outside of do-while loop below - // break to be safe in case code gets added later break; } } while( 0 ); - if (err) + if(err) { - err->collectTrace(TRBOOT_COMP_NAME); - err->collectTrace(NODECOMM_TRACE_NAME); + if(!TRUSTEDBOOT::isTpmRequired()) + { + TRACFCOMP(g_trac_nc,ERR_MRK"nodeCommAbusGetRandom: Error occurred; " + "RC: 0x%.04X; PLID: 0x%.08X. TPM Required policy is off; " + "deleting the error and trying to continue.", + err->reasonCode(), + err->plid()); + // TPM is not required - do not return the error + delete err; + err = nullptr; + } + else + { + err->collectTrace(TRBOOT_COMP_NAME); + err->collectTrace(NODECOMM_TRACE_NAME); + } } TRACFCOMP(g_trac_nc,EXIT_MRK"nodeCommAbusGetRandom: " @@ -228,6 +236,7 @@ errlHndl_t nodeCommAbusGetRandom(uint64_t & o_nonce) o_nonce, get_huid(tpm_tgt), TRACE_ERR_ARGS(err)); +#endif return err; } // end of nodeCommAbusGetRandom @@ -618,17 +627,19 @@ errlHndl_t nodeCommGenSlaveQuoteResponse(const MasterQuoteRequestBlob* const i_r { l_poisonTpmErr->plid(l_errl->plid()); } - errlCommit(l_poisonTpmErr, SECURE_COMP_ID); - } - } - - if(l_errl) - { - if(!l_tpmRequired) - { - // TPM is not required, so no need to propagate the error up and - // fail the boot. - errlCommit(l_errl, SECURE_COMP_ID); + if(l_tpmRequired) + { + errlCommit(l_poisonTpmErr, SECURE_COMP_ID); + } + else + { + TRACFCOMP(g_trac_nc,ERR_MRK"nodeCommGenSlaveQuoteResponse: " + "Could not poison TPMs. Errl PLID: 0x%.08X " + "Deleting the error log and continuing anyway.", + l_poisonTpmErr->plid()); + delete l_poisonTpmErr; + l_poisonTpmErr = nullptr; + } } } @@ -721,14 +732,19 @@ errlHndl_t nodeCommGenMasterQuoteRequest(MasterQuoteRequestBlob* const o_request { l_poisonTpmErr->plid(l_errl->plid()); } - errlCommit(l_poisonTpmErr, SECURE_COMP_ID); - } - - if(!l_tpmRequired) - { - // TPM is not required, so no need to propagate the error up and - // fail the boot. - errlCommit(l_errl, SECURE_COMP_ID); + if(l_tpmRequired) + { + errlCommit(l_poisonTpmErr, SECURE_COMP_ID); + } + else + { + TRACFCOMP(g_trac_nc,ERR_MRK"nodeCommGenMasterQuoteRequest: " + "Could not poison TPMs. Errl PLID: 0x%.08X. " + "Deleting the error log and continuing anyway.", + l_poisonTpmErr->plid()); + delete l_poisonTpmErr; + l_poisonTpmErr = nullptr; + } } } @@ -814,13 +830,19 @@ errlHndl_t nodeCommProcessSlaveQuote(uint8_t* const i_slaveQuote, { l_poisonTpmErr->plid(l_errl->plid()); } - errlCommit(l_poisonTpmErr, SECURE_COMP_ID); - } - - if(!TRUSTEDBOOT::isTpmRequired()) - { - // TPM is not required - do not propagate the error - errlCommit(l_errl, SECURE_COMP_ID); + if(TRUSTEDBOOT::isTpmRequired()) + { + errlCommit(l_poisonTpmErr, SECURE_COMP_ID); + } + else + { + TRACFCOMP(g_trac_nc, ERR_MRK"nodeCommProcessSlaveQuote: " + "Could not poison TPMs. Errl PLID: 0x%.08X. " + "Deleting the error log and continuing.", + l_poisonTpmErr->plid()); + delete l_poisonTpmErr; + l_poisonTpmErr = nullptr; + } } } @@ -1738,9 +1760,24 @@ errlHndl_t nodeCommAbusExchange(void) if (err) { - err->collectTrace(SECURE_COMP_NAME); - err->collectTrace(NODECOMM_TRACE_NAME); - err->collectTrace(TRBOOT_COMP_NAME); + if(!TRUSTEDBOOT::isTpmRequired()) + { + TRACFCOMP(g_trac_nc,EXIT_MRK"nodeCommAbusExchange:An error occurred" + " during secure node communication, but the TPM required " + "policy is not set, so the error will not be propagated." + " Original error RC: 0x%.04X; PLID: 0x%.08X." + " Deleting the error log and continuing.", + err->reasonCode(), + err->plid()); + delete err; + err = nullptr; + } + else + { + err->collectTrace(SECURE_COMP_NAME); + err->collectTrace(NODECOMM_TRACE_NAME); + err->collectTrace(TRBOOT_COMP_NAME); + } } if (l_phys_path_str != nullptr) diff --git a/src/usr/secureboot/node_comm/node_comm_transfer.C b/src/usr/secureboot/node_comm/node_comm_transfer.C index b7afb02ef..4b82688f0 100644 --- a/src/usr/secureboot/node_comm/node_comm_transfer.C +++ b/src/usr/secureboot/node_comm/node_comm_transfer.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -26,11 +26,10 @@ // ---------------------------------------------- // Includes // ---------------------------------------------- -#include <config.h> #include <time.h> #include <devicefw/userif.H> #include <trace/interface.H> -#include <scom/centaurScomCache.H> // for TRACE_ERR_FMT, TRACE_ERR_ARGS +#include <errl/errlentry.H> // for TRACE_ERR_FMT, TRACE_ERR_ARGS #include <targeting/targplatutil.H> #include <secureboot/nodecommif.H> #include <secureboot/secure_reasoncodes.H> diff --git a/src/usr/secureboot/node_comm/node_comm_transfer.H b/src/usr/secureboot/node_comm/node_comm_transfer.H index 201661447..93f45a512 100644 --- a/src/usr/secureboot/node_comm/node_comm_transfer.H +++ b/src/usr/secureboot/node_comm/node_comm_transfer.H @@ -28,7 +28,6 @@ // ---------------------------------------------- // Includes // ---------------------------------------------- -#include <config.h> #include "node_comm.H" #include <map> diff --git a/src/usr/secureboot/runtime/README.md b/src/usr/secureboot/runtime/README.md new file mode 100644 index 000000000..552ca9b6f --- /dev/null +++ b/src/usr/secureboot/runtime/README.md @@ -0,0 +1,21 @@ +# **'runtime'** Secureboot Services in Hostboot +This directory implements a small, select subset of core secureboot-related + functionality that Hostboot provides at runtime, ie as part of + Hostboot runtime services. + +## Files + +* __makefile__ + * Standard Hostboot makefile + +* __[README.md](./README.md)__ + * This file + +* __rt_secureboot.C__ + * This file implements several secureboot functions for hostboot runtime + services + +## sub-directories +* __test__ + * Standard Hostboot test directory that implements CXX Unit Tests + diff --git a/src/usr/secureboot/runtime/rt_secureboot.C b/src/usr/secureboot/runtime/rt_secureboot.C index 7c297be9e..c1608fa73 100644 --- a/src/usr/secureboot/runtime/rt_secureboot.C +++ b/src/usr/secureboot/runtime/rt_secureboot.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -29,14 +29,13 @@ */ #include <runtime/interface.h> -#include <config.h> #include "common/securetrace.H" #include <secureboot/service.H> #include <secureboot/secure_reasoncodes.H> #include <errl/errlmanager.H> -#include <runtime/rt_targeting.H> +#include <targeting/runtime/rt_targeting.H> #include <targeting/common/commontargeting.H> #include <targeting/common/targetservice.H> #include <devicefw/userif.H> diff --git a/src/usr/secureboot/runtime/test/testsecureboot_rt.H b/src/usr/secureboot/runtime/test/testsecureboot_rt.H index 380b9eb0c..5a690d3fa 100644 --- a/src/usr/secureboot/runtime/test/testsecureboot_rt.H +++ b/src/usr/secureboot/runtime/test/testsecureboot_rt.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -33,9 +33,8 @@ #include <cxxtest/TestSuite.H> #include <runtime/interface.h> -#include <config.h> -#include <runtime/rt_targeting.H> +#include <targeting/runtime/rt_targeting.H> #include <errl/errlmanager.H> #include <devicefw/userif.H> diff --git a/src/usr/secureboot/smf/test/testsmf.H b/src/usr/secureboot/smf/test/testsmf.H index 81a50a6e0..fb3993724 100644 --- a/src/usr/secureboot/smf/test/testsmf.H +++ b/src/usr/secureboot/smf/test/testsmf.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -29,6 +29,7 @@ #include <errl/errlmanager.H> #include <targeting/common/target.H> #include <targeting/common/targetservice.H> +#include <targeting/common/utilFilter.H> #include <hbotcompid.H> #include <secureboot/smf.H> #include <secureboot/secure_reasoncodes.H> @@ -346,9 +347,14 @@ public: break; } - if(l_smfBarSize != DISTRIBUTE_EXACT_SMF_AMT) + // Memory is distributed across processors so need to divide the + // expected results by the number of processors + TARGETING::TargetHandleList l_procList; + TARGETING::getAllChips(l_procList, TARGETING::TYPE_PROC, true); + + if(l_smfBarSize != (DISTRIBUTE_EXACT_SMF_AMT/l_procList.size())) { - TS_FAIL("testDistributeExactAmt: Unexpected amount of memory allocated. Expected: 0x%x, actual 0x%x", DISTRIBUTE_EXACT_SMF_AMT, l_smfBarSize); + TS_FAIL("testDistributeExactAmt: Unexpected amount of memory allocated. Expected: 0x%x, actual 0x%x", (DISTRIBUTE_EXACT_SMF_AMT/l_procList.size()), l_smfBarSize); } } while(0); @@ -400,9 +406,14 @@ public: break; } - if(l_smfBarSize != DISTRIBUTE_EXACT_SMF_AMT) + // Memory is distributed across processors so need to divide the + // expected results by the number of processors + TARGETING::TargetHandleList l_procList; + TARGETING::getAllChips(l_procList, TARGETING::TYPE_PROC, true); + + if(l_smfBarSize != (DISTRIBUTE_EXACT_SMF_AMT/l_procList.size())) { - TS_FAIL("testDistributeNotExactAmt: Unexpected amount of memory allocated. Expected: 0x%x, actual 0x%x", DISTRIBUTE_EXACT_SMF_AMT, l_smfBarSize); + TS_FAIL("testDistributeNotExactAmt: Unexpected amount of memory allocated. Expected: 0x%x, actual 0x%x", (DISTRIBUTE_EXACT_SMF_AMT/l_procList.size()), l_smfBarSize); } } while(0); diff --git a/src/usr/secureboot/trusted/README.md b/src/usr/secureboot/trusted/README.md new file mode 100644 index 000000000..effe75f44 --- /dev/null +++ b/src/usr/secureboot/trusted/README.md @@ -0,0 +1,74 @@ +# **'trusted'** Secureboot Services in Hostboot +This directory implements the 'trusted' boot functionality that Hostboot + provides. +It primarily does this by measuring and storing firmware images and system + data into the system's TPMs (Trusted Platform Modules). + +## Key Points +* This code measures specific information on the system, including different + firmware images that are loaded onto the system by hostboot +* These mesasurements, along with other system data, are stored in the TPMs + on the system +* This code also determines which TPMs exist on the system, if they are + functional, and initializes them +* To directly talk to the TPMs this code uses the TPM Device Driver, which + is built on top of the I2C Device Driver: + * [src/usr/i2c/tmpdd.C](../../i2c/tpmdd.C) + * [src/usr/i2c/tpmdd.H](../../i2c/tpmdd.H) + +* The **libsecureboot_trusted.so** module created here is available in + Hostboot's extended image +* However, the code in the 'base' sub-directory is built into + libsecureboot_base.so and is available in Hostboot's base image +* This module implements the interfaces defined in + [trustedbootif.H](../../../include/usr/secureboot/trustedbootif.H) + +## Files + +* __makefile__ + * Standard Hostboot makefile + +* __[README.md](./README.md)__ + * This file + +* __tpmLogMgr.C, tpmLogMgr.H__ + * Defines and implements functions around the TPM Event Log, including + adding new events, extending the log to the TPM, and moving the log to + different memory locations + +* __trustedTypes.C, trustedTypes.H__ + * Defines different structures and methods for sending and receiving data + to and from the TPM + +* __trustedboot.C, trustedboot.H__ + * Defines and implements the majority of the functions that interact with the + TPMs + * Implements the majority of the functions that verify and initialize the TPMs + +* __trustedbootCmds.C, trustedbootCmds.H__ + * Defines and implements commands sent to the TPM and then processes (aka + marshall and unmarshall) the data appropriately + +* __trustedbootUtils.C, trustedbootUtils.H__ + * Defines and implements a few utility functions like a wrapper to the TPM + Device Driver and creating trustedboot error logs. + + +## sub-directories +* __base__ + * These files create a message queue to reserve operations that can be + implemented once the full Hostboot extended code, including + libsecureboot_trusted.so, is available to process them + * These files also take the basic operations that the Hostboot base code + needs and sends them to the message queue + * __trustedboot_base.C__ + * Implements early trustedboot/TPM calls be calling into a message + queue so that they can be processed later + + * __trustedbootMsg.C, trustedbootMsg.H__ + * Defines and implements the message queue so that commands can be + processed later when libsecureboot_trusted.so is available + +* __test__ + * Standard Hostboot test directory that implements CXX Unit Tests + diff --git a/src/usr/secureboot/trusted/base/trustedboot_base.C b/src/usr/secureboot/trusted/base/trustedboot_base.C index 2e5182d2f..eb889131c 100644 --- a/src/usr/secureboot/trusted/base/trustedboot_base.C +++ b/src/usr/secureboot/trusted/base/trustedboot_base.C @@ -45,7 +45,6 @@ #include <secureboot/header.H> #include <secureboot/containerheader.H> #include <pnor/pnorif.H> -#include <config.h> #include "../trustedboot.H" #include "../trustedbootCmds.H" #include "../trustedbootUtils.H" @@ -1165,7 +1164,7 @@ errlHndl_t expandTpmLog(TpmTarget* i_target) int l_rc = msg_sendrecv(systemData.msgQ, l_msg->iv_msg); if(l_rc) { - /** + /*@ * @errortype ERRL_SEV_UNRECOVERABLE * @moduleid MOD_EXPAND_TPM_LOG * @reasoncode RC_SENDRECV_FAIL diff --git a/src/usr/secureboot/trusted/test/trustedbootTest.H b/src/usr/secureboot/trusted/test/trustedbootTest.H index cbf221e57..50564f12d 100755 --- a/src/usr/secureboot/trusted/test/trustedbootTest.H +++ b/src/usr/secureboot/trusted/test/trustedbootTest.H @@ -45,7 +45,6 @@ #include "../trustedboot.H" #include "../trustedbootCmds.H" #include "../tpmLogMgr.H" -#include <config.h> using namespace TRUSTEDBOOT; diff --git a/src/usr/secureboot/trusted/trustedboot.C b/src/usr/secureboot/trusted/trustedboot.C index 6046a76df..d0ec76030 100644 --- a/src/usr/secureboot/trusted/trustedboot.C +++ b/src/usr/secureboot/trusted/trustedboot.C @@ -53,7 +53,6 @@ #ifdef CONFIG_BMC_IPMI #include <ipmi/ipmisensor.H> #endif -#include <config.h> #include <devicefw/driverif.H> #include <i2c/tpmddif.H> #include "trustedboot.H" diff --git a/src/usr/secureboot/trusted/trustedbootCmds.C b/src/usr/secureboot/trusted/trustedbootCmds.C index 604757b7a..fe2956929 100644 --- a/src/usr/secureboot/trusted/trustedbootCmds.C +++ b/src/usr/secureboot/trusted/trustedbootCmds.C @@ -37,7 +37,6 @@ // ---------------------------------------------- #include <string.h> #include <stdlib.h> -#include <config.h> #ifdef __HOSTBOOT_MODULE #include <secureboot/trustedboot_reasoncodes.H> diff --git a/src/usr/targeting/attrPlatOverride.C b/src/usr/targeting/attrPlatOverride.C index 7e1025d40..46f50e566 100644 --- a/src/usr/targeting/attrPlatOverride.C +++ b/src/usr/targeting/attrPlatOverride.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014,2018 */ +/* Contributors Listed Below - COPYRIGHT 2014,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -28,6 +28,7 @@ #include <targeting/common/targreasoncodes.H> #include <errl/errlmanager.H> #include <secureboot/service.H> +#include <console/consoleif.H> namespace TARGETING { @@ -291,6 +292,103 @@ errlHndl_t getAttrOverrides(PNOR::SectionInfo_t &i_sectionInfo, break; } + // Print out the contents of all attribute tanks + for( size_t i=0; i<AttributeTank::TANK_LAYER_LAST; i++ ) + { + if( l_pOverTanks[i]->attributesExist() ) + { + /* Display output like this + + **Found 3 attribute overrides in Tank TARG(2) + - type:n1:p2:c3 + ATTR 12345678 = 0011223344 + ATTR 10102020 = 223344 + - type:nall:pall:call + ATTR 02395414 = 07 + */ + + CONSOLE::displayf("TARG","**Found %d attribute overrides in Tank %s(%d)", + l_pOverTanks[i]->size(), + AttributeTank::layerToString( + static_cast<AttributeTank::TankLayer>(i)), + i); + + AttributeTank::AttributeHeader last_hdr; + std::list<AttributeTank::Attribute*> l_attrList; + l_pOverTanks[i]->getAllAttributes(l_attrList); + for( auto l_attr : l_attrList ) + { + constexpr size_t MAX_DISPLAY = 100; + char outstr[MAX_DISPLAY]; + outstr[0] = '\0'; + + // Only print out the target string once if possible + AttributeTank::AttributeHeader hdr = l_attr->getHeader(); + if( (hdr.iv_targetType != last_hdr.iv_targetType) + || (hdr.iv_node != last_hdr.iv_node) + || (hdr.iv_pos != last_hdr.iv_pos) + || (hdr.iv_unitPos != last_hdr.iv_unitPos) ) + { + EntityPath epath; //func should be static but isn't + sprintf( outstr, "- %s", + epath.pathElementTypeAsString( + static_cast<TARGETING::TYPE>(hdr.iv_targetType)) ); + if( AttributeTank::ATTR_NODE_NA == hdr.iv_node ) + { + strcat( outstr, ":nall" ); + } + else + { + char tmpstr[10]={}; + sprintf( tmpstr, ":n%d", hdr.iv_node ); + strcat( outstr, tmpstr ); + } + if( AttributeTank::ATTR_POS_NA == hdr.iv_pos ) + { + strcat( outstr, ":pall" ); + } + else + { + char tmpstr[10]={}; + sprintf( tmpstr, ":p%d", hdr.iv_pos ); + strcat( outstr, tmpstr ); + } + if( AttributeTank::ATTR_UNIT_POS_NA == hdr.iv_unitPos ) + { + strcat( outstr, ":call" ); + } + else + { + char tmpstr[10]={}; + sprintf( tmpstr, ":c%d", hdr.iv_unitPos ); + strcat( outstr, tmpstr ); + } + CONSOLE::displayf("TARG",outstr); + last_hdr = hdr; + } + + // Now print out the attribute values + sprintf( outstr, " ATTR %.8X [%d] = ", + hdr.iv_attrId, + hdr.iv_valSize ); + size_t max_data = (MAX_DISPLAY - strlen(outstr))/2 - 4; + const char* dataval = + reinterpret_cast<const char*>(l_attr->getValue()); + for( size_t s=0; s<hdr.iv_valSize && s<max_data; s++ ) + { + char datastr[4]={}; + sprintf( datastr, "%.2X", dataval[s] ); + strcat( outstr, datastr ); + } + if( hdr.iv_valSize > max_data ) + { + strcat( outstr, "..." ); + } + CONSOLE::displayf("TARG",outstr); + } + CONSOLE::flush(); + } + } } while(0); TRACFCOMP(g_trac_targeting,"attrPlatOverride::getAttrOverrides EXIT"); diff --git a/src/usr/targeting/attrrp.C b/src/usr/targeting/attrrp.C index 1f7c359d7..7f0782a39 100755 --- a/src/usr/targeting/attrrp.C +++ b/src/usr/targeting/attrrp.C @@ -51,7 +51,6 @@ #include <sys/misc.h> #include <fapi2/plat_attr_override_sync.H> #include <targeting/attrPlatOverride.H> -#include <config.h> #include <secureboot/service.H> #include <kernel/bltohbdatamgr.H> #include <bootloader/bootloaderif.H> diff --git a/src/usr/targeting/common/Targets.pm b/src/usr/targeting/common/Targets.pm index aa1e07f7d..c106ef0fc 100644 --- a/src/usr/targeting/common/Targets.pm +++ b/src/usr/targeting/common/Targets.pm @@ -22,6 +22,7 @@ # permissions and limitations under the License. # # IBM_PROLOG_END_TAG + package Targets; use strict; @@ -78,12 +79,18 @@ my %maxInstance = ( "NPU" => 1, "MC" => 2, "MI" => 4, + "MCC" => 8, + "OMI" => 16, + "OCMB_CHIP" => 16, + "MEM_PORT" => 16, + "DDIMM" => 16, "DMI" => 8, "OCC" => 1, "NV" => 6, "NX" => 1, "MEMBUF" => 8, "SMPGROUP" => 8, + "OMIC" => 6, ); sub new { @@ -94,6 +101,7 @@ sub new targeting => undef, enumerations => undef, MAX_MCS => 0, + master_proc => undef, UNIT_COUNTS => undef, huid_idx => undef, mru_idx => undef, @@ -223,9 +231,17 @@ sub printTarget return; } + my $target_TYPE = $self->getAttribute($target, "TYPE"); + + # Only allow OMI types with MCC parent + # OMIC_PARENT only exists on an OMI target with MCC parent + if ($target_TYPE eq "OMI" && !defined($target_ptr->{ATTRIBUTES}->{"OMIC_PARENT"}->{default})) + { + return; + } + print $fh "<targetInstance>\n"; my $target_id = $self->getAttribute($target, "PHYS_PATH"); - my $target_TYPE = $self->getAttribute($target, "TYPE"); $target_id = substr($target_id, 9); $target_id =~ s/\///g; $target_id =~ s/\-//g; @@ -545,6 +561,13 @@ sub buildHierarchy }, $b ); + push( + @{ + $self->{data}->{TARGETS}->{$source_target}->{CONNECTION} + ->{BUS_PARENT} + }, + $key + ); my %bus_entry; $bus_entry{SOURCE_TARGET} = $source_target; $bus_entry{DEST_TARGET} = $dest_target; @@ -643,9 +666,17 @@ sub buildAffinity my $tpm = -1; my $ucd = -1; my $bmc = -1; + my $mcc = -1; + my $omi = -1; + my $ocmb = -1; + my $mem_port = -1; + my $i2c_mux = -1; + my $dimm = -1; + my $pmic = -1; my $sys_phys = ""; my $node_phys = ""; my $node_aff = ""; + my $proc_fapi = ""; my $sys_pos = 0; # There is always a single system target my $mcbist = -1; my $num_mc = 0 ; @@ -776,6 +807,64 @@ sub buildAffinity $self->deleteAttribute($target, "POSITION"); $self->deleteAttribute($target, "FRU_ID"); } + elsif ($type eq "MCC") + { + $mcc++; + + # For a given proc, there are 2 MCs, 4 MIs, 8 MCCs, and 16 OMIs + # To get the corresponding proc, MC, or MI number for a given MCC + # divide the MCC number by the number of MCCs per unit, then mod 2 + # to get the relative path in terms of 0 or 1 + my $numOfMccsPerProc = $maxInstance{$type}; + my $numOfMccsPerMc = 4; + my $numOfMccsPerMi = 2; + my $proc_num = ($mcc / $numOfMccsPerProc) % 2; + my $mc_num = ($mcc / $numOfMccsPerMc) % 2; + my $mi_num = ($mcc / $numOfMccsPerMi) % 2; + my $mcc_num = $mcc % 2; + my $path = "/proc-$proc_num/mc-$mc_num/mi-$mi_num/mcc-$mcc_num"; + my $mcc_aff = $node_aff . $path; + my $mcc_phys = $node_phys . $path; + $self->setAttribute($target, "AFFINITY_PATH", $mcc_aff); + $self->setAttribute($target, "PHYS_PATH", $mcc_phys); + + $self->setAttribute($target, "REL_POS", $mcc_num); + my $pos = $self->getAttribute($target, "CHIP_UNIT"); + my $fapi_pos = $pos + $numOfMccsPerProc * $proc_fapi; + $self->setAttribute($target, "FAPI_POS", $fapi_pos); + $self->setAttribute($target, "ORDINAL_ID", $mcc); + } + elsif ($type eq "OMI") + { + # We only want OMIs with MCC parent, skip over the ones with OMIC parent + my $parent = $self->getTargetParent($target); + my $parent_type = $self->getType($parent); + if ($parent_type eq "MCC") + { + $omi++; + + # Same logic for MCC, but for OMI instead + my $numOfOmisPerProc = $maxInstance{$type}; + my $numOfOmisPerMc = 8; + my $numOfOmisPerMi = 4; + my $numOfOmisPerMcc = 2; + my $proc_num = ($omi / $numOfOmisPerProc) % 2; + my $mc_num = ($omi / $numOfOmisPerMc) % 2; + my $mi_num = ($omi / $numOfOmisPerMi) % 2; + my $mcc_num = ($omi / $numOfOmisPerMcc) % 2; + my $omi_num = $omi % 2; + my $path = "/proc-$proc_num/mc-$mc_num/mi-$mi_num/mcc-$mcc_num/omi-$omi_num"; + my $omi_aff = $node_aff . $path; + my $omi_phys = $node_phys . $path; + $self->setAttribute($target, "AFFINITY_PATH", $omi_aff); + $self->setAttribute($target, "PHYS_PATH", $omi_phys); + + my $pos = $self->getAttribute($target, "CHIP_UNIT"); + my $fapi_pos = $pos + $numOfOmisPerProc * $proc_fapi; + $self->setAttribute($target, "FAPI_POS", $fapi_pos); + $self->setAttribute($target, "ORDINAL_ID", $omi); + } + } elsif ($type eq "BMC") { $bmc++; @@ -801,7 +890,322 @@ sub buildAffinity my $ddrs = $self->findConnections($target,"DDR4",""); $self->processMcaDimms($ddrs, $sys_pos, $node_phys, $node, $proc); } + elsif ($type eq "OCMB_CHIP") + { + # Ocmbs are not in order, so we take the parent dimm's POSITION as + # our current ocmb number + # Ex. dimm19 = ocmb19 + my $parent = $self->getTargetParent($target); + $ocmb = $self->getAttribute($parent, "POSITION"); + $self->{targeting}{SYS}[0]{NODES}[$node]{OCMB_CHIPS}[$ocmb]{KEY} = $target; + $self->setHuid($target, $sys_pos, $node); + + my $ocmb_phys = $node_phys . "/ocmb_chip-$ocmb"; + + # Find the OMI bus connection to determine target values + my $proc_num = -1; + my $mc_num = -1; + my $mi_num = -1; + my $mcc_num = -1; + my $omi_num = -1; + my $conn = $self->findConnectionsByDirection($target, "OMI", "", 1); + + my $omi_chip_unit = -1; + if ($conn ne "") + { + foreach my $conn (@{$conn->{CONN}}) + { + my $source = $conn->{SOURCE}; + if ($source =~ /omic/i) + { + next; + } + my @targets = split(/\//, $source); + # Split the source into proc#, mc#, mi#, mcc#, omi# + # Source example: + # /sys-#/node-#/Pallid-#/proc_socket-#/Hopper-#/p9_axone/mc#/mi#/mcc#/omi# + foreach my $target (@targets) + { + $target =~ s/\D//g; + } + + # Splitting on "/" makes the first array index empty string + # so every value here is shifted over by 1 + # There are only ever two targets per parent in this case, + # so to get the relative positions for each target, we take + # mod two of the source value + $proc_num = $targets[4] % 2; + $mc_num = $targets[7] % 2; + $mi_num = $targets[8] % 2; + $mcc_num = $targets[9] % 2; + + # omi_num indicates the chip_unit of the corresponding omi + $omi_num = $targets[10]; + $omi_chip_unit = $omi_num; + $omi_num %= 2; + } + } + + my $ocmb_aff = $node_aff . "/proc-$proc_num/mc-$mc_num/mi-$mi_num/mcc-$mcc_num/omi-$omi_num/ocmb_chip-0"; + $self->setAttribute($target, "AFFINITY_PATH", $ocmb_aff); + $self->setAttribute($target, "PHYS_PATH", $ocmb_phys); + + # The standard fapi_pos calculation uses the relative position to + # the proc instead of omi_chip_unit. However, in this case, there is + # no direct way to get the relative position to the proc. The + # relationship between ocmb and omi is 1:1, so we take the chip unit + # of the corresponding omi as the relative position to the proc + my $fapi_pos = $omi_chip_unit + ($maxInstance{$type} * $proc_num); + $self->setAttribute($target, "FAPI_POS", $fapi_pos); + + my $ocmb_num = $fapi_pos; + # The norm for FAPI_NAME has a two digit number at the end + if ($fapi_pos < 10) + { + $ocmb_num = "0$fapi_pos"; + } + + $self->setAttribute($target, "MRU_ID", "0x00060000"); + $self->setAttribute($target, "POSITION", $ocmb); + + # chipunit:system:node:slot:position + $self->setAttribute($target, "FAPI_NAME", "ocmb:k0:n0:s0:p$ocmb_num"); + + $self->setAttribute($target, "REL_POS", "0"); + + my $fapi_name = "FAPI_I2C_CONTROL_INFO"; + my $master_path = "physical:sys-0/node-0/proc-$proc_num"; + $self->setAttributeField($target, $fapi_name, "i2cMasterPath", $master_path); + + my $eeprom_name = "EEPROM_VPD_PRIMARY_INFO"; + $self->setAttributeField($target, $eeprom_name, "i2cMasterPath", $master_path); + $self->setAttributeField($target, $eeprom_name, "chipCount", "0x01"); + } + elsif ($type eq "I2C_MUX") + { + $i2c_mux++; + + $self->{targeting}{SYS}[0]{NODES}[$node]{I2C_MUXS}[$i2c_mux]{KEY} = $target; + + # There exists 1 i2c_mux per MC, so 2 i2c_mux per proc + my $numOfMuxesPerProc = 2; + my $proc_num = ($i2c_mux / $numOfMuxesPerProc) % 2; + my $i2c_aff = $node_aff . "/proc-$proc_num/i2c_mux-$i2c_mux"; + $self->setAttribute($target, "AFFINITY_PATH", $i2c_aff); + + my $i2c_phys = $node_phys . "/i2c_mux-$i2c_mux"; + $self->setAttribute($target, "PHYS_PATH", $i2c_phys); + $self->setHuid($target, $sys_pos, $node); + + my $fapi_name = "FAPI_I2C_CONTROL_INFO"; + my $master_path = $node_phys . "/proc-$proc_num"; + $self->setAttributeField($target, $fapi_name, "i2cMasterPath", $master_path); + my $conn = $self->findConnectionsByDirection($target, "I2C", + "", 1); + if ($conn ne "") + { + # Get the i2c-master-omi which has the engine and port values + # The endpoint mux has the devAddr + foreach my $conn (@{$conn->{CONN}}) + { + my $source = $conn->{SOURCE}; + my $dest = $conn->{DEST}; + if ($self->getTargetParent($conn->{DEST}) eq $target) + { + $self->setAttributeField($target, $fapi_name, "engine", + $self->getAttribute($source, "I2C_ENGINE")); + $self->setAttributeField($target, $fapi_name, "port", + $self->getAttribute($source, "I2C_PORT")); + $self->setAttributeField($target, $fapi_name, "devAddr", + $self->getAttribute($dest, "I2C_ADDRESS")); + } + } + } + } + elsif ($type eq "MEM_PORT") + { + my $parent = $self->getTargetParent($target); + my $ocmb_num = $self->getAttribute($parent, "POSITION"); + my $ocmb_affinity = $self->getAttribute($parent, "AFFINITY_PATH"); + $self->setAttribute($target, "AFFINITY_PATH", "$ocmb_affinity/mem_port-0"); + my $ocmb_phys = $self->getAttribute($parent, "PHYS_PATH"); + $self->setAttribute($target, "PHYS_PATH", "$ocmb_phys/mem_port-0"); + $self->setHuid($target, $sys_pos, $node); + $self->deleteAttribute($target, "EXP_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_PORT"); + + $self->{targeting}{SYS}[0]{NODES}[$node]{OCMB_CHIPS}[$ocmb_num]{MEM_PORTS}[0]{KEY} = $target; + } + # Witherspoon has its own DIMM parsing mechanism so don't want to + # interfere with it + elsif ($type eq "DIMM" && $self->getTargetType($target) eq "lcard-dimm-ddimm") + { + # Dimms are not posted in order, so need to get the dimm's position + $dimm = $self->getAttribute($target, "POSITION"); + + # Find the OMI bus connection to determine target values + my $proc_num = -1; + my $mc_num = -1; + my $mi_num = -1; + my $mcc_num = -1; + my $omi_num = -1; + my $conn = $self->findConnectionsByDirection($target, "OMI", "", 1); + + my $omi_chip_unit = -1; + if ($conn ne "") + { + foreach my $conn (@{$conn->{CONN}}) + { + my $source = $conn->{SOURCE}; + my @targets = split(/\//, $source); + + if ($source =~ /omic/i) + { + next; + } + + # Split the source into proc#, mc#, mi#, mcc#, omi# + # Source example: + # /sys-#/node-#/Pallid-#/proc_socket-#/Hopper-#/p9_axone/mc#/mi#/mcc#/omi# + foreach my $target (@targets) + { + $target =~ s/\D//g; + } + + # Splitting on "/" makes the first array index empty string + # so every value here is shifted over by 1 + # There are only ever two targets per parent in this case, + # so to get the relative positions for each target, we take + # mod two of the source value + $proc_num = $targets[4] % 2; + $mc_num = $targets[7] % 2; + $mi_num = $targets[8] % 2; + $mcc_num = $targets[9] % 2; + $omi_num = $targets[10]; + + # omi_num indicates the chip_unit of the corresponding omi + $omi_chip_unit = $omi_num; + $omi_num %= 2; + } + } + + $self->{targeting}{SYS}[0]{NODES}[$node]{DIMMS}[$dimm]{KEY} = $target; + $self->setAttribute($target, "PHYS_PATH", $node_phys . "/dimm-$dimm"); + $self->setHuid($target, $sys_pos, $node); + + # The standard fapi_pos calculation uses the relative position to + # the proc instead of omi_chip_unit. However, in this case, there is + # no direct way to get the relative position to the proc. The + # relationship between dimm and omi is 1:1, so we take the chip unit + # of the corresponding omi as the relative position to the proc + my $fapi_pos = $omi_chip_unit + ($maxInstance{"DDIMM"} * $proc_num); + $self->setAttribute($target, "FAPI_POS", $fapi_pos); + $self->setAttribute($target, "ORDINAL_ID", $dimm); + $self->setAttribute($target, "REL_POS", 0); + $self->setAttribute($target, "VPD_REC_NUM", $dimm); + + my $dimm_num = $fapi_pos; + if ($fapi_pos < 10) + { + $dimm_num = "0$fapi_pos"; + } + # chipunit:slot:node:system:position + $self->setAttribute($target, "FAPI_NAME", "dimm:k0:n0:s0:p$dimm_num"); + + my $ocmb_num = 0; + my $mem_num = 0; + $dimm_num = 0; + my $dimm_aff = $node_aff . "/proc-$proc_num/mc-$mc_num/mi-$mi_num/mcc-$mcc_num/omi-$omi_num/ocmb_chip-$ocmb_num/mem_port-$mem_num/dimm-$dimm_num"; + $self->setAttribute($target, "AFFINITY_PATH", $dimm_aff); + + my $eeprom_name = "EEPROM_VPD_PRIMARY_INFO"; + $self->setAttributeField($target, $eeprom_name, "chipCount", "0x01"); + $self->setAttributeField($target, $eeprom_name, "i2cMasterPath", "physical:sys-0/node-0/proc-$proc_num"); + } + elsif ($type eq "PMIC") + { + # Pmics are not in order, so we take the parent dimm's + # POSITION * 4 as our current pmic number, adding one + # if it's a pmic1, two if it's a pmic2, three if it's a + # pmic3 + # Ex. on a pmic0, dimm19 = pmic76 + # Ex. on a pmic1, dimm19 = pmic77 + # Ex. on a pmic2, dimm19 = pmic78 + # Ex. on a pmic3, dimm19 = pmic79 + my $instance_name = $self->getInstanceName($target); + my $parent = $self->getTargetParent($target); + my $parent_fapi_pos = $self->getAttribute($parent, "FAPI_POS"); + my $parent_pos = $self->getAttribute($parent, "POSITION"); + my $position = $self->getAttribute($target, "POSITION"); + $pmic = ($parent_pos * 4) + $position; + + $self->{targeting}{SYS}[0]{NODES}[$node]{PMICS}[$pmic]{KEY} = $target; + $self->setAttribute($target, "PHYS_PATH", $node_phys . "/pmic-$pmic"); + $self->setAttribute($target, "ORDINAL_ID", $pmic); + $self->setAttribute($target, "REL_POS", $pmic % 2); + + # Same logic with the position, but with FAPI_POS instead + my $fapi_pos = ($parent_fapi_pos * 4) + $position; + $self->setAttribute($target, "FAPI_POS", $fapi_pos); + $self->setAttribute($target, "POSITION", $pmic); + $self->setHuid($target, $sys_pos, $node); + + my $pmic_num = $fapi_pos; + # The norm for FAPI_NAME has a two digit number at the end + if ($fapi_pos < 10) + { + $pmic_num = "0$fapi_pos"; + } + # chipunit:slot:node:system:position + $self->setAttribute($target, "FAPI_NAME", "pmic:k0:n0:s0:p$pmic_num"); + + # Find the OMI bus connection to determine target values + my $proc_num = -1; + my $mc_num = -1; + my $mi_num = -1; + my $mcc_num = -1; + my $omi_num = -1; + my $conn = $self->findConnectionsByDirection($self->getTargetParent($target), "OMI", "", 1); + if ($conn ne "") + { + foreach my $conn (@{$conn->{CONN}}) + { + my $source = $conn->{SOURCE}; + my @targets = split(/\//, $source); + # Split the source into proc#, mc#, mi#, mcc#, omi# + # Source example: + # /sys-#/node-#/Pallid-#/proc_socket-#/Hopper-#/p9_axone/mc#/mi#/mcc#/omi# + if ($source =~ /omic/i) + { + next; + } + + foreach my $target (@targets) + { + $target =~ s/\D//g; + } + # Splitting on "/" makes the first array index empty string + # so every value here is shifted over by 1 + # There are only ever two targets per parent in this case, + # so to get the relative positions for each target, we take + # mod two of the source value + $proc_num = $targets[4] % 2; + $mc_num = $targets[7] % 2; + $mi_num = $targets[8] % 2; + $mcc_num = $targets[9] % 2; + $omi_num = $targets[10] % 2; + } + } + + my $ocmb_num = 0; + $pmic_num %= 2; + my $pmic_aff = $node_aff . "/proc-$proc_num/mc-$mc_num/mi-$mi_num/mcc-$mcc_num/omi-$omi_num/ocmb_chip-$ocmb_num/pmic-$pmic_num"; + $self->setAttribute($target, "AFFINITY_PATH", $pmic_aff); + + my $fapi_name = "FAPI_I2C_CONTROL_INFO"; + $self->setAttributeField($target, $fapi_name, "i2cMasterPath", + "physical:sys-0/node-0/proc-$proc_num"); + } elsif ($type eq "PROC") { my $socket = $target; @@ -879,14 +1283,14 @@ sub buildAffinity $self->setAttribute($target, "POSITION", $proc); $self->setAttribute($target, "FABRIC_GROUP_ID", - $self->getAttribute($socket,"FABRIC_GROUP_ID")); + $self->getAttribute($socket,"FABRIC_GROUP_ID")); $self->setAttribute($target, "FABRIC_CHIP_ID", - $self->getAttribute($socket,"FABRIC_CHIP_ID")); + $self->getAttribute($socket,"FABRIC_CHIP_ID")); $self->setAttribute($target, "VPD_REC_NUM", $proc); - $self->setAttribute($target, "FAPI_POS", - $self->getAttribute($socket,"FABRIC_GROUP_ID") * - NUM_PROCS_PER_GROUP + - $self->getAttribute($socket,"FABRIC_CHIP_ID")); + $proc_fapi = $self->getAttribute($socket, "FABRIC_GROUP_ID") * + NUM_PROCS_PER_GROUP + + $self->getAttribute($socket, "FABRIC_CHIP_ID"); + $self->setAttribute($target, "FAPI_POS", $proc_fapi); # Both for FSP and BMC based systems, it's good enough # to look for processor with active LPC bus connected @@ -1026,6 +1430,11 @@ sub iterateOverChiplets my $tgt_ptr = $self->getTarget($target); my $tgt_type = $self->getType($target); + # Previous OBUS parent + my $prev_obus = -1; + # Subtract factor for OBUS_BRICK + my $brick_sub = -1; + my $target_children = $self->getTargetChildren($target); if ($target_children eq "") @@ -1120,13 +1529,27 @@ sub iterateOverChiplets #System XML has some sensor target as hidden children #of targets. We don't care for sensors in this function #So, we can avoid them with this conditional - if ($unit_type ne "PCI" && $unit_type ne "NA" && $unit_type ne "FSI" && $unit_type ne "PSI" && $unit_type ne "SYSREFCLKENDPT" && $unit_type ne "MFREFCLKENDPT") { + if ($unit_type eq "OBUS_BRICK") + { + # Check to see if this is on a new obus + # Current obus is the CHIP_UNIT of the parent obus + my $curr_obus = $self->getAttribute($target, + "CHIP_UNIT"); + if ($prev_obus ne $curr_obus) + { + my $brick_pos = $self->getAttribute($child, + "CHIP_UNIT"); + $brick_sub = $brick_pos; + $prev_obus = $curr_obus; + } + } #set common attrs for child - $self->setCommonAttrForChiplet($child, $sys, $node, $proc); + $self->setCommonAttrForChiplet($child, $sys, $node, $proc, + $prev_obus, $brick_sub); $self->iterateOverChiplets($child, $sys, $node, $proc); } } @@ -1156,6 +1579,8 @@ sub setCommonAttrForChiplet my $sys = shift; my $node = shift; my $proc = shift; + my $prev_obus = shift; + my $brick_sub = shift; my $tgt_ptr = $self->getTarget($target); my $tgt_type = $self->getType($target); @@ -1194,7 +1619,15 @@ sub setCommonAttrForChiplet } elsif ($tgt_type eq "OBUS_BRICK") { - $unit_pos = $pos%3; + # Relative position of OBUS_BRICK is just the difference between the + # current position and the position of the first obus_brick of the + # parent obus + # Ex: obus3 -> obus_brick9 + # -> obus_brick10 + # -> obus_brick11 + # Position of first obus_brick of parent obus = 9 + # Relative position of obus_brick11 = 11 - 9 = 2 + $unit_pos = $pos - $brick_sub; } elsif ($tgt_type eq "SMPGROUP") { @@ -1203,6 +1636,11 @@ sub setCommonAttrForChiplet $self->setAttribute($target, "INSTANCE_PATH", $target); $unit_pos = $pos%2; } + elsif ($tgt_type eq "OMIC") + { + # There are 3 OMICs per MC parent + $unit_pos = $pos % 3; + } my $parent_affinity = $self->getAttribute( $self->getTargetParent($target),"AFFINITY_PATH"); @@ -1394,6 +1832,7 @@ sub getPervasiveForUnit my $offset = 0; for my $obrick (0..$maxInstance{"OBUS_BRICK"}-1) { + #todo-RTC:209409-Handle Axone layout $offset += (($obrick%3 == 0) && ($obrick != 0)) ? 1 : 0; $unitToPervasive{"OBUS_BRICK$obrick"} = PERVASIVE_PARENT_OBUS_OFFSET + $offset; @@ -1412,6 +1851,7 @@ sub getPervasiveForUnit return $pervasive } + sub processMcaDimms { my $self = shift; @@ -1546,6 +1986,12 @@ sub processMc foreach my $dmi (@{ $self->getTargetChildren($mi) }) { + my $child_type = $self->getType($dmi); + if ($child_type ne "DMI") + { + next; + } + my $dmi_num = $self->getAttribute($dmi, "CHIP_UNIT"); my $membufnum = $proc * $self->{MAX_DMI} + $dmi_num; @@ -1572,7 +2018,7 @@ sub processMc my $parent_physical = $self->getAttribute($membuf, "PHYS_PATH"); $self->setAttribute($membuf,"FAPI_NAME", - $self->getFapiName($membuf_type, $node, $membufnum)); + $self->getFapiName($membuf_type, $node, $membufnum, $memCardOffset)); my $fapi_pos = (($node * $maxInstance{"PROC"}) + $proc ) * $self->{MAX_DMI} + $dmi_num; @@ -1955,6 +2401,15 @@ sub getConnectionBus return $target_ptr->{CONNECTION}->{BUS}->[$i]; } +sub getConnectionBusParent +{ + my $self = shift; + my $target = shift; + my $i = shift; + my $target_ptr = $self->getTarget($target); + return $target_ptr->{CONNECTION}->{BUS_PARENT}->[$i]; +} + sub findFirstEndpoint { my $self = shift; @@ -2012,6 +2467,192 @@ sub findDestConnections } +sub setEepromAttributesForAxone +{ + my $self = shift; + my $targetObj = shift; + # Expects ocmb target + my $target = shift; + + my %connections; + my $num=0; + + my $eeprom_name = "EEPROM_VPD_PRIMARY_INFO"; + my $fapi_name = "FAPI_I2C_CONTROL_INFO"; + # SPD contains data for EEPROM_VPD_PRIMARY_INFO and FAPI_I2C_CONTROL_INFO + # SPD is the child of ocmb's parent, so get ocmb's parent + # then look for the SPD child + # With the resulting info, we populate pmic0, pmic1, ocmb, and dimm + my $target_parent = $self->getTargetParent($target); + + # Need to store pmic targets because they get parsed before we + # do calculations for engine, port, and muxBusSelector + # pmics need these values, so we store them until we need them later + my $address = 0; + my @pmic_array; + foreach my $child (@{ $self->getTargetChildren($target_parent) }) + { + my $type = $self->getTargetType($child); + if ($type eq "chip-spd-device") + { + my $offset = $self->getAttribute($child, "BYTE_ADDRESS_OFFSET"); + my $memory_size = $self->getAttribute($child, "MEMORY_SIZE_IN_KB"); + my $cycle_time = $self->getAttribute($child, "WRITE_CYCLE_TIME"); + my $page_size = $self->getAttribute($child, "WRITE_PAGE_SIZE"); + + # Populate EEPROM for ocmb + $targetObj->setAttributeField($target, $eeprom_name, "byteAddrOffset", + $offset); + $targetObj->setAttributeField($target, $eeprom_name, "maxMemorySizeKB", + $memory_size); + $targetObj->setAttributeField($target, $eeprom_name, "writeCycleTime", + $cycle_time); + $targetObj->setAttributeField($target, $eeprom_name, "writePageSize", + $page_size); + + # Populate EEPROM for dimm + $targetObj->setAttributeField($target_parent, $eeprom_name, "byteAddrOffset", + $offset); + $targetObj->setAttributeField($target_parent, $eeprom_name, "maxMemorySizeKB", + $memory_size); + $targetObj->setAttributeField($target_parent, $eeprom_name, "writeCycleTime", + $cycle_time); + $targetObj->setAttributeField($target_parent, $eeprom_name, "writePageSize", + $page_size); + + # spd only child is i2c-slave, which contains devAddr info + foreach my $i2c_slave (@{ $self->getTargetChildren($child) }) + { + $address = $self->getAttribute($i2c_slave, "I2C_ADDRESS"); + # Populate EEPROM for dimm + $targetObj->setAttributeField($target_parent, $eeprom_name, "devAddr", + $address); + + # Populate EEPROM for ocmb + $targetObj->setAttributeField($target, $eeprom_name, "devAddr", + $address); + } + } + elsif ($type eq "chip-vreg-generic") + { + push(@pmic_array, $child); + foreach my $i2c_slave (@{ $self->getTargetChildren($child) }) + { + $type = $self->getTargetType($i2c_slave); + # pmic has child i2c_slave which contains the device address + if ($type eq "unit-i2c-slave") + { + $address = $self->getAttribute($i2c_slave, "I2C_ADDRESS"); + + # Populate FAPI for pmic + $targetObj->setAttributeField($child, $fapi_name, "devAddr", + $address); + last; + } + } + } + elsif ($type eq "chip-ocmb") + { + foreach my $i2c_slave (@{ $self->getTargetChildren($child) }) + { + # ocmb has multiple i2c-slaves, so we query with instance_name + my $instance_name = $self->getInstanceName($i2c_slave); + if ($instance_name eq "i2c-ocmb") + { + $address = $self->getAttribute($i2c_slave, "I2C_ADDRESS"); + + # Populate FAPI for ocmb + $targetObj->setAttributeField($target, $fapi_name, "devAddr", + $address); + last; + } + } + } + } + + # Get data from i2c-master-omi, which connects to the i2c_mux PCA9847 + my $conn = $self->findConnectionsByDirection($target, "I2C", "", 1); + if ($conn ne "") + { + # There exists multiple i2c bus connections with chip-ocmb + # They are all the same connections so we just take the first one + # The mux channel has the i2cMuxBusSelector + my $conn_source = @{$conn->{CONN}}[0]->{SOURCE}; + my $mux = $self->getAttribute($conn_source, "MUX_CHANNEL"); + + # Parent PCA9848 determines the mux path + my $parent = $self->getTargetParent($conn_source); + my $parent_pos = $self->getAttribute($parent, "POSITION"); + my $i2c_mux_path = "physical:sys-0/node-0/i2c_mux-$parent_pos"; + + # pmics and ocmb all grab FRU_ID from parent dimm + my $fru = $self->getAttribute($target_parent, "FRU_ID"); + + my $master_i2c = $self->findConnectionsByDirection($self->getTargetParent($conn_source), "I2C", "", 1); + if ($master_i2c ne "") + { + # There exists multiple i2c bus connections with the PCA9847 i2c_mux + # They are all the same connections so we just take the first one + $master_i2c = @{$master_i2c->{CONN}}[0]; + # i2c-master-omi source which has data we need + my $source = $master_i2c->{SOURCE}; + my $dest = $master_i2c->{DEST}; + my $engine = $self->getAttribute($source, "I2C_ENGINE"); + my $port = $self->getAttribute($source, "I2C_PORT"); + + # Populate FAPI for ocmb + $self->setAttributeField($target, $fapi_name, "engine", + $engine); + $self->setAttributeField($target, $fapi_name, "port", + $port); + $self->setAttributeField($target, $fapi_name, "i2cMuxBusSelector", + $mux); + $self->setAttributeField($target, $fapi_name, "i2cMuxPath", + $i2c_mux_path); + $self->setAttribute($target, "FRU_ID", + $fru); + + # Populate EEPROM for ocmb + $self->setAttributeField($target, $eeprom_name, "i2cMuxPath", + $i2c_mux_path); + $self->setAttributeField($target, $eeprom_name, "engine", + $engine); + $self->setAttributeField($target, $eeprom_name, "port", + $port); + $self->setAttributeField($target, $eeprom_name, "i2cMuxBusSelector", + $mux); + + + # Populate FAPI for pmics + foreach my $pmic (@pmic_array) + { + $self->setAttributeField($pmic, $fapi_name, "engine", + $engine); + $self->setAttributeField($pmic, $fapi_name, "port", + $port); + $self->setAttributeField($pmic, $fapi_name, "i2cMuxBusSelector", + $mux); + $self->setAttributeField($pmic, $fapi_name, "i2cMuxPath", + $i2c_mux_path); + $self->setAttribute($pmic, "FRU_ID", + $fru); + } + + # Populate EEPROM for dimm + $self->setAttributeField($target_parent, $eeprom_name, "engine", + $engine); + $self->setAttributeField($target_parent, $eeprom_name, "port", + $port); + $self->setAttributeField($target_parent, $eeprom_name, "i2cMuxBusSelector", + $mux); + $self->setAttributeField($target_parent, $eeprom_name, "i2cMuxPath", + $i2c_mux_path); + $self->setAttribute($target_parent, "FRU_ID", + $fru); + } + } +} + # Find connections from/to $target (and it's children) # $to_this_target indicates the direction to find. sub findConnectionsByDirection @@ -2049,6 +2690,7 @@ sub findConnectionsByDirection { $numOfConnections = $self->getNumConnections($child); } + for (my $i = 0; $i < $numOfConnections; $i++) { my $other_end_target = undef; @@ -2061,6 +2703,7 @@ sub findConnectionsByDirection $other_end_target = $self->getConnectionDestination($child, $i); } + my $other_end_parent = $self->getTargetParent($other_end_target); my $type = $self->getMrwType($other_end_parent); my $dest_type = $self->getType($other_end_parent); @@ -2079,12 +2722,10 @@ sub findConnectionsByDirection #like unit->pingroup->muxgroup->chip where the chip has #the interesting type. while ($type ne $other_end_type) { - $other_end_parent = $self->getTargetParent($other_end_parent); if ($other_end_parent eq "") { last; } - $type = $self->getMrwType($other_end_parent); if ($type eq "NA") { $type = $self->getType($other_end_parent); @@ -2518,7 +3159,6 @@ sub setHuid $index = $self->{huid_idx}->{$type}; } else { $self->{huid_idx}->{$type} = 0; } - # Format: SSSS NNNN TTTTTTTT iiiiiiiiiiiiiiii my $huid = sprintf("%01x%01x%02x%04x", $sys, $node, $type_id, $index); $huid = "0x" . uc($huid); @@ -2554,6 +3194,19 @@ sub setMruid $self->{mru_idx}->{$node}->{$type}++; } +sub getMasterProc +{ + my $self = shift; + return $self->{master_proc}; +} + +sub setMasterProc +{ + my $self = shift; + my $target = shift; + $self->{master_proc}=$target; +} + sub getSystemName { my $self = shift; @@ -2786,11 +3439,16 @@ C<TARGET_STRING>. The bus data structure is also a target with attributes. Returns the target string of the C<INDEX> target found connected to C<TARGET_STRING>. -=item getConnectionBus(C<TARGET_STRING>) +=item getConnectionBus(C<TARGET_STRING>,C<INDEX>) Returns the data structure of the C<INDEX> bus target found connected to C<TARGET_STRING>. +=item getConnectionBusParent(C<TARGET_STRING>,C<INDEX>) + +Returns C<PARENT_TARGET_STRING> of the parent target for the bus target found +connected to C<TARGET_STRING> + =item findEndpoint(C<TARGET_STRING>,C<BUS_TYPE>,C<ENDPOINT_MRW_TYPE>) Searches through all connections to C<TARGET_STRING> diff --git a/src/usr/targeting/common/associationmanager.C b/src/usr/targeting/common/associationmanager.C index 984eb17ec..b811f1861 100644 --- a/src/usr/targeting/common/associationmanager.C +++ b/src/usr/targeting/common/associationmanager.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -199,7 +199,7 @@ errlHndl_t AssociationManager::reconnectSyAndNodeTargets() { TARG_ERR("Failed to find master system target"); - /* + /*@ * @errortype * @refcode LIC_REFCODE * @subsys EPUB_FIRMWARE_SP @@ -304,7 +304,7 @@ errlHndl_t AssociationManager::_clearAssocsOfTypeFromSysOrNodeTarget( pAssocsItrPreTrans, i_pSysOrNodeTarget->getAttr<TARGETING::ATTR_HUID>(), i_pSysOrNodeTarget); - /* + /*@ * @errortype * @refcode LIC_REFCODE * @subsys EPUB_FIRMWARE_SP @@ -447,7 +447,7 @@ errlHndl_t AssociationManager::_addAssocToSysOrNodeTarget( pAssocsItrPreTrans, i_pSourceSysOrNodeTarget->getAttr<TARGETING::ATTR_HUID>(), i_pSourceSysOrNodeTarget); - /* + /*@ * @errortype * @refcode LIC_REFCODE * @subsys EPUB_FIRMWARE_SP @@ -482,7 +482,7 @@ errlHndl_t AssociationManager::_addAssocToSysOrNodeTarget( "maxLinks = %d, i_assocType = 0x%08X, HUID = 0x%08X", association, maxLinks, i_assocType, i_pSourceSysOrNodeTarget->getAttr<TARGETING::ATTR_HUID>()); - /* + /*@ * @errortype * @refcode LIC_REFCODE * @subsys EPUB_FIRMWARE_SP diff --git a/src/usr/targeting/common/attributeTank.C b/src/usr/targeting/common/attributeTank.C index 07ccff982..c6cad3c49 100644 --- a/src/usr/targeting/common/attributeTank.C +++ b/src/usr/targeting/common/attributeTank.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2017 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -99,10 +99,12 @@ void AttributeTank::clearAllAttributes( while (l_itr != iv_attributes.end()) { + // Get a copy of the Attribute's node for quick access + uint8_t l_node = (*l_itr)->getHeader().iv_node; if (i_nodeFilter == NODE_FILTER_NOT_ALL_NODES) { // Only clear attributes that are not for all nodes - if ((*l_itr)->iv_hdr.iv_node == ATTR_NODE_NA) + if (l_node == ATTR_NODE_NA) { l_itr++; continue; @@ -111,8 +113,8 @@ void AttributeTank::clearAllAttributes( else if (i_nodeFilter == NODE_FILTER_SPECIFIC_NODE_AND_ALL) { // Only clear attributes associated with i_node or all - if ( ((*l_itr)->iv_hdr.iv_node != ATTR_NODE_NA) && - ((*l_itr)->iv_hdr.iv_node != i_node) ) + if ( (l_node != ATTR_NODE_NA) && + (l_node != i_node) ) { l_itr++; continue; @@ -121,7 +123,7 @@ void AttributeTank::clearAllAttributes( else if (i_nodeFilter == NODE_FILTER_SPECIFIC_NODE) { // Only clear attributes associated with i_node - if ((*l_itr)->iv_hdr.iv_node != i_node) + if (l_node != i_node) { l_itr++; continue; @@ -153,13 +155,18 @@ void AttributeTank::clearNonConstAttribute(const uint32_t i_attrId, for (AttributesItr_t l_itr = iv_attributes.begin(); l_itr != iv_attributes.end(); ++l_itr) { - if ( ((*l_itr)->iv_hdr.iv_attrId == i_attrId) && - ((*l_itr)->iv_hdr.iv_targetType == i_targetType) && - ((*l_itr)->iv_hdr.iv_pos == i_pos) && - ((*l_itr)->iv_hdr.iv_unitPos == i_unitPos) && - ((*l_itr)->iv_hdr.iv_node == i_node) ) + // Get a (constant) reference to the Attribute Header + // for easy access to data members + const AttributeHeader &l_attributeHeader = (*l_itr)->getHeader(); + + // Find attribute that satisfies search criteria + if ( (l_attributeHeader.iv_attrId == i_attrId) && + (l_attributeHeader.iv_targetType == i_targetType) && + (l_attributeHeader.iv_pos == i_pos) && + (l_attributeHeader.iv_unitPos == i_unitPos) && + (l_attributeHeader.iv_node == i_node) ) { - if (!((*l_itr)->iv_hdr.iv_flags & ATTR_FLAG_CONST)) + if (!(l_attributeHeader.iv_flags & ATTR_FLAG_CONST)) { delete (*l_itr); (*l_itr) = NULL; @@ -196,20 +203,25 @@ void AttributeTank::setAttribute(const uint32_t i_attrId, for (AttributesItr_t l_itr = iv_attributes.begin(); l_itr != iv_attributes.end(); ++l_itr) { - if ( ((*l_itr)->iv_hdr.iv_attrId == i_attrId) && - ((*l_itr)->iv_hdr.iv_targetType == i_targetType) && - ((*l_itr)->iv_hdr.iv_pos == i_pos) && - ((*l_itr)->iv_hdr.iv_unitPos == i_unitPos) && - ((*l_itr)->iv_hdr.iv_node == i_node) && - ((*l_itr)->iv_hdr.iv_valSize == i_valSize) ) + // Get a reference to the Attribute Header + // for easy access to data members + const AttributeHeader &l_attributeHeader = (*l_itr)->getHeader(); + + // Find attribute that satisfies search criteria + if ( (l_attributeHeader.iv_attrId == i_attrId) && + (l_attributeHeader.iv_targetType == i_targetType) && + (l_attributeHeader.iv_pos == i_pos) && + (l_attributeHeader.iv_unitPos == i_unitPos) && + (l_attributeHeader.iv_node == i_node) && + (l_attributeHeader.iv_valSize == i_valSize) ) { // Found existing attribute, update it unless the existing attribute // is const and the new attribute is non-const - if (!( ((*l_itr)->iv_hdr.iv_flags & ATTR_FLAG_CONST) && + if (!( (l_attributeHeader.iv_flags & ATTR_FLAG_CONST) && (!(i_flags & ATTR_FLAG_CONST)) ) ) { - (*l_itr)->iv_hdr.iv_flags = i_flags; - memcpy((*l_itr)->iv_pVal, i_pVal, i_valSize); + (*l_itr)->setFlags(i_flags); + (*l_itr)->setValue(i_pVal, i_valSize); } l_found = true; break; @@ -221,15 +233,13 @@ void AttributeTank::setAttribute(const uint32_t i_attrId, // Add a new attribute to the tank Attribute * l_pAttr = new Attribute(); - l_pAttr->iv_hdr.iv_attrId = i_attrId; - l_pAttr->iv_hdr.iv_targetType = i_targetType; - l_pAttr->iv_hdr.iv_pos = i_pos; - l_pAttr->iv_hdr.iv_unitPos = i_unitPos; - l_pAttr->iv_hdr.iv_node = i_node; - l_pAttr->iv_hdr.iv_flags = i_flags; - l_pAttr->iv_hdr.iv_valSize = i_valSize; - l_pAttr->iv_pVal = new uint8_t[i_valSize]; - memcpy(l_pAttr->iv_pVal, i_pVal, i_valSize); + l_pAttr->setId(i_attrId); + l_pAttr->setTargetType(i_targetType); + l_pAttr->setPosition(i_pos); + l_pAttr->setUnitPosition(i_unitPos); + l_pAttr->setNode(i_node); + l_pAttr->setFlags(i_flags); + l_pAttr->setValue(i_pVal, i_valSize); iv_attributesExist = true; iv_attributes.push_back(l_pAttr); @@ -253,18 +263,22 @@ bool AttributeTank::getAttribute(const uint32_t i_attrId, for (AttributesCItr_t l_itr = iv_attributes.begin(); l_itr != iv_attributes.end(); ++l_itr) { - // Allow match if attribute applies to all positions - if ( ((*l_itr)->iv_hdr.iv_attrId == i_attrId) && - ((*l_itr)->iv_hdr.iv_targetType == i_targetType) && - (((*l_itr)->iv_hdr.iv_pos == ATTR_POS_NA) || - ((*l_itr)->iv_hdr.iv_pos == i_pos)) && - (((*l_itr)->iv_hdr.iv_unitPos == ATTR_UNIT_POS_NA) || - ((*l_itr)->iv_hdr.iv_unitPos == i_unitPos)) && - (((*l_itr)->iv_hdr.iv_node == ATTR_NODE_NA) || - ((*l_itr)->iv_hdr.iv_node == i_node)) ) + // Get a (constant) reference to the Attribute Header + // for easy access to data members + const AttributeHeader &l_attributeHeader = (*l_itr)->getHeader(); + + // Find attribute that satisfies search criteria + if ( (l_attributeHeader.iv_attrId == i_attrId) && + (l_attributeHeader.iv_targetType == i_targetType) && + ((l_attributeHeader.iv_pos == ATTR_POS_NA) || + (l_attributeHeader.iv_pos == i_pos)) && + ((l_attributeHeader.iv_unitPos == ATTR_UNIT_POS_NA) || + (l_attributeHeader.iv_unitPos == i_unitPos)) && + ((l_attributeHeader.iv_node == ATTR_NODE_NA) || + (l_attributeHeader.iv_node == i_node)) ) { l_found = true; - memcpy(o_pVal, (*l_itr)->iv_pVal, (*l_itr)->iv_hdr.iv_valSize); + (*l_itr)->cloneValue(o_pVal, l_attributeHeader.iv_valSize); break; } } @@ -293,10 +307,18 @@ void AttributeTank::serializeAttributes( // Fill up the buffer with as many attributes as possible while (l_itr != iv_attributes.end()) { + // Get a (constant) reference to the Attribute Header + // for easy access to data members + const AttributeHeader &l_attributeHeader = + (*l_itr)->getHeader(); + + // Get a copy of the node for quick access + uint8_t l_node = l_attributeHeader.iv_node; + if (i_nodeFilter == NODE_FILTER_NOT_ALL_NODES) { // Only want attributes that are not for all nodes - if ((*l_itr)->iv_hdr.iv_node == ATTR_NODE_NA) + if (l_node == ATTR_NODE_NA) { l_itr++; continue; @@ -305,8 +327,8 @@ void AttributeTank::serializeAttributes( else if (i_nodeFilter == NODE_FILTER_SPECIFIC_NODE_AND_ALL) { // Only want attributes associated with i_node or all - if ( ((*l_itr)->iv_hdr.iv_node != ATTR_NODE_NA) && - ((*l_itr)->iv_hdr.iv_node != i_node) ) + if ( (l_node != ATTR_NODE_NA) && + (l_node != i_node) ) { l_itr++; continue; @@ -315,15 +337,14 @@ void AttributeTank::serializeAttributes( else if (i_nodeFilter == NODE_FILTER_SPECIFIC_NODE) { // Only want attributes associated with i_node - if ((*l_itr)->iv_hdr.iv_node != i_node) + if (l_node != i_node) { l_itr++; continue; } } - if ((l_index + sizeof(AttributeHeader) + - (*l_itr)->iv_hdr.iv_valSize) > i_chunkSize) + if ((l_index + (*l_itr)->getSize()) > i_chunkSize) { // Attribute will not fit into the buffer if (l_index == 0) @@ -334,7 +355,7 @@ void AttributeTank::serializeAttributes( TRACFCOMP(g_trac_targeting, "serializeAttributes: Error, attr too big to serialize " "(0x%x)", - (*l_itr)->iv_hdr.iv_valSize); + l_attributeHeader.iv_valSize); l_itr++; } else @@ -346,17 +367,8 @@ void AttributeTank::serializeAttributes( } else { - // Copy the attribute header to the buffer - AttributeHeader * l_pHeader = - reinterpret_cast<AttributeHeader *>(l_pBuffer + l_index); - *l_pHeader = (*l_itr)->iv_hdr; - l_index += sizeof(AttributeHeader); - - // Copy the attribute value to the buffer - memcpy((l_pBuffer + l_index), (*l_itr)->iv_pVal, - (*l_itr)->iv_hdr.iv_valSize); - l_index += (*l_itr)->iv_hdr.iv_valSize; - + l_index += (*l_itr)->serialize(l_pBuffer + l_index, + (*l_itr)->getSize()); l_itr++; } } @@ -404,7 +416,7 @@ bool AttributeTank::attributeExists(const uint32_t i_attrId) const for (AttributesCItr_t l_itr = iv_attributes.begin(); l_itr != iv_attributes.end(); ++l_itr) { - if ((*l_itr)->iv_hdr.iv_attrId == i_attrId) + if ((*l_itr)->getHeader().iv_attrId == i_attrId) { l_found = true; break; @@ -424,60 +436,54 @@ void AttributeTank::deserializeAttributes( uint32_t l_index = 0; + // Get a handle to the serialized Attributes + uint8_t* l_serializedData = + reinterpret_cast<uint8_t*>(i_attributes.iv_pAttributes); + + // Iterate thru the Attributes while (l_index < i_attributes.iv_size) { - AttributeHeader * l_pAttrHdr = - reinterpret_cast<AttributeHeader *> - (i_attributes.iv_pAttributes + l_index); + // Create a new Attribute + Attribute * l_pAttribute = new Attribute(); - if (sizeof(AttributeHeader) > (i_attributes.iv_size - l_index)) + // Deserialize the data, if possible + uint32_t l_deserializedDataSize = l_pAttribute->deserialize( + l_serializedData + l_index, + i_attributes.iv_size - l_index); + + if (!l_deserializedDataSize) { + // Unable to deserialize data, delete Attribute + delete l_pAttribute; + l_pAttribute = NULL; + // Remaining chunk smaller than attribute header, quit TRACFCOMP(g_trac_targeting, - "deserializeAttributes: Error, header too big for chunk " - "(0x%x)", + "deserializeAttributes: Error, attribute too big for " + "chunk (0x%x)", (i_attributes.iv_size - l_index)); break; } - l_index += sizeof(AttributeHeader); - - if (l_pAttrHdr->iv_valSize > (i_attributes.iv_size - l_index)) - { - // Remaining chunk smaller than attribute value, quit - TRACFCOMP(g_trac_targeting, - "deserializeAttributes: Error, attr too big for chunk " - "(0x%x:0x%x)", - l_pAttrHdr->iv_valSize, (i_attributes.iv_size - l_index)); - break; - } - - // Create a new Attribute and add it to the tank - Attribute * l_pAttr = new Attribute(); - l_pAttr->iv_hdr = *l_pAttrHdr; - l_pAttr->iv_pVal = new uint8_t[l_pAttrHdr->iv_valSize]; - memcpy(l_pAttr->iv_pVal, (i_attributes.iv_pAttributes + l_index), - l_pAttrHdr->iv_valSize); - - l_index += l_pAttrHdr->iv_valSize; + // Was able to deserialize data, add Attribute to the tank iv_attributesExist = true; - iv_attributes.push_back(l_pAttr); + iv_attributes.push_back(l_pAttribute); + + // Increment the index after deserializing an attribute + l_index += l_deserializedDataSize; - if // attributes should be echo'd - ( i_echoAttributes == true ) + if ( i_echoAttributes == true ) // attributes should be echo'd { // extract individual fields from attribute - uint32_t attrId = l_pAttr->iv_hdr.iv_attrId; - uint32_t targetType = l_pAttr->iv_hdr.iv_targetType; - uint16_t pos = l_pAttr->iv_hdr.iv_pos; - uint8_t unitPos = l_pAttr->iv_hdr.iv_unitPos; - - const uint8_t * pNodeFlags = (&(l_pAttr->iv_hdr.iv_unitPos)) + 1; + uint32_t attrId(l_pAttribute->getHeader().iv_attrId); + uint32_t targetType(l_pAttribute->getHeader().iv_targetType); + uint16_t pos(l_pAttribute->getHeader().iv_pos); + uint8_t unitPos(l_pAttribute->getHeader().iv_unitPos); - uint8_t node = (*pNodeFlags) >> 4; // isolate hi nibble - uint8_t flags = (*pNodeFlags) & 0x0F; // isolate lo nibble + uint8_t node(l_pAttribute->getHeader().iv_node); + uint8_t flags(l_pAttribute->getHeader().iv_flags); - uint32_t valueLen = l_pAttr->iv_hdr.iv_valSize; + uint32_t valueLen(l_pAttribute->getHeader().iv_valSize); TRACFCOMP(g_trac_targeting, "deserializeAttributes: Attribute Hdr: " @@ -488,7 +494,7 @@ void AttributeTank::deserializeAttributes( TRACFBIN(g_trac_targeting, "deserializeAttributes: Parm Value: ", - l_pAttr->iv_pVal, valueLen); + l_pAttribute->getValue(), valueLen); } // end echo attributes } @@ -505,20 +511,6 @@ void AttributeTank::deserializeAttributes( } //****************************************************************************** -AttributeTank::Attribute::Attribute() : - iv_pVal(NULL) -{ - -} - -//****************************************************************************** -AttributeTank::Attribute::~Attribute() -{ - delete[] iv_pVal; - iv_pVal = NULL; -} - -//****************************************************************************** errlHndl_t AttributeTank::writePermAttributes() { errlHndl_t l_err = NULL; @@ -526,8 +518,10 @@ errlHndl_t AttributeTank::writePermAttributes() for(AttributesCItr_t l_attrIter = iv_attributes.begin(); l_attrIter != iv_attributes.end(); ++l_attrIter) { - Attribute* l_attr = *l_attrIter; - AttributeHeader l_attrHdr = l_attr->iv_hdr; + // Get a (constant) reference to the Attribute Header + // for easy access to data members + const AttributeHeader &l_attrHdr = (*l_attrIter)->getHeader(); + PredicatePostfixExpr l_permAttrOverrides; // Predicate to match target type @@ -553,7 +547,7 @@ errlHndl_t AttributeTank::writePermAttributes() bool l_success = (*l_permTargetList)->_trySetAttr( static_cast<ATTRIBUTE_ID>(l_attrHdr.iv_attrId), l_attrHdr.iv_valSize, - l_attr->iv_pVal ); + (*l_attrIter)->getValue() ); if (l_success) { @@ -561,16 +555,17 @@ errlHndl_t AttributeTank::writePermAttributes() "permanent override of Attr ID:0x%X Value:0x%llX applied " "to target 0x%X", l_attrHdr.iv_attrId, - *reinterpret_cast<uint64_t *>(l_attr->iv_pVal), + *reinterpret_cast<const uint64_t *> + ((*l_attrIter)->getValue()), (*l_permTargetList)->getAttr<ATTR_HUID>() ); } else { - uint8_t * io_pAttrData = NULL; + uint8_t * l_pAttrData(NULL); bool l_found = (*l_permTargetList)->_tryGetAttr( static_cast<ATTRIBUTE_ID>(l_attrHdr.iv_attrId), l_attrHdr.iv_valSize, - io_pAttrData); + l_pAttrData); if (l_found) { @@ -579,9 +574,10 @@ errlHndl_t AttributeTank::writePermAttributes() "ID:0x%X Value:0x%llX on target 0x%X - current value " "0x%llX", l_attrHdr.iv_attrId, - *reinterpret_cast<uint64_t *>(l_attr->iv_pVal), + *reinterpret_cast<const uint64_t *> + ((*l_attrIter)->getValue()), (*l_permTargetList)->getAttr<ATTR_HUID>(), - *reinterpret_cast<uint64_t *>(io_pAttrData) ); + *reinterpret_cast<uint64_t *>(l_pAttrData) ); /*@ * @errortype * @moduleid TARG_WRITE_PERM_ATTR @@ -616,7 +612,7 @@ errlHndl_t AttributeTank::writePermAttributes() * @devdesc Given target does not have given attribute * to apply override */ - UTIL::createTracingError( + UTIL::createTracingError( TARG_WRITE_PERM_ATTR, TARG_RC_WRITE_PERM_ATTR_TARGET_FAIL, (*l_permTargetList)->getAttr<ATTR_HUID>(), @@ -641,4 +637,23 @@ size_t AttributeTank::size() const return iv_attributes.size(); } +//****************************************************************************** +void AttributeTank::getAllAttributes( std::list<Attribute *>& o_attributes ) const +{ + o_attributes = iv_attributes; +} + +//****************************************************************************** +const char* AttributeTank::layerToString( TankLayer i_layer ) +{ + switch(i_layer) + { + case(AttributeTank::TANK_LAYER_FAPI): return "FAPI"; + case(AttributeTank::TANK_LAYER_TARG): return "TARG"; + case(AttributeTank::TANK_LAYER_PERM): return "PERM"; + default: return "UNKNOWN"; + } +} + } + diff --git a/src/usr/targeting/common/common.mk b/src/usr/targeting/common/common.mk index 5c357f111..951aa8663 100644 --- a/src/usr/targeting/common/common.mk +++ b/src/usr/targeting/common/common.mk @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2011,2018 +# Contributors Listed Below - COPYRIGHT 2011,2020 # [+] International Business Machines Corp. # # @@ -64,4 +64,3 @@ COMMON_TARGETING_OBJS += ${TARGET_OBJS} COMMON_TARGETING_OBJS += ${PREDICATES_OBJS} COMMON_TARGETING_OBJS += ${ITERATORS_OBJS} COMMON_TARGETING_OBJS += ${OTHER_OBJS} - diff --git a/src/usr/targeting/common/genHDATstructures.pl b/src/usr/targeting/common/genHDATstructures.pl index 5150e3a06..2bbcbfd9a 100755 --- a/src/usr/targeting/common/genHDATstructures.pl +++ b/src/usr/targeting/common/genHDATstructures.pl @@ -6,7 +6,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2015,2018 +# Contributors Listed Below - COPYRIGHT 2015,2019 # [+] International Business Machines Corp. # # diff --git a/src/usr/targeting/common/genHwsvMrwXml.pl b/src/usr/targeting/common/genHwsvMrwXml.pl index 1632b1cfc..c6b185426 100755 --- a/src/usr/targeting/common/genHwsvMrwXml.pl +++ b/src/usr/targeting/common/genHwsvMrwXml.pl @@ -6077,6 +6077,14 @@ sub generate_is_dimm my $uidstr = sprintf( "0x%02X03%04X", $node, $dimm_rel_node ); + # Generate the slot position for mvdimm restrictions + # The formula is: + # [processor position with no gaps, i.e. 0,1,2,3]*16 + + # [mca position on this processor * 2] + [dimm location behind this mca] + my $nvdimmslot = ($proc * MAX_MCA_PER_PROC * ARCH_LIMIT_DIMM_PER_MCA) + + ($mca * 2) + ($dimm_rel_mca); + + # add dimm to mcbist array push(@{$mcbist_dimms{$node . $proc."_".$mcb_rel_proc}}, "n${node}:p${pos}"); @@ -6117,6 +6125,10 @@ sub generate_is_dimm <default>$dimm_drop</default> </attribute> <attribute> + <id>MSS_MRW_NVDIMM_SLOT_POSITION</id> + <default>$nvdimmslot</default> + </attribute> + <attribute> <id>POS_ON_MEM_PORT</id> <default>$dimm_rel_mca</default> </attribute>"; diff --git a/src/usr/targeting/common/hbrt_target.C b/src/usr/targeting/common/hbrt_target.C new file mode 100644 index 000000000..b91979922 --- /dev/null +++ b/src/usr/targeting/common/hbrt_target.C @@ -0,0 +1,101 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/targeting/common/hbrt_target.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#include <targeting/common/hbrt_target.H> +#include <targeting/common/targetservice.H> +#include <targeting/common/targreasoncodes.H> +#include <runtime/customize_attrs_for_payload.H> +#include <targeting/common/trace.H> +#ifdef __HOSTBOOT_MODULE +#include <errl/errludtarget.H> +#endif + +extern trace_desc_t* g_trac_hbrt; +using namespace TARGETING; + +namespace TARGETING +{ + +errlHndl_t getRtTarget( + const TARGETING::Target* i_pTarget, + rtChipId_t& o_rtTargetId) +{ + errlHndl_t pError = NULL; + + do + { + if(i_pTarget == TARGETING::MASTER_PROCESSOR_CHIP_TARGET_SENTINEL) + { + TARGETING::Target* masterProcChip = NULL; + TARGETING::targetService(). + masterProcChipTargetHandle(masterProcChip); + i_pTarget = masterProcChip; + } + + auto hbrtHypId = RUNTIME::HBRT_HYP_ID_UNKNOWN; + if( (!i_pTarget->tryGetAttr<TARGETING::ATTR_HBRT_HYP_ID>(hbrtHypId)) + || (hbrtHypId == RUNTIME::HBRT_HYP_ID_UNKNOWN)) + { + auto huid = get_huid(i_pTarget); + auto targetingTargetType = + i_pTarget->getAttr<TARGETING::ATTR_TYPE>(); + TRACFCOMP(g_trac_targeting, ERR_MRK + "Targeting target type of 0x%08X not supported. " + "HUID: 0x%08X", + targetingTargetType, + huid); + /*@ + * @errortype + * @moduleid TARG_RT_GET_RT_TARGET + * @reasoncode TARG_RT_TARGET_TYPE_NOT_SUPPORTED + * @userdata1 Target's HUID + * @userdata2 target's targeting type + * @devdesc Targeting target's type not supported by runtime + * code + */ + pError = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_INFORMATIONAL, + TARGETING::TARG_RT_GET_RT_TARGET, + TARGETING::TARG_RT_TARGET_TYPE_NOT_SUPPORTED, + huid, + targetingTargetType +#ifdef __HOSTBOOT_MODULE + ,true); + + ERRORLOG::ErrlUserDetailsTarget(i_pTarget,"Targeting Target"). + addToLog(pError); +#else + ); // if not in hostboot code then skip last param of error log + // and do not create a user details section +#endif + } + + o_rtTargetId = hbrtHypId; + + } while(0); + + return pError; +} + +}
\ No newline at end of file diff --git a/src/usr/targeting/common/processMrw.pl b/src/usr/targeting/common/processMrw.pl index 341574246..2b88520ba 100755 --- a/src/usr/targeting/common/processMrw.pl +++ b/src/usr/targeting/common/processMrw.pl @@ -44,9 +44,27 @@ my $debug = 0; my $report = 0; my $sdr_file = ""; my $build = "hb"; -my $system_config = ""; +my $system_config = ""; my $output_filename = ""; +# Map the OMI instance to its corresponding OMIC parent +my %omi_map = (4 => "omic-0", + 5 => "omic-0", + 6 => "omic-0", + 7 => "omic-1", + 2 => "omic-1", + 3 => "omic-1", + 0 => "omic-2", + 1 => "omic-2", + 12 => "omic-0", + 13 => "omic-0", + 14 => "omic-0", + 15 => "omic-1", + 10 => "omic-1", + 11 => "omic-1", + 8 => "omic-2", + 9 => "omic-2"); + # TODO RTC:170860 - Remove this after dimm connector defines VDDR_ID my $num_voltage_rails_per_proc = 1; @@ -378,7 +396,10 @@ foreach my $target (@targets) { processUcd($targetObj, $target); } - + } + elsif ($type eq "OCMB_CHIP") + { + processOcmbChip($targetObj, $target); } processIpmiSensors($targetObj,$target); @@ -1135,7 +1156,6 @@ sub processProcessor ## update path for mvpd's and sbe's my $path = $targetObj->getAttribute($target, "PHYS_PATH"); my $model = $targetObj->getAttribute($target, "MODEL"); - $targetObj->setAttributeField($target, "EEPROM_VPD_PRIMARY_INFO","i2cMasterPath",$path); $targetObj->setAttributeField($target, @@ -1434,9 +1454,9 @@ sub setupBars foreach my $bar (keys %bars) { my $i_base = Math::BigInt->new($bars{$bar}); - my $value=sprintf("0x%016s",substr(( - $i_base+$groupOffset*$group+ - $procOffset*$proc)->as_hex(),2)); + my $value=sprintf("0x%016s",substr(( + $i_base+$groupOffset*$group+ + $procOffset*$proc)->as_hex(),2)); $targetObj->setAttribute($target,$bar,$value); } } @@ -1642,6 +1662,9 @@ sub processMcbist ## sub processMc { + # NOTE: OMI_INBAND_BAR_BASE_ADDR_OFFSET will be set for the MC + # targets via a specific child OMI Target. View the + # processOmi function for further details. my $targetObj = shift; my $target = shift; @@ -1656,6 +1679,10 @@ sub processMc { processMi($targetObj, $child); } + elsif ($child_type eq "OMIC") + { + processOmic($targetObj, $child); + } } { @@ -1669,8 +1696,146 @@ sub processMc } } +#-------------------------------------------------- +## MCC +## +## +sub processMcc +{ + my $targetObj = shift; + my $target = shift; + + foreach my $child (@{ $targetObj->getTargetChildren($target) }) + { + my $child_type = $targetObj->getType($child); + + $targetObj->log($target, + "Processing MCC child: $child Type: $child_type"); + + if ($child_type eq "OMI") + { + processOmi($targetObj, $child); + } + } + + { + use integer; + # There are a total of four MCC units on an MC unit. So, to + # determine which MC an MCC belongs to, the CHIP_UNIT of the MCC can + # be divided by the number of units per MC to arrive at the correct + # offset to add to the pervasive MCC parent offset. + my $numberOfMccPerMc = 4; + my $chip_unit = $targetObj->getAttribute($target, "CHIP_UNIT"); + + my $value = sprintf("0x%x", + Targets::PERVASIVE_PARENT_MI_OFFSET + + ($chip_unit / $numberOfMccPerMc)); + + $targetObj->setAttribute( $target, "CHIPLET_ID", $value); + } +} #-------------------------------------------------- +## OMI +## +## +sub processOmi +{ + my $mrwObj = shift; + my $omitarg = shift; + + use integer; + # There are a total of eight OMI units on an MC unit. So, to + # determine which MC an OMI belongs to, the CHIP_UNIT of the OMI can + # be divided by the number of units per MC to arrive at the correct + # offset to add to the pervasive OMI parent offset. + my $numberOfOmiPerMc = 8; + my $chip_unit = $mrwObj->getAttribute($omitarg, "CHIP_UNIT"); + my $fapi_pos = $mrwObj->getAttribute($omitarg, "FAPI_POS"); + my $value = sprintf("0x%x", + Targets::PERVASIVE_PARENT_MI_OFFSET + + ($chip_unit / $numberOfOmiPerMc)); + + $mrwObj->setAttribute($omitarg, "CHIPLET_ID", $value); + + # Start with our affinity path "sys-a/node-b/proc-c/mc-d/mi-e/mcc-f/omi-g" + # then snip off everything before the mi + my $phys_path = $mrwObj->getAttribute($omitarg, "PHYS_PATH"); + my $up_to_mi = index($phys_path,"mi-"); + my $omic_parent = substr($phys_path,0,$up_to_mi); + $omic_parent = $omic_parent.$omi_map{$chip_unit}; + $mrwObj->setAttribute($omitarg, "OMIC_PARENT", $omic_parent); + + my $omi = Math::BigInt->new($mrwObj->getAttribute($omitarg,"FAPI_POS")); + # Base omi bar offset + # We use this base address in simics_AXONE.system.xml and want our + # addresses to match the ones in that xml + my $base = 0x30400000000; + my $gigabyte = 0x40000000; + my $value = 0; + + # This algorithm is explained in src/usr/mmio/mmio.C + if ($omi % 2 eq 0) + { + $value = $base + $omi * 4 * $gigabyte; + } + else + { + $value = $base + (($omi - 1) * 4 + 2) * $gigabyte; + } + + $value = sprintf("0x%016s", substr(($value)->as_hex(),2)); + $mrwObj->setAttribute($omitarg, "OMI_INBAND_BAR_BASE_ADDR_OFFSET", + $value); + + # Set the parent MC BAR value to value of first OMI unit + if ($omi % 8 eq 0) + { + my $parent_mcc = $mrwObj->getTargetParent($omitarg); + my $parent_mi = $mrwObj->getTargetParent($parent_mcc); + my $parent_mc = $mrwObj->getTargetParent($parent_mi); + $mrwObj->setAttribute($parent_mc, "OMI_INBAND_BAR_BASE_ADDR_OFFSET", + $value); + } +} + +#-------------------------------------------------- +## OMIC +## +## +sub processOmic +{ + my $targetObj = shift; + my $target = shift; + + use integer; + # There are a total of three OMIC units on an MC unit. So, to + # determine which MC an OMIC belongs to, the CHIP_UNIT of the OMIC can + # be divided by the number of units per MC to arrive at the correct + # offset to add to the pervasive OMIC parent offset. + my $numberOfOmicPerMc = 3; + my $chip_unit = $targetObj->getAttribute($target, "CHIP_UNIT"); + + my $value = sprintf("0x%x", + Targets::PERVASIVE_PARENT_MI_OFFSET + + ($chip_unit / $numberOfOmicPerMc)); + + $targetObj->setAttribute( $target, "CHIPLET_ID", $value); +} + +#-------------------------------------------------- +## OCMB_CHIP +## +## +sub processOcmbChip +{ + my $targetObj = shift; + my $target = shift; + + $targetObj->setEepromAttributesForAxone($targetObj, $target); +} + +#-------------------------------------------------g ## MI ## ## @@ -1690,6 +1855,10 @@ sub processMi { processDmi($targetObj, $child); } + elsif ($child_type eq "MCC") + { + processMcc($targetObj, $child); + } } { @@ -1745,7 +1914,7 @@ sub processDmi Targets::PERVASIVE_PARENT_DMI_OFFSET + ($chip_unit / $numberOfDmiPerMc)); - $targetObj->setAttribute( $target, "CHIPLET_ID", $value); + $targetObj->setAttribute($target, "CHIPLET_ID", $value); } } @@ -1837,12 +2006,27 @@ sub processObus if ($match eq 0) { $targetObj->setAttribute($obrick, "OBUS_SLOT_INDEX", -1); - } } } } + + my $chip_unit = $targetObj->getAttribute($target, "CHIP_UNIT"); + my $value = sprintf("0x%x", Targets::PERVASIVE_PARENT_OBUS_OFFSET + $chip_unit); + $targetObj->setAttribute($target, "CHIPLET_ID", $value); + + # Set CHIPLET_ID for OBUS_BRICKs + foreach my $child (@{ $targetObj->getTargetChildren($target) }) + { + my $type = $targetObj->getType($child); + if ($type eq "OBUS_BRICK") + { + # OBUS_BRICK takes on CHIPLET_ID of OBUS parent + $targetObj->setAttribute($child, "CHIPLET_ID", $value); + } + } } + #-------------------------------------------------- ## XBUS ## @@ -2769,6 +2953,23 @@ sub processI2C { $type = "0xFF"; } + # TPM types can vary by MODEL number + elsif ($type_str eq "NUVOTON_TPM") + { + # Model values can be found in tpmddif.H and are kept in + # sync with TPM_MODEL attribute in attribute_types_hb.xml + my $tpm_model = $targetObj->getAttribute($i2c->{DEST_PARENT},"TPM_MODEL"); + if ($tpm_model eq 1) + { + $type = $targetObj->getEnumValue("HDAT_I2C_DEVICE_TYPE",$type_str); + } + if ($tpm_model eq 2) + { + # @TODO RTC 212201 use proper enum when <system>.xml supports it + #$type = $targetObj->getEnumValue("HDAT_I2C_DEVICE_TYPE","TCG_I2C_TPM"); + $type = 0x15; + } + } else { $type = $targetObj->getEnumValue("HDAT_I2C_DEVICE_TYPE",$type_str); @@ -2901,7 +3102,17 @@ sub processI2C # <vendor>,<device type>,<purpose>,<scope> if ($type_str eq "NUVOTON_TPM") { - $label = "nuvoton,npct601,tpm,host"; + # Model values can be found in tpmddif.H and are kept in + # sync with TPM_MODEL attribute in attribute_types_hb.xml + my $tpm_model = $targetObj->getAttribute($i2c->{DEST_PARENT},"TPM_MODEL"); + if ($tpm_model eq 1) + { + $label = "nuvoton,npct601,tpm,host"; + } + if ($tpm_model eq 2) + { + $label = "tcg,tpm_i2c_ptp,tpm,host"; + } } if ($label eq "") @@ -2938,7 +3149,6 @@ sub processI2C \@i2cSpeed, \@i2cType, \@i2cPurpose, \@i2cLabel); } - sub setEepromAttributes { my $targetObj = shift; @@ -2953,9 +3163,7 @@ sub setEepromAttributes # $conn_target->{BUS_NUM}, "I2C_ADDRESS"); my $addr = $targetObj->getAttribute($conn_target->{DEST},"I2C_ADDRESS"); - - my $path = $targetObj->getAttribute($conn_target->{SOURCE_PARENT}, - "PHYS_PATH"); + my $path = $targetObj->getAttribute($conn_target->{SOURCE_PARENT}, "PHYS_PATH"); my $mem = $targetObj->getAttribute($conn_target->{DEST_PARENT}, "MEMORY_SIZE_IN_KB"); my $count = 1; # default for VPD SEEPROMs diff --git a/src/usr/targeting/common/target.C b/src/usr/targeting/common/target.C index 15fedd006..244d04993 100644 --- a/src/usr/targeting/common/target.C +++ b/src/usr/targeting/common/target.C @@ -617,7 +617,9 @@ void Target::getAttrTankTargetPosData(uint16_t & o_pos, } else if ((l_element.type == TYPE_PROC) || (l_element.type == TYPE_MEMBUF) || - (l_element.type == TYPE_DIMM)) + (l_element.type == TYPE_DIMM) || + (l_element.type == TYPE_OCMB_CHIP) || + (l_element.type == TYPE_PMIC)) { o_pos = l_element.instance; } @@ -635,7 +637,11 @@ void Target::getAttrTankTargetPosData(uint16_t & o_pos, (l_element.type == TYPE_PPE) || (l_element.type == TYPE_PERV) || (l_element.type == TYPE_PEC) || - (l_element.type == TYPE_PHB)) + (l_element.type == TYPE_PHB) || + (l_element.type == TYPE_OMI) || + (l_element.type == TYPE_MCC) || + (l_element.type == TYPE_OMIC) || + (l_element.type == TYPE_MEM_PORT)) { o_unitPos = l_element.instance; } @@ -745,6 +751,12 @@ void Target::targAssert(TargAssertReason i_reason, "TARGETING::Target::setAttr<0x%7x>: trySetAttr returned false", i_ffdc); break; + case SET_ATTR_FROM_STD_ARR: + TARG_ASSERT(false, + "TARGETING::Target::setAttrFromStdArr<0x%7x>: setAttrFromStdArr " + "returned false", + i_ffdc); + break; case GET_ATTR: TARG_ASSERT(false, "TARGETING::Target::getAttr<0x%7x>: tryGetAttr returned false", @@ -755,6 +767,12 @@ void Target::targAssert(TargAssertReason i_reason, "TARGETING::Target::getAttrAsString<0x%7x>: tryGetAttr returned false", i_ffdc); break; + case GET_ATTR_AS_STD_ARRAY: + TARG_ASSERT(false, + "TARGETING::Target::getAttrAsStdArray<0x%7x>: getAttrAsStdArray returned" + " false", + i_ffdc); + break; case GET_HB_MUTEX_ATTR: TARG_ASSERT(false, "TARGETING::Target::_getHbMutexAttr<0x%7x>: _getAttrPtr returned NULL", diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml index b1ae2e230..e15880f87 100644 --- a/src/usr/targeting/common/xmltohb/attribute_types.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2012,2019 --> +<!-- Contributors Listed Below - COPYRIGHT 2012,2020 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -187,6 +187,62 @@ </simpleType> </attribute> + <enumerationType> + <default>DEFAULT_ALL</default> + <description>Enumeration for the various BPM update behaviors</description> + <enumerator> + <name>DEFAULT_ALL</name> + <value>0x0000</value> + </enumerator> + <enumerator> + <name>SKIP_ALL</name> + <value>0x1010</value> + </enumerator> + <enumerator> + <name>FORCE_ALL</name> + <value>0x1111</value> + </enumerator> + <enumerator> + <name>SKIP_FW</name> + <value>0x1000</value> + </enumerator> + <enumerator> + <name>FORCE_FW</name> + <value>0x1100</value> + </enumerator> + <enumerator> + <name>SKIP_CONFIG</name> + <value>0x0010</value> + </enumerator> + <enumerator> + <name>FORCE_CONFIG</name> + <value>0x0011</value> + </enumerator> + <enumerator> + <name>FORCE_CONFIG_SKIP_FW</name> + <value>0x1011</value> + </enumerator> + <enumerator> + <name>SKIP_CONFIG_FORCE_FW</name> + <value>0x1110</value> + </enumerator> + <id>BPM_UPDATE_BEHAVIOR</id> + </enumerationType> + + <attribute> + <id>BPM_UPDATE_OVERRIDE</id> + <description> + If non-zero then use value to determine which portion of BPM updates to + skip/force/default behavior. + </description> + <simpleType> + <uint16_t/> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <no_export/> + </attribute> + <attribute> <id>BRAZOS_RX_FIFO_OVERRIDE</id> <description> @@ -884,6 +940,54 @@ </attribute> <attribute> + <description>Specifies a target's eeprom content type.</description> + <hasStringConversion/> + <id>EEPROM_CONTENT_TYPE</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <enumeration> + <id>EEPROM_CONTENT_TYPE</id> + </enumeration> + </simpleType> + </attribute> + + <enumerationType> + <default>RAW</default> + <description>Enumeration indicating a target's eeprom + content type. + RAW - eeprom has no specified layout + ISDIMM - uses standard JEDEC layout for DDR memory + IBM_FRUVPD - uses ipz converged vpd layout with records/keywords for + generic FRUs + IBM_MVPD - use ipz converged vpd layout with records/keywords for + processor modules + DDIMM - uses Differential DIMM layout + </description> + <enumerator> + <name>RAW</name> + <value>0</value> + </enumerator> + <enumerator> + <name>ISDIMM</name> + <value>1</value> + </enumerator> + <enumerator> + <name>IBM_FRUVPD</name> + <value>2</value> + </enumerator> + <enumerator> + <name>IBM_MVPD</name> + <value>3</value> + </enumerator> + <enumerator> + <name>DDIMM</name> + <value>4</value> + </enumerator> + <id>EEPROM_CONTENT_TYPE</id> + </enumerationType> + + <attribute> <id>EEPROM_NV_INFO</id> <description>Information needed to address the NV controller on the NVDIMM</description> <complexType> @@ -1179,8 +1283,9 @@ <attribute> <complexType> - <description>Structure to define the addressing for an I2C - slave device.</description> + <description>Structure to define the addressing for an attached I2C + eeprom device that contains secondary VPD info. + </description> <field> <default>physical:sys-0</default> <description>Entity path to the chip that contains the I2C @@ -1189,49 +1294,49 @@ <type>EntityPath</type> </field> <field> - <default>0x80</default> + <default>0xFF</default> <description>Port from the I2C Master device. This is a 6-bit value.</description> <name>port</name> <type>uint8_t</type> </field> <field> - <default>0x80</default> + <default>0xFF</default> <description>Device address on the I2C bus. This is a 7-bit value, but then shifted 1 bit left.</description> <name>devAddr</name> <type>uint8_t</type> </field> <field> - <default>0x80</default> + <default>0xFF</default> <description>I2C master engine. This is a 2-bit value.</description> <name>engine</name> <type>uint8_t</type> </field> <field> - <default>0x02</default> + <default>0xFF</default> <description>The number of bytes a device requires to set its internal address/offset.</description> <name>byteAddrOffset</name> <type>uint8_t</type> </field> <field> - <default>0x0</default> + <default>0xFFFFFFFFFFFFFFFF</default> <description>The number of kilobytes a device can hold. 'Zero' value possible for some devices.</description> <name>maxMemorySizeKB</name> <type>uint64_t</type> </field> <field> - <default>0x01</default> + <default>0xFF</default> <description>The number of chips making up an eeprom device. </description> <name>chipCount</name> <type>uint8_t</type> </field> <field> - <default>0x0</default> + <default>0xFFFFFFFFFFFFFFFF</default> <description>The maximum number of bytes that can be written to a device at one time. 'Zero' value means no maximum value is expected or checked.</description> @@ -1239,7 +1344,7 @@ <type>uint64_t</type> </field> <field> - <default>0xA</default> + <default>0xFFFFFFFFFFFFFFFF</default> <description>The amount of time in milliseconds a device requires on the completion of a write command to update its internal memory.</description> @@ -1264,6 +1369,12 @@ <name>i2cMuxPath</name> <type>EntityPath</type> </field> + <field> + <default>0xFFFFFFFF</default> + <description>Indicates the target's eeprom content type</description> + <name>eepromContentType</name> + <type>uint32_t</type> + </field> </complexType> <description>Information needed to address the EERPROM slaves</description> <id>EEPROM_VPD_BACKUP_INFO</id> @@ -1273,8 +1384,9 @@ <attribute> <complexType> - <description>Structure to define the addressing for an I2C - slave device.</description> + <description>Structure to define the addressing for an attached I2C + eeprom device that contains primary VPD info. + </description> <field> <default>physical:sys-0</default> <description>Entity path to the chip that contains the I2C @@ -1283,28 +1395,28 @@ <type>EntityPath</type> </field> <field> - <default>0x80</default> + <default>0xFF</default> <description>Port from the I2C Master device. This is a 6-bit value.</description> <name>port</name> <type>uint8_t</type> </field> <field> - <default>0x80</default> + <default>0xFF</default> <description>Device address on the I2C bus. This is a 7-bit value, but then shifted 1 bit left.</description> <name>devAddr</name> <type>uint8_t</type> </field> <field> - <default>0x80</default> + <default>0xFF</default> <description>I2C master engine. This is a 2-bit value.</description> <name>engine</name> <type>uint8_t</type> </field> <field> - <default>0x02</default> + <default>0xFF</default> <description> The number of bytes a device requires to set its internal address/offset. DDR4 DIMMs require a special EEPROM @@ -1318,21 +1430,21 @@ <type>uint8_t</type> </field> <field> - <default>0x0</default> + <default>0xFFFFFFFFFFFFFFFF</default> <description>The number of kilobytes a device can hold. 'Zero' value possible for some devices.</description> <name>maxMemorySizeKB</name> <type>uint64_t</type> </field> <field> - <default>0x01</default> + <default>0xFF</default> <description>The number of chips making up an eeprom device. </description> <name>chipCount</name> <type>uint8_t</type> </field> <field> - <default>0x0</default> + <default>0xFFFFFFFFFFFFFFFF</default> <description>The maximum number of bytes that can be written to a device at one time. 'Zero' value means no maximum value is expected or checked.</description> @@ -1340,7 +1452,7 @@ <type>uint64_t</type> </field> <field> - <default>0xA</default> + <default>0xFFFFFFFFFFFFFFFF</default> <description>The amount of time in milliseconds a device requires on the completion of a write command to update its internal memory.</description> @@ -1365,6 +1477,12 @@ <name>i2cMuxPath</name> <type>EntityPath</type> </field> + <field> + <default>0xFFFFFFFF</default> + <description>Indicates the target's eeprom content type</description> + <name>eepromContentType</name> + <type>uint32_t</type> + </field> </complexType> <description>Information needed to address the EEPROM slaves</description> <id>EEPROM_VPD_PRIMARY_INFO</id> @@ -1672,6 +1790,36 @@ </attribute> <attribute> + <description> + Lab-only trigger to force a factory reset of the NVDIMMs. + NOTE: This will erase any saved image and encryption keys. + </description> + <id>FORCE_NVDIMM_RESET</id> + <persistency>volatile-zeroed</persistency> + <readable/> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + </attribute> + + <attribute> + <id>FORCE_SRAM_MMIO_OVER_I2C</id> + <description> + Force inband SRAM access to be over I2C instead of MMIO + This is a way to get data when the MMIO path is not working + (0x00 = use normal path, 0x01 = force i2c path) + </description> + <simpleType> + <uint8_t/> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + </attribute> + + <attribute> <id>FREQ_CORE_CEILING_MHZ</id> <description> The maximum core frequency in MHz. @@ -2208,6 +2356,46 @@ <value>0xB</value> </enumerator> <enumerator> + <name>THERMAL_SENSOR</name> + <value>0x0C</value> + </enumerator> + <enumerator> + <name>SEEPROM_Atmel24c04</name> + <value>0x0D</value> + </enumerator> + <enumerator> + <name>SEEPROM_Atmel24c412</name> + <value>0x0E</value> + </enumerator> + <enumerator> + <name>SEEPROM_Atmel24c32</name> + <value>0x0F</value> + </enumerator> + <enumerator> + <name>SEEPROM_Atmel24c64</name> + <value>0x10</value> + </enumerator> + <enumerator> + <name>SEEPROM_Atmel24c16</name> + <value>0x11</value> + </enumerator> + <enumerator> + <name>NVDIA_GPU</name> + <value>0x12</value> + </enumerator> + <enumerator> + <name>NXP_LPC_Microcontroller_LPC11U35</name> + <value>0x13</value> + </enumerator> + <enumerator> + <name>9550</name> + <value>0x14</value> + </enumerator> + <enumerator> + <name>TCG_I2C_TPM</name> + <value>0x15</value> + </enumerator> + <enumerator> <name>UNKNOWN</name> <value>0xFF</value> </enumerator> @@ -2782,6 +2970,81 @@ <writeable/> </attribute> + <attribute> + <id>KEY_CLEAR_REQUEST</id> + <description> + Indicates types of Key Clear Requests are being made + </description> + <persistency>volatile-zeroed</persistency> + <readable/> + <simpleType> + <enumeration> + <id>KEY_CLEAR_REQUEST</id> + <default>NONE</default> + </enumeration> + </simpleType> + <writeable/> + </attribute> + + <enumerationType> + <id>KEY_CLEAR_REQUEST</id> + <description> + Enum indicating the different possible Key Clear Request values + </description> + <enumerator> + <description> + (Default) Key clear not requested + </description> + <name>NONE</name> + <value>0x0000</value> + </enumerator> + <enumerator> + <description> + Clear/reset all sensitive data controlled by platform firmware + from the system + </description> + <name>ALL</name> + <value>0x8000</value> + </enumerator> + <enumerator> + <description> + This indicates OPAL to clear the OS platform key + </description> + <name>OS_PK</name> + <value>0x4000</value> + </enumerator> + <enumerator> + <description> + This indicates to OPAL/PEF to clear the System Security Officer + certificate + </description> + <name>PEF_SSO</name> + <value>0x2000</value> + </enumerator> + <enumerator> + <description> + This indicates to PowerVM to clear the system key to the default state + </description> + <name>POWERVM_SYSKEY</name> + <value>0x1000</value> + </enumerator> + <enumerator> + <description> + Clear all sensitive data for MFG processing + Only valid on development drivers + </description> + <name>MFG</name> + <value>0x0100</value> + </enumerator> + <enumerator> + <description> + Reserved bits + </description> + <name>RESERVED</name> + <value>0x00FF</value> + </enumerator> + </enumerationType> + <enumerationType> <id>KEY_TRANSITION_STATE</id> <description> @@ -3842,7 +4105,7 @@ <value>48</value> </enumerator> <enumerator> - <name>EXPLORER</name> + <name>OCMB</name> </enumerator> <enumerator> <name>JEDEC</name> @@ -5033,12 +5296,33 @@ <field> <bits>1</bits> <default>0</default> - <description>NVDIMM controller error detected</description> - <name>error_detected</name> + <description>Is OCC active</description> + <name>occ_active</name> <type>uint8_t</type> </field> <field> - <bits>6</bits> + <bits>1</bits> + <default>0</default> + <description>NVDIMM controller fatal error detected</description> + <name>fatal_error_detected</name> + <type>uint8_t</type> + </field> + <field> + <bits>1</bits> + <default>0</default> + <description>NVDIMM controller risky error detected</description> + <name>risky_error_detected</name> + <type>uint8_t</type> + </field> + <field> + <bits>1</bits> + <default>0</default> + <description>NVDIMM encryption error detected</description> + <name>encryption_error_detected</name> + <type>uint8_t</type> + </field> + <field> + <bits>3</bits> <default>0</default> <description>Reserved for future use</description> <name>reserved</name> @@ -5049,6 +5333,88 @@ </attribute> <attribute> + <id>NVDIMM_AUTO_ARM</id> + <description> + 0 - Do not automatically arm all NVDIMMS in the system at runtime + 1 - Automatically arm all NVDIMMS in the system at runtime + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <writeable/> + </attribute> + + <attribute> + <id>NVDIMM_ENCRYPTION_ENABLE</id> + <description> + 0 - Encryption is not enabled on all NVDIMMS in the system + 1 - Encryption is enabled on all NVDIMMS in the system + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <writeable/> + </attribute> + + <attribute> + <id>NVDIMM_ENCRYPTION_KEYS_ANCHOR</id> + <description> + NVDIMM Encryption keys + Bytes 0..31 Random String (RS) + Bytes 32..63 Erase Key (EK) + Bytes 64..95 Access Key (AK) + Set by HWSV, stored in anchor card + Should match NVDIMM_ENCRYPTION_KEYS_FW + </description> + <simpleType> + <array>96</array> + <uint8_t> + <default> + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + </default> + </uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <writeable/> + </attribute> + + <attribute> + <id>NVDIMM_ENCRYPTION_KEYS_FW</id> + <description> + NVDIMM Encryption keys + Bytes 0..31 Random String (RS) + Bytes 32..63 Erase Key (EK) + Bytes 64..95 Access Key (AK) + Set by Hostboot, stored in FSP flash + Should match NVDIMM_ENCRYPTION_KEYS_ANCHOR + </description> + <simpleType> + <array>96</array> + <uint8_t> + <default> + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + </default> + </uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <writeable/> + </attribute> + + <attribute> <id>NV_OPS_TIMEOUT_MSEC</id> <description> NVDIMM timeout value for 6 main operations @@ -5083,10 +5449,16 @@ NVDIMM status flag. This is used to record the status and later report to OPAL/PHYP. Possible values: - 0x08 - contents not preserved (genesis) - 0x04 - contents preserved - 0x02 - failed to preserve contents - 0x01 - unable to preserve future contents + 0x01: Unable to preserve future contents + 0x02: Failed to preserve contents + 0x04: Contents preserved + 0x08: Contents not preserved + 0x10: Contents are encrypted + 0x20: Secure erase verify complete + 0x40: Error detected, but save/restore might work + 0x80: Reserved + 0xFF: Memory is invalid + NOTE: set for virtual SCM devices, does not persist across reboot </description> <simpleType> <uint8_t> @@ -5149,6 +5521,48 @@ <no_export/> </attribute> + <enumerationType> + <default>DEFAULT_ALL</default> + <description>Enumeration for the various OCMB Firmware update behaviors</description> + <enumerator> + <!-- Compare actual and desired versions, update if they do not match --> + <name>CHECK_VERSIONS</name> + <value>0</value> + </enumerator> + <enumerator> + <!-- Force an update regardless of the current version in the hardware --> + <name>FORCE_UPDATE</name> + <value>1</value> + </enumerator> + <enumerator> + <!-- Do not update the firwmare, do not even check the versions --> + <name>PREVENT_UPDATE</name> + <value>2</value> + </enumerator> + <enumerator> + <!-- Compare actual and desired versions, but do not do any updates --> + <name>CHECK_BUT_NO_UPDATE</name> + <value>3</value> + </enumerator> + <id>OCMB_FW_UPDATE_BEHAVIOR</id> + </enumerationType> + + <attribute> + <description> + Force specific behavior for the OCMB Firmware update function. + </description> + <id>OCMB_FW_UPDATE_OVERRIDE</id> + <!-- @fixme-RTC:244420-Should be volatile-zero --> + <persistency>volatile</persistency> + <readable/> + <simpleType> + <uint8_t> + <!-- Cannot use enumeration directly due to override issue --> + <default>2</default> + </uint8_t> + </simpleType> + </attribute> + <attribute> <description> Physical entity path an OMI's associated OMIC parent target @@ -8131,7 +8545,7 @@ </description> <simpleType> <uint16_t> - <default>1</default> + <default>0</default> </uint16_t> </simpleType> <persistency>volatile</persistency> diff --git a/src/usr/targeting/common/xmltohb/attribute_types_hb.xml b/src/usr/targeting/common/xmltohb/attribute_types_hb.xml index d5dbb659c..7d9af5904 100755 --- a/src/usr/targeting/common/xmltohb/attribute_types_hb.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types_hb.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2012,2019 --> +<!-- Contributors Listed Below - COPYRIGHT 2012,2020 --> <!-- [+] Google Inc. --> <!-- [+] International Business Machines Corp. --> <!-- --> @@ -175,6 +175,21 @@ </attribute> <attribute> + <id>DYNAMIC_I2C_DEVICE_ADDRESS</id> + <description> + This attribute is used when a given target could have different + i2c device addresses depending on which manufacture's device we + are using. + </description> + <simpleType> + <uint8_t/> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + </attribute> + + <attribute> <id>EARLY_TESTCASES_ISTEP</id> <description> Indicates which istep we should execute the CXX testcases after, if @@ -230,6 +245,62 @@ <readable/> </attribute> + <enumerationType> + <description> + Enumeration specifying a target's CEC degraded mode domain + </description> + <default>NO</default> + <enumerator> + <name>NO</name> + <value>0</value> + </enumerator> + <enumerator> + <name>BAR_MISMATCH</name> + <value>1</value> + </enumerator> + <id>FORCE_SBE_UPDATE</id> + </enumerationType> + + <attribute> + <id>FORCE_SBE_UPDATE</id> + <description> + Set to non-zero to force a SBE update at various places in the IPL. + </description> + <simpleType> + <enumeration> + <id>FORCE_SBE_UPDATE</id> + <default>NO</default> + </enumeration> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hbOnly/> + </attribute> + + <attribute> + <!-- Need to add this explicitly to handle the Axone case --> + <id>FREQ_MCA_MHZ</id> + <description> + The frequency of the memory controller channel. In synchronous mode, + this is equivalent to ATTR_FREQ_PB_MHZ. This may be independently set + per pair of memory channels if operating in asynchronous mode, + but this configuration is not anticipated. This clock drives the MCU queues, + and all the associated logic that drives the inputs to the DMI and reads + its outputs + </description> + <simpleType> + <uint32_t/> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_FREQ_MCA_MHZ</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> + </attribute> + <attribute> <id>FSI_MASTER_MUTEX</id> <description>Mutex for FSI Master Operations</description> @@ -254,6 +325,78 @@ <hbOnly/> </attribute> + <attribute> + <id>GPIO_INFO_PHYS_PRES</id> + <description>Information needed to address GPIO device that corresponds + to the Physical Presence Detect circuit</description> + <complexType> + <description>Structure to define the addessing for an I2C + slave device.</description> + <field> + <name>i2cMasterPath</name> + <description>Entity path to the chip that contains the I2C + master</description> + <type>EntityPath</type> + <default>physical:sys-0/node-0/proc-0</default> + </field> + <field> + <name>port</name> + <description>Port from the I2C Master device. This is a 6-bit + value.</description> + <type>uint8_t</type> + <default>0</default> + </field> + <field> + <name>devAddr</name> + <description>Device address on the I2C bus. This is a 7-bit value, + but then shifted 1 bit left.</description> + <type>uint8_t</type> + <default>0xC0</default> + </field> + <field> + <name>engine</name> + <description>I2C master engine. This is a 2-bit + value.</description> + <type>uint8_t</type> + <default>2</default> + </field> + <field> + <name>windowOpenPin</name> + <description>Logical GPIO pin number used to open or close the physcial + presence window</description> + <type>uint8_t</type> + <default>0</default> + </field> + <field> + <name>physicalPresencePin</name> + <description>Logical GPIO pin number used to determine if physical + presence was asserted</description> + <type>uint8_t</type> + <default>1</default> + </field> + <!-- i2c Mux Bus Selector Definition --> + <field> + <default>0xFF</default> + <description>Determines which of the N selectable buses the mux + will connect to. OxFF indicates no mux present + or N/A.</description> + <name>i2cMuxBusSelector</name> + <type>uint8_t</type> + </field> + <!-- i2c Mux Path Definition --> + <field> + <!-- NOTE: physical:sys-0 implies that there is no mux in + the bus path for this part. --> + <default>physical:sys-0</default> + <description>Entity path to the I2C mux for this device.</description> + <name>i2cMuxPath</name> + <type>EntityPath</type> + </field> + </complexType> + <persistency>non-volatile</persistency> + <readable/> + </attribute> + <!-- TODO RTC 122856 When support for HB only volatile attributes with non-zero default is implemented, update default value to match the description, Until that happens, code must set the appropriate default if needed. --> @@ -323,6 +466,18 @@ </enumerator> </enumerationType> + <attribute> + <id>HB_MUTEX_SERIALIZE_TEST_LOCK</id> + <description>Hostboot mutex for serializing certain tests</description> + <simpleType> + <hbmutex/> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hbOnly/> + </attribute> + <!-- For POD Testing --> <attribute> <id>HB_MUTEX_TEST_LOCK</id> @@ -932,6 +1087,40 @@ </attribute> <attribute> + <id>NVDIMM_READING_PAGE4</id> + <description> + 0 - Not reading page4 registers + 1 - Reading of page4 registers in progress + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hbOnly/> + </attribute> + + <attribute> + <id>NVDIMM_READING_VENDOR_LOG</id> + <description> + 0 - Not reading vendor log + 1 - Reading of vendor log in progress + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hbOnly/> + </attribute> + + <attribute> <id>OCC_COMMON_AREA_PHYS_ADDR</id> <description> Physical address where OCC Common Area is placed in mainstore. @@ -946,6 +1135,20 @@ </attribute> <attribute> + <id>OCMB_COUNTER_HB</id> + <description> + Tracks the sequence id for OCMB command transactions. + The platform is expected to guarantee a unique value on each read. + </description> + <simpleType> + <uint32_t/> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + </attribute> + + <attribute> <description> While in Secureboot, this value is set to 1 the first time attribute override is attempted and error logged. @@ -972,7 +1175,7 @@ <description>The part number for a particular FRU target</description> <simpleType> <uint8_t/> - <array>20</array> + <array>48</array> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> @@ -1047,6 +1250,72 @@ </attribute> <attribute> + <description>Designates if the Physical Presence Window was Asserted: + 0 - Physiscal Presence was NOT Asserted + 1 - Physical Presence was Asserted + </description> + <id>PHYS_PRES_ASSERTED</id> + <simpleType> + <uint8_t> + <default>0x0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + </attribute> + + <attribute> + <description>Designates if the assertion of Physical Presence should + be faked: + 0 - Do NOT Fake Physical Presence + 1 - Fake Physical Presence + </description> + <id>PHYS_PRES_FAKE_ASSERT</id> + <simpleType> + <uint8_t> + <default>0x0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + </attribute> + + <attribute> + <description>Designates if there is a request to open the Physical Presence + Window: + 0 - No Request to Open Window (ie, do NOT open window) + 1 - Request to Open Window + </description> + <id>PHYS_PRES_REQUEST_OPEN_WINDOW</id> + <simpleType> + <uint8_t> + <default>0x0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + </attribute> + + <attribute> + <id>SBE_ARCH_DUMP_ADDR</id> + <description> + Physical address where SBE Architectued Dump Area is located (per + Hostboot Instance). Set in istep 21 it is only used during + MPIPLs to retrieve the the architected processor state (SPR/GPR) + </description> + <simpleType> + <uint64_t/> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hbOnly/> + </attribute> + + <attribute> <id>SBE_COMM_ADDR</id> <description> Virtual address where SBE Communications are placed in mainstore. diff --git a/src/usr/targeting/common/xmltohb/hb_customized_attrs.xml b/src/usr/targeting/common/xmltohb/hb_customized_attrs.xml index 25daef3dc..6033800d3 100644 --- a/src/usr/targeting/common/xmltohb/hb_customized_attrs.xml +++ b/src/usr/targeting/common/xmltohb/hb_customized_attrs.xml @@ -418,6 +418,7 @@ <no_export/> </attribute> + <!-- Firmware boots rely on the hypervisor/os to enable the NPUs --> <attribute> <id>ATTR_PROC_NPU_PHY0_BAR_ENABLE</id> <default>0</default> @@ -455,6 +456,74 @@ </attribute> <attribute> + <id>ATTR_PROC_NPU_MMIO_BAR_ENABLE</id> + <default>0</default> + <no_export/> + </attribute> + + <attribute> + <id>ATTR_PROC_NPU0_MMIO_BAR_ENABLE</id> + <default>0</default> + <no_export/> + </attribute> + + <attribute> + <id>ATTR_PROC_NPU1_MMIO_BAR_ENABLE</id> + <default>0</default> + <no_export/> + </attribute> + + <attribute> + <id>ATTR_PROC_NPU2_MMIO_BAR_ENABLE</id> + <default>0</default> + <no_export/> + </attribute> + + <attribute> + <id>ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR_OFFSET</id> + <default>0x0000030200000000</default> + <no_export/> + </attribute> + + <attribute> + <id>ATTR_PROC_NPU0_MMIO_BAR_BASE_ADDR_OFFSET</id> + <default>0x0</default> + <no_export/> + </attribute> + + <attribute> + <id>ATTR_PROC_NPU1_MMIO_BAR_BASE_ADDR_OFFSET</id> + <default>0x0</default> + <no_export/> + </attribute> + + <attribute> + <id>ATTR_PROC_NPU2_MMIO_BAR_BASE_ADDR_OFFSET</id> + <default>0x0</default> + <no_export/> + </attribute> + + <attribute> + <id>ATTR_PROC_NPU0_PRI_CONFIG</id> + <default>0x0,0x0,0x0,0x0</default> + <no_export/> + </attribute> + + <attribute> + <id>ATTR_PROC_NPU1_PRI_CONFIG</id> + <default>0x0,0x0,0x0,0x0</default> + <no_export/> + </attribute> + + <attribute> + <id>ATTR_PROC_NPU2_PRI_CONFIG</id> + <default>0x0,0x0,0x0,0x0</default> + <no_export/> + </attribute> + + <!-- end NPU config --> + + <attribute> <id>ATTR_PROC_NX_RNG_BAR_ENABLE</id> <default>0</default> <no_export/> @@ -763,6 +832,34 @@ <writeable/> <persistency>volatile-zeroed</persistency> </attribute> + + <!-- pSeries always runs in FULL_DIMM mode --> + <attribute> + <id>ATTR_MSS_OCMB_HALF_DIMM_MODE</id> + <no_export/> + <default>FULL_DIMM</default> + </attribute> + + <!-- OCMB Endianess attributes --> + <attribute> + <id>ATTR_MSS_OCMB_EXP_STRUCT_ENDIAN</id> + <default>0x1</default> + <no_export/> + </attribute> + <attribute> + <id>ATTR_MSS_OCMB_EXP_STRUCT_MMIO_ENDIAN_CTRL</id> + <default>0x1</default> + <no_export/> + </attribute> + <attribute> + <id>ATTR_MSS_OCMB_EXP_STRUCT_MMIO_WORD_SWAP</id> + <default>NO_SWAP</default> + <no_export/> + </attribute> + <attribute> + <id>ATTR_MSS_OCMB_EXP_OMI_CFG_ENDIAN_CTRL</id> + <no_export/> + </attribute> <!-- ===================================================================== End of customizations definitions ================================================================= --> diff --git a/src/usr/targeting/common/xmltohb/simics_AXONE.system.xml b/src/usr/targeting/common/xmltohb/simics_AXONE.system.xml index 157582ce6..df431c210 100644 --- a/src/usr/targeting/common/xmltohb/simics_AXONE.system.xml +++ b/src/usr/targeting/common/xmltohb/simics_AXONE.system.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2018,2019 --> +<!-- Contributors Listed Below - COPYRIGHT 2018,2020 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -38,12 +38,12 @@ * Each Axone has has 2 MC units * Each MC unit has 2 MI units (a total of 4 per chip) * Each MI unit has 2 MCC units (a total of 8 per chip) - * Each MCC unit has 4 OMI Units (A total of 16 per chip) + * Each MCC unit has 2 OMI Units (A total of 16 per chip) * OMI Units are special as they have two parents (MI + OMIC (more description below)) * Each OMI unit connects to 1 OCMB chip * Each OCMB unit contains 1 MEM_PORT unit * Each MEM_PORT unit connects to 2 DIMMS (Only 1 dimm per mem_port in this XML) - * Each OCMB chip and its DIMMS are powered by 2 PMIC units + * Each OCMB chip and its DIMMS are powered by up to 4 PMIC units * Each MC unit has 3 OMIC units (a total of 12 per chip) * Each OMIC unit contains 2 or 3 OMI Units (OMIC0/1/3/4 contain 3 and OMIC2/5 contain 2 for a total of 16 per chip) * OMI Units are special as they have two parents (OMIC + MCC (described above)) @@ -53,13 +53,19 @@ * PEC 2 has 3 PHBs * Each Axone has 1 XBUS chiplet (1 XBUS Chiplet translates to multiple xbus units) * Each Axone has 4 OBUS (OB0 to OB3) - * Each OBUS has 3 OBUS_BRICK + * Each OBUS has up to 2 OBUS_BRICKs + * OBUS0 has 2 OBUS_BRICKs + * OBUS1 has 1 OBUS_BRICK + * OBUS2 has 1 OBUS_BRICK + * OBUS3 has 2 OBUS_BRICKs + * Each Axone has 3 NPU units, each associated with 2 OBUS_BRICKs + * NPU0 is associated with OBUS0, used for NVLINK ( 4 x4 links). + * NPU1 is associated with OBUS1/2, used for OpenCAPI ( 1 x8 link). + * NPU2 is associated with OBUS3, used for NVLINK ( 4 x4 links). * Each Axone has 21 PPE units (including the SBE): * 1 SBE, 1 Powerbus/Fabric PPE, 4 GPEs, 12 CMEs, and 3 IO PPEs. * Each chiplet existing in an Axone has 1 equivalent PERV unit - * Each Axone has 2 CAPP units ##TBD## has 2 sys0node0proc0capp0 units - * with same target ID...input MRW has capp0 and capp1...something - * wrong in the processMrw.pl (same observed for Witherspoon) + * Each Axone has 1 CAPP unit * Each Axone has 1 OCC unit - p9Proc0(axone chip) @@ -195,7 +201,7 @@ </attribute> <attribute> <id>ASYNC_NEST_FREQ_MHZ</id> - <default>0xFFFF</default> + <default>2000</default> </attribute> <attribute> <id>HB_SETTINGS</id> @@ -538,7 +544,7 @@ <default>400,400,0,0,0,0,0,0,0,0,0,0,0, 400,400,400,400,0,0,0,0,0,0,0,0,0, 400,400,0,0,0,0,0,0,0,0,0,0,0, - 400,400,400,0,0,0,0,0,0,0,0,0,0</default> + 400,400,400,400,400,400,400,400,400,0,0,0,0</default> </attribute> <attribute> <id>MRU_ID</id> @@ -631,8 +637,243 @@ <id>VPD_REC_NUM</id> <default>0</default> </attribute> + <attribute> + <id>FREQ_OMI_MHZ</id> + <default>25600</default> + </attribute> </targetInstance> +<targetInstance> + <id>sys0node0proc1</id> + <type>chip-processor-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1</default> + </attribute> + <attribute> + <id>ALTFSI_MASTER_CHIP</id> + <default>physical:sys-0</default> + </attribute> + <attribute> + <id>ALTFSI_MASTER_PORT</id> + <default>0x1</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>CHIP</default> + </attribute> + <attribute> + <id>EEPROM_SBE_BACKUP_INFO</id> + <default> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>chipCount</id><value>0x04</value></field> + <field><id>devAddr</id><value>0xA8</value></field> + <field><id>engine</id><value>1</value></field> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>maxMemorySizeKB</id><value>0x100</value></field> + <field><id>port</id><value>3</value></field> + <field><id>writeCycleTime</id><value>0x0A</value></field> + <field><id>writePageSize</id><value>0x80</value></field> + </default> + </attribute> + <attribute> + <id>EEPROM_SBE_PRIMARY_INFO</id> + <default> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>chipCount</id><value>0x04</value></field> + <field><id>devAddr</id><value>0xA8</value></field> + <field><id>engine</id><value>1</value></field> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>maxMemorySizeKB</id><value>0x100</value></field> + <field><id>port</id><value>1</value></field> + <field><id>writeCycleTime</id><value>0x0A</value></field> + <field><id>writePageSize</id><value>0x80</value></field> + </default> + </attribute> + <attribute> + <id>EEPROM_VPD_BACKUP_INFO</id> + <default> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <!-- Note: that there is actually two 64KB chips associated with the MVPD SEEPROM + but Hostboot should never access the second chip --> + <field><id>chipCount</id><value>0x01</value></field> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>engine</id><value>1</value></field> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>maxMemorySizeKB</id><value>0x40</value></field> + <field><id>port</id><value>2</value></field> + <field><id>writeCycleTime</id><value>0x0A</value></field> + <field><id>writePageSize</id><value>0x80</value></field> + </default> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + <default> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <!-- Note: that there is actually two 64KB chips associated with the MVPD SEEPROM + but Hostboot should never access the second chip --> + <field><id>chipCount</id><value>0x01</value></field> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>engine</id><value>1</value></field> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>maxMemorySizeKB</id><value>0x40</value></field> + <field><id>port</id><value>0</value></field> + <field><id>writeCycleTime</id><value>0x0A</value></field> + <field><id>writePageSize</id><value>0x80</value></field> + </default> + </attribute> + <attribute> + <id>FABRIC_CHIP_ID</id> + <default>1</default> + </attribute> + <attribute> + <id>FABRIC_GROUP_ID</id> + <default>0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu:k0:n0:s0:p01</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>1</default> + </attribute> + <attribute> + <id>FSI_MASTER_CHIP</id> + <default>physical:sys-0/node-0/proc-0</default> + </attribute> + <attribute> + <id>FSI_MASTER_PORT</id> + <default>0x1</default> + </attribute> + <attribute> + <id>FSI_MASTER_TYPE</id> + <default>MFSI</default> + </attribute> + <attribute> + <id>FSI_OPTION_FLAGS</id> + <default> + <field><id>flipPort</id><value>0</value></field> + <field><id>reserved</id><value>0</value></field> + </default> + </attribute> + <attribute> + <id>FSI_SLAVE_CASCADE</id> + <default>0</default> + </attribute> + <attribute> + <id>FSP_BASE_ADDR</id> + <default>0x0006070100000000</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00050001</default> + </attribute> + <attribute> + <id>I2C_BUS_SPEED_ARRAY</id> + <default>400,400,0,0,0,0,0,0,0,0,0,0,0, + 400,400,400,400,0,0,0,0,0,0,0,0,0, + 400,400,0,0,0,0,0,0,0,0,0,0,0, + 400,400,400,400,400,400,400,400,400,0,0,0,0</default> + </attribute> + <attribute> + <id>MRU_ID</id> + <default>0x00010000</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>1</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1</default> + </attribute> + <attribute> + <id>POSITION</id> + <default>1</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>PROC_EFF_FABRIC_CHIP_ID</id> + <default>0</default> + </attribute> + <attribute> + <id>PROC_EFF_FABRIC_GROUP_ID</id> + <default>0</default> + </attribute> + <attribute> + <id>PROC_MASTER_TYPE</id> + <default>NOT_MASTER</default> + </attribute> + <attribute> + <id>PROC_R_DISTLOSS_VCS_UOHM</id> + <default>0x640</default> + </attribute> + <attribute> + <id>PROC_R_DISTLOSS_VDD_UOHM</id> + <default>0xAA</default> + </attribute> + <attribute> + <id>PROC_R_DISTLOSS_VDN_UOHM</id> + <default>0xAA</default> + </attribute> + <attribute> + <id>PROC_R_LOADLINE_VCS_UOHM</id> + <default>0x1F4</default> + </attribute> + <attribute> + <id>PROC_R_LOADLINE_VDD_UOHM</id> + <default>0x1F4</default> + </attribute> + <attribute> + <id>PROC_R_LOADLINE_VDN_UOHM</id> + <default>0x1F4</default> + </attribute> + <attribute> + <id>PROC_VRM_VOFFSET_VCS_UV</id> + <default>0x30D4</default> + </attribute> + <attribute> + <id>PROC_VRM_VOFFSET_VDD_UV</id> + <default>0x30D4</default> + </attribute> + <attribute> + <id>PROC_VRM_VOFFSET_VDN_UV</id> + <default>0x30D4</default> + </attribute> + <attribute> + <id>SCOM_SWITCHES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>useFsiScom</id><value>0</value></field> + <field><id>useInbandScom</id><value>0</value></field> + <field><id>useSbeScom</id><value>1</value></field> + <field><id>useXscom</id><value>0</value></field> + </default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PROC</default> + </attribute> + <attribute> + <id>VPD_REC_NUM</id> + <default>1</default> + </attribute> + <attribute> + <id>FREQ_OMI_MHZ</id> + <default>25600</default> + </attribute> +</targetInstance> + + <!-- ===================================================================== --> <!-- EQ Units --> <!-- ===================================================================== --> @@ -1008,6 +1249,228 @@ </attribute> </targetInstance> +<targetInstance> + <id>sys0node0proc1eq0</id> + <type>unit-eq-power9</type> + <attribute><id>HUID</id><default>0x00230006</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.eq:k0:n0:s0:p01:c0</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-0</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>6</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>6</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-16</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x10</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq1</id> + <type>unit-eq-power9</type> + <attribute><id>HUID</id><default>0x00230007</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.eq:k0:n0:s0:p01:c1</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-1</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>7</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>7</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-17</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x11</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq2</id> + <type>unit-eq-power9</type> + <attribute><id>HUID</id><default>0x00230008</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.eq:k0:n0:s0:p01:c2</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-2</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-2</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>8</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>8</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-18</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x12</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq3</id> + <type>unit-eq-power9</type> + <attribute><id>HUID</id><default>0x00230009</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.eq:k0:n0:s0:p01:c3</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-3</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-3</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>9</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>9</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-19</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x13</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq4</id> + <type>unit-eq-power9</type> + <attribute><id>HUID</id><default>0x0023000A</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.eq:k0:n0:s0:p01:c4</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-4</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-4</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>10</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>10</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-20</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>4</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x14</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq5</id> + <type>unit-eq-power9</type> + <attribute><id>HUID</id><default>0x0023000B</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.eq:k0:n0:s0:p01:c5</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-5</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-5</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>11</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>11</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-21</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>5</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x15</default> + </attribute> +</targetInstance> + <!-- ===================================================================== --> <!-- EX Units --> <!-- ===================================================================== --> @@ -1755,6 +2218,402 @@ </attribute> </targetInstance> +<targetInstance> + <id>sys0node0proc1eq0ex0</id> + <type>unit-ex-power9</type> + <attribute><id>HUID</id><default>0x0006000C</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.ex:k0:n0:s0:p01:c0</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-0/ex-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-0/ex-0</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>12</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>12</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x10</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq0ex1</id> + <type>unit-ex-power9</type> + <attribute><id>HUID</id><default>0x0006000D</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.ex:k0:n0:s0:p01:c1</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-0/ex-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-0/ex-1</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>13</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>13</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x10</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq1ex0</id> + <type>unit-ex-power9</type> + <attribute><id>HUID</id><default>0x0006000E</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.ex:k0:n0:s0:p01:c2</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-1/ex-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-1/ex-0</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>14</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>14</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x11</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq1ex1</id> + <type>unit-ex-power9</type> + <attribute><id>HUID</id><default>0x0006000F</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.ex:k0:n0:s0:p01:c3</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-1/ex-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-1/ex-1</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>15</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>15</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x11</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq2ex0</id> + <type>unit-ex-power9</type> + <attribute><id>HUID</id><default>0x00060010</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.ex:k0:n0:s0:p01:c4</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-2/ex-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-2/ex-0</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>16</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>16</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>4</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x12</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq2ex1</id> + <type>unit-ex-power9</type> + <attribute><id>HUID</id><default>0x00060011</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.ex:k0:n0:s0:p01:c5</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-2/ex-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-2/ex-1</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>17</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>17</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>5</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x12</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq3ex0</id> + <type>unit-ex-power9</type> + <attribute><id>HUID</id><default>0x00060012</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.ex:k0:n0:s0:p01:c6</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-3/ex-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-3/ex-0</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>18</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>18</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>6</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x13</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq3ex1</id> + <type>unit-ex-power9</type> + <attribute><id>HUID</id><default>0x00060013</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.ex:k0:n0:s0:p01:c7</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-3/ex-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-3/ex-1</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>19</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>19</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>7</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x13</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq4ex0</id> + <type>unit-ex-power9</type> + <attribute><id>HUID</id><default>0x00060014</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.ex:k0:n0:s0:p01:c8</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-4/ex-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-4/ex-0</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>20</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>20</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>8</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x14</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq4ex1</id> + <type>unit-ex-power9</type> + <attribute><id>HUID</id><default>0x00060015</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.ex:k0:n0:s0:p01:c9</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-4/ex-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-4/ex-1</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>21</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>21</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>9</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x14</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq5ex0</id> + <type>unit-ex-power9</type> + <attribute><id>HUID</id><default>0x00060016</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.ex:k0:n0:s0:p01:c10</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-5/ex-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-5/ex-0</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>22</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>22</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>10</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x15</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq5ex1</id> + <type>unit-ex-power9</type> + <attribute><id>HUID</id><default>0x00060017</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.ex:k0:n0:s0:p01:c11</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-5/ex-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-5/ex-1</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>23</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>23</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>11</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x15</default> + </attribute> +</targetInstance> + <!-- ===================================================================== --> <!-- Core Units --> <!-- ===================================================================== --> @@ -3126,9 +3985,898 @@ </attribute> </targetInstance> +<targetInstance> + <id>sys0node0proc1eq0ex0core0</id> + <type>unit-core-power9</type> + <attribute><id>HUID</id><default>0x00070018</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.core:k0:n0:s0:p01:c0</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-0/ex-0/core-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-0/ex-0/core-0</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>24</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>24</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-32</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x20</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq0ex0core1</id> + <type>unit-core-power9</type> + <attribute><id>HUID</id><default>0x00070019</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.core:k0:n0:s0:p01:c1</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-0/ex-0/core-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-0/ex-0/core-1</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>25</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>25</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-33</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x21</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq0ex1core0</id> + <type>unit-core-power9</type> + <attribute><id>HUID</id><default>0x0007001A</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.core:k0:n0:s0:p01:c2</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-0/ex-1/core-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-0/ex-1/core-0</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>26</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>26</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-34</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x22</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq0ex1core1</id> + <type>unit-core-power9</type> + <attribute><id>HUID</id><default>0x0007001B</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.core:k0:n0:s0:p01:c3</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-0/ex-1/core-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-0/ex-1/core-1</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>27</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>27</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-35</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x23</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq1ex0core0</id> + <type>unit-core-power9</type> + <attribute><id>HUID</id><default>0x0007001C</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.core:k0:n0:s0:p01:c4</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-1/ex-0/core-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-1/ex-0/core-0</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>28</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>28</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-36</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>4</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x24</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq1ex0core1</id> + <type>unit-core-power9</type> + <attribute><id>HUID</id><default>0x0007001D</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.core:k0:n0:s0:p01:c5</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-1/ex-0/core-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-1/ex-0/core-1</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>29</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>29</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-37</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>5</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x25</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq1ex1core0</id> + <type>unit-core-power9</type> + <attribute><id>HUID</id><default>0x0007001E</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.core:k0:n0:s0:p01:c6</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-1/ex-1/core-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-1/ex-1/core-0</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>30</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>30</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-38</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>6</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x26</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq1ex1core1</id> + <type>unit-core-power9</type> + <attribute><id>HUID</id><default>0x0007001F</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.core:k0:n0:s0:p01:c7</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-1/ex-1/core-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-1/ex-1/core-1</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>31</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>31</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-39</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>7</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x27</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq2ex0core0</id> + <type>unit-core-power9</type> + <attribute><id>HUID</id><default>0x00070020</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.core:k0:n0:s0:p01:c8</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-2/ex-0/core-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-2/ex-0/core-0</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>32</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>32</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-40</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>8</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x28</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq2ex0core1</id> + <type>unit-core-power9</type> + <attribute><id>HUID</id><default>0x00070021</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.core:k0:n0:s0:p01:c9</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-2/ex-0/core-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-2/ex-0/core-1</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>33</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>33</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-41</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>9</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x29</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq2ex1core0</id> + <type>unit-core-power9</type> + <attribute><id>HUID</id><default>0x00070022</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.core:k0:n0:s0:p01:c10</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-2/ex-1/core-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-2/ex-1/core-0</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>34</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>34</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-42</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>10</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x2A</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq2ex1core1</id> + <type>unit-core-power9</type> + <attribute><id>HUID</id><default>0x00070023</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.core:k0:n0:s0:p01:c11</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-2/ex-1/core-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-2/ex-1/core-1</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>35</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>35</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-43</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>11</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x2B</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq3ex0core0</id> + <type>unit-core-power9</type> + <attribute><id>HUID</id><default>0x00070024</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.core:k0:n0:s0:p01:c12</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-3/ex-0/core-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-3/ex-0/core-0</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>36</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>36</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-44</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>12</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x2C</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq3ex0core1</id> + <type>unit-core-power9</type> + <attribute><id>HUID</id><default>0x00070025</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.core:k0:n0:s0:p01:c13</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-3/ex-0/core-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-3/ex-0/core-1</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>37</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>37</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-45</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>13</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x2D</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq3ex1core0</id> + <type>unit-core-power9</type> + <attribute><id>HUID</id><default>0x00070026</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.core:k0:n0:s0:p01:c14</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-3/ex-1/core-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-3/ex-1/core-0</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>38</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>38</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-46</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>14</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x2E</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq3ex1core1</id> + <type>unit-core-power9</type> + <attribute><id>HUID</id><default>0x00070027</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.core:k0:n0:s0:p01:c15</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-3/ex-1/core-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-3/ex-1/core-1</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>39</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>39</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-47</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>15</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x2F</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq4ex0core0</id> + <type>unit-core-power9</type> + <attribute><id>HUID</id><default>0x00070028</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.core:k0:n0:s0:p01:c16</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-4/ex-0/core-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-4/ex-0/core-0</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>40</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>40</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-48</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>16</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x30</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq4ex0core1</id> + <type>unit-core-power9</type> + <attribute><id>HUID</id><default>0x00070029</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.core:k0:n0:s0:p01:c17</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-4/ex-0/core-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-4/ex-0/core-1</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>41</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>41</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-49</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>17</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x31</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq4ex1core0</id> + <type>unit-core-power9</type> + <attribute><id>HUID</id><default>0x0007002A</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.core:k0:n0:s0:p01:c18</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-4/ex-1/core-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-4/ex-1/core-0</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>42</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>42</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-50</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>18</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x32</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq4ex1core1</id> + <type>unit-core-power9</type> + <attribute><id>HUID</id><default>0x0007002B</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.core:k0:n0:s0:p01:c19</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-4/ex-1/core-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-4/ex-1/core-1</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>43</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>43</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-51</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>19</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x33</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq5ex0core0</id> + <type>unit-core-power9</type> + <attribute><id>HUID</id><default>0x0007002C</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.core:k0:n0:s0:p01:c20</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-5/ex-0/core-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-5/ex-0/core-0</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>44</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>44</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-52</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>20</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x34</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq5ex0core1</id> + <type>unit-core-power9</type> + <attribute><id>HUID</id><default>0x0007002D</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.core:k0:n0:s0:p01:c21</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-5/ex-0/core-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-5/ex-0/core-1</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>45</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>45</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-53</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>21</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x35</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq5ex1core0</id> + <type>unit-core-power9</type> + <attribute><id>HUID</id><default>0x0007002E</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.core:k0:n0:s0:p01:c22</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-5/ex-1/core-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-5/ex-1/core-0</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>46</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>46</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-54</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>22</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x36</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1eq5ex1core1</id> + <type>unit-core-power9</type> + <attribute><id>HUID</id><default>0x0007002F</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.core:k0:n0:s0:p01:c23</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/eq-5/ex-1/core-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/eq-5/ex-1/core-1</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>47</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>47</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-55</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>23</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x37</default> + </attribute> +</targetInstance> + <!-- ===================================================================== --> <!-- OBUS Units --> <!-- ===================================================================== --> + <targetInstance> <id>sys0node0proc0obus0</id> <type>unit-obus-axone</type> @@ -3393,6 +5141,270 @@ </attribute> </targetInstance> +<targetInstance> + <id>sys0node0proc1obus0</id> + <type>unit-obus-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/obus-0</default> + </attribute> + <attribute> + <id>PEER_PATH</id> + <default>physical:na</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x09</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.obus:k0:n0:s0:p01:c0</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>4</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00280004</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>4</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-9</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/obus-0</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>OBUS</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1obus1</id> + <type>unit-obus-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/obus-1</default> + </attribute> + <attribute> + <id>PEER_PATH</id> + <default>physical:na</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x0A</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.obus:k0:n0:s0:p01:c1</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>5</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00280005</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>5</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-10</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/obus-1</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>OBUS</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1obus2</id> + <type>unit-obus-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/obus-2</default> + </attribute> + <attribute> + <id>PEER_PATH</id> + <default>physical:na</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x0B</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.obus:k0:n0:s0:p01:c2</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>6</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00280006</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>6</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-11</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/obus-2</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>2</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>OBUS</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1obus3</id> + <type>unit-obus-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/obus-3</default> + </attribute> + <attribute> + <id>PEER_PATH</id> + <default>physical:na</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x0C</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.obus:k0:n0:s0:p01:c3</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>7</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00280007</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>7</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-12</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/obus-3</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>3</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>OBUS</default> + </attribute> +</targetInstance> + <!-- ===================================================================== --> <!-- OBUS_BRICK Units --> <!-- ===================================================================== --> @@ -3487,11 +5499,11 @@ </targetInstance> <targetInstance> - <id>sys0node0proc0obus0obus_brick2</id> + <id>sys0node0proc0obus1obus_brick0</id> <type>unit-obus-brick-axone</type> <attribute> <id>AFFINITY_PATH</id> - <default>affinity:sys-0/node-0/proc-0/obus-0/obus_brick-2</default> + <default>affinity:sys-0/node-0/proc-0/obus-1/obus_brick-0</default> </attribute> <attribute> <id>CHIP_UNIT</id> @@ -3499,7 +5511,7 @@ </attribute> <attribute> <id>CHIPLET_ID</id> - <default>0x09</default> + <default>0x0A</default> </attribute> <attribute> <id>FAPI_NAME</id> @@ -3519,24 +5531,24 @@ </attribute> <attribute> <id>PARENT_PERVASIVE</id> - <default>physical:sys-0/node-0/proc-0/perv-9</default> + <default>physical:sys-0/node-0/proc-0/perv-10</default> </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/proc-0/obus-0/obus_brick-2</default> + <default>physical:sys-0/node-0/proc-0/obus-1/obus_brick-0</default> </attribute> <attribute> <id>REL_POS</id> - <default>2</default> + <default>0</default> </attribute> </targetInstance> <targetInstance> - <id>sys0node0proc0obus1obus_brick0</id> + <id>sys0node0proc0obus2obus_brick0</id> <type>unit-obus-brick-axone</type> <attribute> <id>AFFINITY_PATH</id> - <default>affinity:sys-0/node-0/proc-0/obus-1/obus_brick-0</default> + <default>affinity:sys-0/node-0/proc-0/obus-2/obus_brick-0</default> </attribute> <attribute> <id>CHIP_UNIT</id> @@ -3544,15 +5556,15 @@ </attribute> <attribute> <id>CHIPLET_ID</id> - <default>0x0A</default> + <default>0x0B</default> </attribute> <attribute> <id>FAPI_NAME</id> - <default>pu.obus_brick:k0:n0:s0:p00:c3</default> + <default>pu.obus_brick:k0:n0:s0:p00:c4</default> </attribute> <attribute> <id>HUID</id> - <default>0x00420003</default> + <default>0x00420004</default> </attribute> <attribute> <id>OBUS_SLOT_INDEX</id> @@ -3564,11 +5576,11 @@ </attribute> <attribute> <id>PARENT_PERVASIVE</id> - <default>physical:sys-0/node-0/proc-0/perv-10</default> + <default>physical:sys-0/node-0/proc-0/perv-11</default> </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/proc-0/obus-1/obus_brick-0</default> + <default>physical:sys-0/node-0/proc-0/obus-2/obus_brick-0</default> </attribute> <attribute> <id>REL_POS</id> @@ -3577,11 +5589,11 @@ </targetInstance> <targetInstance> - <id>sys0node0proc0obus1obus_brick1</id> + <id>sys0node0proc0obus3obus_brick0</id> <type>unit-obus-brick-axone</type> <attribute> <id>AFFINITY_PATH</id> - <default>affinity:sys-0/node-0/proc-0/obus-1/obus_brick-1</default> + <default>affinity:sys-0/node-0/proc-0/obus-3/obus_brick-0</default> </attribute> <attribute> <id>CHIP_UNIT</id> @@ -3589,15 +5601,15 @@ </attribute> <attribute> <id>CHIPLET_ID</id> - <default>0x0A</default> + <default>0x0C</default> </attribute> <attribute> <id>FAPI_NAME</id> - <default>pu.obus_brick:k0:n0:s0:p00:c4</default> + <default>pu.obus_brick:k0:n0:s0:p00:c6</default> </attribute> <attribute> <id>HUID</id> - <default>0x00420004</default> + <default>0x00420006</default> </attribute> <attribute> <id>OBUS_SLOT_INDEX</id> @@ -3609,24 +5621,24 @@ </attribute> <attribute> <id>PARENT_PERVASIVE</id> - <default>physical:sys-0/node-0/proc-0/perv-10</default> + <default>physical:sys-0/node-0/proc-0/perv-12</default> </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/proc-0/obus-1/obus_brick-1</default> + <default>physical:sys-0/node-0/proc-0/obus-3/obus_brick-0</default> </attribute> <attribute> <id>REL_POS</id> - <default>1</default> + <default>0</default> </attribute> </targetInstance> <targetInstance> - <id>sys0node0proc0obus1obus_brick2</id> + <id>sys0node0proc0obus3obus_brick1</id> <type>unit-obus-brick-axone</type> <attribute> <id>AFFINITY_PATH</id> - <default>affinity:sys-0/node-0/proc-0/obus-1/obus_brick-2</default> + <default>affinity:sys-0/node-0/proc-0/obus-3/obus_brick-1</default> </attribute> <attribute> <id>CHIP_UNIT</id> @@ -3634,7 +5646,7 @@ </attribute> <attribute> <id>CHIPLET_ID</id> - <default>0x0A</default> + <default>0x0C</default> </attribute> <attribute> <id>FAPI_NAME</id> @@ -3642,7 +5654,7 @@ </attribute> <attribute> <id>HUID</id> - <default>0x00420005</default> + <default>0x00420007</default> </attribute> <attribute> <id>OBUS_SLOT_INDEX</id> @@ -3654,40 +5666,40 @@ </attribute> <attribute> <id>PARENT_PERVASIVE</id> - <default>physical:sys-0/node-0/proc-0/perv-10</default> + <default>physical:sys-0/node-0/proc-0/perv-12</default> </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/proc-0/obus-1/obus_brick-2</default> + <default>physical:sys-0/node-0/proc-0/obus-3/obus_brick-1</default> </attribute> <attribute> <id>REL_POS</id> - <default>3</default> + <default>1</default> </attribute> </targetInstance> <targetInstance> - <id>sys0node0proc0obus2obus_brick0</id> + <id>sys0node0proc1obus0obus_brick0</id> <type>unit-obus-brick-axone</type> <attribute> <id>AFFINITY_PATH</id> - <default>affinity:sys-0/node-0/proc-0/obus-2/obus_brick-0</default> + <default>affinity:sys-0/node-0/proc-1/obus-0/obus_brick-0</default> </attribute> <attribute> <id>CHIP_UNIT</id> - <default>6</default> + <default>0</default> </attribute> <attribute> <id>CHIPLET_ID</id> - <default>0x0B</default> + <default>0x09</default> </attribute> <attribute> <id>FAPI_NAME</id> - <default>pu.obus_brick:k0:n0:s0:p00:c6</default> + <default>pu.obus_brick:k0:n0:s0:p01:c0</default> </attribute> <attribute> <id>HUID</id> - <default>0x00420006</default> + <default>0x00420008</default> </attribute> <attribute> <id>OBUS_SLOT_INDEX</id> @@ -3695,15 +5707,15 @@ </attribute> <attribute> <id>ORDINAL_ID</id> - <default>6</default> + <default>8</default> </attribute> <attribute> <id>PARENT_PERVASIVE</id> - <default>physical:sys-0/node-0/proc-0/perv-11</default> + <default>physical:sys-0/node-0/proc-1/perv-9</default> </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/proc-0/obus-2/obus_brick-0</default> + <default>physical:sys-0/node-0/proc-1/obus-0/obus_brick-0</default> </attribute> <attribute> <id>REL_POS</id> @@ -3712,27 +5724,27 @@ </targetInstance> <targetInstance> - <id>sys0node0proc0obus2obus_brick1</id> + <id>sys0node0proc1obus0obus_brick1</id> <type>unit-obus-brick-axone</type> <attribute> <id>AFFINITY_PATH</id> - <default>affinity:sys-0/node-0/proc-0/obus-2/obus_brick-1</default> + <default>affinity:sys-0/node-0/proc-1/obus-0/obus_brick-1</default> </attribute> <attribute> <id>CHIP_UNIT</id> - <default>7</default> + <default>1</default> </attribute> <attribute> <id>CHIPLET_ID</id> - <default>0x0B</default> + <default>0x09</default> </attribute> <attribute> <id>FAPI_NAME</id> - <default>pu.obus_brick:k0:n0:s0:p00:c7</default> + <default>pu.obus_brick:k0:n0:s0:p01:c1</default> </attribute> <attribute> <id>HUID</id> - <default>0x00420007</default> + <default>0x00420009</default> </attribute> <attribute> <id>OBUS_SLOT_INDEX</id> @@ -3740,15 +5752,15 @@ </attribute> <attribute> <id>ORDINAL_ID</id> - <default>7</default> + <default>9</default> </attribute> <attribute> <id>PARENT_PERVASIVE</id> - <default>physical:sys-0/node-0/proc-0/perv-11</default> + <default>physical:sys-0/node-0/proc-1/perv-9</default> </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/proc-0/obus-2/obus_brick-1</default> + <default>physical:sys-0/node-0/proc-1/obus-0/obus_brick-1</default> </attribute> <attribute> <id>REL_POS</id> @@ -3757,27 +5769,27 @@ </targetInstance> <targetInstance> - <id>sys0node0proc0obus2obus_brick2</id> + <id>sys0node0proc1obus1obus_brick0</id> <type>unit-obus-brick-axone</type> <attribute> <id>AFFINITY_PATH</id> - <default>affinity:sys-0/node-0/proc-0/obus-2/obus_brick-2</default> + <default>affinity:sys-0/node-0/proc-1/obus-1/obus_brick-0</default> </attribute> <attribute> <id>CHIP_UNIT</id> - <default>8</default> + <default>2</default> </attribute> <attribute> <id>CHIPLET_ID</id> - <default>0x0B</default> + <default>0x0A</default> </attribute> <attribute> <id>FAPI_NAME</id> - <default>pu.obus_brick:k0:n0:s0:p00:c8</default> + <default>pu.obus_brick:k0:n0:s0:p01:c2</default> </attribute> <attribute> <id>HUID</id> - <default>0x00420008</default> + <default>0x0042000A</default> </attribute> <attribute> <id>OBUS_SLOT_INDEX</id> @@ -3785,44 +5797,44 @@ </attribute> <attribute> <id>ORDINAL_ID</id> - <default>8</default> + <default>10</default> </attribute> <attribute> <id>PARENT_PERVASIVE</id> - <default>physical:sys-0/node-0/proc-0/perv-11</default> + <default>physical:sys-0/node-0/proc-1/perv-10</default> </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/proc-0/obus-2/obus_brick-2</default> + <default>physical:sys-0/node-0/proc-1/obus-1/obus_brick-0</default> </attribute> <attribute> <id>REL_POS</id> - <default>2</default> + <default>0</default> </attribute> </targetInstance> <targetInstance> - <id>sys0node0proc0obus3obus_brick0</id> + <id>sys0node0proc1obus2obus_brick0</id> <type>unit-obus-brick-axone</type> <attribute> <id>AFFINITY_PATH</id> - <default>affinity:sys-0/node-0/proc-0/obus-3/obus_brick-0</default> + <default>affinity:sys-0/node-0/proc-1/obus-2/obus_brick-0</default> </attribute> <attribute> <id>CHIP_UNIT</id> - <default>9</default> + <default>3</default> </attribute> <attribute> <id>CHIPLET_ID</id> - <default>0x0C</default> + <default>0x0B</default> </attribute> <attribute> <id>FAPI_NAME</id> - <default>pu.obus_brick:k0:n0:s0:p00:c9</default> + <default>pu.obus_brick:k0:n0:s0:p01:c4</default> </attribute> <attribute> <id>HUID</id> - <default>0x00420009</default> + <default>0x0042000B</default> </attribute> <attribute> <id>OBUS_SLOT_INDEX</id> @@ -3830,15 +5842,15 @@ </attribute> <attribute> <id>ORDINAL_ID</id> - <default>9</default> + <default>11</default> </attribute> <attribute> <id>PARENT_PERVASIVE</id> - <default>physical:sys-0/node-0/proc-0/perv-12</default> + <default>physical:sys-0/node-0/proc-1/perv-11</default> </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/proc-0/obus-3/obus_brick-0</default> + <default>physical:sys-0/node-0/proc-1/obus-2/obus_brick-0</default> </attribute> <attribute> <id>REL_POS</id> @@ -3847,15 +5859,15 @@ </targetInstance> <targetInstance> - <id>sys0node0proc0obus3obus_brick1</id> + <id>sys0node0proc1obus3obus_brick0</id> <type>unit-obus-brick-axone</type> <attribute> <id>AFFINITY_PATH</id> - <default>affinity:sys-0/node-0/proc-0/obus-3/obus_brick-1</default> + <default>affinity:sys-0/node-0/proc-1/obus-3/obus_brick-0</default> </attribute> <attribute> <id>CHIP_UNIT</id> - <default>10</default> + <default>4</default> </attribute> <attribute> <id>CHIPLET_ID</id> @@ -3863,11 +5875,11 @@ </attribute> <attribute> <id>FAPI_NAME</id> - <default>pu.obus_brick:k0:n0:s0:p00:c10</default> + <default>pu.obus_brick:k0:n0:s0:p01:c6</default> </attribute> <attribute> <id>HUID</id> - <default>0x0042000A</default> + <default>0x0042000C</default> </attribute> <attribute> <id>OBUS_SLOT_INDEX</id> @@ -3875,32 +5887,32 @@ </attribute> <attribute> <id>ORDINAL_ID</id> - <default>10</default> + <default>12</default> </attribute> <attribute> <id>PARENT_PERVASIVE</id> - <default>physical:sys-0/node-0/proc-0/perv-12</default> + <default>physical:sys-0/node-0/proc-1/perv-12</default> </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/proc-0/obus-3/obus_brick-1</default> + <default>physical:sys-0/node-0/proc-1/obus-3/obus_brick-0</default> </attribute> <attribute> <id>REL_POS</id> - <default>1</default> + <default>0</default> </attribute> </targetInstance> <targetInstance> - <id>sys0node0proc0obus3obus_brick2</id> + <id>sys0node0proc1obus3obus_brick1</id> <type>unit-obus-brick-axone</type> <attribute> <id>AFFINITY_PATH</id> - <default>affinity:sys-0/node-0/proc-0/obus-3/obus_brick-2</default> + <default>affinity:sys-0/node-0/proc-1/obus-3/obus_brick-1</default> </attribute> <attribute> <id>CHIP_UNIT</id> - <default>11</default> + <default>5</default> </attribute> <attribute> <id>CHIPLET_ID</id> @@ -3908,11 +5920,11 @@ </attribute> <attribute> <id>FAPI_NAME</id> - <default>pu.obus_brick:k0:n0:s0:p00:c11</default> + <default>pu.obus_brick:k0:n0:s0:p01:c5</default> </attribute> <attribute> <id>HUID</id> - <default>0x0042000B</default> + <default>0x0042000D</default> </attribute> <attribute> <id>OBUS_SLOT_INDEX</id> @@ -3920,22 +5932,325 @@ </attribute> <attribute> <id>ORDINAL_ID</id> - <default>11</default> + <default>13</default> </attribute> <attribute> <id>PARENT_PERVASIVE</id> - <default>physical:sys-0/node-0/proc-0/perv-12</default> + <default>physical:sys-0/node-0/proc-1/perv-12</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/obus-3/obus_brick-1</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> +</targetInstance> + + +<!-- ===================================================================== --> +<!-- NPU Units for node 0 --> +<!-- ===================================================================== --> +<targetInstance> + <!-- Note : NPU0 covers OBUS0 --> + <id>sys0node0proc0npu0</id> + <type>unit-npu-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-0/npu-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x05</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00430000</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>0</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-0/perv-5</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-0/npu-0</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <!-- Note : NPU1 covers OBUS1 and OBUS2, but OBUS1 isn't wired out --> + <!-- on the Swift configuration --> + <id>sys0node0proc0npu1</id> + <type>unit-npu-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-0/npu-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x05</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00430001</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>1</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-0/perv-5</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-0/npu-1</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>NPU</default> + </attribute> +</targetInstance> + +<targetInstance> + <!-- Note : NPU2 covers OBUS3 --> + <id>sys0node0proc0npu2</id> + <type>unit-npu-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-0/npu-2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x03</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00430002</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>2</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-0/perv-3</default> </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/proc-0/obus-3/obus_brick-2</default> + <default>physical:sys-0/node-0/proc-0/npu-2</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> </attribute> <attribute> <id>REL_POS</id> <default>2</default> </attribute> + <attribute> + <id>TYPE</id> + <default>NPU</default> + </attribute> +</targetInstance> + +<targetInstance> + <!-- Note : NPU0 covers OBUS0 --> + <id>sys0node0proc1npu0</id> + <type>unit-npu-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/npu-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x05</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00430003</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>3</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-5</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/npu-0</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> </targetInstance> +<targetInstance> + <!-- Note : NPU1 covers OBUS1 and OBUS2, but OBUS2 isn't wired out --> + <!-- on the Swift configuration --> + <id>sys0node0proc1npu1</id> + <type>unit-npu-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/npu-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x05</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00430004</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>4</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-5</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/npu-1</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>NPU</default> + </attribute> +</targetInstance> + +<targetInstance> + <!-- Note : NPU2 covers OBUS3 --> + <id>sys0node0proc1npu2</id> + <type>unit-npu-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/npu-2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x03</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00430005</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>5</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-3</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/npu-2</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>2</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>NPU</default> + </attribute> +</targetInstance> + + <!-- ===================================================================== --> <!-- TPM Units for node 0 --> <!-- ===================================================================== --> @@ -4041,7 +6356,7 @@ </attribute> <attribute> <id>FAPI_POS</id> - <default>1</default> + <default>0</default> </attribute> <attribute> <id>HUID</id> @@ -4070,23 +6385,23 @@ </targetInstance> <targetInstance> - <id>sys0node0proc0capp1</id> + <id>sys0node0proc1capp0</id> <type>unit-capp-axone</type> <attribute> <id>AFFINITY_PATH</id> - <default>affinity:sys-0/node-0/proc-0/capp-1</default> + <default>affinity:sys-0/node-0/proc-1/capp-0</default> </attribute> <attribute> <id>CHIP_UNIT</id> - <default>1</default> + <default>0</default> </attribute> <attribute> <id>CHIPLET_ID</id> - <default>4</default> + <default>2</default> </attribute> <attribute> <id>FAPI_NAME</id> - <default>pu.capp:k0:n0:s0:p00:c1</default> + <default>pu.capp:k0:n0:s0:p01:c0</default> </attribute> <attribute> <id>FAPI_POS</id> @@ -4098,7 +6413,7 @@ </attribute> <attribute> <id>MRU_ID</id> - <default>0x02090001</default> + <default>0x02090000</default> </attribute> <attribute> <id>ORDINAL_ID</id> @@ -4106,18 +6421,19 @@ </attribute> <attribute> <id>PARENT_PERVASIVE</id> - <default>physical:sys-0/node-0/proc-0/perv-2</default> + <default>physical:sys-0/node-0/proc-1/perv-2</default> </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/proc-0/capp-1</default> + <default>physical:sys-0/node-0/proc-1/capp-0</default> </attribute> <attribute> <id>REL_POS</id> - <default>1</default> + <default>0</default> </attribute> </targetInstance> + <!-- ===================================================================== --> <!-- OCC Units --> <!-- ===================================================================== --> @@ -4179,6 +6495,65 @@ </attribute> </targetInstance> +<targetInstance> + <id>sys0node0proc1occ0</id> + <type>unit-occ-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/occ-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>NA</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00130001</default> + </attribute> + <attribute> + <id>MRU_ID</id> + <default>0x02010000</default> + </attribute> + <attribute> + <id>OCC_MASTER_CAPABLE</id> + <default>1</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>1</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/occ-0</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>OCC</default> + </attribute> +</targetInstance> + + <!-- ===================================================================== --> <!-- NX Units --> <!-- ===================================================================== --> @@ -4195,7 +6570,7 @@ </attribute> <attribute> <id>AFFINITY_PATH</id> - <default>physical:sys-0/node-0/proc-0/nx-0</default> + <default>affinity:sys-0/node-0/proc-0/nx-0</default> </attribute> <attribute> <id>ORDINAL_ID</id> @@ -4207,6 +6582,32 @@ </attribute> </targetInstance> +<targetInstance> + <id>sys0node0proc1nx0</id> + <type>unit-nx-power9</type> + <attribute><id>HUID</id><default>0x001E0001</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>NA</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/nx-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/nx-0</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + + <!-- ===================================================================== --> <!-- PEC Units --> <!-- ===================================================================== --> @@ -4468,6 +6869,264 @@ </attribute> </targetInstance> +<targetInstance> + <id>sys0node0proc1pec0</id> + <type>unit-pec-power9</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/pec-0</default> + </attribute> + <attribute> + <id>CDM_DOMAIN</id> + <default>IO</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0xD</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.pec:k0:n0:s0:p01:c0</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>3</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002D0003</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>3</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-13</default> + </attribute> + <attribute> + <id>PEC_PCIE_IOP_SWAP_NON_BIFURCATED</id> + <default>0</default> + </attribute> + <attribute> + <id>PEC_PCIE_LANE_MASK_NON_BIFURCATED</id> + <default>0xFFFF,0x0000,0x0000,0x0000</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/pec-0</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_CONFIG</id> + <default>1</default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_SWAP</id> + <default>0</default> + </attribute> + <attribute> + <id>PROC_PCIE_LANE_MASK</id> + <default>,0x0000,0x0000,0x0000</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PEC</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1pec1</id> + <type>unit-pec-power9</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/pec-1</default> + </attribute> + <attribute> + <id>CDM_DOMAIN</id> + <default>IO</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0xE</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.pec:k0:n0:s0:p01:c1</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>4</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002D0004</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>4</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-14</default> + </attribute> + <attribute> + <id>PEC_PCIE_IOP_SWAP_NON_BIFURCATED</id> + <default>0</default> + </attribute> + <attribute> + <id>PEC_PCIE_LANE_MASK_NON_BIFURCATED</id> + <default>0xFF00,0x0000,0x00FF,0x0000</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/pec-1</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_CONFIG</id> + <default>1</default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_SWAP</id> + <default>0</default> + </attribute> + <attribute> + <id>PROC_PCIE_LANE_MASK</id> + <default>,0x0000,0x0000,0x0000</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PEC</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1pec2</id> + <type>unit-pec-power9</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/pec-2</default> + </attribute> + <attribute> + <id>CDM_DOMAIN</id> + <default>IO</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0xF</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.pec:k0:n0:s0:p00:c2</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>5</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002D0005</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>5</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-15</default> + </attribute> + <attribute> + <id>PEC_PCIE_IOP_SWAP_NON_BIFURCATED</id> + <default>0</default> + </attribute> + <attribute> + <id>PEC_PCIE_LANE_MASK_NON_BIFURCATED</id> + <default>0xFFFF,0x0000,0x0000,0x0000</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/pec-2</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_CONFIG</id> + <default>1</default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_SWAP</id> + <default>0</default> + </attribute> + <attribute> + <id>PROC_PCIE_LANE_MASK</id> + <default>,0x0000,0x0000,0x0000</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>2</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PEC</default> + </attribute> +</targetInstance> + <!-- ===================================================================== --> <!-- PHB Units --> <!-- ===================================================================== --> @@ -4891,6 +7550,426 @@ </attribute> </targetInstance> +<targetInstance> + <id>sys0node0proc1pec0phb0</id> + <type>unit-phb-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/pec-0/phb-0</default> + </attribute> + <attribute> + <id>CDM_DOMAIN</id> + <default>IO</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0xD</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.phb:k0:n0:s0:p01:c0</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>6</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002E0006</default> + </attribute> + <attribute> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + <default>0x00000031</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>6</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-13</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/pec-0/phb-0</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PHB</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1pec1phb0</id> + <type>unit-phb-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/pec-1/phb-0</default> + </attribute> + <attribute> + <id>CDM_DOMAIN</id> + <default>IO</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0xE</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.phb:k0:n0:s0:p01:c1</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>7</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002E0007</default> + </attribute> + <attribute> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + <default>0x00000031</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>7</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-14</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/pec-1/phb-0</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PHB</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1pec1phb1</id> + <type>unit-phb-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/pec-1/phb-1</default> + </attribute> + <attribute> + <id>CDM_DOMAIN</id> + <default>IO</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0xE</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.phb:k0:n0:s0:p01:c2</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>8</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002E0008</default> + </attribute> + <attribute> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + <default>0x00000031</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>8</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-14</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/pec-1/phb-1</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PHB</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1pec2phb0</id> + <type>unit-phb-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/pec-2/phb-0</default> + </attribute> + <attribute> + <id>CDM_DOMAIN</id> + <default>IO</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0xF</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.phb:k0:n0:s0:p01:c3</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>9</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002E0009</default> + </attribute> + <attribute> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + <default>0x00000031</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>9</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-15</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/pec-2/phb-0</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PHB</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1pec2phb1</id> + <type>unit-phb-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/pec-2/phb-1</default> + </attribute> + <attribute> + <id>CDM_DOMAIN</id> + <default>IO</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>4</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0xF</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.phb:k0:n0:s0:p01:c4</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>10</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002E000A</default> + </attribute> + <attribute> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + <default>0x00000031</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>10</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-15</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/pec-2/phb-1</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PHB</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1pec2phb2</id> + <type>unit-phb-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/pec-2/phb-2</default> + </attribute> + <attribute> + <id>CDM_DOMAIN</id> + <default>IO</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>5</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0xF</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.phb:k0:n0:s0:p01:c5</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>11</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002E000B</default> + </attribute> + <attribute> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + <default>0x00000031</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>11</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-15</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/pec-2/phb-2</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>5</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PHB</default> + </attribute> +</targetInstance> + <!-- ===================================================================== --> <!-- PPE Units --> <!-- ===================================================================== --> @@ -6136,6 +9215,1248 @@ </attribute> </targetInstance> +<targetInstance> + <id>sys0node0proc1ppe0</id> + <type>unit-ppe-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/ppe-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.ppe:k0:n0:s0:p01:c0</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>64</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002B0033</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>64</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/ppe-0</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PPE</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1ppe10</id> + <type>unit-ppe-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/ppe-10</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>10</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.ppe:k0:n0:s0:p01:c10</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>74</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002B003D</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>74</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/ppe-10</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>10</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PPE</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1ppe11</id> + <type>unit-ppe-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/ppe-11</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>11</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.ppe:k0:n0:s0:p01:c11</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>75</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002B003E</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>75</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/ppe-11</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>11</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PPE</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1ppe12</id> + <type>unit-ppe-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/ppe-12</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>12</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.ppe:k0:n0:s0:p01:c12</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>76</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002B003F</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>76</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/ppe-12</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>12</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PPE</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1ppe13</id> + <type>unit-ppe-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/ppe-13</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>13</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.ppe:k0:n0:s0:p01:c13</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>77</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002B0040</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>77</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/ppe-13</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>13</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PPE</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1ppe20</id> + <type>unit-ppe-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/ppe-20</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>20</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.ppe:k0:n0:s0:p01:c20</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>84</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002B0047</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>84</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/ppe-20</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>20</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PPE</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1ppe21</id> + <type>unit-ppe-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/ppe-21</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>21</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.ppe:k0:n0:s0:p01:c21</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>85</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002B0048</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>85</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/ppe-21</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>21</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PPE</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1ppe22</id> + <type>unit-ppe-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/ppe-22</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>22</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.ppe:k0:n0:s0:p01:c22</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>86</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002B0049</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>86</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/ppe-22</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>22</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PPE</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1ppe23</id> + <type>unit-ppe-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/ppe-23</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>23</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.ppe:k0:n0:s0:p01:c23</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>87</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002B004A</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>87</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/ppe-23</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>23</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PPE</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1ppe24</id> + <type>unit-ppe-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/ppe-24</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>24</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.ppe:k0:n0:s0:p01:c24</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>88</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002B004B</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>88</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/ppe-24</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>24</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PPE</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1ppe25</id> + <type>unit-ppe-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/ppe-25</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>25</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.ppe:k0:n0:s0:p01:c25</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>89</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002B004C</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>89</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/ppe-25</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>25</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PPE</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1ppe30</id> + <type>unit-ppe-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/ppe-30</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>30</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.ppe:k0:n0:s0:p01:c30</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>94</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002B0051</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>94</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/ppe-30</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>30</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PPE</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1ppe31</id> + <type>unit-ppe-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/ppe-31</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>31</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.ppe:k0:n0:s0:p01:c31</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>95</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002B0052</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>31</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/ppe-31</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>31</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PPE</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1ppe32</id> + <type>unit-ppe-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/ppe-32</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>32</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.ppe:k0:n0:s0:p01:c32</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>96</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002B0053</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>96</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/ppe-32</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>32</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PPE</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1ppe33</id> + <type>unit-ppe-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/ppe-33</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>33</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.ppe:k0:n0:s0:p01:c33</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>97</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002B0054</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>97</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/ppe-33</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>33</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PPE</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1ppe34</id> + <type>unit-ppe-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/ppe-34</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>34</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.ppe:k0:n0:s0:p01:c34</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>98</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002B0055</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>98</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/ppe-34</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>34</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PPE</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1ppe35</id> + <type>unit-ppe-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/ppe-35</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>35</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.ppe:k0:n0:s0:p01:c35</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>99</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002B0065</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>99</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/ppe-35</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>35</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PPE</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1ppe40</id> + <type>unit-ppe-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/ppe-40</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>40</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.ppe:k0:n0:s0:p01:c40</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>104</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002B005B</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>104</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/ppe-40</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>40</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PPE</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1ppe41</id> + <type>unit-ppe-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/ppe-41</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>41</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.ppe:k0:n0:s0:p01:c41</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>105</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002B005C</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>105</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/ppe-41</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>41</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PPE</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1ppe42</id> + <type>unit-ppe-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/ppe-42</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>42</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.ppe:k0:n0:s0:p01:c42</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>106</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002B005D</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>106</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/ppe-42</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>42</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PPE</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1ppe43</id> + <type>unit-ppe-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/ppe-43</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>43</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.ppe:k0:n0:s0:p01:c43</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>107</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002B005E</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>107</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/ppe-43</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>43</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PPE</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1ppe45</id> + <type>unit-ppe-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/ppe-45</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>45</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.ppe:k0:n0:s0:p01:c45</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>109</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002B0060</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>109</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/ppe-45</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>45</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PPE</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1ppe50</id> + <type>unit-ppe-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/ppe-50</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>50</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.ppe:k0:n0:s0:p01:c50</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>114</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002B0065</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>114</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/ppe-50</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>50</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PPE</default> + </attribute> +</targetInstance> + <!-- ===================================================================== --> <!-- SBE Units --> <!-- ===================================================================== --> @@ -6178,6 +10499,8 @@ <id>PHYS_PATH</id> <default>physical:sys-0/node-0/proc-0/sbe-0</default> </attribute> + <!--The eeprom associated w/ this target will have a valid entry in the EECACHE + that we preload in standalone simics. No cache updates should be needed --> <attribute> <id>PRIMARY_CAPABILITIES</id> <default> @@ -6253,11 +10576,11 @@ </attribute> <attribute> <id>PEER_TARGET</id> - <default>NULL</default> + <default>physical:sys-0/node-0/proc-1/xbus-2</default> </attribute> <attribute> <id>PEER_PATH</id> - <default>physical:na</default> + <default>physical:sys-0/node-0/proc-1/xbus-2</default> </attribute> <attribute> <id>PHYS_PATH</id> @@ -6364,24 +10687,27 @@ </attribute> </targetInstance> +<!-- ===================================================================== --> +<!-- MEMORY SUBSYSTEM --> +<!-- ===================================================================== --> + +<!-- ===================================================================== --> +<!-- MC Units --> +<!-- ===================================================================== --> <targetInstance> - <id>sys0node0proc0xbus2</id> - <type>unit-xbus-axone</type> + <id>sys0node0proc0mc0</id> + <type>unit-mc-axone</type> <attribute> <id>AFFINITY_PATH</id> - <default>affinity:sys-0/node-0/proc-0/xbus-2</default> - </attribute> - <attribute> - <id>CDM_DOMAIN</id> - <default>FABRIC</default> + <default>affinity:sys-0/node-0/proc-0/mc-0</default> </attribute> <attribute> <id>CHIP_UNIT</id> - <default>2</default> + <default>0</default> </attribute> <attribute> <id>CHIPLET_ID</id> - <default>0x06</default> + <default>0x07</default> </attribute> <attribute> <id>CLASS</id> @@ -6389,43 +10715,94 @@ </attribute> <attribute> <id>FAPI_NAME</id> - <default>pu.xbus:k0:n0:s0:p00:c2</default> + <default>pu.mc:k0:n0:s0:p00:c0</default> </attribute> <attribute> <id>FAPI_POS</id> - <default>2</default> + <default>0</default> </attribute> <attribute> <id>HUID</id> - <default>0x000E0002</default> + <default>0x00440000</default> </attribute> <attribute> - <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - <default>0x00000031</default> + <id>ORDINAL_ID</id> + <default>0</default> </attribute> <attribute> - <id>MRU_ID</id> - <default>0x03020002</default> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-0/perv-7</default> </attribute> <attribute> - <id>ORDINAL_ID</id> - <default>2</default> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-0/mc-0</default> </attribute> <attribute> - <id>PARENT_PERVASIVE</id> - <default>physical:sys-0/node-0/proc-0/perv-6</default> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> </attribute> <attribute> - <id>PEER_TARGET</id> - <default>NULL</default> + <id>REL_POS</id> + <default>0</default> </attribute> <attribute> - <id>PEER_PATH</id> - <default>physical:na</default> + <id>TYPE</id> + <default>MC</default> + </attribute> + <attribute> + <id>OMI_INBAND_BAR_BASE_ADDR_OFFSET</id> + <!-- 3TB + 16GB --> + <default>0x30400000000</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc0mc1</id> + <type>unit-mc-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-0/mc-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x08</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.mc:k0:n0:s0:p00:c1</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>1</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00440001</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>1</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-0/perv-8</default> </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/proc-0/xbus-2</default> + <default>physical:sys-0/node-0/proc-0/mc-1</default> </attribute> <attribute> <id>PRIMARY_CAPABILITIES</id> @@ -6438,27 +10815,25 @@ </attribute> <attribute> <id>REL_POS</id> - <default>2</default> + <default>1</default> </attribute> <attribute> <id>TYPE</id> - <default>XBUS</default> + <default>MC</default> + </attribute> + <attribute> + <id>OMI_INBAND_BAR_BASE_ADDR_OFFSET</id> + <!-- 3TB + 48GB --> + <default>0x30C00000000</default> </attribute> </targetInstance> -<!-- ===================================================================== --> -<!-- MEMORY SUBSYSTEM --> -<!-- ===================================================================== --> - -<!-- ===================================================================== --> -<!-- MC Units --> -<!-- ===================================================================== --> <targetInstance> - <id>sys0node0proc0mc0</id> + <id>sys0node0proc1mc0</id> <type>unit-mc-axone</type> <attribute> <id>AFFINITY_PATH</id> - <default>affinity:sys-0/node-0/proc-0/mc-0</default> + <default>affinity:sys-0/node-0/proc-1/mc-0</default> </attribute> <attribute> <id>CHIP_UNIT</id> @@ -6474,27 +10849,27 @@ </attribute> <attribute> <id>FAPI_NAME</id> - <default>pu.mc:k0:n0:s0:p00:c0</default> + <default>pu.mc:k0:n0:s0:p01:c0</default> </attribute> <attribute> <id>FAPI_POS</id> - <default>0</default> + <default>2</default> </attribute> <attribute> <id>HUID</id> - <default>0x00440000</default> + <default>0x00440002</default> </attribute> <attribute> <id>ORDINAL_ID</id> - <default>0</default> + <default>2</default> </attribute> <attribute> <id>PARENT_PERVASIVE</id> - <default>physical:sys-0/node-0/proc-0/perv-7</default> + <default>physical:sys-0/node-0/proc-1/perv-7</default> </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/proc-0/mc-0</default> + <default>physical:sys-0/node-0/proc-1/mc-0</default> </attribute> <attribute> <id>PRIMARY_CAPABILITIES</id> @@ -6521,11 +10896,11 @@ </targetInstance> <targetInstance> - <id>sys0node0proc0mc1</id> + <id>sys0node0proc1mc1</id> <type>unit-mc-axone</type> <attribute> <id>AFFINITY_PATH</id> - <default>affinity:sys-0/node-0/proc-0/mc-1</default> + <default>affinity:sys-0/node-0/proc-1/mc-1</default> </attribute> <attribute> <id>CHIP_UNIT</id> @@ -6541,27 +10916,27 @@ </attribute> <attribute> <id>FAPI_NAME</id> - <default>pu.mc:k0:n0:s0:p00:c1</default> + <default>pu.mc:k0:n0:s0:p01:c1</default> </attribute> <attribute> <id>FAPI_POS</id> - <default>1</default> + <default>3</default> </attribute> <attribute> <id>HUID</id> - <default>0x00440001</default> + <default>0x00440003</default> </attribute> <attribute> <id>ORDINAL_ID</id> - <default>1</default> + <default>3</default> </attribute> <attribute> <id>PARENT_PERVASIVE</id> - <default>physical:sys-0/node-0/proc-0/perv-8</default> + <default>physical:sys-0/node-0/proc-1/perv-8</default> </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/proc-0/mc-1</default> + <default>physical:sys-0/node-0/proc-1/mc-1</default> </attribute> <attribute> <id>PRIMARY_CAPABILITIES</id> @@ -6838,6 +11213,255 @@ </attribute> </targetInstance> +<targetInstance> + <id>sys0node0proc1mc0mi0</id> + <type>unit-mi-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x07</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.mi:k0:n0:s0:p01:c0</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>4</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00260004</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>4</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-7</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-0/mi-0</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>MI</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1mc0mi1</id> + <type>unit-mi-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x07</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.mi:k0:n0:s0:p01:c1</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>5</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00260005</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>5</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-7</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-0/mi-1</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>MI</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1mc1mi0</id> + <type>unit-mi-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-1/mi-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x08</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.mi:k0:n0:s0:p01:c2</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>6</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00260006</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>6</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-8</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-1/mi-0</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>MI</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1mc1mi1</id> + <type>unit-mi-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-1/mi-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x08</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.mi:k0:n0:s0:p01:c3</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>7</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00260007</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>7</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-8</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-1/mi-1</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>MI</default> + </attribute> +</targetInstance> + + <!-- ===================================================================== --> <!-- MCC Units --> <!-- ===================================================================== --> @@ -7337,6 +11961,502 @@ </attribute> </targetInstance> +<targetInstance> + <id>sys0node0proc1mc0mi0mcc0</id> + <type>unit-mcc-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-0/mcc-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x07</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.mcc:k0:n0:s0:p01:c0</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>16</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00490010</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>16</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-7</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-0/mi-0/mcc-0</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>MCC</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1mc0mi0mcc1</id> + <type>unit-mcc-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-0/mcc-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x07</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.mcc:k0:n0:s0:p01:c1</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>17</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00490011</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>17</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-7</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-0/mi-0/mcc-1</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>MCC</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1mc0mi1mcc0</id> + <type>unit-mcc-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-1/mcc-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x07</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.mcc:k0:n0:s0:p01:c2</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>18</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00490012</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>18</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-7</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-0/mi-1/mcc-0</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>MCC</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1mc0mi1mcc1</id> + <type>unit-mcc-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-1/mcc-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x07</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.mcc:k0:n0:s0:p01:c3</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>19</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00490013</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>19</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-7</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-0/mi-1/mcc-1</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>MCC</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1mc1mi0mcc0</id> + <type>unit-mcc-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-1/mi-0/mcc-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>4</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x08</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.mcc:k0:n0:s0:p01:c4</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>20</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00490014</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>20</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-8</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-1/mi-0/mcc-0</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>MCC</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1mc1mi0mcc1</id> + <type>unit-mcc-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-1/mi-0/mcc-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>5</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x08</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.mcc:k0:n0:s0:p01:c5</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>21</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00490015</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>21</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-8</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-1/mi-0/mcc-1</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>MCC</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1mc1mi1mcc0</id> + <type>unit-mcc-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-1/mi-1/mcc-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>6</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x08</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.mcc:k0:n0:s0:p01:c6</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>22</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00490016</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>22</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-8</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-1/mi-1/mcc-0</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>MCC</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1mc1mi1mcc1</id> + <type>unit-mcc-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-1/mi-1/mcc-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>7</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x08</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.mcc:k0:n0:s0:p01:c7</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>23</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00490017</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>23</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-8</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-1/mi-1/mcc-1</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>MCC</default> + </attribute> +</targetInstance> + <!-- ===================================================================== --> <!-- OMI Units --> <!-- ===================================================================== --> @@ -7416,6 +12536,10 @@ <id>OMI_REFCLOCK_SWIZZLE</id> <default>0</default> </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>0</default> + </attribute> </targetInstance> <targetInstance> @@ -7491,6 +12615,10 @@ <id>OMI_REFCLOCK_SWIZZLE</id> <default>1</default> </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>1</default> + </attribute> </targetInstance> <targetInstance> @@ -7566,6 +12694,10 @@ <id>OMI_REFCLOCK_SWIZZLE</id> <default>2</default> </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>1</default> + </attribute> </targetInstance> <targetInstance> @@ -7641,6 +12773,10 @@ <id>OMI_REFCLOCK_SWIZZLE</id> <default>3</default> </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>2</default> + </attribute> </targetInstance> <targetInstance> @@ -7716,6 +12852,10 @@ <id>OMI_REFCLOCK_SWIZZLE</id> <default>4</default> </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>0</default> + </attribute> </targetInstance> <targetInstance> @@ -7791,6 +12931,10 @@ <id>OMI_REFCLOCK_SWIZZLE</id> <default>5</default> </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>1</default> + </attribute> </targetInstance> <targetInstance> @@ -7866,6 +13010,10 @@ <id>OMI_REFCLOCK_SWIZZLE</id> <default>6</default> </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>2</default> + </attribute> </targetInstance> <targetInstance> @@ -7941,6 +13089,10 @@ <id>OMI_REFCLOCK_SWIZZLE</id> <default>7</default> </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>0</default> + </attribute> </targetInstance> <targetInstance> @@ -8016,6 +13168,10 @@ <id>OMI_REFCLOCK_SWIZZLE</id> <default>8</default> </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>0</default> + </attribute> </targetInstance> <targetInstance> @@ -8091,6 +13247,10 @@ <id>OMI_REFCLOCK_SWIZZLE</id> <default>9</default> </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>1</default> + </attribute> </targetInstance> <targetInstance> @@ -8166,6 +13326,10 @@ <id>OMI_REFCLOCK_SWIZZLE</id> <default>10</default> </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>1</default> + </attribute> </targetInstance> <targetInstance> @@ -8213,7 +13377,7 @@ </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/proc-0/mc-1/mi-0/mcc-1/omi-11</default> + <default>physical:sys-0/node-0/proc-0/mc-1/mi-0/mcc-1/omi-1</default> </attribute> <attribute> <id>PRIMARY_CAPABILITIES</id> @@ -8241,6 +13405,10 @@ <id>OMI_REFCLOCK_SWIZZLE</id> <default>11</default> </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>2</default> + </attribute> </targetInstance> <targetInstance> @@ -8316,6 +13484,10 @@ <id>OMI_REFCLOCK_SWIZZLE</id> <default>12</default> </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>0</default> + </attribute> </targetInstance> <targetInstance> @@ -8391,6 +13563,10 @@ <id>OMI_REFCLOCK_SWIZZLE</id> <default>13</default> </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>1</default> + </attribute> </targetInstance> <targetInstance> @@ -8466,6 +13642,10 @@ <id>OMI_REFCLOCK_SWIZZLE</id> <default>14</default> </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>2</default> + </attribute> </targetInstance> <targetInstance> @@ -8541,14 +13721,1286 @@ <id>OMI_REFCLOCK_SWIZZLE</id> <default>15</default> </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1mc0mi0mcc0omi0</id> + <type>unit-omi-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-0/mcc-0/omi-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x07</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.omi:k0:n0:s0:p01:c0</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>16</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00480010</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>16</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-7</default> + </attribute> + <attribute> + <id>OMIC_PARENT</id> + <default>physical:sys-0/node-0/proc-1/mc-0/omic-2</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-0/mi-0/mcc-0/omi-0</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>OMI</default> + </attribute> + <!-- TODO RTC 201493 - Need to remove these sets (all 16 of them) of + OMI_INBAND_BAR_BASE_ADDR_OFFSET once p9a_omi_setup_bars + is working --> + <attribute> + <id>OMI_INBAND_BAR_BASE_ADDR_OFFSET</id> + <!-- 3TB + 16GB --> + <default>0x30400000000</default> + </attribute> + <attribute> + <id>OMI_REFCLOCK_SWIZZLE</id> + <default>0</default> + </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1mc0mi0mcc0omi1</id> + <type>unit-omi-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-0/mcc-0/omi-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x07</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.omi:k0:n0:s0:p01:c1</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>17</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00480011</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>17</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-7</default> + </attribute> + <attribute> + <id>OMIC_PARENT</id> + <default>physical:sys-0/node-0/proc-1/mc-0/omic-2</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-0/mi-0/mcc-0/omi-1</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>OMI</default> + </attribute> + <attribute> + <id>OMI_INBAND_BAR_BASE_ADDR_OFFSET</id> + <!-- 3TB + 18GB --> + <default>0x30480000000</default> + </attribute> + <attribute> + <id>OMI_REFCLOCK_SWIZZLE</id> + <default>1</default> + </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1mc0mi0mcc1omi0</id> + <type>unit-omi-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-0/mcc-1/omi-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x07</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.omi:k0:n0:s0:p01:c2</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>18</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00480012</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>18</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-7</default> + </attribute> + <attribute> + <id>OMIC_PARENT</id> + <default>physical:sys-0/node-0/proc-1/mc-0/omic-1</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-0/mi-0/mcc-1/omi-0</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>OMI</default> + </attribute> + <attribute> + <id>OMI_INBAND_BAR_BASE_ADDR_OFFSET</id> + <!-- 3TB + 24GB --> + <default>0x30600000000</default> + </attribute> + <attribute> + <id>OMI_REFCLOCK_SWIZZLE</id> + <default>2</default> + </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1mc0mi0mcc1omi1</id> + <type>unit-omi-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-0/mcc-1/omi-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x07</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.omi:k0:n0:s0:p01:c3</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>19</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00480013</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>19</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-7</default> + </attribute> + <attribute> + <id>OMIC_PARENT</id> + <default>physical:sys-0/node-0/proc-1/mc-0/omic-1</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-0/mi-0/mcc-1/omi-1</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>OMI</default> + </attribute> + <attribute> + <id>OMI_INBAND_BAR_BASE_ADDR_OFFSET</id> + <!-- 3TB + 26GB --> + <default>0x30680000000</default> + </attribute> + <attribute> + <id>OMI_REFCLOCK_SWIZZLE</id> + <default>3</default> + </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>2</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1mc0mi1mcc0omi0</id> + <type>unit-omi-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-1/mcc-0/omi-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>4</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x07</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.omi:k0:n0:s0:p01:c4</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>20</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00480014</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>20</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-7</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-0/mi-1/mcc-0/omi-0</default> + </attribute> + <attribute> + <id>OMIC_PARENT</id> + <default>physical:sys-0/node-0/proc-1/mc-0/omic-0</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>OMI</default> + </attribute> + <attribute> + <id>OMI_INBAND_BAR_BASE_ADDR_OFFSET</id> + <!-- 3TB + 32GB --> + <default>0x30800000000</default> + </attribute> + <attribute> + <id>OMI_REFCLOCK_SWIZZLE</id> + <default>4</default> + </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1mc0mi1mcc0omi1</id> + <type>unit-omi-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-1/mcc-0/omi-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>5</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x07</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.omi:k0:n0:s0:p01:c5</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>21</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00480015</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>21</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-7</default> + </attribute> + <attribute> + <id>OMIC_PARENT</id> + <default>physical:sys-0/node-0/proc-1/mc-0/omic-0</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-0/mi-1/mcc-0/omi-1</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>OMI</default> + </attribute> + <attribute> + <id>OMI_INBAND_BAR_BASE_ADDR_OFFSET</id> + <!-- 3TB + 34GB --> + <default>0x30880000000</default> + </attribute> + <attribute> + <id>OMI_REFCLOCK_SWIZZLE</id> + <default>5</default> + </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1mc0mi1mcc1omi0</id> + <type>unit-omi-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-1/mcc-1/omi-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>6</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x07</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.omi:k0:n0:s0:p01:c6</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>22</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00480016</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>22</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-7</default> + </attribute> + <attribute> + <id>OMIC_PARENT</id> + <default>physical:sys-0/node-0/proc-1/mc-0/omic-0</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-0/mi-1/mcc-1/omi-0</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>OMI</default> + </attribute> + <attribute> + <id>OMI_INBAND_BAR_BASE_ADDR_OFFSET</id> + <!-- 3TB + 40GB --> + <default>0x30A00000000</default> + </attribute> + <attribute> + <id>OMI_REFCLOCK_SWIZZLE</id> + <default>6</default> + </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>2</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1mc0mi1mcc1omi1</id> + <type>unit-omi-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-1/mcc-1/omi-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>7</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x07</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.omi:k0:n0:s0:p01:c7</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>23</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00480017</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>23</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-7</default> + </attribute> + <attribute> + <id>OMIC_PARENT</id> + <default>physical:sys-0/node-0/proc-1/mc-0/omic-1</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-0/mi-1/mcc-1/omi-1</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>OMI</default> + </attribute> + <attribute> + <id>OMI_INBAND_BAR_BASE_ADDR_OFFSET</id> + <!-- 3TB + 42GB --> + <default>0x30A80000000</default> + </attribute> + <attribute> + <id>OMI_REFCLOCK_SWIZZLE</id> + <default>7</default> + </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1mc1mi0mcc0omi0</id> + <type>unit-omi-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-1/mi-0/mcc-0/omi-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>8</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x08</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.omi:k0:n0:s0:p01:c8</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>24</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00480018</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>24</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-8</default> + </attribute> + <attribute> + <id>OMIC_PARENT</id> + <default>physical:sys-0/node-0/proc-1/mc-1/omic-2</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-1/mi-0/mcc-0/omi-0</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>OMI</default> + </attribute> + <attribute> + <id>OMI_INBAND_BAR_BASE_ADDR_OFFSET</id> + <!-- 3TB + 48GB --> + <default>0x30C00000000</default> + </attribute> + <attribute> + <id>OMI_REFCLOCK_SWIZZLE</id> + <default>8</default> + </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>0</default> + </attribute> </targetInstance> +<targetInstance> + <id>sys0node0proc1mc1mi0mcc0omi1</id> + <type>unit-omi-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-1/mi-0/mcc-0/omi-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>9</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x08</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.omi:k0:n0:s0:p01:c9</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>25</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x00480019</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>25</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-8</default> + </attribute> + <attribute> + <id>OMIC_PARENT</id> + <default>physical:sys-0/node-0/proc-1/mc-1/omic-2</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-1/mi-0/mcc-0/omi-1</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>OMI</default> + </attribute> + <attribute> + <id>OMI_INBAND_BAR_BASE_ADDR_OFFSET</id> + <!-- 3TB + 50GB --> + <default>0x30C80000000</default> + </attribute> + <attribute> + <id>OMI_REFCLOCK_SWIZZLE</id> + <default>9</default> + </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1mc1mi0mcc1omi0</id> + <type>unit-omi-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-1/mi-0/mcc-1/omi-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>10</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x08</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.omi:k0:n0:s0:p01:c10</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>26</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x0048001A</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>26</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-8</default> + </attribute> + <attribute> + <id>OMIC_PARENT</id> + <default>physical:sys-0/node-0/proc-1/mc-1/omic-1</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-1/mi-0/mcc-1/omi-0</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>OMI</default> + </attribute> + <attribute> + <id>OMI_INBAND_BAR_BASE_ADDR_OFFSET</id> + <!-- 3TB + 56GB --> + <default>0x30E00000000</default> + </attribute> + <attribute> + <id>OMI_REFCLOCK_SWIZZLE</id> + <default>10</default> + </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1mc1mi0mcc1omi1</id> + <type>unit-omi-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-1/mi-0/mcc-1/omi-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>11</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x08</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.omi:k0:n0:s0:p01:c11</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>27</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x0048001B</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>27</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-8</default> + </attribute> + <attribute> + <id>OMIC_PARENT</id> + <default>physical:sys-0/node-0/proc-1/mc-1/omic-1</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-1/mi-0/mcc-1/omi-1</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>OMI</default> + </attribute> + <attribute> + <id>OMI_INBAND_BAR_BASE_ADDR_OFFSET</id> + <!-- 3TB + 58GB --> + <default>0x30E80000000</default> + </attribute> + <attribute> + <id>OMI_REFCLOCK_SWIZZLE</id> + <default>11</default> + </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>2</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1mc1mi1mcc0omi0</id> + <type>unit-omi-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-1/mi-1/mcc-0/omi-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>12</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x08</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.omi:k0:n0:s0:p01:c12</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>28</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x0048001C</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>28</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-8</default> + </attribute> + <attribute> + <id>OMIC_PARENT</id> + <default>physical:sys-0/node-0/proc-1/mc-1/omic-0</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-1/mi-1/mcc-0/omi-0</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>OMI</default> + </attribute> + <attribute> + <id>OMI_INBAND_BAR_BASE_ADDR_OFFSET</id> + <!-- 3TB + 64GB --> + <default>0x31000000000</default> + </attribute> + <attribute> + <id>OMI_REFCLOCK_SWIZZLE</id> + <default>12</default> + </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1mc1mi1mcc0omi1</id> + <type>unit-omi-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-1/mi-1/mcc-0/omi-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>13</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x08</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.omi:k0:n0:s0:p01:c13</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>29</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x0048001D</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>13</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-8</default> + </attribute> + <attribute> + <id>OMIC_PARENT</id> + <default>physical:sys-0/node-0/proc-1/mc-1/omic-0</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-1/mi-1/mcc-0/omi-1</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>OMI</default> + </attribute> + <attribute> + <id>OMI_INBAND_BAR_BASE_ADDR_OFFSET</id> + <!-- 3TB + 66GB --> + <default>0x31080000000</default> + </attribute> + <attribute> + <id>OMI_REFCLOCK_SWIZZLE</id> + <default>13</default> + </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1mc1mi1mcc1omi0</id> + <type>unit-omi-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-1/mi-1/mcc-1/omi-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>14</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x08</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.omi:k0:n0:s0:p01:c14</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>30</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x0048001E</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>30</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-8</default> + </attribute> + <attribute> + <id>OMIC_PARENT</id> + <default>physical:sys-0/node-0/proc-1/mc-1/omic-0</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-1/mi-1/mcc-1/omi-0</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>OMI</default> + </attribute> + <attribute> + <id>OMI_INBAND_BAR_BASE_ADDR_OFFSET</id> + <!-- 3TB + 72GB --> + <default>0x31200000000</default> + </attribute> + <attribute> + <id>OMI_REFCLOCK_SWIZZLE</id> + <default>14</default> + </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>2</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1mc1mi1mcc1omi1</id> + <type>unit-omi-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-1/mi-1/mcc-1/omi-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>15</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x08</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.omi:k0:n0:s0:p01:c15</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>31</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x0048001F</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>31</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-8</default> + </attribute> + <attribute> + <id>OMIC_PARENT</id> + <default>physical:sys-0/node-0/proc-1/mc-1/omic-1</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-1/mi-1/mcc-1/omi-1</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>OMI</default> + </attribute> + <attribute> + <id>OMI_INBAND_BAR_BASE_ADDR_OFFSET</id> + <!-- 3TB + 74GB --> + <default>0x31280000000</default> + </attribute> + <attribute> + <id>OMI_REFCLOCK_SWIZZLE</id> + <default>15</default> + </attribute> + <attribute> + <id>OMI_DL_GROUP_POS</id> + <default>0</default> + </attribute> +</targetInstance> + + <!-- ===================================================================== --> <!-- OCMB_CHIP Units --> <!-- ===================================================================== --> <targetInstance> <id>sys0node0ocmb0</id> - <type>chip-ocmb-explorer</type> + <type>chip-ocmb</type> <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mc-0/mi-0/mcc-0/omi-0/ocmb_chip-0</default> @@ -8586,9 +15038,10 @@ <default> <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> <field><id>engine</id><value>3</value></field> - <field><id>port</id><value>0</value></field> - <field><id>devAddr</id><value>0xD0</value></field> - <field><id>i2cMuxBusSelector</id><value>0x08</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>devAddr</id><value>0x40</value></field> + <field><id>i2cMuxBusSelector</id><value>0x00</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> </default> </attribute> @@ -8600,13 +15053,13 @@ <field><id>byteAddrOffset</id><value>0x02</value></field> <field><id>devAddr</id><value>0xA0</value></field> <field><id>chipCount</id><value>0x01</value></field> - <!-- Engine 3 Port 0 connects to a 3 to 8 MUX attached to DDIMM1-8 in the simics axone model --> - <field><id>port</id><value>0</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> <field><id>maxMemorySizeKB</id><value>0x4</value></field> <field><id>writeCycleTime</id><value>05</value></field> <field><id>writePageSize</id><value>0x20</value></field> - <!-- Valid Mux Bus Selections are 0x08-0x0F --> - <field><id>i2cMuxBusSelector</id><value>0x08</value></field> + <!-- Valid Mux Bus Selections are 0x00-0x07 --> + <field><id>i2cMuxBusSelector</id><value>0x00</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> </default> </attribute> @@ -8614,7 +15067,7 @@ <targetInstance> <id>sys0node0ocmb1</id> - <type>chip-ocmb-explorer</type> + <type>chip-ocmb</type> <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mc-0/mi-0/mcc-0/omi-1/ocmb_chip-0</default> @@ -8652,9 +15105,10 @@ <default> <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> <field><id>engine</id><value>3</value></field> - <field><id>port</id><value>0</value></field> - <field><id>devAddr</id><value>0xD0</value></field> - <field><id>i2cMuxBusSelector</id><value>0x09</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>devAddr</id><value>0x40</value></field> + <field><id>i2cMuxBusSelector</id><value>0x01</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> </default> </attribute> @@ -8666,13 +15120,13 @@ <field><id>byteAddrOffset</id><value>0x02</value></field> <field><id>devAddr</id><value>0xA0</value></field> <field><id>chipCount</id><value>0x01</value></field> - <!-- Engine 3 Port 0 connects to a 3 to 8 MUX attached to DDIMM1-8 in the simics axone model --> - <field><id>port</id><value>0</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> <field><id>maxMemorySizeKB</id><value>0x4</value></field> <field><id>writeCycleTime</id><value>05</value></field> <field><id>writePageSize</id><value>0x20</value></field> - <!-- Valid Mux Bus Selections are 0x08-0x0F --> - <field><id>i2cMuxBusSelector</id><value>0x09</value></field> + <!-- Valid Mux Bus Selections are 0x00-0x07 --> + <field><id>i2cMuxBusSelector</id><value>0x01</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> </default> </attribute> @@ -8680,7 +15134,7 @@ <targetInstance> <id>sys0node0ocmb2</id> - <type>chip-ocmb-explorer</type> + <type>chip-ocmb</type> <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mc-0/mi-0/mcc-1/omi-0/ocmb_chip-0</default> @@ -8718,9 +15172,10 @@ <default> <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> <field><id>engine</id><value>3</value></field> - <field><id>port</id><value>0</value></field> - <field><id>devAddr</id><value>0xD0</value></field> - <field><id>i2cMuxBusSelector</id><value>0x0A</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>devAddr</id><value>0x40</value></field> + <field><id>i2cMuxBusSelector</id><value>0x02</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> </default> </attribute> @@ -8732,13 +15187,13 @@ <field><id>byteAddrOffset</id><value>0x02</value></field> <field><id>devAddr</id><value>0xA0</value></field> <field><id>chipCount</id><value>0x01</value></field> - <!-- Engine 3 Port 0 connects to a 3 to 8 MUX attached to DDIMM1-8 in the simics axone model --> - <field><id>port</id><value>0</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> <field><id>maxMemorySizeKB</id><value>0x4</value></field> <field><id>writeCycleTime</id><value>05</value></field> <field><id>writePageSize</id><value>0x20</value></field> - <!-- Valid Mux Bus Selections are 0x08-0x0F --> - <field><id>i2cMuxBusSelector</id><value>0x0A</value></field> + <!-- Valid Mux Bus Selections are 0x00-0x07 --> + <field><id>i2cMuxBusSelector</id><value>0x02</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> </default> </attribute> @@ -8746,7 +15201,7 @@ <targetInstance> <id>sys0node0ocmb3</id> - <type>chip-ocmb-explorer</type> + <type>chip-ocmb</type> <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mc-0/mi-0/mcc-1/omi-1/ocmb_chip-0</default> @@ -8784,9 +15239,10 @@ <default> <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> <field><id>engine</id><value>3</value></field> - <field><id>port</id><value>0</value></field> - <field><id>devAddr</id><value>0xD0</value></field> - <field><id>i2cMuxBusSelector</id><value>0x0B</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>devAddr</id><value>0x40</value></field> + <field><id>i2cMuxBusSelector</id><value>0x03</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> </default> </attribute> @@ -8798,13 +15254,13 @@ <field><id>byteAddrOffset</id><value>0x02</value></field> <field><id>devAddr</id><value>0xA0</value></field> <field><id>chipCount</id><value>0x01</value></field> - <!-- Engine 3 Port 0 connects to a 3 to 8 MUX attached to DDIMM1-8 in the simics axone model --> - <field><id>port</id><value>0</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> <field><id>maxMemorySizeKB</id><value>0x4</value></field> <field><id>writeCycleTime</id><value>05</value></field> <field><id>writePageSize</id><value>0x20</value></field> - <!-- Valid Mux Bus Selections are 0x08-0x0F --> - <field><id>i2cMuxBusSelector</id><value>0x0B</value></field> + <!-- Valid Mux Bus Selections are 0x00-0x07 --> + <field><id>i2cMuxBusSelector</id><value>0x03</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> </default> </attribute> @@ -8812,7 +15268,7 @@ <targetInstance> <id>sys0node0ocmb4</id> - <type>chip-ocmb-explorer</type> + <type>chip-ocmb</type> <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mc-0/mi-1/mcc-0/omi-0/ocmb_chip-0</default> @@ -8850,9 +15306,10 @@ <default> <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> <field><id>engine</id><value>3</value></field> - <field><id>port</id><value>0</value></field> - <field><id>devAddr</id><value>0xD0</value></field> - <field><id>i2cMuxBusSelector</id><value>0x0C</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>devAddr</id><value>0x40</value></field> + <field><id>i2cMuxBusSelector</id><value>0x04</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> </default> </attribute> @@ -8864,13 +15321,13 @@ <field><id>byteAddrOffset</id><value>0x02</value></field> <field><id>devAddr</id><value>0xA0</value></field> <field><id>chipCount</id><value>0x01</value></field> - <!-- Engine 3 Port 0 connects to a 3 to 8 MUX attached to DDIMM1-8 in the simics axone model --> - <field><id>port</id><value>0</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> <field><id>maxMemorySizeKB</id><value>0x4</value></field> <field><id>writeCycleTime</id><value>05</value></field> <field><id>writePageSize</id><value>0x20</value></field> - <!-- Valid Mux Bus Selections are 0x08-0x0F --> - <field><id>i2cMuxBusSelector</id><value>0x0C</value></field> + <!-- Valid Mux Bus Selections are 0x00-0x07 --> + <field><id>i2cMuxBusSelector</id><value>0x04</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> </default> </attribute> @@ -8878,7 +15335,7 @@ <targetInstance> <id>sys0node0ocmb5</id> - <type>chip-ocmb-explorer</type> + <type>chip-ocmb</type> <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mc-0/mi-1/mcc-0/omi-1/ocmb_chip-0</default> @@ -8916,9 +15373,10 @@ <default> <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> <field><id>engine</id><value>3</value></field> - <field><id>port</id><value>0</value></field> - <field><id>devAddr</id><value>0xD0</value></field> - <field><id>i2cMuxBusSelector</id><value>0x0D</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>devAddr</id><value>0x40</value></field> + <field><id>i2cMuxBusSelector</id><value>0x05</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> </default> </attribute> @@ -8930,13 +15388,13 @@ <field><id>byteAddrOffset</id><value>0x02</value></field> <field><id>devAddr</id><value>0xA0</value></field> <field><id>chipCount</id><value>0x01</value></field> - <!-- Engine 3 Port 0 connects to a 3 to 8 MUX attached to DDIMM1-8 in the simics axone model --> - <field><id>port</id><value>0</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> <field><id>maxMemorySizeKB</id><value>0x4</value></field> <field><id>writeCycleTime</id><value>05</value></field> <field><id>writePageSize</id><value>0x20</value></field> - <!-- Valid Mux Bus Selections are 0x08-0x0F --> - <field><id>i2cMuxBusSelector</id><value>0x0D</value></field> + <!-- Valid Mux Bus Selections are 0x00-0x07 --> + <field><id>i2cMuxBusSelector</id><value>0x05</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> </default> </attribute> @@ -8944,7 +15402,7 @@ <targetInstance> <id>sys0node0ocmb6</id> - <type>chip-ocmb-explorer</type> + <type>chip-ocmb</type> <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mc-0/mi-1/mcc-1/omi-0/ocmb_chip-0</default> @@ -8982,9 +15440,10 @@ <default> <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> <field><id>engine</id><value>3</value></field> - <field><id>port</id><value>0</value></field> - <field><id>devAddr</id><value>0xD0</value></field> - <field><id>i2cMuxBusSelector</id><value>0x0E</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>devAddr</id><value>0x40</value></field> + <field><id>i2cMuxBusSelector</id><value>0x06</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> </default> </attribute> @@ -8996,13 +15455,13 @@ <field><id>byteAddrOffset</id><value>0x02</value></field> <field><id>devAddr</id><value>0xA0</value></field> <field><id>chipCount</id><value>0x01</value></field> - <!-- Engine 3 Port 0 connects to a 3 to 8 MUX attached to DDIMM1-8 in the simics axone model --> - <field><id>port</id><value>0</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> <field><id>maxMemorySizeKB</id><value>0x4</value></field> <field><id>writeCycleTime</id><value>05</value></field> <field><id>writePageSize</id><value>0x20</value></field> - <!-- Valid Mux Bus Selections are 0x08-0x0F --> - <field><id>i2cMuxBusSelector</id><value>0x0E</value></field> + <!-- Valid Mux Bus Selections are 0x00-0x07 --> + <field><id>i2cMuxBusSelector</id><value>0x06</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> </default> </attribute> @@ -9010,7 +15469,7 @@ <targetInstance> <id>sys0node0ocmb7</id> - <type>chip-ocmb-explorer</type> + <type>chip-ocmb</type> <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mc-0/mi-1/mcc-1/omi-1/ocmb_chip-0</default> @@ -9048,9 +15507,10 @@ <default> <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> <field><id>engine</id><value>3</value></field> - <field><id>port</id><value>0</value></field> - <field><id>devAddr</id><value>0xD0</value></field> - <field><id>i2cMuxBusSelector</id><value>0x0F</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>devAddr</id><value>0x40</value></field> + <field><id>i2cMuxBusSelector</id><value>0x07</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> </default> </attribute> @@ -9062,13 +15522,13 @@ <field><id>byteAddrOffset</id><value>0x02</value></field> <field><id>devAddr</id><value>0xA0</value></field> <field><id>chipCount</id><value>0x01</value></field> - <!-- Engine 3 Port 0 connects to a 3 to 8 MUX attached to DDIMM1-8 in the simics axone model --> - <field><id>port</id><value>0</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> <field><id>maxMemorySizeKB</id><value>0x4</value></field> <field><id>writeCycleTime</id><value>05</value></field> <field><id>writePageSize</id><value>0x20</value></field> - <!-- Valid Mux Bus Selections are 0x08-0x0F --> - <field><id>i2cMuxBusSelector</id><value>0x0F</value></field> + <!-- Valid Mux Bus Selections are 0x00-0x07 --> + <field><id>i2cMuxBusSelector</id><value>0x07</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> </default> </attribute> @@ -9076,7 +15536,7 @@ <targetInstance> <id>sys0node0ocmb8</id> - <type>chip-ocmb-explorer</type> + <type>chip-ocmb</type> <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mc-1/mi-0/mcc-0/omi-0/ocmb_chip-0</default> @@ -9114,8 +15574,9 @@ <default> <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> <field><id>engine</id><value>3</value></field> - <field><id>port</id><value>1</value></field> - <field><id>devAddr</id><value>0xD0</value></field> + <!-- Engine 3 Port 0 is directly attached to DDIMM8 in the simics axone model --> + <field><id>port</id><value>0</value></field> + <field><id>devAddr</id><value>0x40</value></field> <field><id>i2cMuxBusSelector</id><value>0xFF</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0</value></field> </default> @@ -9127,8 +15588,8 @@ <field><id>chipCount</id><value>0x01</value></field> <field><id>devAddr</id><value>0xA0</value></field> <field><id>engine</id><value>3</value></field> - <!-- Engine 3 Port 1 is directly attached to DDIMM0 in the simics axone model --> - <field><id>port</id><value>1</value></field> + <!-- Engine 3 Port 0 is directly attached to DDIMM8 in the simics axone model --> + <field><id>port</id><value>0</value></field> <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> <field><id>maxMemorySizeKB</id><value>0x4</value></field> <field><id>writeCycleTime</id><value>20</value></field> @@ -9141,7 +15602,7 @@ <targetInstance> <id>sys0node0ocmb9</id> - <type>chip-ocmb-explorer</type> + <type>chip-ocmb</type> <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mc-1/mi-0/mcc-0/omi-1/ocmb_chip-0</default> @@ -9174,13 +15635,18 @@ <id>FAPI_POS</id> <default>9</default> </attribute> + <!-- Note that EEPROM_VPD_PRIMARY_INFO/FAPI_I2C_CONTROL_INFO attrs for OCMB 9-15 and DIMM 9-15 + are invalid. The engine value is set to be engine 1 (C) which has 12 + valid ports according to the simics axone model. Only the first 4 ports + are actually used so we will use 5-12 as dummy ports for the unused dimm targets. + We cannot use the ports on engine 3 (E) becuase simics only has 2 ports marked as valid--> <attribute> <id>FAPI_I2C_CONTROL_INFO</id> <default> <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> - <field><id>engine</id><value>3</value></field> - <field><id>port</id><value>1</value></field> - <field><id>devAddr</id><value>0xD2</value></field> + <field><id>engine</id><value>1</value></field> + <field><id>port</id><value>5</value></field> + <field><id>devAddr</id><value>0xD0</value></field> <field><id>i2cMuxBusSelector</id><value>0xFF</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0</value></field> </default> @@ -9188,25 +15654,22 @@ <attribute> <id>EEPROM_VPD_PRIMARY_INFO</id> <default> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>engine</id><value>1</value></field> + <field><id>port</id><value>5</value></field> + <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> <field><id>byteAddrOffset</id><value>0x02</value></field> <field><id>chipCount</id><value>0x01</value></field> - <field><id>devAddr</id><value>0xA2</value></field> - <field><id>engine</id><value>3</value></field> - <!-- Engine 3 Port 1 is directly attached to DDIMM0 in the simics axone model --> - <field><id>port</id><value>1</value></field> - <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> - <field><id>maxMemorySizeKB</id><value>0x4</value></field> - <field><id>writeCycleTime</id><value>20</value></field> - <field><id>writePageSize</id><value>32</value></field> - <field><id>i2cMuxBusSelector</id><value>0xFF</value></field> - <field><id>i2cMuxPath</id><value>physical:sys-0</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> </default> </attribute> </targetInstance> <targetInstance> <id>sys0node0ocmb10</id> - <type>chip-ocmb-explorer</type> + <type>chip-ocmb</type> <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mc-1/mi-0/mcc-1/omi-0/ocmb_chip-0</default> @@ -9239,13 +15702,18 @@ <id>FAPI_POS</id> <default>10</default> </attribute> + <!-- Note that EEPROM_VPD_PRIMARY_INFO/FAPI_I2C_CONTROL_INFO attrs for OCMB 9-15 and DIMM 9-15 + are invalid. The engine value is set to be engine 1 (C) which has 12 + valid ports according to the simics axone model. Only the first 4 ports + are actually used so we will use 5-12 as dummy ports for the unused dimm targets. + We cannot use the ports on engine 3 (E) becuase simics only has 2 ports marked as valid--> <attribute> <id>FAPI_I2C_CONTROL_INFO</id> <default> <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> - <field><id>engine</id><value>3</value></field> - <field><id>port</id><value>1</value></field> - <field><id>devAddr</id><value>0xD4</value></field> + <field><id>engine</id><value>1</value></field> + <field><id>port</id><value>6</value></field> + <field><id>devAddr</id><value>0xD0</value></field> <field><id>i2cMuxBusSelector</id><value>0xFF</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0</value></field> </default> @@ -9253,25 +15721,22 @@ <attribute> <id>EEPROM_VPD_PRIMARY_INFO</id> <default> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>engine</id><value>1</value></field> + <field><id>port</id><value>6</value></field> + <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> <field><id>byteAddrOffset</id><value>0x02</value></field> <field><id>chipCount</id><value>0x01</value></field> - <field><id>devAddr</id><value>0xA4</value></field> - <field><id>engine</id><value>3</value></field> - <!-- Engine 3 Port 1 is directly attached to DDIMM0 in the simics axone model --> - <field><id>port</id><value>1</value></field> - <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> - <field><id>maxMemorySizeKB</id><value>0x4</value></field> - <field><id>writeCycleTime</id><value>20</value></field> - <field><id>writePageSize</id><value>32</value></field> - <field><id>i2cMuxBusSelector</id><value>0xFF</value></field> - <field><id>i2cMuxPath</id><value>physical:sys-0</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> </default> </attribute> </targetInstance> <targetInstance> <id>sys0node0ocmb11</id> - <type>chip-ocmb-explorer</type> + <type>chip-ocmb</type> <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mc-1/mi-0/mcc-1/omi-1/ocmb_chip-0</default> @@ -9304,13 +15769,16 @@ <id>FAPI_POS</id> <default>11</default> </attribute> + <!-- Note that EEPROM_VPD_PRIMARY_INFO/FAPI_I2C_CONTROL_INFO attrs for OCMB 9-15 and DIMM 9-15 + are invalid. The port and devAddr values are invalid, info is just here to fully test + the EEPROM caching code (DIMM X should match OCMB X) --> <attribute> <id>FAPI_I2C_CONTROL_INFO</id> <default> <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> <field><id>engine</id><value>3</value></field> - <field><id>port</id><value>1</value></field> - <field><id>devAddr</id><value>0xD6</value></field> + <field><id>port</id><value>4</value></field> + <field><id>devAddr</id><value>0xD4</value></field> <field><id>i2cMuxBusSelector</id><value>0xFF</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0</value></field> </default> @@ -9318,25 +15786,24 @@ <attribute> <id>EEPROM_VPD_PRIMARY_INFO</id> <default> - <field><id>byteAddrOffset</id><value>0x02</value></field> - <field><id>chipCount</id><value>0x01</value></field> - <field><id>devAddr</id><value>0xA6</value></field> + <field><id>devAddr</id><value>0xA4</value></field> <field><id>engine</id><value>3</value></field> - <!-- Engine 3 Port 1 is directly attached to DDIMM0 in the simics axone model --> - <field><id>port</id><value>1</value></field> - <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>port</id><value>4</value></field> <field><id>maxMemorySizeKB</id><value>0x4</value></field> - <field><id>writeCycleTime</id><value>20</value></field> - <field><id>writePageSize</id><value>32</value></field> - <field><id>i2cMuxBusSelector</id><value>0xFF</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0</value></field> + <field><id>i2cMuxBusSelector</id><value>0xFF</value></field> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> </default> </attribute> </targetInstance> <targetInstance> <id>sys0node0ocmb12</id> - <type>chip-ocmb-explorer</type> + <type>chip-ocmb</type> <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mc-1/mi-1/mcc-0/omi-0/ocmb_chip-0</default> @@ -9369,13 +15836,16 @@ <id>FAPI_POS</id> <default>12</default> </attribute> + <!-- Note that EEPROM_VPD_PRIMARY_INFO/FAPI_I2C_CONTROL_INFO attrs for OCMB 9-15 and DIMM 9-15 + are invalid. The port and devAddr values are invalid, info is just here to fully test + the EEPROM caching code (DIMM X should match OCMB X) --> <attribute> <id>FAPI_I2C_CONTROL_INFO</id> <default> <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> <field><id>engine</id><value>3</value></field> - <field><id>port</id><value>2</value></field> - <field><id>devAddr</id><value>0xD2</value></field> + <field><id>port</id><value>5</value></field> + <field><id>devAddr</id><value>0xD5</value></field> <field><id>i2cMuxBusSelector</id><value>0xFF</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0</value></field> </default> @@ -9383,25 +15853,24 @@ <attribute> <id>EEPROM_VPD_PRIMARY_INFO</id> <default> - <field><id>byteAddrOffset</id><value>0x02</value></field> - <field><id>chipCount</id><value>0x01</value></field> - <field><id>devAddr</id><value>0xA2</value></field> + <field><id>devAddr</id><value>0xA5</value></field> <field><id>engine</id><value>3</value></field> - <!-- Engine 3 Port 1 is directly attached to DDIMM0 in the simics axone model --> - <field><id>port</id><value>2</value></field> - <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>port</id><value>5</value></field> <field><id>maxMemorySizeKB</id><value>0x4</value></field> - <field><id>writeCycleTime</id><value>20</value></field> - <field><id>writePageSize</id><value>32</value></field> - <field><id>i2cMuxBusSelector</id><value>0xFF</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0</value></field> + <field><id>i2cMuxBusSelector</id><value>0xFF</value></field> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> </default> </attribute> </targetInstance> <targetInstance> <id>sys0node0ocmb13</id> - <type>chip-ocmb-explorer</type> + <type>chip-ocmb</type> <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mc-1/mi-1/mcc-0/omi-1/ocmb_chip-0</default> @@ -9434,13 +15903,16 @@ <id>FAPI_POS</id> <default>13</default> </attribute> + <!-- Note that EEPROM_VPD_PRIMARY_INFO/FAPI_I2C_CONTROL_INFO attrs for OCMB 9-15 and DIMM 9-15 + are invalid. The port and devAddr values are invalid, info is just here to fully test + the EEPROM caching code (DIMM X should match OCMB X) --> <attribute> <id>FAPI_I2C_CONTROL_INFO</id> <default> <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> <field><id>engine</id><value>3</value></field> - <field><id>port</id><value>2</value></field> - <field><id>devAddr</id><value>0xD4</value></field> + <field><id>port</id><value>6</value></field> + <field><id>devAddr</id><value>0xD6</value></field> <field><id>i2cMuxBusSelector</id><value>0xFF</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0</value></field> </default> @@ -9448,25 +15920,24 @@ <attribute> <id>EEPROM_VPD_PRIMARY_INFO</id> <default> - <field><id>byteAddrOffset</id><value>0x02</value></field> - <field><id>chipCount</id><value>0x01</value></field> - <field><id>devAddr</id><value>0xA4</value></field> + <field><id>devAddr</id><value>0xA6</value></field> <field><id>engine</id><value>3</value></field> - <!-- Engine 3 Port 1 is directly attached to DDIMM0 in the simics axone model --> - <field><id>port</id><value>2</value></field> - <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>port</id><value>6</value></field> <field><id>maxMemorySizeKB</id><value>0x4</value></field> - <field><id>writeCycleTime</id><value>20</value></field> - <field><id>writePageSize</id><value>32</value></field> - <field><id>i2cMuxBusSelector</id><value>0xFF</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0</value></field> + <field><id>i2cMuxBusSelector</id><value>0xFF</value></field> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> </default> </attribute> </targetInstance> <targetInstance> <id>sys0node0ocmb14</id> - <type>chip-ocmb-explorer</type> + <type>chip-ocmb</type> <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mc-1/mi-1/mcc-1/omi-0/ocmb_chip-0</default> @@ -9499,13 +15970,16 @@ <id>FAPI_POS</id> <default>14</default> </attribute> + <!-- Note that EEPROM_VPD_PRIMARY_INFO/FAPI_I2C_CONTROL_INFO attrs for OCMB 9-15 and DIMM 9-15 + are invalid. The port and devAddr values are invalid, info is just here to fully test + the EEPROM caching code (DIMM X should match OCMB X) --> <attribute> <id>FAPI_I2C_CONTROL_INFO</id> <default> <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> <field><id>engine</id><value>3</value></field> - <field><id>port</id><value>2</value></field> - <field><id>devAddr</id><value>0xD6</value></field> + <field><id>port</id><value>7</value></field> + <field><id>devAddr</id><value>0xD7</value></field> <field><id>i2cMuxBusSelector</id><value>0xFF</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0</value></field> </default> @@ -9513,25 +15987,24 @@ <attribute> <id>EEPROM_VPD_PRIMARY_INFO</id> <default> - <field><id>byteAddrOffset</id><value>0x02</value></field> - <field><id>chipCount</id><value>0x01</value></field> - <field><id>devAddr</id><value>0xA6</value></field> + <field><id>devAddr</id><value>0xA7</value></field> <field><id>engine</id><value>3</value></field> - <!-- Engine 3 Port 1 is directly attached to DDIMM0 in the simics axone model --> - <field><id>port</id><value>2</value></field> - <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>port</id><value>7</value></field> <field><id>maxMemorySizeKB</id><value>0x4</value></field> - <field><id>writeCycleTime</id><value>20</value></field> - <field><id>writePageSize</id><value>32</value></field> - <field><id>i2cMuxBusSelector</id><value>0xFF</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0</value></field> + <field><id>i2cMuxBusSelector</id><value>0xFF</value></field> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> </default> </attribute> </targetInstance> <targetInstance> <id>sys0node0ocmb15</id> - <type>chip-ocmb-explorer</type> + <type>chip-ocmb</type> <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mc-1/mi-1/mcc-1/omi-1/ocmb_chip-0</default> @@ -9564,6 +16037,9 @@ <id>FAPI_POS</id> <default>15</default> </attribute> + <!-- Note that EEPROM_VPD_PRIMARY_INFO/FAPI_I2C_CONTROL_INFO attrs for OCMB 9-15 and DIMM 9-15 + are invalid. The port and devAddr values are invalid, info is just here to fully test + the EEPROM caching code (DIMM X should match OCMB X) --> <attribute> <id>FAPI_I2C_CONTROL_INFO</id> <default> @@ -9578,13 +16054,614 @@ <attribute> <id>EEPROM_VPD_PRIMARY_INFO</id> <default> - <field><id>byteAddrOffset</id><value>0x02</value></field> - <field><id>chipCount</id><value>0x01</value></field> <field><id>devAddr</id><value>0xA8</value></field> <field><id>engine</id><value>3</value></field> - <!-- Engine 3 Port 1 is directly attached to DDIMM0 in the simics axone model --> - <field><id>port</id><value>2</value></field> + <field><id>port</id><value>8</value></field> + <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>i2cMuxBusSelector</id><value>0xFF</value></field> <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> + </default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0ocmb16</id> + <type>chip-ocmb</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-0/mcc-0/omi-0/ocmb_chip-0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>ocmb:k0:n0:s0:p16</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x0004B0010</default> + </attribute> + <attribute> + <id>MRU_ID</id> + <default>0x00060000</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/ocmb_chip-16</default> + </attribute> + <attribute> + <id>POSITION</id> + <default>16</default> + </attribute> + <attribute> + <id>VPD_REC_NUM</id> + <default>16</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>16</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>devAddr</id><value>0x40</value></field> + <field><id>i2cMuxBusSelector</id><value>0x00</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> + <!-- Valid Mux Bus Selections are 0x00-0x07 --> + <field><id>i2cMuxBusSelector</id><value>0x00</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0ocmb17</id> + <type>chip-ocmb</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-0/mcc-0/omi-1/ocmb_chip-0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>ocmb:k0:n0:s0:p17</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x0004B0011</default> + </attribute> + <attribute> + <id>MRU_ID</id> + <default>0x00060000</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/ocmb_chip-17</default> + </attribute> + <attribute> + <id>POSITION</id> + <default>17</default> + </attribute> + <attribute> + <id>VPD_REC_NUM</id> + <default>17</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>1</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>devAddr</id><value>0x40</value></field> + <field><id>i2cMuxBusSelector</id><value>0x01</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> + <!-- Valid Mux Bus Selections are 0x00-0x07 --> + <field><id>i2cMuxBusSelector</id><value>0x01</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0ocmb18</id> + <type>chip-ocmb</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-0/mcc-1/omi-0/ocmb_chip-0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>ocmb:k0:n0:s0:p18</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x0004B0012</default> + </attribute> + <attribute> + <id>MRU_ID</id> + <default>0x00060000</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/ocmb_chip-18</default> + </attribute> + <attribute> + <id>POSITION</id> + <default>18</default> + </attribute> + <attribute> + <id>VPD_REC_NUM</id> + <default>18</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>18</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>devAddr</id><value>0x40</value></field> + <field><id>i2cMuxBusSelector</id><value>0x02</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> + <!-- Valid Mux Bus Selections are 0x00-0x07 --> + <field><id>i2cMuxBusSelector</id><value>0x02</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0ocmb19</id> + <type>chip-ocmb</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-0/mcc-1/omi-1/ocmb_chip-0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>ocmb:k0:n0:s0:p19</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x0004B0013</default> + </attribute> + <attribute> + <id>MRU_ID</id> + <default>0x00060000</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/ocmb_chip-19</default> + </attribute> + <attribute> + <id>POSITION</id> + <default>19</default> + </attribute> + <attribute> + <id>VPD_REC_NUM</id> + <default>19</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>19</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>devAddr</id><value>0x40</value></field> + <field><id>i2cMuxBusSelector</id><value>0x03</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> + <!-- Valid Mux Bus Selections are 0x00-0x07 --> + <field><id>i2cMuxBusSelector</id><value>0x03</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0ocmb20</id> + <type>chip-ocmb</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-1/mcc-0/omi-0/ocmb_chip-0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>ocmb:k0:n0:s0:p20</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x0004B0014</default> + </attribute> + <attribute> + <id>MRU_ID</id> + <default>0x00060000</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/ocmb_chip-20</default> + </attribute> + <attribute> + <id>POSITION</id> + <default>20</default> + </attribute> + <attribute> + <id>VPD_REC_NUM</id> + <default>20</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>20</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>devAddr</id><value>0x40</value></field> + <field><id>i2cMuxBusSelector</id><value>0x04</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> + <!-- Valid Mux Bus Selections are 0x00-0x07 --> + <field><id>i2cMuxBusSelector</id><value>0x04</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0ocmb21</id> + <type>chip-ocmb</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-1/mcc-0/omi-1/ocmb_chip-0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>ocmb:k0:n0:s0:p21</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x0004B0015</default> + </attribute> + <attribute> + <id>MRU_ID</id> + <default>0x00060000</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/ocmb_chip-21</default> + </attribute> + <attribute> + <id>POSITION</id> + <default>21</default> + </attribute> + <attribute> + <id>VPD_REC_NUM</id> + <default>21</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>21</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>devAddr</id><value>0x40</value></field> + <field><id>i2cMuxBusSelector</id><value>0x05</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> + <!-- Valid Mux Bus Selections are 0x00-0x07 --> + <field><id>i2cMuxBusSelector</id><value>0x05</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0ocmb22</id> + <type>chip-ocmb</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-1/mcc-1/omi-0/ocmb_chip-0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>ocmb:k0:n0:s0:p22</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x0004B0016</default> + </attribute> + <attribute> + <id>MRU_ID</id> + <default>0x00060000</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/ocmb_chip-22</default> + </attribute> + <attribute> + <id>POSITION</id> + <default>22</default> + </attribute> + <attribute> + <id>VPD_REC_NUM</id> + <default>22</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>22</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>devAddr</id><value>0x40</value></field> + <field><id>i2cMuxBusSelector</id><value>0x06</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> + <!-- Valid Mux Bus Selections are 0x00-0x07 --> + <field><id>i2cMuxBusSelector</id><value>0x06</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0ocmb23</id> + <type>chip-ocmb</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-1/mcc-1/omi-1/ocmb_chip-0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>ocmb:k0:n0:s0:p23</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x0004B0017</default> + </attribute> + <attribute> + <id>MRU_ID</id> + <default>0x00060000</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/ocmb_chip-23</default> + </attribute> + <attribute> + <id>POSITION</id> + <default>23</default> + </attribute> + <attribute> + <id>VPD_REC_NUM</id> + <default>23</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>23</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>devAddr</id><value>0x40</value></field> + <field><id>i2cMuxBusSelector</id><value>0x07</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> + <!-- Valid Mux Bus Selections are 0x00-0x07 --> + <field><id>i2cMuxBusSelector</id><value>0x07</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0ocmb24</id> + <type>chip-ocmb</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-1/mi-0/mcc-0/omi-0/ocmb_chip-0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>ocmb:k0:n0:s0:p24</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x0004B0018</default> + </attribute> + <attribute> + <id>MRU_ID</id> + <default>0x00060000</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/ocmb_chip-24</default> + </attribute> + <attribute> + <id>POSITION</id> + <default>24</default> + </attribute> + <attribute> + <id>VPD_REC_NUM</id> + <default>24</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>24</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <!-- Engine 3 Port 0 is directly attached to DDIMM8 in the simics axone model --> + <field><id>port</id><value>0</value></field> + <field><id>devAddr</id><value>0x40</value></field> + <field><id>i2cMuxBusSelector</id><value>0xFF</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0</value></field> + </default> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + <default> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>engine</id><value>3</value></field> + <!-- Engine 3 Port 0 is directly attached to DDIMM8 in the simics axone model --> + <field><id>port</id><value>0</value></field> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> <field><id>maxMemorySizeKB</id><value>0x4</value></field> <field><id>writeCycleTime</id><value>20</value></field> <field><id>writePageSize</id><value>32</value></field> @@ -9613,6 +16690,10 @@ <default>pmic:k0:n0:s0:p00</default> </attribute> <attribute> + <id>FAPI_POS</id> + <default>0</default> + </attribute> + <attribute> <id>FAPI_I2C_CONTROL_INFO</id> <default> <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> @@ -9653,6 +16734,10 @@ <default>pmic:k0:n0:s0:p01</default> </attribute> <attribute> + <id>FAPI_POS</id> + <default>1</default> + </attribute> + <attribute> <id>FAPI_I2C_CONTROL_INFO</id> <default> <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> @@ -9678,11 +16763,11 @@ </targetInstance> <targetInstance> - <id>sys0node0pmic2</id> + <id>sys0node0pmic4</id> <type>pmic</type> <attribute> <id>HUID</id> - <default>0x00360002</default> + <default>0x00360004</default> </attribute> <attribute> <id>AFFINITY_PATH</id> @@ -9690,7 +16775,11 @@ </attribute> <attribute> <id>FAPI_NAME</id> - <default>pmic:k0:n0:s0:p02</default> + <default>pmic:k0:n0:s0:p04</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>4</default> </attribute> <attribute> <id>FAPI_I2C_CONTROL_INFO</id> @@ -9705,11 +16794,11 @@ </attribute> <attribute> <id>ORDINAL_ID</id> - <default>2</default> + <default>4</default> </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/pmic-2</default> + <default>physical:sys-0/node-0/pmic-4</default> </attribute> <attribute> <id>REL_POS</id> @@ -9718,11 +16807,11 @@ </targetInstance> <targetInstance> - <id>sys0node0pmic3</id> + <id>sys0node0pmic5</id> <type>pmic</type> <attribute> <id>HUID</id> - <default>0x00360003</default> + <default>0x00360005</default> </attribute> <attribute> <id>AFFINITY_PATH</id> @@ -9730,7 +16819,11 @@ </attribute> <attribute> <id>FAPI_NAME</id> - <default>pmic:k0:n0:s0:p03</default> + <default>pmic:k0:n0:s0:p05</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>5</default> </attribute> <attribute> <id>FAPI_I2C_CONTROL_INFO</id> @@ -9745,11 +16838,11 @@ </attribute> <attribute> <id>ORDINAL_ID</id> - <default>3</default> + <default>5</default> </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/pmic-3</default> + <default>physical:sys-0/node-0/pmic-5</default> </attribute> <attribute> <id>REL_POS</id> @@ -9758,11 +16851,11 @@ </targetInstance> <targetInstance> - <id>sys0node0pmic4</id> + <id>sys0node0pmic8</id> <type>pmic</type> <attribute> <id>HUID</id> - <default>0x00360004</default> + <default>0x00360008</default> </attribute> <attribute> <id>AFFINITY_PATH</id> @@ -9770,7 +16863,11 @@ </attribute> <attribute> <id>FAPI_NAME</id> - <default>pmic:k0:n0:s0:p04</default> + <default>pmic:k0:n0:s0:p08</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>8</default> </attribute> <attribute> <id>FAPI_I2C_CONTROL_INFO</id> @@ -9785,11 +16882,11 @@ </attribute> <attribute> <id>ORDINAL_ID</id> - <default>4</default> + <default>8</default> </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/pmic-4</default> + <default>physical:sys-0/node-0/pmic-8</default> </attribute> <attribute> <id>REL_POS</id> @@ -9798,11 +16895,11 @@ </targetInstance> <targetInstance> - <id>sys0node0pmic5</id> + <id>sys0node0pmic9</id> <type>pmic</type> <attribute> <id>HUID</id> - <default>0x00360005</default> + <default>0x00360009</default> </attribute> <attribute> <id>AFFINITY_PATH</id> @@ -9810,7 +16907,11 @@ </attribute> <attribute> <id>FAPI_NAME</id> - <default>pmic:k0:n0:s0:p05</default> + <default>pmic:k0:n0:s0:p09</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>9</default> </attribute> <attribute> <id>FAPI_I2C_CONTROL_INFO</id> @@ -9825,11 +16926,11 @@ </attribute> <attribute> <id>ORDINAL_ID</id> - <default>5</default> + <default>9</default> </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/pmic-5</default> + <default>physical:sys-0/node-0/pmic-9</default> </attribute> <attribute> <id>REL_POS</id> @@ -9838,11 +16939,11 @@ </targetInstance> <targetInstance> - <id>sys0node0pmic6</id> + <id>sys0node0pmic12</id> <type>pmic</type> <attribute> <id>HUID</id> - <default>0x00360006</default> + <default>0x0036000C</default> </attribute> <attribute> <id>AFFINITY_PATH</id> @@ -9850,7 +16951,11 @@ </attribute> <attribute> <id>FAPI_NAME</id> - <default>pmic:k0:n0:s0:p06</default> + <default>pmic:k0:n0:s0:p12</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>12</default> </attribute> <attribute> <id>FAPI_I2C_CONTROL_INFO</id> @@ -9865,11 +16970,11 @@ </attribute> <attribute> <id>ORDINAL_ID</id> - <default>6</default> + <default>12</default> </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/pmic-6</default> + <default>physical:sys-0/node-0/pmic-12</default> </attribute> <attribute> <id>REL_POS</id> @@ -9878,11 +16983,11 @@ </targetInstance> <targetInstance> - <id>sys0node0pmic7</id> + <id>sys0node0pmic13</id> <type>pmic</type> <attribute> <id>HUID</id> - <default>0x00360007</default> + <default>0x0036000D</default> </attribute> <attribute> <id>AFFINITY_PATH</id> @@ -9890,7 +16995,11 @@ </attribute> <attribute> <id>FAPI_NAME</id> - <default>pmic:k0:n0:s0:p07</default> + <default>pmic:k0:n0:s0:p13</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>13</default> </attribute> <attribute> <id>FAPI_I2C_CONTROL_INFO</id> @@ -9905,11 +17014,11 @@ </attribute> <attribute> <id>ORDINAL_ID</id> - <default>7</default> + <default>13</default> </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/pmic-7</default> + <default>physical:sys-0/node-0/pmic-13</default> </attribute> <attribute> <id>REL_POS</id> @@ -9918,11 +17027,11 @@ </targetInstance> <targetInstance> - <id>sys0node0pmic8</id> + <id>sys0node0pmic16</id> <type>pmic</type> <attribute> <id>HUID</id> - <default>0x00360008</default> + <default>0x00360010</default> </attribute> <attribute> <id>AFFINITY_PATH</id> @@ -9930,7 +17039,7 @@ </attribute> <attribute> <id>FAPI_NAME</id> - <default>pmic:k0:n0:s0:p08</default> + <default>pmic:k0:n0:s0:p16</default> </attribute> <attribute> <id>FAPI_I2C_CONTROL_INFO</id> @@ -9945,11 +17054,11 @@ </attribute> <attribute> <id>ORDINAL_ID</id> - <default>8</default> + <default>16</default> </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/pmic-8</default> + <default>physical:sys-0/node-0/pmic-16</default> </attribute> <attribute> <id>REL_POS</id> @@ -9958,11 +17067,11 @@ </targetInstance> <targetInstance> - <id>sys0node0pmic9</id> + <id>sys0node0pmic17</id> <type>pmic</type> <attribute> <id>HUID</id> - <default>0x00360009</default> + <default>0x00360011</default> </attribute> <attribute> <id>AFFINITY_PATH</id> @@ -9970,7 +17079,11 @@ </attribute> <attribute> <id>FAPI_NAME</id> - <default>pmic:k0:n0:s0:p09</default> + <default>pmic:k0:n0:s0:p17</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>17</default> </attribute> <attribute> <id>FAPI_I2C_CONTROL_INFO</id> @@ -9985,11 +17098,11 @@ </attribute> <attribute> <id>ORDINAL_ID</id> - <default>9</default> + <default>17</default> </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/pmic-9</default> + <default>physical:sys-0/node-0/pmic-17</default> </attribute> <attribute> <id>REL_POS</id> @@ -9998,11 +17111,11 @@ </targetInstance> <targetInstance> - <id>sys0node0pmic10</id> + <id>sys0node0pmic20</id> <type>pmic</type> <attribute> <id>HUID</id> - <default>0x0036000A</default> + <default>0x00360014</default> </attribute> <attribute> <id>AFFINITY_PATH</id> @@ -10010,7 +17123,7 @@ </attribute> <attribute> <id>FAPI_NAME</id> - <default>pmic:k0:n0:s0:p10</default> + <default>pmic:k0:n0:s0:p20</default> </attribute> <attribute> <id>FAPI_I2C_CONTROL_INFO</id> @@ -10025,11 +17138,11 @@ </attribute> <attribute> <id>ORDINAL_ID</id> - <default>10</default> + <default>20</default> </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/pmic-0</default> + <default>physical:sys-0/node-0/pmic-20</default> </attribute> <attribute> <id>REL_POS</id> @@ -10038,11 +17151,11 @@ </targetInstance> <targetInstance> - <id>sys0node0pmic11</id> + <id>sys0node0pmic21</id> <type>pmic</type> <attribute> <id>HUID</id> - <default>0x0036000B</default> + <default>0x00360015</default> </attribute> <attribute> <id>AFFINITY_PATH</id> @@ -10050,7 +17163,7 @@ </attribute> <attribute> <id>FAPI_NAME</id> - <default>pmic:k0:n0:s0:p11</default> + <default>pmic:k0:n0:s0:p21</default> </attribute> <attribute> <id>FAPI_I2C_CONTROL_INFO</id> @@ -10065,11 +17178,11 @@ </attribute> <attribute> <id>ORDINAL_ID</id> - <default>11</default> + <default>21</default> </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/pmic-1</default> + <default>physical:sys-0/node-0/pmic-21</default> </attribute> <attribute> <id>REL_POS</id> @@ -10078,11 +17191,11 @@ </targetInstance> <targetInstance> - <id>sys0node0pmic12</id> + <id>sys0node0pmic24</id> <type>pmic</type> <attribute> <id>HUID</id> - <default>0x0036000C</default> + <default>0x00360018</default> </attribute> <attribute> <id>AFFINITY_PATH</id> @@ -10090,7 +17203,11 @@ </attribute> <attribute> <id>FAPI_NAME</id> - <default>pmic:k0:n0:s0:p12</default> + <default>pmic:k0:n0:s0:p24</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>24</default> </attribute> <attribute> <id>FAPI_I2C_CONTROL_INFO</id> @@ -10105,11 +17222,11 @@ </attribute> <attribute> <id>ORDINAL_ID</id> - <default>12</default> + <default>24</default> </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/pmic-0</default> + <default>physical:sys-0/node-0/pmic-24</default> </attribute> <attribute> <id>REL_POS</id> @@ -10118,11 +17235,11 @@ </targetInstance> <targetInstance> - <id>sys0node0pmic13</id> + <id>sys0node0pmic25</id> <type>pmic</type> <attribute> <id>HUID</id> - <default>0x0036000D</default> + <default>0x00360019</default> </attribute> <attribute> <id>AFFINITY_PATH</id> @@ -10130,7 +17247,7 @@ </attribute> <attribute> <id>FAPI_NAME</id> - <default>pmic:k0:n0:s0:p13</default> + <default>pmic:k0:n0:s0:p25</default> </attribute> <attribute> <id>FAPI_I2C_CONTROL_INFO</id> @@ -10145,11 +17262,11 @@ </attribute> <attribute> <id>ORDINAL_ID</id> - <default>13</default> + <default>25</default> </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/pmic-1</default> + <default>physical:sys-0/node-0/pmic-25</default> </attribute> <attribute> <id>REL_POS</id> @@ -10158,11 +17275,11 @@ </targetInstance> <targetInstance> - <id>sys0node0pmic14</id> + <id>sys0node0pmic28</id> <type>pmic</type> <attribute> <id>HUID</id> - <default>0x0036000E</default> + <default>0x0036001C</default> </attribute> <attribute> <id>AFFINITY_PATH</id> @@ -10170,7 +17287,11 @@ </attribute> <attribute> <id>FAPI_NAME</id> - <default>pmic:k0:n0:s0:p14</default> + <default>pmic:k0:n0:s0:p28</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>28</default> </attribute> <attribute> <id>FAPI_I2C_CONTROL_INFO</id> @@ -10185,11 +17306,11 @@ </attribute> <attribute> <id>ORDINAL_ID</id> - <default>14</default> + <default>28</default> </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/pmic-0</default> + <default>physical:sys-0/node-0/pmic-28</default> </attribute> <attribute> <id>REL_POS</id> @@ -10198,11 +17319,11 @@ </targetInstance> <targetInstance> - <id>sys0node0pmic15</id> + <id>sys0node0pmic29</id> <type>pmic</type> <attribute> <id>HUID</id> - <default>0x0036000F</default> + <default>0x0036001D</default> </attribute> <attribute> <id>AFFINITY_PATH</id> @@ -10210,7 +17331,7 @@ </attribute> <attribute> <id>FAPI_NAME</id> - <default>pmic:k0:n0:s0:p15</default> + <default>pmic:k0:n0:s0:p29</default> </attribute> <attribute> <id>FAPI_I2C_CONTROL_INFO</id> @@ -10225,11 +17346,11 @@ </attribute> <attribute> <id>ORDINAL_ID</id> - <default>15</default> + <default>29</default> </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/pmic-1</default> + <default>physical:sys-0/node-0/pmic-29</default> </attribute> <attribute> <id>REL_POS</id> @@ -10238,11 +17359,11 @@ </targetInstance> <targetInstance> - <id>sys0node0pmic16</id> + <id>sys0node0pmic32</id> <type>pmic</type> <attribute> <id>HUID</id> - <default>0x00360010</default> + <default>0x00360020</default> </attribute> <attribute> <id>AFFINITY_PATH</id> @@ -10250,7 +17371,11 @@ </attribute> <attribute> <id>FAPI_NAME</id> - <default>pmic:k0:n0:s0:p16</default> + <default>pmic:k0:n0:s0:p32</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>32</default> </attribute> <attribute> <id>FAPI_I2C_CONTROL_INFO</id> @@ -10265,11 +17390,11 @@ </attribute> <attribute> <id>ORDINAL_ID</id> - <default>16</default> + <default>32</default> </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/pmic-0</default> + <default>physical:sys-0/node-0/pmic-32</default> </attribute> <attribute> <id>REL_POS</id> @@ -10278,11 +17403,11 @@ </targetInstance> <targetInstance> - <id>sys0node0pmic17</id> + <id>sys0node0pmic33</id> <type>pmic</type> <attribute> <id>HUID</id> - <default>0x00360011</default> + <default>0x00360021</default> </attribute> <attribute> <id>AFFINITY_PATH</id> @@ -10290,7 +17415,11 @@ </attribute> <attribute> <id>FAPI_NAME</id> - <default>pmic:k0:n0:s0:p17</default> + <default>pmic:k0:n0:s0:p33</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>33</default> </attribute> <attribute> <id>FAPI_I2C_CONTROL_INFO</id> @@ -10305,11 +17434,783 @@ </attribute> <attribute> <id>ORDINAL_ID</id> - <default>17</default> + <default>33</default> </attribute> <attribute> <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/pmic-1</default> + <default>physical:sys-0/node-0/pmic-33</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0pmic34</id> + <type>pmic</type> + <attribute> + <id>HUID</id> + <default>0x00360022</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-0/mcc-0/omi-0/ocmb_chip-0/pmic-0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pmic:k0:n0:s0:p34</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>34</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>port</id><value>0</value></field> + <field><id>devAddr</id><value>0x90</value></field> + <field><id>i2cMuxBusSelector</id><value>0x08</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>34</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/pmic-34</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0pmic35</id> + <type>pmic</type> + <attribute> + <id>HUID</id> + <default>0x00360023</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-0/mcc-0/omi-0/ocmb_chip-0/pmic-1</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pmic:k0:n0:s0:p35</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>35</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>port</id><value>0</value></field> + <field><id>devAddr</id><value>0xC0</value></field> + <field><id>i2cMuxBusSelector</id><value>0x08</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>35</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/pmic-35</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0pmic38</id> + <type>pmic</type> + <attribute> + <id>HUID</id> + <default>0x00360026</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-0/mcc-0/omi-1/ocmb_chip-0/pmic-0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pmic:k0:n0:s0:p38</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>38</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>port</id><value>0</value></field> + <field><id>devAddr</id><value>0x90</value></field> + <field><id>i2cMuxBusSelector</id><value>0x09</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>38</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/pmic-38</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0pmic39</id> + <type>pmic</type> + <attribute> + <id>HUID</id> + <default>0x00360027</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-0/mcc-0/omi-1/ocmb_chip-0/pmic-1</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pmic:k0:n0:s0:p39</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>39</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>port</id><value>0</value></field> + <field><id>devAddr</id><value>0xC0</value></field> + <field><id>i2cMuxBusSelector</id><value>0x09</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>39</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/pmic-39</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0pmic42</id> + <type>pmic</type> + <attribute> + <id>HUID</id> + <default>0x0036002A</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-0/mcc-1/omi-0/ocmb_chip-0/pmic-0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pmic:k0:n0:s0:p42</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>42</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>port</id><value>0</value></field> + <field><id>devAddr</id><value>0x90</value></field> + <field><id>i2cMuxBusSelector</id><value>0x0A</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>42</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/pmic-42</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0pmic43</id> + <type>pmic</type> + <attribute> + <id>HUID</id> + <default>0x0036002B</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-0/mcc-1/omi-0/ocmb_chip-0/pmic-1</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pmic:k0:n0:s0:p43</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>43</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>port</id><value>0</value></field> + <field><id>devAddr</id><value>0xC0</value></field> + <field><id>i2cMuxBusSelector</id><value>0x0A</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>43</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/pmic-43</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0pmic46</id> + <type>pmic</type> + <attribute> + <id>HUID</id> + <default>0x0036002E</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-0/mcc-1/omi-1/ocmb_chip-0/pmic-0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pmic:k0:n0:s0:p46</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>46</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>port</id><value>0</value></field> + <field><id>devAddr</id><value>0x90</value></field> + <field><id>i2cMuxBusSelector</id><value>0x0B</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>46</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/pmic-46</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0pmic47</id> + <type>pmic</type> + <attribute> + <id>HUID</id> + <default>0x0036002F</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-0/mcc-1/omi-1/ocmb_chip-0/pmic-1</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pmic:k0:n0:s0:p47</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>47</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>port</id><value>0</value></field> + <field><id>devAddr</id><value>0xC0</value></field> + <field><id>i2cMuxBusSelector</id><value>0x0B</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>47</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/pmic-47</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0pmic48</id> + <type>pmic</type> + <attribute> + <id>HUID</id> + <default>0x00360032</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-1/mcc-0/omi-0/ocmb_chip-0/pmic-0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pmic:k0:n0:s0:p48</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>port</id><value>0</value></field> + <field><id>devAddr</id><value>0x90</value></field> + <field><id>i2cMuxBusSelector</id><value>0x0C</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>48</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/pmic-48</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0pmic51</id> + <type>pmic</type> + <attribute> + <id>HUID</id> + <default>0x00360033</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-1/mcc-0/omi-0/ocmb_chip-0/pmic-1</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pmic:k0:n0:s0:p51</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>51</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>port</id><value>0</value></field> + <field><id>devAddr</id><value>0xC0</value></field> + <field><id>i2cMuxBusSelector</id><value>0x0C</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>51</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/pmic-51</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0pmic54</id> + <type>pmic</type> + <attribute> + <id>HUID</id> + <default>0x00360036</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-1/mcc-0/omi-1/ocmb_chip-0/pmic-0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pmic:k0:n0:s0:p54</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>port</id><value>0</value></field> + <field><id>devAddr</id><value>0x90</value></field> + <field><id>i2cMuxBusSelector</id><value>0x0D</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>54</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/pmic-54</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0pmic55</id> + <type>pmic</type> + <attribute> + <id>HUID</id> + <default>0x00360037</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-1/mcc-0/omi-1/ocmb_chip-0/pmic-1</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pmic:k0:n0:s0:p55</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>port</id><value>0</value></field> + <field><id>devAddr</id><value>0xC0</value></field> + <field><id>i2cMuxBusSelector</id><value>0x0D</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>55</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/pmic-55</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0pmic58</id> + <type>pmic</type> + <attribute> + <id>HUID</id> + <default>0x0036003A</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-1/mcc-1/omi-0/ocmb_chip-0/pmic-0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pmic:k0:n0:s0:p58</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>58</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>port</id><value>0</value></field> + <field><id>devAddr</id><value>0x90</value></field> + <field><id>i2cMuxBusSelector</id><value>0x0E</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>58</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/pmic-58</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0pmic59</id> + <type>pmic</type> + <attribute> + <id>HUID</id> + <default>0x0036003B</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-1/mcc-1/omi-0/ocmb_chip-0/pmic-1</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pmic:k0:n0:s0:p59</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>port</id><value>0</value></field> + <field><id>devAddr</id><value>0xC0</value></field> + <field><id>i2cMuxBusSelector</id><value>0x0E</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>59</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/pmic-59</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0pmic62</id> + <type>pmic</type> + <attribute> + <id>HUID</id> + <default>0x0036003E</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-1/mcc-1/omi-1/ocmb_chip-0/pmic-0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pmic:k0:n0:s0:p62</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>62</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>port</id><value>0</value></field> + <field><id>devAddr</id><value>0x90</value></field> + <field><id>i2cMuxBusSelector</id><value>0x0F</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>62</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/pmic-62</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0pmic63</id> + <type>pmic</type> + <attribute> + <id>HUID</id> + <default>0x0036003F</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-1/mcc-1/omi-1/ocmb_chip-0/pmic-1</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pmic:k0:n0:s0:p63</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>port</id><value>0</value></field> + <field><id>devAddr</id><value>0xC0</value></field> + <field><id>i2cMuxBusSelector</id><value>0x0F</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>63</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/pmic-63</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0pmic66</id> + <type>pmic</type> + <attribute> + <id>HUID</id> + <default>0x00360042</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-1/mi-0/mcc-0/omi-0/ocmb_chip-0/pmic-0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pmic:k0:n0:s0:p66</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>66</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>port</id><value>1</value></field> + <field><id>devAddr</id><value>0x90</value></field> + <field><id>i2cMuxBusSelector</id><value>0xFF</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0</value></field> + </default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>66</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/pmic-66</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0pmic67</id> + <type>pmic</type> + <attribute> + <id>HUID</id> + <default>0x00360043</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-1/mi-0/mcc-0/omi-0/ocmb_chip-0/pmic-1</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pmic:k0:n0:s0:p67</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>67</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>port</id><value>1</value></field> + <field><id>devAddr</id><value>0xC0</value></field> + <field><id>i2cMuxBusSelector</id><value>0xFF</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0</value></field> + </default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>67</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/pmic-67</default> </attribute> <attribute> <id>REL_POS</id> @@ -10720,12 +18621,412 @@ </attribute> </targetInstance> +<targetInstance> + <id>sys0node0ocmb16memport0</id> + <type>unit-mem_port</type> + <attribute><id>HUID</id><default>0x004C0010</default></attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/ocmb_chip-16/mem_port-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-0/mcc-0/omi-0/ocmb_chip-0/mem_port-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id><default>ocmb.mp:k0:n0:s0:p01:c00</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0ocmb17memport0</id> + <type>unit-mem_port</type> + <attribute><id>HUID</id><default>0x004C0011</default></attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/ocmb_chip-17/mem_port-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-0/mcc-0/omi-1/ocmb_chip-0/mem_port-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id><default>ocmb.mp:k0:n0:s0:p01:c01</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0ocmb18memport0</id> + <type>unit-mem_port</type> + <attribute><id>HUID</id><default>0x004C0012</default></attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/ocmb_chip-18/mem_port-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-0/mcc-1/omi-0/ocmb_chip-0/mem_port-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id><default>ocmb.mp:k0:n0:s0:p01:c02</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0ocmb19memport0</id> + <type>unit-mem_port</type> + <attribute><id>HUID</id><default>0x004C0013</default></attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/ocmb_chip-19/mem_port-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-0/mcc-1/omi-1/ocmb_chip-0/mem_port-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id><default>ocmb.mp:k0:n0:s0:p01:c03</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0ocmb20memport0</id> + <type>unit-mem_port</type> + <attribute><id>HUID</id><default>0x004C0014</default></attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/ocmb_chip-20/mem_port-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-1/mcc-0/omi-0/ocmb_chip-0/mem_port-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id><default>ocmb.mp:k0:n0:s0:p01:c04</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0ocmb21memport0</id> + <type>unit-mem_port</type> + <attribute><id>HUID</id><default>0x004C0015</default></attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/ocmb_chip-21/mem_port-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-1/mcc-0/omi-1/ocmb_chip-0/mem_port-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id><default>ocmb.mp:k0:n0:s0:p01:c05</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0ocmb22memport0</id> + <type>unit-mem_port</type> + <attribute><id>HUID</id><default>0x004C0016</default></attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/ocmb_chip-22/mem_port-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-1/mcc-1/omi-0/ocmb_chip-0/mem_port-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id><default>ocmb.mp:k0:n0:s0:p01:c06</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0ocmb23memport0</id> + <type>unit-mem_port</type> + <attribute><id>HUID</id><default>0x004C0017</default></attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/ocmb_chip-23/mem_port-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-1/mcc-1/omi-1/ocmb_chip-0/mem_port-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id><default>ocmb.mp:k0:n0:s0:p01:c07</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0ocmb24memport0</id> + <type>unit-mem_port</type> + <attribute><id>HUID</id><default>0x004C0018</default></attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/ocmb_chip-24/mem_port-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-1/mi-0/mcc-0/omi-0/ocmb_chip-0/mem_port-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id><default>ocmb.mp:k0:n0:s0:p01:c08</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0ocmb25memport0</id> + <type>unit-mem_port</type> + <attribute><id>HUID</id><default>0x004C0019</default></attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/ocmb_chip-25/mem_port-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-1/mi-0/mcc-0/omi-1/ocmb_chip-0/mem_port-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id><default>ocmb.mp:k0:n0:s0:p01:c09</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0ocmb26memport0</id> + <type>unit-mem_port</type> + <attribute><id>HUID</id><default>0x004C001A</default></attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/ocmb_chip-26/mem_port-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-1/mi-0/mcc-1/omi-0/ocmb_chip-0/mem_port-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id><default>ocmb.mp:k0:n0:s0:p01:c10</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0ocmb27memport0</id> + <type>unit-mem_port</type> + <attribute><id>HUID</id><default>0x004C001B</default></attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/ocmb_chip-27/mem_port-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-1/mi-0/mcc-1/omi-1/ocmb_chip-0/mem_port-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id><default>ocmb.mp:k0:n0:s0:p01:c11</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0ocmb28memport0</id> + <type>unit-mem_port</type> + <attribute><id>HUID</id><default>0x004C001C</default></attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/ocmb_chip-28/mem_port-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-1/mi-1/mcc-0/omi-0/ocmb_chip-0/mem_port-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id><default>ocmb.mp:k0:n0:s0:p01:c12</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0ocmb29memport0</id> + <type>unit-mem_port</type> + <attribute><id>HUID</id><default>0x004C001D</default></attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/ocmb_chip-29/mem_port-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-1/mi-1/mcc-0/omi-1/ocmb_chip-0/mem_port-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id><default>ocmb.mp:k0:n0:s0:p01:c13</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0ocmb30memport0</id> + <type>unit-mem_port</type> + <attribute><id>HUID</id><default>0x004C001E</default></attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/ocmb_chip-30/mem_port-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-1/mi-1/mcc-1/omi-0/ocmb_chip-0/mem_port-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id><default>ocmb.mp:k0:n0:s0:p01:c14</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0ocmb31memport0</id> + <type>unit-mem_port</type> + <attribute><id>HUID</id><default>0x004C001F</default></attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/ocmb_chip-31/mem_port-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-1/mi-1/mcc-1/omi-1/ocmb_chip-0/mem_port-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>FAPI_NAME</id><default>ocmb.mp:k0:n0:s0:p01:c15</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> +</targetInstance> + <!-- ===================================================================== --> <!-- DIMM Units --> <!-- ===================================================================== --> <targetInstance> <id>sys0node0dimm0</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-ddimm</type> <attribute><id>HUID</id><default>0x00030000</default></attribute> <attribute><id>POSITION</id><default>0</default></attribute> <attribute> @@ -10758,25 +19059,25 @@ <attribute> <id>EEPROM_VPD_PRIMARY_INFO</id> <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>engine</id><value>3</value></field> <field><id>byteAddrOffset</id><value>0x02</value></field> - <field><id>chipCount</id><value>0x01</value></field> <field><id>devAddr</id><value>0xA0</value></field> - <field><id>engine</id><value>3</value></field> - <!-- Engine 3 Port 1 is directly attached to DDIMM0 in the simics axone model --> + <field><id>chipCount</id><value>0x01</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> <field><id>port</id><value>1</value></field> - <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> <field><id>maxMemorySizeKB</id><value>0x4</value></field> - <field><id>writeCycleTime</id><value>20</value></field> - <field><id>writePageSize</id><value>32</value></field> - <field><id>i2cMuxBusSelector</id><value>0xFF</value></field> - <field><id>i2cMuxPath</id><value>physical:sys-0</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> + <field><id>i2cMuxBusSelector</id><value>0x00</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> </default> </attribute> </targetInstance> <targetInstance> <id>sys0node0dimm1</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-ddimm</type> <attribute><id>HUID</id><default>0x00030001</default></attribute> <attribute><id>POSITION</id><default>1</default></attribute> <attribute> @@ -10814,13 +19115,12 @@ <field><id>byteAddrOffset</id><value>0x02</value></field> <field><id>devAddr</id><value>0xA0</value></field> <field><id>chipCount</id><value>0x01</value></field> - <!-- Engine 3 Port 0 connects to a 3 to 8 MUX attached to DDIMM1-8 in the simics axone model --> - <field><id>port</id><value>0</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> <field><id>maxMemorySizeKB</id><value>0x4</value></field> <field><id>writeCycleTime</id><value>05</value></field> <field><id>writePageSize</id><value>0x20</value></field> - <!-- Valid Mux Bus Selections are 0x08-0x0F --> - <field><id>i2cMuxBusSelector</id><value>0x08</value></field> + <field><id>i2cMuxBusSelector</id><value>0x01</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> </default> </attribute> @@ -10828,7 +19128,7 @@ <targetInstance> <id>sys0node0dimm2</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-ddimm</type> <attribute><id>HUID</id><default>0x00030002</default></attribute> <attribute><id>POSITION</id><default>2</default></attribute> <attribute> @@ -10866,13 +19166,12 @@ <field><id>byteAddrOffset</id><value>0x02</value></field> <field><id>devAddr</id><value>0xA0</value></field> <field><id>chipCount</id><value>0x01</value></field> - <!-- Engine 3 Port 0 connects to a 3 to 8 MUX attached to DDIMM1-8 in the simics axone model --> - <field><id>port</id><value>0</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> <field><id>maxMemorySizeKB</id><value>0x4</value></field> <field><id>writeCycleTime</id><value>05</value></field> <field><id>writePageSize</id><value>0x20</value></field> - <!-- Valid Mux Bus Selections are 0x08-0x0F --> - <field><id>i2cMuxBusSelector</id><value>0x09</value></field> + <field><id>i2cMuxBusSelector</id><value>0x02</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> </default> </attribute> @@ -10880,7 +19179,7 @@ <targetInstance> <id>sys0node0dimm3</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-ddimm</type> <attribute><id>HUID</id><default>0x00030003</default></attribute> <attribute><id>POSITION</id><default>3</default></attribute> <attribute> @@ -10918,13 +19217,12 @@ <field><id>byteAddrOffset</id><value>0x02</value></field> <field><id>devAddr</id><value>0xA0</value></field> <field><id>chipCount</id><value>0x01</value></field> - <!-- Engine 3 Port 0 connects to a 3 to 8 MUX attached to DDIMM1-8 in the simics axone model --> - <field><id>port</id><value>0</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> <field><id>maxMemorySizeKB</id><value>0x4</value></field> <field><id>writeCycleTime</id><value>05</value></field> <field><id>writePageSize</id><value>0x20</value></field> - <!-- Valid Mux Bus Selections are 0x08-0x0F --> - <field><id>i2cMuxBusSelector</id><value>0x0A</value></field> + <field><id>i2cMuxBusSelector</id><value>0x03</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> </default> </attribute> @@ -10932,7 +19230,7 @@ <targetInstance> <id>sys0node0dimm4</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-ddimm</type> <attribute><id>HUID</id><default>0x00030004</default></attribute> <attribute><id>POSITION</id><default>4</default></attribute> <attribute> @@ -10970,13 +19268,12 @@ <field><id>byteAddrOffset</id><value>0x02</value></field> <field><id>devAddr</id><value>0xA0</value></field> <field><id>chipCount</id><value>0x01</value></field> - <!-- Engine 3 Port 0 connects to a 3 to 8 MUX attached to DDIMM1-8 in the simics axone model --> - <field><id>port</id><value>0</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> <field><id>maxMemorySizeKB</id><value>0x4</value></field> <field><id>writeCycleTime</id><value>05</value></field> <field><id>writePageSize</id><value>0x20</value></field> - <!-- Valid Mux Bus Selections are 0x08-0x0F --> - <field><id>i2cMuxBusSelector</id><value>0x0B</value></field> + <field><id>i2cMuxBusSelector</id><value>0x04</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> </default> </attribute> @@ -10984,7 +19281,7 @@ <targetInstance> <id>sys0node0dimm5</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-ddimm</type> <attribute><id>HUID</id><default>0x00030005</default></attribute> <attribute><id>POSITION</id><default>5</default></attribute> <attribute> @@ -11022,13 +19319,12 @@ <field><id>byteAddrOffset</id><value>0x02</value></field> <field><id>devAddr</id><value>0xA0</value></field> <field><id>chipCount</id><value>0x01</value></field> - <!-- Engine 3 Port 0 connects to a 3 to 8 MUX attached to DDIMM1-8 in the simics axone model --> - <field><id>port</id><value>0</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> <field><id>maxMemorySizeKB</id><value>0x4</value></field> <field><id>writeCycleTime</id><value>05</value></field> <field><id>writePageSize</id><value>0x20</value></field> - <!-- Valid Mux Bus Selections are 0x08-0x0F --> - <field><id>i2cMuxBusSelector</id><value>0x0C</value></field> + <field><id>i2cMuxBusSelector</id><value>0x05</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> </default> </attribute> @@ -11036,7 +19332,7 @@ <targetInstance> <id>sys0node0dimm6</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-ddimm</type> <attribute><id>HUID</id><default>0x00030006</default></attribute> <attribute><id>POSITION</id><default>6</default></attribute> <attribute> @@ -11074,13 +19370,12 @@ <field><id>byteAddrOffset</id><value>0x02</value></field> <field><id>devAddr</id><value>0xA0</value></field> <field><id>chipCount</id><value>0x01</value></field> - <!-- Engine 3 Port 0 connects to a 3 to 8 MUX attached to DDIMM1-8 in the simics axone model --> - <field><id>port</id><value>0</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> <field><id>maxMemorySizeKB</id><value>0x4</value></field> <field><id>writeCycleTime</id><value>05</value></field> <field><id>writePageSize</id><value>0x20</value></field> - <!-- Valid Mux Bus Selections are 0x08-0x0F --> - <field><id>i2cMuxBusSelector</id><value>0x0D</value></field> + <field><id>i2cMuxBusSelector</id><value>0x06</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> </default> </attribute> @@ -11088,7 +19383,7 @@ <targetInstance> <id>sys0node0dimm7</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-ddimm</type> <attribute><id>HUID</id><default>0x00030007</default></attribute> <attribute><id>POSITION</id><default>7</default></attribute> <attribute> @@ -11126,13 +19421,12 @@ <field><id>byteAddrOffset</id><value>0x02</value></field> <field><id>devAddr</id><value>0xA0</value></field> <field><id>chipCount</id><value>0x01</value></field> - <!-- Engine 3 Port 0 connects to a 3 to 8 MUX attached to DDIMM1-8 in the simics axone model --> - <field><id>port</id><value>0</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> <field><id>maxMemorySizeKB</id><value>0x4</value></field> <field><id>writeCycleTime</id><value>05</value></field> <field><id>writePageSize</id><value>0x20</value></field> - <!-- Valid Mux Bus Selections are 0x08-0x0F --> - <field><id>i2cMuxBusSelector</id><value>0x0E</value></field> + <field><id>i2cMuxBusSelector</id><value>0x07</value></field> <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> </default> </attribute> @@ -11140,7 +19434,7 @@ <targetInstance> <id>sys0node0dimm8</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-ddimm</type> <attribute><id>HUID</id><default>0x00030008</default></attribute> <attribute><id>POSITION</id><default>8</default></attribute> <attribute> @@ -11173,26 +19467,25 @@ <attribute> <id>EEPROM_VPD_PRIMARY_INFO</id> <default> - <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> - <field><id>engine</id><value>3</value></field> <field><id>byteAddrOffset</id><value>0x02</value></field> - <field><id>devAddr</id><value>0xA0</value></field> <field><id>chipCount</id><value>0x01</value></field> - <!-- Engine 3 Port 0 connects to a 3 to 8 MUX attached to DDIMM1-8 in the simics axone model --> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>engine</id><value>3</value></field> + <!-- Engine 3 Port 0 is directly attached to DDIMM8 in the simics axone model --> <field><id>port</id><value>0</value></field> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> <field><id>maxMemorySizeKB</id><value>0x4</value></field> - <field><id>writeCycleTime</id><value>05</value></field> - <field><id>writePageSize</id><value>0x20</value></field> - <!-- Valid Mux Bus Selections are 0x08-0x0F --> - <field><id>i2cMuxBusSelector</id><value>0x0F</value></field> - <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> + <field><id>writeCycleTime</id><value>20</value></field> + <field><id>writePageSize</id><value>32</value></field> + <field><id>i2cMuxBusSelector</id><value>0xFF</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0</value></field> </default> </attribute> </targetInstance> <targetInstance> <id>sys0node0dimm9</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-ddimm</type> <attribute><id>HUID</id><default>0x00030009</default></attribute> <attribute><id>POSITION</id><default>9</default></attribute> <attribute> @@ -11223,22 +19516,29 @@ <default>9</default> </attribute> <!-- Note that EEPROM_VPD_PRIMARY_INFO attrs for OCMB 9-15 and DIMM 9-15 - are invalid. The port value is invalid, info is just here to fully test - the EEPROM caching code (DIMM X should match OCMB X) --> + are invalid. The engine value is set to be engine 1 (C) which has 12 + valid ports according to the simics axone model. Only the first 4 ports + are actually used so we will use 5-12 as dummy ports for the unused dimm targets. + We cannot use the ports on engine 3 (E) becuase simics only has 2 ports marked as valid--> <attribute> <id>EEPROM_VPD_PRIMARY_INFO</id> <default> <field><id>devAddr</id><value>0xA0</value></field> - <field><id>engine</id><value>3</value></field> - <field><id>port</id><value>2</value></field> + <field><id>engine</id><value>1</value></field> + <field><id>port</id><value>5</value></field> <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> </default> </attribute> </targetInstance> <targetInstance> <id>sys0node0dimm10</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-ddimm</type> <attribute><id>HUID</id><default>0x0003000A</default></attribute> <attribute><id>POSITION</id><default>10</default></attribute> <attribute> @@ -11269,22 +19569,29 @@ <default>10</default> </attribute> <!-- Note that EEPROM_VPD_PRIMARY_INFO attrs for OCMB 9-15 and DIMM 9-15 - are invalid. The port value is invalid, info is just here to fully test - the EEPROM caching code (DIMM X should match OCMB X) --> + are invalid. The engine value is set to be engine 1 (C) which has 12 + valid ports according to the simics axone model. Only the first 4 ports + are actually used so we will use 5-12 as dummy ports for the unused dimm targets. + We cannot use the ports on engine 3 (E) becuase simics only has 2 ports marked as valid--> <attribute> <id>EEPROM_VPD_PRIMARY_INFO</id> <default> <field><id>devAddr</id><value>0xA0</value></field> - <field><id>engine</id><value>3</value></field> - <field><id>port</id><value>3</value></field> + <field><id>engine</id><value>1</value></field> + <field><id>port</id><value>6</value></field> <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> </default> </attribute> </targetInstance> <targetInstance> <id>sys0node0dimm11</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-ddimm</type> <attribute><id>HUID</id><default>0x0003000B</default></attribute> <attribute><id>POSITION</id><default>11</default></attribute> <attribute> @@ -11315,22 +19622,27 @@ <default>11</default> </attribute> <!-- Note that EEPROM_VPD_PRIMARY_INFO attrs for OCMB 9-15 and DIMM 9-15 - are invalid. The port value is invalid, info is just here to fully test + are invalid. The port and devAddr values are invalid, info is just here to fully test the EEPROM caching code (DIMM X should match OCMB X) --> <attribute> <id>EEPROM_VPD_PRIMARY_INFO</id> <default> - <field><id>devAddr</id><value>0xA0</value></field> + <field><id>devAddr</id><value>0xA4</value></field> <field><id>engine</id><value>3</value></field> <field><id>port</id><value>4</value></field> <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> </default> </attribute> </targetInstance> <targetInstance> <id>sys0node0dimm12</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-ddimm</type> <attribute><id>HUID</id><default>0x0003000C</default></attribute> <attribute><id>POSITION</id><default>12</default></attribute> <attribute> @@ -11361,22 +19673,27 @@ <default>12</default> </attribute> <!-- Note that EEPROM_VPD_PRIMARY_INFO attrs for OCMB 9-15 and DIMM 9-15 - are invalid. The port value is invalid, info is just here to fully test + are invalid. The port and devAddr values are invalid, info is just here to fully test the EEPROM caching code (DIMM X should match OCMB X) --> <attribute> <id>EEPROM_VPD_PRIMARY_INFO</id> <default> - <field><id>devAddr</id><value>0xA0</value></field> + <field><id>devAddr</id><value>0xA5</value></field> <field><id>engine</id><value>3</value></field> <field><id>port</id><value>5</value></field> <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> </default> </attribute> </targetInstance> <targetInstance> <id>sys0node0dimm13</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-ddimm</type> <attribute><id>HUID</id><default>0x0003000D</default></attribute> <attribute><id>POSITION</id><default>13</default></attribute> <attribute> @@ -11407,22 +19724,27 @@ <default>13</default> </attribute> <!-- Note that EEPROM_VPD_PRIMARY_INFO attrs for OCMB 9-15 and DIMM 9-15 - are invalid. The port value is invalid, info is just here to fully test + are invalid. The port and devAddr values are invalid, info is just here to fully test the EEPROM caching code (DIMM X should match OCMB X) --> <attribute> <id>EEPROM_VPD_PRIMARY_INFO</id> <default> - <field><id>devAddr</id><value>0xA0</value></field> + <field><id>devAddr</id><value>0xA6</value></field> <field><id>engine</id><value>3</value></field> <field><id>port</id><value>6</value></field> <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> </default> </attribute> </targetInstance> <targetInstance> <id>sys0node0dimm14</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-ddimm</type> <attribute><id>HUID</id><default>0x0003000E</default></attribute> <attribute><id>POSITION</id><default>14</default></attribute> <attribute> @@ -11453,22 +19775,27 @@ <default>14</default> </attribute> <!-- Note that EEPROM_VPD_PRIMARY_INFO attrs for OCMB 9-15 and DIMM 9-15 - are invalid. The port value is invalid, info is just here to fully test + are invalid. The port and devAddr values are invalid, info is just here to fully test the EEPROM caching code (DIMM X should match OCMB X) --> <attribute> <id>EEPROM_VPD_PRIMARY_INFO</id> <default> - <field><id>devAddr</id><value>0xA0</value></field> + <field><id>devAddr</id><value>0xA7</value></field> <field><id>engine</id><value>3</value></field> <field><id>port</id><value>7</value></field> <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> </default> </attribute> </targetInstance> <targetInstance> <id>sys0node0dimm15</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-ddimm</type> <attribute><id>HUID</id><default>0x0003000F</default></attribute> <attribute><id>POSITION</id><default>15</default></attribute> <attribute> @@ -11499,15 +19826,479 @@ <default>15</default> </attribute> <!-- Note that EEPROM_VPD_PRIMARY_INFO attrs for OCMB 9-15 and DIMM 9-15 - are invalid. The port value is invalid, info is just here to fully test + are invalid. The port and devAddr values are invalid, info is just here to fully test the EEPROM caching code (DIMM X should match OCMB X) --> <attribute> <id>EEPROM_VPD_PRIMARY_INFO</id> <default> - <field><id>devAddr</id><value>0xA0</value></field> + <field><id>devAddr</id><value>0xA8</value></field> <field><id>engine</id><value>3</value></field> <field><id>port</id><value>8</value></field> <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> + </default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0dimm16</id> + <type>lcard-dimm-ddimm</type> + <attribute><id>HUID</id><default>0x00030010</default></attribute> + <attribute><id>POSITION</id><default>16</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>dimm:k0:n0:s0:p16</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/dimm-16</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>16</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-0/mcc-0/omi-0/ocmb_chip-0/mem_port-0/dimm-0</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>16</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>VPD_REC_NUM</id> + <default>16</default> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> + <field><id>i2cMuxBusSelector</id><value>0x00</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0dimm17</id> + <type>lcard-dimm-ddimm</type> + <attribute><id>HUID</id><default>0x00030011</default></attribute> + <attribute><id>POSITION</id><default>17</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>dimm:k0:n0:s0:p17</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/dimm-17</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-0/mcc-0/omi-1/ocmb_chip-0/mem_port-0/dimm-0</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>17</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>VPD_REC_NUM</id> + <default>17</default> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> + <field><id>i2cMuxBusSelector</id><value>0x01</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0dimm18</id> + <type>lcard-dimm-ddimm</type> + <attribute><id>HUID</id><default>0x00030012</default></attribute> + <attribute><id>POSITION</id><default>18</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>dimm:k0:n0:s0:p18</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/dimm-18</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>18</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-0/mcc-1/omi-0/ocmb_chip-0/mem_port-0/dimm-0</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>18</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>VPD_REC_NUM</id> + <default>18</default> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> + <field><id>i2cMuxBusSelector</id><value>0x02</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0dimm19</id> + <type>lcard-dimm-ddimm</type> + <attribute><id>HUID</id><default>0x00030013</default></attribute> + <attribute><id>POSITION</id><default>19</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>dimm:k0:n0:s0:p19</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/dimm-19</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>19</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-0/mcc-1/omi-1/ocmb_chip-0/mem_port-0/dimm-0</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>19</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>VPD_REC_NUM</id> + <default>19</default> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> + <field><id>i2cMuxBusSelector</id><value>0x03</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0dimm20</id> + <type>lcard-dimm-ddimm</type> + <attribute><id>HUID</id><default>0x00030014</default></attribute> + <attribute><id>POSITION</id><default>20</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>dimm:k0:n0:s0:p20</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/dimm-20</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>20</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-1/mcc-0/omi-0/ocmb_chip-0/mem_port-0/dimm-0</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>20</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>VPD_REC_NUM</id> + <default>20</default> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> + <field><id>i2cMuxBusSelector</id><value>0x04</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0dimm21</id> + <type>lcard-dimm-ddimm</type> + <attribute><id>HUID</id><default>0x00030015</default></attribute> + <attribute><id>POSITION</id><default>21</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>dimm:k0:n0:s0:p21</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/dimm-21</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>21</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-1/mcc-0/omi-1/ocmb_chip-0/mem_port-0/dimm-0</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>21</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>VPD_REC_NUM</id> + <default>21</default> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> + <field><id>i2cMuxBusSelector</id><value>0x05</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0dimm22</id> + <type>lcard-dimm-ddimm</type> + <attribute><id>HUID</id><default>0x00030016</default></attribute> + <attribute><id>POSITION</id><default>22</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>dimm:k0:n0:s0:p22</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/dimm-22</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>22</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-1/mcc-1/omi-0/ocmb_chip-0/mem_port-0/dimm-0</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>22</default> + </attribute> + <attribute> + <id>VPD_REC_NUM</id> + <default>22</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> + <field><id>i2cMuxBusSelector</id><value>0x06</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0dimm23</id> + <type>lcard-dimm-ddimm</type> + <attribute><id>HUID</id><default>0x00030017</default></attribute> + <attribute><id>POSITION</id><default>23</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>dimm:k0:n0:s0:p23</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/dimm-23</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>23</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/mi-1/mcc-1/omi-1/ocmb_chip-0/mem_port-0/dimm-0</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>23</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>VPD_REC_NUM</id> + <default>23</default> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <!-- Engine 3 Port 1 connects to a 3 to 8 MUX attached to DDIMM0-7 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> + <field><id>i2cMuxBusSelector</id><value>0x07</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-2</value></field> + </default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0dimm24</id> + <type>lcard-dimm-ddimm</type> + <attribute><id>HUID</id><default>0x00030018</default></attribute> + <attribute><id>POSITION</id><default>24</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>dimm:k0:n0:s0:p24</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/dimm-24</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>24</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-1/mi-0/mcc-0/omi-0/ocmb_chip-0/mem_port-0/dimm-0</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>24</default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>VPD_REC_NUM</id> + <default>24</default> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + <default> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>engine</id><value>3</value></field> + <!-- Engine 3 Port 0 is directly attached to DDIMM8 in the simics axone model --> + <field><id>port</id><value>0</value></field> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> + <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>writeCycleTime</id><value>20</value></field> + <field><id>writePageSize</id><value>32</value></field> + <field><id>i2cMuxBusSelector</id><value>0xFF</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0</value></field> </default> </attribute> </targetInstance> @@ -11887,6 +20678,378 @@ </attribute> </targetInstance> +<targetInstance> + <id>sys0node0proc1mc0omic0</id> + <type>unit-omic-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/omic-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x07</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.omic:k0:n0:s0:p01:c0</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>6</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x004A0006</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>6</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-7</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-0/omic-0</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>OMIC</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1mc0omic1</id> + <type>unit-omic-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/omic-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x07</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.omic:k0:n0:s0:p01:c1</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>7</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x004A0007</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>7</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-7</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-0/omic-1</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>OMIC</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1mc0omic2</id> + <type>unit-omic-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-0/omic-2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x07</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.omic:k0:n0:s0:p01:c2</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>8</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x004A0008</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>8</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-7</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-0/omic-2</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>2</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>OMIC</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1mc1omic0</id> + <type>unit-omic-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-1/omic-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x08</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.omic:k0:n0:s0:p01:c3</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>9</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x004A0009</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>9</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-8</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-1/omic-0</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>OMIC</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1mc1omic1</id> + <type>unit-omic-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-1/omic-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>4</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x08</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.omic:k0:n0:s0:p01:c4</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>10</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x004A000A</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>10</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-8</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-1/omic-1</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>OMIC</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1mc1omic2</id> + <type>unit-omic-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/mc-1/omic-2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>5</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x08</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.omic:k0:n0:s0:p01:c5</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>11</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x004A000B</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>11</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-8</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/mc-1/omic-2</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>2</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>OMIC</default> + </attribute> +</targetInstance> + <!-- ===================================================================== --> <!-- END MEMORY SUBSYSTEM --> <!-- ===================================================================== --> @@ -12417,6 +21580,122 @@ </targetInstance> <targetInstance> + <id>sys0node0proc0perv10</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-0/perv-10</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>10</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>10</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p00:c10</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>10</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C000A</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>10</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-0/perv-10</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>10</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc0perv11</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-0/perv-11</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>11</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>11</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p00:c11</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>11</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C000B</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>11</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-0/perv-11</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>11</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> <id>sys0node0proc0perv12</id> <type>unit-perv-axone</type> <attribute> @@ -14396,6 +23675,2450 @@ </attribute> </targetInstance> +<targetInstance> + <id>sys0node0proc1perv1</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>1</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c1</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>57</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C0039</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>57</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-1</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>1</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv2</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>2</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c2</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>58</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C003A</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>58</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-2</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>2</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv3</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-3</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>3</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c3</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>59</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C003B</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>59</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-3</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>3</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv4</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-4</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>4</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>4</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c4</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>60</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C003C</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>60</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-4</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>4</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv5</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-5</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>5</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>5</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c5</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>61</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C003D</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>61</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-5</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>5</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv6</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-6</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>6</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>6</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c6</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>62</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C003E</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>62</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-6</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>6</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv7</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-7</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>7</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>7</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c7</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>63</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C003F</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>63</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-7</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>7</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv8</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-8</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>8</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>8</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c8</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>64</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C0040</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>64</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-8</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>8</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv9</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-9</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>9</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>9</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c9</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>65</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C0041</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>65</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-9</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>9</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv10</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-10</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>10</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>10</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c10</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>66</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C0042</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>66</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-10</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>10</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv11</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-11</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>11</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>11</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c11</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>67</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C0043</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>67</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-11</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>11</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv12</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-12</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>12</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>12</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c12</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>68</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C0044</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>68</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-12</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>12</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv13</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-13</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>13</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>13</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c13</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>69</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C0045</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>69</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-13</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>13</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv14</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-14</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>14</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>14</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c14</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>70</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C0046</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>70</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-14</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>14</default> + </attribute> + <attribute> + <id>RESOURCE_IS_CRITICAL</id> + <default>0</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv15</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-15</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>15</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>15</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c15</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>71</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C0047</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>71</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-15</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>15</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv16</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-16</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>16</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>16</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c16</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>72</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C0048</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>72</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-16</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>16</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv17</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-17</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>17</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>17</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c17</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>73</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C0049</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>73</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-17</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>17</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv18</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-18</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>18</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>18</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c18</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>74</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C004A</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>74</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-18</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>18</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv19</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-19</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>19</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>19</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c19</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>75</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C004B</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>75</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-19</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>19</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv20</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-20</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>20</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>20</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c20</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>76</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C004C</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>76</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-20</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>20</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv21</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-21</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>21</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>21</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c21</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>77</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C004D</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>77</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-21</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>21</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv32</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-32</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>32</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>32</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c32</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>88</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C0058</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>88</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-32</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>32</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv33</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-33</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>33</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>33</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c33</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>89</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C0059</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>69</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-33</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>33</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv34</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-34</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>34</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>34</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c34</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>90</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C005A</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>90</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-34</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>34</default> + </attribute> + <attribute> + <id>RESOURCE_IS_CRITICAL</id> + <default>0</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv35</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-35</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>35</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>35</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c35</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>91</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C005B</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>91</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-35</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>35</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv36</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-36</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>36</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>36</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c36</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>92</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C005C</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>92</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-36</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>36</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv37</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-37</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>37</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>37</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c37</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>93</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C005D</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>93</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-37</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>37</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv38</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-38</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>38</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>38</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c38</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>94</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C005E</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>94</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-38</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>38</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv39</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-39</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>39</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>39</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c39</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>95</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C005F</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>85</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-39</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>39</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv40</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-40</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>40</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>40</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c40</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>96</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C0060</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>96</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-40</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>40</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv41</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-41</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>41</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>41</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c41</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>97</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C0061</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>97</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-41</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>41</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv42</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-42</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>42</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>42</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c42</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>98</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C0062</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>98</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-42</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>42</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv43</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-43</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>43</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>43</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c43</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>99</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C0063</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>99</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-43</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>43</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv44</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-44</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>44</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>44</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c44</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>100</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C0064</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>100</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-44</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>44</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv45</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-45</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>45</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>45</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c45</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>101</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C0065</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>101</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-45</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>45</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv46</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-46</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>46</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>46</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c46</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>102</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C0066</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>102</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-46</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>46</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv47</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-47</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>47</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>47</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c47</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>103</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C0067</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>103</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-47</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>47</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv48</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-48</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>48</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>48</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c48</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>104</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C0068</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>104</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-48</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>48</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv49</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-49</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>49</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>49</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c49</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>105</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C0069</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>105</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-49</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>49</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv50</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-50</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>50</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>50</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c50</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>106</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C006A</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>106</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-50</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>50</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv51</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-51</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>51</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>51</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c51</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>107</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C006B</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>107</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-51</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>51</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1perv52</id> + <type>unit-perv-axone</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/perv-52</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>52</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>52</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p01:c52</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>108</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C006B</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>108</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/perv-52</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>52</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + <!-- ===================================================================== --> <!-- I2C_MUX --> <!-- ===================================================================== --> @@ -14428,13 +26151,48 @@ <default>0</default> </attribute> <attribute> - <id>FAPI_NAME</id> - <default>NA</default> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>port</id><value>1</value></field> + <field><id>devAddr</id><value>0xE0</value></field> + <field><id>engine</id><value>3</value></field> + </default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0i2cmux2</id> + <type>i2c_mux_pca9847</type> + <attribute> + <id>HUID</id> + <default>0x004D0002</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/i2c_mux-2</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/i2c_mux-0</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>0</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>0</value></field> + </default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>2</default> </attribute> <attribute> <id>FAPI_I2C_CONTROL_INFO</id> <default> - <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-1</value></field> <field><id>port</id><value>1</value></field> <field><id>devAddr</id><value>0xE0</value></field> <field><id>engine</id><value>3</value></field> @@ -14442,4 +26200,97 @@ </attribute> </targetInstance> +<!-- ===================================================================== --> +<!-- XBUS --> +<!-- ===================================================================== --> +<targetInstance> + <id>sys0node0proc0xbus2</id> + <type>unit-xbus-axone</type> + <attribute><id>HUID</id><default>0x000E0002</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.xbus:k0:n0:s0:p00:c2</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-0/xbus-2</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-0/xbus-2</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>2</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x06</default> + </attribute> + <attribute> + <id>PEER_TARGET</id> + <default>physical:sys-0/node-0/proc-1/xbus-0</default> + </attribute> + <attribute> + <id>PEER_PATH</id> + <default>physical:sys-0/node-0/proc-1/xbus-0</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-0/perv-6</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1xbus0</id> + <type>unit-xbus-axone</type> + <attribute><id>HUID</id><default>0x000E0003</default></attribute> + <attribute> + <id>FAPI_NAME</id><default>pu.xbus:k0:n0:s0:p01:c0</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/xbus-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/xbus-0</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>3</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>3</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>0x06</default> + </attribute> + <attribute> + <id>PEER_TARGET</id> + <default>physical:sys-0/node-0/proc-0/xbus-2</default> + </attribute> + <attribute> + <id>PEER_PATH</id> + <default>physical:sys-0/node-0/proc-0/xbus-2</default> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + <default>physical:sys-0/node-0/proc-1/perv-6</default> + </attribute> +</targetInstance> + </attributes> diff --git a/src/usr/targeting/common/xmltohb/simics_CUMULUS.system.xml b/src/usr/targeting/common/xmltohb/simics_CUMULUS.system.xml index e82b9e38a..17aee231d 100644 --- a/src/usr/targeting/common/xmltohb/simics_CUMULUS.system.xml +++ b/src/usr/targeting/common/xmltohb/simics_CUMULUS.system.xml @@ -7958,7 +7958,7 @@ </attribute> <attribute> <id>AFFINITY_PATH</id> - <default>physical:sys-0/node-0/proc-0/nx-0</default> + <default>affinity:sys-0/node-0/proc-0/nx-0</default> </attribute> <attribute> <id>ORDINAL_ID</id> @@ -8955,6 +8955,138 @@ <default>PERV</default> </attribute> </targetInstance> + +<targetInstance> + <id>sys0node0proc0perv10</id> + <type>unit-perv-cumulus</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-0/perv-10</default> + </attribute> + + + <attribute> + <id>CHIP_UNIT</id> + <default>10</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>10</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p00:c10</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>10</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C000A</default> + </attribute> + + + + + + <attribute> + <id>ORDINAL_ID</id> + <default>10</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-0/perv-10</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>10</default> + </attribute> + <attribute> + <id>RESOURCE_IS_CRITICAL</id> + <default>0</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc0perv11</id> + <type>unit-perv-cumulus</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-0/perv-11</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>11</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>11</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p00:c11</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>11</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C000B</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>11</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-0/perv-11</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>11</default> + </attribute> + <attribute> + <id>RESOURCE_IS_CRITICAL</id> + <default>0</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + <targetInstance> <id>sys0node0proc0perv12</id> <type>unit-perv-cumulus</type> diff --git a/src/usr/targeting/common/xmltohb/simics_CUMULUS_CDIMM.system.xml b/src/usr/targeting/common/xmltohb/simics_CUMULUS_CDIMM.system.xml index fe3bea78c..6e0177ea2 100644 --- a/src/usr/targeting/common/xmltohb/simics_CUMULUS_CDIMM.system.xml +++ b/src/usr/targeting/common/xmltohb/simics_CUMULUS_CDIMM.system.xml @@ -7950,7 +7950,7 @@ </attribute> <attribute> <id>AFFINITY_PATH</id> - <default>physical:sys-0/node-0/proc-0/nx-0</default> + <default>affinity:sys-0/node-0/proc-0/nx-0</default> </attribute> <attribute> <id>ORDINAL_ID</id> @@ -8947,6 +8947,134 @@ <default>PERV</default> </attribute> </targetInstance> + + +<targetInstance> + <id>sys0node0proc0perv10</id> + <type>unit-perv-cumulus</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-0/perv-10</default> + </attribute> + + + <attribute> + <id>CHIP_UNIT</id> + <default>10</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>10</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p00:c10</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>10</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C000A</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>10</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-0/perv-10</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>10</default> + </attribute> + <attribute> + <id>RESOURCE_IS_CRITICAL</id> + <default>0</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc0perv11</id> + <type>unit-perv-cumulus</type> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-0/perv-11</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>11</default> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + <default>11</default> + </attribute> + <attribute> + <id>CLASS</id> + <default>UNIT</default> + </attribute> + <attribute> + <id>FAPI_NAME</id> + <default>pu.perv:k0:n0:s0:p00:c11</default> + </attribute> + <attribute> + <id>FAPI_POS</id> + <default>11</default> + </attribute> + <attribute> + <id>HUID</id> + <default>0x002C000B</default> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + <default>11</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-0/perv-11</default> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + <default> + <field><id>reserved</id><value>0</value></field> + <field><id>supportsFsiScom</id><value>1</value></field> + <field><id>supportsInbandScom</id><value>0</value></field> + <field><id>supportsXscom</id><value>1</value></field> + </default> + </attribute> + <attribute> + <id>REL_POS</id> + <default>11</default> + </attribute> + <attribute> + <id>RESOURCE_IS_CRITICAL</id> + <default>0</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>PERV</default> + </attribute> +</targetInstance> + <targetInstance> <id>sys0node0proc0perv12</id> <type>unit-perv-cumulus</type> diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml index 1b5b615a9..f87b8fa6e 100644 --- a/src/usr/targeting/common/xmltohb/target_types.xml +++ b/src/usr/targeting/common/xmltohb/target_types.xml @@ -159,6 +159,13 @@ <parent>chip-tpm-cectpm</parent> </targetType> + <!-- This special I2C_MUX target adapts the MRW to Hostboot's specific I2C_MUX + target. All attributes should be declared against the parent target --> + <targetType> + <id>chip-PCA9847</id> + <parent>i2c_mux_pca9847</parent> + </targetType> + <!-- This special UCD target adapts the MRW to Hostboot's specific UCD target. All attributes should be declared against the parent target. --> @@ -404,7 +411,7 @@ </attribute> </targetType> - <!-- Generic OCMB --> + <!-- Generic OCMB, used for Explorer, Gemini, etc --> <targetType> <id>chip-ocmb</id> <parent>chip</parent> @@ -413,6 +420,60 @@ <id>DECONFIG_GARDABLE</id> </attribute> <attribute> + <default> + <field> + <value>0xFF</value> + <id>byteAddrOffset</id> + </field> + <field> + <value>0xFF</value> + <id>chipCount</id> + </field> + <field> + <value>0xFF</value> + <id>devAddr</id> + </field> + <field> + <!--Since enum values cannot be used as default values in + a complexType, this is a workaround to set the value to the + corresponding enum value.--> + <!--value>DDIMM</value--> + <value>0x4</value> + <id>eepromContentType</id> + </field> + <field> + <value>0xFF</value> + <id>engine</id> + </field> + <field> + <value>physical:sys-0</value> + <id>i2cMasterPath</id> + </field> + <field> + <value>0xFF</value> + <id>i2cMuxBusSelector</id> + </field> + <field> + <value>physical:sys-0</value> + <id>i2cMuxPath</id> + </field> + <field> + <value>0xFFFFFFFFFFFFFFFF</value> + <id>maxMemorySizeKB</id> + </field> + <field> + <value>0xFF</value> + <id>port</id> + </field> + <field> + <value>0xFFFFFFFFFFFFFFFF</value> + <id>writeCycleTime</id> + </field> + <field> + <value>0xFFFFFFFFFFFFFFFF</value> + <id>writePageSize</id> + </field> + </default> <id>EEPROM_VPD_PRIMARY_INFO</id> </attribute> <attribute> @@ -426,6 +487,10 @@ <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> </attribute> <attribute> + <default>OCMB</default> + <id>MODEL</id> + </attribute> + <attribute> <default> <field> <id>childRollupAllowed</id> @@ -443,23 +508,6 @@ <id>PARENT_DECONFIG_RULES</id> </attribute> <attribute> - <default>OCMB_CHIP</default> - <id>TYPE</id> - </attribute> - <attribute> - <id>VPD_REC_NUM</id> - </attribute> - </targetType> - - <!-- Explorer OCMB --> - <targetType> - <id>chip-ocmb-explorer</id> - <parent>chip-ocmb</parent> - <attribute> - <default>EXPLORER</default> - <id>MODEL</id> - </attribute> - <attribute> <default> <field> <id>reserved</id> @@ -509,6 +557,13 @@ </default> <id>SCOM_SWITCHES</id> </attribute> + <attribute> + <default>OCMB_CHIP</default> + <id>TYPE</id> + </attribute> + <attribute> + <id>VPD_REC_NUM</id> + </attribute> </targetType> <targetType> @@ -601,9 +656,6 @@ <id>LOCATION_CODE</id> </attribute> <attribute> - <id>NVDIMM_ARMED</id> - </attribute> - <attribute> <default> <field> <id>childRollupAllowed</id> @@ -753,9 +805,117 @@ <id>EEPROM_SBE_PRIMARY_INFO</id> </attribute> <attribute> + <default> + <field> + <value>0xFF</value> + <id>byteAddrOffset</id> + </field> + <field> + <value>0xFF</value> + <id>chipCount</id> + </field> + <field> + <value>0xFF</value> + <id>devAddr</id> + </field> + <field> + <!--Since enum values cannot be used as default values in + a complexType, this is a workaround to set the value to the + corresponding enum value.--> + <!--value>IBM_MVPD</value--> + <value>0x3</value> + <id>eepromContentType</id> + </field> + <field> + <value>0xFF</value> + <id>engine</id> + </field> + <field> + <value>physical:sys-0</value> + <id>i2cMasterPath</id> + </field> + <field> + <value>0xFF</value> + <id>i2cMuxBusSelector</id> + </field> + <field> + <value>physical:sys-0</value> + <id>i2cMuxPath</id> + </field> + <field> + <value>0xFFFFFFFFFFFFFFFF</value> + <id>maxMemorySizeKB</id> + </field> + <field> + <value>0xFF</value> + <id>port</id> + </field> + <field> + <value>0xFFFFFFFFFFFFFFFF</value> + <id>writeCycleTime</id> + </field> + <field> + <value>0xFFFFFFFFFFFFFFFF</value> + <id>writePageSize</id> + </field> + </default> <id>EEPROM_VPD_BACKUP_INFO</id> </attribute> <attribute> + <default> + <field> + <value>0xFF</value> + <id>byteAddrOffset</id> + </field> + <field> + <value>0xFF</value> + <id>chipCount</id> + </field> + <field> + <value>0xFF</value> + <id>devAddr</id> + </field> + <field> + <!--Since enum values cannot be used as default values in + a complexType, this is a workaround to set the value to the + corresponding enum value.--> + <!--value>IBM_MVPD</value--> + <value>0x3</value> + <id>eepromContentType</id> + </field> + <field> + <value>0xFF</value> + <id>engine</id> + </field> + <field> + <value>physical:sys-0</value> + <id>i2cMasterPath</id> + </field> + <field> + <value>0xFF</value> + <id>i2cMuxBusSelector</id> + </field> + <field> + <value>physical:sys-0</value> + <id>i2cMuxPath</id> + </field> + <field> + <value>0xFFFFFFFFFFFFFFFF</value> + <id>maxMemorySizeKB</id> + </field> + <field> + <value>0xFF</value> + <id>port</id> + </field> + <field> + <value>0xFFFFFFFFFFFFFFFF</value> + <id>writeCycleTime</id> + </field> + <field> + <value>0xFFFFFFFFFFFFFFFF</value> + <id>writePageSize</id> + </field> + </default> <id>EEPROM_VPD_PRIMARY_INFO</id> </attribute> <attribute> @@ -990,6 +1150,60 @@ <id>DECONFIG_GARDABLE</id> </attribute> <attribute> + <default> + <field> + <value>0xFF</value> + <id>byteAddrOffset</id> + </field> + <field> + <value>0xFF</value> + <id>chipCount</id> + </field> + <field> + <value>0xFF</value> + <id>devAddr</id> + </field> + <field> + <!--Since enum values cannot be used as default values in + a complexType, this is a workaround to set the value to the + corresponding enum value.--> + <!--value>IBM_FRUVPD</value--> + <value>0x2</value> + <id>eepromContentType</id> + </field> + <field> + <value>0xFF</value> + <id>engine</id> + </field> + <field> + <value>physical:sys-0</value> + <id>i2cMasterPath</id> + </field> + <field> + <value>0xFF</value> + <id>i2cMuxBusSelector</id> + </field> + <field> + <value>physical:sys-0</value> + <id>i2cMuxPath</id> + </field> + <field> + <value>0xFFFFFFFFFFFFFFFF</value> + <id>maxMemorySizeKB</id> + </field> + <field> + <value>0xFF</value> + <id>port</id> + </field> + <field> + <value>0xFFFFFFFFFFFFFFFF</value> + <id>writeCycleTime</id> + </field> + <field> + <value>0xFFFFFFFFFFFFFFFF</value> + <id>writePageSize</id> + </field> + </default> <id>EEPROM_VPD_PRIMARY_INFO</id> </attribute> <attribute> @@ -1153,6 +1367,7 @@ </attribute> </targetType> + <!-- Represents a I2C Mux device that is compatible with the PCA9847 spec --> <targetType> <id>i2c_mux_pca9847</id> <parent>chip</parent> @@ -1205,6 +1420,60 @@ <id>EEPROM_NV_INFO</id> </attribute> <attribute> + <default> + <field> + <value>0xFF</value> + <id>byteAddrOffset</id> + </field> + <field> + <value>0xFF</value> + <id>chipCount</id> + </field> + <field> + <value>0xFF</value> + <id>devAddr</id> + </field> + <field> + <!--Since enum values cannot be used as default values in + a complexType, this is a workaround to set the value to the + corresponding enum value.--> + <!--value>ISDIMM</value--> + <value>0x1</value> + <id>eepromContentType</id> + </field> + <field> + <value>0xFF</value> + <id>engine</id> + </field> + <field> + <value>physical:sys-0</value> + <id>i2cMasterPath</id> + </field> + <field> + <value>0xFF</value> + <id>i2cMuxBusSelector</id> + </field> + <field> + <value>physical:sys-0</value> + <id>i2cMuxPath</id> + </field> + <field> + <value>0xFFFFFFFFFFFFFFFF</value> + <id>maxMemorySizeKB</id> + </field> + <field> + <value>0xFF</value> + <id>port</id> + </field> + <field> + <value>0xFFFFFFFFFFFFFFFF</value> + <id>writeCycleTime</id> + </field> + <field> + <value>0xFFFFFFFFFFFFFFFF</value> + <id>writePageSize</id> + </field> + </default> <id>EEPROM_VPD_PRIMARY_INFO</id> </attribute> <attribute> @@ -1226,6 +1495,9 @@ <id>MEM_PORT</id> </attribute> <attribute> + <id>NVDIMM_ARMED</id> + </attribute> + <attribute> <id>NV_OPS_TIMEOUT_MSEC</id> </attribute> <attribute> @@ -1279,6 +1551,68 @@ </targetType> <targetType> + <id>lcard-dimm-ddimm</id> + <parent>lcard-dimm</parent> + <attribute> + <default> + <field> + <value>0xFF</value> + <id>byteAddrOffset</id> + </field> + <field> + <value>0xFF</value> + <id>chipCount</id> + </field> + <field> + <value>0xFF</value> + <id>devAddr</id> + </field> + <field> + <!--Since enum values cannot be used as default values in + a complexType, this is a workaround to set the value to the + corresponding enum value.--> + <!--value>DDIMM</value--> + <value>0x4</value> + <id>eepromContentType</id> + </field> + <field> + <value>0xFF</value> + <id>engine</id> + </field> + <field> + <value>physical:sys-0</value> + <id>i2cMasterPath</id> + </field> + <field> + <value>0xFF</value> + <id>i2cMuxBusSelector</id> + </field> + <field> + <value>physical:sys-0</value> + <id>i2cMuxPath</id> + </field> + <field> + <value>0xFFFFFFFFFFFFFFFF</value> + <id>maxMemorySizeKB</id> + </field> + <field> + <value>0xFF</value> + <id>port</id> + </field> + <field> + <value>0xFFFFFFFFFFFFFFFF</value> + <id>writeCycleTime</id> + </field> + <field> + <value>0xFFFFFFFFFFFFFFFF</value> + <id>writePageSize</id> + </field> + </default> + <id>EEPROM_VPD_PRIMARY_INFO</id> + </attribute> + </targetType> + + <targetType> <id>lcard-dimm-ddr4</id> <parent>lcard-dimm</parent> </targetType> @@ -1465,6 +1799,9 @@ <id>BOOT_FREQ_MHZ</id> </attribute> <attribute> + <id>BPM_UPDATE_OVERRIDE</id> + </attribute> + <attribute> <id>BRAZOS_RX_FIFO_OVERRIDE</id> </attribute> <attribute> @@ -1520,6 +1857,12 @@ <id>FIELD_TH_P8EX_L3_LINE_DELETES</id> </attribute> <attribute> + <id>FORCE_NVDIMM_RESET</id> + </attribute> + <attribute> + <id>FORCE_SRAM_MMIO_OVER_I2C</id> + </attribute> + <attribute> <id>FREQ_CORE_CEILING_MHZ</id> </attribute> <attribute> @@ -1578,6 +1921,9 @@ <id>ISTEP_PAUSE_ENABLE</id> </attribute> <attribute> + <id>KEY_CLEAR_REQUEST</id> + </attribute> + <attribute> <default>0x0006030000000000</default> <id>LPC_BUS_ADDR</id> </attribute> @@ -1613,6 +1959,9 @@ <id>MAX_SBE_SEEPROM_SIZE</id> </attribute> <attribute> + <id>MC_PLL_BUCKET</id> + </attribute> + <attribute> <id>MFG_TRACE_ENABLE</id> </attribute> <attribute> @@ -1767,6 +2116,21 @@ <id>NUMERIC_POD_TYPE_TEST</id> </attribute> <attribute> + <id>NVDIMM_AUTO_ARM</id> + </attribute> + <attribute> + <id>NVDIMM_ENCRYPTION_ENABLE</id> + </attribute> + <attribute> + <id>NVDIMM_ENCRYPTION_KEYS_ANCHOR</id> + </attribute> + <attribute> + <id>NVDIMM_ENCRYPTION_KEYS_FW</id> + </attribute> + <attribute> + <id>OCMB_FW_UPDATE_OVERRIDE</id> + </attribute> + <attribute> <id>O_EREPAIR_THRESHOLD_FIELD</id> </attribute> <attribute> @@ -2356,6 +2720,9 @@ <id>MODEL</id> <default>AXONE</default> </attribute> + <attribute> + <id>OMI_INBAND_BAR_BASE_ADDR_OFFSET</id> + </attribute> </targetType> <targetType> @@ -2640,6 +3007,60 @@ <id>DECONFIG_GARDABLE</id> </attribute> <attribute> + <default> + <field> + <value>0xFF</value> + <id>byteAddrOffset</id> + </field> + <field> + <value>0xFF</value> + <id>chipCount</id> + </field> + <field> + <value>0xFF</value> + <id>devAddr</id> + </field> + <field> + <!--Since enum values cannot be used as default values in + a complexType, this is a workaround to set the value to the + corresponding enum value.--> + <!--value>IBM_FRUVPD</value--> + <value>0x2</value> + <id>eepromContentType</id> + </field> + <field> + <value>0xFF</value> + <id>engine</id> + </field> + <field> + <value>physical:sys-0</value> + <id>i2cMasterPath</id> + </field> + <field> + <value>0xFF</value> + <id>i2cMuxBusSelector</id> + </field> + <field> + <value>physical:sys-0</value> + <id>i2cMuxPath</id> + </field> + <field> + <value>0xFFFFFFFFFFFFFFFF</value> + <id>maxMemorySizeKB</id> + </field> + <field> + <value>0xFF</value> + <id>port</id> + </field> + <field> + <value>0xFFFFFFFFFFFFFFFF</value> + <id>writeCycleTime</id> + </field> + <field> + <value>0xFFFFFFFFFFFFFFFF</value> + <id>writePageSize</id> + </field> + </default> <id>EEPROM_VPD_PRIMARY_INFO</id> </attribute> <!--fsp requirement--> @@ -2784,6 +3205,7 @@ </attribute> </targetType> + <!-- Three NPUs per proc --> <targetType> <id>unit-npu-axone</id> <parent>unit-npu-power9</parent> @@ -2791,8 +3213,26 @@ <id>MODEL</id> <default>AXONE</default> </attribute> + <attribute> + <default> + <field> + <id>childRollupAllowed</id> + <value>1</value> + </field> + <field> + <id>deconfigureParent</id> + <value>1</value> + </field> + <field> + <id>valid</id> + <value>1</value> + </field> + </default> + <id>PARENT_DECONFIG_RULES</id> + </attribute> </targetType> + <!-- One NPU per proc --> <targetType> <id>unit-npu-cumulus</id> <parent>unit-npu-power9</parent> @@ -2802,6 +3242,7 @@ </attribute> </targetType> + <!-- One NPU per proc --> <targetType> <id>unit-npu-nimbus</id> <parent>unit-npu-power9</parent> @@ -2811,7 +3252,6 @@ </attribute> </targetType> - <!-- One NPU per proc --> <targetType> <id>unit-npu-power9</id> <parent>unit</parent> @@ -3165,6 +3605,12 @@ <default>AXONE</default> <id>MODEL</id> </attribute> + <attribute> + <id>OMI_INBAND_BAR_BASE_ADDR_OFFSET</id> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + </attribute> </targetType> <!-- OMI (Special has two parents) diff --git a/src/usr/targeting/common/xmltohb/target_types_hb.xml b/src/usr/targeting/common/xmltohb/target_types_hb.xml index ff955cf28..e2be5b6f8 100644 --- a/src/usr/targeting/common/xmltohb/target_types_hb.xml +++ b/src/usr/targeting/common/xmltohb/target_types_hb.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2012,2019 --> +<!-- Contributors Listed Below - COPYRIGHT 2012,2020 --> <!-- [+] Google Inc. --> <!-- [+] International Business Machines Corp. --> <!-- --> @@ -87,10 +87,19 @@ <targetTypeExtension> <id>chip-ocmb</id> <attribute> + <id>HBRT_HYP_ID</id> + </attribute> + <attribute> + <id>IBSCOM_MUTEX</id> + </attribute> + <attribute> <default>0</default> <id>MMIO_VM_ADDR</id> </attribute> <attribute> + <id>OCMB_COUNTER_HB</id> + </attribute> + <attribute> <id>VPD_SWITCHES</id> </attribute> </targetTypeExtension> @@ -107,6 +116,9 @@ <id>FSI_SCOM_MUTEX</id> </attribute> <attribute> + <id>GPIO_INFO_PHYS_PRES</id> + </attribute> + <attribute> <id>HBRT_HYP_ID</id> </attribute> <attribute> @@ -240,6 +252,12 @@ <id>DIMM_SPD_BYTE_SIZE</id> </attribute> <attribute> + <id>NVDIMM_READING_PAGE4</id> + </attribute> + <attribute> + <id>NVDIMM_READING_VENDOR_LOG</id> + </attribute> + <attribute> <id>PART_NUMBER</id> </attribute> <attribute> @@ -251,6 +269,14 @@ </targetTypeExtension> <targetTypeExtension> + <id>pmic</id> + <attribute> + <id>DYNAMIC_I2C_DEVICE_ADDRESS</id> + <default>0</default> + </attribute> + </targetTypeExtension> + + <targetTypeExtension> <id>sys-sys-power9</id> <attribute> <id>ALLOW_ATTR_OVERRIDES_IN_SECURE_MODE</id> @@ -274,9 +300,19 @@ <id>FORCE_PRE_PAYLOAD_DRTM</id> </attribute> <attribute> + <id>FORCE_SBE_UPDATE</id> + </attribute> + <!-- Need to add this explicitly to handle the Axone case --> + <attribute> + <id>FREQ_MCA_MHZ</id> + </attribute> + <attribute> <id>HB_EXISTING_IMAGE</id> </attribute> <attribute> + <id>HB_MUTEX_SERIALIZE_TEST_LOCK</id> + </attribute> + <attribute> <id>HB_MUTEX_TEST_LOCK</id> </attribute> <attribute> @@ -311,7 +347,7 @@ </attribute> <attribute> <id>OVERRIDES_ATTEMPTED_FLAG</id> - </attribute> + </attribute> <attribute> <id>PDA_CAPTURED_THREAD_REG_ARRAY_ADDR</id> </attribute> @@ -324,6 +360,18 @@ <attribute> <id>PDA_THREAD_REG_STATE_ENTRY_FORMAT</id> </attribute> + <attribute> + <id>PHYS_PRES_ASSERTED</id> + </attribute> + <attribute> + <id>PHYS_PRES_FAKE_ASSERT</id> + </attribute> + <attribute> + <id>PHYS_PRES_REQUEST_OPEN_WINDOW</id> + </attribute> + <attribute> + <id>SBE_ARCH_DUMP_ADDR</id> + </attribute> </targetTypeExtension> <targetTypeExtension> diff --git a/src/usr/targeting/common/xmltohb/xmltohb.pl b/src/usr/targeting/common/xmltohb/xmltohb.pl index b3370906e..339c26960 100755 --- a/src/usr/targeting/common/xmltohb/xmltohb.pl +++ b/src/usr/targeting/common/xmltohb/xmltohb.pl @@ -8,6 +8,7 @@ # # Contributors Listed Below - COPYRIGHT 2012,2019 # [+] International Business Machines Corp. +# [+] YADRO # # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -26,10 +27,7 @@ # # Purpose: -# Author: Nick Bofferding -# Last Updated: 09/09/2011 -# -# Version: 1.0 +# Process the attribute xml files, generate code, create binaries, etc # # Change Log ********************************************************** # @@ -363,17 +361,17 @@ if( !($cfgSrcOutputDir =~ "none") ) writeFapi2PlatAttrMacrosHeaderFileFooter ($fapi2PlatAttrMacrosHeaderFile); close $fapi2PlatAttrMacrosHeaderFile; - open(ATTR_ATTRERRL_C_FILE,">$cfgSrcOutputDir"."errludattribute.C") + open(ATTR_ATTRERRL_C_FILE,">$cfgSrcOutputDir"."errludattribute_gen.C") or croak ("Attribute errlog C file: \"$cfgSrcOutputDir" - . "errludattribute.C\" could not be opened."); + . "errludattribute_gen.C\" could not be opened."); my $attrErrlCFile = *ATTR_ATTRERRL_C_FILE; writeAttrErrlCFile($attributes,$attrErrlCFile); close $attrErrlCFile; mkdir("$cfgSrcOutputDir/errl"); - open(ATTR_ATTRERRL_H_FILE,">$cfgSrcOutputDir"."errl/errludattribute.H") + open(ATTR_ATTRERRL_H_FILE,">$cfgSrcOutputDir"."errl/errludattributeP_gen.H") or croak ("Attribute errlog H file: \"$cfgSrcOutputDir" - . "errl/errludattribute.H\" could not be opened."); + . "errl/errludattributeP_gen.H\" could not be opened."); my $attrErrlHFile = *ATTR_ATTRERRL_H_FILE; writeAttrErrlHFile($attributes,$attrErrlHFile); close $attrErrlHFile; @@ -1018,32 +1016,30 @@ sub validateAttributes { my($attributes) = @_; my %elements = ( ); - $elements{"id"} = { required => 1, isscalar => 1}; - $elements{"description"} = { required => 1, isscalar => 1}; - $elements{"persistency"} = { required => 1, isscalar => 1}; - $elements{"fspOnly"} = { required => 0, isscalar => 0}; - $elements{"hbOnly"} = { required => 0, isscalar => 0}; - $elements{"readable"} = { required => 0, isscalar => 0}; - $elements{"simpleType"} = { required => 0, isscalar => 0}; - $elements{"complexType"} = { required => 0, isscalar => 0}; - $elements{"nativeType"} = { required => 0, isscalar => 0}; - $elements{"writeable"} = { required => 0, isscalar => 0}; - $elements{"hasStringConversion"} - = { required => 0, isscalar => 0}; - $elements{"hwpfToHbAttrMap"} - = { required => 0, isscalar => 0}; - $elements{"display-name"} = { required => 0, isscalar => 1}; - $elements{"virtual"} = { required => 0, isscalar => 0}; - $elements{"tempAttribute"} = { required => 0, isscalar => 0}; - $elements{"serverwizReadonly"} = { required => 0, isscalar => 0}; - $elements{"serverwizShow"} = { required => 0, isscalar => 1}; - $elements{"global"} = { required => 0, isscalar => 0}; - $elements{"range"} = { required => 0, isscalar => 0}; - $elements{"ignoreEkb"} = { required => 0, isscalar => 0}; - $elements{"mrwRequired"} = { required => 0, isscalar => 0}; + $elements{"id"} = { required => 1, isscalar => 1}; + $elements{"description"} = { required => 1, isscalar => 1}; + $elements{"persistency"} = { required => 1, isscalar => 1}; + $elements{"fspOnly"} = { required => 0, isscalar => 0}; + $elements{"hbOnly"} = { required => 0, isscalar => 0}; + $elements{"readable"} = { required => 0, isscalar => 0}; + $elements{"simpleType"} = { required => 0, isscalar => 0}; + $elements{"complexType"} = { required => 0, isscalar => 0}; + $elements{"nativeType"} = { required => 0, isscalar => 0}; + $elements{"writeable"} = { required => 0, isscalar => 0}; + $elements{"hasStringConversion"} = { required => 0, isscalar => 0}; + $elements{"hwpfToHbAttrMap"} = { required => 0, isscalar => 0}; + $elements{"display-name"} = { required => 0, isscalar => 1}; + $elements{"virtual"} = { required => 0, isscalar => 0}; + $elements{"tempAttribute"} = { required => 0, isscalar => 0}; + $elements{"serverwizReadonly"} = { required => 0, isscalar => 0}; + $elements{"serverwizShow"} = { required => 0, isscalar => 1}; + $elements{"global"} = { required => 0, isscalar => 0}; + $elements{"range"} = { required => 0, isscalar => 0}; + $elements{"ignoreEkb"} = { required => 0, isscalar => 0}; + $elements{"mrwRequired"} = { required => 0, isscalar => 0}; # do NOT export attribute & its associated enum to serverwiz - $elements{"no_export"} = { required => 0, isscalar => 0}; + $elements{"no_export"} = { required => 0, isscalar => 0}; foreach my $attribute (@{$attributes->{attribute}}) { @@ -2438,6 +2434,9 @@ print $outFile <<VERBATIM; // STD #include <stdint.h> #include <stdlib.h> +#ifdef __HOSTBOOT_MODULE +#include <array> +#endif VERBATIM foreach my $attribute (@{$attributes->{attribute}}) @@ -2541,12 +2540,11 @@ sub writeTraitFileTraits { $traits .= " fspAccessible,"; } - chop($traits); - # Build value type my $type = ""; my $dimensions = ""; + my $stdArrAddOn = ""; # Only used if attr holds array type if(exists $attribute->{simpleType}) { my $simpleType = $attribute->{simpleType}; @@ -2569,11 +2567,26 @@ sub writeTraitFileTraits { if( (exists $simpleType->{array}) && ($simpleTypeProperties->{$typeName}{supportsArray}) ) { - my @bounds = split(/,/,$simpleType->{array}); - foreach my $bound (@bounds) + + my @revBounds = reverse split(/,/,$simpleType->{array}); + + for my $idx (0 .. $#revBounds) { - $dimensions .= "[$bound]"; + $dimensions = "[@revBounds[$idx]]$dimensions"; + + # Creating std::array, even if multi-dimensional + if ($idx == 0) + { + $stdArrAddOn = "std::array<$type, " + ."@revBounds[$idx]>"; + } + else + { + $stdArrAddOn = "std::array<$stdArrAddOn, " + ."@revBounds[$idx]>"; + } } + } if(exists $simpleType->{string}) @@ -2611,6 +2624,8 @@ sub writeTraitFileTraits { . "$attribute->{id}."); } + chop($traits); + # if it already exists skip it if( !exists($attrValHash{$attribute->{id}})) { @@ -2625,6 +2640,13 @@ sub writeTraitFileTraits { print $outFile " public:\n"; print $outFile " enum {",$traits," };\n"; print $outFile " typedef ", $type, " Type$dimensions;\n"; + if ($stdArrAddOn ne "") + { + # Append typedef for std::array if attr holds array value + print $outFile "#ifdef __HOSTBOOT_MODULE\n"; + print $outFile " typedef $stdArrAddOn TypeStdArr;\n"; + print $outFile "#endif\n"; + } print $outFile "};\n\n"; $typedefs .= "// Type aliases and/or sizes for ATTR_" @@ -2637,6 +2659,14 @@ sub writeTraitFileTraits { $typedefs .= "typedef " . $type . " ATTR_" . "$attribute->{id}" . "_type" . $dimensions . ";\n"; + if ($stdArrAddOn ne "") + { + $typedefs .= "#ifdef __HOSTBOOT_MODULE\n"; + $typedefs .= "typedef $stdArrAddOn " + ."ATTR_$attribute->{id}_typeStdArr;\n"; + $typedefs .= "#endif\n"; + } + # If a string, append max # of characters for the string if( (exists $attribute->{simpleType}) && (exists $attribute->{simpleType}->{string})) @@ -2718,14 +2748,6 @@ VERBATIM sub writeAttrErrlCFile { my($attributes,$outFile) = @_; - #First setup the includes and function definition - print $outFile "#include <stdint.h>\n"; - print $outFile "#include <stdio.h>\n"; - print $outFile "#include <string.h>\n"; - print $outFile "#include <errl/errludattribute.H>\n"; - print $outFile "#include <errl/errlreasoncodes.H>\n"; - print $outFile "#include <targeting/common/targetservice.H>\n"; - print $outFile "#include <targeting/common/trace.H>\n"; print $outFile "\n"; print $outFile "namespace ERRORLOG\n"; print $outFile "{\n"; @@ -2742,52 +2764,38 @@ sub writeAttrErrlCFile { print $outFile "\n"; print $outFile " switch (i_attr) {\n"; - print $outFile " case (ATTR_SERIAL_NUMBER): { //simpleType:uint, :int...\n"; - print $outFile " //TRACDCOMP( g_trac_errl, \"ErrlUserDetailsAttribute: SERIAL_NUMBER entry\");\n"; - print $outFile " AttributeTraits<ATTR_SERIAL_NUMBER>::Type tmp;\n"; - print $outFile " if( iv_pTarget->tryGetAttr<ATTR_SERIAL_NUMBER>(tmp) ) {\n"; - print $outFile " tmpBuffer = new char[sizeof(tmp)];\n"; - print $outFile " memcpy(tmpBuffer, &tmp, sizeof(tmp));\n"; - print $outFile " attrSize = sizeof(tmp);\n"; - print $outFile " }\n"; - print $outFile " break;\n"; - print $outFile " }\n"; - print $outFile " case (ATTR_PART_NUMBER): { //simpleType:uint, :int...\n"; - print $outFile " //TRACDCOMP( g_trac_errl, \"ErrlUserDetailsAttribute: PART_NUMBER entry\");\n"; - print $outFile " AttributeTraits<ATTR_PART_NUMBER>::Type tmp;\n"; - print $outFile " if( iv_pTarget->tryGetAttr<ATTR_PART_NUMBER>(tmp) ) {\n"; - print $outFile " tmpBuffer = new char[sizeof(tmp)];\n"; - print $outFile " memcpy(tmpBuffer, &tmp, sizeof(tmp));\n"; - print $outFile " attrSize = sizeof(tmp);\n"; - print $outFile " }\n"; - print $outFile " break;\n"; - print $outFile " }\n"; - print $outFile " case (ATTR_PEC_PCIE_HX_KEYWORD_DATA): { //simpleType:uint, :int...\n"; - print $outFile " //TRACDCOMP( g_trac_errl, \"ErrlUserDetailsAttribute: PEC_PCIE_HX_KEYWORD_DATA entry\");\n"; - print $outFile " AttributeTraits<ATTR_PEC_PCIE_HX_KEYWORD_DATA>::Type tmp;\n"; - print $outFile " if( iv_pTarget->tryGetAttr<ATTR_PEC_PCIE_HX_KEYWORD_DATA>(tmp) ) {\n"; - print $outFile " tmpBuffer = new char[sizeof(tmp)];\n"; - print $outFile " memcpy(tmpBuffer, &tmp, sizeof(tmp));\n"; - print $outFile " attrSize = sizeof(tmp);\n"; - print $outFile " }\n"; - print $outFile " break;\n"; - print $outFile " }\n"; - print $outFile "#if 0 //\@fixme-RTC:152874\n"; + # List of attributes we want to explicitly support + my @allowed_attributes = ( + "SERIAL_NUMBER", + "PART_NUMBER", + "PEC_PCIE_HX_KEYWORD_DATA", + "ECID", + "HUID", + ); - # loop through every attribute to make the swith/case + # loop through every attribute to make the switch/case foreach my $attribute (@{$attributes->{attribute}}) { + my $skippedattr = 0; + if( grep { $_ eq $attribute->{id} } @allowed_attributes ) + { + print "Allowing $attribute->{id}\n"; + } + else + { + print $outFile "#if 0 //\@fixme-RTC:152874\n"; + $skippedattr = 1; + } + # things we'll skip: if(!(exists $attribute->{readable}) || # write-only attributes - !(exists $attribute->{writeable}) || # read-only attributes (exists $attribute->{simpleType} && ( (exists $attribute->{simpleType}->{hbmutex}) || (exists $attribute->{simpleType}->{hbrecrusivemutex}) || (exists $attribute->{simpleType}->{fspmutex}))) # mutex attributes ) { print $outFile " case (ATTR_",$attribute->{id},"): { break; }\n"; - next; } # any complicated types just get dumped as raw hex binary elsif(exists $attribute->{complexType}) { @@ -2872,6 +2880,11 @@ sub writeAttrErrlCFile { print $outFile " break;\n"; print $outFile " }\n"; } + + if( $skippedattr ) + { + print $outFile "#endif //\@fixme-RTC:152874\n"; + } } print $outFile " default: { //Shouldn't be anything here!!\n"; @@ -2879,7 +2892,6 @@ sub writeAttrErrlCFile { print $outFile " break;\n"; print $outFile " }\n"; - print $outFile "#endif //\@fixme-RTC:152874\n"; print $outFile " } //switch\n"; print $outFile "\n"; @@ -2898,45 +2910,6 @@ sub writeAttrErrlCFile { print $outFile "}\n"; print $outFile "\n"; - # build constructor that dumps 1 attribute - print $outFile "\n"; - print $outFile "//------------------------------------------------------------------------------\n"; - print $outFile "ErrlUserDetailsAttribute::ErrlUserDetailsAttribute(\n"; - print $outFile " const Target * i_pTarget, uint32_t i_attr)\n"; - print $outFile " : iv_pTarget(i_pTarget), iv_dataSize(0)\n"; - print $outFile "{\n"; - print $outFile " // Set up ErrlUserDetails instance variables\n"; - print $outFile " iv_CompId = ERRL_COMP_ID;\n"; - print $outFile " iv_Version = 1;\n"; - print $outFile " iv_SubSection = ERRL_UDT_ATTRIBUTE;\n"; - print $outFile " // override the default of false\n"; - print $outFile " iv_merge = true;\n"; - print $outFile "\n"; - print $outFile " // first, write out the HUID\n"; - print $outFile " addData(ATTR_HUID);\n"; - print $outFile " if (i_attr != ATTR_HUID) {\n"; - print $outFile " addData(i_attr);\n"; - print $outFile " }\n"; - print $outFile "}\n"; - print $outFile "\n"; - - # build constructor that dumps all attributes - print $outFile "//------------------------------------------------------------------------------\n"; - print $outFile "ErrlUserDetailsAttribute::ErrlUserDetailsAttribute(\n"; - print $outFile " const Target * i_pTarget)\n"; - print $outFile " : iv_pTarget(i_pTarget), iv_dataSize(0)\n"; - print $outFile "{\n"; - print $outFile " // Set up ErrlUserDetails instance variables\n"; - print $outFile " iv_CompId = ERRL_COMP_ID;\n"; - print $outFile " iv_Version = 1;\n"; - print $outFile " iv_SubSection = ERRL_UDT_ATTRIBUTE;\n"; - print $outFile " // override the default of false\n"; - print $outFile " iv_merge = true;\n"; - print $outFile "\n"; - print $outFile " dumpAll();\n"; - print $outFile "}\n"; - print $outFile "\n"; - # build internal function that dumps all attributes print $outFile "//------------------------------------------------------------------------------\n"; print $outFile "void ErrlUserDetailsAttribute::dumpAll()\n"; @@ -2967,10 +2940,7 @@ sub writeAttrErrlCFile { print $outFile "\n"; - print $outFile "//------------------------------------------------------------------------------\n"; - print $outFile "ErrlUserDetailsAttribute::~ErrlUserDetailsAttribute()\n"; - print $outFile "{ }\n"; - print $outFile "} // namespace\n"; + print $outFile "} // namespace\n\n"; } # sub writeAttrErrlCFile @@ -2980,44 +2950,7 @@ sub writeAttrErrlCFile { sub writeAttrErrlHFile { my($attributes,$outFile) = @_; - #First setup the includes and function definition - print $outFile "\n"; - print $outFile "#ifndef ERRL_UDATTRIBUTE_H\n"; - print $outFile "#define ERRL_UDATTRIBUTE_H\n"; - print $outFile "\n"; - print $outFile "#if !defined(PARSER) && !defined(LOGPARSER)\n"; - print $outFile "\n"; - print $outFile "#include <errl/errluserdetails.H>\n"; - print $outFile "\n"; - print $outFile "namespace TARGETING // Forward reference\n"; - print $outFile "{ class Target; }\n"; - print $outFile "\n"; - print $outFile "namespace ERRORLOG\n"; - print $outFile "{\n"; - print $outFile "class ErrlUserDetailsAttribute : public ErrlUserDetails {\n"; - print $outFile "public:\n"; - print $outFile "\n"; - print $outFile " ErrlUserDetailsAttribute(const TARGETING::Target * i_pTarget, uint32_t i_attr);\n"; - print $outFile " ErrlUserDetailsAttribute(const TARGETING::Target * i_pTarget);\n"; - print $outFile " void addData(uint32_t i_attr);\n"; - print $outFile " virtual ~ErrlUserDetailsAttribute();\n"; - print $outFile "\n"; - print $outFile "private:\n"; - print $outFile "\n"; - print $outFile " // Disabled\n"; - print $outFile " ErrlUserDetailsAttribute(const ErrlUserDetailsAttribute &);\n"; - print $outFile " ErrlUserDetailsAttribute & operator=(const ErrlUserDetailsAttribute &);\n"; - print $outFile "\n"; - print $outFile " // internal function\n"; - print $outFile " void dumpAll();\n"; - print $outFile "\n"; - print $outFile " const TARGETING::Target * iv_pTarget;\n"; - print $outFile " uint32_t iv_dataSize;\n"; - print $outFile "};\n"; - print $outFile "}\n"; - print $outFile "#else // if LOGPARSER defined\n"; - print $outFile "\n"; - print $outFile "#include \"errluserdetails.H\"\n"; + # Included by errludattributeP.H print $outFile "\n"; print $outFile "namespace ERRORLOG\n"; print $outFile "{\n"; @@ -3048,8 +2981,9 @@ sub writeAttrErrlHFile { print $outFile " for (; (l_ptr + sizeof(uint32_t)) <= ((uint8_t*)i_pBuffer + i_buflen); )\n"; print $outFile " {\n"; print $outFile " // first 4 bytes is the attr enum\n"; - print $outFile " uint32_t attrEnum = ntohl(*(uint32_t *)l_ptr);\n"; + print $outFile " uint32_t attrEnum = ntohl(UINT32_FROM_PTR(l_ptr));\n"; print $outFile " l_ptr += sizeof(attrEnum);\n"; + print $outFile " char* tmplabel = NULL;\n"; print $outFile "\n"; print $outFile " switch (attrEnum) {\n"; @@ -3179,21 +3113,21 @@ sub writeAttrErrlHFile { elsif (exists $attribute->{simpleType}->{uint16_t}) { print $outFile " l_traceEntry.resize(10+offset + $total_count * 7);\n"; print $outFile " for (uint32_t i = 0;i<$total_count;i++) {\n"; - print $outFile " sprintf(&(l_traceEntry[offset+i*7]), \"0x%.4X \", ntohs(*(((uint16_t *)l_ptr)+i)));\n"; + print $outFile " sprintf(&(l_traceEntry[offset+i*7]), \"0x%.4X \", ntohs(UINT16_FROM_PTR(reinterpret_cast<const uint16_t*>(l_ptr) + i)));\n"; print $outFile " }\n"; print $outFile " l_ptr += $total_count * sizeof(uint16_t);\n"; } elsif (exists $attribute->{simpleType}->{uint32_t}) { print $outFile " l_traceEntry.resize(10+offset + $total_count * 11);\n"; print $outFile " for (uint32_t i = 0;i<$total_count;i++) {\n"; - print $outFile " sprintf(&(l_traceEntry[offset+i*11]), \"0x%.8X \", ntohl(*(((uint32_t *)l_ptr)+i)));\n"; + print $outFile " sprintf(&(l_traceEntry[offset+i*11]), \"0x%.8X \", ntohl(UINT32_FROM_PTR(reinterpret_cast<const uint32_t*>(l_ptr)+i)));\n"; print $outFile " }\n"; print $outFile " l_ptr += $total_count * sizeof(uint32_t);\n"; } elsif (exists $attribute->{simpleType}->{uint64_t}) { print $outFile " l_traceEntry.resize(10+offset + $total_count * 19);\n"; print $outFile " for (uint32_t i = 0;i<$total_count;i++) {\n"; - print $outFile " sprintf(&(l_traceEntry[offset+i*19]), \"0x%.16llX \", ntohll(*(((uint64_t *)l_ptr)+i)));\n"; + print $outFile " sprintf(&(l_traceEntry[offset+i*19]), \"0x%.16llX \", ntohll(UINT64_FROM_PTR(reinterpret_cast<const uint64_t*>(l_ptr)+i)));\n"; print $outFile " }\n"; print $outFile " l_ptr += $total_count * sizeof(uint64_t);\n"; } @@ -3207,21 +3141,21 @@ sub writeAttrErrlHFile { elsif (exists $attribute->{simpleType}->{int16_t}) { print $outFile " l_traceEntry.resize(10+offset + $total_count * 7);\n"; print $outFile " for (uint32_t i = 0;i<$total_count;i++) {\n"; - print $outFile " sprintf(&(l_traceEntry[offset+i*7]), \"0x%.4X \", ntohs(*(((int16_t *)l_ptr)+i)));\n"; + print $outFile " sprintf(&(l_traceEntry[offset+i*7]), \"0x%.4X \", ntohs(INT16_FROM_PTR(reinterpret_cast<const int16_t*>(l_ptr)+i)));\n"; print $outFile " }\n"; print $outFile " l_ptr += $total_count * sizeof(int16_t);\n"; } elsif (exists $attribute->{simpleType}->{int32_t}) { print $outFile " l_traceEntry.resize(10+offset + $total_count * 11);\n"; print $outFile " for (uint32_t i = 0;i<$total_count;i++) {\n"; - print $outFile " sprintf(&(l_traceEntry[offset+i*11]), \"0x%.8X \", ntohl(*(((int32_t *)l_ptr)+i)));\n"; + print $outFile " sprintf(&(l_traceEntry[offset+i*11]), \"0x%.8X \", ntohl(INT32_FROM_PTR(reinterpret_cast<const int32_t*>(l_ptr)+i)));\n"; print $outFile " }\n"; print $outFile " l_ptr += $total_count * sizeof(int32_t);\n"; } elsif (exists $attribute->{simpleType}->{int64_t}) { print $outFile " l_traceEntry.resize(10+offset + $total_count * 19);\n"; print $outFile " for (uint32_t i = 0;i<$total_count;i++) {\n"; - print $outFile " sprintf(&(l_traceEntry[offset+i*19]), \"0x%.16llX \", ntohll(*(((int64_t *)l_ptr)+i)));\n"; + print $outFile " sprintf(&(l_traceEntry[offset+i*19]), \"0x%.16llX \", ntohll(INT64_FROM_PTR(reinterpret_cast<const int64_t*>(l_ptr)+i)));\n"; print $outFile " }\n"; print $outFile " l_ptr += $total_count * sizeof(int64_t);\n"; } @@ -3296,7 +3230,9 @@ sub writeAttrErrlHFile { print $outFile " }\n"; } print $outFile " default: {\n"; - print $outFile " pLabel = \"unknown Attribute\";\n"; + print $outFile " tmplabel = new char[30];\n"; + print $outFile " sprintf( tmplabel, \"Unknown [0x%x]\", attrEnum );\n"; + print $outFile " pLabel = tmplabel;\n"; print $outFile " break;\n"; print $outFile " }\n"; print $outFile " } // switch\n"; @@ -3305,6 +3241,7 @@ sub writeAttrErrlHFile { print $outFile " if (pLabel != NULL) {\n"; print $outFile " i_parser.PrintString(pLabel, &(l_traceEntry[0]));\n"; print $outFile " }\n"; + print $outFile " if( tmplabel != NULL ) { delete[] tmplabel; }\n"; print $outFile " } // for\n"; print $outFile " } // parse\n\n"; print $outFile "private:\n"; @@ -3313,9 +3250,7 @@ sub writeAttrErrlHFile { print $outFile "ErrlUserDetailsParserAttribute(const ErrlUserDetailsParserAttribute &);\n"; print $outFile "ErrlUserDetailsParserAttribute & operator=(const ErrlUserDetailsParserAttribute &);\n"; print $outFile "};\n"; - print $outFile "} // namespace\n"; - print $outFile "#endif\n"; - print $outFile "#endif\n"; + print $outFile "} // namespace\n\n"; } # sub writeAttrErrlHFile ###### @@ -4016,11 +3951,11 @@ sub writeTargetErrlHFile { print $outFile " // first 4 are always the same\n"; print $outFile " if ((l_ptr32 + 4) <= (uint32_t *)((uint8_t*)i_pBuffer + i_buflen)) {\n"; - print $outFile " i_parser.PrintNumber( l_label, \"HUID = 0x%08X\", ntohl(*l_ptr32) );\n"; + print $outFile " i_parser.PrintNumber( l_label, \"HUID = 0x%08X\", ntohl(UINT32_FROM_PTR(l_ptr32)) );\n"; print $outFile " l_ptr32++;\n"; # find CLASS - print $outFile " switch (ntohl(*l_ptr32)) { // CLASS\n"; + print $outFile " switch (ntohl(UINT32_FROM_PTR(l_ptr32))) { // CLASS\n"; foreach my $enumerationType (@{$attributes->{enumerationType}}) { if( $enumerationType->{id} eq "CLASS" ) { @@ -4039,7 +3974,7 @@ sub writeTargetErrlHFile { print $outFile " l_ptr32++;\n"; # find TYPE - print $outFile " switch (ntohl(*l_ptr32)) { // TYPE\n"; + print $outFile " switch (ntohl(UINT32_FROM_PTR(l_ptr32))) { // TYPE\n"; foreach my $enumerationType (@{$attributes->{enumerationType}}) { if( $enumerationType->{id} eq "TYPE" ) { @@ -4058,7 +3993,7 @@ sub writeTargetErrlHFile { print $outFile " l_ptr32++;\n"; # find MODEL - print $outFile " switch (ntohl(*l_ptr32)) { // MODEL\n"; + print $outFile " switch (ntohl(UINT32_FROM_PTR(l_ptr32))) { // MODEL\n"; foreach my $enumerationType (@{$attributes->{enumerationType}}) { if( $enumerationType->{id} eq "MODEL" ) { @@ -4096,7 +4031,7 @@ sub writeTargetErrlHFile { } } - print $outFile " uint32_t l_pathType = ntohl(*l_ptr32);\n"; + print $outFile " uint32_t l_pathType = ntohl(UINT32_FROM_PTR(l_ptr32));\n"; print $outFile " if ((l_pathType == $attrPhysPath) || // ATTR_PHYS_PATH\n"; print $outFile " (l_pathType == $attrAffinityPath)) // ATTR_AFFINITY_PATH\n"; print $outFile " {\n"; diff --git a/src/usr/targeting/hostboot_common.mk b/src/usr/targeting/hostboot_common.mk index 7be1449d7..4d10df929 100644 --- a/src/usr/targeting/hostboot_common.mk +++ b/src/usr/targeting/hostboot_common.mk @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2013,2016 +# Contributors Listed Below - COPYRIGHT 2013,2020 # [+] International Business Machines Corp. # # @@ -30,6 +30,9 @@ COMMON_TARGETING_MAKEFILE = ${COMMON_TARGETING_REL_PATH}/common.mk include ${COMMON_TARGETING_MAKEFILE} +# TODO: 248022 move this to common.mk when CMVC files are updated for fips +TARGET_OBJS += hbrt_target.o + VPATH += ${TARGETING_REL_PATH}/adapters VPATH += ${COMMON_TARGETING_REL_PATH} VPATH += ${addprefix ${COMMON_TARGETING_REL_PATH}/, ${COMMON_TARGETING_SUBDIRS}} diff --git a/src/usr/targeting/makefile b/src/usr/targeting/makefile index 531c3fb7f..af1978f64 100644 --- a/src/usr/targeting/makefile +++ b/src/usr/targeting/makefile @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2011,2018 +# Contributors Listed Below - COPYRIGHT 2011,2020 # [+] International Business Machines Corp. # # @@ -54,7 +54,6 @@ HOSTBOOT_SPECIFIC_OBJS += ${ATTR_RP_OBJS} HOSTBOOT_SPECIFIC_OBJS += ${DEBUG_OBJS} HOSTBOOT_SPECIFIC_OBJS += ${HOSTBOOT_RT_IPL_COMMON_OBJS} HOSTBOOT_SPECIFIC_OBJS += namedtarget.o -HOSTBOOT_SPECIFIC_OBJS += errludattribute.o HOSTBOOT_SPECIFIC_OBJS += attrcheck_errl.o OBJS += persistrwattrcheck.o diff --git a/src/usr/targeting/runtime/attrPlatOverride_rt.C b/src/usr/targeting/runtime/attrPlatOverride_rt.C index b379313d9..3c805381c 100644 --- a/src/usr/targeting/runtime/attrPlatOverride_rt.C +++ b/src/usr/targeting/runtime/attrPlatOverride_rt.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014,2018 */ +/* Contributors Listed Below - COPYRIGHT 2014,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -24,14 +24,13 @@ /* IBM_PROLOG_END_TAG */ #include <runtime/interface.h> -#include <runtime/rt_targeting.H> +#include <targeting/runtime/rt_targeting.H> #include <targeting/common/commontargeting.H> #include <targeting/attrPlatOverride.H> #include <fapi2/plat_attr_override_sync.H> #include <targeting/common/trace.H> #include <errl/errlmanager.H> #include <initservice/initserviceif.H> -#include <config.h> #include <secureboot/service.H> #include <targeting/common/targreasoncodes.H> #include <devicefw/userif.H> diff --git a/src/usr/targeting/runtime/makefile b/src/usr/targeting/runtime/makefile index ffb2e8a14..eb1dd366e 100644 --- a/src/usr/targeting/runtime/makefile +++ b/src/usr/targeting/runtime/makefile @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2013,2018 +# Contributors Listed Below - COPYRIGHT 2013,2020 # [+] International Business Machines Corp. # # @@ -38,7 +38,6 @@ HOSTBOOT_RUNTIME_SPECIFIC_OBJS += start_rt.o HOSTBOOT_RUNTIME_SPECIFIC_OBJS += targplatutil.o HOSTBOOT_RUNTIME_SPECIFIC_OBJS += rt_targeting.o HOSTBOOT_RUNTIME_SPECIFIC_OBJS += attrPlatOverride_rt.o -HOSTBOOT_RUNTIME_SPECIFIC_OBJS += errludattribute.o HOSTBOOT_RUNTIME_SPECIFIC_OBJS += attributestrings.o HOSTBOOT_RUNTIME_SPECIFIC_OBJS += attrsync.o HOSTBOOT_RUNTIME_SPECIFIC_OBJS += rt_startup.o diff --git a/src/usr/targeting/runtime/rt_startup.C b/src/usr/targeting/runtime/rt_startup.C index 578750006..ed190f196 100644 --- a/src/usr/targeting/runtime/rt_startup.C +++ b/src/usr/targeting/runtime/rt_startup.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -#include <runtime/rt_targeting.H> +#include <targeting/runtime/rt_targeting.H> #include <runtime/interface.h> #include <targeting/common/target.H> #include <targeting/common/targetservice.H> diff --git a/src/usr/targeting/runtime/rt_targeting.C b/src/usr/targeting/runtime/rt_targeting.C index 581386985..28c1fdf7d 100644 --- a/src/usr/targeting/runtime/rt_targeting.C +++ b/src/usr/targeting/runtime/rt_targeting.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014,2018 */ +/* Contributors Listed Below - COPYRIGHT 2014,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -39,7 +39,7 @@ #include <targeting/attrrp.H> #include <arch/pirformat.H> #include <runtime/customize_attrs_for_payload.H> -#include <runtime/rt_targeting.H> +#include <targeting/runtime/rt_targeting.H> #include <runtime/interface.h> #include <map> #include <util/memoize.H> @@ -54,61 +54,6 @@ using namespace TARGETING; namespace RT_TARG { -errlHndl_t getRtTarget( - const TARGETING::Target* i_pTarget, - rtChipId_t& o_rtTargetId) -{ - errlHndl_t pError = NULL; - - do - { - if(i_pTarget == TARGETING::MASTER_PROCESSOR_CHIP_TARGET_SENTINEL) - { - TARGETING::Target* masterProcChip = NULL; - TARGETING::targetService(). - masterProcChipTargetHandle(masterProcChip); - i_pTarget = masterProcChip; - } - - auto hbrtHypId = RUNTIME::HBRT_HYP_ID_UNKNOWN; - if( (!i_pTarget->tryGetAttr<TARGETING::ATTR_HBRT_HYP_ID>(hbrtHypId)) - || (hbrtHypId == RUNTIME::HBRT_HYP_ID_UNKNOWN)) - { - auto huid = get_huid(i_pTarget); - auto targetingTargetType = - i_pTarget->getAttr<TARGETING::ATTR_TYPE>(); - TRACFCOMP(g_trac_targeting, ERR_MRK - "Targeting target type of 0x%08X not supported. " - "HUID: 0x%08X", - targetingTargetType, - huid); - /*@ - * @errortype - * @moduleid TARG_RT_GET_RT_TARGET - * @reasoncode TARG_RT_TARGET_TYPE_NOT_SUPPORTED - * @userdata1 Target's HUID - * @userdata2 target's targeting type - * @devdesc Targeting target's type not supported by runtime - * code - */ - pError = new ERRORLOG::ErrlEntry( - ERRORLOG::ERRL_SEV_INFORMATIONAL, - TARGETING::TARG_RT_GET_RT_TARGET, - TARGETING::TARG_RT_TARGET_TYPE_NOT_SUPPORTED, - huid, - targetingTargetType, - true); - - ERRORLOG::ErrlUserDetailsTarget(i_pTarget,"Targeting Target"). - addToLog(pError); - } - - o_rtTargetId = hbrtHypId; - - } while(0); - - return pError; -} /** * @brief API documentation same as for getHbTarget; this just implements the diff --git a/src/usr/targeting/runtime/test/testtargeting.H b/src/usr/targeting/runtime/test/testtargeting.H index fce91f46d..c6c7c0d60 100644 --- a/src/usr/targeting/runtime/test/testtargeting.H +++ b/src/usr/targeting/runtime/test/testtargeting.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2018 */ +/* Contributors Listed Below - COPYRIGHT 2013,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -25,7 +25,7 @@ #include <cxxtest/TestSuite.H> #include <targeting/common/commontargeting.H> #include <runtime/interface.h> -#include <runtime/rt_targeting.H> +#include <targeting/runtime/rt_targeting.H> #include <errl/errlentry.H> #include <errl/errlmanager.H> #include <targeting/common/trace.H> @@ -62,7 +62,7 @@ class TargetingTestSuite : public CxxTest::TestSuite { using namespace TARGETING; errlHndl_t err = NULL; - RT_TARG::rtChipId_t rt_chipid; + TARGETING::rtChipId_t rt_chipid; TARGETING::TargetHandleList allTargets; TARGETING::TargetHandleList targetList; @@ -91,7 +91,7 @@ class TargetingTestSuite : public CxxTest::TestSuite for(TargetHandleList::iterator pTarg = allTargets.begin(); pTarg != allTargets.end(); ++pTarg) { - err = RT_TARG::getRtTarget(*pTarg, rt_chipid); + err = TARGETING::getRtTarget(*pTarg, rt_chipid); if( err ) { TS_FAIL("getRtTarget returned error log"); @@ -629,7 +629,8 @@ class TargetingTestSuite : public CxxTest::TestSuite // Compare the complete set of memory if( memcmp( l_lidStruct, l_rsvdMemPtr, l_attr_size ) ) { - TS_FAIL( "testSaveRestoreAttrs> Data does not match" ); + TS_FAIL( "testSaveRestoreAttrs> Data does not match. Attr size = 0x%lx", + l_attr_size ); } uint64_t l_memcmpOffset = 0; @@ -757,7 +758,6 @@ class TargetingTestSuite : public CxxTest::TestSuite if(l_memcmpFailed != 0) { TS_FAIL("testSaveRestoreAttrs FAILED memcmp %d " - ERR_MRK"testSaveRestoreAttrs FAILED memcmp %d " "(0x%.8x) times out of %d (0x%.8x)", l_memcmpFailed, l_memcmpFailed, diff --git a/src/usr/targeting/targetservicestart.C b/src/usr/targeting/targetservicestart.C index 943b7befc..dea0b9867 100755 --- a/src/usr/targeting/targetservicestart.C +++ b/src/usr/targeting/targetservicestart.C @@ -61,7 +61,6 @@ #include <errl/errlentry.H> #include <errl/errlmanager.H> #include <devicefw/userif.H> -#include <config.h> #include <initservice/initserviceif.H> #include <util/misc.H> #include <util/utilrsvdmem.H> @@ -74,6 +73,7 @@ #include <sbeio/sbeioif.H> #include <sys/mm.h> #include "../runtime/hdatstructs.H" +#include <console/consoleif.H> #ifdef CONFIG_BMC_IPMI #include <ipmi/ipmiif.H> @@ -591,11 +591,18 @@ static void initializeAttributes(TargetService& i_targetService, (HB_INITIATED_PM_RESET_INACTIVE); // clear the NVDIMM arming status so it gets redone when OCC is active - ATTR_NVDIMM_ARMED_type l_nvdimms_armed_state = - l_chip->getAttr<ATTR_NVDIMM_ARMED>(); - // Only force rearming (error setting should persist) - l_nvdimms_armed_state.armed = 0; - l_chip->setAttr<ATTR_NVDIMM_ARMED>(l_nvdimms_armed_state); + TargetHandleList l_nvdimmTargetList = getProcNVDIMMs(l_chip); + for (auto const l_nvdimm : l_nvdimmTargetList) + { + ATTR_NVDIMM_ARMED_type l_armed_state = {}; + l_armed_state = l_nvdimm->getAttr<ATTR_NVDIMM_ARMED>(); + + // Only force rearming (error setting should persist) + l_armed_state.armed = 0; + l_armed_state.occ_active = 0; + + l_nvdimm->setAttr<ATTR_NVDIMM_ARMED>(l_armed_state); + } if (l_chip == l_pMasterProcChip) { @@ -839,6 +846,10 @@ static void adjustMemoryMap( TargetService& i_targetService ) ATTR_LPC_BUS_ADDR_type l_lpcBase = l_pTopLevel->getAttr<ATTR_LPC_BUS_ADDR>(); + // Whether to update the SYS's ATTR_XSCOM_BASE_ADDRESS with a new + // BAR before returning from this function + bool l_updateSysXscomBar = false; + // Loop through all the procs to recompute all the BARs // also find the victim to swap with Target* l_swapVictim = nullptr; @@ -866,11 +877,13 @@ static void adjustMemoryMap( TargetService& i_targetService ) if(l_curXscomBAR & IS_SMF_ADDR_BIT) { l_xscomBAR |= IS_SMF_ADDR_BIT; + l_updateSysXscomBar = true; } TARG_INF( " XSCOM=%.16llX", l_xscomBAR ); l_procChip->setAttr<ATTR_XSCOM_BASE_ADDRESS>(l_xscomBAR); + // See if this chip's space now belongs to the master if( l_xscomBAR == l_curXscomBAR ) { @@ -961,11 +974,65 @@ static void adjustMemoryMap( TargetService& i_targetService ) // Set the rest of the BARs... } - // We must have found a match somewhere - TARG_ASSERT( l_swapVictim != nullptr, "No swap match found" ); + // We should have found a match, but if a processor was swapped + // between different systems we could end up with a non-match + if( l_swapVictim == nullptr ) + { + TARG_INF( "No swap victim was found, forcing master proc to use calculated proc0 values" ); + + // figure out what fabric id we actually booted with + uint8_t l_bootGroup = 0; + uint8_t l_bootChip = 0; + getFabricIdFromAddr( l_curXscomBAR, l_bootGroup, l_bootChip ); + CONSOLE::displayf( NULL, "Module swap detected - handling memory remap from g%d:c%d\n", l_bootGroup, l_bootChip ); + + // now adjust the attributes that our early code is going to consume + // to match the fabric id we're currently using + ATTR_XSCOM_BASE_ADDRESS_type l_xscomBAR = + computeMemoryMapOffset( l_xscomBase, l_bootGroup, l_bootChip ); + l_pMasterProcChip->setAttr<ATTR_XSCOM_BASE_ADDRESS>(l_xscomBAR); + + ATTR_LPC_BUS_ADDR_type l_lpcBAR = + computeMemoryMapOffset( l_lpcBase, l_bootGroup, l_bootChip ); + l_pMasterProcChip->setAttr<ATTR_LPC_BUS_ADDR>(l_lpcBAR); + + ATTR_PSI_BRIDGE_BASE_ADDR_type l_psiBridgeBAR = + computeMemoryMapOffset(MMIO_GROUP0_CHIP0_PSI_BRIDGE_BASE_ADDR, + l_bootGroup, + l_bootChip); + l_pMasterProcChip->setAttr<ATTR_PSI_BRIDGE_BASE_ADDR>(l_psiBridgeBAR); + + ATTR_XIVE_CONTROLLER_BAR_ADDR_type l_xiveCtrlBAR = + computeMemoryMapOffset(MMIO_GROUP0_CHIP0_XIVE_CONTROLLER_BASE_ADDR, + l_bootGroup, + l_bootChip); + l_pMasterProcChip->setAttr<ATTR_XIVE_CONTROLLER_BAR_ADDR>(l_xiveCtrlBAR); + + ATTR_XIVE_THREAD_MGMT1_BAR_ADDR_type l_xiveThreadMgmtBAR = + computeMemoryMapOffset(MMIO_GROUP0_CHIP0_XIVE_THREAD_MGMT1_BASE_ADDR, + l_bootGroup, + l_bootChip); + TARG_INF( " XIVE_THREAD_MGMT1_BAR =%.16llX", l_xiveThreadMgmtBAR ); + l_pMasterProcChip->setAttr<ATTR_XIVE_THREAD_MGMT1_BAR_ADDR>(l_xiveThreadMgmtBAR); + + ATTR_PSI_HB_ESB_ADDR_type l_psiHbEsbBAR = + computeMemoryMapOffset(MMIO_GROUP0_CHIP0_PSI_HB_ESB_BASE_ADDR, + l_bootGroup, + l_bootChip); + l_pMasterProcChip->setAttr<ATTR_PSI_HB_ESB_ADDR>(l_psiHbEsbBAR); + + ATTR_INTP_BASE_ADDR_type l_intpBAR = + computeMemoryMapOffset(MMIO_GROUP0_CHIP0_INTP_BASE_ADDR, + l_bootGroup, + l_bootChip); + l_pMasterProcChip->setAttr<ATTR_INTP_BASE_ADDR>(l_intpBAR); + // Set the attribute to force a SBE update later + l_pTopLevel->setAttr<TARGETING::ATTR_FORCE_SBE_UPDATE> + (TARGETING::FORCE_SBE_UPDATE_BAR_MISMATCH); + } // Now swap the BARs between the master and the victim if needed - if( l_swapVictim != l_pMasterProcChip ) + else if( l_swapVictim != l_pMasterProcChip ) { // Walk through all of the attributes we cached above SWAP_ATTRIBUTE( ATTR_PROC_EFF_FABRIC_GROUP_ID, l_pMasterProcChip, @@ -992,23 +1059,33 @@ static void adjustMemoryMap( TargetService& i_targetService ) // Cross-check that what we ended up setting in the attributes // matches the non-TARGETING values that the XSCOM and LPC - // drivers computed - if( l_pMasterProcChip->getAttr<ATTR_LPC_BUS_ADDR>() - != LPC::get_lpc_bar() ) + // drivers computed (only if we found a swap victim) + if( l_swapVictim && + (l_pMasterProcChip->getAttr<ATTR_LPC_BUS_ADDR>() + != LPC::get_lpc_bar()) ) { TARG_ERR( "LPC attribute=%.16llX, live=%.16llX", l_pMasterProcChip->getAttr<ATTR_LPC_BUS_ADDR>(), LPC::get_lpc_bar() ); TARG_ASSERT( false, "LPC BARs are inconsistent" ); } - if( l_pMasterProcChip->getAttr<ATTR_XSCOM_BASE_ADDRESS>() - != XSCOM::get_master_bar() ) + if( l_swapVictim && + (l_pMasterProcChip->getAttr<ATTR_XSCOM_BASE_ADDRESS>() + != XSCOM::get_master_bar()) ) { TARG_ERR( "XSCOM attribute=%.16llX, live=%.16llX", l_pMasterProcChip->getAttr<ATTR_XSCOM_BASE_ADDRESS>(), XSCOM::get_master_bar() ); TARG_ASSERT( false, "XSCOM BARs are inconsistent" ); } + + if(l_updateSysXscomBar) + { + l_pTopLevel->setAttr<ATTR_XSCOM_BASE_ADDRESS>( + l_xscomBase |= IS_SMF_ADDR_BIT); + TARG_INF("Updating the SYS XSCOM BAR to 0x%.16llX", + l_xscomBase |= IS_SMF_ADDR_BIT); + } } diff --git a/src/usr/targeting/targplatutil.C b/src/usr/targeting/targplatutil.C index c8054cf60..24084d8b1 100644 --- a/src/usr/targeting/targplatutil.C +++ b/src/usr/targeting/targplatutil.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2018 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -42,7 +42,6 @@ #include <targeting/common/predicates/predicates.H> #include <targeting/common/utilFilter.H> #include <errl/errlmanager.H> -#include <config.h> #include <algorithm> namespace TARGETING { diff --git a/src/usr/targeting/test/makefile b/src/usr/targeting/test/makefile index b8d466539..fa6fd0584 100644 --- a/src/usr/targeting/test/makefile +++ b/src/usr/targeting/test/makefile @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2011,2015 +# Contributors Listed Below - COPYRIGHT 2011,2019 # [+] International Business Machines Corp. # # @@ -67,6 +67,8 @@ COMMON_TESTCASE_REL_PATHS = \ TESTS += testtargeting.H TESTS += testattrsync.H TESTS += testattrtank.H +TESTS += testAttribute.H +TESTS += testTargetUtil.H TESTS += ${COMMON_TESTCASE_REL_PATHS} OBJS += attributestrings.o diff --git a/src/usr/targeting/test/testAttribute.H b/src/usr/targeting/test/testAttribute.H new file mode 100644 index 000000000..8014f1397 --- /dev/null +++ b/src/usr/targeting/test/testAttribute.H @@ -0,0 +1,1271 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/targeting/test/testAttribute.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2011,2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +#ifndef __TEST_ATTRIBUTE_H +#define __TEST_ATTRIBUTE_H + +/** + * @file targeting/test/testAttribute.H + * + * @brief Unit test for TARGETING::AttributeTank::Attribute + */ + +//****************************************************************************** +// Includes +//****************************************************************************** + +// CXX TEST +#include <cxxtest/TestSuite.H> + +#include <targeting/common/attributeTank.H> + +using namespace TARGETING; + +class AttributeTest: public CxxTest::TestSuite +{ +public: + /** + * @test Tests the setters and getter methods + */ + void testSimpleSettersAndGetters(void); + + /** + * @test Test setting the Attribute Value + */ + void testSettingAndGettingValue(void); + + /** + * @test Test Serialize and Deserialize methods + */ + void testSerializeAndDeserializeMethod(void); + + /** + * @test Test the Operator Equal method + */ + void testOperatorEqual(void); + + /** + * @test Test the Copy Constructor Method + */ + void testCopyConstructor(void); + + private: + + /** + * @test Compare the Attribute Header for the two given attributes + * + * @param[in] l_attribute1 Attribute to compare with + * @param[in] l_attribute2 Attribute to compare with + * + * @return true if Attribute Header's match, false otherwise + */ + bool compareAttributeHeader( + const AttributeTank::Attribute* const l_attribute1, + const AttributeTank::Attribute* const l_attribute2); + + /** + * @test Compare the Attribute Values for the two given attributes + * + * @param[in] l_attribute1 Attribute to compare with + * @param[in] l_attribute2 Attribute to compare with + * + * @return true if Attribute Values` match, false otherwise + */ + bool compareAttributeValues( + const AttributeTank::Attribute* const l_attribute1, + const AttributeTank::Attribute* const l_attribute2); +}; // end class AttributeTest + + +// testSimpleSettersAndGetters +void AttributeTest::testSimpleSettersAndGetters(void) +{ + TRACFCOMP( g_trac_test, ENTER_MRK "testSimpleSettersAndGetters" ); + + // Test stats + uint8_t l_numTests(0); + uint8_t l_numFails(0); + + // Create an Attribute to test against + TARGETING::AttributeTank::Attribute l_attribute; + + // Get a reference to the Attribute Header to test that + // what is returned is truly a reference and not a copy + const TARGETING::AttributeTank::AttributeHeader &l_attributeHeader = + l_attribute.getHeader(); + + // Test setting/getting the Attribute ID + ++l_numTests; + l_attribute.setId(0x1001); + if (0x1001 != l_attribute.getHeader().iv_attrId) + { + TS_FAIL("testSimpleSettersAndGetters: Test 1 - " + "set/get Attribute ID failed; " + "expected 0x1001 but got back 0x%X", + l_attribute.getHeader().iv_attrId); + ++l_numFails; + } + + ++l_numTests; + if (0x1001 != l_attributeHeader.iv_attrId) + { + TS_FAIL("testSimpleSettersAndGetters: Test 2 - get Attribute ID " + "via Attribute Header reference failed; " + "expected 0x1001 but got back 0x%X", + l_attributeHeader.iv_attrId); + ++l_numFails; + } + + // Test setting/getting the Attribute Target Type + ++l_numTests; + l_attribute.setTargetType(0x2002); + if (0x2002 != l_attribute.getHeader().iv_targetType) + { + TS_FAIL("testSimpleSettersAndGetters: Test 3 - " + "set/get Attribute Target Type failed; " + "expected 0x2002 but got back 0x%X", + l_attribute.getHeader().iv_targetType); + ++l_numFails; + } + + ++l_numTests; + if (0x2002 != l_attributeHeader.iv_targetType) + { + TS_FAIL("testSimpleSettersAndGetters: Test 4 - get Attribute " + "Target Type via Attribute Header reference failed; " + "expected 0x2002 but got back 0x%X", + l_attributeHeader.iv_targetType); + ++l_numFails; + } + + // Test setting/getting the Attribute Position + ++l_numTests; + l_attribute.setPosition(0x3003); + if (0x3003 != l_attribute.getHeader().iv_pos) + { + TS_FAIL("testSimpleSettersAndGetters: Test 5 - " + "set/get Attribute Position failed; " + "expected 0x3003 but got back 0x%X", + l_attribute.getHeader().iv_pos); + ++l_numFails; + } + + ++l_numTests; + if (0x3003 != l_attributeHeader.iv_pos) + { + TS_FAIL("testSimpleSettersAndGetters: Test 6 - get Attribute Position " + "via Attribute Header reference failed; " + "expected 0x3003 but got back 0x%X", + l_attributeHeader.iv_pos); + ++l_numFails; + } + + // Test setting/getting the Attribute Unit Position + ++l_numTests; + l_attribute.setUnitPosition(0x4); + if (0x4 != l_attribute.getHeader().iv_unitPos) + { + TS_FAIL("testSimpleSettersAndGetters: Test 7 - " + "set/get Attribute Unit Position failed; " + "expected 0x4 but got back 0x%X", + l_attribute.getHeader().iv_unitPos); + ++l_numFails; + } + + ++l_numTests; + if (0x4 != l_attributeHeader.iv_unitPos) + { + TS_FAIL("testSimpleSettersAndGetters: Test 8 - " + "get Attribute Unit Position via Attribute Header reference " + "failed; expected 0x4 but got back 0x%X", + l_attributeHeader.iv_unitPos); + ++l_numFails; + } + + // Test setting/getting the Attribute Node + ++l_numTests; + l_attribute.setNode(0x5); + if (0x5 != l_attribute.getHeader().iv_node) + { + TS_FAIL("testSimpleSettersAndGetters: Test 9 - " + "set/get Attribute Node failed; " + "expected 0x5 but got back 0x%X", + l_attribute.getHeader().iv_node); + ++l_numFails; + } + + ++l_numTests; + if (0x5 != l_attributeHeader.iv_node) + { + TS_FAIL("testSimpleSettersAndGetters: Test 10 - get Attribute Node " + "via Attribute Header reference failed; " + "expected 0x5 but got back 0x%X", + l_attributeHeader.iv_node); + ++l_numFails; + } + + // Test setting/getting the Attribute Flags + ++l_numTests; + l_attribute.setFlags(0x6); + if (0x6 != l_attribute.getHeader().iv_flags) + { + TS_FAIL("testSimpleSettersAndGetters: Test 11 - " + "set/get Attribute Flags failed; " + "expected 0x6 but got back 0x%X", + l_attribute.getHeader().iv_flags); + ++l_numFails; + } + + ++l_numTests; + if (0x6 != l_attributeHeader.iv_flags) + { + TS_FAIL("testSimpleSettersAndGetters: Test 12 - get Attribute Flags " + "via Attribute Header reference failed; " + "expected 0x6 but got back 0x%X", + l_attributeHeader.iv_flags); + ++l_numFails; + } + + TRACFCOMP( g_trac_test, EXIT_MRK "testSimpleSettersAndGetters " + "num tests = %d / num fails = %d", l_numTests, l_numFails); +} // end testSimpleSettersAndGetters + + +// testSettingAndGettingValue +void AttributeTest::testSettingAndGettingValue(void) +{ + TRACFCOMP( g_trac_test, ENTER_MRK "testSettingAndGettingValue" ); + + // Test stats + uint8_t l_numTests(0); + uint8_t l_numFails(0); + + // Create an Attribute to test with + TARGETING::AttributeTank::Attribute l_attribute; + + /// Test getting Size of the Attribute when no Value exists/has been set + ++l_numTests; + if (l_attribute.getSize() != + sizeof(TARGETING::AttributeTank::AttributeHeader)) + { + TS_FAIL("testSettingAndGettingValue: Test 1 - " + "get Attribute Size failed, when no value set; " + "expected size %d but got back size %d", + sizeof(TARGETING::AttributeTank::AttributeHeader), + l_attribute.getSize()); + ++l_numFails; + } + + /// Test cloning the value when no Value exists/has been set + // First create a buffer + uint32_t l_bufferSize = 3; + uint8_t l_buffer[l_bufferSize] = { 0 }; + uint8_t l_compareBuffer[l_bufferSize] = { 0 }; + + uint32_t l_returnedSize = l_attribute.cloneValue(l_buffer, l_bufferSize); + // Make sure 0 is returned + ++l_numTests; + if (0 != l_returnedSize) + { + TS_FAIL("testSettingAndGettingValue: Test 2 - " + "Attribute clone value failed, with buffer size 0; " + "expected size 0 but got back size %d", + l_returnedSize); + ++l_numFails; + } + + // Make sure cloned data is correct + ++l_numTests; + if (0 != memcmp(l_buffer, l_compareBuffer, l_bufferSize)) + { + TS_FAIL("testSettingAndGettingValue: Test 3 - " + "Attribute clone value failed, with buffer size 0; " + "incorrect data returned"); + ++l_numFails; + } + + /// Test clearing the Value + l_returnedSize = l_attribute.setValue(nullptr, 0); + // Make sure 0 is returned + ++l_numTests; + if (0 != l_returnedSize) + { + TS_FAIL("testSettingAndGettingValue: Test 4 - " + "returned Attribute Size failed, sent a value of size 0; " + "expected size 0 but got back size %d", + l_returnedSize); + ++l_numFails; + } + + // Make sure size is only the Attribute Header size + ++l_numTests; + if (l_attribute.getSize() != + sizeof(TARGETING::AttributeTank::AttributeHeader)) + { + TS_FAIL("testSettingAndGettingValue: Test 5 - " + "get Attribute Size failed, sent a value of size 0; " + "expected size %d but got back size %d", + sizeof(TARGETING::AttributeTank::AttributeHeader), + l_attribute.getSize()); + ++l_numFails; + } + + // Make sure value is NULL + ++l_numTests; + if (nullptr != l_attribute.getValue()) + { + TS_FAIL("testSettingAndGettingValue: Test 6 - " + "get Attribute Value failed, sent a value of size 0; " + "expected nullptr but got back %p", + l_attribute.getValue()); + ++l_numFails; + } + + /// Send in buffer with smaller size than actual size of buffer + // Add data o the buffer + l_buffer[0] = 0xAA; + l_buffer[1] = 0xBB; + l_buffer[2] = 0xCC; + + // Set the Attribute Value to the buffer's first element + l_returnedSize = l_attribute.setValue(l_buffer, 1); + // Make sure only 1 is returned + ++l_numTests; + if (1 != l_returnedSize) + { + TS_FAIL("testSettingAndGettingValue: Test 7 - " + "returned Attribute Size failed, sent a value of size 1; " + "expected size 1 but got back size %d", + l_returnedSize); + ++l_numFails; + } + + // Make sure Attribute Value size is size of Attribute Header plus one + ++l_numTests; + if (l_attribute.getSize() != + (sizeof(TARGETING::AttributeTank::AttributeHeader) + 1)) + { + TS_FAIL("testSettingAndGettingValue: Test 8 - " + "get Attribute Size failed, sent a Value of size 1 " + "expected size %d but got back size %d", + sizeof(TARGETING::AttributeTank::AttributeHeader) + 1, + l_attribute.getSize()); + ++l_numFails; + } + + // Get a handle to the Value to do some testing on it + const uint8_t* const l_value = + reinterpret_cast<const uint8_t* const>(l_attribute.getValue()); + + // Make sure Value is not NULL + ++l_numTests; + if (nullptr == l_value) + { + TS_FAIL("testSettingAndGettingValue: Test 9 - " + "get Attribute Value failed; " + "expected a non-null pointer but got back a null pointer"); + ++l_numFails; + } + + // Make sure the first value is what we expect + ++l_numTests; + if (l_value[0] != 0xAA) + { + TS_FAIL("testSettingAndGettingValue: Test 10 - " + "Accessing first value in Attribute Value failed; " + "expected 0xAA but got back 0x%X", + l_value[0]); + ++l_numFails; + } + + // Test cloning with Attribute + uint8_t l_clonedBuffer[l_bufferSize] = { 0 }; + memset(l_compareBuffer, 0, l_bufferSize); + l_compareBuffer[0] = 0xAA; + l_returnedSize = l_attribute.cloneValue(l_clonedBuffer, l_bufferSize); + // Make sure 1 is returned + ++l_numTests; + if (1 != l_returnedSize) + { + TS_FAIL("testSettingAndGettingValue: Test 11 - " + "Attribute clone value failed, with buffer size 1; " + "expected size 1 but got back size %d", + l_returnedSize); + ++l_numFails; + } + + // Make sure the cloned data is correct + ++l_numTests; + if (0 != memcmp(l_clonedBuffer, l_compareBuffer, l_bufferSize)) + { + TS_FAIL("testSettingAndGettingValue: Test 12 - " + "Attribute clone value failed, with buffer size 1; " + "incorrect data returned"); + ++l_numFails; + } + + /// Send in buffer with actual size of said buffer + // First set the buffer's values + l_buffer[0] = 0xDD; + l_buffer[1] = 0xEE; + l_buffer[2] = 0xFF; + l_returnedSize = l_attribute.setValue(l_buffer, l_bufferSize); + + // Make sure buffer size is returned correctly + ++l_numTests; + if (l_bufferSize != l_returnedSize) + { + TS_FAIL("testSettingAndGettingValue: Test 13 - " + "returned Attribute Size failed, sent a buffer of size %d; " + "expected size %d but got back size %d", + l_bufferSize, + l_bufferSize, + l_returnedSize); + ++l_numFails; + } + + // Make sure Attribute Value size is size of Attribute Header + // plus buffer size + ++l_numTests; + if (l_attribute.getSize() != + (sizeof(TARGETING::AttributeTank::AttributeHeader) + l_bufferSize)) + { + TS_FAIL("testSettingAndGettingValue: Test 14 - " + "get Attribute Size failed, sent a buffer of size %d; " + "expected size %d but got back size %d", + l_bufferSize, + sizeof(TARGETING::AttributeTank::AttributeHeader) + l_bufferSize, + l_attribute.getSize()); + ++l_numFails; + } + + // Get a handle to the Value to do some testing on it + const uint8_t* const l_value2 = + reinterpret_cast<const uint8_t* const>(l_attribute.getValue()); + + // Make sure Value is not NULL + ++l_numTests; + if (nullptr == l_value2) + { + TS_FAIL("testSettingAndGettingValue: Test 15 - " + "get Attribute Value failed, sent a buffer of size %d " + "expected a non-null pointer but got back a null pointer", + l_bufferSize); + ++l_numFails; + } + + // Make sure the first value is what we expect + ++l_numTests; + if (l_value2[0] != 0xDD) + { + TS_FAIL("testSettingAndGettingValue: Test 16 - " + "Accessing first value in Attribute Value failed, " + "for a Value of size %d; " + "expected 0xDD but got back 0x%X", + l_bufferSize, + l_value2[0]); + ++l_numFails; + } + + // Make sure the second value is what we expect + ++l_numTests; + if (l_value2[1] != 0xEE) + { + TS_FAIL("testSettingAndGettingValue: Test 17 - " + "Accessing second value in Attribute Value failed, " + "for a Value of size %d; " + "expected 0xEE but got back 0x%X", + l_bufferSize, + l_value2[1]); + ++l_numFails; + } + + // Make sure the third value is what we expect + ++l_numTests; + if (l_value2[2] != 0xFF) + { + TS_FAIL("testSettingAndGettingValue: Test 18 - " + "Accessing third value in Attribute Value failed, " + "for a Value of size %d; " + "expected 0xFF but got back 0x%X", + l_bufferSize, + l_value2[2]); + ++l_numFails; + } + + /// Make sure previously cloned data is an actually cloned and not + /// a copy + ++l_numTests; + if (0 != memcmp(l_clonedBuffer, l_compareBuffer, l_bufferSize)) + { + TS_FAIL("testSettingAndGettingValue: Test 19 - " + "Attribute clone value failed, with buffer size 1; " + "data not cloned but is a reference a pointer"); + ++l_numFails; + } + + l_returnedSize = l_attribute.cloneValue(l_clonedBuffer, l_bufferSize); + // Make sure 3 is returned + ++l_numTests; + if (3 != l_returnedSize) + { + TS_FAIL("testSettingAndGettingValue: Test 20 - " + "returned Attribute clone value failed, with buffer size 3; " + "expected size 3 but got back size %d", + l_returnedSize); + ++l_numFails; + } + + /// Make sure previously cloned data is correct + ++l_numTests; + if (0 != memcmp(l_clonedBuffer, l_buffer, l_bufferSize)) + { + TS_FAIL("testSettingAndGettingValue: Test 21 - " + "Attribute clone value failed, with buffer size 3 ; " + "incorrect data returned"); + ++l_numFails; + } + + TRACFCOMP( g_trac_test, EXIT_MRK "testSettingAndGettingValue " + "num tests = %d / num fails = %d", l_numTests, l_numFails); +} // end AttributeTest::testSettingAndGettingValue + + +// testSerializeAndDeserializeMethod +void AttributeTest::testSerializeAndDeserializeMethod(void) +{ + TRACFCOMP( g_trac_test, ENTER_MRK "testSerializeAndDeserializeMethod" ); + + // Test stats + uint8_t l_numTests(0); + uint8_t l_numFails(0); + + // Create an Attribute to test with + AttributeTank::Attribute l_attribute; + // Get a copy of the Attribute Size for later purposes + uint32_t l_attributeSize(l_attribute.getSize()); + + /// Test serializing when attribute has no data at all + { + // Create a buffer to hold serialized data + uint8_t* l_serializedData = new uint8_t[l_attributeSize]; + // Get the serialized data + uint32_t l_returnedSize = l_attribute.serialize(l_serializedData, + l_attributeSize); + + // Make sure serialized data is the size expected + ++l_numTests; + if (l_returnedSize != l_attributeSize) + { + TS_FAIL("testSerializeAndDeserializeMethod: Test 1 - " + "Attribute Serialize failed, with a 0 size Data Value; " + "expected size %d but got back size %d", + l_attributeSize, + l_returnedSize); + ++l_numFails; + } + + // Make sure the serialized Attribute Header + // matches original Attribute Header + // Get a handle to Attribute Header + AttributeTank::Attribute* l_attribute2 = + reinterpret_cast<AttributeTank::Attribute*>(l_serializedData); + const AttributeTank::AttributeHeader & l_attributeHeader2 = + l_attribute2->getHeader(); + + // Compare the two different Attribute Header for a match + ++l_numTests; + if (!compareAttributeHeader(l_attribute2, &l_attribute)) + { + TS_FAIL("testSerializeAndDeserializeMethod: Test 2 - " + "Attribute Serialize failed, with a 0 size Data Value; " + "incorrect Attribute Header data returned"); + ++l_numFails; + } + + // Make sure that the size of the Attribute Values is zero + ++l_numTests; + if (0 != l_attributeHeader2.iv_valSize) + { + TS_FAIL("testSerializeAndDeserializeMethod: Test 3 - " + "Attribute Serialize failed, with a 0 size Data Value; " + "Expected 0 size Data Value but %d was returned", + l_attributeHeader2.iv_valSize); + ++l_numFails; + } + + // Test deserialize + { + AttributeTank::Attribute l_attribute3; + uint32_t l_returnedSize2 = + l_attribute3.deserialize(l_serializedData, l_returnedSize); + + // Make sure data size copied is correct + ++l_numTests; + if (l_returnedSize2 != l_returnedSize) + { + TS_FAIL("testSerializeAndDeserializeMethod: Test 4 - " + "Attribute Deserialize failed, with a 0 size Data Value; " + "expected size %d but got back size %d", + l_returnedSize, + l_returnedSize2); + ++l_numFails; + } + + // Make sure the Attribute Header matches original data + ++l_numTests; + if (!compareAttributeHeader(&l_attribute3, &l_attribute)) + { + TS_FAIL("testSerializeAndDeserializeMethod: Test 5 - " + "Attribute deserialize failed, with a 0 size Data Value; " + "incorrect Attribute Header data returned"); + ++l_numFails; + } + + // Test when buffer is too small + ++l_numTests; + AttributeTank::Attribute l_attribute4; + l_returnedSize2 = l_attribute4.deserialize(l_serializedData, + l_returnedSize - 1); + if (0 != l_returnedSize2) + { + TS_FAIL("testSerializeAndDeserializeMethod: Test 6 - " + "Attribute Deserialize failed, with too small of buffer;" + "expected size 0 but got back size %d", + l_returnedSize2); + ++l_numFails; + } + } + // Cleanup memory used for this test + delete []l_serializedData; + l_serializedData = nullptr; + } + + /// Test serializing when Attribute has Attribute Header data + /// and no Attribute Values + // Set some values for the Attribute Header + l_attribute.setId(0x1001); + l_attribute.setTargetType(0x2002); + l_attribute.setPosition(0x3003); + l_attribute.setUnitPosition(0x4); + l_attribute.setNode(0x5); + l_attribute.setFlags(0x6); + { + // Create a buffer to hold serialized data + uint8_t* l_serializedData = new uint8_t[l_attributeSize]; + // Get the serialized data + uint32_t l_returnedSize = l_attribute.serialize(l_serializedData, + l_attributeSize); + + // Make sure serialized data is the size expected + ++l_numTests; + if (l_returnedSize != l_attributeSize) + { + TS_FAIL("testSerializeAndDeserializeMethod: Test 7 - " + "Attribute Serialize failed, with valid Attribute " + "Header data and no Data Value;" + "expected size %d but got back size %d", + l_attributeSize, + l_returnedSize); + ++l_numFails; + } + + // Make sure the serialized Attribute Header + // matches original Attribute Header + // Get a handle to Attribute Header + AttributeTank::Attribute* l_attribute2 = + reinterpret_cast<AttributeTank::Attribute*>(l_serializedData); + const AttributeTank::AttributeHeader & l_attributeHeader2 = + l_attribute2->getHeader(); + // Compare the two different Attribute Header for a match + ++l_numTests; + if (!compareAttributeHeader(l_attribute2, &l_attribute)) + { + TS_FAIL("testSerializeAndDeserializeMethod: Test 8 - " + "Attribute Serialize failed, with valid Attribute " + "Header data and no Data Value;" + "incorrect Attribute Header data returned"); + ++l_numFails; + } + + // Make sure that the size of the Attribute Values is zero + ++l_numTests; + if (0 != l_attributeHeader2.iv_valSize) + { + TS_FAIL("testSerializeAndDeserializeMethod: Test 9 - " + "Attribute Serialize failed, with valid Attribute " + "Header data and no Data Value;" + "Expected 0 size Data Value but %d was returned", + l_attributeHeader2.iv_valSize); + ++l_numFails; + } + + // Test deserialize + { + AttributeTank::Attribute l_attribute3; + uint32_t l_returnedSize2 = + l_attribute3.deserialize(l_serializedData, l_returnedSize); + + // Make sure data size copied is correct + ++l_numTests; + if (l_returnedSize2 != l_returnedSize) + { + TS_FAIL("testSerializeAndDeserializeMethod: Test 10 - " + "Attribute Deserialize failed, with valid Attribute " + "Header data and no Data Value;" + "expected size %d but got back size %d", + l_returnedSize, + l_returnedSize2); + ++l_numFails; + } + + // Make sure the Attribute Header matches original data + ++l_numTests; + if (!compareAttributeHeader(&l_attribute3, &l_attribute)) + { + TS_FAIL("testSerializeAndDeserializeMethod: Test 11 - " + "Attribute Deserialize failed, with valid Attribute " + "Header data and no Data Value;" + "incorrect Attribute Header data returned"); + ++l_numFails; + } + } + + // Cleanup memory used for this test + delete []l_serializedData; + l_serializedData = nullptr; + } + + /// Test serializing when Attribute has Attribute Header data + /// and a single Attribute Value + // Give the Attribute a single Attribute Value + uint8_t l_dataBuffer[1] = { 0 }; + l_dataBuffer[0] = 0x44; + l_attribute.setValue(l_dataBuffer, 1); + l_attributeSize = l_attribute.getSize(); + { + // Create a buffer to hold serialized data + uint8_t* l_serializedData = new uint8_t[l_attributeSize]; + // Get the serialized data + uint32_t l_returnedSize = l_attribute.serialize(l_serializedData, + l_attributeSize); + + // Make sure serialized data is the size expected + ++l_numTests; + if (l_returnedSize != l_attributeSize) + { + TS_FAIL("testSerializeAndDeserializeMethod: Test 12 - " + "Attribute Serialize failed, with a size 1 Data Value; " + "expected size %d but got back size %d", + l_attributeSize, + l_returnedSize); + ++l_numFails; + } + + // Make sure the serialized Attribute Header + // matches original Attribute Header + // Get a handle to Attribute Header + AttributeTank::Attribute* l_attribute2 = + reinterpret_cast<AttributeTank::Attribute*>(l_serializedData); + const AttributeTank::AttributeHeader & l_attributeHeader2 = + l_attribute2->getHeader(); + // Compare the two different Attribute Header for a match + ++l_numTests; + if (!compareAttributeHeader(l_attribute2, &l_attribute)) + { + TS_FAIL("testSerializeAndDeserializeMethod: Test 13 - " + "Attribute Serialize failed, with a size 1 Data Value; " + "incorrect Attribute Header data returned"); + ++l_numFails; + } + + // Make sure that the size of the Attribute Values is 1 + ++l_numTests; + if (1 != l_attributeHeader2.iv_valSize) + { + TS_FAIL("testSerializeAndDeserializeMethod: Test 14 - " + "Attribute Serialize failed, with a size 1 Data Value; " + "Expected 1 size Data Value but %d was returned", + l_attributeHeader2.iv_valSize); + ++l_numFails; + } + + // Point to the Attribute Values + l_serializedData += sizeof(AttributeTank::AttributeHeader); + + // Compare the two different Attribute Value + ++l_numTests; + if (0 != memcmp(l_serializedData, &l_dataBuffer, 1)) + { + TS_FAIL("testSerializeAndDeserializeMethod: Test 15 - " + "Attribute Serialize failed, with a size 1 Data Value; " + "incorrect Attribute Data Value returned"); + ++l_numFails; + } + + // Reset the Serialized Data for next test + l_serializedData -= sizeof(AttributeTank::AttributeHeader); + + // Test deserialize + { + AttributeTank::Attribute l_attribute3; + uint32_t l_returnedSize2 = + l_attribute3.deserialize(l_serializedData, l_returnedSize); + // Make sure data size copied is correct + ++l_numTests; + if (l_returnedSize2 != l_returnedSize) + { + + TS_FAIL("testSerializeAndDeserializeMethod: Test 16 - " + "Attribute Deserialize failed, with a size 1 Data Value; " + "expected size %d but got back size %d", + l_returnedSize, + l_returnedSize2); + ++l_numFails; + } + + // Make sure the Attribute Header matches original data + ++l_numTests; + if (!compareAttributeHeader(&l_attribute3, &l_attribute)) + { + TS_FAIL("testSerializeAndDeserializeMethod: Test 17 - " + "Attribute deserialize failed, with a size 1 Data Value; " + "incorrect Attribute Header data returned"); + ++l_numFails; + } + + // Test when buffer is too small + AttributeTank::Attribute l_attribute4; + l_returnedSize2 = l_attribute4.deserialize(l_serializedData, + l_returnedSize - 1); + + // Make sure returned size is 0 + ++l_numTests; + if (0 != l_returnedSize2) + { + TS_FAIL("testSerializeAndDeserializeMethod: Test 18 - " + "Attribute Deserialize failed, with too small of buffer " + "for 1 data value; expected size 0 but got back size %d", + l_returnedSize2); + ++l_numFails; + } + } + + // Cleanup memory used for this test + delete []l_serializedData; + l_serializedData = nullptr; + } + + /// Test serializing when Attribute has Attribute Header data + /// and a several Attribute Values + // Give the Attribute several Attribute Values + uint32_t l_bufferSize(3); + uint8_t l_dataBuffer2[l_bufferSize] = { 0 }; + l_dataBuffer2[0] = 0x55; + l_dataBuffer2[1] = 0x66; + l_dataBuffer2[2] = 0x77; + l_attribute.setValue(l_dataBuffer2, l_bufferSize); + l_attributeSize = l_attribute.getSize(); + { + // Create a buffer to hold serialized data + uint8_t* l_serializedData = new uint8_t[l_attributeSize]; + // Get the serialized data + uint32_t l_returnedSize = l_attribute.serialize(l_serializedData, + l_attributeSize); + + // Make sure serialized data is the size expected + ++l_numTests; + if (l_returnedSize != l_attributeSize) + { + TS_FAIL("testSerializeAndDeserializeMethod: Test 19 - " + "Attribute Serialize failed, with a size 3 Data Value; " + "expected size %d but got back size %d", + l_attributeSize, + l_returnedSize); + ++l_numFails; + } + + // Make sure the serialized Attribute Header + // matches original Attribute Header + // Get a handle to Attribute Header + AttributeTank::Attribute* l_attribute2 = + reinterpret_cast<AttributeTank::Attribute*>(l_serializedData); + + // Compare the two different Attribute Header for a match + ++l_numTests; + if (!compareAttributeHeader(l_attribute2, &l_attribute)) + { + TS_FAIL("testSerializeAndDeserializeMethod: Test 20 - " + "Attribute Serialize failed, with a size 3 Data Value; " + "incorrect Attribute Header data returned"); + ++l_numFails; + } + + // Make sure that the size of the Attribute Values is 3 + ++l_numTests; + if (l_bufferSize != l_attribute2->getHeader().iv_valSize) + { + TS_FAIL("testSerializeAndDeserializeMethod: Test 21 - " + "Attribute Serialize failed, with a size 3 Data Value; " + "Expected %d size Data Value but %d was returned", + l_bufferSize, + l_attribute2->getHeader().iv_valSize); + + ++l_numFails; + } + + // Point to the Attribute Values + l_serializedData += sizeof(AttributeTank::AttributeHeader); + + + // Compare the two different Attribute Value + ++l_numTests; + if (0 != memcmp(l_serializedData, &l_dataBuffer2, l_bufferSize)) + { + TS_FAIL("testSerializeAndDeserializeMethod: Test 22 - " + "Attribute Serialize failed, with a size 3 Data Value; " + "incorrect Attribute Data Values returned"); + ++l_numFails; + } + + // Reset the Serialized Data for next test + l_serializedData -= sizeof(AttributeTank::AttributeHeader); + + // Test deserialize + { + AttributeTank::Attribute l_attribute3; + uint32_t l_returnedSize2 = + l_attribute3.deserialize(l_serializedData, l_returnedSize); + + // Make sure data size copied is correct + ++l_numTests; + if (l_returnedSize2 != l_returnedSize) + { + TS_FAIL("testSerializeAndDeserializeMethod: Test 23 - " + "Attribute Deserialize failed, with a size 3 Data Value; " + "expected size %d but got back size %d", + l_returnedSize, + l_returnedSize2); + ++l_numFails; + } + + // Make sure the Attribute Header matches original data + ++l_numTests; + if (!compareAttributeHeader(&l_attribute3, &l_attribute)) + { + TS_FAIL("testSerializeAndDeserializeMethod: Test 24 - " + "Attribute Deserialize failed, with a size 3 Data Value; " + "incorrect Attribute Header data returned"); + ++l_numFails; + } + + // Test when buffer is too small + AttributeTank::Attribute l_attribute4; + l_returnedSize2 = l_attribute4.deserialize(l_serializedData, + l_returnedSize - 1); + + // Make sure returned size is 0 + ++l_numTests; + if (0 != l_returnedSize2) + { + TS_FAIL("testSerializeAndDeserializeMethod: Test 25 - " + "Attribute Deserialize failed, with too small of buffer " + "for 3 data values; expected size 0 but got back size %d", + l_returnedSize2); + ++l_numFails; + } + } + + // Cleanup memory used for this test + delete []l_serializedData; + l_serializedData = nullptr; + } + + TRACFCOMP( g_trac_test, EXIT_MRK "testSerializeAndDeserializeMethod " + "num tests = %d / num fails = %d", l_numTests, l_numFails); +} // end AttributeTest::testSerializeAndDeserializeMethod + +// testOperatorEqual +void AttributeTest::testOperatorEqual(void) +{ + TRACFCOMP( g_trac_test, ENTER_MRK "testOperatorEqual" ); + + // Test stats + uint8_t l_numTests(0); + uint8_t l_numFails(0); + + // Create an Attribute to test against + AttributeTank::Attribute l_attribute1; + + // Test with an empty attribute + AttributeTank::Attribute l_attribute2; + // Invoke Operator Equal + l_attribute2 = l_attribute1; + + // Make sure the Attribute Header match + ++l_numTests; + if (!compareAttributeHeader(&l_attribute1, &l_attribute2)) + { + TS_FAIL("testOperatorEqual: Test 1 - " + "Attribute Operator = failed, with default values; " + "incorrect Attribute Header data returned"); + ++l_numFails; + } + + // Modify the data + l_attribute1.setId(0x1001); + l_attribute1.setTargetType(0x2002); + l_attribute1.setPosition(0x3003); + l_attribute1.setUnitPosition(0x4); + l_attribute1.setNode(0x5); + l_attribute1.setFlags(0x6); + + // Test with modified data + AttributeTank::Attribute l_attribute3; + // Invoke Operator Equal + l_attribute3 = l_attribute1; + + // Make sure the Attribute Header match + ++l_numTests; + if (!compareAttributeHeader(&l_attribute1, &l_attribute3)) + { + TS_FAIL("testOperatorEqual: Test 2 - " + "Attribute Operator = failed, with modifed values; " + "incorrect Attribute Header data returned"); + ++l_numFails; + } + + // Add attribute values + uint32_t l_bufferSize(3); + uint8_t l_buffer[l_bufferSize]; + l_buffer[0] = 0x66; + l_buffer[0] = 0x77; + l_buffer[0] = 0x88; + l_attribute1.setValue(l_buffer, l_bufferSize); + + // Test with modified data + AttributeTank::Attribute l_attribute4; + // Invoke Operator Equal + l_attribute4 = l_attribute1; + + // Make sure the Attribute Header match + ++l_numTests; + if (!compareAttributeHeader(&l_attribute1, &l_attribute4)) + { + TS_FAIL("testOperatorEqual: Test 3 - " + "Attribute Operator = failed, with data values; " + "incorrect Attribute Header data returned"); + ++l_numFails; + } + + // Make sure the Attribute Values match + ++l_numTests; + if (!compareAttributeValues(&l_attribute1, &l_attribute4)) + { + TS_FAIL("testOperatorEqual: Test 4 - " + "Attribute Operator = failed, with data values; " + "incorrect Attribute Values data returned"); + ++l_numFails; + } + + // Update the Attribute Values and test again + l_buffer[0] = 0x22; + l_buffer[0] = 0x33; + l_buffer[0] = 0x55; + l_attribute1.setValue(l_buffer, l_bufferSize); + + // Make sure the Attribute Header match original data + ++l_numTests; + if (!compareAttributeHeader(&l_attribute1, &l_attribute4)) + { + TS_FAIL("testOperatorEqual: Test 5 - " + "Attribute Operator = failed, with data values updated; " + "incorrect Attribute Header data returned"); + ++l_numFails; + } + + // Make sure the Attribute Values DO NOT match + ++l_numTests; + if (compareAttributeValues(&l_attribute1, &l_attribute4)) + { + TS_FAIL("testOperatorEqual: Test 6 - " + "Attribute Operator = failed, with data values updated; " + "incorrect Attribute Values data returned"); + ++l_numFails; + } + + TRACFCOMP( g_trac_test, EXIT_MRK "testOperatorEqual " + "num tests = %d / num fails = %d", l_numTests, l_numFails); +} // end testOperatorEqual + +// testCopyConstructor +void AttributeTest::testCopyConstructor(void) +{ + TRACFCOMP( g_trac_test, ENTER_MRK "testCopyConstructor" ); + + // Test stats + uint8_t l_numTests(0); + uint8_t l_numFails(0); + + // Create an Attribute to test against + AttributeTank::Attribute l_attribute1; + + l_attribute1.setId(0x1001); + l_attribute1.setFlags(0x5); + + // Test with an empty attribute, invoke copy constructor + AttributeTank::Attribute l_attribute2 = l_attribute1; + + // Make sure the Attribute Header match + ++l_numTests; + if (!compareAttributeHeader(&l_attribute1, &l_attribute2)) + { + TS_FAIL("testCopyConstructor: Test 1 - " + "Attribute Copy Ctor failed, with default values; " + "incorrect Attribute Header data returned"); + ++l_numFails; + } + + // Modify the data + l_attribute1.setId(0x1001); + l_attribute1.setTargetType(0x2002); + l_attribute1.setPosition(0x3003); + l_attribute1.setUnitPosition(0x4); + l_attribute1.setNode(0x5); + l_attribute1.setFlags(0x6); + + // Test with modified data, invoke copy constructor + AttributeTank::Attribute l_attribute3 = l_attribute1; + + // Make sure the Attribute Header match + ++l_numTests; + if (!compareAttributeHeader(&l_attribute1, &l_attribute3)) + { + TS_FAIL("testCopyConstructor: Test 2 - " + "Attribute Copy Ctor failed, with modifed values; " + "incorrect Attribute Header data returned"); + ++l_numFails; + } + + // Add attribute values + uint32_t l_bufferSize(3); + uint8_t l_buffer[l_bufferSize]; + l_buffer[0] = 0x66; + l_buffer[0] = 0x77; + l_buffer[0] = 0x88; + l_attribute1.setValue(l_buffer, l_bufferSize); + + // Test with modified data, invoke copy constructor + AttributeTank::Attribute l_attribute4 = l_attribute1; + + // Make sure the Attribute Header match + ++l_numTests; + if (!compareAttributeHeader(&l_attribute1, &l_attribute4)) + { + TS_FAIL("testCopyConstructor: Test 3 - " + "Attribute Copy Ctor failed, with data values; " + "incorrect Attribute Header data returned"); + ++l_numFails; + } + + // Make sure the Attribute Values match + ++l_numTests; + if (!compareAttributeValues(&l_attribute1, &l_attribute4)) + { + TS_FAIL("testCopyConstructor: Test 4 - " + "Attribute Copy Ctor failed, with data values; " + "incorrect Attribute Values data returned"); + ++l_numFails; + } + + // Update the Attribute Values and test again + l_buffer[0] = 0x22; + l_buffer[0] = 0x33; + l_buffer[0] = 0x55; + l_attribute1.setValue(l_buffer, l_bufferSize); + + // Make sure the Attribute Header match original data + ++l_numTests; + if (!compareAttributeHeader(&l_attribute1, &l_attribute4)) + { + TS_FAIL("testCopyConstructor: Test 5 - " + "Attribute Copy Ctor failed, with data values updated; " + "incorrect Attribute Header data returned"); + ++l_numFails; + } + + // Make sure the Attribute Values DO NOT match + ++l_numTests; + if (compareAttributeValues(&l_attribute1, &l_attribute4)) + { + TS_FAIL("testCopyConstructor: Test 6 - " + "Attribute Copy Ctor failed, with data values updated; " + "incorrect Attribute Values data returned"); + ++l_numFails; + } + + TRACFCOMP( g_trac_test, EXIT_MRK "testCopyConstructor " + "num tests = %d / num fails = %d", l_numTests, l_numFails); +} // end testCopyConstructor + +// compareAttributeHeader +bool AttributeTest::compareAttributeHeader( + const AttributeTank::Attribute* const l_attribute1, + const AttributeTank::Attribute* const l_attribute2) +{ + bool retVal(true); + + // Make sure the Attribute Header matches original data + if (0 != memcmp(&(l_attribute1->getHeader()), + &(l_attribute2->getHeader()), + sizeof(AttributeTank::AttributeHeader))) + { + retVal = false; + } + + return retVal; + +} // end compareAttributeHeader + +// compareAttributeValues +bool AttributeTest::compareAttributeValues( + const AttributeTank::Attribute* const l_attribute1, + const AttributeTank::Attribute* const l_attribute2) +{ + bool retVal(true); + + // Compare the Attribute Values for a match + if (0 != memcmp(l_attribute1->getValue(), + l_attribute2->getValue(), + l_attribute2->getHeader().iv_valSize)) + { + retVal = false; + } + + return retVal; + +} // end compareAttributeValues + +#endif // end __TEST_ATTRIBUTE_H diff --git a/src/usr/targeting/test/testTargetUtil.H b/src/usr/targeting/test/testTargetUtil.H new file mode 100644 index 000000000..1cfc8412f --- /dev/null +++ b/src/usr/targeting/test/testTargetUtil.H @@ -0,0 +1,458 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/targeting/test/testTargetUtil.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2011,2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +#ifndef __TEST_TARGETING_UTIL_H +#define __TEST_TARGETING_UTIL_H + +/** + * @file targeting/test/testTargetUtil.H + * + * @brief Unit test for the templates makeAttribute + * and makeAttributeStdArr + */ + +//****************************************************************************** +// Includes +//****************************************************************************** + +// CXX TEST +#include <cxxtest/TestSuite.H> + +#include <targeting/common/targetUtil.H> + +using namespace TARGETING; + +//****************************************************************************** +// class MakeAttributeTest +//****************************************************************************** +class MakeAttributeTest: public CxxTest::TestSuite +{ +public: + + /** + * @test Test the Make Attribute template + */ + void testMakeAttribute(void); + + /** + * @test Test the Make Attribute for Standard Array template + */ + void testMakeAttributeStdArr(void); + +}; // end class MakeAttributeTest + +// testMakeAttribute +void MakeAttributeTest::testMakeAttribute(void) +{ + TRACFCOMP( g_trac_test, ENTER_MRK "testMakeAttribute" ); + + // Test stats + uint8_t l_numTests(0); + uint8_t l_numFails(0); + + if (!TARGETING::targetService().isInitialized()) + { + TS_FAIL("testMakeAttribute: Target Service is not initialized, " + "cannot perform test, exiting"); + + TRACFCOMP( g_trac_test, EXIT_MRK "testMakeAttribute " + "num tests = 1 / num fails = 1"); + return; + } + + // Get the top level target + TARGETING::Target * l_sys(nullptr); + TARGETING::targetService().getTopLevelTarget( l_sys ); + + if(!l_sys) + { + TS_FAIL("testMakeAttribute: Get Top Level Target failed, " + "unable to get top level target, cannot perform " + "test, exiting"); + + TRACFCOMP( g_trac_test, EXIT_MRK "testMakeAttribute " + "num tests = 1 / num fails = 1"); + return; + } + + // Save initial value to restore later + uint8_t l_simpleTypeRestoreValue = + l_sys->getAttr<TARGETING::ATTR_IS_SIMULATION>(); + + // Test 1, test a simple attribute with known data + ++l_numTests; + do + { + // Set the attribute 'Is Simulation' to a known value to + // facilitate testing + uint8_t l_isSimulationSet = 1; + l_sys->setAttr<TARGETING::ATTR_IS_SIMULATION>(l_isSimulationSet); + uint8_t l_isSimulationReturn = + l_sys->getAttr<TARGETING::ATTR_IS_SIMULATION>(); + + // Verify setting the attribute worked + if (l_isSimulationSet != l_isSimulationReturn) + { + TS_FAIL("testMakeAttribute: Test 1 - Setting attribute failed " + "to initialize attribute to %d but retained " + "value at %d, cannot perform test, exiting", + l_isSimulationSet, + l_isSimulationReturn); + ++l_numFails; + break; + } + + // Retrieve that set attribute back via the 'make attribute' call + TARGETING::AttributeTank::Attribute l_attribute; + bool l_return = + TARGETING::makeAttribute<TARGETING::ATTR_IS_SIMULATION> + (l_sys, l_attribute); + + // Verify the called worked + if (true != l_return) + { + TS_INFO("testMakeAttribute: Test 1 - Make attribute call failed"); + ++l_numFails; + break; + } + + // Get a pointer to the attribute created in make attribute call, + // to get to the data. + const uint8_t* l_attributeValue = + static_cast<const uint8_t*>(l_attribute.getValue()); + + // If the pointer to the data is NULL, then the make attribute did fail + if (l_attributeValue == nullptr) + { + TS_INFO("testMakeAttribute: Test 1 - Getting attribute value " + "failed, NULL pointer returned when getting value."); + ++l_numFails; + break; + } + + // Verify the returned attribute matches it's set value + if (*l_attributeValue != l_isSimulationSet) + { + TS_INFO("testMakeAttribute: Test 1 - Retrieved attribute value " + "failed, retrieved attribute value(%d) does not " + "match set attribute value(%d)", + l_isSimulationSet, + *l_attributeValue); + ++l_numFails; + break; + } + } + while (0); + + // Test 2, test the same simple attribute but with different data + ++l_numTests; + do + { + // Set the attribute 'Is Simulation' to a known value to + // facilitate testing + uint8_t l_isSimulationSet = 5; + l_sys->setAttr<TARGETING::ATTR_IS_SIMULATION>(l_isSimulationSet); + uint8_t l_isSimulationReturn = + l_sys->getAttr<TARGETING::ATTR_IS_SIMULATION>(); + + // Verify setting the attribute worked + if (l_isSimulationSet != l_isSimulationReturn) + { + TS_FAIL("testMakeAttribute: Test 2 - Setting attribute failed " + "to initialize attribute to %d but retained " + "value at %d, cannot perform test, exiting", + l_isSimulationSet, + l_isSimulationReturn); + ++l_numFails; + break; + } + + // Retrieve that set attribute back via the 'make attribute' call + TARGETING::AttributeTank::Attribute l_attribute; + bool l_return = + TARGETING::makeAttribute<TARGETING::ATTR_IS_SIMULATION> + (l_sys, l_attribute); + + // Verify the called worked + if (true != l_return) + { + TS_INFO("testMakeAttribute: Test 2 - Make attribute call failed"); + ++l_numFails; + break; + } + + // Get a pointer to the attribute created in make attribute call, + // to get to the data. + const uint8_t* l_attributeValue = + static_cast<const uint8_t*>(l_attribute.getValue()); + + // If the pointer to the data is NULL, then the make attribute did fail + if (l_attributeValue == nullptr) + { + TS_INFO("testMakeAttribute: Test 1 - Getting attribute value " + "failed, NULL pointer returned when getting value."); + ++l_numFails; + break; + } + + // Verify the returned attribute matches it's set value + if (*l_attributeValue != l_isSimulationSet) + { + TS_INFO("testMakeAttribute: Test 2 - Retrieved attribute value " + "failed, retrieved attribute value(%d) does not " + "match set attribute value(%d)", + l_isSimulationSet, + *l_attributeValue); + ++l_numFails; + break; + } + } + while (0); + + // Restore value + l_sys->setAttr<TARGETING::ATTR_IS_SIMULATION>(l_simpleTypeRestoreValue); + + TRACFCOMP( g_trac_test, EXIT_MRK "testMakeAttribute " + "num tests = %d / num fails = %d", l_numTests, l_numFails); +} // end testMakeAttribute + +// testMakeAttributeStdArr +void MakeAttributeTest::testMakeAttributeStdArr(void) +{ + TRACFCOMP( g_trac_test, ENTER_MRK "testMakeAttributeStdArr" ); + + // Test stats + uint8_t l_numTests(0); + uint8_t l_numFails(0); + + + if (!TARGETING::targetService().isInitialized()) + { + TS_FAIL("testMakeAttributeStdArr: Target Service is not initialized, " + "cannot perform test, exiting"); + + TRACFCOMP( g_trac_test, EXIT_MRK "testMakeAttributeStdArr: " + "num tests = 1 / num fails = 1"); + return; + } + + // Get the top level target + TARGETING::Target * l_sys(nullptr); + TARGETING::targetService().getTopLevelTarget( l_sys ); + + if(!l_sys) + { + TS_FAIL("testMakeAttributeStdArr: Get Top Level Target failed, " + "unable to get top level target, cannot perform " + "test, exiting"); + + TRACFCOMP( g_trac_test, EXIT_MRK "testMakeAttributeStdArr: " + "num tests = 1 / num fails = 1"); + return; + } + + // Save initial value to restore later + TARGETING::ATTR_IPC_NODE_BUFFER_GLOBAL_ADDRESS_typeStdArr + l_complexTypeRestoreValue; + + // Test 1, test a complex attribute with known data + ++l_numTests; + do + { + // Set the attribute 'IPC Node Buffer Global Address' to a + // known value to facilitate testing + TARGETING::ATTR_IPC_NODE_BUFFER_GLOBAL_ADDRESS_typeStdArr + l_complexTypeSet = {9, 6, 3, 1, 5, 1, 7, 3}; + + if ( !l_sys->trySetAttr<TARGETING::ATTR_IPC_NODE_BUFFER_GLOBAL_ADDRESS>( + l_complexTypeSet) ) + { + TS_FAIL("testMakeAttributeStdArr: Test 1 - can't set " + "TARGETING::ATTR_IPC_NODE_BUFFER_GLOBAL_ADDRESS "); + ++l_numFails; + break; + } + + // Do a sanity check and make sure we can set/get attribute via + // trySetAttr/tryGetAttr + TARGETING::ATTR_IPC_NODE_BUFFER_GLOBAL_ADDRESS_typeStdArr + l_complexTypeGet; + + if ( !l_sys->tryGetAttr<TARGETING::ATTR_IPC_NODE_BUFFER_GLOBAL_ADDRESS>( + l_complexTypeGet) ) + { + TS_FAIL("testMakeAttributeStdArr: Test 1 - can't get " + "TARGETING::ATTR_IPC_NODE_BUFFER_GLOBAL_ADDRESS "); + ++l_numFails; + break; + } + + // Verify setting the attribute worked + if (0 != memcmp(&l_complexTypeGet, &l_complexTypeSet, + sizeof(l_complexTypeSet)) ) + { + TS_FAIL("testMakeAttributeStdArr: Test 1 - Setting " + "attribute failed, cannot perform test, exiting"); + ++l_numFails; + break; + } + + // Retrieved that set attribute back via the 'make attribute' call + TARGETING::AttributeTank::Attribute l_attribute; + bool l_return = + TARGETING::makeAttributeStdArr + <TARGETING::ATTR_IPC_NODE_BUFFER_GLOBAL_ADDRESS> + (l_sys, l_attribute); + + // Verify the called worked + if (l_return == false) + { + TS_FAIL("testMakeAttributeStdArr: Test 1 - Make " + "attribute call failed"); + ++l_numFails; + break; + } + + // Get a pointer to the attribute created in make attribute call, + // to get to the data. + const uint8_t* l_attributeValue = + static_cast<const uint8_t*>(l_attribute.getValue()); + + // If the pointer to the data is NULL, then the make attribute did fail + if (l_attributeValue == nullptr) + { + TS_INFO("testMakeAttributeStdArr: Test 1 - Getting attribute value " + "failed, NULL pointer returned when getting value."); + ++l_numFails; + } + + // Verify the returned attribute matches it's set value + if (0 != memcmp(l_attributeValue, &l_complexTypeSet, + sizeof(l_complexTypeSet)) ) + { + TS_INFO("testMakeAttributeStdArr: Test 1 - Retrieved attribute " + "value failed, expected value and retrieved value do " + "not match"); + ++l_numFails; + break; + } + } + while (0); + + + // Test 2, test the same complex attribute but with different data + ++l_numTests; + do + { + // Set the attribute 'IPC Node Buffer Global Address' to a + // known value to facilitate testing + TARGETING::ATTR_IPC_NODE_BUFFER_GLOBAL_ADDRESS_typeStdArr + l_complexTypeSet = {1, 2, 6, 8, 3, 2, 9, 3}; + + if ( !l_sys->trySetAttr<TARGETING::ATTR_IPC_NODE_BUFFER_GLOBAL_ADDRESS>( + l_complexTypeSet) ) + { + TS_FAIL("testMakeAttributeStdArr: Test 2 - can't set " + "TARGETING::ATTR_IPC_NODE_BUFFER_GLOBAL_ADDRESS "); + ++l_numFails; + break; + } + + // Do a sanity check and make sure we can set/get attribute via + // trySetAttr/tryGetAttr + TARGETING::ATTR_IPC_NODE_BUFFER_GLOBAL_ADDRESS_typeStdArr + l_complexTypeGet; + + if ( !l_sys->tryGetAttr<TARGETING::ATTR_IPC_NODE_BUFFER_GLOBAL_ADDRESS>( + l_complexTypeGet) ) + { + TS_FAIL("testMakeAttributeStdArr: Test 2 - can't get " + "TARGETING::ATTR_IPC_NODE_BUFFER_GLOBAL_ADDRESS "); + ++l_numFails; + break; + } + + // Verify setting the attribute worked + if (0 != memcmp(&l_complexTypeGet, &l_complexTypeSet, + sizeof(l_complexTypeSet)) ) + { + TS_FAIL("testMakeAttributeStdArr: Test 2 - Setting " + "attribute failed, cannot perform test, exiting"); + ++l_numFails; + break; + } + + // Retrieved that set attribute back via the 'make attribute' call + TARGETING::AttributeTank::Attribute l_attribute; + bool l_return = + TARGETING::makeAttributeStdArr + <TARGETING::ATTR_IPC_NODE_BUFFER_GLOBAL_ADDRESS> + (l_sys, l_attribute); + + // Verify the called worked + if (l_return == false) + { + TS_FAIL("testMakeAttributeStdArr: Test 2 - Make " + "attribute call failed"); + ++l_numFails; + break; + } + + // Get a pointer to the attribute created in make attribute call, + // to get to the data. + const uint8_t* l_attributeValue = + static_cast<const uint8_t*>(l_attribute.getValue()); + + // If the pointer to the data is NULL, then the make attribute did fail + if (l_attributeValue == nullptr) + { + TS_INFO("testMakeAttributeStdArr: Test 2 - Getting attribute value " + "failed, NULL pointer returned when getting value."); + ++l_numFails; + } + + // Verify the returned attribute matches it's set value + if (0 != memcmp(l_attributeValue, &l_complexTypeSet, + sizeof(l_complexTypeSet)) ) + { + TS_INFO("testMakeAttributeStdArr: Test 2 - Retrieved attribute " + "value failed, expected value and retrieved value do " + "not match"); + ++l_numFails; + break; + } + } + while (0); + + // Restore value + l_sys->trySetAttr<TARGETING::ATTR_IPC_NODE_BUFFER_GLOBAL_ADDRESS>( + l_complexTypeRestoreValue); + + TRACFCOMP( g_trac_test, EXIT_MRK "testMakeAttributeStdArr " + "num tests = %d / num fails = %d", l_numTests, l_numFails); + +} // end testMakeAttributeStdArr + +#endif // end __TEST_ATTRIBUTE_H diff --git a/src/usr/targeting/test/testtargeting.H b/src/usr/targeting/test/testtargeting.H index 66bb940ca..5f49781df 100644 --- a/src/usr/targeting/test/testtargeting.H +++ b/src/usr/targeting/test/testtargeting.H @@ -147,6 +147,76 @@ void* funcTestRecursiveMutexEntry(void* i_pData) return nullptr; } +/** + * @brief Function to test get and set of std::array values for attributes that + * support it. Any N-th dimensional array can be tested. + * + * @param[in] i_target Pointer to target object + * @param[in] i_setVal TA_typeStdArr type value to set + */ +template <const TARGETING::ATTRIBUTE_ID TA, typename TA_typeStdArr, + typename TA_type> +void testStdArrayND(TARGETING::Target *i_target, TA_typeStdArr i_setVal) +{ + + // Storing original value + TA_type l_origVal; + + if(!i_target->tryGetAttr<TA>(l_origVal)) + { + TS_FAIL("Failed to get original value of attribute."); + return; + } + + // Setting value using std::array as input + i_target->setAttrFromStdArr<TA>(i_setVal); + + // Get c-style array + TA_type l_cArrOutVal; + if(!i_target->tryGetAttr<TA>(l_cArrOutVal)) + { + TS_FAIL("Could not get c-style array value of attribute."); + return; + } + + // Copying l_cArrOutVal to a std::array var so that it can be + // compared with l_outVal below + TA_typeStdArr l_cArrOutValStdArr; + memcpy(&l_cArrOutValStdArr, &l_cArrOutVal, sizeof(l_cArrOutVal)); + + // std::array output + auto l_outVal = i_target->getAttrAsStdArr<TA>(); + + // Comparing set value with std::array value, and std::array value with + // c-array value + if (l_outVal == i_setVal) + { + TS_INFO("Success, get value equals set value."); + if (l_cArrOutValStdArr == l_outVal) + { + TS_INFO("Success, get c-style array value equals get std::array" + " value."); + } + else + { + TS_FAIL("Failure, get c-style array value does not equal get" + " std::array value."); + } + } + else + { + TS_FAIL("Failure, get value does not equal set value."); + } + + // Restoring original value + if(!i_target->trySetAttr<TA>(l_origVal)) + { + TS_FAIL("Failed to restore original attribute value."); + } + +} + + class TargetingTestSuite : public CxxTest::TestSuite { public: @@ -489,6 +559,59 @@ class TargetingTestSuite : public CxxTest::TestSuite TS_TRACE(EXIT_MRK "testSignedAttribute"); } + /** + * @brief Testing attribute's ability to get/set using std::array + */ + void testStdArray() + { + + // Testing 1D array + + TS_INFO(ENTER_MRK "testStdArray: Testing 1D array"); + + constexpr auto TA = TARGETING::ATTR_IPC_NODE_BUFFER_GLOBAL_ADDRESS; + // TA: targeting attribute + typedef TARGETING::ATTR_IPC_NODE_BUFFER_GLOBAL_ADDRESS_typeStdArr + TA_typeStdArr; + typedef TARGETING::ATTR_IPC_NODE_BUFFER_GLOBAL_ADDRESS_type TA_type; + + TARGETING::Target* l_pTarget = nullptr; + TARGETING::targetService().getTopLevelTarget(l_pTarget); + assert(l_pTarget != nullptr, "testStdArray, unable to establish top" + " level target service"); + + TA_typeStdArr l_setVal = {9, 6, 3, 1, 5, 1, 7, 3}; + + testStdArrayND<TA, TA_typeStdArr, TA_type>(l_pTarget, l_setVal); + + // Testing 2D array + TS_INFO(ENTER_MRK "testStdArray: Testing 2D array"); + + constexpr auto TA2 = TARGETING::ATTR_EEPROM_PAGE_ARRAY; + typedef TARGETING::ATTR_EEPROM_PAGE_ARRAY_typeStdArr TA2_typeStdArr; + typedef TARGETING::ATTR_EEPROM_PAGE_ARRAY_type TA2_type; + + TARGETING::TargetHandleList l_procList; + TARGETING::getAllChips(l_procList, TARGETING::TYPE_PROC); + + if (l_procList.size() == 0 ) + { + TS_FAIL("Failed to get proc targets."); + } + else + { + // Setting value using std::array as input + TA2_typeStdArr l_setVal2 {{ {9, 6, 3, 1}, {8, 4, 2, 44}, + {18, 14, 22, 2}, {77, 8, 6, 54} }}; + + testStdArrayND<TA2, TA2_typeStdArr, TA2_type>(l_procList.front(), + l_setVal2); + } + + TS_INFO(EXIT_MRK "testStdArray"); + + } + void testPciPhbTarget() { TS_TRACE(ENTER_MRK "testPciPhbTarget" ); @@ -598,6 +721,9 @@ class TargetingTestSuite : public CxxTest::TestSuite { // Mask off upper 8 bits in case of multiple nodes uint32_t l_huid = get_huid(*l_targetList) & 0x00FFFFFF; + + // Only keep lower bits for instance num + uint8_t l_instanceNum = l_huid & 0xFF; // Extract the type, drop instance info l_huid = l_huid >> 16; if (TARGETING::TYPE_I2C_MUX != l_huid) @@ -621,14 +747,30 @@ class TargetingTestSuite : public CxxTest::TestSuite char * l_pathAsString = l_i2cMuxInfo.i2cMasterPath.toString(); - if (0 != strcmp(l_pathAsString, - "Physical:/Sys0/Node0/Proc0")) + + // There is 1 mux per MC, so 2 muxes per proc + if (l_instanceNum >= 0 && l_instanceNum < 2) { - TS_FAIL("testI2cMux::i2cMuxPath path " - "returned(%s), " - "expected(Physical:/Sys0/Node0/Proc0)", - l_pathAsString); - } // end if (TARGETING + if (0 != strcmp(l_pathAsString, + "Physical:/Sys0/Node0/Proc0")) + { + TS_FAIL("testI2cMux::i2cMuxPath path " + "returned(%s), " + "expected(Physical:/Sys0/Node0/Proc0)", + l_pathAsString); + } + } + else + { + if (0 != strcmp(l_pathAsString, + "Physical:/Sys0/Node0/Proc1")) + { + TS_FAIL("testI2cMux::i2cMuxPath path " + "returned(%s), " + "expected(Physical:/Sys0/Node0/Proc1)", + l_pathAsString); + } + } free (l_pathAsString); l_pathAsString = nullptr; diff --git a/src/usr/targeting/xmltohb/fapi_utils.pl b/src/usr/targeting/xmltohb/fapi_utils.pl index 9253fa9eb..f1e7bd124 100644 --- a/src/usr/targeting/xmltohb/fapi_utils.pl +++ b/src/usr/targeting/xmltohb/fapi_utils.pl @@ -6,7 +6,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2017 +# Contributors Listed Below - COPYRIGHT 2017,2019 # [+] International Business Machines Corp. # # @@ -282,7 +282,8 @@ sub createTargetExtensionFromFapi(\%,\%) TARGET_TYPE_OMIC => "unit-omic-power9", TARGET_TYPE_MCC => "unit-mcc-power9", TARGET_TYPE_OCMB_CHIP => "chip-ocmb", - TARGET_TYPE_MEM_PORT => "unit-mem_port" + TARGET_TYPE_MEM_PORT => "unit-mem_port", + TARGET_TYPE_PMIC => "pmic", }; # Loop through all of the targets that this attribute @@ -293,7 +294,7 @@ sub createTargetExtensionFromFapi(\%,\%) my $foundmatch = 0; $type =~ s/\s//g; my $targtype = $fapi2targ->{$type}; - #print "type = $type -> $targtype\n"; + # print "type = $type -> $targtype\n"; my $attrid = $fapiattr->{id}; $attrid =~ s/ATTR_//; diff --git a/src/usr/targeting/xmltohb/makefile b/src/usr/targeting/xmltohb/makefile index 8f36b995e..213d9a3a5 100755 --- a/src/usr/targeting/xmltohb/makefile +++ b/src/usr/targeting/xmltohb/makefile @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2011,2018 +# Contributors Listed Below - COPYRIGHT 2011,2019 # [+] International Business Machines Corp. # # @@ -59,11 +59,13 @@ FAPIATTRSRVC_SOURCE = \ # Attribute XML files. -FAPI2_ATTR_XML += $(wildcard $(ROOTPATH)/src/import/chips/p9/procedures/xml/attribute_info/*) -FAPI2_ATTR_XML += $(wildcard $(ROOTPATH)/src/import/hwpf/fapi2/xml/attribute_info/*) -FAPI2_ATTR_XML += $(wildcard $(ROOTPATH)/src/import/chips/centaur/procedures/xml/attribute_info/*) -FAPI2_ATTR_XML += $(wildcard $(ROOTPATH)/src/import/generic/procedures/xml/attribute_info/*) -FAPI2_ATTR_XML += $(wildcard $(ROOTPATH)/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/*) +FAPI2_ATTR_XML += $(wildcard $(ROOTPATH)/src/import/chips/p9/procedures/xml/attribute_info/*.xml) +FAPI2_ATTR_XML += $(wildcard $(ROOTPATH)/src/import/hwpf/fapi2/xml/attribute_info/*.xml) +FAPI2_ATTR_XML += $(wildcard $(ROOTPATH)/src/import/chips/centaur/procedures/xml/attribute_info/*.xml) +FAPI2_ATTR_XML += $(wildcard $(ROOTPATH)/src/import/generic/procedures/xml/attribute_info/*.xml) +FAPI2_ATTR_XML += $(wildcard $(ROOTPATH)/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/*.xml) +FAPI2_ATTR_XML += $(wildcard $(ROOTPATH)/src/import/chips/ocmb/common/procedures/xml/attribute_info/*.xml) + # Filter out Temp defaults XML file from Attribute XML files. # NOTE: The hb_temp_defaults.xml file is not a normal attribute file with the @@ -230,7 +232,8 @@ CLEAN_TARGETS += $(addprefix $(GENDIR)/, ${XMLTOHB_SYSTEM_BINARIES:.bin=.xml}) CLEAN_TARGETS += ${GENDIR}/${HB_PLAT_ATTR_SRVC_H} CLEAN_TARGETS += ${GENDIR}/${XMLTOHB_GENERIC_XML} CLEAN_TARGETS += ${GENDIR}/${XMLTOHB_FAPI_XML} -CLEAN_TARGETS += ${GENDIR}/errl/errludattribute.H +CLEAN_TARGETS += ${GENDIR}/errl/errludattributeP_gen.H +CLEAN_TARGETS += ${GENDIR}/errludattribute_gen.C CLEAN_TARGETS += ${GENDIR}/errl/errludtarget.H CLEAN_TARGETS += ${GENDIR}/targAttrInfo.csv CLEAN_TARGETS += ${GENDIR}/targAttrOverrideData.H @@ -381,8 +384,7 @@ ${GENDIR}/${XMLTOHB_FULL_ATTRIBUTE_TYPES}: \ $(addprefix --ekbXmlFile=,${GENDIR}/${XMLTOHB_EKB_ATTRIBUTE_TYPES}) \ $(addprefix --hbXmlFile=,${GENDIR}/${XMLTOHB_SRC_ATTRIBUTE_TYPES}) \ $(addprefix --fapi2Header=,${ROOTPATH}/src/include/usr/fapi2/attribute_service.H) \ - $(addprefix --outFile=,${GENDIR}/${XMLTOHB_FULL_ATTRIBUTE_TYPES}) \ - --verbose + $(addprefix --outFile=,${GENDIR}/${XMLTOHB_FULL_ATTRIBUTE_TYPES}) # Add EKB attribute xml to config xml to produce the final output. # Skip adding any attributes that already exists in the src xml @@ -393,8 +395,7 @@ ${GENDIR}/${XMLTOHB_SP_ATTRIBUTE_TYPES}: \ $(addprefix --ekbXmlFile=,${GENDIR}/${XMLTOHB_EKB_ATTRIBUTE_TYPES}) \ $(addprefix --hbXmlFile=,${GENDIR}/${XMLTOHB_CONFIG_ATTRIBUTE_TYPES}) \ $(addprefix --fapi2Header=,${ROOTPATH}/src/include/usr/fapi2/attribute_service.H) \ - $(addprefix --outFile=,${GENDIR}/${XMLTOHB_SP_ATTRIBUTE_TYPES}) \ - --verbose + $(addprefix --outFile=,${GENDIR}/${XMLTOHB_SP_ATTRIBUTE_TYPES}) # generic XML is created from the generic sources only ${GENDIR}/${XMLTOHB_GENERIC_XML}: \ @@ -409,7 +410,7 @@ $(XMLTOHB_RAN_INDICATION): ${XMLTOHB_COMPILER_SCRIPT} \ $(addprefix --fapi-attributes-xml-file=,${GENDIR}/${XMLTOHB_FAPI_XML}) \ --src-output-dir=$(GENDIR) --img-output-dir=none \ --img-output-file=none - cp ${GENDIR_ERRL}/errludattribute.H ${GENDIR_PLUGINS} + cp ${GENDIR_ERRL}/errludattributeP_gen.H ${GENDIR_PLUGINS} cp ${GENDIR_ERRL}/errludtarget.H ${GENDIR_PLUGINS} touch $(XMLTOHB_RAN_INDICATION) diff --git a/src/usr/testcore/kernel/misctest.H b/src/usr/testcore/kernel/misctest.H index c61741fac..e6322d741 100644 --- a/src/usr/testcore/kernel/misctest.H +++ b/src/usr/testcore/kernel/misctest.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2018 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -64,8 +64,8 @@ class MiscTest : public CxxTest::TestSuite phys = mm_virt_to_phys( heap ); if( phys != (reinterpret_cast<uint64_t>(heap)|hrmor) ) { - TS_FAIL("Unexpected Physical Address for Heap."); TS_TRACE( "heap> virt=%p, phys=%lX", (void*)heap, phys ); + TS_FAIL("Unexpected Physical Address for Heap."); } free(heap); @@ -78,18 +78,23 @@ class MiscTest : public CxxTest::TestSuite } // Verify a MMIO (XSCOM) - TARGETING::EntityPath epath(TARGETING::EntityPath::PATH_PHYSICAL); - epath.addLast(TARGETING::TYPE_SYS,0); - epath.addLast(TARGETING::TYPE_NODE,0); - epath.addLast(TARGETING::TYPE_PROC,1); - TARGETING::Target* l_targ = - TARGETING::targetService().toTarget(epath); - if(l_targ != NULL) + TARGETING::Target * l_masterProc = nullptr; + TARGETING::Target * l_masterNode = nullptr; + bool l_onlyFunctional = true; // Make sure masterproc is functional + errlHndl_t l_err(nullptr); + l_err = TARGETING::targetService().queryMasterProcChipTargetHandle( + l_masterProc, + l_masterNode, + l_onlyFunctional); + + //Validate we found a master proc and + // didn't encounter any error finding it + if(l_masterProc != nullptr && !l_err) { uint64_t xscom = - l_targ->getAttr<TARGETING::ATTR_XSCOM_VIRTUAL_ADDR>(); + l_masterProc->getAttr<TARGETING::ATTR_XSCOM_VIRTUAL_ADDR>(); phys = mm_virt_to_phys( (void*)xscom ); - if( (phys != (1020*TERABYTE+32*GIGABYTE)) + if( (phys != (1020*TERABYTE+32*GIGABYTE)) && (xscom != 0) ) //never got set { TS_FAIL("Unexpected Physical Address for MMIO."); diff --git a/src/usr/testcore/kernel/vmmpagetest.H b/src/usr/testcore/kernel/vmmpagetest.H index 80d2b9c9a..c1c21068b 100644 --- a/src/usr/testcore/kernel/vmmpagetest.H +++ b/src/usr/testcore/kernel/vmmpagetest.H @@ -5,7 +5,9 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2011,2014 */ +/* Contributors Listed Below - COPYRIGHT 2011,2019 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ @@ -50,13 +52,13 @@ class vmmpagetest: public CxxTest::TestSuite rc = mm_alloc_block(iv_mq,reinterpret_cast<void*>(iv_va),iv_size); if (rc != 0) { - TS_FAIL("Unable to allocate block.\n"); + TS_FAIL("Unable to allocate block - rc=%d.\n",rc); } rc = mm_set_permission(reinterpret_cast<void*>(iv_va),iv_size, initPerm); if (rc != 0) { - TS_FAIL("Failed to set block permissions to READ_ONLY.\n"); + TS_FAIL("Failed to set block permissions to READ_ONLY - rc=%d.\n",rc); } task_create(testDaemon, NULL); } @@ -76,7 +78,7 @@ class vmmpagetest: public CxxTest::TestSuite reinterpret_cast<void*>(iv_va),iv_size); if (rc != 0) { - TS_FAIL("Failed to release read pages\n"); + TS_FAIL("Failed to release read pages - rc=%d.\n",rc); } } @@ -86,7 +88,7 @@ class vmmpagetest: public CxxTest::TestSuite if (rc != 0) { TS_FAIL( - "Failed to set WRITE_TRACKED permissions on first page.\n"); + "Failed to set WRITE_TRACKED permissions on first page - rc=%d.\n",rc); } (*(volatile uint64_t *)iv_va) = 0x12345678; sync(); @@ -99,13 +101,13 @@ class vmmpagetest: public CxxTest::TestSuite if (rc != 0) { TS_FAIL( - "Failed to set WRITE_TRACKED permissions on second page.\n"); + "Failed to set WRITE_TRACKED permissions on second page - rc=%d.\n",rc); } rc = mm_remove_pages(FLUSH, reinterpret_cast<void*>(iv_va),iv_size); if (rc != 0) { - TS_FAIL("Failed to flush write tracked pages\n"); + TS_FAIL("Failed to flush write tracked pages - rc=%d.\n",rc); } } @@ -115,7 +117,7 @@ class vmmpagetest: public CxxTest::TestSuite if (rc != 0) { TS_FAIL( - "Failed to set WRITE_TRACKED permissions on first page.\n"); + "Failed to set WRITE_TRACKED permissions on first page - rc=%d.\n",rc); } (*(volatile uint64_t *)(iv_va+2*PAGESIZE)) = 0x33333333; sync(); @@ -126,14 +128,14 @@ class vmmpagetest: public CxxTest::TestSuite if (rc != 0) { TS_FAIL( - "Failed to set WRITE_TRACKED permissions on first page.\n"); + "Failed to set WRITE_TRACKED permissions on first page - rc=%d.\n",rc); } rc = mm_remove_pages(RELEASE, reinterpret_cast<void*>(iv_va),iv_size); if (rc != 0) { - TS_FAIL("Failed to release write track pages\n"); + TS_FAIL("Failed to release write track pages - rc=%d.\n",rc); } } @@ -143,7 +145,7 @@ class vmmpagetest: public CxxTest::TestSuite rc = mm_set_permission(reinterpret_cast<void*>(iv_va+4*PAGESIZE), 3*PAGESIZE, READ_ONLY); if (rc != 0) { - TS_FAIL(" 1 Failed to Update permissions.\n"); + TS_FAIL(" 1 Failed to Update permissions - rc=%d.\n",rc); } // try to write to a read_only page @@ -153,13 +155,13 @@ class vmmpagetest: public CxxTest::TestSuite if ((child != task_wait_tid(child, &status, NULL)) || (status != TASK_STATUS_CRASHED)) { - TS_FAIL("ERROR! Write to READ_ONLY address not caught."); + TS_FAIL("ERROR! Write to READ_ONLY address not caught - status=%d.",status); } rc = mm_set_permission(reinterpret_cast<void*>(iv_va+4*PAGESIZE), 3*PAGESIZE, EXECUTABLE); if (rc != 0) { - TS_FAIL("2 Failed to Update permissions.\n"); + TS_FAIL("2 Failed to Update permissions - rc=%d.\n",rc); } // try to write to an executable page @@ -168,13 +170,13 @@ class vmmpagetest: public CxxTest::TestSuite if ((child != task_wait_tid(child, &status, NULL)) || (status != TASK_STATUS_CRASHED)) { - TS_FAIL("ERROR! Write to EXECUTABLE address not caught."); + TS_FAIL("ERROR! Write to EXECUTABLE address not caught - status=%d",status); } rc = mm_set_permission(reinterpret_cast<void*>(iv_va+4*PAGESIZE), 3*PAGESIZE, NO_ACCESS); if (rc != 0) { - TS_FAIL("3 Failed to Update permissions.\n"); + TS_FAIL("3 Failed to Update permissions - rc=%d.\n",rc); } // try to write to a no access page @@ -183,7 +185,7 @@ class vmmpagetest: public CxxTest::TestSuite if ((child != task_wait_tid(child, &status, NULL)) || (status != TASK_STATUS_CRASHED)) { - TS_FAIL("ERROR! write to a NO_ACCESS addr not caught.\n"); + TS_FAIL("ERROR! write to a NO_ACCESS addr not caught - status=%d",status); } // test that you cannot set WRITABLE and EXECUTABLE permissions @@ -191,13 +193,13 @@ class vmmpagetest: public CxxTest::TestSuite if (rc == 0) { printk("Error .. invalid combination that did not get detected\n"); - TS_FAIL(" ERROR..Failed to detect a bad parm condition.\n"); + TS_FAIL(" ERROR..Failed to detect a bad parm condition - rc=%d.\n",rc); } rc = mm_set_permission(reinterpret_cast<void*>(iv_va+4*PAGESIZE), 3*PAGESIZE, WRITABLE); if (rc != 0) { - TS_FAIL(" 4 Failed to detect a bad parm condition.\n"); + TS_FAIL(" 4 Failed to detect a bad parm condition - rc=%d.\n",rc); } diff --git a/src/usr/testcore/lib/stltest.H b/src/usr/testcore/lib/stltest.H index 31cc3cbe9..34cb64d4a 100644 --- a/src/usr/testcore/lib/stltest.H +++ b/src/usr/testcore/lib/stltest.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2017 */ +/* Contributors Listed Below - COPYRIGHT 2011,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -782,5 +782,35 @@ class STLTest : public CxxTest::TestSuite } } + /// Test std::begin() and std::end() on base-type array + void testBaseTypeBeginEnd() + { + const int MAX_ENTRIES = 1025; + int baseA[MAX_ENTRIES] = {0}; // base-type array + + // Initialize base array to known values + for (int i = 0; i < MAX_ENTRIES; i++) + { + baseA[i] = i; + } + + // use std::begin() and std::end() to copy base-type array to vector + std::vector<int> baseV ( std::begin(baseA), std::end(baseA)); + + if (baseV.size() != MAX_ENTRIES) + { + TS_FAIL("testBaseTypeBeginEnd: expected %d elements, found %d in vector", + MAX_ENTRIES, baseV.size()); + } + + for (int i = 0; i < MAX_ENTRIES; i++) + { + if (baseA[i] != baseV[i]) + { + TS_FAIL("testBaseTypeBeginEnd: No match at index %d (base %d vs vector %d)", + i, baseA[i], baseV[i]); + } + } + } }; #endif diff --git a/src/usr/testcore/rtloader/loader.H b/src/usr/testcore/rtloader/loader.H index c7f1193ef..d9d1448a2 100644 --- a/src/usr/testcore/rtloader/loader.H +++ b/src/usr/testcore/rtloader/loader.H @@ -25,6 +25,7 @@ #ifndef __TESTCORE_RTLOADER_LOADER_H #define __TESTCORE_RTLOADER_LOADER_H + #include <util/align.H> #include <sys/mm.h> #include <targeting/common/targetservice.H> @@ -44,7 +45,6 @@ #include <pnor/ecc.H> #include <ipmi/ipmiif.H> #include <targeting/common/attributeTank.H> -#include <config.h> #include <util/utilrsvdmem.H> #include <sys/misc.h> #include <errno.h> @@ -57,7 +57,10 @@ TRAC_INIT(&g_trac_hbrt, "HBRT_TEST", 12*KILOBYTE); class RuntimeLoaderTest : public CxxTest::TestSuite { - public: +public: + // ===================================================================== + // testLoader + // ===================================================================== void testLoader() { static const uint64_t HEADER_OFFSET = 0x2000; @@ -188,9 +191,12 @@ class RuntimeLoaderTest : public CxxTest::TestSuite } #endif - } + } // end testLoader private: + // ===================================================================== + // tearDown + // ===================================================================== void tearDown() { if (cv_hb_data_addr != 0) @@ -218,8 +224,11 @@ class RuntimeLoaderTest : public CxxTest::TestSuite TRACFCOMP( g_trac_hbrt, "tearDown(): skipping unmap hb_data virt addr"); } - } + } // end tearDown + // ===================================================================== + // callViaCtr + // ===================================================================== uint64_t callViaCtr(uint64_t entry, void* param0, void* param1) { register uint64_t result = 0; @@ -232,23 +241,35 @@ class RuntimeLoaderTest : public CxxTest::TestSuite "r10","r11"); // TODO: Need to double check the ABI here. return result; - } + } // end callViaCtr + // ===================================================================== + // rt_puts + // ===================================================================== static void rt_puts(const char* str) { TRACFCOMP(g_trac_hbrt, "HBRT TRACE: %s", str); } + // ===================================================================== + // rt_setPageExecute + // ===================================================================== static int rt_setPageExecute(void* addr) { return mm_set_permission(addr, PAGESIZE, EXECUTABLE); } + // ===================================================================== + // rt_assert + // ===================================================================== static void rt_assert() { assert(false); } + // ===================================================================== + // rt_scom_read + // ===================================================================== static int rt_scom_read(uint64_t chipid, uint64_t addr, void* data) @@ -284,8 +305,11 @@ class RuntimeLoaderTest : public CxxTest::TestSuite } return rc; - } + } // end rt_scom_read + // ===================================================================== + // rt_scom_write + // ===================================================================== static int rt_scom_write(uint64_t chipid, uint64_t addr, void* data) @@ -313,12 +337,11 @@ class RuntimeLoaderTest : public CxxTest::TestSuite } return rc; - } - - typedef std::pair<uint64_t,uint64_t> SCOM_KEY; - typedef std::map<SCOM_KEY,uint64_t> SCOM_MAP; - static SCOM_MAP cv_scomMap; + } // end rt_scom_write + // ===================================================================== + // rt_logErr + // ===================================================================== static int rt_logErr(uint32_t plid, uint32_t data_len, void * data) @@ -340,10 +363,11 @@ class RuntimeLoaderTest : public CxxTest::TestSuite errlCommit(err,CXXTEST_COMP_ID); return rc; - } - - static std::map<void*, UtilLidMgr*> cv_loadedLids; + } // end rt_logErr + // ===================================================================== + // rt_lid_load + // ===================================================================== static int rt_lid_load(uint32_t lid, void** buffer, size_t* size) { errlHndl_t l_errl = NULL; @@ -375,9 +399,11 @@ class RuntimeLoaderTest : public CxxTest::TestSuite cv_loadedLids[*buffer] = lidmgr; return 0; } + } // end rt_lid_load - } - + // ===================================================================== + // rt_lid_unload + // ===================================================================== static int rt_lid_unload(void* buffer) { UtilLidMgr* lidmgr = cv_loadedLids[buffer]; @@ -389,7 +415,9 @@ class RuntimeLoaderTest : public CxxTest::TestSuite return 0; } - //-------------------------------------------------------------------- + // ===================================================================== + // rt_get_reserved_mem + // ===================================================================== static uint64_t rt_get_reserved_mem(const char* i_region, uint32_t i_instance) { @@ -401,6 +429,9 @@ class RuntimeLoaderTest : public CxxTest::TestSuite return 0; } + // ===================================================================== + // rt_get_hb_data + // ===================================================================== static uint64_t rt_get_hb_data(uint32_t i_instance) { TRACFCOMP( g_trac_hbrt, @@ -416,7 +447,6 @@ class RuntimeLoaderTest : public CxxTest::TestSuite return cv_hb_data_addr; } - uint64_t l_physical_addr = cpu_spr_value(CPU_SPR_HRMOR) + VMM_HB_DATA_TOC_START_OFFSET; @@ -469,9 +499,11 @@ class RuntimeLoaderTest : public CxxTest::TestSuite i_instance, cv_hb_data_addr); return cv_hb_data_addr; - } - + } // end rt_get_hb_data + // ===================================================================== + // find_sectionId + // ===================================================================== static PNOR::SectionId find_sectionId (const char* i_partitionName) { PNOR::SectionId l_id = PNOR::INVALID_SECTION; @@ -485,8 +517,11 @@ class RuntimeLoaderTest : public CxxTest::TestSuite } } return l_id; - } + } // end find_sectionId + // ===================================================================== + // rt_pnor_read + // ===================================================================== static int rt_pnor_read (uint32_t i_proc, const char* i_partitionName, uint64_t i_offset, void* o_data, size_t i_sizeBytes) { @@ -559,9 +594,11 @@ class RuntimeLoaderTest : public CxxTest::TestSuite } TRACFCOMP(g_trac_hbrt, EXIT_MRK"rt_pnor_read"); return rc; - } - + } // end rt_pnor_read + // ===================================================================== + // rt_pnor_write + // ===================================================================== static int rt_pnor_write(uint32_t i_proc, const char* i_partitionName, uint64_t i_offset, void* i_data, size_t i_sizeBytes) { @@ -624,9 +661,11 @@ class RuntimeLoaderTest : public CxxTest::TestSuite } TRACFCOMP(g_trac_hbrt, EXIT_MRK"rt_pnor_write"); return rc; - } + } // end rt_pnor_write - //-------------------------------------------------------------------- + // ===================================================================== + // rt_get_comm + // ===================================================================== static uint64_t rt_get_comm(uint32_t i_instance) { if (cv_comm_addr != 0) @@ -677,9 +716,11 @@ class RuntimeLoaderTest : public CxxTest::TestSuite "calculated cv_comm_addr:%lld", cv_comm_addr); return cv_comm_addr; - } + } // end rt_get_comm - //-------------------------------------------------------------------- + // ===================================================================== + // rt_ipmi_msg + // ===================================================================== static int rt_ipmi_msg(uint8_t netfn, uint8_t cmd, void *tx_buf, size_t tx_size, void *rx_buf, size_t *rx_size) @@ -704,9 +745,11 @@ class RuntimeLoaderTest : public CxxTest::TestSuite } TRACFCOMP(g_trac_hbrt, EXIT_MRK"rt_ipmi_msg"); return l_plid; - } + } // end rt_ipmi_msg - //-------------------------------------------------------------------- + // ===================================================================== + // rt_hcode_update + // ===================================================================== static int rt_hcode_update( uint64_t i_chipId, uint32_t i_section, uint32_t i_operation, @@ -721,291 +764,677 @@ class RuntimeLoaderTest : public CxxTest::TestSuite return 0; } - //-------------------------------------------------------------------- - static int rt_firmware_request(uint64_t i_reqLen, void *i_req, - uint64_t* o_respLen, void *o_resp ) + // ===================================================================== + // rt_firmware_request + // ===================================================================== + static int rt_firmware_request(uint64_t i_reqLen, void *i_req, + uint64_t* o_respLen, void *o_resp ) { + TRACFCOMP(g_trac_hbrt, ENTER_MRK"rt_firmware_request: " + "request length:%d, request ptr:%p, " + "response length:%d, response ptr:%p", + i_reqLen, i_req, *o_respLen, o_resp ); + + if ( (i_req == nullptr) || + (o_respLen == nullptr) || + (o_resp == nullptr) ) + { + TS_FAIL("rt_firmware_request: FAILED: Received bad input - " + "either request message, response length " + "or response message is NULL") + + return -EINVAL; + } + + if ( (*o_respLen != i_reqLen) && + (*o_respLen < (hostInterfaces::HBRT_FW_MSG_BASE_SIZE + + sizeof(hostInterfaces::hbrt_fw_msg))) ) + { + TS_FAIL("rt_firmware_request: FAILED: Response length(%d) " + "needs to be at a minimum(%d), or equal to " + "request length(%d)", + *o_respLen, + (hostInterfaces::HBRT_FW_MSG_BASE_SIZE + + sizeof(hostInterfaces::hbrt_fw_msg)), + i_reqLen); + + return -EINVAL; + } + size_t retVal = 0; + do { - if (i_req == nullptr || - o_respLen == nullptr || - o_resp == nullptr) - { - retVal = -EINVAL; - break; - } + // Cast the input to the type of data that it is + hostInterfaces::hbrt_fw_msg* l_req_fw_msg = + reinterpret_cast<hostInterfaces::hbrt_fw_msg*>(i_req); + hostInterfaces::hbrt_fw_msg* l_resp_fw_msg = + reinterpret_cast<hostInterfaces::hbrt_fw_msg*>(o_resp); - hostInterfaces::hbrt_fw_msg* l_req_fw_msg = - (hostInterfaces::hbrt_fw_msg*) i_req; - hostInterfaces::hbrt_fw_msg* l_resp_fw_msg = - (hostInterfaces::hbrt_fw_msg*) o_resp; - - if (hostInterfaces::HBRT_FW_MSG_TYPE_REQ_HCODE_UPDATE + if (hostInterfaces::HBRT_FW_MSG_TYPE_REQ_HCODE_UPDATE == l_req_fw_msg->io_type) - { - if (i_reqLen < (hostInterfaces::HBRT_FW_MSG_BASE_SIZE + - sizeof(l_req_fw_msg->req_hcode_update))) - { - retVal = -EINVAL; - break; - } - - if (*o_respLen < (hostInterfaces::HBRT_FW_MSG_BASE_SIZE + - sizeof(l_resp_fw_msg->resp_generic))) - { - retVal = -EINVAL; - break; - } - - TRACFCOMP(g_trac_hbrt, - "rt_firmware_request for HCODE SCOM update: " - "type:%d, chipId:0x%X, section:%d, " - "operation:%d, scomAddr:0x%X scomData:0x%X", - l_req_fw_msg->io_type, - l_req_fw_msg->req_hcode_update.i_chipId, - l_req_fw_msg->req_hcode_update.i_section, - l_req_fw_msg->req_hcode_update.i_operation, - l_req_fw_msg->req_hcode_update.i_scomAddr, - l_req_fw_msg->req_hcode_update.i_scomData); - - l_resp_fw_msg->io_type = - hostInterfaces::HBRT_FW_MSG_TYPE_RESP_GENERIC; - - // dummy return value for testing - l_resp_fw_msg->resp_generic.o_status = 264; - - retVal = 1; // just return 1 for testing - } - else if (hostInterfaces::HBRT_FW_MSG_TYPE_ERROR_LOG + { + retVal = testFirmwareRequestHcodeUpdate(i_reqLen, + l_req_fw_msg, + *o_respLen, + l_resp_fw_msg ); + } + else if (hostInterfaces::HBRT_FW_MSG_TYPE_ERROR_LOG == l_req_fw_msg->io_type) - { - if (i_reqLen < (hostInterfaces::HBRT_FW_MSG_BASE_SIZE + - sizeof(l_req_fw_msg->error_log))) - { - retVal = -EINVAL; - break; - } - - if (i_reqLen < (hostInterfaces::HBRT_FW_MSG_BASE_SIZE + - sizeof(l_req_fw_msg->error_log) + - l_req_fw_msg->error_log.i_errlSize - 1)) - { - retVal = -EINVAL; - break; - } - - if (*o_respLen < (hostInterfaces::HBRT_FW_MSG_BASE_SIZE + - sizeof(l_resp_fw_msg->resp_generic))) - { - retVal = -EINVAL; - break; - } - - TRACFCOMP(g_trac_hbrt, - "rt_firmware_request for error log: " - "type:%d, plid:0x%08x, size:%d, data:0x%02x", - l_req_fw_msg->io_type, - l_req_fw_msg->error_log.i_plid, - l_req_fw_msg->error_log.i_errlSize, - l_req_fw_msg->error_log.i_data); - - l_resp_fw_msg->io_type = - hostInterfaces::HBRT_FW_MSG_TYPE_RESP_GENERIC; - - // dummy return value for testing - l_resp_fw_msg->resp_generic.o_status = 20; - - retVal = 0; // just return 0 for testing - } - else if (hostInterfaces::HBRT_FW_MSG_HBRT_FSP_REQ + { + retVal = testFirmwareRequestErrLogToFsp(i_reqLen, + l_req_fw_msg, + *o_respLen, + l_resp_fw_msg ); + } + else if (hostInterfaces::HBRT_FW_MSG_HBRT_FSP_REQ == l_req_fw_msg->io_type) - { - if (i_reqLen < (hostInterfaces::HBRT_FW_MSG_BASE_SIZE + - sizeof(l_req_fw_msg->generic_msg))) - { - retVal = -EINVAL; - break; - } - - if (*o_respLen < (hostInterfaces::HBRT_FW_MSG_BASE_SIZE + - sizeof(l_resp_fw_msg->generic_msg))) - { - retVal = -EINVAL; - break; - } - - if (i_reqLen != *o_respLen) - { - retVal = -EINVAL; - break; - } - - uint32_t* l_data = - (uint32_t*) &(l_req_fw_msg->generic_msg.data); - TRACFCOMP(g_trac_hbrt, - "rt_firmware_request request: " - "type:%d, magic:0x%.8X, dataSize:%d, " - "structVer:0x%.8X, seqnum:%d, msgq:0x%.8X, " - "msgType:0x%.8X, __req:%d, __onlyError:%d, " - "data:0x%.8X, plid:0x%.8X, huid:0x%.8X", - l_req_fw_msg->io_type, - l_req_fw_msg->generic_msg.magic, - l_req_fw_msg->generic_msg.dataSize, - l_req_fw_msg->generic_msg.structVer, - l_req_fw_msg->generic_msg.seqnum, - l_req_fw_msg->generic_msg.msgq, - l_req_fw_msg->generic_msg.msgType, - l_req_fw_msg->generic_msg.__req, - l_req_fw_msg->generic_msg.__onlyError, - l_req_fw_msg->generic_msg.data, - l_data[0], - l_data[1]); - - // Simple map of SCOM addresses to values, this ignores - // the target (or huid). - static std::map<uint64_t, uint64_t> l_scomCache; - - // Used to give unique, spoofed SCOM values - static uint64_t l_fakeVal = 0x11; - - // Simulate response message from FSP - l_resp_fw_msg->io_type = + { + if (i_reqLen < (hostInterfaces::HBRT_FW_MSG_BASE_SIZE + + sizeof(l_req_fw_msg->generic_msg))) + { + TS_FAIL("rt_firmware_request: FAILED: Generic FSP " + "Message' response length(%d) needs to be " + "at a minimum(%d)", + *o_respLen, + (hostInterfaces::HBRT_FW_MSG_BASE_SIZE + + sizeof(l_req_fw_msg->generic_msg)) ); + + retVal = -EINVAL; + break; + } + + TRACDCOMP(g_trac_hbrt, + "rt_firmware_request: Generic FSP Message' " + "Request data set 1/2: " + "type:%d, magic:0x%.8X, dataSize:%d, " + "structVer:0x%.8X, seqnum:%d, msgq:0x%.8X", + l_req_fw_msg->io_type, + l_req_fw_msg->generic_msg.magic, + l_req_fw_msg->generic_msg.dataSize, + l_req_fw_msg->generic_msg.structVer, + l_req_fw_msg->generic_msg.seqnum, + l_req_fw_msg->generic_msg.msgq); + + TRACDCOMP(g_trac_hbrt, + "rt_firmware_request: Generic FSP Message' " + "Request data set 2/2: " + "msgType:0x%.8X, __req:%d, " + "__onlyError:%d, data:0x%.8X", + l_req_fw_msg->generic_msg.msgType, + l_req_fw_msg->generic_msg.__req, + l_req_fw_msg->generic_msg.__onlyError, + l_req_fw_msg->generic_msg.data); + + // Simulate response message from FSP + l_resp_fw_msg->io_type = hostInterfaces::HBRT_FW_MSG_HBRT_FSP_RESP; - l_resp_fw_msg->generic_msg.magic = + l_resp_fw_msg->generic_msg.magic = GenericFspMboxMessage_t::MAGIC_NUMBER; - l_resp_fw_msg->generic_msg.structVer = + l_resp_fw_msg->generic_msg.structVer = l_req_fw_msg->generic_msg.structVer; - l_resp_fw_msg->generic_msg.seqnum = + l_resp_fw_msg->generic_msg.seqnum = l_req_fw_msg->generic_msg.seqnum + 1; - l_resp_fw_msg->generic_msg.msgq = + l_resp_fw_msg->generic_msg.msgq = l_req_fw_msg->generic_msg.msgq; - l_resp_fw_msg->generic_msg.msgType = + l_resp_fw_msg->generic_msg.msgType = l_req_fw_msg->generic_msg.msgType; - l_resp_fw_msg->generic_msg.__req = + l_resp_fw_msg->generic_msg.__req = GenericFspMboxMessage_t::RESPONSE; - l_resp_fw_msg->generic_msg.__onlyError = + l_resp_fw_msg->generic_msg.__onlyError = GenericFspMboxMessage_t::NOT_ERROR_ONLY; - switch (l_req_fw_msg->generic_msg.msgType) - { - case GenericFspMboxMessage_t::MSG_SINGLE_SCOM_OP: - { - SingleScomOpHbrtFspData_t* l_req_fspData = - reinterpret_cast<SingleScomOpHbrtFspData_t*> - (&(l_req_fw_msg->generic_msg.data)); - SingleScomOpHbrtFspData_t* l_resp_fspData = - reinterpret_cast<SingleScomOpHbrtFspData_t*> - (&(l_resp_fw_msg->generic_msg.data)); - - l_resp_fw_msg->generic_msg.dataSize = - GENERIC_FSP_MBOX_MESSAGE_BASE_SIZE + - sizeof(SingleScomOpHbrtFspData_t); - - auto l_scomAddr = l_req_fspData->scom_addr; - auto targ = l_scomCache.find(l_scomAddr); - if (targ == l_scomCache.end()) // need to create - { // a cache entry - l_scomCache[l_scomAddr] = l_fakeVal++; - } - - l_resp_fspData->scom_op = l_req_fspData->scom_op; - l_resp_fspData->huid = l_req_fspData->huid; - l_resp_fspData->scom_addr = l_req_fspData->scom_addr; - if (l_resp_fspData->scom_op == DeviceFW::WRITE) - { - l_scomCache[l_scomAddr] = - l_req_fspData->scom_data; - } - l_resp_fspData->scom_data = l_scomCache[l_scomAddr]; - retVal = 0; - break; - } - case GenericFspMboxMessage_t::MSG_MULTI_SCOM_OP: - { - MultiScomReadHbrtFspData_t* l_req_fspData = - reinterpret_cast<MultiScomReadHbrtFspData_t*> - (&(l_req_fw_msg->generic_msg.data)); - MultiScomReadHbrtFspData_t* l_resp_fspData = - reinterpret_cast<MultiScomReadHbrtFspData_t*> - (&(l_resp_fw_msg->generic_msg.data)); - - l_resp_fw_msg->generic_msg.dataSize = - GENERIC_FSP_MBOX_MESSAGE_BASE_SIZE + - sizeof(MultiScomReadHbrtFspData_t) + - ((l_req_fspData->scom_num - 1) * sizeof(uint64_t)); - - auto l_scomAddrs = - static_cast<uint64_t *> - (&l_req_fspData->scom_data); - auto l_scomData = - static_cast<uint64_t *> - (&l_resp_fspData->scom_data); - - l_resp_fspData->huid = l_req_fspData->huid; - l_resp_fspData->scom_num = l_req_fspData->scom_num; - for (int i = 0;i < l_resp_fspData->scom_num;++i) - { - auto targ = l_scomCache.find(l_scomAddrs[i]); - if (targ == l_scomCache.end()) // need to create - { // a cache entry - l_scomCache[l_scomAddrs[i]] = l_fakeVal++; - } - l_scomData[i] = l_scomCache[l_scomAddrs[i]]; - } - retVal = 0; - break; - } - default: - // random testing data - struct - { - uint32_t plid; - uint32_t huid; - } l_resp_data; - - l_resp_fw_msg->generic_msg.dataSize = - sizeof(l_resp_fw_msg->generic_msg); - - l_resp_data.plid = 0x60; - l_resp_data.huid = 0x70; - memcpy(&(l_resp_fw_msg->generic_msg.data), - &(l_resp_data), - sizeof(l_resp_fw_msg->generic_msg.data)); - retVal = 5; - break; - } - - TRACFCOMP(g_trac_hbrt, - "rt_firmware_request response: " - "type:%d, magic:0x%.8X, dataSize:%d, structVer:0x%.8X, " - "seqnum:%d, msgq:0x%.8X, msgType:0x%.8X, __req:%d, " - "__onlyError:%d, data:0x%.8X, plid:0x%.8X, huid:0x%.8X, " - "retVal=%d", - l_resp_fw_msg->io_type, - l_resp_fw_msg->generic_msg.magic, - l_resp_fw_msg->generic_msg.dataSize, - l_resp_fw_msg->generic_msg.structVer, - l_resp_fw_msg->generic_msg.seqnum, - l_resp_fw_msg->generic_msg.msgq, - l_resp_fw_msg->generic_msg.msgType, - l_resp_fw_msg->generic_msg.__req, - l_resp_fw_msg->generic_msg.__onlyError, - l_resp_fw_msg->generic_msg.data, - l_resp_fw_msg->generic_msg.data >> 32, - 0x0000FFFF & l_resp_fw_msg->generic_msg.data, - retVal); - } - else - { - TRACFCOMP(g_trac_hbrt, - "rt_firmware_request: unrecognized request, type=%d", - l_req_fw_msg->io_type); + + // Check the individual message types + switch (l_req_fw_msg->generic_msg.msgType) + { + case GenericFspMboxMessage_t::MSG_SINGLE_SCOM_OP: + { + testFirmwareRequestSingleScomOperation(i_reqLen, + l_req_fw_msg, + *o_respLen, + l_resp_fw_msg); + break; + } + case GenericFspMboxMessage_t::MSG_MULTI_SCOM_OP: + { + testFirmwareRequestMultipleScomOperation(i_reqLen, + l_req_fw_msg, + *o_respLen, + l_resp_fw_msg); + break; + } + case GenericFspMboxMessage_t::MSG_ATTR_WRITE_OP: + { + testFirmwareRequestSendAttributes(i_reqLen, + l_req_fw_msg, + *o_respLen, + l_resp_fw_msg); + break; + } + case GenericFspMboxMessage_t::MSG_SBE_ERROR: + { + retVal = testFirmwareRequestSbeRetry(i_reqLen, + l_req_fw_msg, + *o_respLen, + l_resp_fw_msg); + break; + } + + default: + { + TS_FAIL("rt_firmware_request: FAILED: Generic FSP " + "unrecognized test request, type(0x%X). " + "Need to add a test case for this " + "generic FSP firmware request type", + l_req_fw_msg->generic_msg.msgType); + break; + } + } // end switch (l_req_fw_msg->generic_msg.msgType) + + TRACDCOMP(g_trac_hbrt, + "rt_firmware_request: Generic FSP Message' " + "Response data set 1/2: " + "type:%d, magic:0x%.8X, dataSize:%d, " + "structVer:0x%.8X, seqnum:%d, msgq:0x%.8X", + l_resp_fw_msg->io_type, + l_resp_fw_msg->generic_msg.magic, + l_resp_fw_msg->generic_msg.dataSize, + l_resp_fw_msg->generic_msg.structVer, + l_resp_fw_msg->generic_msg.seqnum, + l_resp_fw_msg->generic_msg.msgq); + + TRACDCOMP(g_trac_hbrt, + "rt_firmware_request: Generic FSP Message' " + "Response data set 2/2: " + "msgType:0x%.8X, __req:%d, __onlyError:%d, " + "data:0x%.8X", + l_resp_fw_msg->generic_msg.msgType, + l_resp_fw_msg->generic_msg.__req, + l_resp_fw_msg->generic_msg.__onlyError, + l_resp_fw_msg->generic_msg.data); + + } // end else if (hostInterfaces::HBRT_FW_MSG_HBRT_FSP_REQ + else + { + TS_FAIL("rt_firmware_request: FAILED: " + "unrecognized test request, type(0x%X). Need to " + "add a test case for this firmware request type", + l_req_fw_msg->io_type); } } while (0) ; + TRACFCOMP(g_trac_hbrt, EXIT_MRK"rt_firmware_request: returning %d", + retVal ); + return retVal; - } + } // end static int rt_firmware_request ... + + /// Firmware Request Test Helper Functions + // ===================================================================== + // testFirmwareRequestSbeRetry + // ===================================================================== + static size_t testFirmwareRequestSbeRetry( + uint64_t i_reqLen, + hostInterfaces::hbrt_fw_msg* i_req_fw_msg, + uint64_t i_respLen, + hostInterfaces::hbrt_fw_msg* i_resp_fw_msg ) + { + TRACFCOMP(g_trac_hbrt, ENTER_MRK + "rt_firmware_request::testFirmwareRequestSbeRetry"); + + struct + { + uint32_t plid; + uint32_t huid; + } l_resp_data; + + i_resp_fw_msg->generic_msg.dataSize = + sizeof(i_resp_fw_msg->generic_msg); + + l_resp_data.plid = 0x60; + l_resp_data.huid = 0x70; + memcpy(&(i_resp_fw_msg->generic_msg.data), + &(l_resp_data), + sizeof(i_resp_fw_msg->generic_msg.data)); + + TRACFCOMP(g_trac_hbrt, EXIT_MRK + "rt_firmware_request::testFirmwareRequestSbeRetry"); + + return 5; + } // end testFirmwareRequestSbeRetry + + // ===================================================================== + // testFirmwareRequestSingleScomOperation + // ===================================================================== + static void testFirmwareRequestSingleScomOperation( + uint64_t i_reqLen, + hostInterfaces::hbrt_fw_msg* i_req_fw_msg, + uint64_t i_respLen, + hostInterfaces::hbrt_fw_msg* i_resp_fw_msg ) + { + TRACFCOMP(g_trac_hbrt, ENTER_MRK + "rt_firmware_request::testFirmwareRequestSingleScomOperation"); + + // Simple map of SCOM addresses to values, this ignores + // the target (or huid). + static std::map<uint64_t, uint64_t> l_scomCache; + + // Used to give unique, spoofed SCOM values + static uint64_t l_fakeVal = 0x11; + + SingleScomOpHbrtFspData_t* l_req_fspData = + reinterpret_cast<SingleScomOpHbrtFspData_t*> + (&(i_req_fw_msg->generic_msg.data)); + + SingleScomOpHbrtFspData_t* l_resp_fspData = + reinterpret_cast<SingleScomOpHbrtFspData_t*> + (&(i_resp_fw_msg->generic_msg.data)); + + i_resp_fw_msg->generic_msg.dataSize = + GENERIC_FSP_MBOX_MESSAGE_BASE_SIZE + + sizeof(SingleScomOpHbrtFspData_t); + + auto l_scomAddr = l_req_fspData->scom_addr; + auto targ = l_scomCache.find(l_scomAddr); + if (targ == l_scomCache.end()) // need to create + { // a cache entry + l_scomCache[l_scomAddr] = l_fakeVal++; + } + + l_resp_fspData->scom_op = l_req_fspData->scom_op; + l_resp_fspData->huid = l_req_fspData->huid; + l_resp_fspData->scom_addr = l_req_fspData->scom_addr; + + if (l_resp_fspData->scom_op == DeviceFW::WRITE) + { + l_scomCache[l_scomAddr] = + l_req_fspData->scom_data; + } + l_resp_fspData->scom_data = l_scomCache[l_scomAddr]; + + TRACFCOMP(g_trac_hbrt, EXIT_MRK + "rt_firmware_request::testFirmwareRequestSingleScomOperation"); + } // end testFirmwareRequestSingleScomOperation + + // ===================================================================== + // testFirmwareRequestMultipleScomOperation + // ===================================================================== + static void testFirmwareRequestMultipleScomOperation( + uint64_t i_reqLen, + hostInterfaces::hbrt_fw_msg* i_req_fw_msg, + uint64_t i_respLen, + hostInterfaces::hbrt_fw_msg* i_resp_fw_msg ) + { + TRACFCOMP(g_trac_hbrt, ENTER_MRK + "rt_firmware_request::testFirmwareRequestMultipleScomOperation"); + + // Simple map of SCOM addresses to values, this ignores + // the target (or huid). + static std::map<uint64_t, uint64_t> l_scomCache; + + // Used to give unique, spoofed SCOM values + static uint64_t l_fakeVal = 0x11; + + MultiScomReadHbrtFspData_t* l_req_fspData = + reinterpret_cast<MultiScomReadHbrtFspData_t*> + (&(i_req_fw_msg->generic_msg.data)); + MultiScomReadHbrtFspData_t* l_resp_fspData = + reinterpret_cast<MultiScomReadHbrtFspData_t*> + (&(i_resp_fw_msg->generic_msg.data)); + + i_resp_fw_msg->generic_msg.dataSize = + GENERIC_FSP_MBOX_MESSAGE_BASE_SIZE + + sizeof(MultiScomReadHbrtFspData_t) + + ((l_req_fspData->scom_num - 1) * sizeof(uint64_t)); + + auto l_scomAddrs = + static_cast<uint64_t *> + (&l_req_fspData->scom_data); + auto l_scomData = + static_cast<uint64_t *> + (&l_resp_fspData->scom_data); + + l_resp_fspData->huid = l_req_fspData->huid; + l_resp_fspData->scom_num = l_req_fspData->scom_num; + for (int i = 0;i < l_resp_fspData->scom_num;++i) + { + auto targ = l_scomCache.find(l_scomAddrs[i]); + if (targ == l_scomCache.end()) // need to create + { // a cache entry + l_scomCache[l_scomAddrs[i]] = l_fakeVal++; + } + l_scomData[i] = l_scomCache[l_scomAddrs[i]]; + } + + TRACFCOMP(g_trac_hbrt, EXIT_MRK + "rt_firmware_request::testFirmwareRequestMultipleScomOperation"); + } // end testFirmwareRequestMultipleScomOperation + + // ===================================================================== + // testFirmwareRequestSendAttributes + // ===================================================================== + static void testFirmwareRequestSendAttributes( + uint64_t i_reqLen, + hostInterfaces::hbrt_fw_msg* i_req_fw_msg, + uint64_t i_respLen, + hostInterfaces::hbrt_fw_msg* i_resp_fw_msg ) + { + TRACFCOMP(g_trac_hbrt, ENTER_MRK + "rt_firmware_request::testFirmwareRequestSendAttributes"); + + uint32_t l_dataSize = i_reqLen - + ( hostInterfaces::HBRT_FW_MSG_BASE_SIZE + + sizeof(i_req_fw_msg->generic_msg.data) + + sizeof(AttributeSetter_t) ); + + if (l_dataSize < 0) + { + TS_FAIL("rt_firmware_request::" + "testFirmwareRequestSendAttributes: FAILED: " + "Size of the AttributeSetter_t data is " + "negative(%d)", l_dataSize); + return; + } + + // Get a handle to the AttributeSetter_t + AttributeSetter_t* l_attributeSetter = + reinterpret_cast<AttributeSetter_t*> + (&(i_req_fw_msg->generic_msg.data)); + // Get a handle to the Attributes Data + uint8_t* l_attributeData = reinterpret_cast<uint8_t*> + (l_attributeSetter->iv_attrData); + + // Create some Attributes to populate with serialized data and + // compare to expected values + TARGETING::AttributeTank::Attribute l_sentAttribute, + l_expectedAttribute; + uint32_t l_deserializedDataSize(0); + + // Create a buffer to be used to test against + uint32_t l_bufferSize(3); + uint8_t l_buffer[l_bufferSize]; + + // Populate buffer with known values + l_buffer[0] = 0xAA; + l_buffer[1] = 0xBB; + l_buffer[2] = 0xCC; + + // Iterate thru the attributes and compare to expected values + for (uint16_t i = 0; i < l_attributeSetter->iv_numAttributes; ++i) + { + // Deserialize the data, if possible + l_deserializedDataSize = l_sentAttribute.deserialize + (l_attributeData, l_dataSize); + + if (!l_deserializedDataSize) + { + TS_FAIL("rt_firmware_request::" + "testFirmwareRequestSendAttributes: FAILED: " + "deserialization of attribute failed") + return; + } + + if (0 == i) + { + // Verify first deserialized Attribute + if (!compareAttributeHeader(&l_sentAttribute, + &l_expectedAttribute)) + { + TS_FAIL("rt_firmware_request::" + "testFirmwareRequestSendAttributes: " + "Test 1 FAILED: sent Attribute does not match " + "expected Values"); + } + + // Prep for next test + l_expectedAttribute.setId(0x1001); + l_expectedAttribute.setTargetType(0x2002); + l_expectedAttribute.setPosition(0x3003); + l_expectedAttribute.setUnitPosition(0x4); + l_expectedAttribute.setNode(0x5); + l_expectedAttribute.setFlags(0x6); + } // end if (0 == i) + else if (1 == i) + { + // Verify second deserialized Attribute + if (!compareAttributeHeader(&l_sentAttribute, + &l_expectedAttribute)) + { + TS_FAIL("rt_firmware_request::" + "testFirmwareRequestSendAttributes: " + "Test 2 FAILED: sent Attribute does not match " + "expected Values"); + } + + // Prep for next test + l_expectedAttribute.setValue(l_buffer, 1); + } // end else if (1 == i) + else if (2 == i) + { + // Verify third deserialized Attribute + if (!compareAttributeHeader(&l_sentAttribute, + &l_expectedAttribute)) + { + TS_FAIL("rt_firmware_request::" + "testFirmwareRequestSendAttributes: " + "Test 3 FAILED: sent Attribute does not match " + "expected Values"); + } + + if (!compareAttributeValues(&l_sentAttribute, + &l_expectedAttribute)) + { + TS_FAIL("rt_firmware_request::" + "testFirmwareRequestSendAttributes: " + "Test 3 FAILED: sent Attribute Values does not " + "match expected Values"); + } + + // Prep for next test + l_buffer[0] = 0xDD; + l_expectedAttribute.setValue(l_buffer, l_bufferSize); + } // end else if (2 == i) + else if (3 == i) + { + // Verify fourth deserialized Attribute + if (!compareAttributeHeader(&l_sentAttribute, + &l_expectedAttribute)) + { + TS_FAIL("rt_firmware_request::" + "testFirmwareRequestSendAttributes: " + "Test 4 FAILED: sent Attribute does not match " + "expected Values"); + } + + if (!compareAttributeValues(&l_sentAttribute, + &l_expectedAttribute)) + { + TS_FAIL("rt_firmware_request::" + "testFirmwareRequestSendAttributes: " + "Test 4 FAILED: sent Attribute Values does not " + "match expected Values"); + } + } // end else if (3 == i) + + // Decrement/increment our counters/pointers + l_dataSize -= l_deserializedDataSize; + l_attributeData += l_deserializedDataSize; + + } // end for (uint16_t i = 0; ... + + TRACFCOMP(g_trac_hbrt, EXIT_MRK + "rt_firmware_request::testFirmwareRequestSendAttributes"); + } // end testFirmwareRequestSendAttributes + + // ===================================================================== + // testFirmwareRequestErrLogToFsp + // ===================================================================== + static size_t testFirmwareRequestErrLogToFsp( + uint64_t i_reqLen, + hostInterfaces::hbrt_fw_msg* i_req_fw_msg, + uint64_t i_respLen, + hostInterfaces::hbrt_fw_msg* i_resp_fw_msg ) + + { + + TRACFCOMP(g_trac_hbrt, ENTER_MRK + "rt_firmware_request::testFirmwareRequestErrLogToFsp"); + + if (i_reqLen < (hostInterfaces::HBRT_FW_MSG_BASE_SIZE + + sizeof(i_req_fw_msg->error_log))) + { + TS_FAIL("rt_firmware_request::testFirmwareRequestErrLogToFsp: " + "FAILED: Request length(%d) needs to be at a " + "minimum(%d)", + i_reqLen, + (hostInterfaces::HBRT_FW_MSG_BASE_SIZE + + sizeof(i_req_fw_msg->error_log)) ); + return -EINVAL; + } + + if (i_reqLen < (hostInterfaces::HBRT_FW_MSG_BASE_SIZE + + sizeof(i_req_fw_msg->error_log) + + i_req_fw_msg->error_log.i_errlSize - 1)) + { + TS_FAIL("rt_firmware_request::testFirmwareRequestErrLogToFsp: " + "FAILED: Request length(%d) needs to be at a " + "minimum(%d)", + i_reqLen, + (hostInterfaces::HBRT_FW_MSG_BASE_SIZE + + sizeof(i_req_fw_msg->error_log) + + i_req_fw_msg->error_log.i_errlSize - 1) ); + return -EINVAL; + } + + if ( (0x300 != i_req_fw_msg->error_log.i_plid) || + ( 1 != i_req_fw_msg->error_log.i_errlSize) || + ( 0xAA != i_req_fw_msg->error_log.i_data) ) + { + TS_FAIL("rt_firmware_request::testFirmwareRequestErrLogToFsp: " + "FAILED: Loader received incorrect data: type:%d, " + "plid:0x%08x, size:%d, data:0x%02x", + i_req_fw_msg->io_type, + i_req_fw_msg->error_log.i_plid, + i_req_fw_msg->error_log.i_errlSize, + i_req_fw_msg->error_log.i_data); + } + + i_resp_fw_msg->io_type = + hostInterfaces::HBRT_FW_MSG_TYPE_RESP_GENERIC; + + // dummy return value for testing + i_resp_fw_msg->resp_generic.o_status = 20; + + TRACFCOMP(g_trac_hbrt, EXIT_MRK + "rt_firmware_request::testFirmwareRequestErrLogToFsp"); + + // just return 0 for testing + return 0; + } // end testFirmwareRequestErrLogToFsp + + // ===================================================================== + // testFirmwareRequestHcodeUpdate + // ===================================================================== + static size_t testFirmwareRequestHcodeUpdate( + uint64_t i_reqLen, + hostInterfaces::hbrt_fw_msg* i_req_fw_msg, + uint64_t i_respLen, + hostInterfaces::hbrt_fw_msg* i_resp_fw_msg ) + { + TRACFCOMP(g_trac_hbrt, ENTER_MRK + "rt_firmware_request::testFirmwareRequestHcodeUpdate"); + + if (i_reqLen < (hostInterfaces::HBRT_FW_MSG_BASE_SIZE + + sizeof(i_req_fw_msg->req_hcode_update))) + { + TRACFCOMP(g_trac_hbrt, ENTER_MRK"rt_firmware_request::" + "testFirmwareRequestHcodeUpdate: FAILED: Request " + "length(%d) needs to be at a minimum(%d)", + i_reqLen, + (hostInterfaces::HBRT_FW_MSG_BASE_SIZE + + sizeof(i_req_fw_msg->req_hcode_update)) ); + return -EINVAL; + } + + if ( (0x100 != i_req_fw_msg->req_hcode_update.i_chipId) || + ( 20 != i_req_fw_msg->req_hcode_update.i_section) || + ( 30 != i_req_fw_msg->req_hcode_update.i_operation) || + (0x400 != i_req_fw_msg->req_hcode_update.i_scomAddr) || + (0x500 != i_req_fw_msg->req_hcode_update.i_scomData) ) + { + TS_FAIL("rt_firmware_request::testFirmwareRequestHcodeUpdate: " + "FAILED: Loader received incorrect data: chipId:0x%X, " + "section:%d, operation:%d, scomAddr:0x%X, scomData:0x%X", + i_req_fw_msg->req_hcode_update.i_chipId, + i_req_fw_msg->req_hcode_update.i_section, + i_req_fw_msg->req_hcode_update.i_operation, + i_req_fw_msg->req_hcode_update.i_scomAddr, + i_req_fw_msg->req_hcode_update.i_scomData); + } + + i_resp_fw_msg->io_type = + hostInterfaces::HBRT_FW_MSG_TYPE_RESP_GENERIC; + + // dummy return value for testing + i_resp_fw_msg->resp_generic.o_status = 264; + + + TRACFCOMP(g_trac_hbrt, EXIT_MRK + "rt_firmware_request::testFirmwareRequestHcodeUpdate"); + + // just return 1 for testing + return 1; + } // end firmwareRequestHcodeUpdateTest + + // ===================================================================== + // compareAttributeHeader + // ===================================================================== + static bool compareAttributeHeader( + const TARGETING::AttributeTank::Attribute* const l_attribute1, + const TARGETING::AttributeTank::Attribute* const l_attribute2) + { + bool retVal(true); + + // Make sure the Attribute Header matches original data + if (0 != memcmp(&(l_attribute1->getHeader()), + &(l_attribute2->getHeader()), + sizeof(TARGETING::AttributeTank::AttributeHeader))) + { + retVal = false; + } + + return retVal; + } // end compareAttributeHeader + + // ===================================================================== + // compareAttributeValues + // ===================================================================== + static bool compareAttributeValues( + const TARGETING::AttributeTank::Attribute* const l_attribute1, + const TARGETING::AttributeTank::Attribute* const l_attribute2) + { + bool retVal(true); + + // Compare the Attribute Values for a match + if (0 != memcmp(l_attribute1->getValue(), + l_attribute2->getValue(), + l_attribute2->getHeader().iv_valSize)) + { + retVal = false; + } + + return retVal; + } // end compareAttributeValues + /// end Firmware Request Test Helper Functions + + // ===================================================================== + // Some needed definitions + // ===================================================================== + typedef std::pair<uint64_t,uint64_t> SCOM_KEY; + typedef std::map<SCOM_KEY,uint64_t> SCOM_MAP; + static SCOM_MAP cv_scomMap; + static std::map<void*, UtilLidMgr*> cv_loadedLids; static uint64_t cv_hb_data_addr; static uint64_t cv_comm_addr; static uint64_t cv_comm_phys_addr; @@ -1015,6 +1444,7 @@ class RuntimeLoaderTest : public CxxTest::TestSuite RuntimeLoaderTest::SCOM_MAP RuntimeLoaderTest::cv_scomMap; std::map<void*, UtilLidMgr*> RuntimeLoaderTest::cv_loadedLids; +// Initialize static member variables uint64_t RuntimeLoaderTest::cv_hb_data_addr = 0; uint64_t RuntimeLoaderTest::cv_comm_addr = 0; uint64_t RuntimeLoaderTest::cv_comm_phys_addr = 0; diff --git a/src/usr/trace/bufferpage.C b/src/usr/trace/bufferpage.C index c6cfb57e0..27feb9bd7 100644 --- a/src/usr/trace/bufferpage.C +++ b/src/usr/trace/bufferpage.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2017 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -41,7 +41,7 @@ namespace TRACE uint64_t l_usedSize = this->usedSize; // Verify there is enough space. - while ((usedSize + i_size) < (PAGESIZE - sizeof(BufferPage))) + while ((l_usedSize + i_size) < (PAGESIZE - sizeof(BufferPage))) { // Atomically attempt to claim i_size worth. uint64_t newSize = l_usedSize + i_size; diff --git a/src/usr/trace/daemon/daemon.C b/src/usr/trace/daemon/daemon.C index a70ad2997..dffe118b8 100644 --- a/src/usr/trace/daemon/daemon.C +++ b/src/usr/trace/daemon/daemon.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2018 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] Google Inc. */ /* [+] International Business Machines Corp. */ /* */ @@ -47,7 +47,6 @@ #include <devicefw/userif.H> #include <mbox/mboxif.H> -#include <config.h> #include <console/consoleif.H> #include <util/utilmbox_scratch.H> #include <debugpointers.H> diff --git a/src/usr/trace/runtime/rt_rsvdtracebuffer.C b/src/usr/trace/runtime/rt_rsvdtracebuffer.C index b9d21b774..175850ff8 100644 --- a/src/usr/trace/runtime/rt_rsvdtracebuffer.C +++ b/src/usr/trace/runtime/rt_rsvdtracebuffer.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017,2018 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -28,6 +28,18 @@ namespace TRACE { + +/// Some constants to help keep track of the structure of the buffer +/// Have these build on each other +// A pointer of where the reserved memory points to itself. Helps to determine +// if the buffer has been relocated +const uint32_t RESERVED_MEMORY_POINTER_OFFSET = 0; +// The location of the buffer for Entries. +const uint32_t BUFFER_BEGINNINIG_BOUNDARY_OFFSET = + sizeof(uintptr_t) + RESERVED_MEMORY_POINTER_OFFSET; +// Minimum size of the buffer, based on the buffers needs to be functional +const uint32_t MINIMUM_SIZE_OF_BUFFER_IN_BYTES = + BUFFER_BEGINNINIG_BOUNDARY_OFFSET; /** * ctor */ @@ -48,17 +60,27 @@ void RsvdTraceBuffer::init(uint32_t i_bufferSize, uintptr_t i_addressToBuffer, uintptr_t* i_addressToHead) { - // If buffer is not already initilaized and incoming data is legit + // If buffer is not already initialized and incoming data is legit if ( (false == isBufferValid()) && - (i_bufferSize > 0 ) && + (i_bufferSize > MINIMUM_SIZE_OF_BUFFER_IN_BYTES ) && (i_addressToBuffer > 0) && (nullptr != i_addressToHead) ) { - setBeginningBoundary(convertToCharPointer(i_addressToBuffer)); - setEndingBoundary(convertToCharPointer(i_addressToBuffer + - i_bufferSize - 1)); + // Set the list head pointer. This needs to be set first. setListHeadPtr(i_addressToHead); + // Set the reserved memory pointer + iv_ptrToRsvdMem = reinterpret_cast<uintptr_t*> + (i_addressToBuffer + RESERVED_MEMORY_POINTER_OFFSET); + + setBeginningBoundary(convertToCharPointer + (i_addressToBuffer + BUFFER_BEGINNINIG_BOUNDARY_OFFSET)); + setEndingBoundary(convertToCharPointer + (i_addressToBuffer + i_bufferSize - 1)); + + // Check if buffer has moved and if so, realign the pointers + checkBuffer(); + // Now that there is an actual/real buffer to point to, the buffer is // valid, although it may/may not have any entries associated with it. setBufferValidity(true); @@ -66,6 +88,60 @@ void RsvdTraceBuffer::init(uint32_t i_bufferSize, } /** + * checkBuffer + */ +void RsvdTraceBuffer::checkBuffer() +{ + intptr_t l_offset(0); + + // If the reserved memory data is not zero, meaning that buffer is being + // revisited again, and the memory does not match the current pointer of + // the reserved memory data, then the buffer has been relocated and the + // pointer info in the buffer needs to be realigned/corrected. + // The buffer gets revisited to pull data when a crash happens. Please + // see the details section for the class in the .H file. + if ((0 != iv_ptrToRsvdMem[0]) && + (reinterpret_cast<uintptr_t>(iv_ptrToRsvdMem) != iv_ptrToRsvdMem[0])) + { + // Get the difference in memory location + l_offset = reinterpret_cast<uintptr_t> + (iv_ptrToRsvdMem) - iv_ptrToRsvdMem[0]; + + realignListPointers(l_offset); + } + + // Persist the current buffer location + iv_ptrToRsvdMem[0] = reinterpret_cast<uintptr_t>(iv_ptrToRsvdMem); +} + +/** + * realignListPointers + */ +void RsvdTraceBuffer::realignListPointers(intptr_t l_offset) +{ + // Verify that there is actual data to realign + Entry* l_head = getListHead(); + if (l_head) + { + // Update the pointer to the list + *iv_ptrToHead = *iv_ptrToHead + l_offset; + + // Get the the head of list to traverse over and correct pointers + Entry* l_entry = l_head = getListHead(); + do + { + // Update the pointers of Entry item + l_entry->next = reinterpret_cast<Entry *>( + reinterpret_cast<uintptr_t>(l_entry->next) + l_offset); + l_entry->prev = reinterpret_cast<Entry *>( + reinterpret_cast<uintptr_t>(l_entry->prev) + l_offset); + + l_entry = l_entry->next; + } while (l_entry != l_head); + } +} + +/** * insertEntry */ Entry* RsvdTraceBuffer::insertEntry(uint32_t i_dataSize) @@ -83,9 +159,11 @@ Entry* RsvdTraceBuffer::insertEntry(uint32_t i_dataSize) // (Alignment is needed so that Entry's members can be atomically // updated). uint32_t l_entrySize = getAlignedSizeOfEntry(i_dataSize); - if (makeSpaceForEntry(l_entrySize, l_availableAddress) && l_availableAddress) + if (makeSpaceForEntry(l_entrySize, l_availableAddress) && + l_availableAddress) { - // Set entry if space was created and an avilable address is returned + // Set entry if space was created and an available address + // is returned l_entry = reinterpret_cast<Entry*>(l_availableAddress); setListTail(l_entry); @@ -104,7 +182,8 @@ uint32_t RsvdTraceBuffer::makeSpaceForEntry(uint32_t i_spaceNeeded, o_availableAddress = nullptr; uint32_t l_spaceAvailable = 0; - // Only look for space if requested space is less or equal to buffer size + // Only look for space if requested space is less than + // or equal to buffer size if (i_spaceNeeded <= getBufferSize()) { l_spaceAvailable = getAvailableSpace(i_spaceNeeded, o_availableAddress); @@ -112,7 +191,7 @@ uint32_t RsvdTraceBuffer::makeSpaceForEntry(uint32_t i_spaceNeeded, // Keep requesting for space until we get the space that is asked for while (l_spaceAvailable < i_spaceNeeded) { - // If we can't remove any entries, then we exhausted all efforts + // If we can't remove any entries, then we exhausted all efforts. // Should not happen, because the space requested should be less // than or equal to buffer size if (!removeOldestEntry()) @@ -167,7 +246,7 @@ uint32_t RsvdTraceBuffer::getAvailableSpace(uint32_t i_spaceNeeded, // space needed, then return that value else return the space // available at the beginning of the buffer. If the space at the // end does not have enough of the needed space, then space will - // ultimately be made at the beginning of the + // ultimately be made at the beginning of the buffer. // // Right now, you are probably thinking, what if I only need 5 free // spaces and if the end has 10 available and the beginning has 7 @@ -215,7 +294,7 @@ bool RsvdTraceBuffer::removeOldestEntry() if (!isListEmpty()) { // Get a handle to the head - Entry* l_head = getListHead(); + Entry* l_head(getListHead()); // Is there only one entry? if (l_head->next == l_head) @@ -252,12 +331,17 @@ uint32_t RsvdTraceBuffer::getTrace(void* o_data, uint32_t i_dataSize) const // Before continuing, make sure the buffer is valid if (isBufferValid()) { + // If caller passed in a nullptr for the data or zero for the data size, + // then that signals the user only wants to ascertain the size + // requirement to hold all the data associated with the entries. if ((nullptr == o_data) || (0 == i_dataSize)) { + // Caller wants to ascertain size requirements for data l_sizeOfBufferExtracted = getAggregateSizeOfEntries(); } else { + // Caller wants to collect data - enough data to fill data size l_sizeOfBufferExtracted = getTraceEntries(o_data, i_dataSize); } } @@ -273,7 +357,7 @@ uint32_t RsvdTraceBuffer::getAggregateSizeOfEntries() const uint32_t l_aggregatedSize(0); // Get a handle to the head - Entry* l_head = getListHead(); + Entry* l_head(getListHead()); // Make sure the list is not null if (l_head) @@ -283,8 +367,8 @@ uint32_t RsvdTraceBuffer::getAggregateSizeOfEntries() const { // Need to add to the size, the size of an uint32_t. The uint32_t // will hold the size of the data that is to be returned along - // with the returned data. This is why it is added. - l_aggregatedSize += l_entry->size + sizeof(uint32_t); + // with the returned data. + l_aggregatedSize += ALIGN_8(l_entry->size) + sizeof(uint32_t); l_entry = l_entry->next; } while (l_entry != l_head); } @@ -304,12 +388,12 @@ uint32_t RsvdTraceBuffer::getTraceEntries(void* o_data, uint32_t i_dataSize) con if ((nullptr != o_data) && (i_dataSize >= sizeof(trace_buf_head_t)) ) { + // Clear the outgoing data before populating it + memset(o_data, 0, i_dataSize); + // Get a useful "trace buffer head" handle to the data buffer passed in trace_buf_head_t* l_header =reinterpret_cast<trace_buf_head_t*>(o_data); - // Now that we have an easy handle to the data, let's clear it for now - memset(l_header, '\0', sizeof(trace_buf_head_t)); - // Now populate the trace buffer header with some useful info l_header->ver = TRACE_BUF_VERSION; l_header->hdr_len = l_header->size = sizeof(trace_buf_head_t); @@ -318,35 +402,42 @@ uint32_t RsvdTraceBuffer::getTraceEntries(void* o_data, uint32_t i_dataSize) con l_header->endian_flg = 'B'; // Big Endian. // Get a handle to the head - Entry* l_head = getListHead(); + Entry* l_head(getListHead()); // Extract the trace info from this class' internal buffer // If the list is not empty and have data then extract the trace info if (l_head) { - // Keep a tally of the size of the data that can be copied over - uint32_t l_totalSize(l_head->size); + // Keep a tally of the size of the data that can be copied over. + // Also account for the trace_buf_head_t that is at the beginning + // of buffer o_data. + uint32_t l_totalSize(sizeof(trace_buf_head_t)); // Keep a tally of the number of entries that can be extracted uint32_t l_entriesToExtract(0); // The entry size as data type uint32_t; for code up keep uint32_t l_entrySize(0); // Get a handle on the last entry on the list - Entry* l_entry = l_head->prev; + Entry* l_entry(l_head->prev); - // Calculate the number of entries that can be stuffed into data buffer - // starting with newest entry (tail) to oldest entry (head) + // Calculate the number of entries that can be stuffed into the data + // buffer - starting with newest entry (tail) to oldest entry (head) do { - // Calculate the size: add the size of the data, that will be - // copied over, plus the size of the type of the entry size, - // that will hold the size of the data being copied over. - if ((l_totalSize + l_entry->size + sizeof(l_entrySize)) <= i_dataSize) + // Calculate the size: add the size of the data (that will be + // copied over) plus the size of the type of the entry size + // (that will hold the size of the data being copied over). + if ((l_totalSize + ALIGN_8(l_entry->size) + sizeof(l_entrySize)) + <= i_dataSize) { - l_totalSize += l_entry->size + sizeof(l_entrySize); + l_totalSize += ALIGN_8(l_entry->size) + sizeof(l_entrySize); ++l_entriesToExtract; } else // Can't retrieve this entry; it breaks the size limitation { + // Although we are done here, we still need to point to + // the previous item. The continuation of this algorithm + // depends on it (expects to be one behind the needed data) + l_entry = l_entry->prev; break; } @@ -368,17 +459,18 @@ uint32_t RsvdTraceBuffer::getTraceEntries(void* o_data, uint32_t i_dataSize) con // Copy entry data. memcpy(&l_data[l_header->size], l_entry->data, l_entry->size); - l_header->size += l_entry->size; + l_header->size += ALIGN_8(l_entry->size); // Copy entry size. l_entrySize = l_entry->size + sizeof(l_entrySize); memcpy(&l_data[l_header->size], &l_entrySize, sizeof(l_entrySize)); l_header->size += sizeof(l_entrySize); + // increment/decrements our counters ++l_header->te_count; --l_entriesToExtract; } // end while (l_entriesToExtract) - } // end if (!isListEmpty()) + } // end if (l_head) // Update the size of the entries retrieved and the // next free memory location in header trace buffer diff --git a/src/usr/trace/runtime/rt_rsvdtracebuffer.H b/src/usr/trace/runtime/rt_rsvdtracebuffer.H index 24c9204cf..e804a41ed 100644 --- a/src/usr/trace/runtime/rt_rsvdtracebuffer.H +++ b/src/usr/trace/runtime/rt_rsvdtracebuffer.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2018 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -43,9 +43,25 @@ namespace TRACE * * @brief Class to manage the Reserved Trace Buffer * - * This is a utility class to manage the buffer - looking for space - * for an entry, adding entries and removing entries. - * + * @details This is a utility class to manage the buffer - looking + * for space for an entry, adding entries and removing entries. + * When a system crashes, this buffer will persist the last + * few traces. When HB is IPLed again, the persisted data + * will be retrieved for inspection. + * With PHYP, the buffer will be retrieved at the same memory + * location as before the crash. With OPAL, the buffer may be + * relocated to a different location and all the pointers within + * the buffer will be invalid. If the buffer does get relocated, + * this class will correct the pointers. + * To correct the pointers, a section at the beginning of the + * persisted buffer is reserved to save the address of the buffer. + * Such that when the buffer is retrieved after a crash, if that + * data does not match the current buffer address, then we can + * conclude it has been relocated and the pointers in the buffer + * need to be updated/corrected. + * If the data at the beginning of the buffer is 0, then this is + * first time this buffer is being used and therefore no need to + * correct pointers. */ class RsvdTraceBuffer { @@ -61,7 +77,7 @@ namespace TRACE * * @param[in] i_addressToBuffer - Where the buffer begins * - * @param[in] i_addressToHead - A pointer to a ponter to the first + * @param[in] i_addressToHead - A pointer to a pointer to the first * Entry, cannot be a nullptr */ void init(uint32_t i_bufferSize, @@ -89,12 +105,12 @@ namespace TRACE * If o_data is valid and the i_size is greater than * the size of trace_buf_head_t, then as many trace * entries will be returned in the o_data buffer that - * i_size will allow. + * i_size will allow, minus size of trace_buf_head_t. * - * @param[in] o_data - if not null, the buffer area to copy + * @param[out] o_data - if not null, the buffer area to copy * trace data into * - * @param[out] i_dataSize - if not 0, the size of the buffer area, + * @param[in] i_dataSize - if not 0, the size of the buffer area, * which dictates how many trace entries' * payload (or data the entry contains) * that can be copied @@ -123,7 +139,23 @@ namespace TRACE */ uint32_t getNumberOfEntries() const; + // Private methods private: + + /** @brief Checks the buffer to see if it has been relocated and if + * so, realign the pointers within the buffer. + */ + void checkBuffer(); + + + /** @brief When and if buffer has been relocated this method will + * realign the pointers within the buffer. + * + * @param[in] i_offset - the offset the buffer has moved + * within memory + */ + void realignListPointers(intptr_t i_offset); + /** @brief This function will find a contiguous piece of memory that * is large enough in size to accommodate the space needed. * If not enough free contiguous memory exists to accommodate @@ -147,7 +179,8 @@ namespace TRACE * requested is not larger in size to the buffer size, * then an available space will eventually be returned. * - * @param[in] i_spaceNeeded - @see insertEntry::i_dataSize above + * @param[in] i_spaceNeeded - The size of the contiguous piece + * of memory caller desires * * @param[out] o_availableAddress - A pointer to the contiguous * piece of memory found that satisfies the caller's @@ -160,8 +193,8 @@ namespace TRACE char* &o_availableAddress); /** @brief Returns a contiguous piece of memory that will satisfy - * the space that is needed if large enough space can be - * had, else returns the size of the largest contiguous + * the space that is needed if a large enough space can be + * found, else return the size of the largest contiguous * piece of memory. * * @algorithm There are three cases to consider: @@ -176,7 +209,7 @@ namespace TRACE * --------------------------------------------------------- * | < - 10 bytes -> | Head | .....| Tail | <- 20 bytes -> | * --------------------------------------------------------- - * scenario 1: Contigous space desired: 15 bytes + * scenario 1: Contiguous space desired: 15 bytes * Return the 20 bytes after the Tail * scenario 2: Contiguous space desired: 10 bytes * Return the 20 bytes after the Tail @@ -223,18 +256,21 @@ namespace TRACE * --------------------------------------------------------- * | .... | Tail | < - 30 bytes -> | Head | .... * --------------------------------------------------------- - * Case 1: Contigous space desired: 25 bytes + * Case 1: Contiguous space desired: 25 bytes * Return the 30 bytes between Tail and Head. - * Case 2: Contigous space desired: 40 bytes + * Case 2: Contiguous space desired: 40 bytes * Return the 30 bytes between Tail and Head. * - * @param[in] i_spaceNeeded - @see insertEntry::i_dataSize above + * @param[in] i_spaceNeeded - The size of the contiguous piece + * of memory caller desires * - * @param[out] o_availableAddress - @see makeSpaceForEntry above + * @param[out] o_availableAddress - A pointer to the biggest + * piece of contiguous memory found. May or may + * not satisfy i_spaceNeeded. * * @return The minimum size of the space found that meets the * requested space needed; or the largest size that comes - * close to meeting the space needed + * close to meeting the space needed. * */ uint32_t getAvailableSpace(uint32_t i_spaceNeeded, @@ -256,7 +292,7 @@ namespace TRACE uint32_t getAggregateSizeOfEntries() const; /** @brief This will return as many data entries that can be - * accommodated by size + * accommodated by i_dataSize * * @param[out] o_data - the buffer area to copy trace data into * @@ -380,7 +416,6 @@ namespace TRACE * * @param[in] i_tail - a pointer to an Entry data type; * OK to be a nullptr - * */ void setListTail(Entry* i_newEntry) { @@ -448,9 +483,13 @@ namespace TRACE void clearPtrToHead() { iv_ptrToHead = nullptr; } + // Private data members + private: + uintptr_t* iv_ptrToRsvdMem; //< Pointer to Reserved Memory. Used to + // realign pointers if RsvdMem relocates + uintptr_t* iv_ptrToHead; //< Pointer to oldest Entry (time wise) char *iv_bufferBeginningBoundary; //< Pointer to beginning of buffer char *iv_bufferEndingBoundary; //< Pointer to end of buffer - uintptr_t* iv_ptrToHead; //< Pointer to oldest Entry (time wise) bool iv_isBufferValid; //< Indicates an initialized buffer // For testing purposes only diff --git a/src/usr/trace/runtime/rt_rsvdtracebufservice.C b/src/usr/trace/runtime/rt_rsvdtracebufservice.C index 3d0c1bb95..21316e6f6 100644 --- a/src/usr/trace/runtime/rt_rsvdtracebufservice.C +++ b/src/usr/trace/runtime/rt_rsvdtracebufservice.C @@ -80,10 +80,10 @@ void RsvdTraceBufService::init() // If the data is not NULL, then retrieve crashed data // I want NULL in this case, not nullptr; *l_addressToHead is an int. // If I use nullptr; compiler complains - //if (*l_addressToHead != NULL) - //{ - // retrieveDataFromLastCrash(); - //} + if (*l_addressToHead != NULL) + { + retrieveDataFromLastCrash(); + } // After gathering trace info from previous crash, clear buffer data iv_rsvdTraceBuffer.clearBuffer(); diff --git a/src/usr/trace/runtime/test/testrsvdtracebuf.H b/src/usr/trace/runtime/test/testrsvdtracebuf.H index 148df5d07..0b6374ba7 100644 --- a/src/usr/trace/runtime/test/testrsvdtracebuf.H +++ b/src/usr/trace/runtime/test/testrsvdtracebuf.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2018 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -25,10 +25,8 @@ #include <cxxtest/TestSuite.H> #include <trace/runtime/rt_rsvdtracebuffer.H> // TRACE::RsvdTraceBuffer -#include <trace/runtime/rt_rsvdtracebufservice.H> // TRACE::RsvdTraceBufService -#include <trace/entry.H> // TRACE::Entry -#include <trace/compdesc.H> // TRACE::ComponentDesc -#include <util/runtime/util_rt.H> // hb_get_rt_rsvd_mem +#include <trace/entry.H> // TRACE::Entry +#include <trace/compdesc.H> // TRACE::ComponentDesc #include <stdint.h> // uint32_t #include <stdlib.h> // malloc @@ -83,7 +81,7 @@ void testRsvdTraceBuffConstructor() } TRACFCOMP(g_trac_test, EXIT_MRK"RsvdTraceBuffTestSuite:%s", __func__); -} // void testRsvdTraceBuffConstructor() +} // end void testRsvdTraceBuffConstructor // Some more simple tests - the initializer void testRsvdTraceBuffInit() @@ -108,7 +106,7 @@ void testRsvdTraceBuffInit() l_addressToHead); char* l_bufferBegin = reinterpret_cast<char*>(l_bufferAddr + - sizeof(uintptr_t)); + (2 * sizeof(uintptr_t))); char* l_bufferEnd = reinterpret_cast<char*>(l_bufferAddr + l_bufferSize - 1); @@ -155,7 +153,7 @@ void testRsvdTraceBuffInit() } TRACFCOMP(g_trac_test, EXIT_MRK"RsvdTraceBuffTestSuite:%s", __func__); -} // end void testRsvdTraceBuffInit() +} // end void testRsvdTraceBuffInit // Test where buffer is too small to accommodate any Entry size void testRsvdTraceBuffBufferToSmall() @@ -225,7 +223,7 @@ void testRsvdTraceBuffBufferToSmall() free(l_buffer); TRACFCOMP(g_trac_test, EXIT_MRK"RsvdTraceBuffTestSuite:%s", __func__); -} // end void testRsvdTraceBuffBufferToSmall() +} // end void testRsvdTraceBuffBufferToSmall // Test where buffer is just the right size to fit a single Entry void testRsvdTraceBuffOnlyAccommodateOneItem() @@ -283,7 +281,8 @@ void testRsvdTraceBuffOnlyAccommodateOneItem() TS_FAIL("%s:%s: Pointer to list is not correct", __FILE__, __func__); } - if (true != runSelfDiagnostics(l_rsvd)) + uint32_t l_itemCount(0); + if (true != runSelfDiagnostics(l_rsvd, l_itemCount)) { TS_FAIL("%s:%s: self diagnostics discovered an error", __FILE__, __func__); @@ -329,7 +328,8 @@ void testRsvdTraceBuffOnlyAccommodateOneItem() TS_FAIL("%s:%s: Pointer to list is not correct", __FILE__, __func__); } - if (true != runSelfDiagnostics(l_rsvd)) + l_itemCount = 0; + if (true != runSelfDiagnostics(l_rsvd, l_itemCount)) { TS_FAIL("%s:%s: self diagnostics discovered an error", __FILE__, __func__); @@ -354,7 +354,8 @@ void testRsvdTraceBuffOnlyAccommodateOneItem() TS_FAIL("%s:%s: Pointer to list is not correct", __FILE__, __func__); } - if (true != runSelfDiagnostics(l_rsvd)) + l_itemCount = 0; + if (true != runSelfDiagnostics(l_rsvd, l_itemCount)) { TS_FAIL("%s:%s: self diagnostics discovered an error", __FILE__, __func__); @@ -363,7 +364,7 @@ void testRsvdTraceBuffOnlyAccommodateOneItem() free(l_buffer); TRACFCOMP(g_trac_test, EXIT_MRK"RsvdTraceBuffTestSuite:%s", __func__); -} // end void testRsvdTraceBuffOnlyAccommodateOneItem() +} // end void testRsvdTraceBuffOnlyAccommodateOneItem // Test where buffer is just the right size to fit a single Entry plus size void testRsvdTraceBuffOnlyAccommodateOneItemPlusSize() @@ -378,7 +379,7 @@ void testRsvdTraceBuffOnlyAccommodateOneItemPlusSize() l_rsvd); // Adjust buffer to the area we are interested in - char* l_buffer = l_fullBuffer + sizeof(uintptr_t); + char* l_buffer = l_fullBuffer + (2 * sizeof(uintptr_t)); if (l_rsvd.getBufferSize() != l_bufferSize) { @@ -434,8 +435,8 @@ void testRsvdTraceBuffOnlyAccommodateOneItemPlusSize() __FILE__, __func__); } - - if (true != runSelfDiagnostics(l_rsvd)) + uint32_t l_itemCount(0); + if (true != runSelfDiagnostics(l_rsvd, l_itemCount)) { TS_FAIL("%s:%s: self diagnostics discovered an error", __FILE__, __func__); @@ -533,7 +534,8 @@ void testRsvdTraceBuffOnlyAccommodateOneItemPlusSize() __FILE__, __func__); } - if (true != runSelfDiagnostics(l_rsvd)) + l_itemCount = 0; + if (true != runSelfDiagnostics(l_rsvd, l_itemCount)) { TS_FAIL("%s:%s: self diagnostics discovered an error", __FILE__, __func__); @@ -603,7 +605,8 @@ void testRsvdTraceBuffOnlyAccommodateOneItemPlusSize() __FILE__, __func__); } - if (true != runSelfDiagnostics(l_rsvd)) + l_itemCount = 0; + if (true != runSelfDiagnostics(l_rsvd, l_itemCount)) { TS_FAIL("%s:%s: self diagnostics discovered an error", __FILE__, __func__); @@ -682,7 +685,7 @@ void testRsvdTraceBuffOnlyAccommodateOneItemPlusSize() free(l_fullBuffer); TRACFCOMP(g_trac_test, EXIT_MRK"RsvdTraceBuffTestSuite:%s", __func__); -} // end void testRsvdTraceBuffOnlyAccommodateOneItemPlusSize() +} // end void testRsvdTraceBuffOnlyAccommodateOneItemPlusSize // Test where buffer is just the right size to fit two Entries void testRsvdTraceBuffOnlyAccommodateTwoItems() @@ -697,7 +700,7 @@ void testRsvdTraceBuffOnlyAccommodateTwoItems() l_rsvd); // Adjust buffer to the area we are interested in - char* l_buffer = l_fullBuffer + sizeof(uintptr_t); + char* l_buffer = l_fullBuffer + (2 * sizeof(uintptr_t)); if (l_rsvd.getBufferSize() != l_bufferSize) { @@ -741,7 +744,8 @@ void testRsvdTraceBuffOnlyAccommodateTwoItems() __FILE__, __func__); } - if (true != runSelfDiagnostics(l_rsvd)) + uint32_t l_itemCount(0); + if (true != runSelfDiagnostics(l_rsvd, l_itemCount)) { TS_FAIL("%s:%s: self diagnostics discovered an error", __FILE__, __func__); @@ -790,7 +794,8 @@ void testRsvdTraceBuffOnlyAccommodateTwoItems() __FILE__, __func__); } - if (true != runSelfDiagnostics(l_rsvd)) + l_itemCount = 0; + if (true != runSelfDiagnostics(l_rsvd, l_itemCount)) { TS_FAIL("%s:%s: self diagnostics discovered an error", __FILE__, __func__); @@ -833,7 +838,8 @@ void testRsvdTraceBuffOnlyAccommodateTwoItems() __FILE__, __func__); } - if (true != runSelfDiagnostics(l_rsvd)) + l_itemCount = 0; + if (true != runSelfDiagnostics(l_rsvd, l_itemCount)) { TS_FAIL("%s:%s: self diagnostics discovered an error", __FILE__, __func__); @@ -887,7 +893,8 @@ void testRsvdTraceBuffOnlyAccommodateTwoItems() __FILE__, __func__); } - if (true != runSelfDiagnostics(l_rsvd)) + l_itemCount = 0; + if (true != runSelfDiagnostics(l_rsvd, l_itemCount)) { TS_FAIL("%s:%s: self diagnostics discovered an error", __FILE__, __func__); @@ -912,7 +919,7 @@ void testRsvdTraceBuffTestTheEnds() l_rsvd); // Adjust buffer to the area we are interested in - char* l_buffer = l_fullBuffer + sizeof(uintptr_t); + char* l_buffer = l_fullBuffer + (2 * sizeof(uintptr_t)); if (l_rsvd.getBufferSize() != l_bufferSize) { @@ -991,7 +998,8 @@ void testRsvdTraceBuffTestTheEnds() __FILE__, __func__); } - if (true != runSelfDiagnostics(l_rsvd)) + uint32_t l_itemCount(0); + if (true != runSelfDiagnostics(l_rsvd, l_itemCount)) { TS_FAIL("%s:%s: self diagnostics discovered an error", __FILE__, __func__); @@ -1028,7 +1036,8 @@ void testRsvdTraceBuffTestTheEnds() __FILE__, __func__); } - if (true != runSelfDiagnostics(l_rsvd)) + l_itemCount = 0; + if (true != runSelfDiagnostics(l_rsvd, l_itemCount)) { TS_FAIL("%s:%s: self diagnostics discovered an error", __FILE__, __func__); @@ -1064,7 +1073,8 @@ void testRsvdTraceBuffTestTheEnds() __FILE__, __func__); } - if (true != runSelfDiagnostics(l_rsvd)) + l_itemCount = 0; + if (true != runSelfDiagnostics(l_rsvd, l_itemCount)) { TS_FAIL("%s:%s: self diagnostics discovered an error", __FILE__, __func__); @@ -1089,16 +1099,18 @@ void testRsvdTraceBuffTestReentrant () iv_buffer = initializeRsvdBuffer(iv_bufferSize, l_rsvd); + iv_bufferBeginningBoundary = l_rsvd.iv_bufferBeginningBoundary; iv_bufferEndingBoundary = l_rsvd.iv_bufferEndingBoundary; // Adjust buffer to the area we are interested in - char* l_buffer = iv_buffer + sizeof(uintptr_t); + char* l_buffer = iv_buffer + (2 * sizeof(uintptr_t)); - if (l_rsvd.getBufferSize() != iv_bufferSize) + if (l_rsvd.getBufferSize() != (iv_bufferSize - sizeof(uintptr_t))) { - TS_FAIL("%s:%s: buffer size is not correct", - __FILE__, __func__); + TS_FAIL("%s:%s: buffer size is not correct %d %d", + __FILE__, __func__, l_rsvd.getBufferSize(), + (iv_bufferSize - sizeof(uintptr_t))); } if (true != l_rsvd.isBufferValid()) @@ -1149,7 +1161,8 @@ void testRsvdTraceBuffTestReentrant () __FILE__, __func__); } - if (true != runSelfDiagnostics(l_rsvd)) + uint32_t l_itemCount(0); + if (true != runSelfDiagnostics(l_rsvd, l_itemCount)) { TS_FAIL("%s:%s: self diagnostics discovered an error", __FILE__, __func__); @@ -1168,7 +1181,7 @@ void testRsvdTraceBuffTestReentrant2() TRACE::RsvdTraceBuffer l_rsvd; initializeRsvdBufferForReentrant(l_rsvd); - if (l_rsvd.getBufferSize() != iv_bufferSize) + if (l_rsvd.getBufferSize() != (iv_bufferSize - sizeof(uintptr_t))) { TS_FAIL("%s:%s: buffer size is not correct", __FILE__, __func__); @@ -1196,7 +1209,8 @@ void testRsvdTraceBuffTestReentrant2() TS_FAIL("%s:%s: buffer is not valid", __FILE__, __func__); } - if (true != runSelfDiagnostics(l_rsvd)) + uint32_t l_itemCount(0); + if (true != runSelfDiagnostics(l_rsvd, l_itemCount)) { TS_FAIL("%s:%s: self diagnostics discovered an error", __FILE__, __func__); @@ -1259,7 +1273,7 @@ void testRsvdTraceBuffTestReentrant3() TRACE::RsvdTraceBuffer l_rsvd; initializeRsvdBufferForReentrant(l_rsvd); - if (l_rsvd.getBufferSize() != iv_bufferSize) + if (l_rsvd.getBufferSize() != (iv_bufferSize - sizeof(uintptr_t))) { TS_FAIL("%s:%s: buffer size is not correct", __FILE__, __func__); @@ -1353,7 +1367,7 @@ void testRsvdTraceBuffTestReentrant4() TRACE::RsvdTraceBuffer l_rsvd; initializeRsvdBufferForReentrant(l_rsvd); - if (l_rsvd.getBufferSize() != iv_bufferSize) + if (l_rsvd.getBufferSize() != (iv_bufferSize - sizeof(uintptr_t))) { TS_FAIL("%s:%s: buffer size is not correct", __FILE__, __func__); @@ -1423,7 +1437,7 @@ void testRsvdTraceBuffTestReentrant5() TRACE::RsvdTraceBuffer l_rsvd; initializeRsvdBufferForReentrant(l_rsvd); - if (l_rsvd.getBufferSize() != iv_bufferSize) + if (l_rsvd.getBufferSize() != (iv_bufferSize - sizeof(uintptr_t))) { TS_FAIL("%s:%s: buffer size is not correct", __FILE__, __func__); @@ -1474,11 +1488,175 @@ void testRsvdTraceBuffTestReentrant5() TRACFCOMP(g_trac_test, EXIT_MRK"RsvdTraceBuffTestSuite:%s", __func__); } // end void testRsvdTraceBuffTestReentrant5 +// Test when the buffer has been relocated +// To simulate that the buffer has been relocated in memory and the pointers +// within the buffer corrected, I create a buffer and divided it into +// 3 sections. I populate the middle section with data and verify that it +// is valid. Then I copy the middle buffer data over to the top section, +// basically a memory location before the middle buffer. Zero out the middle +// section to keep myself honest, then hand that buffer over to the +// RsvdTraceBuffer class, which should detect that the buffer has been relocated +// and correct the pointers. Once the RsvdTraceBuffer class has worked it's +// magic, the buffer is tested for correctness. I repeat this process by +// moving the buffer data to the bottom buffer, basically a memory location +// after the top and repeat this test. +void testRsvdTraceBuffTestBufferRelocation() +{ + TRACFCOMP(g_trac_test, ENTER_MRK"RsvdTraceBuffTestSuite:%s", __func__); + + // Size of each buffer segment (top buffer, middle buffer, bottom buffer) + const uint32_t SEGMENT_BUFFER_SIZE = 1024; + const uint32_t NUM_SEGMENTS = 3; + // Aggregate the size of the 3 buffer segments. + uint32_t l_bufferSize = NUM_SEGMENTS * SEGMENT_BUFFER_SIZE; + // Create the buffer of all combined segments and 'zero' out + char l_buffer[l_bufferSize]; + memset(l_buffer, 0, l_bufferSize); + + // Segment the buffer into 3 sections, top, middle, bottom + char * l_niflheim = l_buffer; + char * l_midgard = &(l_buffer[1 * SEGMENT_BUFFER_SIZE]); + char * l_muspelheim = &(l_buffer[2 * SEGMENT_BUFFER_SIZE]); + + uint32_t l_itemCount(0); + uint32_t l_expectedItemCount(3); + TRACE::RsvdTraceBuffer l_rsvd; + + // Populate middle buffer with data and verify it is correct + // This is just setting up the data before simulating a relocation + { + // Get the address of buffer + uintptr_t l_bufferAddr = reinterpret_cast<uintptr_t>(l_midgard); + + // Get a pointer to where the list head needs to reside in the buffer + uintptr_t *l_addressToListHead = reinterpret_cast<uintptr_t *>(l_bufferAddr); + + + l_rsvd.init(SEGMENT_BUFFER_SIZE - sizeof(uintptr_t), // subtract list head pointer + l_bufferAddr + sizeof(uintptr_t), // 'hop' over list head pointer + l_addressToListHead); + + // populate the middle buffer (l_midgard) with data + l_rsvd.insertEntry(sizeof(TRACE::Entry) + 20); + l_rsvd.insertEntry(sizeof(TRACE::Entry) + 5); + l_rsvd.insertEntry(sizeof(TRACE::Entry) + 30); + + // Validate the buffer + l_itemCount = 0; + if (true != runSelfDiagnostics(l_rsvd, l_itemCount)) + { + TS_FAIL("%s:%s: Entry datas in midgard are corrupt", + __FILE__, __func__); + } + + if (l_itemCount != l_expectedItemCount) + { + TS_FAIL("%s:%s: The number of items found in midgard is incorrect, " + " expected %d, but got back %d", + __FILE__, __func__, l_expectedItemCount, l_itemCount); + } + } + + // Copy data over to the top buffer and clear out the middle buffer + // Simulate a relocation of the buffer to a memory address that precedes + // the original buffer's memory location + memcpy(l_niflheim, l_midgard, SEGMENT_BUFFER_SIZE); + memset(l_midgard, 0, SEGMENT_BUFFER_SIZE); + + // Test the top buffer + { + // Get the address of buffer + uintptr_t l_bufferAddr = reinterpret_cast<uintptr_t>(l_niflheim); + + // Get a pointer to where the list head needs to reside in the buffer + uintptr_t *l_addressToListHead = reinterpret_cast<uintptr_t *>(l_bufferAddr); + + // First invalidate buffer + // We need to invalidate the buffer before using it again. Saying + // it is invalid is probably a misnomer here, it really should be + // 'buffer is not initialized'. In a real situation, HB would have + // crashed and restarted. The validity of the buffer would be false + // since that info is not persisted. The buffer gets initialized with + // buffer data, which may or may not be empty. During the + // initialization the buffer gets evaluated to see if there is crash + // data to retrieve and a buffer that may or may not need the pointers + // corrected. + l_rsvd.iv_isBufferValid = false; + l_rsvd.init(SEGMENT_BUFFER_SIZE - sizeof(uintptr_t), // subtract list head pointer + l_bufferAddr + sizeof(uintptr_t), // 'hop' over list head pointer + l_addressToListHead); + + // Validate the buffer + l_itemCount = 0; + if (true != runSelfDiagnostics(l_rsvd, l_itemCount)) + { + TS_FAIL("%s:%s: Entry datas in niflheim are corrupt", + __FILE__, __func__); + } + + if (l_itemCount != l_expectedItemCount) + { + TS_FAIL("%s:%s: The number of items found in niflheim is incorrect, " + " expected %d, but got back %d", + __FILE__, __func__, l_expectedItemCount, l_itemCount); + + } + } + + // Copy data over to the bottom buffer and clear out the top buffer + // Simulate a relocation of the buffer to a memory address that succeeds + // the original buffer's memory location + memcpy(l_muspelheim, l_niflheim, SEGMENT_BUFFER_SIZE); + memset(l_niflheim, 0, SEGMENT_BUFFER_SIZE); + + // Test the bottom buffer + { + // Get the address of buffer + uintptr_t l_bufferAddr = reinterpret_cast<uintptr_t>(l_muspelheim); + + // Get a pointer to where the list head needs to reside in the buffer + uintptr_t *l_addressToListHead = reinterpret_cast<uintptr_t *>(l_bufferAddr); + + // First invalidate buffer + // We need to invalidate the buffer before using it again. Saying + // it is invalid is probably a misnomer here, it really should be + // 'buffer is not initialized'. In a real situation, HB would have + // crashed and restarted. The validity of the buffer would be false + // since that info is not persisted. The buffer gets initialized with + // buffer data, which may or may not be empty. During the + // initialization the buffer gets evaluated to see if there is crash + // data to retrieve and a buffer that may or may not need the pointers + // corrected. + l_rsvd.iv_isBufferValid = false; + l_rsvd.init(SEGMENT_BUFFER_SIZE - sizeof(uintptr_t), // subtract list head pointer + l_bufferAddr + sizeof(uintptr_t), // 'hop' over list head pointer + l_addressToListHead); + + // Validate the buffer + l_itemCount = 0; + if (true != runSelfDiagnostics(l_rsvd, l_itemCount)) + { + TS_FAIL("%s:%s: Entry datas in muspelheim are corrupt", + __FILE__, __func__); + } + + if (l_itemCount != l_expectedItemCount) + { + TS_FAIL("%s:%s: The number of items found in muspelheim is incorrect, " + " expected %d, but got back %d", + __FILE__, __func__, l_expectedItemCount, l_itemCount); + } + } + TRACFCOMP(g_trac_test, EXIT_MRK"RsvdTraceBuffTestSuite:%s", __func__); +} // end void testRsvdTraceBuffTestBufferRelocation + private: // Helpful methods to help in testing char* initializeRsvdBuffer(uint32_t i_bufferSize, TRACE::RsvdTraceBuffer& i_rsvd) { + i_bufferSize += sizeof(uintptr_t); + iv_bufferSize = i_bufferSize; // Create a buffer uint32_t l_realBufferSize = i_bufferSize + sizeof(uintptr_t); char *l_buffer = reinterpret_cast<char*>(malloc(l_realBufferSize)); @@ -1513,7 +1691,7 @@ void initializeRsvdBufferForReentrant(TRACE::RsvdTraceBuffer& i_rsvd) } -bool runSelfDiagnostics(TRACE::RsvdTraceBuffer& l_rsvd) +bool runSelfDiagnostics(TRACE::RsvdTraceBuffer& l_rsvd, uint32_t & o_itemCount) { bool l_everythingChecksOut = true; uintptr_t l_bufferBeginningBoundary = l_rsvd.getAddressOfPtr @@ -1521,15 +1699,15 @@ bool runSelfDiagnostics(TRACE::RsvdTraceBuffer& l_rsvd) uintptr_t l_bufferEndingBoundary = l_rsvd.getAddressOfPtr (l_rsvd.iv_bufferEndingBoundary); + o_itemCount = 0; + if (!l_rsvd.isListEmpty()) { - uint32_t l_itemCount(0); - TRACE::Entry* l_entry = l_rsvd.getListHead(); TRACE::Entry* l_head = l_entry; do { - ++l_itemCount; + ++o_itemCount; uintptr_t l_entryAddr = l_rsvd.getAddressOfPtr(l_entry); uintptr_t l_entryAddrEnd = l_rsvd.getEndingAddressOfEntry(l_entry); @@ -1539,7 +1717,7 @@ bool runSelfDiagnostics(TRACE::RsvdTraceBuffer& l_rsvd) TS_FAIL("Item [%d] at address (0x%X) precedes the " "allocated memory location at address " "(0x%X) by %d byte(s)", - l_itemCount, l_entryAddr, l_bufferBeginningBoundary, + o_itemCount, l_entryAddr, l_bufferBeginningBoundary, (l_bufferBeginningBoundary - l_entryAddr)); l_everythingChecksOut = false; } @@ -1548,7 +1726,7 @@ bool runSelfDiagnostics(TRACE::RsvdTraceBuffer& l_rsvd) TS_FAIL("Item [%d] at address (0x%X) is beyond the " "ending allocated memory location at address " "(0x%X) by %d byte(s)", - l_itemCount, l_entryAddr, l_bufferEndingBoundary, + o_itemCount, l_entryAddr, l_bufferEndingBoundary, (l_entryAddr - l_bufferEndingBoundary)); l_everythingChecksOut = false; } @@ -1557,7 +1735,7 @@ bool runSelfDiagnostics(TRACE::RsvdTraceBuffer& l_rsvd) TS_FAIL("Item [%d] at address (0x%X) overruns the " "ending allocated memory location at address " "(0x%X) by %d byte(s)", - l_itemCount, l_entryAddr, l_bufferEndingBoundary, + o_itemCount, l_entryAddr, l_bufferEndingBoundary, (l_entryAddrEnd - l_bufferEndingBoundary)); l_everythingChecksOut = false; } @@ -1570,7 +1748,7 @@ bool runSelfDiagnostics(TRACE::RsvdTraceBuffer& l_rsvd) { TS_FAIL("Item [%d] at address (0x%X) overruns the " "next item at address (0x%X) by %d byte(s)", - l_itemCount, l_entryAddr, l_entryNextAddr, + o_itemCount, l_entryAddr, l_entryNextAddr, (l_entryAddrEnd - l_entryNextAddr + 1)); l_everythingChecksOut = false; } diff --git a/src/usr/trace/service.C b/src/usr/trace/service.C index ad8a0250c..21b2269b5 100644 --- a/src/usr/trace/service.C +++ b/src/usr/trace/service.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2018 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] Google Inc. */ /* [+] International Business Machines Corp. */ /* */ @@ -37,7 +37,6 @@ #include <util/singleton.H> #include <assert.h> #include <time.h> -#include <config.h> #include <console/consoleif.H> #include <stdio.h> #include <ctype.h> diff --git a/src/usr/util/runtime/rt_cmds.C b/src/usr/util/runtime/rt_cmds.C index c015215b5..aa23ae7c0 100644 --- a/src/usr/util/runtime/rt_cmds.C +++ b/src/usr/util/runtime/rt_cmds.C @@ -48,6 +48,7 @@ // switchToFspScomAccess #ifdef CONFIG_NVDIMM #include <isteps/nvdimm/nvdimm.H> // notify NVDIMM protection change +#include <util/runtime/rt_fwnotify.H> #endif extern char hbi_ImageId; @@ -1162,42 +1163,101 @@ void cmd_nvdimm_protection_msg( char* &o_output, uint32_t i_huid, { errlHndl_t l_err = nullptr; o_output = new char[500]; - uint8_t l_notifyType = NVDIMM::NOT_PROTECTED; TARGETING::Target* l_targ{}; l_targ = getTargetFromHUID(i_huid); - if (l_targ != NULL) - { - if (protection == 1) - { - l_notifyType = NVDIMM::PROTECTED; - l_err = notifyNvdimmProtectionChange(l_targ, NVDIMM::PROTECTED); - } - else if (protection == 2) - { - l_notifyType = NVDIMM::UNPROTECTED_BECAUSE_ERROR; - l_err = notifyNvdimmProtectionChange(l_targ, NVDIMM::UNPROTECTED_BECAUSE_ERROR); - } - else - { - l_err = notifyNvdimmProtectionChange(l_targ, NVDIMM::NOT_PROTECTED); - } - if (l_err) - { - sprintf( o_output, "Error on call to notifyNvdimmProtectionChange" - "(0x%.8X, %d), rc=0x%.8X, plid=0x%.8X", - i_huid, l_notifyType, ERRL_GETRC_SAFE(l_err), l_err->plid() ); - errlCommit(l_err, UTIL_COMP_ID); - return; - } + + // protection should match enum from nvdimm_protection_t + // No match will just return, no error generated + l_err = notifyNvdimmProtectionChange( l_targ, + (NVDIMM::nvdimm_protection_t)protection); + if (l_err) + { + sprintf( o_output, "Error on call to notifyNvdimmProtectionChange" + "(0x%.8X, %d), rc=0x%.8X, plid=0x%.8X", + i_huid, protection, ERRL_GETRC_SAFE(l_err), l_err->plid() ); + errlCommit(l_err, UTIL_COMP_ID); + } +} + +/** + * @brief Check the ES (energy source) health status of all NVDIMMs in the + * system. If check fails, see HBRT traces for further details. + * @param[out] o_output Output display buffer, memory allocated here. + * Will inform caller if ES health check passes or fails. + */ +void cmd_nvDimmEsCheckHealthStatus( char* &o_output) +{ + o_output = new char[500]; + if (NVDIMM::nvDimmEsCheckHealthStatusOnSystem()) + { + sprintf( o_output, "cmd_nvDimmEsCheckHealthStatus: " + "ES (energy source) health status check passed."); + } else { - sprintf( o_output, "cmd_nvdimm_protection_msg: HUID 0x%.8X not found", - i_huid ); - return; + sprintf( o_output, "cmd_nvDimmEsCheckHealthStatus: " + "ES (energy source) health status check failed. " + "Inspect HBRT traces for further details."); + + } + + return; +} // end cmd_nvDimmEsCheckHealthStatus + +/** + * @brief Check the NVM (non-volatile memory) health status of all NVDIMMs in + * the system. If check fails, see HBRT traces for further details. + * @param[out] o_output Output display buffer, memory allocated here. + * Will inform caller if NVM health check passes or fails. + */ + +void cmd_nvdDmmNvmCheckHealthStatus( char* &o_output) +{ + o_output = new char[500]; + if (NVDIMM::nvDimmNvmCheckHealthStatusOnSystem()) + { + sprintf( o_output, "cmd_nvdDmmNvmCheckHealthStatus: " + "NVM (non-volatile memory) health status check passed."); + + } + else + { + sprintf( o_output, "cmd_nvdDmmNvmCheckHealthStatus: " + "NVM (non-volatile memory) health status check failed. " + "Inspect HBRT traces for further details."); + + } + + return; +} // end cmd_nvdDmmNvmCheckHealthStatus + + +/** + * @brief Execute nvdimm operation, see interface.h for operation format + * @param[out] o_output Output display buffer, memory allocated here. + * Will inform caller if nvdimm op passes or fails. + * @param[in] i_op nvdimm operation to perform, see interface.h + */ +void cmd_nvdimm_op( char* &o_output, uint16_t i_op ) +{ + o_output = new char[500]; + + hostInterfaces::nvdimm_operation_t l_operation; + l_operation.procId = HBRT_NVDIMM_OPERATION_APPLY_TO_ALL_NVDIMMS; + l_operation.rsvd1 = 0x0; + l_operation.rsvd2 = 0x0; + l_operation.opType = (hostInterfaces::NVDIMM_Op_t)i_op; + + int rc = doNvDimmOperation(l_operation); + if (rc == -1) + { + sprintf( o_output, "Error on call doNvDimmOperation() op 0x%X",i_op); } } + + #endif /** @@ -1534,6 +1594,44 @@ int hbrtCommand( int argc, sprintf(*l_output, "ERROR: nvdimm_protection <huid> <0 or 1>"); } } + else if( !strcmp( argv[0], "nvdimm_es_check_status" ) ) + { + if (argc == 1) + { + cmd_nvDimmEsCheckHealthStatus( *l_output ); + } + else + { + *l_output = new char[100]; + sprintf(*l_output, "Usage: nvdimm_es_check_status"); + } + } + else if( !strcmp( argv[0], "nvdimm_nvm_check_status" ) ) + { + if (argc == 1) + { + cmd_nvdDmmNvmCheckHealthStatus( *l_output ); + } + else + { + *l_output = new char[100]; + sprintf(*l_output, "Usage: nvdimm_nvm_check_status"); + } + } + else if( !strcmp( argv[0], "nvdimm_op" ) ) + { + if (argc == 2) + { + uint16_t op = strtou64(argv[1], NULL, 16); + cmd_nvdimm_op( *l_output, op ); + } + else + { + *l_output = new char[100]; + sprintf(*l_output, "ERROR: nvdimm_op <op>"); + } + } + #endif else { @@ -1574,6 +1672,16 @@ int hbrtCommand( int argc, #ifdef CONFIG_NVDIMM sprintf( l_tmpstr, "nvdimm_protection <huid> <0 or 1>\n"); strcat( *l_output, l_tmpstr ); + sprintf( l_tmpstr, "nvdimm_es_check_status\n"); + strcat( *l_output, l_tmpstr ); + sprintf( l_tmpstr, "nvdimm_nvm_check_status\n"); + strcat( *l_output, l_tmpstr ); + sprintf( l_tmpstr, "nvdimm_op <op>\n" + " 0x1=disarm 0x2=disable_encryption 0x4=remove_keys\n" + " 0x8=enable_encryption 0x10=arm 0x20=es_healthcheck\n" + " 0x40=nvm_healthcheck\n"); + strcat( *l_output, l_tmpstr ); + #endif } diff --git a/src/usr/util/runtime/rt_fwnotify.C b/src/usr/util/runtime/rt_fwnotify.C index dae81e7d6..556a1c31f 100644 --- a/src/usr/util/runtime/rt_fwnotify.C +++ b/src/usr/util/runtime/rt_fwnotify.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017,2019 */ +/* Contributors Listed Below - COPYRIGHT 2017,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -31,10 +31,14 @@ #include <errl/errlmanager.H> // errlCommit #include <errl/hberrltypes.H> // TWO_UINT32_TO_UINT64 #include <targeting/common/target.H> // TargetHandle_t, getTargetFromHuid +#include <targeting/runtime/rt_targeting.H> // RT_TARG::getHbTarget #include <attributeenums.H> // ATTRIBUTE_ID #ifdef CONFIG_NVDIMM -#include <isteps/nvdimm/nvdimm.H> // notify NVDIMM protection change +#include <isteps/nvdimm/nvdimm.H> // NVDIMM related activities +#include <targeting/common/targetUtil.H> // makeAttribute +#include <runtime/hbrt_utilities.H> +using namespace NVDIMM; #endif using namespace TARGETING; @@ -43,6 +47,7 @@ using namespace ERRORLOG; using namespace MBOX; using namespace SBEIO; + // Trace definition extern trace_desc_t* g_trac_runtime; extern trace_desc_t* g_trac_hbrt; @@ -51,7 +56,7 @@ extern trace_desc_t* g_trac_hbrt; * @brief The lower and upper bounds for the sequence ID. **/ const uint16_t SEQ_ID_MIN = 0x0000; -const uint16_t SEQ_ID_MAX = 0x7FFF; +const uint16_t SEQ_ID_MAX = 0x7FFF; /** * @brief Set the sequence ID to the minimum value @@ -85,7 +90,7 @@ uint16_t SeqId_t::getNextSeqId() **/ uint16_t SeqId_t::getCurrentSeqId() { - return SeqId_t::SEQ_ID; + return SeqId_t::SEQ_ID; } /** @@ -96,12 +101,12 @@ uint16_t SeqId_t::getCurrentSeqId() **/ void sbeAttemptRecovery(uint64_t i_data) { - // Create a useful struct to get to the data - // The data is expected to be a HUID (in the first 4 bytes) - // followed by a PLID (in the last 4 bytes). - SbeRetryReqData_t *l_sbeRetryData = reinterpret_cast<SbeRetryReqData_t*>(&i_data); + // Create a useful struct to get to the data + // The data is expected to be a HUID (in the first 4 bytes) + // followed by a PLID (in the last 4 bytes). + SbeRetryReqData_t *l_sbeRetryData = reinterpret_cast<SbeRetryReqData_t*>(&i_data); - TRACFCOMP(g_trac_runtime, ENTER_MRK"sbeAttemptRecovery: plid:0x%X, " + TRACFCOMP(g_trac_runtime, ENTER_MRK"sbeAttemptRecovery: plid:0x%X, " "HUID:0x%X", l_sbeRetryData->plid, l_sbeRetryData->huid); errlHndl_t l_err = nullptr; @@ -115,7 +120,7 @@ void sbeAttemptRecovery(uint64_t i_data) // If HUID invalid, log error and quit if (nullptr == l_target) { - TRACFCOMP(g_trac_runtime, ERR_MRK"sbeAttemptRecovery: " + TRACFCOMP(g_trac_runtime, ERR_MRK"sbeAttemptRecovery: " "No target associated with HUID:0x%.8X", l_sbeRetryData->huid); @@ -149,7 +154,7 @@ void sbeAttemptRecovery(uint64_t i_data) if (nullptr == g_hostInterfaces || nullptr == g_hostInterfaces->firmware_request) { - TRACFCOMP(g_trac_runtime, ERR_MRK"sbeAttemptRecovery: " + TRACFCOMP(g_trac_runtime, ERR_MRK"sbeAttemptRecovery: " "Hypervisor firmware_request interface not linked"); /*@ @@ -260,12 +265,12 @@ void occActiveNotification( void * i_data ) if (*l_active) { l_err = NVDIMM::notifyNvdimmProtectionChange(l_proc, - NVDIMM::PROTECTED); + NVDIMM::OCC_ACTIVE); } else { l_err = NVDIMM::notifyNvdimmProtectionChange(l_proc, - NVDIMM::NOT_PROTECTED); + NVDIMM::OCC_INACTIVE); } // commit error if it exists @@ -294,12 +299,12 @@ void attrSyncRequest( void * i_data) HbrtAttrSyncData_t * l_hbrtAttrData = reinterpret_cast<HbrtAttrSyncData_t*>(i_data); TRACFCOMP(g_trac_runtime, ENTER_MRK"attrSyncRequest: Target HUID 0x%0X " - "for AttrID: 0x%0X with AttrSize: %lld", l_hbrtAttrData->huid, - l_hbrtAttrData->attrID, l_hbrtAttrData->sizeOfAttrData); + "for AttrID: 0x%0X with AttrSize: %lld", l_hbrtAttrData->huid, + l_hbrtAttrData->attrID, l_hbrtAttrData->sizeOfAttrData); TRACFBIN(g_trac_runtime, "Attribute data: ", - &(l_hbrtAttrData->attrDataStart), - l_hbrtAttrData->sizeOfAttrData); + &(l_hbrtAttrData->attrDataStart), + l_hbrtAttrData->sizeOfAttrData); // extract the target from the given HUID TargetHandle_t l_target = Target::getTargetFromHuid(l_hbrtAttrData->huid); @@ -325,36 +330,496 @@ void attrSyncRequest( void * i_data) memcpy(&l_attrData, &(l_hbrtAttrData->attrDataStart), l_attrSize); /*@ - * @errortype - * @severity ERRL_SEV_PREDICTIVE - * @moduleid MOD_RT_ATTR_SYNC_REQUEST - * @reasoncode RC_ATTR_UPDATE_FAILED - * @userdata1[0:31] Target HUID - * @userdata1[32:63] Attribute ID - * @userdata2[0:31] Data Size - * @userdata2[32:63] Up to 4 bytes of attribute data - * @devdesc Attribute failed to update on HBRT side - */ - errlHndl_t l_err = new ErrlEntry(ERRL_SEV_PREDICTIVE, - MOD_RT_ATTR_SYNC_REQUEST, - RC_ATTR_UPDATE_FAILED, - TWO_UINT32_TO_UINT64( + * @errortype + * @severity ERRL_SEV_PREDICTIVE + * @moduleid MOD_RT_ATTR_SYNC_REQUEST + * @reasoncode RC_ATTR_UPDATE_FAILED + * @userdata1[0:31] Target HUID + * @userdata1[32:63] Attribute ID + * @userdata2[0:31] Data Size + * @userdata2[32:63] Up to 4 bytes of attribute data + * @devdesc Attribute failed to update on HBRT side + */ + errlHndl_t l_err = new ErrlEntry(ERRL_SEV_PREDICTIVE, + MOD_RT_ATTR_SYNC_REQUEST, + RC_ATTR_UPDATE_FAILED, + TWO_UINT32_TO_UINT64( l_hbrtAttrData->huid, l_hbrtAttrData->attrID), - TWO_UINT32_TO_UINT64( + TWO_UINT32_TO_UINT64( l_hbrtAttrData->sizeOfAttrData, l_attrData), - true); + true); - l_err->collectTrace(RUNTIME_COMP_NAME, 256); + l_err->collectTrace(RUNTIME_COMP_NAME, 256); - //Commit the error - errlCommit(l_err, RUNTIME_COMP_ID); + //Commit the error + errlCommit(l_err, RUNTIME_COMP_ID); } TRACFCOMP(g_trac_runtime, EXIT_MRK"attrSyncRequest"); } +#ifdef CONFIG_NVDIMM +/** + * @brief Utility function to set ATTR_NVDIMM_ENCRYPTION_ENABLE + * and send the value to the FSP + */ +void set_ATTR_NVDIMM_ENCRYPTION_ENABLE( + ATTR_NVDIMM_ENCRYPTION_ENABLE_type i_val ) +{ + errlHndl_t l_err = nullptr; + + Target* l_sys = nullptr; + targetService().getTopLevelTarget( l_sys ); + assert(l_sys, "set_ATTR_NVDIMM_ENCRYPTION_ENABLE: no TopLevelTarget"); + l_sys->setAttr<ATTR_NVDIMM_ENCRYPTION_ENABLE>(i_val); + + // Send it down to the FSP + AttributeTank::Attribute l_attr = {}; + if( !makeAttribute<ATTR_NVDIMM_ENCRYPTION_ENABLE> + (l_sys, l_attr) ) + { + TRACFCOMP(g_trac_runtime, ERR_MRK"set_ATTR_NVDIMM_ENCRYPTION_ENABLE() Could not create Attribute"); + /*@ + *@errortype + *@reasoncode RC_CANNOT_MAKE_ATTRIBUTE + *@severity ERRORLOG_SEV_PREDICTIVE + *@moduleid SET_ATTR_NVDIMM_ENCRYPTION_ENABLE + *@devdesc Couldn't create an Attribute to send the data + * to the FSP + *@custdesc NVDIMM encryption error + */ + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_PREDICTIVE, + SET_ATTR_NVDIMM_ENCRYPTION_ENABLE, + RC_CANNOT_MAKE_ATTRIBUTE, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT ); + l_err->collectTrace(NVDIMM_COMP_NAME); + errlCommit( l_err, NVDIMM_COMP_ID ); + } + else + { + std::vector<TARGETING::AttributeTank::Attribute> l_attrList; + l_attrList.push_back(l_attr); + l_err = sendAttributes( l_attrList ); + if (l_err) + { + TRACFCOMP(g_trac_runtime, ERR_MRK"set_ATTR_NVDIMM_ENCRYPTION_ENABLE() Error sending ATTR_NVDIMM_ENCRYPTION_ENABLE down to FSP"); + l_err->setSev(ERRORLOG::ERRL_SEV_PREDICTIVE); + l_err->collectTrace(NVDIMM_COMP_NAME); + errlCommit( l_err, NVDIMM_COMP_ID ); + } + } +} +#endif //CONFIG_NVDIMM + +/** + * @brief Perform an NVDIMM operation + * @param[in] i_nvDimmOp - A struct that contains the operation(s) to perform + * and a flag indicating whether to perform operation + * on all processors or a given single processor. + * + * @Note The arming/disarming operations below are in the order of which they + * should be performed. If a new sequence is added to the + * arming/disarming sequence, make sure it is inserted in the + * correct order. + * The current order is: disarm -> disable encryption -> remove keys -> + * enable encryption -> arm + **/ +int doNvDimmOperation(const hostInterfaces::nvdimm_operation_t& i_nvDimmOp) +{ + int rc = 0; +#ifndef CONFIG_NVDIMM + TRACFCOMP(g_trac_runtime, ENTER_MRK"doNvDimmOperation: not an " + "NVDIMM configuration, this call becomes a noop."); + +#else + TRACFCOMP(g_trac_runtime, ENTER_MRK"doNvDimmOperation: Operation(s) " + "0x%0X, processor ID 0x%0X", + i_nvDimmOp.opType, + i_nvDimmOp.procId); + + // Error log handle for capturing any errors + errlHndl_t l_err{nullptr}; + // List of NVDIMM Targets to execute NVDIMM operation on + TargetHandleList l_nvDimmTargetList; + + // Perform the operations requested + do + { + /// Populate the NVDIMM target list + // If requesting to perform operation on all NVDIMMs, then + // retrieve all NVDIMMs from system + if (HBRT_NVDIMM_OPERATION_APPLY_TO_ALL_NVDIMMS == i_nvDimmOp.procId) + { + nvdimm_getNvdimmList(l_nvDimmTargetList); + } + // Else retrieve only the NVDIMMs from given processor ID + else + { + /// Get the NVDIMMs associated with procId + // Convert the procId to a real boy, uh, I mean target + TARGETING::TargetHandle_t l_procTarget; + l_err = RT_TARG::getHbTarget(i_nvDimmOp.procId, l_procTarget); + if (l_err) + { + TRACFCOMP(g_trac_runtime, "doNvDimmOperation: Error getting " + "HB Target from processor ID 0x%0X, " + "exiting ...", + i_nvDimmOp.procId); + rc = -1; + break; + } + + // Get the list of NVDIMMs associated with processor target + l_nvDimmTargetList = TARGETING::getProcNVDIMMs(l_procTarget); + } + + // No point in continuing if the list of NVDIMM Targets is empty + if (!l_nvDimmTargetList.size()) + { + TRACFCOMP(g_trac_runtime, "doNvDimmOperation: No NVDIMMs found, " + "exiting ..."); + rc = -1; + break; + } + + // Perform the arming/disarming operations. If anyone fails in the + // sequence, no point in calling the next, if there is a next operation. + do + { + // Disarm the NV logic + if (i_nvDimmOp.opType & hostInterfaces::HBRT_FW_NVDIMM_DISARM) + { + // Make call to disarm + if (!nvdimmDisarm(l_nvDimmTargetList)) + { + TRACFCOMP(g_trac_runtime, "doNvDimmOperation: " + "Call to disarm failed. Will not perform any " + "more arming/disarming calls, if they exist"); + rc = -1; + break; + } + else + { + TRACFCOMP(g_trac_runtime, "doNvDimmOperation: " + "Call to disarm succeeded"); + } + } + + // Disable encryption on the NVDIMM and clear saved values from FW + if (i_nvDimmOp.opType & + hostInterfaces::HBRT_FW_NVDIMM_DISABLE_ENCRYPTION) + { + // Make call to disable encryption + if (!nvdimm_crypto_erase(l_nvDimmTargetList)) + { + TRACFCOMP(g_trac_runtime, "doNvDimmOperation: " + "Call to disable encryption failed. Will not " + "perform any more arming/disarming calls, if " + "they exist"); + + // Clear the encryption enable attribute + set_ATTR_NVDIMM_ENCRYPTION_ENABLE(0); + + rc = -1; + break; + } + else + { + TRACFCOMP(g_trac_runtime, "doNvDimmOperation: " + "Call to disable encryption succeeded."); + } + + // Clear the encryption enable attribute + set_ATTR_NVDIMM_ENCRYPTION_ENABLE(0); + } + + // Remove keys + if (i_nvDimmOp.opType & hostInterfaces::HBRT_FW_NVDIMM_REMOVE_KEYS) + { + // Make call to remove keys + if (!nvdimm_remove_keys()) + { + TRACFCOMP(g_trac_runtime, "doNvDimmOperation: " + "Call to remove keys failed. Will not perform " + "any more arming/disarming calls, if they exist"); + rc = -1; + break; + } + else + { + TRACFCOMP(g_trac_runtime, "doNvDimmOperation: " + "Call to remove keys succeeded."); + } + } + + // Enable encryption on the NVDIMM + if (i_nvDimmOp.opType & + hostInterfaces::HBRT_FW_NVDIMM_ENABLE_ENCRYPTION) + { + // Set the encryption enable attribute + set_ATTR_NVDIMM_ENCRYPTION_ENABLE(1); + + // Make call to generate keys before enabling encryption + if(!nvdimm_gen_keys()) + { + TRACFCOMP(g_trac_runtime, "doNvDimmOperation: " + "Call to generate keys failed, unable to enable " + "encryption. Will not perform any more " + "arming/disarming calls, if they exist"); + rc = -1; + break; + } + else + { + // Make call to enable encryption + if (!nvdimm_encrypt_enable(l_nvDimmTargetList)) + { + TRACFCOMP(g_trac_runtime, "doNvDimmOperation: " + "Call to enable encryption failed. " + "Will not perform any more arming/disarming " + "calls, if they exist"); + rc = -1; + break; + } + else + { + TRACFCOMP(g_trac_runtime, "doNvDimmOperation: " + "Call to enable encryption succeeded."); + } + } // end if(!nvdimm_gen_keys()) ... else ... + } + + // Arm the NV logic + if (i_nvDimmOp.opType & hostInterfaces::HBRT_FW_NVDIMM_ARM) + { + // Make call to arm + if (!nvdimmArm(l_nvDimmTargetList)) + { + TRACFCOMP(g_trac_runtime, "doNvDimmOperation: " + "Call to arm failed."); + rc = -1; + break; + } + else + { + TRACFCOMP(g_trac_runtime, "doNvDimmOperation: " + "Call to arm succeeded."); + } + } // end if (nvDimmOp.opType & hostInterfaces::HBRT_FW_NVDIMM_ARM) + } while (0); // end Perform the arming/disarming operations. + + // Perform the ES (energy source) health check operation + if (i_nvDimmOp.opType & hostInterfaces::HBRT_FW_MNFG_ES_HEALTH_CHECK) + { + if (!nvDimmEsCheckHealthStatus(l_nvDimmTargetList)) + { + TRACFCOMP(g_trac_runtime, "doNvDimmOperation: " + "Call to do an ES (energy source) health check failed."); + rc = -1; + break; + } + else + { + TRACFCOMP(g_trac_runtime, "doNvDimmOperation: " + "Call to do an ES (energy source) health check succeeded."); + } + } + + // Perform the NVM (non-volatile memory) health check operation + if (i_nvDimmOp.opType & hostInterfaces::HBRT_FW_MNFG_NVM_HEALTH_CHECK) + { + if (!nvDimmNvmCheckHealthStatus(l_nvDimmTargetList)) + { + TRACFCOMP(g_trac_runtime, "doNvDimmOperation: " + "Call to do a NVM (non-volatile memory) health check failed."); + rc = -1; + break; + } + else + { + TRACFCOMP(g_trac_runtime, "doNvDimmOperation: " + "Call to do a NVM (non-volatile memory) health check succeeded."); + } + } + + // Perform the factory default operation + if (i_nvDimmOp.opType & hostInterfaces::HBRT_FW_NVDIMM_FACTORY_DEFAULT) + { + if (!nvdimmFactoryDefault(l_nvDimmTargetList)) + { + TRACFCOMP(g_trac_runtime, "doNvDimmOperation: " + "Call to do NVDIMM Factory Default operation failed."); + rc = -1; + break; + } + else + { + TRACFCOMP(g_trac_runtime, "doNvDimmOperation: " + "Call to do NVDIMM Factory Default operation succeeded."); + } + } + + // Perform the secure erase verify start operation + if (i_nvDimmOp.opType & hostInterfaces::HBRT_FW_NVDIMM_SECURE_EV_START) + { + if (!nvdimmSecureEraseVerifyStart(l_nvDimmTargetList)) + { + TRACFCOMP(g_trac_runtime, "doNvDimmOperation: " + "Call to do NVDIMM Secure Erase Verify Start failed."); + rc = -1; + break; + } + else + { + TRACFCOMP(g_trac_runtime, "doNvDimmOperation: " + "Call to do NVDIMM Secure Erase Verify Start succeeded."); + } + } + + // Perform the secure erase verify status operation + if (i_nvDimmOp.opType & hostInterfaces::HBRT_FW_NVDIMM_SECURE_EV_STATUS) + { + if (!nvdimmSecureEraseVerifyStatus(l_nvDimmTargetList)) + { + TRACFCOMP(g_trac_runtime, "doNvDimmOperation: " + "Call to do NVDIMM Secure Erase Verify Status failed."); + rc = -1; + break; + } + else + { + TRACFCOMP(g_trac_runtime, "doNvDimmOperation: " + "Call to do NVDIMM Secure Erase Verify Status succeeded."); + } + } + + } while(0); // end Perform the operations requested + + if (l_err) + { + //Commit the error if it exists + errlCommit(l_err, RUNTIME_COMP_ID); + } + +#endif + + TRACFCOMP(g_trac_runtime, EXIT_MRK"doNvDimmOperation") + return rc; +} + +/** + * @brief Log the gard event from PHYP/OPAL + * + * @param[in] i_gardEvent - The details of the gard event + * @see hostInterfaces::gard_event_t for more info + * + **/ +void logGardEvent(const hostInterfaces::gard_event_t& i_gardEvent) +{ + // Trace input components + TRACFCOMP(g_trac_runtime, + ENTER_MRK"logGardEvent: Gard Event Data: " + "error type(0x%.8X), processor ID(0x%.8X), " + "PLID(0x%.8X), sub unit mask(0x.%4X), " + "recovery level(0x.%4X)", + i_gardEvent.i_error_type, + i_gardEvent.i_procId, + i_gardEvent.i_plid, + i_gardEvent.i_sub_unit_mask, + i_gardEvent.i_recovery_level); + + errlHndl_t l_err{nullptr}; + + do + { + // Make sure the error type is valid, if not, log it + if ((i_gardEvent.i_error_type == hostInterfaces::HBRT_GARD_ERROR_UNKNOWN ) || + (i_gardEvent.i_error_type >= hostInterfaces::HBRT_GARD_ERROR_LAST) ) + { + TRACFCOMP(g_trac_runtime, "logGardEvent: ERROR: unknown/invalid " + "error type 0x%.8X", + i_gardEvent.i_error_type); + + /* @ + * @errortype + * @severity ERRL_SEV_PREDICTIVE + * @moduleid MOD_RT_FIRMWARE_NOTIFY + * @reasoncode RC_LOG_GARD_EVENT_UNKNOWN_ERROR_TYPE + * @userdata1[0:31] GARD error type + * @userdata1[32:63] Processor ID + * @userdata2[0:31] Sub unit mask + * @userdata2[32:63] Recovery level + * @devdesc Unknown/invalid error type + * @custdesc Internal firmware error + */ + l_err = new ErrlEntry( ERRL_SEV_PREDICTIVE, + MOD_RT_FIRMWARE_NOTIFY, + RC_LOG_GARD_EVENT_UNKNOWN_ERROR_TYPE, + TWO_UINT32_TO_UINT64( + i_gardEvent.i_error_type, + i_gardEvent.i_procId), + TWO_UINT32_TO_UINT64( + i_gardEvent.i_sub_unit_mask, + i_gardEvent.i_recovery_level), + ErrlEntry::ADD_SW_CALLOUT); + break; + } + + + // Get the Target associated with processor ID + TARGETING::TargetHandle_t l_procTarget{nullptr}; + l_err = RT_TARG::getHbTarget(i_gardEvent.i_procId, l_procTarget); + if (l_err) + { + TRACFCOMP(g_trac_runtime, "logGardEvent: Error getting " + "HB Target from processor ID 0x%0X, " + "exiting ...", + i_gardEvent.i_procId); + break; + } + + // Log the GARD event + /* @ + * @errortype + * @severity ERRL_SEV_PREDICTIVE + * @moduleid MOD_RT_FIRMWARE_NOTIFY + * @reasoncode RC_LOG_GARD_EVENT + * @userdata1[0:31] GARD error type + * @userdata1[32:63] Processor ID + * @userdata2[0:31] Sub unit mask + * @userdata2[32:63] Recovery level + * @devdesc Gard event from Opal/Phyp + * @custdesc Hardware error detected at runtime + */ + l_err = new ErrlEntry( ERRL_SEV_PREDICTIVE, + MOD_RT_FIRMWARE_NOTIFY, + RC_LOG_GARD_EVENT, + TWO_UINT32_TO_UINT64( + i_gardEvent.i_error_type, + i_gardEvent.i_procId), + TWO_UINT32_TO_UINT64( + i_gardEvent.i_sub_unit_mask, + i_gardEvent.i_recovery_level)); + + // Set the PLID to the given gard event PLID if it exist + if (i_gardEvent.i_plid) + { + l_err->plid(i_gardEvent.i_plid); + } + + // Do the actual gard + l_err->addHwCallout( l_procTarget, HWAS::SRCI_PRIORITY_MED, + HWAS::NO_DECONFIG, HWAS::GARD_PHYP); + } while(0); + + // Commit any error log that occurred. + errlCommit(l_err, RUNTIME_COMP_ID); + + TRACFCOMP(g_trac_runtime, EXIT_MRK"logGardEvent") +} /** * @see src/include/runtime/interface.h for definition of call @@ -362,12 +827,12 @@ void attrSyncRequest( void * i_data) */ void firmware_notify( uint64_t i_len, void *i_data ) { - TRACFCOMP(g_trac_hbrt, ENTER_MRK"firmware_notify: " + TRACFCOMP(g_trac_hbrt, ENTER_MRK"firmware_notify: " "i_len:%d", i_len ); - TRACFBIN(g_trac_runtime, "firmware_notify: i_data", i_data, i_len); + TRACFBIN(g_trac_runtime, "firmware_notify: i_data", i_data, i_len); - errlHndl_t l_err = nullptr; + errlHndl_t l_err = nullptr; // Flag to detect an invalid/unknown/not used message bool l_badMessage = false; @@ -381,12 +846,12 @@ void firmware_notify( uint64_t i_len, void *i_data ) // data necessary to determine type of message if (i_len < hostInterfaces::HBRT_FW_MSG_BASE_SIZE) { - l_badMessage = true; + l_badMessage = true; - TRACFCOMP(g_trac_runtime, ERR_MRK"firmware_notify: " - "Received a non hostInterfaces::hbrt_fw_msg data stream" ); + TRACFCOMP(g_trac_runtime, ERR_MRK"firmware_notify: Received " + "a non hostInterfaces::hbrt_fw_msg data stream" ); - break; + break; } // Cast the data to an hbrt_fw_msg to extract the input type @@ -394,68 +859,116 @@ void firmware_notify( uint64_t i_len, void *i_data ) static_cast<hostInterfaces::hbrt_fw_msg*>(i_data); switch (l_hbrt_fw_msg->io_type) { - case hostInterfaces::HBRT_FW_MSG_HBRT_FSP_REQ: - { - // Distinguish based on msgType and msgq - if ( (l_hbrt_fw_msg->generic_msg.msgType == + case hostInterfaces::HBRT_FW_MSG_HBRT_FSP_REQ: + { + // Distinguish based on msgType and msgq + if ( (l_hbrt_fw_msg->generic_msg.msgType == GenericFspMboxMessage_t::MSG_ATTR_SYNC_REQUEST) && (l_hbrt_fw_msg->generic_msg.msgq == MBOX::HB_ATTR_SYNC_MSGQ) ) - { - attrSyncRequest((void*)&(l_hbrt_fw_msg->generic_msg.data)); - } - else if ((l_hbrt_fw_msg->generic_msg.msgType == - GenericFspMboxMessage_t::MSG_OCC_ACTIVE) && - (l_hbrt_fw_msg->generic_msg.msgq == - MBOX::FSP_OCC_MSGQ_ID) ) - { - occActiveNotification((void*)&(l_hbrt_fw_msg->generic_msg.data)); - } - // Placing this at end as it does not have a msgq specified - // Want to match msgType & msgq combos first - else if (l_hbrt_fw_msg->generic_msg.msgType == - GenericFspMboxMessage_t::MSG_SBE_ERROR) - { - sbeAttemptRecovery(l_hbrt_fw_msg->generic_msg.data); - } - else - { - l_badMessage = true; - - TRACFCOMP(g_trac_runtime, ERR_MRK"firmware_notify: " - "Unknown FSP message type:0x%.8X, " - "message queue id:0x%.8X, seqNum:%d ", - l_hbrt_fw_msg->generic_msg.msgType, - l_hbrt_fw_msg->generic_msg.msgq, - l_hbrt_fw_msg->generic_msg.seqnum); - - // Pack user data 1 with message input type and - // firmware request message sequence number - l_userData1 = TWO_UINT32_TO_UINT64( - l_hbrt_fw_msg->io_type, - l_hbrt_fw_msg->generic_msg.seqnum); - - // Pack user data 2 with message queue and message type - l_userData2 = TWO_UINT32_TO_UINT64( - l_hbrt_fw_msg->generic_msg.msgq, - l_hbrt_fw_msg->generic_msg.msgType); - } - } // END case HBRT_FW_MSG_HBRT_FSP_REQ: + { + attrSyncRequest((void*)&(l_hbrt_fw_msg->generic_msg.data)); + } + else if ((l_hbrt_fw_msg->generic_msg.msgType == + GenericFspMboxMessage_t::MSG_OCC_ACTIVE) && + (l_hbrt_fw_msg->generic_msg.msgq == + MBOX::FSP_OCC_MSGQ_ID) ) + { + occActiveNotification((void*)&(l_hbrt_fw_msg->generic_msg.data)); + } + // Placing this at end as it does not have a msgq specified + // Want to match msgType & msgq combos first + else if (l_hbrt_fw_msg->generic_msg.msgType == + GenericFspMboxMessage_t::MSG_SBE_ERROR) + { + sbeAttemptRecovery(l_hbrt_fw_msg->generic_msg.data); + } + else + { + l_badMessage = true; + + TRACFCOMP(g_trac_runtime, ERR_MRK"firmware_notify: " + "Unknown FSP message type:0x%.8X, " + "message queue id:0x%.8X, seqNum:%d ", + l_hbrt_fw_msg->generic_msg.msgType, + l_hbrt_fw_msg->generic_msg.msgq, + l_hbrt_fw_msg->generic_msg.seqnum); + + // Pack user data 1 with message input type and + // firmware request message sequence number + l_userData1 = TWO_UINT32_TO_UINT64( + l_hbrt_fw_msg->io_type, + l_hbrt_fw_msg->generic_msg.seqnum); + + // Pack user data 2 with message queue and message type + l_userData2 = TWO_UINT32_TO_UINT64( + l_hbrt_fw_msg->generic_msg.msgq, + l_hbrt_fw_msg->generic_msg.msgType); + } // END if ( (l_hbrt_fw_msg->generic_msg.msgType ... else ... + } // END case hostInterfaces::HBRT_FW_MSG_HBRT_FSP_REQ: + break; - break; + case hostInterfaces::HBRT_FW_MSG_TYPE_NVDIMM_OPERATION: + { + uint64_t l_minMsgSize = hostInterfaces::HBRT_FW_MSG_BASE_SIZE + + sizeof(hostInterfaces::hbrt_fw_msg::nvdimm_operation); + if (i_len < l_minMsgSize) + { + l_badMessage = true; + + TRACFCOMP(g_trac_runtime, ERR_MRK"firmware_notify: " + "Received message HBRT_FW_MSG_TYPE_NVDIMM_OPERATION, " + "but size of message data(%d) is not adequate for a " + "complete message of this type, with size requirement of " + "%d", i_len, l_minMsgSize ); + + // Pack user data 1 with the message input type, the only + // data that can be safely retrieved + l_userData1 = l_hbrt_fw_msg->io_type; + + break; + } + + doNvDimmOperation(l_hbrt_fw_msg->nvdimm_operation); + } // END case hostInterfaces::HBRT_FW_MSG_TYPE_NVDIMM_OPERATION: + break; - default: - { - l_badMessage = true; + case hostInterfaces::HBRT_FW_MSG_TYPE_GARD_EVENT: + { + uint64_t l_minMsgSize = hostInterfaces::HBRT_FW_MSG_BASE_SIZE + + sizeof(hostInterfaces::hbrt_fw_msg::gard_event); + if (i_len < l_minMsgSize) + { + l_badMessage = true; + + TRACFCOMP(g_trac_runtime, ERR_MRK"firmware_notify: " + "Received message HBRT_FW_MSG_TYPE_GARD_EVENT, " + "but size of message data(%d) is not adequate for a " + "complete message of this type, with size requirement of " + "%d", i_len, l_minMsgSize ); + + // Pack user data 1 with the message input type, the only + // data that can be safely retrieved + l_userData1 = l_hbrt_fw_msg->io_type; + + break; + } + + logGardEvent(l_hbrt_fw_msg->gard_event); + } // END case hostInterfaces::HBRT_FW_MSG_TYPE_GARD_EVENT: + break; - TRACFCOMP(g_trac_runtime, ERR_MRK"firmware_notify: " - "Unknown firmware request input type:0x%.8X ", - l_hbrt_fw_msg->io_type); + default: + { + l_badMessage = true; - l_userData1 = l_hbrt_fw_msg->io_type; - } // END default + TRACFCOMP(g_trac_runtime, ERR_MRK"firmware_notify: " + "Unknown firmware request input type:0x%.8X ", + l_hbrt_fw_msg->io_type); - break; + l_userData1 = l_hbrt_fw_msg->io_type; + } // END default + break; }; // END switch (l_hbrt_fw_msg->io_type) @@ -463,42 +976,42 @@ void firmware_notify( uint64_t i_len, void *i_data ) if (l_badMessage) { - /*@ - * @errortype - * @severity ERRL_SEV_PREDICTIVE - * @moduleid MOD_RT_FIRMWARE_NOTIFY - * @reasoncode RC_FW_NOTIFY_RT_INVALID_MSG - * @userdata1[0:31] Firmware Request type - * @userdata1[32:63] Sequence number (FSP msg) - * @userdata2[0:31] MBOX message type (FSP msg) - * @userdata2[32:63] Message Type (FSP msg) - * @devdesc Error with Firmware Notify request - */ - l_err = new ErrlEntry(ERRL_SEV_PREDICTIVE, - MOD_RT_FIRMWARE_NOTIFY, - RC_FW_NOTIFY_RT_INVALID_MSG, - l_userData1, - l_userData2, - true); - - if (i_len > 0) - { - l_err->addFFDC(RUNTIME_COMP_ID, - i_data, - i_len, - 0, 0, false ); - } - - l_err->collectTrace( "FW_REQ", 256); + /*@ + * @errortype + * @severity ERRL_SEV_PREDICTIVE + * @moduleid MOD_RT_FIRMWARE_NOTIFY + * @reasoncode RC_FW_NOTIFY_RT_INVALID_MSG + * @userdata1[0:31] Firmware Request type + * @userdata1[32:63] Sequence number (FSP msg) + * @userdata2[0:31] MBOX message type (FSP msg) + * @userdata2[32:63] Message Type (FSP msg) + * @devdesc Error with Firmware Notify request + */ + l_err = new ErrlEntry(ERRL_SEV_PREDICTIVE, + MOD_RT_FIRMWARE_NOTIFY, + RC_FW_NOTIFY_RT_INVALID_MSG, + l_userData1, + l_userData2, + true); + + if (i_len > 0) + { + l_err->addFFDC(RUNTIME_COMP_ID, + i_data, + i_len, + 0, 0, false ); + } + + l_err->collectTrace(RUNTIME_COMP_NAME, 256); } if (l_err) { - //Commit the error if it exists - errlCommit(l_err, RUNTIME_COMP_ID); + //Commit the error if it exists + errlCommit(l_err, RUNTIME_COMP_ID); } - TRACFCOMP(g_trac_hbrt, EXIT_MRK"firmware_notify"); + TRACFCOMP(g_trac_hbrt, EXIT_MRK"firmware_notify"); }; struct registerFwNotify diff --git a/src/usr/util/runtime/rt_fwreq_helper.C b/src/usr/util/runtime/rt_fwreq_helper.C index f94dab238..ce2a1baf6 100644 --- a/src/usr/util/runtime/rt_fwreq_helper.C +++ b/src/usr/util/runtime/rt_fwreq_helper.C @@ -27,6 +27,7 @@ #include <runtime/interface.h> // hostInterfaces #include <runtime/runtime_reasoncodes.H> // MOD_RT_FIRMWARE_REQUEST, etc #include <errl/errlmanager.H> // errlCommit +#include <targeting/common/targetUtil.H> // makeAttribute using namespace ERRORLOG; using namespace RUNTIME; @@ -629,3 +630,285 @@ errlHndl_t firmware_request_helper(uint64_t i_reqLen, void *i_req, return l_err; }; + +/** + * @brief A handy utility to create the firmware request and response + * messages, for FSP, where the messages must be of equal size. + */ +bool createGenericFspMsg(uint32_t i_fspReqPayloadSize, + uint32_t &o_fspMsgSize, + uint64_t &o_requestMsgSize, + hostInterfaces::hbrt_fw_msg* &o_requestMsg, + uint64_t &o_responseMsgSize, + hostInterfaces::hbrt_fw_msg* &o_responseMsg) +{ + // Default the return value to true, assume things will go right + bool l_retVal(true); + + // Do some quick initialization of the output data + o_fspMsgSize = o_requestMsgSize = o_responseMsgSize = 0; + o_requestMsg = o_responseMsg = nullptr; + + // Calculate the total size of the Generic FSP Message. + o_fspMsgSize = GENERIC_FSP_MBOX_MESSAGE_BASE_SIZE + + i_fspReqPayloadSize; + + // The total Generic FSP Message size must be at a minimum the + // size of the FSP generic message (sizeof(GenericFspMboxMessage_t)) + if (o_fspMsgSize < sizeof(GenericFspMboxMessage_t)) + { + o_fspMsgSize = sizeof(GenericFspMboxMessage_t); + } + + // Calculate the total size of the hbrt_fw_msgs which + // means only adding hostInterfaces::HBRT_FW_MSG_BASE_SIZE to + // the previous calculated Generic FSP Message size. + o_requestMsgSize = o_responseMsgSize = + hostInterfaces::HBRT_FW_MSG_BASE_SIZE + o_fspMsgSize; + + // Create the hbrt_fw_msgs + o_responseMsg = reinterpret_cast<hostInterfaces::hbrt_fw_msg *> + (new uint8_t[o_responseMsgSize]); + o_requestMsg = reinterpret_cast<hostInterfaces::hbrt_fw_msg *> + (new uint8_t[o_requestMsgSize]); + + // If any one of these two message's memory can't be allocated, then + // delete both messages (in case one did allocate memory), set both + // messages to NULL pointers and set their respective sizes to zero. + if (!o_responseMsg || !o_requestMsg) + { + // OK to delete a NULL pointer if it happens + delete []o_responseMsg; + delete []o_requestMsg; + + // Return output data zeroed out + o_responseMsg = o_requestMsg = nullptr; + o_fspMsgSize = o_requestMsgSize = o_responseMsgSize = 0; + + // Return false, indicating that this function had an issue creating + // the request and/or response message + l_retVal = false; + } + else + { + // Initialize/zero out hbrt_fw_msgs + o_requestMsg->generic_msg.initialize(); + memset(o_responseMsg, 0, o_responseMsgSize); + + // We can at least set these parameters based on current usage + o_requestMsg->io_type = hostInterfaces::HBRT_FW_MSG_HBRT_FSP_REQ; + o_requestMsg->generic_msg.dataSize = o_fspMsgSize; + o_requestMsg->generic_msg.__req = GenericFspMboxMessage_t::REQUEST; + } + + return l_retVal; +} // end createGenericFspMsg + + +/** + * @brief Serializes a list of Attributes to be sent to FSP + */ +errlHndl_t sendAttributes(const std::vector<TARGETING::AttributeTank::Attribute>& + i_attributeList) +{ + TRACFCOMP(g_trac_runtime, + ENTER_MRK"sendAttributes - number of attributes to send %d", + i_attributeList.size()); + + // Handle to error log + errlHndl_t l_err{nullptr}; + + // Handles to the firmware messages + hostInterfaces::hbrt_fw_msg *l_fwRequestMsg{nullptr}; // request message + hostInterfaces::hbrt_fw_msg *l_fwResponseMsg{nullptr}; // response message + + do + { + // If caller passes in an empty list, then nothing to do + if (!i_attributeList.size()) + { + TRACFCOMP(g_trac_runtime, "sendAttributes: attribute list is " + "empty,nothing to do ..."); + break; + } + + // Make sure we have all of our function pointers setup right + if ((nullptr == g_hostInterfaces) || + (nullptr == g_hostInterfaces->firmware_request)) + { + TRACFCOMP(g_trac_runtime, ERR_MRK"sendAttributes: " + "Hypervisor firmware_request interface not linked"); + + /*@ + * @errortype + * @severity ERRL_SEV_UNRECOVERABLE + * @moduleid MOD_RT_FIRMWARE_REQUEST + * @reasoncode RC_FW_REQUEST_RT_NULL_PTR + * @userdata1 Number of Attributes to serialize and send + * @devdesc Hypervisor firmware request interface not linked + * @custdesc Internal firmware error + */ + l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE, + RUNTIME::MOD_RT_FIRMWARE_REQUEST, + RUNTIME::RC_FW_REQUEST_RT_NULL_PTR, + i_attributeList.size(), + 0, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + + break; + } + + /// Calculate the size requirements needed to serialize + /// the Attribute info + // Aggregate the size of the incoming Attributes + uint32_t l_aggregatedAttributeSize(0); + for (auto l_attribute: i_attributeList) + { + l_aggregatedAttributeSize += l_attribute.getSize(); + } + + // Combine the size of the AttributeSetter_t itself to the size of + // incoming Attributes to get the full size requirement needed + uint32_t l_dataSize(sizeof(AttributeSetter_t) + + l_aggregatedAttributeSize); + + // Create and initialize to zero a few needed variables + uint32_t l_fullFspDataSize(0); + uint64_t l_fwRequestMsgSize(0), l_fwResponseMsgSize(0); + + // Create the dynamic firmware messages + if (!createGenericFspMsg(l_dataSize, + l_fullFspDataSize, + l_fwRequestMsgSize, + l_fwRequestMsg, + l_fwResponseMsgSize, + l_fwResponseMsg) ) + { + TRACFCOMP(g_trac_runtime, ERR_MRK"sendAttributes: " + "Unable to allocate firmware request messages"); + + /*@ + * @errortype + * @severity ERRL_SEV_UNRECOVERABLE + * @moduleid MOD_SEND_ATTRIBUTES_TO_FSP + * @reasoncode RC_NULL_FIRMWARE_MSG_PTR + * @userdata1 Number of Attributes to serialize and send + * @devdesc Unable to allocate firmware request messages + * @custdesc Internal firmware error + */ + l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE, + RUNTIME::MOD_SEND_ATTRIBUTES_TO_FSP, + RUNTIME::RC_NULL_FIRMWARE_MSG_PTR, + i_attributeList.size(), + 0, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + + break; + } + + // Populate the 'message queue' and 'message type' for this message + l_fwRequestMsg->generic_msg.msgq = MBOX::FSP_NVDIMM_KEYS_MSGQ_ID; + l_fwRequestMsg->generic_msg.msgType = + GenericFspMboxMessage_t::MSG_ATTR_WRITE_OP; + + // Create a useful struct to populate the generic_msg::data field + AttributeSetter_t* l_attributeSetter = + reinterpret_cast<AttributeSetter_t*> + (&(l_fwRequestMsg->generic_msg.data)); + + // Initialize the AttributeSetter to default values + l_attributeSetter->initialize(); + + // The number of attributes being copied can be obtained from + // size of the attrbute input list + l_attributeSetter->iv_numAttributes = i_attributeList.size(); + + // Retrieve the individual attributes (header and value) + // Create a useful struct to poulate attribute data + uint8_t* l_attributeData = l_attributeSetter->iv_attrData; + uint32_t l_sizeOfDataCopied(0); + + // Iterate thru the attribute list and serialize the attributes + for (const auto & l_attribute: i_attributeList) + { + if (l_aggregatedAttributeSize >= l_attribute.getSize()) + { + l_sizeOfDataCopied = l_attribute.serialize( + l_attributeData, l_aggregatedAttributeSize); + + if (!l_sizeOfDataCopied) + { + TRACFCOMP(g_trac_runtime, ERR_MRK"sendAttributes: " + "Serialization of an Attribute failed, " + "should never happen") + + /*@ + * @errortype + * @severity ERRL_SEV_UNRECOVERABLE + * @moduleid MOD_SEND_ATTRIBUTES_TO_FSP + * @reasoncode RC_SERIALIZE_ATTRIBUTE_FAILED + * @userdata1 Number of Attributes to serialize and send + * @devdesc Serialization of an Attribute Failed + * @custdesc Internal firmware error + */ + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + RUNTIME::MOD_SEND_ATTRIBUTES_TO_FSP, + RUNTIME::RC_SERIALIZE_ATTRIBUTE_FAILED, + i_attributeList.size(), + 0, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + + break; + } // end if (!l_sizeOfDataCopied) + } + else + { + TRACFCOMP(g_trac_runtime, ERR_MRK"sendAttributes: " + "Miscalculation of aggregated size of attributes, " + "should never happen") + + /*@ + * @errortype + * @severity ERRL_SEV_UNRECOVERABLE + * @moduleid MOD_SEND_ATTRIBUTES_TO_FSP + * @reasoncode RC_NO_SPACE_FOR_ATTRIBUTE_SERIALIZATION + * @userdata1 Number of Attributes to serialize and send + * @devdesc Serialization data of Attribute to large + * for given buffer + * @custdesc Internal firmware error + */ + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + RUNTIME::MOD_SEND_ATTRIBUTES_TO_FSP, + RUNTIME::RC_NO_SPACE_FOR_ATTRIBUTE_SERIALIZATION, + i_attributeList.size(), + 0, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + + break; + } + + // Decrement/increment our counters/pointers + l_aggregatedAttributeSize -= l_sizeOfDataCopied; + l_attributeData += l_sizeOfDataCopied; + } // end for (const auto & l_attribute: i_attributeList) + + // Make the firmware_request call + l_err = firmware_request_helper(l_fwRequestMsgSize, + l_fwRequestMsg, + &l_fwResponseMsgSize, + l_fwResponseMsg); + } while (0); + + // Release the firmware messages and set to NULL + delete []l_fwRequestMsg; + delete []l_fwResponseMsg; + l_fwRequestMsg = l_fwResponseMsg = nullptr; + + TRACFCOMP(g_trac_runtime, EXIT_MRK"sendAttributes - exit with %s", + (nullptr == l_err ? "no error" : "error")); + + + return l_err; +} diff --git a/src/usr/util/runtime/test/testlidmgr_rt.H b/src/usr/util/runtime/test/testlidmgr_rt.H index 36eb8bc64..a6681b37b 100644 --- a/src/usr/util/runtime/test/testlidmgr_rt.H +++ b/src/usr/util/runtime/test/testlidmgr_rt.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014,2016 */ +/* Contributors Listed Below - COPYRIGHT 2014,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -26,7 +26,6 @@ #include <cxxtest/TestSuite.H> #include <errl/errlmanager.H> #include <utilbase.H> -#include <config.h> class LidMgrRtTest : public CxxTest::TestSuite { diff --git a/src/usr/util/runtime/test/testruncommand.H b/src/usr/util/runtime/test/testruncommand.H index 9dbb6b5c0..f6563819e 100644 --- a/src/usr/util/runtime/test/testruncommand.H +++ b/src/usr/util/runtime/test/testruncommand.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -24,7 +24,6 @@ /* IBM_PROLOG_END_TAG */ #include <cxxtest/TestSuite.H> #include <errl/errlmanager.H> -#include <config.h> #include <runtime/interface.h> #include <string.h> #include <stdio.h> diff --git a/src/usr/util/runtime/utillidmgr_rt.C b/src/usr/util/runtime/utillidmgr_rt.C index ad5a7cd48..55bebdeb3 100644 --- a/src/usr/util/runtime/utillidmgr_rt.C +++ b/src/usr/util/runtime/utillidmgr_rt.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2018 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -192,13 +192,24 @@ errlHndl_t UtilLidMgr::loadLid() UTIL_FT(ERR_MRK"UtilLidMgr::loadLid - setheader failed"); break; } - iv_lidSize = l_conHdr.payloadTextSize(); UTIL_FT("UtilLidMgr::loadLid - resv mem section has secure header"); - - // Increment by page size to not expose secure header - iv_lidBuffer = static_cast<uint8_t*>(iv_lidBuffer) + - PAGESIZE; + if (l_conHdr.sb_flags()->sw_hash) + { + // Size of lid has to be size of unprotected data. So we + // need to take out header and hash table sizes + iv_lidSize = l_conHdr.totalContainerSize() - PAGESIZE - + l_conHdr.payloadTextSize(); + iv_lidBuffer = static_cast<uint8_t*>(iv_lidBuffer) + + PAGESIZE + l_conHdr.payloadTextSize(); + } + else + { + iv_lidSize = l_conHdr.payloadTextSize(); + // Increment by page size to not expose secure header + iv_lidBuffer = static_cast<uint8_t*>(iv_lidBuffer) + + PAGESIZE; + } } } else if(iv_isLidInVFS) diff --git a/src/usr/util/test/threadpool.H b/src/usr/util/test/threadpool.H index 9784540a9..7e474b2c3 100644 --- a/src/usr/util/test/threadpool.H +++ b/src/usr/util/test/threadpool.H @@ -5,7 +5,9 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ @@ -25,6 +27,15 @@ #include <cxxtest/TestSuite.H> #include <util/threadpool.H> +#include <errl/errlentry.H> +#include <errl/errlmanager.H> +#include <util/util_reasoncodes.H> +#include <hbotcompid.H> +#include <kernel/console.H> + +// Thread pool constructor flags +#define DISABLE_CHILD_RC_CHECKING false +#define CHECK_CHILD_RC true namespace __ThreadPoolTest { @@ -86,6 +97,17 @@ namespace __ThreadPoolTest uint64_t* iv_value; }; + /** A simple work item that causes the task to crash */ + struct CrashedTask + { + CrashedTask() {}; + void operator()() + { + uint8_t* l_ptr = nullptr; + *l_ptr = 1; + } + }; + }; @@ -96,7 +118,8 @@ class ThreadPoolTest: public CxxTest::TestSuite * ordered pools. */ void testSimpleWorkItem() { - Util::ThreadPool<__ThreadPoolTest::Simple> instance; + Util::ThreadPool<__ThreadPoolTest::Simple> + instance(DISABLE_CHILD_RC_CHECKING); uint64_t value = 0; instance.insert(new __ThreadPoolTest::Simple(&value)); @@ -108,7 +131,8 @@ class ThreadPoolTest: public CxxTest::TestSuite TS_FAIL("Value was not changed by Simple worker thread."); } - Util::ThreadPool<__ThreadPoolTest::SimpleOrdered> instance2; + Util::ThreadPool<__ThreadPoolTest::SimpleOrdered> + instance2(DISABLE_CHILD_RC_CHECKING); value = 0; instance2.insert(new __ThreadPoolTest::SimpleOrdered(&value)); @@ -127,7 +151,8 @@ class ThreadPoolTest: public CxxTest::TestSuite * threads as directed. */ void testThreadManager() { - Util::ThreadPool<__ThreadPoolTest::EnsureThreads> instance; + Util::ThreadPool<__ThreadPoolTest::EnsureThreads> + instance(DISABLE_CHILD_RC_CHECKING); barrier_t barrier; for (size_t count = 1; count < 5; count++) @@ -151,7 +176,8 @@ class ThreadPoolTest: public CxxTest::TestSuite /** Test that the order functions work on the thread pool. */ void testThreadOrder() { - Util::ThreadPool<__ThreadPoolTest::EnsureOrder> instance; + Util::ThreadPool<__ThreadPoolTest::EnsureOrder> + instance(DISABLE_CHILD_RC_CHECKING); uint64_t value = 0; // Ensure that adding work items in order works. @@ -191,6 +217,104 @@ class ThreadPoolTest: public CxxTest::TestSuite instance.start(); instance.shutdown(); } + + /** Test a good child task that doesn't return an error. */ + void testChildRCGoodTask() + { + TS_INFO(ENTER_MRK"testChildRCGoodTask"); + Util::ThreadPool<__ThreadPoolTest::Simple> + l_threadPool(CHECK_CHILD_RC); + uint64_t l_value = 0; + + do { + l_threadPool.insert(new __ThreadPoolTest::Simple(&l_value)); + l_threadPool.start(); + errlHndl_t l_errl = l_threadPool.shutdown(); + if(l_errl) + { + TS_FAIL("testChildRCGoodTask: an unexpected error log (EID 0x%.8%x) returned from the thread pool", l_errl->eid()); + errlCommit(l_errl, CXXTEST_COMP_ID); + break; + } + + if(l_value == 0) + { + TS_FAIL("testChildRCGoodTask: the test value was not changed by the child task"); + break; + } + + }while(0); + TS_INFO(EXIT_MRK"testChildRCGoodTask"); + } + + /** Test that the crashed task's error log is returned to thread pool + correctly */ + void testChildRCCrashedTask() + { + TS_INFO(ENTER_MRK"testChildRCCrashedTask"); + Util::ThreadPool<__ThreadPoolTest::CrashedTask> + l_threadPool(CHECK_CHILD_RC); + errlHndl_t l_errl = nullptr; + + do { + printk("testChildRCCrashedTask: Expect to see uncaught exception\n"); + l_threadPool.insert(new __ThreadPoolTest::CrashedTask()); + l_threadPool.start(); + l_errl = l_threadPool.shutdown(); + if(!l_errl) + { + TS_FAIL("testChildRCCrashedTask: the thread pool did not return an error log as was expected"); + break; + } + + if(l_errl->moduleId() != Util::UTIL_MOD_TP_SHUTDOWN) + { + TS_FAIL("testChildRCCrashedTask: unexpected moduleId returned from EID 0x%.8x; expected: 0x%x; actual: 0x%x", + l_errl->eid(), + Util::UTIL_MOD_TP_SHUTDOWN, + l_errl->moduleId()); + break; + } + + if(l_errl->reasonCode() != Util::UTIL_RC_CHILD_TASK_FAILED) + { + TS_FAIL("testChildRCCrashedTask: unexpected return code from EID 0x%.8x; expected: 0x%x; actual 0x%x", + l_errl->eid(), + Util::UTIL_RC_CHILD_TASK_FAILED, + l_errl->reasonCode()); + break; + } + }while(0); + + if(l_errl) + { + ERRORLOG::errlCommit(l_errl, CXXTEST_COMP_ID); + } + TS_INFO(EXIT_MRK"testChildRCCrashedTask"); + } + + /* Test that error is not returned by crashed task when explicitly + not requested by thread pool */ + void testChildNoRCCrashedTask() + { + TS_INFO(ENTER_MRK"testChildNoRCCrashedTask"); + Util::ThreadPool<__ThreadPoolTest::CrashedTask> + l_threadPool(DISABLE_CHILD_RC_CHECKING); + errlHndl_t l_errl = nullptr; + + printk("testChildNoRCCrashedTask: Expect to see uncaught exception\n"); + l_threadPool.insert(new __ThreadPoolTest::CrashedTask()); + l_threadPool.start(); + l_errl = l_threadPool.shutdown(); + + if(l_errl) + { + TS_FAIL("testChildNoRCCrashedTask: unexpected error returned from the thread pool (EID 0x%.8x)", l_errl->eid()); + ERRORLOG::errlCommit(l_errl, CXXTEST_COMP_ID); + } + + TS_INFO(EXIT_MRK"testChildNoRCCrashedTask"); + } }; #endif diff --git a/src/usr/util/threadpool.C b/src/usr/util/threadpool.C index d2b156839..b51cca642 100644 --- a/src/usr/util/threadpool.C +++ b/src/usr/util/threadpool.C @@ -5,7 +5,9 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ @@ -23,6 +25,9 @@ #include <util/threadpool.H> #include <sys/task.h> #include <sys/misc.h> +#include <util/util_reasoncodes.H> +#include <errl/errlmanager.H> +#include <hbotcompid.H> void Util::__Util_ThreadPool_Impl::ThreadPoolImpl::__init() { @@ -96,10 +101,15 @@ void Util::__Util_ThreadPool_Impl::ThreadPoolImpl::__start( mutex_unlock(&iv_mutex); } -void Util::__Util_ThreadPool_Impl::ThreadPoolImpl::__shutdown() +errlHndl_t Util::__Util_ThreadPool_Impl::ThreadPoolImpl::__shutdown() { mutex_lock(&iv_mutex); + int l_childRc = 0; + void* l_childRetval = nullptr; + errlHndl_t l_origError = nullptr; + errlHndl_t l_errl = nullptr; + // Set shutdown status and signal all children to release from their // condition variable. iv_shutdown = true; @@ -109,14 +119,52 @@ void Util::__Util_ThreadPool_Impl::ThreadPoolImpl::__shutdown() while(!iv_children.empty()) { tid_t child = iv_children.front(); + tid_t l_returnedTid = 0; iv_children.pop_front(); mutex_unlock(&iv_mutex); - task_wait_tid(child, NULL, NULL); // Don't need status. + l_returnedTid = task_wait_tid(child, &l_childRc, &l_childRetval); + if(iv_checkChildRc && + ((l_returnedTid != child) || + (l_childRc != TASK_STATUS_EXITED_CLEAN))) + { + /** + * @errortype + * @moduleid UTIL_MOD_TP_SHUTDOWN + * @reasoncode UTIL_RC_CHILD_TASK_FAILED + * @userdata1 The return code of the child thread + * @userdata2[0:31] The returned task ID of the child thread + * @userdata2[32:63] The original task ID of the child thread + * @devdesc The child thread of a thread pool returned an + * error + * @custdesc A failure occurred during the IPL of the system + */ + l_errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE, + UTIL_MOD_TP_SHUTDOWN, + UTIL_RC_CHILD_TASK_FAILED, + l_childRc, + TWO_UINT32_TO_UINT64(l_returnedTid, + child), + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT + ); + l_errl->collectTrace(UTIL_COMP_NAME); + + if(!l_origError) + { + l_origError = l_errl; + l_errl = nullptr; + } + else + { + l_errl->plid(l_origError->plid()); + errlCommit(l_errl, UTIL_COMP_ID); + } + } mutex_lock(&iv_mutex); } mutex_unlock(&iv_mutex); + return l_origError; } // Default thread count of one per HW thread. diff --git a/src/usr/util/utillidmgr.C b/src/usr/util/utillidmgr.C index da9b26052..05c671fe4 100644 --- a/src/usr/util/utillidmgr.C +++ b/src/usr/util/utillidmgr.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2018 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -37,7 +37,6 @@ #include <sys/mm.h> #include <util/align.H> -#include <config.h> #ifdef CONFIG_SECUREBOOT #include <pnor/pnorif.H> #include <secureboot/service.H> diff --git a/src/usr/util/utillidpnor.C b/src/usr/util/utillidpnor.C index 7e910f6eb..89dc09711 100644 --- a/src/usr/util/utillidpnor.C +++ b/src/usr/util/utillidpnor.C @@ -25,7 +25,6 @@ #include <util/utillidmgr.H> #include <util/utillidpnor.H> -#include <config.h> #include <pnor/pnorif.H> #include <errl/errlmanager.H> @@ -53,10 +52,6 @@ static const PnorLidsMap PnorToLidsMap = { PNOR::OCC, LidAndContainerLid(OCC_LIDID, OCC_CONTAINER_LIDID)}, { PNOR::WOFDATA, LidAndContainerLid(WOF_LIDID, WOF_CONTAINER_LIDID)}, { PNOR::HCODE, LidAndContainerLid(NIMBUS_HCODE_LIDID, HCODE_CONTAINER_LIDID)}, - /* @TODO RTC:177927 - Figure out how to handle different Lids for the - same PNOR section based on chip. - { PNOR::HCODE, LidAndContainerLid(CUMULUS_HCODE_LIDID, HCODE_CONTAINER_LIDID)}, - */ { PNOR::RINGOVD, LidAndContainerLid(HWREFIMG_RINGOVD_LIDID,INVALID_LIDID)}, }; @@ -179,7 +174,13 @@ errlHndl_t UtilLidMgr::getLidPnorSectionInfo(const uint32_t i_lidId, // downstream logic from going past the end of the image. // NOTE: This assumes that any secure lid loaded from PNOR by // UtilLidMgr does not contain an unprotected section - iv_lidPnorInfo.size = iv_lidPnorInfo.secureProtectedPayloadSize; + // In this case of hash tables, we need to load the entire + // partition size because the user data is part of the + // unprotected payload + if (!iv_lidPnorInfo.hasHashTable) + { + iv_lidPnorInfo.size = iv_lidPnorInfo.secureProtectedPayloadSize; + } } #endif #endif diff --git a/src/usr/vfs/vfsrp.C b/src/usr/vfs/vfsrp.C index fde05d820..aaf4aa57d 100644 --- a/src/usr/vfs/vfsrp.C +++ b/src/usr/vfs/vfsrp.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2018 */ +/* Contributors Listed Below - COPYRIGHT 2011,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -45,7 +45,6 @@ #include <secureboot/service.H> #include <secureboot/containerheader.H> #include <kernel/console.H> -#include <config.h> using namespace VFS; @@ -754,7 +753,7 @@ void VfsRp::get_test_modules(std::vector<const char *> & o_list) const VfsSystemModule * vfsItr = (VfsSystemModule *) (iv_pnor_vaddr + VFS_EXTENDED_MODULE_TABLE_OFFSET); - //TRACDCOMP(g_trac_vfs,"finding test modules..."); + TRACFCOMP(g_trac_vfs,"finding test modules..."); while(vfsItr->module[0] != '\0') { @@ -762,7 +761,7 @@ void VfsRp::get_test_modules(std::vector<const char *> & o_list) const { if (NULL != vfsItr->start) { - //TRACDCOMP( g_trac_vfs, "%s",vfsItr->module); + TRACDCOMP( g_trac_vfs, "%s",vfsItr->module); o_list.push_back(vfsItr->module); } } diff --git a/src/usr/vfs/vfsrp.H b/src/usr/vfs/vfsrp.H index ebf9c86fd..7530445c1 100644 --- a/src/usr/vfs/vfsrp.H +++ b/src/usr/vfs/vfsrp.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2017 */ +/* Contributors Listed Below - COPYRIGHT 2011,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ diff --git a/src/usr/vpd/HBconfig b/src/usr/vpd/HBconfig index 0d321192c..86979d7fa 100644 --- a/src/usr/vpd/HBconfig +++ b/src/usr/vpd/HBconfig @@ -1,10 +1,12 @@ config MEMVPD_READ_FROM_PNOR default y + default n if SUPPORT_EEPROM_CACHING help Read memory VPD data from PNOR cache config MEMVPD_READ_FROM_HW default n + default y if SUPPORT_EEPROM_CACHING depends on !PALMETTO_PASS1 help Read memory VPD data from HW resources @@ -17,12 +19,14 @@ config MEMVPD_READ config MEMVPD_WRITE_TO_PNOR default y if MEMVPD_READ_FROM_PNOR + default n if SUPPORT_EEPROM_CACHING depends on MEMVPD_READ_FROM_PNOR help Write memory VPD data to PNOR cache config MEMVPD_WRITE_TO_HW default y if MEMVPD_READ_FROM_HW + default y if SUPPORT_EEPROM_CACHING depends on !PALMETTO_PASS1 && MEMVPD_READ_FROM_HW help Write memory VPD data to HW resources @@ -40,6 +44,7 @@ config PVPD_READ_FROM_PNOR config PVPD_READ_FROM_HW default n + default y if SUPPORT_EEPROM_CACHING help Read Planar VPD data from HW resources @@ -51,17 +56,20 @@ config PVPD_WRITE_TO_PNOR config PVPD_WRITE_TO_HW default y if PVPD_READ_FROM_HW + default y if SUPPORT_EEPROM_CACHING depends on PVPD_READ_FROM_HW help Write Planar VPD data to HW resources config MVPD_READ_FROM_PNOR default y + default n if SUPPORT_EEPROM_CACHING help Read Module VPD data from PNOR cache config MVPD_READ_FROM_HW default n + default y if SUPPORT_EEPROM_CACHING help Read Module VPD data from HW resources @@ -73,11 +81,13 @@ config MVPD_READ config MVPD_WRITE_TO_PNOR default y if MVPD_READ_FROM_PNOR + default n if SUPPORT_EEPROM_CACHING help Write Module VPD data to PNOR cache config MVPD_WRITE_TO_HW default y if MVPD_READ_FROM_HW + default y if SUPPORT_EEPROM_CACHING depends on MVPD_READ_FROM_HW help Write Module VPD data to HW resources @@ -90,11 +100,13 @@ config MVPD_WRITE config DJVPD_READ_FROM_PNOR default y + default n if SUPPORT_EEPROM_CACHING help Read Dimm JEDEC VPD/SPD data from PNOR cache config DJVPD_READ_FROM_HW default n + default y if SUPPORT_EEPROM_CACHING help Read Dimm JEDEC VPD/SPD data from HW resources @@ -106,6 +118,7 @@ config DJVPD_READ config DJVPD_WRITE_TO_PNOR default y if DJVPD_READ_FROM_PNOR + default n if SUPPORT_EEPROM_CACHING help Write Dimm JEDEC VPD/SPD data to PNOR cache diff --git a/src/usr/vpd/cvpd.C b/src/usr/vpd/cvpd.C index 354e76ab9..5b56655f0 100644 --- a/src/usr/vpd/cvpd.C +++ b/src/usr/vpd/cvpd.C @@ -41,7 +41,6 @@ #include <vpd/cvpdenums.H> #include <vpd/vpd_if.H> #include <i2c/eepromif.H> -#include <config.h> #include "cvpd.H" #include "pvpd.H" #include "vpd.H" diff --git a/src/usr/vpd/cvpd.H b/src/usr/vpd/cvpd.H index 31f89b29f..05f09386b 100644 --- a/src/usr/vpd/cvpd.H +++ b/src/usr/vpd/cvpd.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2018 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -40,7 +40,6 @@ #include <vpd/cvpdenums.H> #include "ipvpd.H" -#include <config.h> namespace CVPD { diff --git a/src/usr/vpd/dimmPres.C b/src/usr/vpd/dimmPres.C index a62d31f5e..dad7c027e 100755 --- a/src/usr/vpd/dimmPres.C +++ b/src/usr/vpd/dimmPres.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2016 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] Google Inc. */ /* [+] International Business Machines Corp. */ /* */ @@ -41,7 +41,6 @@ #include <devicefw/driverif.H> #include <vpd/vpdreasoncodes.H> #include <vpd/spdenums.H> -#include <config.h> #include <initservice/initserviceif.H> #include <fsi/fsiif.H> diff --git a/src/usr/vpd/dvpd.C b/src/usr/vpd/dvpd.C index d0238b997..9d3bc796d 100644 --- a/src/usr/vpd/dvpd.C +++ b/src/usr/vpd/dvpd.C @@ -39,7 +39,6 @@ #include <vpd/dvpdenums.H> #include <vpd/vpd_if.H> #include <i2c/eepromif.H> -#include <config.h> #include "dvpd.H" #include "cvpd.H" #include "vpd.H" diff --git a/src/usr/vpd/dvpd.H b/src/usr/vpd/dvpd.H index 92985aebe..7517fce2a 100644 --- a/src/usr/vpd/dvpd.H +++ b/src/usr/vpd/dvpd.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2018 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -40,7 +40,6 @@ #include <vpd/dvpdenums.H> #include "ipvpd.H" -#include <config.h> namespace DVPD { diff --git a/src/usr/vpd/errlud_vpd.C b/src/usr/vpd/errlud_vpd.C index f24a5a030..8030e134c 100644 --- a/src/usr/vpd/errlud_vpd.C +++ b/src/usr/vpd/errlud_vpd.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014 */ +/* Contributors Listed Below - COPYRIGHT 2014,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -61,8 +61,8 @@ UdVpdParms::UdVpdParms( TARGETING::Target * i_target, reallocUsrBuf(sizeof(uint8_t) +sizeof(uint32_t) +sizeof(uint64_t)*3)); - uint32_t tmp64 = 0; - uint16_t tmp32 = 0; + uint64_t tmp64 = 0; + uint32_t tmp32 = 0; uint8_t tmp8 = 0; tmp8 = read_notWrite; @@ -124,8 +124,8 @@ UdConfigParms::UdConfigParms( TARGETING::Target * i_target, char * l_pBuf = reinterpret_cast<char *>( reallocUsrBuf(sizeof(uint32_t) +sizeof(uint64_t)*7)); - uint32_t tmp64 = 0; - uint16_t tmp32 = 0; + uint64_t tmp64 = 0; + uint32_t tmp32 = 0; tmp32 = TARGETING::get_huid(i_target); memcpy(l_pBuf, &tmp32, sizeof(tmp32)); diff --git a/src/usr/vpd/ipvpd.C b/src/usr/vpd/ipvpd.C index 168bc5d36..b38bd77a3 100644 --- a/src/usr/vpd/ipvpd.C +++ b/src/usr/vpd/ipvpd.C @@ -39,7 +39,6 @@ #include <vfs/vfs.H> #include <vpd/vpdreasoncodes.H> #include <vpd/vpd_if.H> -#include <config.h> #include <vpd/ipvpdenums.H> #include <util/utilrsvdmem.H> #include <util/runtime/util_rt.H> @@ -319,6 +318,117 @@ errlHndl_t IpVpdFacade::write ( TARGETING::Target * i_target, } // ------------------------------------------------------------------ +// IpVpdFacade::cmpEecacheToEeprom +// ------------------------------------------------------------------ +errlHndl_t IpVpdFacade::cmpEecacheToEeprom(TARGETING::Target * i_target, + VPD::vpdRecord i_record, + VPD::vpdKeyword i_keyword, + bool & o_match) +{ + errlHndl_t l_err = nullptr; + + TRACSSCOMP(g_trac_vpd, ENTER_MRK"cmpEecacheToEeprom() "); + + o_match = false; + + input_args_t l_cacheArgs; + l_cacheArgs.record = i_record; + l_cacheArgs.keyword = i_keyword; + l_cacheArgs.location = VPD::SEEPROM; + l_cacheArgs.eepromSource = EEPROM::CACHE; + + input_args_t l_hardwareArgs; + l_hardwareArgs.record = i_record; + l_hardwareArgs.keyword = i_keyword; + l_hardwareArgs.location = VPD::SEEPROM; + l_hardwareArgs.eepromSource = EEPROM::HARDWARE; + + do + { + // Get the CACHE size + size_t l_sizeCache = 0; + + l_err = read(i_target, + nullptr, + l_sizeCache, + l_cacheArgs); + + if( l_err || (l_sizeCache == 0) ) + { + TRACFCOMP(g_trac_vpd, + "cmpEecacheToEeprom() an error occurred reading the keyword size in cache"); + break; + } + + // Get the CACHE data + uint8_t l_dataCache[l_sizeCache]; + l_err = read( i_target, + l_dataCache, + l_sizeCache, + l_cacheArgs ); + + if( l_err ) + { + TRACFCOMP(g_trac_vpd, + "cmpEecacheToEeprom() an error occurred reading the keyword in cache"); + break; + } + + // Get the HARDWARE size + size_t l_sizeHardware = 0; + l_err = read( i_target, + nullptr, + l_sizeHardware, + l_hardwareArgs ); + + if( l_err || (l_sizeHardware == 0) ) + { + TRACFCOMP(g_trac_vpd, + "cmpEecacheToEeprom() an error occurred reading the keyword size in hardware"); + break; + } + + // Get the HARDWARE data + uint8_t l_dataHardware[l_sizeHardware]; + l_err = read( i_target, + l_dataHardware, + l_sizeHardware, + l_hardwareArgs ); + + if( l_err ) + { + TRACFCOMP(g_trac_vpd, + "cmpEecacheToEeprom() an error occurred reading the keyword in hardware"); + break; + } + + // Compare the CACHE/HARDWARE keyword size/data + if( l_sizeCache != l_sizeHardware ) + { + // Leave o_match == false since there isn't a match. + break; + } + + if( memcmp( l_dataCache, + l_dataHardware, + l_sizeCache ) != 0 ) + { + TRACFCOMP( g_trac_vpd, "cmpEecacheToEeprom found mismatch for HUID %.8X 0x%X:0x%X", TARGETING::get_huid(i_target), i_record, i_keyword ); + TRACFBIN( g_trac_vpd, "HARDWARE", l_dataHardware, l_sizeHardware ); + TRACFBIN( g_trac_vpd, "CACHE", l_dataCache, l_sizeCache ); + break; + } + + o_match = true; + + } while(0); + + TRACSSCOMP( g_trac_vpd, EXIT_MRK"cmpEecacheToEeprom()" ); + + return l_err; +} + +// ------------------------------------------------------------------ // IpVpdFacade::cmpPnorToSeeprom // ------------------------------------------------------------------ errlHndl_t IpVpdFacade::cmpPnorToSeeprom ( TARGETING::Target * i_target, @@ -885,8 +995,12 @@ errlHndl_t IpVpdFacade::findRecordOffset ( const char * i_record, return err; } - TRACFCOMP( g_trac_vpd, INFO_MRK" Record %s for target 0x%.8X exists at %p in PNOR", + // Don't trace that record exists in PNOR if it does not + if (l_overridePtr != nullptr) + { + TRACFCOMP( g_trac_vpd, INFO_MRK" Record %s for target 0x%.8X exists at %p in PNOR", i_record, get_huid(i_target), l_overridePtr ); + } } // If we have an override, the record is already pointed at directly @@ -1180,7 +1294,7 @@ errlHndl_t IpVpdFacade::findRecordOffsetSeeprom ( const char * i_record, TARGETING::Target * i_target, input_args_t i_args ) { - errlHndl_t err = NULL; + errlHndl_t err = nullptr; char l_buffer[256] = { 0 }; uint16_t offset = 0x0; @@ -1248,6 +1362,12 @@ errlHndl_t IpVpdFacade::findRecordOffsetSeeprom ( const char * i_record, err = retrieveKeyword( "PT", "VTOC", offset, index, i_target, l_buffer, pt_len, i_args ); if ( err ) { + // There may be only one PT record + if (index != 0) + { + delete err; + err = nullptr; + } break; } @@ -1271,7 +1391,7 @@ errlHndl_t IpVpdFacade::findRecordOffsetSeeprom ( const char * i_record, } } - if ( !found && err == NULL ) { + if ( !found && err == nullptr ) { TRACFCOMP( g_trac_vpd, ERR_MRK"IpVpdFacade::findRecordOffsetSeeprom: " "No matching Record (%s) found in VTOC!", i_record ); @@ -1618,6 +1738,36 @@ errlHndl_t IpVpdFacade::retrieveRecord( const char * i_recordName, return err; } + +// ------------------------------------------------------------------ +// IpVpdFacade::fetchData +// ------------------------------------------------------------------ +errlHndl_t IpVpdFacade::fetchData ( uint64_t i_byteAddr, + size_t i_numBytes, + void * o_data, + TARGETING::Target * i_target, + VPD::vpdCmdTarget i_location, + const char* i_record ) +{ + errlHndl_t err = nullptr; + + // Create an input_args struct which will default EEPROM_SOURCE + // to EEPROM::AUTOSELECT. + input_args_t inputArgs; + + // Set the VPD location to the given location (PNOR/SEEPROM). + inputArgs.location = i_location; + + err = fetchData(i_byteAddr, + i_numBytes, + o_data, + i_target, + inputArgs, + i_record); + + return err; +} + // ------------------------------------------------------------------ // IpVpdFacade::fetchData // ------------------------------------------------------------------ @@ -1625,7 +1775,7 @@ errlHndl_t IpVpdFacade::fetchData ( uint64_t i_byteAddr, size_t i_numBytes, void * o_data, TARGETING::Target * i_target, - VPD::vpdCmdTarget i_location, + input_args_t i_args, const char* i_record ) { errlHndl_t err = NULL; @@ -1636,12 +1786,12 @@ errlHndl_t IpVpdFacade::fetchData ( uint64_t i_byteAddr, configError = VPD::resolveVpdSource( i_target, iv_configInfo.vpdReadPNOR, iv_configInfo.vpdReadHW, - i_location, + i_args.location, vpdSource ); // Look for a record override in our image unless explicitly told not to bool l_foundOverride = false; - if( (i_location & VPD::OVERRIDE_MASK) != VPD::USEVPD ) + if( (i_args.location & VPD::OVERRIDE_MASK) != VPD::USEVPD ) { uint8_t* l_overridePtr = nullptr; VPD::RecordTargetPair_t l_recTarg = @@ -1694,7 +1844,11 @@ errlHndl_t IpVpdFacade::fetchData ( uint64_t i_byteAddr, } else if ( (vpdSource == VPD::SEEPROM) && !l_foundOverride ) { - err = fetchDataFromEeprom( i_byteAddr, i_numBytes, o_data, i_target ); + err = fetchDataFromEeprom(i_byteAddr, + i_numBytes, + o_data, + i_target, + i_args.eepromSource); } else { @@ -1723,7 +1877,7 @@ errlHndl_t IpVpdFacade::fetchData ( uint64_t i_byteAddr, VPD::VPD_READ_SOURCE_UNRESOLVED, TWO_UINT32_TO_UINT64( TARGETING::get_huid(i_target), - i_location ), + i_args.location ), TWO_UINT32_TO_UINT64( iv_configInfo.vpdReadPNOR, iv_configInfo.vpdReadHW ), @@ -1777,10 +1931,11 @@ errlHndl_t IpVpdFacade::fetchDataFromPnor ( uint64_t i_byteAddr, // ------------------------------------------------------------------ // IpVpdFacade::fetchDataFromEeprom // ------------------------------------------------------------------ -errlHndl_t IpVpdFacade::fetchDataFromEeprom ( uint64_t i_byteAddr, - size_t i_numBytes, - void * o_data, - TARGETING::Target * i_target ) +errlHndl_t IpVpdFacade::fetchDataFromEeprom(uint64_t i_byteAddr, + size_t i_numBytes, + void * o_data, + TARGETING::Target * i_target, + EEPROM::EEPROM_SOURCE i_eepromSource) { errlHndl_t err = NULL; TRACSSCOMP( g_trac_vpd, @@ -1797,7 +1952,8 @@ errlHndl_t IpVpdFacade::fetchDataFromEeprom ( uint64_t i_byteAddr, i_numBytes, DEVICE_EEPROM_ADDRESS( EEPROM::VPD_PRIMARY, - i_byteAddr, EEPROM::AUTOSELECT ) ); + i_byteAddr, + i_eepromSource ) ); if( err ) { break; @@ -1896,21 +2052,31 @@ errlHndl_t IpVpdFacade::findKeywordAddr ( const char * i_keywordName, offset, i_recordName ); + // convert data for SRC display + uint32_t exp_rec; + memcpy( &exp_rec, i_recordName, RECORD_BYTE_SIZE ); + uint32_t act_rec; + memcpy( &act_rec, record, RECORD_BYTE_SIZE ); + /*@ * @errortype * @reasoncode VPD::VPD_RECORD_MISMATCH * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE * @moduleid VPD::VPD_IPVPD_FIND_KEYWORD_ADDR - * @userdata1 Current offset into VPD - * @userdata2 Start of Record offset + * @userdata1[00:31] Current offset into VPD + * @userdata1[32:63] Start of Record offset + * @userdata2[00:31] Expected record name + * @userdata2[32:63] Found record name * @devdesc Record name does not match value expected for * offset read. */ err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_UNRECOVERABLE, VPD::VPD_IPVPD_FIND_KEYWORD_ADDR, VPD::VPD_RECORD_MISMATCH, - offset, - i_offset ); + TWO_UINT32_TO_UINT64(offset, + i_offset ), + TWO_UINT32_TO_UINT64(exp_rec, + act_rec) ); // Could be the VPD of the target wasn't set up properly // -- DECONFIG so that we can possibly keep booting diff --git a/src/usr/vpd/ipvpd.H b/src/usr/vpd/ipvpd.H index 597c6e256..c47a241a6 100644 --- a/src/usr/vpd/ipvpd.H +++ b/src/usr/vpd/ipvpd.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2018 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] Google Inc. */ /* [+] International Business Machines Corp. */ /* */ @@ -31,9 +31,8 @@ #include <map> #include <pnor/pnorif.H> #include <devicefw/driverif.H> -#include <config.h> #include "vpd.H" - +#include <i2c/eeprom_const.H> /** @file ipvpd.H * @brief Provides base support for i/p-Series style IBM VPD @@ -79,11 +78,35 @@ class IpVpdFacade /** * @brief Structure for all VPD dd input parameter arguments */ - typedef struct + typedef struct device_driver_input_args { - VPD::vpdRecord record; - VPD::vpdKeyword keyword; - VPD::vpdCmdTarget location; + VPD::vpdRecord record; + VPD::vpdKeyword keyword; + VPD::vpdCmdTarget location; + EEPROM::EEPROM_SOURCE eepromSource; + + // Default constructor + device_driver_input_args() : record(0xFFFFFFFF), + keyword(0xFFFFFFFF), + location(VPD::AUTOSELECT), + eepromSource(EEPROM::AUTOSELECT) + {}; + + // This constructor allows for existing code using brace-enclosed + // initializer lists of the first three arguments to continue to + // function normally. Since the default behavior for EEPROM_SOURCE is + // AUTOSELECT, setting it automatically here is done to maintain that + // default assumption. + device_driver_input_args(VPD::vpdRecord i_record, + VPD::vpdKeyword i_keyword, + VPD::vpdCmdTarget i_location) + : record(i_record), + keyword(i_keyword), + location(i_location), + eepromSource(EEPROM::AUTOSELECT) + {}; + + } input_args_t; /** @@ -237,6 +260,28 @@ class IpVpdFacade VPD::vpdRecord record, VPD::vpdKeyword keyword ); + + /** + * @brief This function compares the specified record/keyword + * in CACHE/HARDWARE and returns the result. A mismatch + * will not return an error. + * + * @param[in] i_target Target device + * + * @param[in] i_record Record to compare + * + * @param[in] i_keyword Keyword to compare + * + * @param[out] o_match Result of compare + * + * @return errlHndl_t NULL if successful, otherwise a pointer to the + * error log. + */ + errlHndl_t cmpEecacheToEeprom(TARGETING::Target * i_target, + VPD::vpdRecord i_record, + VPD::vpdKeyword i_keyword, + bool & o_match); + /** * @brief This function compares the specified record/keyword * in PNOR/SEEPROM and returns the result. A mismatch @@ -594,6 +639,8 @@ class IpVpdFacade uint64_t& o_byteAddr, input_args_t i_args ); + + /** * @brief This function calls the PNOR or EEPROM version of * the fetchData function based on the configInfo @@ -613,12 +660,38 @@ class IpVpdFacade * @return errHndl_t - NULL if successful, otherwise a pointer to the * error log. */ - errlHndl_t fetchData ( uint64_t i_byteAddr, - size_t i_numBytes, - void * o_data, - TARGETING::Target * i_target, - VPD::vpdCmdTarget i_location, - const char* i_record ); + errlHndl_t fetchData(uint64_t i_byteAddr, + size_t i_numBytes, + void * o_data, + TARGETING::Target * i_target, + VPD::vpdCmdTarget i_location, + const char* i_record); + + /** + * @brief This function calls the PNOR or EEPROM version of + * the fetchData function based on the configInfo + * + * @param[in] i_byteAddr The offset to be read. + * + * @param[in] i_numBytes The number of bytes to read. + * + * @param[out] o_data The data buffer where the data will be placed. + * + * @param[in] i_target Target device. + * + * @param[in] i_args The input arguments + * + * @param[in] i_record String representation of the record. + * + * @return errHndl_t NULL if successful, otherwise a pointer to the + * error log. + */ + errlHndl_t fetchData(uint64_t i_byteAddr, + size_t i_numBytes, + void * o_data, + TARGETING::Target * i_target, + input_args_t i_args, + const char* i_record); /** * @brief This function actually reads the data from PNOR @@ -653,10 +726,11 @@ class IpVpdFacade * @return errHndl_t - NULL if successful, otherwise a pointer to the * error log. */ - errlHndl_t fetchDataFromEeprom ( uint64_t i_byteAddr, - size_t i_numBytes, - void * o_data, - TARGETING::Target * i_target ); + errlHndl_t fetchDataFromEeprom(uint64_t i_byteAddr, + size_t i_numBytes, + void * o_data, + TARGETING::Target * i_target, + EEPROM::EEPROM_SOURCE i_eepromSource = EEPROM::AUTOSELECT); /** * @brief This function compares 2 ipvpd record values. Used for binary diff --git a/src/usr/vpd/makefile b/src/usr/vpd/makefile index 728750fca..9ef60d788 100644 --- a/src/usr/vpd/makefile +++ b/src/usr/vpd/makefile @@ -31,7 +31,6 @@ include vpd.mk #include unique objects OBJS += vpd.o OBJS += dimmPres.o -OBJS += ocmb_spd.o OBJS += rtvpd_load.o SUBDIRS += test.d diff --git a/src/usr/vpd/mvpd.C b/src/usr/vpd/mvpd.C index 4de720594..242e3bab1 100644 --- a/src/usr/vpd/mvpd.C +++ b/src/usr/vpd/mvpd.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2017 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] Google Inc. */ /* [+] International Business Machines Corp. */ /* */ @@ -38,7 +38,6 @@ #include <vpd/mvpdenums.H> #include <vpd/vpd_if.H> #include <i2c/eepromif.H> -#include <config.h> #include "mvpd.H" #include "ipvpd.H" diff --git a/src/usr/vpd/ocmb_spd.C b/src/usr/vpd/ocmb_spd.C index c4f8137cc..2767efca7 100644 --- a/src/usr/vpd/ocmb_spd.C +++ b/src/usr/vpd/ocmb_spd.C @@ -28,16 +28,24 @@ #include <errl/errlentry.H> #include <vpd/vpdreasoncodes.H> +#include "ocmb_spd.H" +#include "spd.H" +#include "errlud_vpd.H" +#include <vpd/vpd_if.H> + extern trace_desc_t * g_trac_spd; +//#define TRACSSCOMP(args...) TRACFCOMP(args) +#define TRACSSCOMP(args...) + +// Namespace alias for targeting +namespace T = TARGETING; + namespace SPD { /** * @brief Handle SPD READ deviceOp to OCMB_CHIP targets - * This function performs read operations on OCMBs by in turn performing - * an EEPROM deviceOp on this target, reading the first 2 KB of the OCMB's - * Primary VPD eeprom and returning it via a buffer * * @param[in] i_opType Operation type, see driverif.H * @param[in] i_target MMIO target @@ -50,107 +58,327 @@ namespace SPD * In this function, there is one argument, * the l_keyword, so far we only support ENTIRE_SPD * @return errlHndl_t - * - * NOTE: ONLY ENTIRE_SPD READ SUPPORTED CURRENTLY */ errlHndl_t ocmbSPDPerformOp(DeviceFW::OperationType i_opType, - TARGETING::Target* i_target, - void* io_buffer, - size_t& io_buflen, - int64_t i_accessType, - va_list i_args); + T::TargetHandle_t i_target, + void* io_buffer, + size_t& io_buflen, + int64_t i_accessType, + va_list i_args); // Register the perform Op with the routing code for OCMBs. -DEVICE_REGISTER_ROUTE( DeviceFW::READ, - DeviceFW::SPD, - TARGETING::TYPE_OCMB_CHIP, - ocmbSPDPerformOp ); +DEVICE_REGISTER_ROUTE(DeviceFW::READ, + DeviceFW::SPD, + T::TYPE_OCMB_CHIP, + ocmbSPDPerformOp); -/** - * @brief Read keyword from SPD - * - * Currently used to detect I2C_MUTEX and OCMB_CHIP targets - * - * @param[in] i_target OCMB target to read data from - * @param[in] i_keyword keyword from spdenums.H to read - * @param[in/out] io_buffer databuffer SPD will be written to - * @param[in] i_buflen length of the given data buffer - * - * @pre io_buffer and i_target must be non-null - * @pre currenlty only supported value for i_keyword is ENTIRE_SPD - * - * @return errlHndl_t - */ -errlHndl_t ocmbGetSPD(const TARGETING::Target* i_target, - const uint64_t & i_keyword, - void* const io_buffer, - const size_t& i_buflen) +errlHndl_t ocmbGetSPD(T::TargetHandle_t i_target, + void* io_buffer, + size_t& io_buflen, + const VPD::vpdKeyword i_keyword, + const uint8_t i_memType, + EEPROM::EEPROM_SOURCE i_location) { errlHndl_t l_errl = nullptr; - TRACFCOMP( g_trac_spd, - ENTER_MRK"ocmbGetSPD()" ); - - // If any of these asserts fail it is a SW error - assert(io_buffer != nullptr, "io_buffer is nullptr in ocmbGetSPD"); assert(i_target != nullptr, "i_target is nullptr in ocmbGetSPD"); - assert(i_buflen >= SPD::OCMB_SPD_EFD_COMBINED_SIZE, "Buffer must be at least 2 KB in ocmbGetSPD"); do { - if(i_keyword != ENTIRE_SPD) + const KeywordData* entry = nullptr; + l_errl = getKeywordEntry(i_keyword, + i_memType, + i_target, + entry); + if (l_errl != nullptr) + { + break; + } + + // Check to be sure entry is not nullptr. + if (entry == nullptr) { - TRACFCOMP( g_trac_spd, - "ocmbGetSPD() only entire SPD currently supported, 0x%X is not supported", - i_keyword); + TRACFCOMP(g_trac_spd, + ERR_MRK"KeywordData entry pointer is nullptr!"); + /*@ * @errortype - * @moduleid VPD::VPD_OCMB_GET_SPD - * @reasoncode VPD::VPD_NOT_SUPPORTED - * @userdata1 Keyword Enum - * @userdata2 Target huid - * @devdesc Attempted to lookup SPD keyword not supported - * @custdesc Firmware error during system IPL + * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE + * @moduleid VPD::VPD_OCMB_GET_SPD + * @reasoncode VPD::VPD_NULL_ENTRY + * @userdata1[00:31] Buffer Size + * @userdata1[32:63] Memory Type + * @userdata2[00:31] SPD Keyword + * @userdata2[32:63] Target HUID + * @devdesc SPD is not valid for this part + * @custdesc A problem occurred during the IPL + * of the system. */ l_errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE, - VPD::VPD_OCMB_GET_SPD, - VPD::VPD_NOT_SUPPORTED, - i_keyword, - i_target->getAttr<TARGETING::ATTR_HUID>(), - ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + VPD::VPD_OCMB_GET_SPD, + VPD::VPD_NULL_ENTRY, + TWO_UINT32_TO_UINT64(io_buflen, + i_memType), + TWO_UINT32_TO_UINT64(i_keyword, + T::get_huid(i_target)), + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + + l_errl->collectTrace( "SPD", 256); + break; + } + + // Only allow keywords supported by DDIMM + l_errl = checkModSpecificKeyword(*entry, + i_memType, + i_target, + VPD::SEEPROM); + if (l_errl != nullptr) + { + break; + } + + if (entry->isSpecialCase) + { + l_errl = spdSpecialCases(*entry, + io_buffer, + i_target, + i_memType, + VPD::SEEPROM); + if (l_errl != nullptr) + { + break; + } + } + + // Support passing in nullptr buffer to return VPD field size. + if (io_buffer == nullptr) + { + io_buflen = entry->length; + break; } - size_t l_spdReadBufferLen = SPD::OCMB_SPD_EFD_COMBINED_SIZE; - l_errl = DeviceFW::deviceOp(DeviceFW::READ, - const_cast<TARGETING::Target*>(i_target), - io_buffer, - l_spdReadBufferLen, - DEVICE_EEPROM_ADDRESS(EEPROM::VPD_PRIMARY, - 0, - EEPROM::AUTOSELECT) - ); + l_errl = spdCheckSize(io_buflen, + entry->length, + i_keyword); - }while(0); + if (l_errl != nullptr) + { + break; + } + + l_errl = ocmbFetchData(i_target, + entry->offset, + entry->length, + io_buffer, + i_location); + + if (l_errl != nullptr) + { + break; + } + + // Return the size read. + io_buflen = entry->length; + + } while(0); return l_errl; } +// ------------------------------------------------------------------ +// ocmbFetchData +// ------------------------------------------------------------------ +errlHndl_t ocmbFetchData(T::TargetHandle_t i_target, + uint64_t i_byteAddr, + size_t i_numBytes, + void* o_data, + EEPROM::EEPROM_SOURCE i_location) +{ + errlHndl_t err = nullptr; + + TRACSSCOMP(g_trac_spd, + ENTER_MRK"ocmbFetchData()" + " i_byteAddr = 0x%x i_numBytes = %d i_location = 0x%x", + i_byteAddr, i_numBytes, i_location); + + do + { + // Get the data + err = DeviceFW::deviceOp(DeviceFW::READ, + i_target, + o_data, + i_numBytes, + DEVICE_EEPROM_ADDRESS(EEPROM::VPD_PRIMARY, + i_byteAddr, + i_location)); + if( err ) + { + TRACFCOMP(g_trac_spd, + ERR_MRK"ocmbFetchData(): failing out of deviceOp"); + break; + } + + } while(0); + + TRACSSCOMP(g_trac_spd, + EXIT_MRK"ocmbFetchData(): returning %s errors", + ((err != nullptr) ? "with" : "with no") ); + + return err; +} + +// ------------------------------------------------------------------ +// isValidOcmbDimmType +// ------------------------------------------------------------------ +bool isValidOcmbDimmType(const uint8_t i_dimmType) +{ + return ((SPD_DDR4_TYPE == i_dimmType )); +} + +// ------------------------------------------------------------------ +// getMemType +// ------------------------------------------------------------------ +errlHndl_t getMemType(uint8_t& o_memType, + T::TargetHandle_t i_target, + EEPROM::EEPROM_SOURCE i_location) +{ + errlHndl_t err = nullptr; + + err = ocmbFetchData(i_target, + MEM_TYPE_ADDR, + MEM_TYPE_SZ, + &o_memType, + i_location); + + TRACSSCOMP(g_trac_spd, + EXIT_MRK"SPD::getMemType() - MemType: 0x%02x, Error: %s", + o_memType, + ((err != nullptr) ? "Yes" : "No")); + + return err; +} + // See above for details errlHndl_t ocmbSPDPerformOp(DeviceFW::OperationType i_opType, - TARGETING::Target* i_target, + T::TargetHandle_t i_target, void* io_buffer, size_t& io_buflen, int64_t i_accessType, va_list i_args) { - errlHndl_t l_errl = nullptr; - const uint64_t l_keyword = va_arg(i_args, uint64_t); - l_errl = ocmbGetSPD(i_target, l_keyword, io_buffer, io_buflen); - return l_errl; -} + errlHndl_t errl = nullptr; + const uint64_t keyword = va_arg(i_args, uint64_t); + + TRACSSCOMP(g_trac_spd, + ENTER_MRK"ocmbSPDPerformOP(), io_buflen: %d, keyword: 0x%04x", + io_buflen, keyword ); + + do + { + // Read the Basic Memory Type + uint8_t memType(MEM_TYPE_INVALID); + errl = getMemType(memType, i_target, EEPROM::AUTOSELECT); + + if( errl ) + { + break; + } + + TRACSSCOMP(g_trac_spd, + INFO_MRK"Mem Type: %04x", + memType); + + // Check the Basic Memory Type + if (isValidOcmbDimmType(memType)) + { + // If the user wanted the Basic memory type, return this now. + if(BASIC_MEMORY_TYPE == keyword) + { + io_buflen = MEM_TYPE_SZ; + if (io_buffer != nullptr) + { + memcpy(io_buffer, &memType, io_buflen); + } + break; + } + + // Read the keyword value + errl = ocmbGetSPD(i_target, + io_buffer, + io_buflen, + keyword, + memType, + EEPROM::AUTOSELECT); + + if( errl ) + { + break; + } + } + else + { + TRACFCOMP(g_trac_spd, + ERR_MRK"Invalid Basic Memory Type (0x%04x), " + "target huid = 0x%x", + memType, + T::get_huid(i_target)); + + /*@ + * @errlortype + * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE + * @moduleid VPD::VPD_OCMB_SPD_PERFORM_OP + * @reasoncode VPD::VPD_INVALID_BASIC_MEMORY_TYPE + * @userdata1[00:31] Basic Memory Type (Byte 2) + * @userdata1[32:63] Target HUID + * @userdata2 Keyword Requested + * @devdesc Invalid Basic Memory Type + */ + errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE, + VPD::VPD_OCMB_SPD_PERFORM_OP, + VPD::VPD_INVALID_BASIC_MEMORY_TYPE, + TWO_UINT32_TO_UINT64(memType, + T::get_huid(i_target)), + keyword); + // User could have installed a bad/unsupported dimm + errl->addHwCallout(i_target, + HWAS::SRCI_PRIORITY_HIGH, + HWAS::DECONFIG, + HWAS::GARD_NULL); + + errl->addProcedureCallout(HWAS::EPUB_PRC_HB_CODE, + HWAS::SRCI_PRIORITY_LOW); + + errl->addProcedureCallout(HWAS::EPUB_PRC_SP_CODE, + HWAS::SRCI_PRIORITY_LOW); + + errl->collectTrace("SPD", 256); + + break; + } + } while(0); + + // If there is an error, add parameter info to log + if ( errl != nullptr ) + { + VPD::UdVpdParms(i_target, + io_buflen, + 0, + keyword, + true) // read + .addToLog(errl); + } + + TRACSSCOMP(g_trac_spd, + EXIT_MRK"ocmbSPDPerformOP(): returning %s errors", + (errl ? "with" : "with no") ); + + return errl; } + + +} // End of SPD namespace diff --git a/src/usr/vpd/ocmb_spd.H b/src/usr/vpd/ocmb_spd.H new file mode 100644 index 000000000..91123dfd4 --- /dev/null +++ b/src/usr/vpd/ocmb_spd.H @@ -0,0 +1,102 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/vpd/ocmb_spd.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef __OCMB_SPD_H +#define __OCMB_SPD_H + +#include <i2c/eeprom_const.H> + +namespace SPD +{ + +/* + * @brief Read keyword from SPD + * + * @param[in] i_target OCMB target to read data from + * @param[in/out] io_buffer databuffer SPD will be written to + * @param[in/out] io_buflen length of the given data buffer + * @param[in] i_keyword keyword from spdenums.H to read + * @param[in] i_memType The memory type of this target. + * @param[in] i_location The EEPROM source (CACHE/HARDWARE). + * + * @return errlHndl_t nullptr on success. Otherwise, error log. + */ +errlHndl_t ocmbGetSPD(TARGETING::TargetHandle_t i_target, + void* io_buffer, + size_t& io_buflen, + const VPD::vpdKeyword i_keyword, + const uint8_t i_memType, + EEPROM::EEPROM_SOURCE i_location); + +/* + * @brief Determine if the given DIMM type is a known DIMM type or not + * + * @param[in] i_dimmType - The DIMM to verify if valid + * + * @return boolean - return true if given parameter is a known DIMM type, + * false otherwise + */ +bool isValidOcmbDimmType(const uint8_t i_dimmType); + +/* + * @brief This function will read the DIMM memory type for OCMBs. + * + * @param[out] o_memType - The memory type value to return. + * + * @param[in] i_target - The target to read data from. + * + * @param[in] i_eepromSource - The EEPROM source (CACHE/HARDWARE). + * + * @return errlHndl_t - NULL if successful, otherwise a pointer + * to the error log. + */ +errlHndl_t getMemType(uint8_t& o_memType, + TARGETING::TargetHandle_t i_target, + EEPROM::EEPROM_SOURCE i_eepromSource); + +/** + * @param This function is a wrapper for reading the correct keyword. + * + * @param[in] i_target The target DDIMM to access. + * + * @param[in] i_byteAddr The offset into the JEDEC SPD layout. + * + * @param[in] i_numbytes Number of bytes to read. + * + * @param[out] o_data The data buffer that will return the data read. + * + * @param[in] i_location The EEPROM source (CACHE/HARDWARE). + * + * @return errlHndl_t nullptr if successful, otherwise a pointer to the + * error log. + */ +errlHndl_t ocmbFetchData(TARGETING::TargetHandle_t i_target, + uint64_t i_byteAddr, + size_t i_numBytes, + void* o_data, + EEPROM::EEPROM_SOURCE i_location); + +} + +#endif diff --git a/src/usr/vpd/pvpd.C b/src/usr/vpd/pvpd.C index 371a87deb..ae6442554 100644 --- a/src/usr/vpd/pvpd.C +++ b/src/usr/vpd/pvpd.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2018 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -39,9 +39,9 @@ #include <vpd/pvpdenums.H> #include <vpd/vpd_if.H> #include <i2c/eepromif.H> -#include <config.h> #include "pvpd.H" #include "cvpd.H" +#include "dvpd.H" #include "vpd.H" #include <initservice/initserviceif.H> @@ -245,7 +245,7 @@ errlHndl_t nodePresenceDetect(DeviceFW::OperationType i_opType, } pvpd_present = VPD::pvpdPresent( i_target ); -#if(defined( CONFIG_PVPD_READ_FROM_HW ) && !defined( __HOSTBOOT_RUNTIME) ) +#if(defined( CONFIG_PVPD_READ_FROM_HW ) && !defined( __HOSTBOOT_RUNTIME) && defined(CONFIG_PVPD_READ_FROM_PNOR)) if( pvpd_present ) { // Check if the VPD data in the PNOR matches the SEEPROM diff --git a/src/usr/vpd/pvpd.H b/src/usr/vpd/pvpd.H index e3e947521..cd6115c26 100644 --- a/src/usr/vpd/pvpd.H +++ b/src/usr/vpd/pvpd.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2017 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -40,7 +40,6 @@ #include <vpd/pvpdenums.H> #include "ipvpd.H" -#include <config.h> namespace PVPD { diff --git a/src/usr/vpd/rtvpd_load.C b/src/usr/vpd/rtvpd_load.C index 26ad6f031..f12d23d01 100644 --- a/src/usr/vpd/rtvpd_load.C +++ b/src/usr/vpd/rtvpd_load.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2017 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -108,6 +108,7 @@ errlHndl_t VPD::vpd_load_rt_image(uint64_t & i_vpd_addr) do { +#ifndef CONFIG_SUPPORT_EEPROM_CACHING void* vptr = reinterpret_cast<void*>(i_vpd_addr); uint8_t* vpd_ptr = reinterpret_cast<uint8_t*>(vptr); @@ -136,6 +137,21 @@ errlHndl_t VPD::vpd_load_rt_image(uint64_t & i_vpd_addr) { break; } +#else + // In Axone we store all contents of EEPROMs in EECACHE + // so copy the EECACHE pnor section to the space in reserved + // memory allocated for VPD. + void* vptr = reinterpret_cast<void*>(i_vpd_addr); + uint8_t* vpd_ptr = reinterpret_cast<uint8_t*>(vptr); + + err = bld_vpd_image(PNOR::EECACHE, + vpd_ptr, + VMM_RT_VPD_SIZE); + if(err) + { + break; + } +#endif } while( 0 ); diff --git a/src/usr/vpd/runtime/rt_vpd.C b/src/usr/vpd/runtime/rt_vpd.C index ba0335484..ee7fa9f7b 100644 --- a/src/usr/vpd/runtime/rt_vpd.C +++ b/src/usr/vpd/runtime/rt_vpd.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2018 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -34,7 +34,7 @@ #include <util/runtime/rt_fwreq_helper.H> // firmware_request_helper #include <targeting/common/util.H> #include <util/runtime/util_rt.H> -#include <runtime/rt_targeting.H> +#include <targeting/runtime/rt_targeting.H> #include <runtime/interface.h> #include <initservice/initserviceif.H> diff --git a/src/usr/vpd/spd.C b/src/usr/vpd/spd.C index a58398e4a..47dfe0f83 100644 --- a/src/usr/vpd/spd.C +++ b/src/usr/vpd/spd.C @@ -48,10 +48,12 @@ #include <vpd/spdenums.H> #include <algorithm> #include "spd.H" +#include "ocmb_spd.H" #include "spdDDR3.H" #include "spdDDR4.H" +#include "spdDDR4_DDIMM.H" #include "errlud_vpd.H" -#include <config.h> +#include "ocmb_spd.H" // ---------------------------------------------- // Trace definitions @@ -115,12 +117,27 @@ const bool g_usePNOR = true; * * @param[in] i_dimmType - The DIMM to verify if valid * -* @return boolean - return true if given paramter is a known DIMM type, +* @return boolean - return true if given parameter is a known DIMM type, * false otherwise */ bool isValidDimmType ( uint8_t i_dimmType ); /** + * @brief Determines if the given DIMM type is a known DIMM type or not by + * calling the correct isValidDimmType function for OCMB_SPD or SPD. + * + * @param[in] i_dimmType - The DIMM to verify if valid + * + * @param[in] i_eepromType - The eeprom content type of the DIMM + * + * @return boolean - return true if given paramter is a known DIMM type, + * false otherwise + */ +bool isValidDimmType(uint8_t i_dimmType, + TARGETING::EEPROM_CONTENT_TYPE i_eepromType); + + +/** * @brief Compare two values and return whether e2 is greater than * the e1 value. This is used during lower_bound to cut * search time down. @@ -140,18 +157,42 @@ bool compareEntries ( const KeywordData e1, /** * @brief This function will read the DIMM memory type. * - * @param[out] o_memType - The memory type value to return. + * @param[out] o_memType - The memory type value to return. * - * @param[in] i_target - The target to read data from. + * @param[in] i_target - The target to read data from. * - * @param[in] i_location - The SPD source (PNOR/SEEPROM). + * @param[in] i_location - The SPD source (PNOR/SEEPROM). + * + * @param[in] i_eepromSource - The EEPROM source (CACHE/HARDWARE). + * Default to AUTOSELECT. * * @return errlHndl_t - NULL if successful, otherwise a pointer * to the error log. */ -errlHndl_t getMemType ( uint8_t & o_memType, - TARGETING::Target * i_target, - VPD::vpdCmdTarget i_location ); +errlHndl_t getMemType(uint8_t & o_memType, + TARGETING::Target * i_target, + VPD::vpdCmdTarget i_location, + EEPROM::EEPROM_SOURCE i_eepromSource = EEPROM::AUTOSELECT); + +/** + * @brief This function will read the DIMM memory type by calling the correct + * function given the eeprom content type. + * + * @param[out] o_memType - The memory type value to return. + * + * @param[in] i_target - The target to read data from. + * + * @param[in] i_eepromType - The Eeprom content type of the target. + * + * @param[in] i_eepromSource - The EEPROM source (CACHE/HARDWARE). + * + * @return errlHndl_t - NULL if successful, otherwise a pointer + * to the error log. + */ +errlHndl_t getMemType(uint8_t & o_memType, + TARGETING::Target * i_target, + TARGETING::EEPROM_CONTENT_TYPE i_eepromType, + EEPROM::EEPROM_SOURCE i_eepromSource); /** * @brief This function will read the DIMM module type. @@ -173,26 +214,6 @@ errlHndl_t getModType ( modSpecTypes_t & o_modType, VPD::vpdCmdTarget i_location ); /** - * @brief This function will scan the table and return the entry - * corresponding to the keyword being requested. - * - * @param[in] i_keyword - The keyword being requested. - * - * @param[in] i_memType - The memory type of the target. - * - * @param[in] i_target - Target (only used for callouts) - * - * @param[out] o_entry - The table entry corresponding to the keyword. - * - * @return errlHndl_t - NULL if successful, otherwise a pointer to - * the error log. - */ -errlHndl_t getKeywordEntry ( VPD::vpdKeyword i_keyword, - uint64_t i_memType, - TARGETING::Target * i_target, - const KeywordData *& o_entry ); - -/** * @brief This function will set the size of SPD for the given target based on * the DIMM type. * @@ -226,6 +247,29 @@ bool isValidDimmType ( const uint8_t i_dimmType ) ( SPD_DDR4_TYPE == i_dimmType ) ); } + +bool isValidDimmType(uint8_t i_memType, + TARGETING::EEPROM_CONTENT_TYPE i_eepromType) +{ + bool isValid = false; + +// TODO RTC:204341 Add support for reading/write EECACHE during runtime +#ifndef __HOSTBOOT_RUNTIME + if (i_eepromType == TARGETING::EEPROM_CONTENT_TYPE_ISDIMM) + { + isValid = isValidDimmType(i_memType); + } + else if (i_eepromType == TARGETING::EEPROM_CONTENT_TYPE_DDIMM) + { + isValid = isValidOcmbDimmType(i_memType); + } + +#endif + + return isValid; +} + + // ------------------------------------------------------------------ // spdGetKeywordValue // ------------------------------------------------------------------ @@ -456,11 +500,12 @@ errlHndl_t spdWriteKeywordValue ( DeviceFW::OperationType i_opType, // ------------------------------------------------------------------ // spdFetchData // ------------------------------------------------------------------ -errlHndl_t spdFetchData ( uint64_t i_byteAddr, - size_t i_numBytes, - void * o_data, - TARGETING::Target * i_target, - VPD::vpdCmdTarget i_location ) +errlHndl_t spdFetchData ( uint64_t i_byteAddr, + size_t i_numBytes, + void * o_data, + TARGETING::Target * i_target, + VPD::vpdCmdTarget i_location, + EEPROM::EEPROM_SOURCE i_eepromSource) { errlHndl_t err{nullptr}; @@ -516,7 +561,7 @@ errlHndl_t spdFetchData ( uint64_t i_byteAddr, DEVICE_EEPROM_ADDRESS( EEPROM::VPD_PRIMARY, i_byteAddr, - EEPROM::AUTOSELECT) ); + i_eepromSource)); if( err ) { TRACFCOMP(g_trac_spd, @@ -640,12 +685,13 @@ errlHndl_t spdWriteData ( uint64_t i_offset, // ------------------------------------------------------------------ // spdGetValue // ------------------------------------------------------------------ -errlHndl_t spdGetValue ( VPD::vpdKeyword i_keyword, - void * io_buffer, - size_t & io_buflen, - TARGETING::Target * i_target, - uint64_t i_DDRRev, - VPD::vpdCmdTarget i_location ) +errlHndl_t spdGetValue(VPD::vpdKeyword i_keyword, + void * io_buffer, + size_t & io_buflen, + TARGETING::Target * i_target, + uint64_t i_DDRRev, + VPD::vpdCmdTarget i_location, + EEPROM::EEPROM_SOURCE i_eepromSource) { errlHndl_t err{nullptr}; uint8_t * tmpBuffer = static_cast<uint8_t *>(io_buffer); @@ -1247,6 +1293,36 @@ errlHndl_t ddr3SpecialCases(const KeywordData & i_kwdData, return err; } + +errlHndl_t fetchDataFromEepromType(uint64_t i_byteAddr, + size_t i_numBytes, + void * o_data, + TARGETING::Target * i_target, + VPD::vpdCmdTarget i_location, + TARGETING::EEPROM_CONTENT_TYPE i_eepromType) +{ + errlHndl_t errl = nullptr; + + if (i_eepromType == TARGETING::EEPROM_CONTENT_TYPE_ISDIMM) + { + errl = spdFetchData(i_byteAddr, + i_numBytes, + o_data, + i_target, + i_location); + } + else if (i_eepromType == TARGETING::EEPROM_CONTENT_TYPE_DDIMM) + { + errl = ocmbFetchData(i_target, + i_byteAddr, + i_numBytes, + o_data, + EEPROM::AUTOSELECT); + } + + return errl; +} + // ------------------------------------------------------------------ // ddr4SpecialCases // ------------------------------------------------------------------ @@ -1260,6 +1336,12 @@ errlHndl_t ddr4SpecialCases(const KeywordData & i_kwdData, TRACSSCOMP( g_trac_spd, ENTER_MRK"ddr4SpecialCases()" ); + auto eepromVpd = + i_target->getAttr<TARGETING::ATTR_EEPROM_VPD_PRIMARY_INFO>(); + + TARGETING::EEPROM_CONTENT_TYPE eepromType = + static_cast<TARGETING::EEPROM_CONTENT_TYPE>(eepromVpd.eepromContentType); + switch( i_kwdData.keyword ) { // ================================================== @@ -1276,12 +1358,14 @@ errlHndl_t ddr4SpecialCases(const KeywordData & i_kwdData, case RMM_CRC: case MODSPEC_MM_MFR_ID_CODE: case LRMM_CRC: + // Get MSB - err = spdFetchData( i_kwdData.offset, - 1, /* Read 1 byte at a time */ - &tmpBuffer[0], - i_target, - i_location ); + err = fetchDataFromEepromType(i_kwdData.offset, + 1, /* Read 1 byte at a time */ + &tmpBuffer[0], + i_target, + i_location, + eepromType); if( err ) break; @@ -1293,22 +1377,24 @@ errlHndl_t ddr4SpecialCases(const KeywordData & i_kwdData, } // Get LSB - err = spdFetchData( (i_kwdData.offset - 1), - 1, /* Read 1 byte at a time */ - &tmpBuffer[1], - i_target, - i_location ); + err = fetchDataFromEepromType((i_kwdData.offset - 1), + 1, /* Read 1 byte at a time */ + &tmpBuffer[1], + i_target, + i_location, + eepromType); break; // ================================================== // 2 byte - MSB with mask then LSB is 2 more than MSB case TRC_MIN: // Get MSB - err = spdFetchData( i_kwdData.offset, - 1, /* Read 1 byte at a time */ - &tmpBuffer[0], - i_target, - i_location ); + err = fetchDataFromEepromType(i_kwdData.offset, + 1, /* Read 1 byte at a time */ + &tmpBuffer[0], + i_target, + i_location, + eepromType); if( err ) break; @@ -1320,49 +1406,54 @@ errlHndl_t ddr4SpecialCases(const KeywordData & i_kwdData, } // Get LSB - err = spdFetchData( (i_kwdData.offset + 2), - 1, /* Read 1 byte at a time */ - &tmpBuffer[1], - i_target, - i_location ); + err = fetchDataFromEepromType((i_kwdData.offset + 2), + 1, /* Read 1 byte at a time */ + &tmpBuffer[1], + i_target, + i_location, + eepromType); break; // ================================================== // 4 byte - LSB first, no mask case CAS_LATENCIES_SUPPORTED_DDR4: // Get 4th byte - err = spdFetchData( i_kwdData.offset, - 1, /* Read 1 byte at a time */ - &tmpBuffer[0], - i_target, - i_location ); + err = fetchDataFromEepromType(i_kwdData.offset, + 1, /* Read 1 byte at a time */ + &tmpBuffer[0], + i_target, + i_location, + eepromType); if( err ) break; // Get 3rd Byte - err = spdFetchData( (i_kwdData.offset - 1), - 1, /* Read 1 byte at a time */ - &tmpBuffer[1], - i_target, - i_location ); + err = fetchDataFromEepromType((i_kwdData.offset - 1), + 1, /* Read 1 byte at a time */ + &tmpBuffer[1], + i_target, + i_location, + eepromType); if( err ) break; // Get 2nd Byte - err = spdFetchData( (i_kwdData.offset - 2), - 1, /* Read 1 byte at a time */ - &tmpBuffer[2], - i_target, - i_location ); + err = fetchDataFromEepromType((i_kwdData.offset - 2), + 1, /* Read 1 byte at a time */ + &tmpBuffer[2], + i_target, + i_location, + eepromType); if( err ) break; // Get 1st Byte - err = spdFetchData( (i_kwdData.offset - 3), - 1, /* Read 1 byte at a time */ - &tmpBuffer[3], - i_target, - i_location ); + err = fetchDataFromEepromType((i_kwdData.offset - 3), + 1, /* Read 1 byte at a time */ + &tmpBuffer[3], + i_target, + i_location, + eepromType); break; // ================================================== @@ -1685,12 +1776,6 @@ errlHndl_t checkModSpecificKeyword ( KeywordData i_kwdData, do { - // If not a Module Specific keyword, skip this logic - if( NA == i_kwdData.modSpec ) - { - break; - } - // Check that a Module Specific keyword is being accessed from a DIMM // of the correct Module Type. modSpecTypes_t modType = NA; @@ -1701,263 +1786,43 @@ errlHndl_t checkModSpecificKeyword ( KeywordData i_kwdData, break; } - // Check Unbuffered Memory Module (UMM) - if (UMM == modType) - { - if ((UMM != i_kwdData.modSpec) && - (ALL != i_kwdData.modSpec) ) - { - TRACFCOMP( g_trac_spd, ERR_MRK"checkModSpecificKeyword: " - "Keyword (0x%04x) is not valid with UMM modules!", - i_kwdData.keyword ); - /*@ - * @errortype - * @reasoncode VPD::VPD_MOD_SPECIFIC_MISMATCH_UMM - * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE - * @moduleid VPD::VPD_SPD_CHECK_MODULE_SPECIFIC_KEYWORD - * @userdata1[0:31] Module Type (byte 3[3:0]) - * @userdata1[32:63] Memory Type (byte 2) - * @userdata2[0:31] SPD Keyword - * @userdata2[32:63] Module Specific flag - * @devdesc Keyword requested was not UMM Module - * specific. - * @custdesc A problem occurred during the IPL - * of the system. - */ - err = new ERRORLOG::ErrlEntry( - ERRORLOG::ERRL_SEV_UNRECOVERABLE, - VPD::VPD_SPD_CHECK_MODULE_SPECIFIC_KEYWORD, - VPD::VPD_MOD_SPECIFIC_MISMATCH_UMM, - TWO_UINT32_TO_UINT64( modType, i_memType ), - TWO_UINT32_TO_UINT64( i_kwdData.keyword, - i_kwdData.modSpec ) ); - - // HB code asked for an unsupprted keyword for this Module - err->addProcedureCallout(HWAS::EPUB_PRC_HB_CODE, - HWAS::SRCI_PRIORITY_HIGH); - - // Or user could have installed a bad/unsupported dimm - err->addHwCallout( i_target, - HWAS::SRCI_PRIORITY_LOW, - HWAS::DECONFIG, - HWAS::GARD_NULL ); - - err->collectTrace( "SPD", 256); - - break; - } - } - // Check Registered Memory Module (RMM) - else if (RMM == modType) - { - if ((RMM != i_kwdData.modSpec) && - (ALL != i_kwdData.modSpec) ) - { - TRACFCOMP( g_trac_spd, ERR_MRK"checkModSpecificKeyword: " - "Keyword (0x%04x) is not valid with RMM modules!", - i_kwdData.keyword ); - /*@ - * @errortype - * @reasoncode VPD::VPD_MOD_SPECIFIC_MISMATCH_RMM - * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE - * @moduleid VPD::VPD_SPD_CHECK_MODULE_SPECIFIC_KEYWORD - * @userdata1[0:31] Module Type (byte 3[3:0]) - * @userdata1[32:63] Memory Type (byte 2) - * @userdata2[0:31] SPD Keyword - * @userdata2[32:63] Module Specific flag - * @devdesc Keyword requested was not RMM Module - * specific. - * @custdesc A problem occurred during the IPL - * of the system. - */ - err = new ERRORLOG::ErrlEntry( - ERRORLOG::ERRL_SEV_UNRECOVERABLE, - VPD::VPD_SPD_CHECK_MODULE_SPECIFIC_KEYWORD, - VPD::VPD_MOD_SPECIFIC_MISMATCH_RMM, - TWO_UINT32_TO_UINT64( modType, i_memType ), - TWO_UINT32_TO_UINT64( i_kwdData.keyword, - i_kwdData.modSpec ) ); - - // HB code asked for an unsupprted keyword for this Module - err->addProcedureCallout(HWAS::EPUB_PRC_HB_CODE, - HWAS::SRCI_PRIORITY_HIGH); - - // Or user could have installed a bad/unsupported dimm - err->addHwCallout( i_target, - HWAS::SRCI_PRIORITY_LOW, - HWAS::DECONFIG, - HWAS::GARD_NULL ); - - err->collectTrace( "SPD", 256); - - break; - } - } - // Check Clocked Memory Module (CMM) - else if (CMM == modType) - { - if ((CMM != i_kwdData.modSpec) && - (ALL != i_kwdData.modSpec) ) - { - TRACFCOMP( g_trac_spd, ERR_MRK"checkModSpecificKeyword: " - "Keyword (0x%04x) is not valid with CMM modules!", - i_kwdData.keyword ); - /*@ - * @errortype - * @reasoncode VPD::VPD_MOD_SPECIFIC_MISMATCH_CMM - * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE - * @moduleid VPD::VPD_SPD_CHECK_MODULE_SPECIFIC_KEYWORD - * @userdata1[0:31] Module Type (byte 3[3:0]) - * @userdata1[32:63] Memory Type (byte 2) - * @userdata2[0:31] SPD Keyword - * @userdata2[32:63] Module Specific flag - * @devdesc Keyword requested was not CMM Module - * specific. - * @custdesc A problem occurred during the IPL - * of the system. - */ - err = new ERRORLOG::ErrlEntry( - ERRORLOG::ERRL_SEV_UNRECOVERABLE, - VPD::VPD_SPD_CHECK_MODULE_SPECIFIC_KEYWORD, - VPD::VPD_MOD_SPECIFIC_MISMATCH_CMM, - TWO_UINT32_TO_UINT64( modType, i_memType ), - TWO_UINT32_TO_UINT64( i_kwdData.keyword, - i_kwdData.modSpec ) ); - - // HB code asked for an unsupprted keyword for this Module - err->addProcedureCallout(HWAS::EPUB_PRC_HB_CODE, - HWAS::SRCI_PRIORITY_HIGH); - - // Or user could have installed a bad/unsupported dimm - err->addHwCallout( i_target, - HWAS::SRCI_PRIORITY_LOW, - HWAS::DECONFIG, - HWAS::GARD_NULL ); - - err->collectTrace( "SPD", 256); - - break; - } - } - // Check Load Reduction Memory Module (LRMM) - else if (LRMM == modType) - { - if ((LRMM != i_kwdData.modSpec) && - (ALL != i_kwdData.modSpec) ) - { - TRACFCOMP( g_trac_spd, ERR_MRK"checkModSpecificKeyword: " - "Keyword (0x%04x) is not valid with LRMM modules!", - i_kwdData.keyword ); - /*@ - * @errortype - * @reasoncode VPD::VPD_MOD_SPECIFIC_MISMATCH_LRMM - * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE - * @moduleid VPD::VPD_SPD_CHECK_MODULE_SPECIFIC_KEYWORD - * @userdata1[0:31] Module Type (byte 3[3:0]) - * @userdata1[32:63] Memory Type (byte 2) - * @userdata2[0:31] SPD Keyword - * @userdata2[32:63] Module Specific flag - * @devdesc Keyword requested was not LRMM Module - * specific. - * @custdesc A problem occurred during the IPL - * of the system. - */ - err = new ERRORLOG::ErrlEntry( - ERRORLOG::ERRL_SEV_UNRECOVERABLE, - VPD::VPD_SPD_CHECK_MODULE_SPECIFIC_KEYWORD, - VPD::VPD_MOD_SPECIFIC_MISMATCH_LRMM, - TWO_UINT32_TO_UINT64( modType, i_memType ), - TWO_UINT32_TO_UINT64( i_kwdData.keyword, - i_kwdData.modSpec ) ); - - // HB code asked for an unsupprted keyword for this Module - err->addProcedureCallout(HWAS::EPUB_PRC_HB_CODE, - HWAS::SRCI_PRIORITY_HIGH); - - // Or user could have installed a bad/unsupported dimm - err->addHwCallout( i_target, - HWAS::SRCI_PRIORITY_LOW, - HWAS::DECONFIG, - HWAS::GARD_NULL ); - - err->collectTrace( "SPD", 256); - - break; - } - } - else if(DDIMM == modType) - { - if ((DDIMM != i_kwdData.modSpec) && - (ALL != i_kwdData.modSpec) ) - { - TRACFCOMP( g_trac_spd, ERR_MRK"checkModSpecificKeyword: " - "Keyword (0x%04x) is not valid with DDIMM modules!", - i_kwdData.keyword ); - /*@ - * @errortype - * @reasoncode VPD::VPD_MOD_SPECIFIC_MISMATCH_DDIMM - * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE - * @moduleid VPD::VPD_SPD_CHECK_MODULE_SPECIFIC_KEYWORD - * @userdata1[0:31] Module Type (byte 3[3:0]) - * @userdata1[32:63] Memory Type (byte 2) - * @userdata2[0:31] SPD Keyword - * @userdata2[32:63] Module Specific flag - * @devdesc Keyword requested was not LRMM Module - * specific. - * @custdesc A problem occurred during the IPL - * of the system. - */ - err = new ERRORLOG::ErrlEntry( - ERRORLOG::ERRL_SEV_UNRECOVERABLE, - VPD::VPD_SPD_CHECK_MODULE_SPECIFIC_KEYWORD, - VPD::VPD_MOD_SPECIFIC_MISMATCH_DDIMM, - TWO_UINT32_TO_UINT64( modType, i_memType ), - TWO_UINT32_TO_UINT64( i_kwdData.keyword, - i_kwdData.modSpec ) ); - - // HB code asked for an unsupprted keyword for this Module - err->addProcedureCallout(HWAS::EPUB_PRC_HB_CODE, - HWAS::SRCI_PRIORITY_HIGH); - - // Or user could have installed a bad/unsupported dimm - err->addHwCallout( i_target, - HWAS::SRCI_PRIORITY_LOW, - HWAS::DECONFIG, - HWAS::GARD_NULL ); - - err->collectTrace( "SPD", 256); - - break; - } - } - else + if (!(modType & i_kwdData.modSpec)) { TRACFCOMP( g_trac_spd, ERR_MRK"checkModSpecificKeyword: " "Module specific keyword could not be matched with an " "appropriate scenario!" ); + TRACFCOMP( g_trac_spd, ERR_MRK " Mem Type: 0x%04x, Mod Type: 0x%04x, Keyword: 0x%04x", i_memType, modType, i_kwdData.keyword ); + + uint32_t udUpper32 = TWO_UINT16_TO_UINT32(modType, i_memType); + uint32_t udLower32 = TWO_UINT16_TO_UINT32(i_kwdData.keyword, + i_kwdData.modSpec); + uint64_t userdata1 = TWO_UINT32_TO_UINT64(udUpper32, udLower32); + /*@ * @errortype - * @reasoncode VPD::VPD_MOD_SPECIFIC_UNSUPPORTED * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE * @moduleid VPD::VPD_SPD_CHECK_MODULE_SPECIFIC_KEYWORD - * @userdata1 Module Type - * @userdata2 Memory Type (byte 2) + * @reasoncode VPD::VPD_MOD_SPECIFIC_UNSUPPORTED + * @userdata1[00:15] Memory Module Type + * @userdata1[16:31] Memory Type (byte 2) + * @userdata1[32:47] SPD Keyword + * @userdata1[48:63] Module Specific Flag + * @userdata2 Target HUID * @devdesc Unsupported Module Type. * @custdesc A problem occurred during the IPL * of the system. */ err = new ERRORLOG::ErrlEntry( - ERRORLOG::ERRL_SEV_UNRECOVERABLE, - VPD::VPD_SPD_CHECK_MODULE_SPECIFIC_KEYWORD, - VPD::VPD_MOD_SPECIFIC_UNSUPPORTED, - TWO_UINT32_TO_UINT64( modType, i_memType ), - TWO_UINT32_TO_UINT64( i_kwdData.keyword, - i_kwdData.modSpec ) ); + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + VPD::VPD_SPD_CHECK_MODULE_SPECIFIC_KEYWORD, + VPD::VPD_MOD_SPECIFIC_UNSUPPORTED, + userdata1, + TARGETING::get_huid(i_target)); // HB code asked for an unsupprted keyword for this Module err->addProcedureCallout(HWAS::EPUB_PRC_HB_CODE, @@ -1987,9 +1852,10 @@ errlHndl_t checkModSpecificKeyword ( KeywordData i_kwdData, // ------------------------------------------------------------------ // getMemType // ------------------------------------------------------------------ -errlHndl_t getMemType ( uint8_t & o_memType, - TARGETING::Target * i_target, - VPD::vpdCmdTarget i_location ) +errlHndl_t getMemType(uint8_t & o_memType, + TARGETING::Target * i_target, + VPD::vpdCmdTarget i_location, + EEPROM::EEPROM_SOURCE i_eepromSource) { errlHndl_t err{nullptr}; @@ -1997,7 +1863,8 @@ errlHndl_t getMemType ( uint8_t & o_memType, MEM_TYPE_SZ, &o_memType, i_target, - i_location ); + i_location, + i_eepromSource); TRACUCOMP( g_trac_spd, EXIT_MRK"SPD::getMemType() - MemType: 0x%02x, Error: %s", @@ -2007,6 +1874,57 @@ errlHndl_t getMemType ( uint8_t & o_memType, return err; } + +errlHndl_t getMemType(uint8_t & o_memType, + TARGETING::Target * i_target, + TARGETING::EEPROM_CONTENT_TYPE i_eepromType, + EEPROM::EEPROM_SOURCE i_eepromSource) +{ + errlHndl_t err = nullptr; + +// @TODO RTC 204341 Implement for runtime +#ifndef __HOSTBOOT_RUNTIME + + if (i_eepromType == TARGETING::EEPROM_CONTENT_TYPE_ISDIMM) + { + err = getMemType(o_memType, + i_target, + VPD::AUTOSELECT, + i_eepromSource); + } + else if (i_eepromType == TARGETING::EEPROM_CONTENT_TYPE_DDIMM) + { + err = getMemType(o_memType, + i_target, + i_eepromSource); + } + else + { + /*@ + * @errortype + * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE + * @moduleid VPD::VPD_GET_MEMTYPE + * @reasoncode VPD::VPD_INVALID_EEPROM_CONTENT_TYPE + * @userdata1 Eeprom Content Type Given + * @userdata2 Target HUID + * @devdesc An unsupported eeprom content type was supplied. + * @custdesc A problem occurred during the IPL + * of the system. + */ + err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE, + VPD::VPD_GET_MEMTYPE, + VPD::VPD_INVALID_EEPROM_CONTENT_TYPE, + i_eepromType, + TARGETING::get_huid(i_target), + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + } + +#endif + + return err; + +} + // ------------------------------------------------------------------ // getModType // ------------------------------------------------------------------ @@ -2018,12 +1936,19 @@ errlHndl_t getModType ( modSpecTypes_t & o_modType, errlHndl_t err{nullptr}; o_modType = NA; + auto eepromVpd = + i_target->getAttr<TARGETING::ATTR_EEPROM_VPD_PRIMARY_INFO>(); + + TARGETING::EEPROM_CONTENT_TYPE eepromType = + static_cast<TARGETING::EEPROM_CONTENT_TYPE>(eepromVpd.eepromContentType); + uint8_t modTypeVal = 0; - err = spdFetchData( MOD_TYPE_ADDR, - MOD_TYPE_SZ, - &modTypeVal, - i_target, - i_location ); + err = fetchDataFromEepromType(MOD_TYPE_ADDR, + MOD_TYPE_SZ, + &modTypeVal, + i_target, + i_location, + eepromType); if (err) { @@ -2145,8 +2070,18 @@ errlHndl_t getKeywordEntry ( VPD::vpdKeyword i_keyword, } else if ( SPD_DDR4_TYPE == i_memType ) { - arraySize = (sizeof(ddr4Data)/sizeof(ddr4Data[0])); - kwdData = ddr4Data; + modSpecTypes_t modType = NA; + err = getModType(modType, i_target, i_memType, VPD::AUTOSELECT); + if (modType == DDIMM) + { + arraySize = (sizeof(ddr4DDIMMData)/sizeof(ddr4DDIMMData[0])); + kwdData = ddr4DDIMMData; + } + else + { + arraySize = (sizeof(ddr4Data)/sizeof(ddr4Data[0])); + kwdData = ddr4Data; + } } else { @@ -2354,6 +2289,214 @@ void setPartAndSerialNumberAttributes( TARGETING::Target * i_target ) TRACSSCOMP(g_trac_spd, EXIT_MRK"spd.C::setPartAndSerialNumberAttributes()"); } +/* + * @brief Read keyword from SPD by determining which function to call based on + * eeprom content type. + * + * @param[in] i_target target to read data from + * @param[in] i_eepromType Eeprom content type of the target. + * @param[in] i_keyword keyword from spdenums.H to read + * @param[in] i_memType The memory type of this target. + * @param[in/out] io_buffer data buffer SPD will be written to + * @param[in/out] io_buflen length of the given data buffer + * @param[in] i_eepromSource The EEPROM source (CACHE/HARDWARE). + * + * + * @return errlHndl_t nullptr on success. Otherwise, error log. + */ +errlHndl_t readFromEepromSource(TARGETING::Target* i_target, + TARGETING::EEPROM_CONTENT_TYPE i_eepromType, + const VPD::vpdKeyword i_keyword, + const uint8_t i_memType, + void* io_buffer, + size_t& io_buflen, + EEPROM::EEPROM_SOURCE i_eepromSource) +{ + errlHndl_t err = nullptr; + + TRACSSCOMP(g_trac_spd, ENTER_MRK + "readFromEepromSource: i_eepromSource %d , i_memType %d, i_eepromType %d", + i_eepromSource, i_memType, i_eepromType); + +// @TODO RTC 204341 Implement for runtime +#ifndef __HOSTBOOT_RUNTIME + if (i_eepromType == TARGETING::EEPROM_CONTENT_TYPE_ISDIMM) + { + err = spdGetValue(i_keyword, + io_buffer, + io_buflen, + i_target, + i_memType, + VPD::SEEPROM, + i_eepromSource); + } + else if (i_eepromType == TARGETING::EEPROM_CONTENT_TYPE_DDIMM) + { + err = ocmbGetSPD(i_target, + io_buffer, + io_buflen, + i_keyword, + i_memType, + i_eepromSource); + } + else + { + /*@ + * @errortype + * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE + * @moduleid VPD::VPD_READ_FROM_EEPROM_SOURCE + * @reasoncode VPD::VPD_INVALID_EEPROM_CONTENT_TYPE + * @userdata1 Eeprom Content Type Given + * @userdata2 Target HUID + * @devdesc An unsupported eeprom content type was supplied. + * @custdesc A problem occurred during the IPL + * of the system. + */ + err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE, + VPD::VPD_READ_FROM_EEPROM_SOURCE, + VPD::VPD_INVALID_EEPROM_CONTENT_TYPE, + i_eepromType, + TARGETING::get_huid(i_target), + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + } +#endif + + return err; +} + + +// ------------------------------------------------------------------ +// cmpEecacheToEeprom +// ------------------------------------------------------------------ +errlHndl_t cmpEecacheToEeprom(TARGETING::Target * i_target, + TARGETING::EEPROM_CONTENT_TYPE i_eepromType, + VPD::vpdKeyword i_keyword, + bool &o_match) +{ + errlHndl_t err = nullptr; + + TRACSSCOMP(g_trac_spd, ENTER_MRK"cmpEecacheToEeprom()"); + + o_match = false; + do + { + // Read the Basic Memory Type from the Eeprom Cache + uint8_t memTypeCache(MEM_TYPE_INVALID); + err = getMemType(memTypeCache, + i_target, + i_eepromType, + EEPROM::CACHE); + if (err) + { + break; + } + + if (!isValidDimmType(memTypeCache, i_eepromType)) + { + TRACFCOMP(g_trac_spd, ERR_MRK + "cmpEecacheToEeprom() Invalid DIMM type found in cache copy of eeprom," + " we will not be able to understand contents"); + break; + } + + // Read the Basic Memory Type from HARDWARE + uint8_t memTypeHardware(MEM_TYPE_INVALID); + err = getMemType(memTypeHardware, + i_target, + i_eepromType, + EEPROM::HARDWARE); + if (err) + { + break; + } + + if (!isValidDimmType(memTypeHardware, i_eepromType)) + { + // Leave o_match == false and exit. + TRACFCOMP(g_trac_spd, ERR_MRK"cmpEecacheToEeprom() Invalid DIMM type found in hw copy of eeprom"); + break; + } + + if (memTypeCache != memTypeHardware) + { + // CACHE and HARDWARE don't match. + // Leave o_match == false and exit. + break; + } + + // Get the keyword size + const KeywordData* entry = nullptr; + err = getKeywordEntry(i_keyword, + memTypeHardware, + i_target, + entry); + if (err) + { + break; + } + size_t dataSize = entry->length; + + + // Read the keyword from HARDWARE + size_t sizeHardware = dataSize; + uint8_t dataHardware[sizeHardware]; + err = readFromEepromSource(i_target, + i_eepromType, + i_keyword, + memTypeHardware, + dataHardware, + sizeHardware, + EEPROM::HARDWARE); + if (err) + { + break; + } + + // Read the keyword from CACHE + size_t sizeCache = dataSize; + uint8_t dataCache[sizeCache]; + err = readFromEepromSource(i_target, + i_eepromType, + i_keyword, + memTypeHardware, + dataCache, + sizeCache, + EEPROM::CACHE); + if (err) + { + // CACHE may not be loaded, ignore the error + delete err; + err = NULL; + break; + } + + // Compare the HARDWARE/CACHE keyword size/data + if (sizeHardware != sizeCache) + { + // CACHE and HARDWARE don't match. + // Leave o_match == false and exit. + break; + } + if (memcmp(dataHardware, dataCache, sizeHardware)) + { + // CACHE and HARDWARE don't match. + // Leave o_match == false and exit. + break; + } + + o_match = true; + + } while(0); + + TRACDBIN(g_trac_spd, "Hardware data : ", dataHardware, sizeHardware); + TRACDBIN(g_trac_spd, "Cache data : ", dataCache, sizeCache); + + TRACSSCOMP( g_trac_spd, EXIT_MRK"cmpEecacheToEeprom(): returning %s errors. o_match = 0x%X ", + (err ? "with" : "with no"), o_match ); + + return err; + } + // ------------------------------------------------------------------ // cmpPnorToSeeprom // ------------------------------------------------------------------ @@ -2368,17 +2511,37 @@ errlHndl_t cmpPnorToSeeprom ( TARGETING::Target * i_target, o_match = false; do { - // Read the Basic Memory Type - uint8_t memType(MEM_TYPE_INVALID); - err = getMemType( memType, + // Read the Basic Memory Type from the Seeprom + uint8_t memTypeSeeprom(MEM_TYPE_INVALID); + err = getMemType( memTypeSeeprom, i_target, - VPD::AUTOSELECT ); + VPD::SEEPROM ); if( err ) { break; } - if( false == isValidDimmType(memType) ) + if( false == isValidDimmType(memTypeSeeprom) ) + { + break; + } + + // Read the Basic Memory Type from PNOR + uint8_t memTypePnor(MEM_TYPE_INVALID); + err = getMemType( memTypePnor, + i_target, + VPD::PNOR ); + if( err ) + { + break; + } + + if( false == isValidDimmType(memTypePnor) ) + { + break; + } + + if (memTypeSeeprom != memTypePnor) { break; } @@ -2386,7 +2549,7 @@ errlHndl_t cmpPnorToSeeprom ( TARGETING::Target * i_target, // Get the keyword size const KeywordData* entry = NULL; err = getKeywordEntry( i_keyword, - memType, + memTypePnor, i_target, entry ); if( err ) @@ -2403,7 +2566,7 @@ errlHndl_t cmpPnorToSeeprom ( TARGETING::Target * i_target, dataPnor, sizePnor, i_target, - memType, + memTypePnor, VPD::PNOR ); if( err ) { @@ -2420,7 +2583,7 @@ errlHndl_t cmpPnorToSeeprom ( TARGETING::Target * i_target, dataSeeprom, sizeSeeprom, i_target, - memType, + memTypePnor, VPD::SEEPROM ); if( err ) { diff --git a/src/usr/vpd/spd.H b/src/usr/vpd/spd.H index edf7d74c7..f0e1a157b 100755 --- a/src/usr/vpd/spd.H +++ b/src/usr/vpd/spd.H @@ -39,6 +39,8 @@ #include <errl/errlentry.H> #include <vpd/spdenums.H> #include "vpd.H" +#include <attributeenums.H> +#include <i2c/eeprom_const.H> namespace SPD { @@ -94,13 +96,13 @@ enum */ typedef enum { - NA = 0x00, - UMM = 0x01, // Unbuffered Memory Modules - RMM = 0x02, // Registered Memory Modules - CMM = 0x04, // Clocked Memory Modules - LRMM = 0x08, // Load Reduction Memory Modules - DDIMM = 0x0A, - ALL = 0xFFFF, + NA = 0x00, // Invalid Type + UMM = 0x01, // Unbuffered Memory Modules + RMM = 0x02, // Registered Memory Modules + CMM = 0x04, // Clocked Memory Modules + LRMM = 0x08, // Load Reduction Memory Modules + DDIMM = 0x10, // Differential DIMM + ALL = 0xFFFF, } modSpecTypes_t; @@ -202,14 +204,19 @@ errlHndl_t spdWriteKeywordValue ( DeviceFW::OperationType i_opType, * * @param[in] i_location - The SPD source (PNOR/SEEPROM). * + * @param[in] i_eepromSource Eeprom source (CACHE/HARDWARE). + * Default AUTOSELECT + * * @return errlHndl_t - NULL if successful, otherwise a pointer to the * error log. */ -errlHndl_t spdFetchData ( uint64_t i_byteAddr, - size_t i_numBytes, - void * o_data, - TARGETING::Target * i_target, - VPD::vpdCmdTarget i_location ); +errlHndl_t spdFetchData(uint64_t i_byteAddr, + size_t i_numBytes, + void * o_data, + TARGETING::Target * i_target, + VPD::vpdCmdTarget i_location, + EEPROM::EEPROM_SOURCE i_eepromSource = EEPROM::AUTOSELECT + ); /** * @brief This function is a wrapper for writing the correct keyword. @@ -254,15 +261,20 @@ errlHndl_t spdWriteData ( uint64_t i_offset, * * @param[in] i_location - The SPD source (PNOR/SEEPROM). * + * @param[in] i_eepromSource The eeprom source (CACHE/HARDWARE). + * Default AUTOSELECT + * * @return errlHndl_t - NULL if successful, otherwise a pointer to the * error log. */ -errlHndl_t spdGetValue ( VPD::vpdKeyword i_keyword, - void * io_buffer, - size_t & io_buflen, - TARGETING::Target * i_target, - uint64_t i_DDRRev, - VPD::vpdCmdTarget i_location ); +errlHndl_t spdGetValue(VPD::vpdKeyword i_keyword, + void * io_buffer, + size_t & io_buflen, + TARGETING::Target * i_target, + uint64_t i_DDRRev, + VPD::vpdCmdTarget i_location, + EEPROM::EEPROM_SOURCE i_eepromSource = EEPROM::AUTOSELECT + ); /** @@ -392,6 +404,45 @@ errlHndl_t dimmPresenceDetect( DeviceFW::OperationType i_opType, int64_t i_accessType, va_list i_args ); + +/** + * @brief This function will read the DIMM module type. + * + * @param[out] o_modType - The module type value to return. + * + * @param[in] i_target - The target to read data from. + * + * @param[in] i_memType - The memory type + * + * @param[in] i_location - The SPD source (PNOR/SEEPROM). + * + * @return errlHndl_t - NULL if successful, otherwise a pointer + * to the error log. + */ +errlHndl_t getModType ( modSpecTypes_t & o_modType, + TARGETING::Target * i_target, + uint64_t i_memType, + VPD::vpdCmdTarget i_location ); + +/** + * @brief This function will scan the table and return the entry + * corresponding to the keyword being requested. + * + * @param[in] i_keyword - The keyword being requested. + * + * @param[in] i_memType - The memory type of the target. + * + * @param[in] i_target - Target (only used for callouts) + * + * @param[out] o_entry - The table entry corresponding to the keyword. + * + * @return errlHndl_t - NULL if successful, otherwise a pointer to + * the error log. + */ +errlHndl_t getKeywordEntry(VPD::vpdKeyword i_keyword, + uint64_t i_memType, + TARGETING::Target* i_target, + const KeywordData* &o_entry ); /** * @brief This function is used to check the parameters in the SPD data that * indicate which module specific keywords are valid, and then check that @@ -457,6 +508,26 @@ errlHndl_t cmpPnorToSeeprom( TARGETING::Target * i_target, bool &o_match ); /** + * @brief This function compares value of the keyword in CACHE/HARDWARE + * and returns the result + * + * @param[in] i_target - Target device + * + * @param[in] i_eepromType - Eeprom content type of target device + * + * @param [in] i_keyword - Keyword to compare + * + * @param [in] o_match - Result of keyword compare + * + * @return errlHndl_t - NULL if successful, otherwise a pointer to the + * error log. A mismatch will not return an error. + */ +errlHndl_t cmpEecacheToEeprom(TARGETING::Target * i_target, + TARGETING::EEPROM_CONTENT_TYPE i_eepromType, + VPD::vpdKeyword i_keyword, + bool& o_match); + +/** * @brief This function loads the SPD data from the SEEPROM into the PNOR cache * * @param[in] i_target - Target device diff --git a/src/usr/vpd/spdDDR3.H b/src/usr/vpd/spdDDR3.H index 06fc33aa5..26aa36660 100644 --- a/src/usr/vpd/spdDDR3.H +++ b/src/usr/vpd/spdDDR3.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2015 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -68,74 +68,74 @@ const KeywordData ddr3Data[] = // Number Case able Spec // ------------------------------------------------------------------------------------------ // Normal fields supported on both DDR3 and DDR4 - { CRC_EXCLUDE, 0x00, 0x01, 0x80, 0x07, false, false, NA }, - { SPD_BYTES_TOTAL, 0x00, 0x01, 0x70, 0x04, false, false, NA }, - { SPD_BYTES_USED, 0x00, 0x01, 0x0F, 0x00, false, false, NA }, - { SPD_MAJOR_REVISION, 0x01, 0x01, 0xF0, 0x04, false, false, NA }, - { SPD_MINOR_REVISION, 0x01, 0x01, 0x0F, 0x00, false, false, NA }, - { BASIC_MEMORY_TYPE, 0x02, 0x01, 0x00, 0x00, false, false, NA }, - { CUSTOM, 0x03, 0x01, 0x80, 0x07, false, false, NA }, - { MODULE_TYPE, 0x03, 0x01, 0x0F, 0x00, false, false, NA }, - { DENSITY, 0x04, 0x01, 0x0F, 0x00, false, false, NA }, - { ROW_ADDRESS, 0x05, 0x01, 0x38, 0x03, false, false, NA }, - { COL_ADDRESS, 0x05, 0x01, 0x07, 0x00, false, false, NA }, - { MODULE_RANKS, 0x07, 0x01, 0x38, 0x03, false, false, NA }, - { MODULE_DRAM_WIDTH, 0x07, 0x01, 0x07, 0x00, false, false, NA }, - { MODULE_MEMORY_BUS_WIDTH, 0x08, 0x01, 0x1f, 0x00, false, false, NA }, - { MODULE_MEMORY_BUS_WIDTH_EXT, 0x08, 0x01, 0x18, 0x03, false, false, NA }, - { MODULE_MEMORY_BUS_WIDTH_PRI, 0x08, 0x01, 0x07, 0x00, false, false, NA }, - { TCK_MIN, 0x0c, 0x01, 0x00, 0x00, false, false, NA }, - { MIN_CAS_LATENCY, 0x10, 0x01, 0x00, 0x00, false, false, NA }, - { TRCD_MIN, 0x12, 0x01, 0x00, 0x00, false, false, NA }, - { TRP_MIN, 0x14, 0x01, 0x00, 0x00, false, false, NA }, - { TRC_MIN, 0x15, 0x02, 0xF0, 0x04, true, false, NA }, - { TRAS_MIN, 0x15, 0x02, 0x0F, 0x00, false, false, NA }, - { TFAW_MIN, 0x1c, 0x02, 0x0F, 0x00, false, false, NA }, - { SDRAM_OPTIONAL_FEATURES, 0x1e, 0x01, 0x00, 0x00, false, false, NA }, - { SDRAM_THERMAL_REFRESH_OPTIONS, 0x1f, 0x01, 0x00, 0x00, false, false, NA }, - { MODULE_THERMAL_SENSOR, 0x20, 0x01, 0x00, 0x00, false, false, NA }, - { THERMAL_SENSOR_PRESENT, 0x20, 0x01, 0x80, 0x07, false, false, NA }, - { THERMAL_SENSOR_ACCURACY, 0x20, 0x01, 0x7F, 0x00, false, false, NA }, - { SDRAM_DEVICE_TYPE, 0x21, 0x01, 0x80, 0x07, false, false, NA }, - { SDRAM_DIE_COUNT, 0x21, 0x01, 0x70, 0x04, false, false, NA }, - { SDRAM_DEVICE_TYPE_SIGNAL_LOADING, 0x21, 0x01, 0x03, 0x00, false, false, NA }, - { TCKMIN_FINE_OFFSET, 0x22, 0x01, 0x00, 0x00, false, false, NA }, - { TAAMIN_FINE_OFFSET, 0x23, 0x01, 0x00, 0x00, false, false, NA }, - { TRCDMIN_FINE_OFFSET, 0x24, 0x01, 0x00, 0x00, false, false, NA }, - { TRPMIN_FINE_OFFSET, 0x25, 0x01, 0x00, 0x00, false, false, NA }, - { TRCMIN_FINE_OFFSET, 0x26, 0x01, 0x00, 0x00, false, false, NA }, - { MODULE_TYPE_SPECIFIC_SECTION, 0x3c, 0x39, 0x00, 0x00, false, false, NA }, - { MODULE_MANUFACTURER_ID, 0x76, 0x02, 0x00, 0x00, true, false, NA }, - { MODULE_MANUFACTURING_LOCATION, 0x77, 0x01, 0x00, 0x00, false, false, NA }, - { MODULE_MANUFACTURING_DATE, 0x78, 0x02, 0x00, 0x00, false, false, NA }, - { MODULE_SERIAL_NUMBER, 0x7a, 0x04, 0x00, 0x00, false, false, NA }, - { MODULE_PART_NUMBER, 0x80, 0x12, 0x00, 0x00, false, false, NA }, - { DRAM_MANUFACTURER_ID, 0x95, 0x02, 0x00, 0x00, true, false, NA }, - { MANUFACTURER_SPECIFIC_DATA, 0x96, 0x1a, 0x00, 0x00, false, false, NA }, - { DIMM_BAD_DQ_DATA, 0xb0, 0x50, 0x00, 0x00, false, true, NA }, + { CRC_EXCLUDE, 0x00, 0x01, 0x80, 0x07, false, false, ALL }, + { SPD_BYTES_TOTAL, 0x00, 0x01, 0x70, 0x04, false, false, ALL }, + { SPD_BYTES_USED, 0x00, 0x01, 0x0F, 0x00, false, false, ALL }, + { SPD_MAJOR_REVISION, 0x01, 0x01, 0xF0, 0x04, false, false, ALL }, + { SPD_MINOR_REVISION, 0x01, 0x01, 0x0F, 0x00, false, false, ALL }, + { BASIC_MEMORY_TYPE, 0x02, 0x01, 0x00, 0x00, false, false, ALL }, + { CUSTOM, 0x03, 0x01, 0x80, 0x07, false, false, ALL }, + { MODULE_TYPE, 0x03, 0x01, 0x0F, 0x00, false, false, ALL }, + { DENSITY, 0x04, 0x01, 0x0F, 0x00, false, false, ALL }, + { ROW_ADDRESS, 0x05, 0x01, 0x38, 0x03, false, false, ALL }, + { COL_ADDRESS, 0x05, 0x01, 0x07, 0x00, false, false, ALL }, + { MODULE_RANKS, 0x07, 0x01, 0x38, 0x03, false, false, ALL }, + { MODULE_DRAM_WIDTH, 0x07, 0x01, 0x07, 0x00, false, false, ALL }, + { MODULE_MEMORY_BUS_WIDTH, 0x08, 0x01, 0x1f, 0x00, false, false, ALL }, + { MODULE_MEMORY_BUS_WIDTH_EXT, 0x08, 0x01, 0x18, 0x03, false, false, ALL }, + { MODULE_MEMORY_BUS_WIDTH_PRI, 0x08, 0x01, 0x07, 0x00, false, false, ALL }, + { TCK_MIN, 0x0c, 0x01, 0x00, 0x00, false, false, ALL }, + { MIN_CAS_LATENCY, 0x10, 0x01, 0x00, 0x00, false, false, ALL }, + { TRCD_MIN, 0x12, 0x01, 0x00, 0x00, false, false, ALL }, + { TRP_MIN, 0x14, 0x01, 0x00, 0x00, false, false, ALL }, + { TRC_MIN, 0x15, 0x02, 0xF0, 0x04, true, false, ALL }, + { TRAS_MIN, 0x15, 0x02, 0x0F, 0x00, false, false, ALL }, + { TFAW_MIN, 0x1c, 0x02, 0x0F, 0x00, false, false, ALL }, + { SDRAM_OPTIONAL_FEATURES, 0x1e, 0x01, 0x00, 0x00, false, false, ALL }, + { SDRAM_THERMAL_REFRESH_OPTIONS, 0x1f, 0x01, 0x00, 0x00, false, false, ALL }, + { MODULE_THERMAL_SENSOR, 0x20, 0x01, 0x00, 0x00, false, false, ALL }, + { THERMAL_SENSOR_PRESENT, 0x20, 0x01, 0x80, 0x07, false, false, ALL }, + { THERMAL_SENSOR_ACCURACY, 0x20, 0x01, 0x7F, 0x00, false, false, ALL }, + { SDRAM_DEVICE_TYPE, 0x21, 0x01, 0x80, 0x07, false, false, ALL }, + { SDRAM_DIE_COUNT, 0x21, 0x01, 0x70, 0x04, false, false, ALL }, + { SDRAM_DEVICE_TYPE_SIGNAL_LOADING, 0x21, 0x01, 0x03, 0x00, false, false, ALL }, + { TCKMIN_FINE_OFFSET, 0x22, 0x01, 0x00, 0x00, false, false, ALL }, + { TAAMIN_FINE_OFFSET, 0x23, 0x01, 0x00, 0x00, false, false, ALL }, + { TRCDMIN_FINE_OFFSET, 0x24, 0x01, 0x00, 0x00, false, false, ALL }, + { TRPMIN_FINE_OFFSET, 0x25, 0x01, 0x00, 0x00, false, false, ALL }, + { TRCMIN_FINE_OFFSET, 0x26, 0x01, 0x00, 0x00, false, false, ALL }, + { MODULE_TYPE_SPECIFIC_SECTION, 0x3c, 0x39, 0x00, 0x00, false, false, ALL }, + { MODULE_MANUFACTURER_ID, 0x76, 0x02, 0x00, 0x00, true, false, ALL }, + { MODULE_MANUFACTURING_LOCATION, 0x77, 0x01, 0x00, 0x00, false, false, ALL }, + { MODULE_MANUFACTURING_DATE, 0x78, 0x02, 0x00, 0x00, false, false, ALL }, + { MODULE_SERIAL_NUMBER, 0x7a, 0x04, 0x00, 0x00, false, false, ALL }, + { MODULE_PART_NUMBER, 0x80, 0x12, 0x00, 0x00, false, false, ALL }, + { DRAM_MANUFACTURER_ID, 0x95, 0x02, 0x00, 0x00, true, false, ALL }, + { MANUFACTURER_SPECIFIC_DATA, 0x96, 0x1a, 0x00, 0x00, false, false, ALL }, + { DIMM_BAD_DQ_DATA, 0xb0, 0x50, 0x00, 0x00, false, true, ALL }, // Normal fields supported on DDR3 only - { BANK_ADDRESS_BITS, 0x04, 0x01, 0x70, 0x04, false, false, NA }, - { MODULE_NOMINAL_VOLTAGE, 0x06, 0x01, 0x07, 0x00, false, false, NA }, - { FTB_DIVIDEND, 0x09, 0x01, 0xF0, 0x04, false, false, NA }, - { FTB_DIVISOR, 0x09, 0x01, 0x0F, 0x00, false, false, NA }, - { MTB_DIVIDEND, 0x0a, 0x01, 0x00, 0x00, false, false, NA }, - { MTB_DIVISOR, 0x0b, 0x01, 0x00, 0x00, false, false, NA }, - { CAS_LATENCIES_SUPPORTED, 0x0f, 0x02, 0x7F, 0x00, true, false, NA }, - { TWR_MIN, 0x11, 0x01, 0x00, 0x00, false, false, NA }, - { TRRD_MIN, 0x13, 0x01, 0x00, 0x00, false, false, NA }, - { TRFC_MIN, 0x19, 0x02, 0x00, 0x00, true, false, NA }, - { TWTR_MIN, 0x1a, 0x01, 0x00, 0x00, false, false, NA }, - { TRTP_MIN, 0x1b, 0x01, 0x00, 0x00, false, false, NA }, - { DLL_OFF, 0x1e, 0x01, 0x80, 0x07, false, false, NA }, - { RZQ_7, 0x1e, 0x01, 0x02, 0x01, false, false, NA }, - { RZQ_6, 0x1e, 0x01, 0x01, 0x00, false, false, NA }, - { PASR, 0x1f, 0x01, 0x80, 0x07, false, false, NA }, - { ODTS, 0x1f, 0x01, 0x08, 0x03, false, false, NA }, - { ASR, 0x1f, 0x01, 0x04, 0x02, false, false, NA }, - { ETR_1X, 0x1f, 0x01, 0x02, 0x01, false, false, NA }, - { ETR, 0x1f, 0x01, 0x01, 0x00, false, false, NA }, - { MODULE_CRC, 0x7f, 0x02, 0x00, 0x00, true, false, NA }, - { MODULE_REVISION_CODE, 0x93, 0x02, 0x00, 0x00, true, false, NA }, + { BANK_ADDRESS_BITS, 0x04, 0x01, 0x70, 0x04, false, false, ALL }, + { MODULE_NOMINAL_VOLTAGE, 0x06, 0x01, 0x07, 0x00, false, false, ALL }, + { FTB_DIVIDEND, 0x09, 0x01, 0xF0, 0x04, false, false, ALL }, + { FTB_DIVISOR, 0x09, 0x01, 0x0F, 0x00, false, false, ALL }, + { MTB_DIVIDEND, 0x0a, 0x01, 0x00, 0x00, false, false, ALL }, + { MTB_DIVISOR, 0x0b, 0x01, 0x00, 0x00, false, false, ALL }, + { CAS_LATENCIES_SUPPORTED, 0x0f, 0x02, 0x7F, 0x00, true, false, ALL }, + { TWR_MIN, 0x11, 0x01, 0x00, 0x00, false, false, ALL }, + { TRRD_MIN, 0x13, 0x01, 0x00, 0x00, false, false, ALL }, + { TRFC_MIN, 0x19, 0x02, 0x00, 0x00, true, false, ALL }, + { TWTR_MIN, 0x1a, 0x01, 0x00, 0x00, false, false, ALL }, + { TRTP_MIN, 0x1b, 0x01, 0x00, 0x00, false, false, ALL }, + { DLL_OFF, 0x1e, 0x01, 0x80, 0x07, false, false, ALL }, + { RZQ_7, 0x1e, 0x01, 0x02, 0x01, false, false, ALL }, + { RZQ_6, 0x1e, 0x01, 0x01, 0x00, false, false, ALL }, + { PASR, 0x1f, 0x01, 0x80, 0x07, false, false, ALL }, + { ODTS, 0x1f, 0x01, 0x08, 0x03, false, false, ALL }, + { ASR, 0x1f, 0x01, 0x04, 0x02, false, false, ALL }, + { ETR_1X, 0x1f, 0x01, 0x02, 0x01, false, false, ALL }, + { ETR, 0x1f, 0x01, 0x01, 0x00, false, false, ALL }, + { MODULE_CRC, 0x7f, 0x02, 0x00, 0x00, true, false, ALL }, + { MODULE_REVISION_CODE, 0x93, 0x02, 0x00, 0x00, true, false, ALL }, // Module Specific fields supported on both DDR3 and DDR4 { MODSPEC_COM_NOM_HEIGHT_MAX, 0x3c, 0x01, 0x1f, 0x00, false, false, ALL }, { MODSPEC_COM_MAX_THICK_BACK, 0x3d, 0x01, 0xf0, 0x04, false, false, ALL }, diff --git a/src/usr/vpd/spdDDR4.H b/src/usr/vpd/spdDDR4.H index 0d732fa92..b29a1043f 100755 --- a/src/usr/vpd/spdDDR4.H +++ b/src/usr/vpd/spdDDR4.H @@ -69,76 +69,76 @@ const KeywordData ddr4Data[] = // ------------------------------------------------------------------------------------------ // // Normal fields supported on both DDR3 and DDR4 - { SPD_BYTES_TOTAL, 0x00, 0x01, 0x70, 0x04, false, false, NA }, - { SPD_BYTES_USED, 0x00, 0x01, 0x0F, 0x00, false, false, NA }, - { SPD_MAJOR_REVISION, 0x01, 0x01, 0xF0, 0x04, false, false, NA }, - { SPD_MINOR_REVISION, 0x01, 0x01, 0x0F, 0x00, false, false, NA }, - { BASIC_MEMORY_TYPE, 0x02, 0x01, 0x00, 0x00, false, false, NA }, - { CUSTOM, 0x03, 0x01, 0x80, 0x07, false, false, NA }, - { MODULE_TYPE, 0x03, 0x01, 0x0F, 0x00, false, false, NA }, - { DENSITY, 0x04, 0x01, 0x0F, 0x00, false, false, NA }, - { ROW_ADDRESS, 0x05, 0x01, 0x38, 0x03, false, false, NA }, - { COL_ADDRESS, 0x05, 0x01, 0x07, 0x00, false, false, NA }, - { MODULE_RANKS, 0x0c, 0x01, 0x38, 0x03, false, false, NA }, - { MODULE_DRAM_WIDTH, 0x0c, 0x01, 0x07, 0x00, false, false, NA }, - { MODULE_MEMORY_BUS_WIDTH, 0x0d, 0x01, 0x1f, 0x00, false, false, NA }, - { MODULE_MEMORY_BUS_WIDTH_EXT, 0x0d, 0x01, 0x18, 0x03, false, false, NA }, - { MODULE_MEMORY_BUS_WIDTH_PRI, 0x0d, 0x01, 0x07, 0x00, false, false, NA }, - { TCK_MIN, 0x12, 0x01, 0x00, 0x00, false, false, NA }, - { MIN_CAS_LATENCY, 0x18, 0x01, 0x00, 0x00, false, false, NA }, - { TRCD_MIN, 0x19, 0x01, 0x00, 0x00, false, false, NA }, - { TRP_MIN, 0x1a, 0x01, 0x00, 0x00, false, false, NA }, - { TRC_MIN, 0x1b, 0x02, 0xF0, 0x04, true, false, NA }, - { TRAS_MIN, 0x1b, 0x02, 0x0F, 0x00, false, false, NA }, - { TFAW_MIN, 0x24, 0x02, 0x0F, 0x00, false, false, NA }, - { SDRAM_OPTIONAL_FEATURES, 0x07, 0x01, 0x00, 0x00, false, false, NA }, - { SDRAM_THERMAL_REFRESH_OPTIONS, 0x08, 0x01, 0x00, 0x00, false, false, NA }, - { MODULE_THERMAL_SENSOR, 0x0e, 0x01, 0x00, 0x00, false, false, NA }, - { THERMAL_SENSOR_PRESENT, 0x0e, 0x01, 0x80, 0x07, false, false, NA }, - { SDRAM_DEVICE_TYPE , 0x06, 0x01, 0x80, 0x07, false, false, NA }, - { SDRAM_DIE_COUNT, 0x06, 0x01, 0x70, 0x04, false, false, NA }, - { SDRAM_DEVICE_TYPE_SIGNAL_LOADING, 0x06, 0x01, 0x03, 0x00, false, false, NA }, - { TCKMIN_FINE_OFFSET, 0x7d, 0x01, 0x00, 0x00, false, false, NA }, - { TAAMIN_FINE_OFFSET, 0x7b, 0x01, 0x00, 0x00, false, false, NA }, - { TRCDMIN_FINE_OFFSET, 0x7a, 0x01, 0x00, 0x00, false, false, NA }, - { TRPMIN_FINE_OFFSET, 0x79, 0x01, 0x00, 0x00, false, false, NA }, - { TRCMIN_FINE_OFFSET, 0x78, 0x01, 0x00, 0x00, false, false, NA }, - // Note - All data below 128 is common across all DDR4 DIMMs, even DDIMM - { MODULE_TYPE_SPECIFIC_SECTION, 0x80, 0x80, 0x00, 0x00, false, false, NA }, - { MODULE_MANUFACTURER_ID, 0x141, 0x02, 0x00, 0x00, true, false, NA }, - { MODULE_MANUFACTURING_LOCATION, 0x142, 0x01, 0x00, 0x00, false, false, NA }, - { MODULE_MANUFACTURING_DATE, 0x143, 0x02, 0x00, 0x00, false, false, NA }, - { MODULE_SERIAL_NUMBER, 0x145, 0x04, 0x00, 0x00, false, false, NA }, - { MODULE_PART_NUMBER, 0x149, 0x14, 0x00, 0x00, false, false, NA }, - { DRAM_MANUFACTURER_ID, 0x15f, 0x02, 0x00, 0x00, true, false, NA }, - { MANUFACTURER_SPECIFIC_DATA, 0x161, 0x1d, 0x00, 0x00, false, false, NA }, - { DIMM_BAD_DQ_DATA, 0x180, 0x50, 0x00, 0x00, false, true, NA }, - { MODULE_REVISION_CODE, 0x15d, 0x01, 0x00, 0x00, false, false, NA }, + { SPD_BYTES_TOTAL, 0x00, 0x01, 0x70, 0x04, false, false, ALL }, + { SPD_BYTES_USED, 0x00, 0x01, 0x0F, 0x00, false, false, ALL }, + { SPD_MAJOR_REVISION, 0x01, 0x01, 0xF0, 0x04, false, false, ALL }, + { SPD_MINOR_REVISION, 0x01, 0x01, 0x0F, 0x00, false, false, ALL }, + { BASIC_MEMORY_TYPE, 0x02, 0x01, 0x00, 0x00, false, false, ALL }, + { CUSTOM, 0x03, 0x01, 0x80, 0x07, false, false, ALL }, + { MODULE_TYPE, 0x03, 0x01, 0x0F, 0x00, false, false, ALL }, + { DENSITY, 0x04, 0x01, 0x0F, 0x00, false, false, ALL }, + { ROW_ADDRESS, 0x05, 0x01, 0x38, 0x03, false, false, ALL }, + { COL_ADDRESS, 0x05, 0x01, 0x07, 0x00, false, false, ALL }, + { MODULE_RANKS, 0x0c, 0x01, 0x38, 0x03, false, false, ALL }, + { MODULE_DRAM_WIDTH, 0x0c, 0x01, 0x07, 0x00, false, false, ALL }, + { MODULE_MEMORY_BUS_WIDTH, 0x0d, 0x01, 0x1f, 0x00, false, false, ALL }, + { MODULE_MEMORY_BUS_WIDTH_EXT, 0x0d, 0x01, 0x18, 0x03, false, false, ALL }, + { MODULE_MEMORY_BUS_WIDTH_PRI, 0x0d, 0x01, 0x07, 0x00, false, false, ALL }, + { TCK_MIN, 0x12, 0x01, 0x00, 0x00, false, false, ALL }, + { MIN_CAS_LATENCY, 0x18, 0x01, 0x00, 0x00, false, false, ALL }, + { TRCD_MIN, 0x19, 0x01, 0x00, 0x00, false, false, ALL }, + { TRP_MIN, 0x1a, 0x01, 0x00, 0x00, false, false, ALL }, + { TRC_MIN, 0x1b, 0x02, 0xF0, 0x04, true, false, ALL }, + { TRAS_MIN, 0x1b, 0x02, 0x0F, 0x00, false, false, ALL }, + { TFAW_MIN, 0x24, 0x02, 0x0F, 0x00, false, false, ALL }, + { SDRAM_OPTIONAL_FEATURES, 0x07, 0x01, 0x00, 0x00, false, false, ALL }, + { SDRAM_THERMAL_REFRESH_OPTIONS, 0x08, 0x01, 0x00, 0x00, false, false, ALL }, + { MODULE_THERMAL_SENSOR, 0x0e, 0x01, 0x00, 0x00, false, false, ALL }, + { THERMAL_SENSOR_PRESENT, 0x0e, 0x01, 0x80, 0x07, false, false, ALL }, + { SDRAM_DEVICE_TYPE , 0x06, 0x01, 0x80, 0x07, false, false, ALL }, + { SDRAM_DIE_COUNT, 0x06, 0x01, 0x70, 0x04, false, false, ALL }, + { SDRAM_DEVICE_TYPE_SIGNAL_LOADING, 0x06, 0x01, 0x03, 0x00, false, false, ALL }, + { TCKMIN_FINE_OFFSET, 0x7d, 0x01, 0x00, 0x00, false, false, ALL }, + { TAAMIN_FINE_OFFSET, 0x7b, 0x01, 0x00, 0x00, false, false, ALL }, + { TRCDMIN_FINE_OFFSET, 0x7a, 0x01, 0x00, 0x00, false, false, ALL }, + { TRPMIN_FINE_OFFSET, 0x79, 0x01, 0x00, 0x00, false, false, ALL }, + { TRCMIN_FINE_OFFSET, 0x78, 0x01, 0x00, 0x00, false, false, ALL }, + // Note - All data below 128 is common across all DDR4 DIMMs, except DDIMM + { MODULE_TYPE_SPECIFIC_SECTION, 0x80, 0x80, 0x00, 0x00, false, false, ALL }, + { MODULE_MANUFACTURER_ID, 0x141, 0x02, 0x00, 0x00, true, false, ALL }, + { MODULE_MANUFACTURING_LOCATION, 0x142, 0x01, 0x00, 0x00, false, false, ALL }, + { MODULE_MANUFACTURING_DATE, 0x143, 0x02, 0x00, 0x00, false, false, ALL }, + { MODULE_SERIAL_NUMBER, 0x145, 0x04, 0x00, 0x00, false, false, ALL }, + { MODULE_PART_NUMBER, 0x149, 0x14, 0x00, 0x00, false, false, ALL }, + { DRAM_MANUFACTURER_ID, 0x15f, 0x02, 0x00, 0x00, true, false, ALL }, + { MANUFACTURER_SPECIFIC_DATA, 0x161, 0x1d, 0x00, 0x00, false, false, ALL }, + { DIMM_BAD_DQ_DATA, 0x180, 0x50, 0x00, 0x00, false, true, ALL }, + { MODULE_REVISION_CODE, 0x15d, 0x01, 0x00, 0x00, false, false, ALL }, // Normal fields supported on DDR4 only - { BANK_GROUP_BITS, 0x04, 0x01, 0xC0, 0x06, false, false, NA }, - { BANK_ADDRESS_BITS_DDR4, 0x04, 0x01, 0x30, 0x04, false, false, NA }, - { MODULE_NOMINAL_VOLTAGE_DDR4, 0x0b, 0x01, 0x3F, 0x00, false, false, NA }, - { TIMEBASES_MTB , 0x11, 0x01, 0x0C, 0x02, false, false, NA }, - { TIMEBASES_FTB, 0x11, 0x01, 0x03, 0x00, false, false, NA }, - { TCK_MAX, 0x13, 0x01, 0x00, 0x00, false, false, NA }, - { CAS_LATENCIES_SUPPORTED_DDR4, 0x17, 0x04, 0x00, 0x00, true, false, NA }, - { TRFC1_MIN, 0x1f, 0x02, 0x00, 0x00, true, false, NA }, - { TRFC2_MIN, 0x21, 0x02, 0x00, 0x00, true, false, NA }, - { TRFC4_MIN, 0x23, 0x02, 0x00, 0x00, true, false, NA }, - { TRRDS_MIN, 0x26, 0x01, 0x00, 0x00, false, false, NA }, - { TRRDL_MIN, 0x27, 0x01, 0x00, 0x00, false, false, NA }, - { TCCDL_MIN, 0x28, 0x01, 0x00, 0x00, false, false, NA }, - { CONNECTOR_SDRAM_MAP, 0x3C, 0x12, 0x00, 0x00, false, false, NA }, - { TCCDL_FINE_OFFSET, 0x75, 0x01, 0x00, 0x00, false, false, NA }, - { TRRDL_FINE_OFFSET, 0x76, 0x01, 0x00, 0x00, false, false, NA }, - { TRRDS_FINE_OFFSET, 0x77, 0x01, 0x00, 0x00, false, false, NA }, - { TCKMAX_FINE_OFFSET, 0x7c, 0x01, 0x00, 0x00, false, false, NA }, - { BASE_CONFIG_CRC, 0x7f, 0x02, 0x00, 0x00, true, false, NA }, - { DRAM_STEPPING, 0x160, 0x01, 0x00, 0x00, false, false, NA }, - { MANUFACTURING_SECTION_CRC, 0x17f, 0x02, 0x00, 0x00, true, false, NA }, - { NVM_INIT_TIME, 0xCB, 0x01, 0x00, 0x00, false, false, NA }, - { RAW_MODULE_PRODUCT_ID, 0xc0, 0x02, 0x00, 0x00, false, false, NA }, - { RAW_MODULE_MANUFACTURER_ID, 0x140, 0x02, 0x00, 0x00, false, false, NA }, + { BANK_GROUP_BITS, 0x04, 0x01, 0xC0, 0x06, false, false, ALL }, + { BANK_ADDRESS_BITS_DDR4, 0x04, 0x01, 0x30, 0x04, false, false, ALL }, + { MODULE_NOMINAL_VOLTAGE_DDR4, 0x0b, 0x01, 0x3F, 0x00, false, false, ALL }, + { TIMEBASES_MTB, 0x11, 0x01, 0x0C, 0x02, false, false, ALL }, + { TIMEBASES_FTB, 0x11, 0x01, 0x03, 0x00, false, false, ALL }, + { TCK_MAX, 0x13, 0x01, 0x00, 0x00, false, false, ALL }, + { CAS_LATENCIES_SUPPORTED_DDR4, 0x17, 0x04, 0x00, 0x00, true, false, ALL }, + { TRFC1_MIN, 0x1f, 0x02, 0x00, 0x00, true, false, ALL }, + { TRFC2_MIN, 0x21, 0x02, 0x00, 0x00, true, false, ALL }, + { TRFC4_MIN, 0x23, 0x02, 0x00, 0x00, true, false, ALL }, + { TRRDS_MIN, 0x26, 0x01, 0x00, 0x00, false, false, ALL }, + { TRRDL_MIN, 0x27, 0x01, 0x00, 0x00, false, false, ALL }, + { TCCDL_MIN, 0x28, 0x01, 0x00, 0x00, false, false, ALL }, + { CONNECTOR_SDRAM_MAP, 0x3C, 0x12, 0x00, 0x00, false, false, ALL }, + { TCCDL_FINE_OFFSET, 0x75, 0x01, 0x00, 0x00, false, false, ALL }, + { TRRDL_FINE_OFFSET, 0x76, 0x01, 0x00, 0x00, false, false, ALL }, + { TRRDS_FINE_OFFSET, 0x77, 0x01, 0x00, 0x00, false, false, ALL }, + { TCKMAX_FINE_OFFSET, 0x7c, 0x01, 0x00, 0x00, false, false, ALL }, + { BASE_CONFIG_CRC, 0x7f, 0x02, 0x00, 0x00, true, false, ALL }, + { DRAM_STEPPING, 0x160, 0x01, 0x00, 0x00, false, false, ALL }, + { MANUFACTURING_SECTION_CRC, 0x17f, 0x02, 0x00, 0x00, true, false, ALL }, + { NVM_INIT_TIME, 0xCB, 0x01, 0x00, 0x00, false, false, ALL }, + { RAW_MODULE_PRODUCT_ID, 0xc0, 0x02, 0x00, 0x00, false, false, ALL }, + { RAW_MODULE_MANUFACTURER_ID, 0x140, 0x02, 0x00, 0x00, false, false, ALL }, // Module Specific fields supported on both DDR3 and DDR4 { MODSPEC_COM_NOM_HEIGHT_MAX, 0x80, 0x01, 0x1f, 0x00, false, false, ALL }, { MODSPEC_COM_MAX_THICK_BACK, 0x81, 0x01, 0xf0, 0x04, false, false, ALL }, diff --git a/src/usr/vpd/spdDDR4_DDIMM.H b/src/usr/vpd/spdDDR4_DDIMM.H new file mode 100755 index 000000000..38899b88e --- /dev/null +++ b/src/usr/vpd/spdDDR4_DDIMM.H @@ -0,0 +1,141 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/vpd/spdDDR4_DDIMM.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef __SPDDDR4_DDIMM_H +#define __SPDDDR4_DDIMM_H + +/** + * @file spdDDR4_DDIMM.H + * + * @brief Provides the DDR4 field information for DDIMM + * + */ + +// ---------------------------------------------- +// Includes +// ---------------------------------------------- +#include "spd.H" + +namespace SPD +{ + +/** + * @brief Pre-defined lookup table for DDR4 keywords and the + * information needed to read that data from the SPD data. + */ +const KeywordData ddr4DDIMMData[] = +{ + // ---------------------------------------------------------------------------------- + // NOTE: This list must remain an ordered list! The Keyword must be in numerical + // order (values defined in spdenums.H) to allow efficient searching, a unit + // test enforces this. + // ---------------------------------------------------------------------------------- + // Bit order for each byte is [7:0] as defined by the JEDEC spec (little endian) + // + // For multi-byte fields, the offset specifies the byte that is placed at offset 0 in + // the output buffer. + // - If SpecialCase=false then the next byte in SPD is placed at the next offset in + // the output buffer until complete. Any bitmask/shift only affects the byte at + // offset 0 + // - If SpecialCase=true then spd.C handles the field in a custom way (e.g. working + // backwards through SPD bytes). + // Typically for a 2-byte field consisting of (LSB,MSB), the offset points to MSB and + // it is a SpecialCase where spd.C first copies the MSB to the output buffer then + // copies the previous byte (LSB) to the output buffer (big endian). + // ------------------------------------------------------------------------------------------ + // Keyword offset size Bitmsk Shift Spec Writ- Mod + // Number Case able Spec + // ------------------------------------------------------------------------------------------ + // + // Normal fields supported on both DDR3 and DDR4 + { SPD_BYTES_TOTAL, 0x00, 0x01, 0x70, 0x04, false, false, ALL }, + { SPD_BYTES_USED, 0x00, 0x01, 0x0F, 0x00, false, false, ALL }, + { SPD_MAJOR_REVISION, 0x01, 0x01, 0xF0, 0x04, false, false, ALL }, + { SPD_MINOR_REVISION, 0x01, 0x01, 0x0F, 0x00, false, false, ALL }, + { BASIC_MEMORY_TYPE, 0x02, 0x01, 0x00, 0x00, false, false, ALL }, + { CUSTOM, 0x03, 0x01, 0x80, 0x07, false, false, ALL }, + { MODULE_TYPE, 0x03, 0x01, 0x0F, 0x00, false, false, ALL }, + { DENSITY, 0x04, 0x01, 0x0F, 0x00, false, false, ALL }, + { ROW_ADDRESS, 0x05, 0x01, 0x38, 0x03, false, false, ALL }, + { COL_ADDRESS, 0x05, 0x01, 0x07, 0x00, false, false, ALL }, + { MODULE_RANKS, 0x0c, 0x01, 0x38, 0x03, false, false, ALL }, + { MODULE_DRAM_WIDTH, 0x0c, 0x01, 0x07, 0x00, false, false, ALL }, + { MODULE_MEMORY_BUS_WIDTH, 0x0d, 0x01, 0x1f, 0x00, false, false, ALL }, + { MODULE_MEMORY_BUS_WIDTH_EXT, 0x0d, 0x01, 0x18, 0x03, false, false, ALL }, + { MODULE_MEMORY_BUS_WIDTH_PRI, 0x0d, 0x01, 0x07, 0x00, false, false, ALL }, + { TCK_MIN, 0x12, 0x01, 0x00, 0x00, false, false, ALL }, + { MIN_CAS_LATENCY, 0x18, 0x01, 0x00, 0x00, false, false, ALL }, + { TRCD_MIN, 0x19, 0x01, 0x00, 0x00, false, false, ALL }, + { TRP_MIN, 0x1a, 0x01, 0x00, 0x00, false, false, ALL }, + { TRC_MIN, 0x1b, 0x02, 0xF0, 0x04, true, false, ALL }, + { TRAS_MIN, 0x1b, 0x02, 0x0F, 0x00, false, false, ALL }, + { TFAW_MIN, 0x24, 0x02, 0x0F, 0x00, false, false, ALL }, + { SDRAM_OPTIONAL_FEATURES, 0x07, 0x01, 0x00, 0x00, false, false, ALL }, + { SDRAM_THERMAL_REFRESH_OPTIONS, 0x08, 0x01, 0x00, 0x00, false, false, ALL }, + { MODULE_THERMAL_SENSOR, 0x0e, 0x01, 0x00, 0x00, false, false, ALL }, + { THERMAL_SENSOR_PRESENT, 0x0e, 0x01, 0x80, 0x07, false, false, ALL }, + { SDRAM_DEVICE_TYPE , 0x06, 0x01, 0x80, 0x07, false, false, ALL }, + { SDRAM_DIE_COUNT, 0x06, 0x01, 0x70, 0x04, false, false, ALL }, + { SDRAM_DEVICE_TYPE_SIGNAL_LOADING, 0x06, 0x01, 0x03, 0x00, false, false, ALL }, + { TCKMIN_FINE_OFFSET, 0x7d, 0x01, 0x00, 0x00, false, false, ALL }, + { TAAMIN_FINE_OFFSET, 0x7b, 0x01, 0x00, 0x00, false, false, ALL }, + { TRCDMIN_FINE_OFFSET, 0x7a, 0x01, 0x00, 0x00, false, false, ALL }, + { TRPMIN_FINE_OFFSET, 0x79, 0x01, 0x00, 0x00, false, false, ALL }, + { TRCMIN_FINE_OFFSET, 0x78, 0x01, 0x00, 0x00, false, false, ALL }, + // Note - All data below 128 is common across all DDR4 DIMMs, except DDIMM + { MODULE_MANUFACTURER_ID, 0x200, 0x02, 0x00, 0x00, true, false, ALL }, + { MODULE_SERIAL_NUMBER, 0x205, 0x04, 0x00, 0x00, false, false, ALL }, + { MODULE_PART_NUMBER, 0x209, 0x1E, 0x00, 0x00, false, false, ALL }, + { DIMM_BAD_DQ_DATA, 0x280, 0x50, 0x00, 0x00, false, true, ALL }, + { MODULE_REVISION_CODE, 0x277, 0x01, 0x00, 0x00, false, false, ALL }, + // Normal fields supported on DDR4 only + { BANK_GROUP_BITS, 0x04, 0x01, 0xC0, 0x06, false, false, ALL }, + { BANK_ADDRESS_BITS_DDR4, 0x04, 0x01, 0x30, 0x04, false, false, ALL }, + { MODULE_NOMINAL_VOLTAGE_DDR4, 0x0b, 0x01, 0x3F, 0x00, false, false, ALL }, + { TIMEBASES_MTB, 0x11, 0x01, 0x0C, 0x02, false, false, ALL }, + { TIMEBASES_FTB, 0x11, 0x01, 0x03, 0x00, false, false, ALL }, + { TCK_MAX, 0x13, 0x01, 0x00, 0x00, false, false, ALL }, + { CAS_LATENCIES_SUPPORTED_DDR4, 0x17, 0x04, 0x00, 0x00, true, false, ALL }, + { TRFC1_MIN, 0x1f, 0x02, 0x00, 0x00, true, false, ALL }, + { TRFC2_MIN, 0x21, 0x02, 0x00, 0x00, true, false, ALL }, + { TRFC4_MIN, 0x23, 0x02, 0x00, 0x00, true, false, ALL }, + { TRRDS_MIN, 0x26, 0x01, 0x00, 0x00, false, false, ALL }, + { TRRDL_MIN, 0x27, 0x01, 0x00, 0x00, false, false, ALL }, + { TCCDL_MIN, 0x28, 0x01, 0x00, 0x00, false, false, ALL }, + { CONNECTOR_SDRAM_MAP, 0x3C, 0x12, 0x00, 0x00, false, false, ALL }, + { TCCDL_FINE_OFFSET, 0x75, 0x01, 0x00, 0x00, false, false, ALL }, + { TRRDL_FINE_OFFSET, 0x76, 0x01, 0x00, 0x00, false, false, ALL }, + { TRRDS_FINE_OFFSET, 0x77, 0x01, 0x00, 0x00, false, false, ALL }, + { TCKMAX_FINE_OFFSET, 0x7c, 0x01, 0x00, 0x00, false, false, ALL }, + { BASE_CONFIG_CRC, 0x7f, 0x02, 0x00, 0x00, true, false, ALL }, + // Module Specific fields supported on DDR4 only + { ENTIRE_SPD_WITHOUT_EFD, 0x00, 0x280, 0x00, 0x00, false, false, ALL }, + { ENTIRE_SPD, 0x00, 0x800, 0x00, 0x00, false, false, ALL }, + //--------------------------------------------------------------------------------------- +}; + + +}; // end SPD namespace + +#endif // __SPDDDR4_DDR4_H diff --git a/src/usr/vpd/test/dvpdtest.H b/src/usr/vpd/test/dvpdtest.H index b0d62a062..3f16139f3 100755 --- a/src/usr/vpd/test/dvpdtest.H +++ b/src/usr/vpd/test/dvpdtest.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2018 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -37,7 +37,6 @@ #include <errl/errlentry.H> #include <devicefw/driverif.H> #include <targeting/common/predicates/predicatectm.H> -#include <config.h> #include <vpd/dvpdenums.H> #include <vpd/vpdreasoncodes.H> @@ -732,7 +731,7 @@ class DVPDTest: public CxxTest::TestSuite DVPDTest() : CxxTest::TestSuite() { TRACFCOMP( g_trac_vpd, "Starting DVPDTest" ); -#ifdef CONFIG_SECUREBOOT +#if (defined CONFIG_SECUREBOOT && ! defined CONFIG_AXONE) #ifndef __HOSTBOOT_RUNTIME errlHndl_t l_err = loadSecureSection(PNOR::MEMD); if(l_err) @@ -746,7 +745,7 @@ class DVPDTest: public CxxTest::TestSuite ~DVPDTest() { -#ifdef CONFIG_SECUREBOOT +#if (defined CONFIG_SECUREBOOT && ! defined CONFIG_AXONE) #ifndef __HOSTBOOT_RUNTIME errlHndl_t l_err = unloadSecureSection(PNOR::MEMD); TRACFCOMP( g_trac_vpd, "Ending DVPDTest" ); diff --git a/src/usr/vpd/test/spdtest.H b/src/usr/vpd/test/spdtest.H index bd7f6ef5b..a2e4c7b70 100755 --- a/src/usr/vpd/test/spdtest.H +++ b/src/usr/vpd/test/spdtest.H @@ -43,6 +43,7 @@ #include <vpd/spdenums.H> #include "../spdDDR3.H" #include "../spdDDR4.H" +#include "../spdDDR4_DDIMM.H" #include "../spd.H" extern trace_desc_t* g_trac_spd; @@ -117,16 +118,31 @@ class SPDTest: public CxxTest::TestSuite uint8_t memType = 0x0; err = getMemType( theTarget, memType ); + if( err ) + { + fails++; + TS_FAIL("testSpdRead- Failure reading Basic memory type!" ); + errlCommit( err, + VPD_COMP_ID ); + break; + } + // Get the module type. + modSpecTypes_t modType = NA; + err = getModType(modType, + theTarget, + memType, + VPD::AUTOSELECT); if( err ) { fails++; - TS_FAIL( "testSpdRead- Failure reading Basic memory type!" ); + TS_FAIL("testSpdRead- Failure reading memory module type!"); errlCommit( err, VPD_COMP_ID ); - break;; + break; } + for( uint64_t keyword = SPD::SPD_FIRST_NORM_KEYWORD; keyword <= SPD::SPD_LAST_NORM_KEYWORD; keyword++ ) { @@ -154,14 +170,29 @@ class SPDTest: public CxxTest::TestSuite } else if( SPD_DDR4_TYPE == memType ) { + size_t dataSize = (modType == DDIMM) + ? (sizeof(ddr4DDIMMData)/sizeof(ddr4DDIMMData[0])) + : (sizeof(ddr4Data)/sizeof(ddr4Data[0])); + for( entry = 0; - entry < (sizeof(ddr4Data)/sizeof(ddr4Data[0])); + entry < dataSize; entry++ ) { - if( keyword == ddr4Data[entry].keyword ) + if (modType == DDIMM) { - theSize = ddr4Data[entry].length; - break; + if( keyword == ddr4DDIMMData[entry].keyword ) + { + theSize = ddr4DDIMMData[entry].length; + break; + } + } + else + { + if( keyword == ddr4Data[entry].keyword ) + { + theSize = ddr4Data[entry].length; + break; + } } } } @@ -304,6 +335,21 @@ class SPDTest: public CxxTest::TestSuite break; } + // Get the module type. + modSpecTypes_t modType = NA; + err = getModType(modType, + theTarget, + memType, + VPD::AUTOSELECT); + if( err ) + { + fails++; + TS_FAIL("testSpdRead- Failure reading memory module type!"); + errlCommit( err, + VPD_COMP_ID ); + break; + } + // Get the size if( SPD_DDR3_TYPE == memType ) { @@ -320,14 +366,29 @@ class SPDTest: public CxxTest::TestSuite } else if( SPD_DDR4_TYPE == memType ) { + size_t dataSize = (modType == DDIMM) + ? (sizeof(ddr4DDIMMData)/sizeof(ddr4DDIMMData[0])) + : (sizeof(ddr4Data)/sizeof(ddr4Data[0])); + for( uint32_t entry = 0; - entry < (sizeof(ddr4Data)/sizeof(ddr4Data[0])); + entry < dataSize; entry++ ) { - if( SPD::DIMM_BAD_DQ_DATA == ddr4Data[entry].keyword ) + if (modType == DDIMM) { - theSize = ddr4Data[entry].length; - break; + if( SPD::DIMM_BAD_DQ_DATA == ddr4DDIMMData[entry].keyword ) + { + theSize = ddr4DDIMMData[entry].length; + break; + } + } + else + { + if( SPD::DIMM_BAD_DQ_DATA == ddr4Data[entry].keyword ) + { + theSize = ddr4Data[entry].length; + break; + } } } } @@ -343,6 +404,14 @@ class SPDTest: public CxxTest::TestSuite break; } + if( 0 == theSize ) + { + // memType not supported or Keyword not supported on + // this memType + cmds++; + break; + } + // Allocate data buffer origData = static_cast<uint8_t*>(malloc( theSize )); @@ -892,6 +961,21 @@ class SPDTest: public CxxTest::TestSuite break; } + // Get the module type. + modSpecTypes_t modType = NA; + err = getModType(modType, + theTarget, + memType, + VPD::AUTOSELECT); + if( err ) + { + fails++; + TS_FAIL("testSpdRead- Failure reading memory module type!"); + errlCommit( err, + VPD_COMP_ID ); + break; + } + // The real Keyword read testing for( uint64_t keyword = SPD::SPD_FIRST_MOD_SPEC; keyword <= SPD::SPD_LAST_MOD_SPEC; keyword++ ) @@ -922,15 +1006,31 @@ class SPDTest: public CxxTest::TestSuite } else if( SPD_DDR4_TYPE == memType ) { + size_t dataSize = (modType == DDIMM) + ? (sizeof(ddr4DDIMMData)/sizeof(ddr4DDIMMData[0])) + : (sizeof(ddr4Data)/sizeof(ddr4Data[0])); + for( entry = 0; - entry < (sizeof(ddr4Data)/sizeof(ddr4Data[0])); + entry < dataSize; entry++ ) { - if( keyword == ddr4Data[entry].keyword ) + if (modType == DDIMM) { - kwdData = ddr4Data[entry]; - theSize = ddr4Data[entry].length; - break; + if( keyword == ddr4DDIMMData[entry].keyword ) + { + kwdData = ddr4DDIMMData[entry]; + theSize = ddr4DDIMMData[entry].length; + break; + } + } + else + { + if( keyword == ddr4Data[entry].keyword ) + { + kwdData = ddr4Data[entry]; + theSize = ddr4Data[entry].length; + break; + } } } } diff --git a/src/usr/vpd/vpd.C b/src/usr/vpd/vpd.C index a9bc590b5..490c8bbc8 100755 --- a/src/usr/vpd/vpd.C +++ b/src/usr/vpd/vpd.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2018 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -475,55 +475,55 @@ void setPartAndSerialNumberAttributes( TARGETING::Target * i_target ) void updateSerialNumberFromBMC( TARGETING::Target * i_nodetarget ) { #ifdef CONFIG_UPDATE_SN_FROM_BMC - errlHndl_t l_errl = NULL; - size_t l_vpdSize = 0; - - //Get Product Serial Number from Backplane - char* l_sn_prod = NULL; - l_sn_prod = IPMIFRUINV::getProductSN(0); - if (l_sn_prod != NULL) - { - TRACFCOMP(g_trac_vpd, "Got system serial number from BMC."); - TRACFCOMP(g_trac_vpd, "SN from BMC is: %s", l_sn_prod); - - l_errl = deviceRead(i_nodetarget, NULL, l_vpdSize, - DEVICE_PVPD_ADDRESS( PVPD::OSYS, PVPD::SS )); - - if(l_errl == NULL) - { - uint8_t l_vpddata[l_vpdSize]; - - l_errl = deviceRead(i_nodetarget, l_vpddata, l_vpdSize, - DEVICE_PVPD_ADDRESS( PVPD::OSYS, PVPD::SS )); - - if(l_errl == NULL) - { - TRACFCOMP(g_trac_vpd, "SN in PVPD::OSYS:SS: %s, size: %d", l_vpddata, l_vpdSize); - - if (strncmp(l_sn_prod, l_vpddata, l_vpdSize) != 0) - { - l_errl = deviceWrite(i_nodetarget, l_sn_prod, l_vpdSize, - DEVICE_PVPD_ADDRESS( PVPD::OSYS, PVPD::SS )); - CONSOLE::displayf(NULL, "updated SN from BMC into PVPD."); - CONSOLE::flush(); - CONSOLE::displayf(NULL, "Need a reboot."); - CONSOLE::flush(); - INITSERVICE::requestReboot(); - } - } - } - - if(l_errl) - { - ERRORLOG::errlCommit(l_errl,VPD_COMP_ID); - } - - //getProductSN requires the caller to delete the char array - delete[] l_sn_prod; - l_sn_prod = NULL; - - TRACFCOMP(g_trac_vpd, "End updateSerialNumberFromBMC."); - } + errlHndl_t l_errl = NULL; + size_t l_vpdSize = 0; + + //Get Product Serial Number from Backplane + char* l_sn_prod = NULL; + l_sn_prod = IPMIFRUINV::getProductSN(0); + if (l_sn_prod != NULL) + { + TRACFCOMP(g_trac_vpd, "Got system serial number from BMC."); + TRACFCOMP(g_trac_vpd, "SN from BMC is: %s", l_sn_prod); + + l_errl = deviceRead(i_nodetarget, NULL, l_vpdSize, + DEVICE_PVPD_ADDRESS( PVPD::OSYS, PVPD::SS )); + + if(l_errl == NULL) + { + uint8_t l_vpddata[l_vpdSize]; + + l_errl = deviceRead(i_nodetarget, l_vpddata, l_vpdSize, + DEVICE_PVPD_ADDRESS( PVPD::OSYS, PVPD::SS )); + + if(l_errl == NULL) + { + TRACFCOMP(g_trac_vpd, "SN in PVPD::OSYS:SS: %s, size: %d", l_vpddata, l_vpdSize); + + if (strncmp(l_sn_prod, l_vpddata, l_vpdSize) != 0) + { + l_errl = deviceWrite(i_nodetarget, l_sn_prod, l_vpdSize, + DEVICE_PVPD_ADDRESS( PVPD::OSYS, PVPD::SS )); + CONSOLE::displayf(NULL, "updated SN from BMC into PVPD."); + CONSOLE::flush(); + CONSOLE::displayf(NULL, "Need a reboot."); + CONSOLE::flush(); + INITSERVICE::requestReboot(); + } + } + } + + if(l_errl) + { + ERRORLOG::errlCommit(l_errl,VPD_COMP_ID); + } + + //getProductSN requires the caller to delete the char array + delete[] l_sn_prod; + l_sn_prod = NULL; + + TRACFCOMP(g_trac_vpd, "End updateSerialNumberFromBMC."); + } #endif } @@ -590,56 +590,19 @@ errlHndl_t getPnAndSnRecordAndKeywords( TARGETING::Target * i_target, io_keywordSN = CVPD::SN; #endif } - else if( i_type == TARGETING::TYPE_DIMM ) + else if(( i_type == TARGETING::TYPE_DIMM ) + || (i_type == TARGETING::TYPE_OCMB_CHIP)) { // SPD does not have singleton instance - // SPD does not use records + // SPD does not use record io_keywordPN = SPD::MODULE_PART_NUMBER; io_keywordSN = SPD::MODULE_SERIAL_NUMBER; } else if( i_type == TARGETING::TYPE_NODE ) { -#if defined(CONFIG_PVPD_READ_FROM_HW) && defined(CONFIG_PVPD_READ_FROM_PNOR) - IpVpdFacade* l_ipvpd = &(Singleton<PvpdFacade>::instance()); io_record = PVPD::OPFR; io_keywordPN = PVPD::VP; io_keywordSN = PVPD::VS; - - bool l_zeroPN; - l_err = l_ipvpd->cmpSeepromToZero( i_target, - io_record, - io_keywordPN, - l_zeroPN ); - if (l_err) - { - TRACFCOMP(g_trac_vpd,ERR_MRK"VPD::getPnAndSnRecordAndKeywords: Error checking if OPFR:VP == 0"); - break; - } - - bool l_zeroSN; - l_err = l_ipvpd->cmpSeepromToZero( i_target, - io_record, - io_keywordSN, - l_zeroSN ); - if (l_err) - { - TRACFCOMP(g_trac_vpd,ERR_MRK"VPD::getPnAndSnRecordAndKeywords: Error checking if OPFR:VS == 0"); - break; - } - - // If VP and VS are zero, use VINI instead - if( l_zeroPN && l_zeroSN ) - { - TRACFCOMP(g_trac_vpd, "setting cvpd to VINI PN SN"); - io_record = PVPD::VINI; - io_keywordPN = PVPD::PN; - io_keywordSN = PVPD::SN; - } -#else - io_record = PVPD::VINI; - io_keywordPN = PVPD::PN; - io_keywordSN = PVPD::SN; -#endif } else if( i_type == TARGETING::TYPE_MCS ) { @@ -672,6 +635,249 @@ errlHndl_t getPnAndSnRecordAndKeywords( TARGETING::Target * i_target, return l_err; } +/** + * @brief This function compares the specified record/keyword in + * CACHE/HARDWARE by calling the correct function based on the + * target's eeprom content type and returns the result. A mismatch + * will not return an error. + * + * @param[in] i_target Target device + * + * @param[in] i_eepromType Eeprom content type for the target. + * + * @param[in] i_keyword Keyword to compare + * + * @param[in] i_record Record to compare + * + * @param[out] o_match Result of compare + * + * @return errlHndl_t NULL if successful, otherwise a pointer to the + * error log. + */ +errlHndl_t cmpEecacheToEeprom(TARGETING::Target * i_target, + TARGETING::EEPROM_CONTENT_TYPE i_eepromType, + vpdKeyword i_keyword, + vpdRecord i_record, + bool& o_match) +{ + errlHndl_t l_err = nullptr; + + if ( (i_eepromType == TARGETING::EEPROM_CONTENT_TYPE_IBM_MVPD) + || (i_eepromType == TARGETING::EEPROM_CONTENT_TYPE_IBM_FRUVPD)) + { + auto l_type = i_target->getAttr<TARGETING::ATTR_TYPE>(); + IpVpdFacade* l_ipvpd = &(Singleton<MvpdFacade>::instance()); + + // If we have a NODE, use pvpd api + if(l_type == TARGETING::TYPE_NODE) + { + l_ipvpd = &(Singleton<PvpdFacade>::instance()); + } + + l_err = l_ipvpd->cmpEecacheToEeprom(i_target, + i_record, + i_keyword, + o_match); + } + else if ( (i_eepromType == TARGETING::EEPROM_CONTENT_TYPE_ISDIMM) + || (i_eepromType == TARGETING::EEPROM_CONTENT_TYPE_DDIMM)) + { + l_err = SPD::cmpEecacheToEeprom(i_target, + i_eepromType, + i_keyword, + o_match); + } + else + { + assert(false, "Error, invalid EEPROM type 0x%x for target HUID 0x%X passed to cmpEecacheToEeprom", + i_eepromType, get_huid(i_target)); + } + + return l_err; +} + + +// ------------------------------------------------------------------ +// ensureEepromCacheIsInSync +// ------------------------------------------------------------------ +errlHndl_t ensureEepromCacheIsInSync(TARGETING::Target * i_target, + TARGETING::EEPROM_CONTENT_TYPE i_eepromType, + bool & o_isInSync) +{ + errlHndl_t l_err = nullptr; + + TRACDCOMP(g_trac_vpd, ENTER_MRK"ensureEepromCacheIsInSync() "); + + vpdRecord l_record = 0; + vpdKeyword l_keywordPN = 0; + vpdKeyword l_keywordSN = 0; + TARGETING::TYPE l_type = i_target->getAttr<TARGETING::ATTR_TYPE>(); + + do + { + // Get the correct Part and serial numbers + l_err = getPnAndSnRecordAndKeywords(i_target, + i_target-> + getAttr<TARGETING::ATTR_TYPE>(), + l_record, + l_keywordPN, + l_keywordSN); + if( l_err ) + { + TRACFCOMP(g_trac_vpd, + "VPD::ensureEepromCacheIsInSync: " + "Error getting part and serial numbers"); + break; + } + + // Compare the Part Numbers in CACHE/HARDWARE + bool l_matchPN = false; + l_err = cmpEecacheToEeprom(i_target, + i_eepromType, + l_keywordPN, + l_record, + l_matchPN); + + if (l_err) + { + TRACFCOMP(g_trac_vpd,ERR_MRK + "VPD::ensureEepromCacheIsInSync: " + "Error checking for CACHE/HARDWARE PN match"); + break; + } + + // Compare the Serial Numbers in CACHE/HARDWARE + bool l_matchSN = false; + l_err = cmpEecacheToEeprom(i_target, + i_eepromType, + l_keywordSN, + l_record, + l_matchSN); + + if (l_err) + { + TRACFCOMP(g_trac_vpd, ERR_MRK + "VPD::ensureEepromCacheIsInSync: Error checking for " + "CACHE/HARDWARE SN match"); + break; + } + + // Check the serial number and part number of the system if the previous + // record/key pair matched. Note that this time the record/key pairs are + // OSYS/SS and OSYS/MM for serial number and part number, respectively + if (l_type == TARGETING::TYPE_NODE && + (l_matchSN && l_matchPN)) + { + // If we have a NODE, use pvpd api + IpVpdFacade* l_ipvpd = &(Singleton<PvpdFacade>::instance()); + bool l_zeroPN = false; + bool l_zeroSN = false; + l_err = l_ipvpd->cmpSeepromToZero(i_target, + PVPD::OSYS, + PVPD::MM, + l_zeroPN); + if(l_err) + { + TRACDCOMP(g_trac_vpd,ERR_MRK"VPD::ensureEepromCacheIsInSync: " + "cmpSeepromToZero returned an error. Assuming this error is " + "related to OSYS/MM not being present in SEEPROM. Skipping " + "this error. HUID: 0x%.8X", + TARGETING::get_huid(i_target)); + delete l_err; + l_err = nullptr; + l_zeroPN = true; + + } + + l_err = l_ipvpd->cmpSeepromToZero(i_target, + PVPD::OSYS, + PVPD::SS, + l_zeroSN); + if(l_err) + { + TRACDCOMP(g_trac_vpd,ERR_MRK"VPD::ensureEepromCacheIsInSync: " + "cmpSeepromToZero returned an error. Assuming this error is " + "related to OSYS/SS not being present in SEEPROM. Skipping " + "this error. HUID: 0x%.8X", + TARGETING::get_huid(i_target)); + delete l_err; + l_err = nullptr; + l_zeroSN = true; + } + + //Only compare the SN/PN between SEEPROM and EECACHE if they are + //nonzero. + if(!l_zeroPN) + { + l_err = cmpEecacheToEeprom(i_target, + i_eepromType, + PVPD::MM, + PVPD::OSYS, + l_matchPN); + if(l_err) + { + TRACFCOMP(g_trac_vpd,ERR_MRK"VPD::ensureEepromCacheIsInSync: Error" + " checking for EECACHE/SEEPROM PN match for NODE target 0x%.8X", + TARGETING::get_huid(i_target)); + break; + } + } + + if(!l_zeroSN) + { + l_err = cmpEecacheToEeprom(i_target, + i_eepromType, + PVPD::SS, + PVPD::OSYS, + l_matchSN); + if(l_err) + { + TRACFCOMP(g_trac_vpd,ERR_MRK"VPD::ensureEepromCacheIsInSync: Error" + " checking for EECACHE/SEEPROM SN match for NODE target 0x%.8X", + TARGETING::get_huid(i_target)); + break; + } + } + } + + o_isInSync = (l_matchPN && l_matchSN); + + // If we did not match, we need to load HARDWARE VPD data into CACHE + if (o_isInSync) + { + TRACFCOMP(g_trac_vpd, + "VPD::ensureEepromCacheIsInSync: " + "CACHE_PN/SN == HARDWARE_PN/SN for target %.8X", + TARGETING::get_huid(i_target)); + } + else + { + TRACFCOMP(g_trac_vpd, + "VPD::ensureEepromCacheIsInSync: CACHE_PN/SN != HARDWARE_PN/SN,CACHE must be loaded from HARDWARE for target %.8X", + TARGETING::get_huid(i_target)); + const char* l_pathstring + = i_target->getAttr<TARGETING::ATTR_PHYS_PATH>().toString(); + CONSOLE::displayf(NULL,"Detected new part : %.8X (%s)", + TARGETING::get_huid(i_target), + l_pathstring); + free((void*)(l_pathstring)); + l_pathstring = nullptr; + CONSOLE::flush(); +#ifndef CONFIG_SUPPORT_EEPROM_CACHING + //Set the targets as changed since the p/n's don't match + HWAS::markTargetChanged(i_target); +#else + //No need to mark target changed here, it will be handled by eecache code +#endif + } + + } while(0); + + TRACDCOMP(g_trac_vpd, EXIT_MRK"ensureEepromCacheIsInSync()"); + + return l_err; +} + // ------------------------------------------------------------------ // ensureCacheIsInSync // ------------------------------------------------------------------ @@ -842,6 +1048,14 @@ errlHndl_t ensureCacheIsInSync ( TARGETING::Target * i_target ) else { TRACFCOMP(g_trac_vpd,"VPD::ensureCacheIsInSync: PNOR_PN/SN != SEEPROM_PN/SN, Loading PNOR from SEEPROM for target %.8X",TARGETING::get_huid(i_target)); + const char* l_pathstring = + i_target->getAttr<TARGETING::ATTR_PHYS_PATH>().toString(); + CONSOLE::displayf(NULL,"Detected new part : %.8X (%s)", + TARGETING::get_huid(i_target), + l_pathstring); + free((void*)(l_pathstring)); + l_pathstring = nullptr; + CONSOLE::flush(); //Set the targets as changed since the p/n's don't match HWAS::markTargetChanged(i_target); @@ -1122,14 +1336,16 @@ void getListOfOverrideSections( OverrideRsvMemMap_t& o_overrides ) delete l_elog; return; } + else + { + // Add MEMD section + OverrideSpecifier_t l_memd = { + PNOR::MEMD, + l_memd_info.size + }; - // Add MEMD section - OverrideSpecifier_t l_memd = { - PNOR::MEMD, - l_memd_info.size - }; - - o_overrides[0x4D454D44/*MEMD*/] = l_memd; + o_overrides[0x4D454D44/*MEMD*/] = l_memd; + } } }; //end VPD namespace diff --git a/src/usr/vpd/vpd.mk b/src/usr/vpd/vpd.mk index d5717e653..aa3333291 100644 --- a/src/usr/vpd/vpd.mk +++ b/src/usr/vpd/vpd.mk @@ -34,4 +34,5 @@ OBJS += cvpd.o OBJS += pvpd.o OBJS += dvpd.o OBJS += spd.o +OBJS += ocmb_spd.o OBJS += errlud_vpd.o diff --git a/src/usr/vpd/vpd_common.C b/src/usr/vpd/vpd_common.C index 0196b8be8..92c4e9294 100644 --- a/src/usr/vpd/vpd_common.C +++ b/src/usr/vpd/vpd_common.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2018 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -156,6 +156,8 @@ bool resolveVpdSource( TARGETING::Target * i_target, } } + TRACDCOMP(g_trac_vpd,"resolveVpdSource: o_vpdSource = %s" ,o_vpdSource == VPD::PNOR ? "PNOR" : "SEEPROM" ); + return badConfig; } diff --git a/src/usr/xscom/test/xscomtest.H b/src/usr/xscom/test/xscomtest.H index a3d7076ce..03718532c 100644 --- a/src/usr/xscom/test/xscomtest.H +++ b/src/usr/xscom/test/xscomtest.H @@ -71,9 +71,10 @@ const testXscomAddrData g_xscomMultiWriteTable[] = {0x21010A89, 0x0200000000000000}, {0x22010A89, 0x0030000000000000}, {0x23010A89, 0x0004000000000000}, - // Local checkstop regs - {0x10040018, 0x1000000000000000}, // ChipletID 0x10 - {0x20040018, 0x1000000000000000}, // ChipletID 0x20 + // Group0 Xstop mask regs, TPEQPCC.EPS.FIR.GXSTOP0_MASK_REG + // Use register without actions attached to it + {0x10040014, 0x8000000000000000}, // ChipletID 0x10, set bit0 + {0x20040014, 0x8000000000000000}, // ChipletID 0x20, set bit0 }; const uint32_t g_xscomMultiWriteTableSz = sizeof(g_xscomMultiWriteTable)/sizeof(testXscomAddrData); @@ -85,10 +86,10 @@ const testXscomAddrData g_xscomMultiReadTable[] = // Scratch reg 3 // Multicast OR op {0x41010a89, 0x1234000000000000}, - // Local checkstop regs + // Group0 Xstop Mask regs, TPEQPCC.EPS.FIR.GXSTOP0_MASK_REG // ChipletID 0x10 0x20 // Multicast BITWISE op - {0x50040018, 0x0000800080000000}, + {0x50040014, 0x0000800080000000}, }; const uint32_t g_xscomMultiReadTableSz = sizeof(g_xscomMultiReadTable)/sizeof(testXscomAddrData); @@ -404,8 +405,8 @@ public: uint32_t l_num; do { -#if defined(CONFIG_EARLY_TESTCASES) || defined(CONFIG_AXONE_BRING_UP) - TS_TRACE("testXscom4: Skipping test, multicast groups not setup yet"); +#if defined(CONFIG_EARLY_TESTCASES) + TS_INFO("testXscom4: Skipping test, multicast groups not setup yet"); break; #endif diff --git a/src/usr/xscom/xscom.C b/src/usr/xscom/xscom.C index 73d7e9e22..3b3a59d40 100644 --- a/src/usr/xscom/xscom.C +++ b/src/usr/xscom/xscom.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2018 */ +/* Contributors Listed Below - COPYRIGHT 2011,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -810,11 +810,8 @@ uint64_t generate_mmio_addr( TARGETING::Target* i_proc, // Build the XSCom address (relative to group 0, chip 0) XSComP9Address l_mmioAddr(i_scomAddr); - // Get the offset - uint64_t l_offset = l_mmioAddr.offset(); - // Compute value relative to target chip - l_returnAddr = l_XSComBaseAddr + l_offset; + l_returnAddr = l_XSComBaseAddr + l_mmioAddr; return l_returnAddr; } |
