diff options
Diffstat (limited to 'src/usr/hwas/common/hwas.C')
| -rw-r--r-- | src/usr/hwas/common/hwas.C | 148 |
1 files changed, 128 insertions, 20 deletions
diff --git a/src/usr/hwas/common/hwas.C b/src/usr/hwas/common/hwas.C index 45a88cf85..94d947dad 100644 --- a/src/usr/hwas/common/hwas.C +++ b/src/usr/hwas/common/hwas.C @@ -41,7 +41,6 @@ #include <stdio.h> // sprintf #ifdef __HOSTBOOT_MODULE -#include <config.h> #include <initservice/initserviceif.H> #endif @@ -569,6 +568,59 @@ errlHndl_t discoverMuxTargetsAndEnable(const Target &i_sysTarget) return l_err; } +/** + * @brief Do presence detect on only PMIC targets and enable HWAS state + * + * @param[in] i_sysTarget the top level target (CLASS_SYS) + * @return errlHndl_t return nullptr if no error, + * else return a handle to an error entry + * + */ +errlHndl_t discoverPmicTargetsAndEnable(const Target &i_sysTarget) +{ + HWAS_INF(ENTER_MRK"discoverPmicTargetsAndEnable"); + + errlHndl_t l_err{nullptr}; + + do + { + // Only get PMIC targets + const PredicateCTM l_pmicPred(CLASS_ASIC, TYPE_PMIC); + TARGETING::PredicatePostfixExpr l_asicPredExpr; + l_asicPredExpr.push(&l_pmicPred); + TargetHandleList l_pPmicCheckPres; + targetService().getAssociated( l_pPmicCheckPres, (&i_sysTarget), + TargetService::CHILD, TargetService::ALL, &l_asicPredExpr); + + // Do the presence detect on only PMIC targets + // NOTE: this function will remove any non-functional targets + // from pPmicCheckPres + l_err = platPresenceDetect(l_pPmicCheckPres); + + // If an issue with platPresenceDetect, then exit, returning + // error back to caller + if (nullptr != l_err) + { + break; + } + + // Enable the HWAS State for the PMICs + const bool l_present(true); + const bool l_functional(true); + const uint32_t l_errlEid(0); + for (TargetHandle_t pTarget : l_pPmicCheckPres) + { + // set HWAS state to show PMIC is present and functional + enableHwasState(pTarget, l_present, l_functional, l_errlEid); + } + } while (0); + + HWAS_INF(EXIT_MRK"discoverPmicTargetsAndEnable exit with %s", + (nullptr == l_err ? "no error" : "error")); + + return l_err; +} + errlHndl_t discoverTargets() { HWAS_DBG("discoverTargets entry"); @@ -643,11 +695,13 @@ errlHndl_t discoverTargets() PredicateCTM predPmic(CLASS_ASIC, TYPE_PMIC); // We can ignore chips of TYPE_I2C_MUX because they // were already detected above in discoverMuxTargetsAndEnable + // Also we can ignore chips of type PMIC because they will be processed + // below. PredicateCTM predMux(CLASS_CHIP, TYPE_I2C_MUX); PredicatePostfixExpr checkExpr; checkExpr.push(&predChip).push(&predDimm).Or().push(&predEnc).Or(). - push(&predMcs).Or().push(&predPmic).Or(). - push(&predMux).Not().And(); + push(&predMcs).Or().push(&predMux).Not().And(). + push(&predPmic).Not().And(); TargetHandleList pCheckPres; targetService().getAssociated( pCheckPres, pSys, @@ -728,19 +782,22 @@ errlHndl_t discoverTargets() MOD_DISCOVER_TARGETS, RC_PARTIAL_GOOD_INFORMATION); - if( (pTarget->getAttr<ATTR_CLASS>() == CLASS_CHIP) && - (l_targetType != TYPE_TPM) && - (l_targetType != TYPE_SP) && - (l_targetType != TYPE_BMC) && - (l_targetType != TYPE_I2C_MUX)) + if( (pTarget->getAttr<ATTR_CLASS>() == CLASS_CHIP) + && (l_targetType != TYPE_TPM) + && (l_targetType != TYPE_SP) + && (l_targetType != TYPE_BMC) + && (l_targetType != TYPE_I2C_MUX)) { // read Chip ID/EC data from these physical chips errl = platReadIDEC(pTarget); if (errl) - { // read of ID/EC failed even tho we THOUGHT we were present. - HWAS_INF("pTarget %.8X - read IDEC failed (eid 0x%X) - bad", - errl->eid(), pTarget->getAttr<ATTR_HUID>()); + { + // read of ID/EC failed even tho we THOUGHT we were present. + HWAS_INF("pTarget 0x%.8X - read IDEC failed " + "(eid 0x%X) - bad", + get_huid(pTarget), errl->eid()); + // chip NOT present and NOT functional, so that FSP doesn't // include this for HB to process chipPresent = false; @@ -758,8 +815,9 @@ errlHndl_t discoverTargets() if (errl) { // read of PG failed even tho we were present.. - HWAS_INF("pTarget %.8X - read PG failed (eid 0x%X)- bad", - errl->eid(), pTarget->getAttr<ATTR_HUID>()); + HWAS_INF("pTarget 0x%.8X - read PG failed " + "(eid 0x%X) - bad", + get_huid(pTarget), errl->eid()); chipFunctional = false; errlEid = errl->eid(); @@ -861,6 +919,16 @@ errlHndl_t discoverTargets() } // for pTarget_it + // After processing all other targets look at the pmics, + // we must wait because we need the SPD cached from the OCMBs + // which occurs when OCMBs go through presence detection above + errl = discoverPmicTargetsAndEnable(*pSys); + + if (errl != NULL) + { + break; // break out of the do/while so that we can return + } + // Check for non-present Procs and if found, trigger // DeconfigGard::_invokeDeconfigureAssocProc() to run by setting // setXAOBusEndpointDeconfigured to true @@ -966,6 +1034,13 @@ bool isChipFunctional(const TARGETING::TargetHandle_t &i_target, uint16_t l_xbus = (l_model == MODEL_NIMBUS) ? VPD_CP00_PG_XBUS_GOOD_NIMBUS : VPD_CP00_PG_XBUS_GOOD_CUMULUS; + uint16_t l_perv = (l_model == MODEL_AXONE) ? + VPD_CP00_PG_PERVASIVE_GOOD_AXONE : VPD_CP00_PG_PERVASIVE_GOOD; + + uint16_t l_n2 = (l_model == MODEL_AXONE) ? + VPD_CP00_PG_N2_GOOD_AXONE : VPD_CP00_PG_N2_GOOD; + + // Check all bits in FSI entry if (i_pgData[VPD_CP00_PG_FSI_INDEX] != VPD_CP00_PG_FSI_GOOD) @@ -981,14 +1056,14 @@ bool isChipFunctional(const TARGETING::TargetHandle_t &i_target, else // Check all bits in PRV entry if (i_pgData[VPD_CP00_PG_PERVASIVE_INDEX] != - VPD_CP00_PG_PERVASIVE_GOOD) + l_perv) { HWAS_INF("pTarget %.8X - Pervasive pgData[%d]: " "actual 0x%04X, expected 0x%04X - bad", i_target->getAttr<ATTR_HUID>(), VPD_CP00_PG_PERVASIVE_INDEX, i_pgData[VPD_CP00_PG_PERVASIVE_INDEX], - VPD_CP00_PG_PERVASIVE_GOOD); + l_perv); l_chipFunctional = false; } else @@ -1018,14 +1093,14 @@ bool isChipFunctional(const TARGETING::TargetHandle_t &i_target, } else // Check all bits in N2 entry - if (i_pgData[VPD_CP00_PG_N2_INDEX] != VPD_CP00_PG_N2_GOOD) + if (i_pgData[VPD_CP00_PG_N2_INDEX] != l_n2) { HWAS_INF("pTarget %.8X - N2 pgData[%d]: " "actual 0x%04X, expected 0x%04X - bad", i_target->getAttr<ATTR_HUID>(), VPD_CP00_PG_N2_INDEX, i_pgData[VPD_CP00_PG_N2_INDEX], - VPD_CP00_PG_N2_GOOD); + l_n2); l_chipFunctional = false; } else @@ -3839,7 +3914,7 @@ errlHndl_t updateProcCompatibilityRiskLevel() "force compatibility of invalid MRW risk level %d", l_risk); - /* + /*@ * @errortype * @severity ERRL_SEV_UNRECOVERABLE * @moduleid MOD_UPDATE_PROC_COMPAT_RISK_LEVEL @@ -3906,7 +3981,7 @@ errlHndl_t updateProcCompatibilityRiskLevel() "force native compatibility of mixed processor levels", " (0x%02X and 0x%02X)", l_firstEc, l_lastEc ); - /* + /*@ * @errortype * @severity ERRL_SEV_UNRECOVERABLE * @moduleid MOD_UPDATE_PROC_COMPAT_RISK_LEVEL @@ -3977,7 +4052,7 @@ errlHndl_t updateProcCompatibilityRiskLevel() "force native compatibility of DD2.3 for risk level %d", l_risk); - /* + /*@ * @errortype * @severity ERRL_SEV_UNRECOVERABLE * @moduleid MOD_UPDATE_PROC_COMPAT_RISK_LEVEL @@ -4064,6 +4139,33 @@ errlHndl_t updateProcCompatibilityRiskLevel() return l_err; } +/** + * @brief Normalize the RISK_LEVEL for Axone to use the upper range + */ +void normalizeRiskLevelForAxone( void ) +{ + // Axone follows Nimbus DD2.3 settings except it can use + // the low or high numbers. Let's normalize it to the + // high range to make things less confusing. + Target* pSys; + targetService().getTopLevelTarget(pSys); + auto l_risk = pSys->getAttr<TARGETING::ATTR_RISK_LEVEL>(); + if( TARGETING::UTIL::P9A_RUGBY_FAVOR_SECURITY_LOWER == l_risk ) + { + l_risk = TARGETING::UTIL::P9A_RUGBY_FAVOR_SECURITY; + } + else if( TARGETING::UTIL::P9A_RUGBY_FAVOR_PERFORMANCE_LOWER == l_risk ) + { + l_risk = TARGETING::UTIL::P9A_RUGBY_FAVOR_PERFORMANCE; + } + else + { + // Nothing to change, just leave + return; + } + pSys->setAttr<TARGETING::ATTR_RISK_LEVEL>(l_risk); +} + errlHndl_t validateProcessorEcLevels() { HWAS_INF("validateProcessorEcLevels entry"); @@ -4109,6 +4211,12 @@ errlHndl_t validateProcessorEcLevels() break; } } + else if(TARGETING::MODEL_AXONE == l_model) + { + // Axone follows Nimbus DD2.3 settings except it can use + // the low or high numbers, going to force one way. + normalizeRiskLevelForAxone(); + } //Loop through all functional procs and create error logs //for any processors whose EC does not match the master |
