diff options
Diffstat (limited to 'src/usr/vpd/spdDDR3.H')
| -rw-r--r-- | src/usr/vpd/spdDDR3.H | 136 |
1 files changed, 68 insertions, 68 deletions
diff --git a/src/usr/vpd/spdDDR3.H b/src/usr/vpd/spdDDR3.H index 06fc33aa5..26aa36660 100644 --- a/src/usr/vpd/spdDDR3.H +++ b/src/usr/vpd/spdDDR3.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2015 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -68,74 +68,74 @@ const KeywordData ddr3Data[] = // Number Case able Spec // ------------------------------------------------------------------------------------------ // Normal fields supported on both DDR3 and DDR4 - { CRC_EXCLUDE, 0x00, 0x01, 0x80, 0x07, false, false, NA }, - { SPD_BYTES_TOTAL, 0x00, 0x01, 0x70, 0x04, false, false, NA }, - { SPD_BYTES_USED, 0x00, 0x01, 0x0F, 0x00, false, false, NA }, - { SPD_MAJOR_REVISION, 0x01, 0x01, 0xF0, 0x04, false, false, NA }, - { SPD_MINOR_REVISION, 0x01, 0x01, 0x0F, 0x00, false, false, NA }, - { BASIC_MEMORY_TYPE, 0x02, 0x01, 0x00, 0x00, false, false, NA }, - { CUSTOM, 0x03, 0x01, 0x80, 0x07, false, false, NA }, - { MODULE_TYPE, 0x03, 0x01, 0x0F, 0x00, false, false, NA }, - { DENSITY, 0x04, 0x01, 0x0F, 0x00, false, false, NA }, - { ROW_ADDRESS, 0x05, 0x01, 0x38, 0x03, false, false, NA }, - { COL_ADDRESS, 0x05, 0x01, 0x07, 0x00, false, false, NA }, - { MODULE_RANKS, 0x07, 0x01, 0x38, 0x03, false, false, NA }, - { MODULE_DRAM_WIDTH, 0x07, 0x01, 0x07, 0x00, false, false, NA }, - { MODULE_MEMORY_BUS_WIDTH, 0x08, 0x01, 0x1f, 0x00, false, false, NA }, - { MODULE_MEMORY_BUS_WIDTH_EXT, 0x08, 0x01, 0x18, 0x03, false, false, NA }, - { MODULE_MEMORY_BUS_WIDTH_PRI, 0x08, 0x01, 0x07, 0x00, false, false, NA }, - { TCK_MIN, 0x0c, 0x01, 0x00, 0x00, false, false, NA }, - { MIN_CAS_LATENCY, 0x10, 0x01, 0x00, 0x00, false, false, NA }, - { TRCD_MIN, 0x12, 0x01, 0x00, 0x00, false, false, NA }, - { TRP_MIN, 0x14, 0x01, 0x00, 0x00, false, false, NA }, - { TRC_MIN, 0x15, 0x02, 0xF0, 0x04, true, false, NA }, - { TRAS_MIN, 0x15, 0x02, 0x0F, 0x00, false, false, NA }, - { TFAW_MIN, 0x1c, 0x02, 0x0F, 0x00, false, false, NA }, - { SDRAM_OPTIONAL_FEATURES, 0x1e, 0x01, 0x00, 0x00, false, false, NA }, - { SDRAM_THERMAL_REFRESH_OPTIONS, 0x1f, 0x01, 0x00, 0x00, false, false, NA }, - { MODULE_THERMAL_SENSOR, 0x20, 0x01, 0x00, 0x00, false, false, NA }, - { THERMAL_SENSOR_PRESENT, 0x20, 0x01, 0x80, 0x07, false, false, NA }, - { THERMAL_SENSOR_ACCURACY, 0x20, 0x01, 0x7F, 0x00, false, false, NA }, - { SDRAM_DEVICE_TYPE, 0x21, 0x01, 0x80, 0x07, false, false, NA }, - { SDRAM_DIE_COUNT, 0x21, 0x01, 0x70, 0x04, false, false, NA }, - { SDRAM_DEVICE_TYPE_SIGNAL_LOADING, 0x21, 0x01, 0x03, 0x00, false, false, NA }, - { TCKMIN_FINE_OFFSET, 0x22, 0x01, 0x00, 0x00, false, false, NA }, - { TAAMIN_FINE_OFFSET, 0x23, 0x01, 0x00, 0x00, false, false, NA }, - { TRCDMIN_FINE_OFFSET, 0x24, 0x01, 0x00, 0x00, false, false, NA }, - { TRPMIN_FINE_OFFSET, 0x25, 0x01, 0x00, 0x00, false, false, NA }, - { TRCMIN_FINE_OFFSET, 0x26, 0x01, 0x00, 0x00, false, false, NA }, - { MODULE_TYPE_SPECIFIC_SECTION, 0x3c, 0x39, 0x00, 0x00, false, false, NA }, - { MODULE_MANUFACTURER_ID, 0x76, 0x02, 0x00, 0x00, true, false, NA }, - { MODULE_MANUFACTURING_LOCATION, 0x77, 0x01, 0x00, 0x00, false, false, NA }, - { MODULE_MANUFACTURING_DATE, 0x78, 0x02, 0x00, 0x00, false, false, NA }, - { MODULE_SERIAL_NUMBER, 0x7a, 0x04, 0x00, 0x00, false, false, NA }, - { MODULE_PART_NUMBER, 0x80, 0x12, 0x00, 0x00, false, false, NA }, - { DRAM_MANUFACTURER_ID, 0x95, 0x02, 0x00, 0x00, true, false, NA }, - { MANUFACTURER_SPECIFIC_DATA, 0x96, 0x1a, 0x00, 0x00, false, false, NA }, - { DIMM_BAD_DQ_DATA, 0xb0, 0x50, 0x00, 0x00, false, true, NA }, + { CRC_EXCLUDE, 0x00, 0x01, 0x80, 0x07, false, false, ALL }, + { SPD_BYTES_TOTAL, 0x00, 0x01, 0x70, 0x04, false, false, ALL }, + { SPD_BYTES_USED, 0x00, 0x01, 0x0F, 0x00, false, false, ALL }, + { SPD_MAJOR_REVISION, 0x01, 0x01, 0xF0, 0x04, false, false, ALL }, + { SPD_MINOR_REVISION, 0x01, 0x01, 0x0F, 0x00, false, false, ALL }, + { BASIC_MEMORY_TYPE, 0x02, 0x01, 0x00, 0x00, false, false, ALL }, + { CUSTOM, 0x03, 0x01, 0x80, 0x07, false, false, ALL }, + { MODULE_TYPE, 0x03, 0x01, 0x0F, 0x00, false, false, ALL }, + { DENSITY, 0x04, 0x01, 0x0F, 0x00, false, false, ALL }, + { ROW_ADDRESS, 0x05, 0x01, 0x38, 0x03, false, false, ALL }, + { COL_ADDRESS, 0x05, 0x01, 0x07, 0x00, false, false, ALL }, + { MODULE_RANKS, 0x07, 0x01, 0x38, 0x03, false, false, ALL }, + { MODULE_DRAM_WIDTH, 0x07, 0x01, 0x07, 0x00, false, false, ALL }, + { MODULE_MEMORY_BUS_WIDTH, 0x08, 0x01, 0x1f, 0x00, false, false, ALL }, + { MODULE_MEMORY_BUS_WIDTH_EXT, 0x08, 0x01, 0x18, 0x03, false, false, ALL }, + { MODULE_MEMORY_BUS_WIDTH_PRI, 0x08, 0x01, 0x07, 0x00, false, false, ALL }, + { TCK_MIN, 0x0c, 0x01, 0x00, 0x00, false, false, ALL }, + { MIN_CAS_LATENCY, 0x10, 0x01, 0x00, 0x00, false, false, ALL }, + { TRCD_MIN, 0x12, 0x01, 0x00, 0x00, false, false, ALL }, + { TRP_MIN, 0x14, 0x01, 0x00, 0x00, false, false, ALL }, + { TRC_MIN, 0x15, 0x02, 0xF0, 0x04, true, false, ALL }, + { TRAS_MIN, 0x15, 0x02, 0x0F, 0x00, false, false, ALL }, + { TFAW_MIN, 0x1c, 0x02, 0x0F, 0x00, false, false, ALL }, + { SDRAM_OPTIONAL_FEATURES, 0x1e, 0x01, 0x00, 0x00, false, false, ALL }, + { SDRAM_THERMAL_REFRESH_OPTIONS, 0x1f, 0x01, 0x00, 0x00, false, false, ALL }, + { MODULE_THERMAL_SENSOR, 0x20, 0x01, 0x00, 0x00, false, false, ALL }, + { THERMAL_SENSOR_PRESENT, 0x20, 0x01, 0x80, 0x07, false, false, ALL }, + { THERMAL_SENSOR_ACCURACY, 0x20, 0x01, 0x7F, 0x00, false, false, ALL }, + { SDRAM_DEVICE_TYPE, 0x21, 0x01, 0x80, 0x07, false, false, ALL }, + { SDRAM_DIE_COUNT, 0x21, 0x01, 0x70, 0x04, false, false, ALL }, + { SDRAM_DEVICE_TYPE_SIGNAL_LOADING, 0x21, 0x01, 0x03, 0x00, false, false, ALL }, + { TCKMIN_FINE_OFFSET, 0x22, 0x01, 0x00, 0x00, false, false, ALL }, + { TAAMIN_FINE_OFFSET, 0x23, 0x01, 0x00, 0x00, false, false, ALL }, + { TRCDMIN_FINE_OFFSET, 0x24, 0x01, 0x00, 0x00, false, false, ALL }, + { TRPMIN_FINE_OFFSET, 0x25, 0x01, 0x00, 0x00, false, false, ALL }, + { TRCMIN_FINE_OFFSET, 0x26, 0x01, 0x00, 0x00, false, false, ALL }, + { MODULE_TYPE_SPECIFIC_SECTION, 0x3c, 0x39, 0x00, 0x00, false, false, ALL }, + { MODULE_MANUFACTURER_ID, 0x76, 0x02, 0x00, 0x00, true, false, ALL }, + { MODULE_MANUFACTURING_LOCATION, 0x77, 0x01, 0x00, 0x00, false, false, ALL }, + { MODULE_MANUFACTURING_DATE, 0x78, 0x02, 0x00, 0x00, false, false, ALL }, + { MODULE_SERIAL_NUMBER, 0x7a, 0x04, 0x00, 0x00, false, false, ALL }, + { MODULE_PART_NUMBER, 0x80, 0x12, 0x00, 0x00, false, false, ALL }, + { DRAM_MANUFACTURER_ID, 0x95, 0x02, 0x00, 0x00, true, false, ALL }, + { MANUFACTURER_SPECIFIC_DATA, 0x96, 0x1a, 0x00, 0x00, false, false, ALL }, + { DIMM_BAD_DQ_DATA, 0xb0, 0x50, 0x00, 0x00, false, true, ALL }, // Normal fields supported on DDR3 only - { BANK_ADDRESS_BITS, 0x04, 0x01, 0x70, 0x04, false, false, NA }, - { MODULE_NOMINAL_VOLTAGE, 0x06, 0x01, 0x07, 0x00, false, false, NA }, - { FTB_DIVIDEND, 0x09, 0x01, 0xF0, 0x04, false, false, NA }, - { FTB_DIVISOR, 0x09, 0x01, 0x0F, 0x00, false, false, NA }, - { MTB_DIVIDEND, 0x0a, 0x01, 0x00, 0x00, false, false, NA }, - { MTB_DIVISOR, 0x0b, 0x01, 0x00, 0x00, false, false, NA }, - { CAS_LATENCIES_SUPPORTED, 0x0f, 0x02, 0x7F, 0x00, true, false, NA }, - { TWR_MIN, 0x11, 0x01, 0x00, 0x00, false, false, NA }, - { TRRD_MIN, 0x13, 0x01, 0x00, 0x00, false, false, NA }, - { TRFC_MIN, 0x19, 0x02, 0x00, 0x00, true, false, NA }, - { TWTR_MIN, 0x1a, 0x01, 0x00, 0x00, false, false, NA }, - { TRTP_MIN, 0x1b, 0x01, 0x00, 0x00, false, false, NA }, - { DLL_OFF, 0x1e, 0x01, 0x80, 0x07, false, false, NA }, - { RZQ_7, 0x1e, 0x01, 0x02, 0x01, false, false, NA }, - { RZQ_6, 0x1e, 0x01, 0x01, 0x00, false, false, NA }, - { PASR, 0x1f, 0x01, 0x80, 0x07, false, false, NA }, - { ODTS, 0x1f, 0x01, 0x08, 0x03, false, false, NA }, - { ASR, 0x1f, 0x01, 0x04, 0x02, false, false, NA }, - { ETR_1X, 0x1f, 0x01, 0x02, 0x01, false, false, NA }, - { ETR, 0x1f, 0x01, 0x01, 0x00, false, false, NA }, - { MODULE_CRC, 0x7f, 0x02, 0x00, 0x00, true, false, NA }, - { MODULE_REVISION_CODE, 0x93, 0x02, 0x00, 0x00, true, false, NA }, + { BANK_ADDRESS_BITS, 0x04, 0x01, 0x70, 0x04, false, false, ALL }, + { MODULE_NOMINAL_VOLTAGE, 0x06, 0x01, 0x07, 0x00, false, false, ALL }, + { FTB_DIVIDEND, 0x09, 0x01, 0xF0, 0x04, false, false, ALL }, + { FTB_DIVISOR, 0x09, 0x01, 0x0F, 0x00, false, false, ALL }, + { MTB_DIVIDEND, 0x0a, 0x01, 0x00, 0x00, false, false, ALL }, + { MTB_DIVISOR, 0x0b, 0x01, 0x00, 0x00, false, false, ALL }, + { CAS_LATENCIES_SUPPORTED, 0x0f, 0x02, 0x7F, 0x00, true, false, ALL }, + { TWR_MIN, 0x11, 0x01, 0x00, 0x00, false, false, ALL }, + { TRRD_MIN, 0x13, 0x01, 0x00, 0x00, false, false, ALL }, + { TRFC_MIN, 0x19, 0x02, 0x00, 0x00, true, false, ALL }, + { TWTR_MIN, 0x1a, 0x01, 0x00, 0x00, false, false, ALL }, + { TRTP_MIN, 0x1b, 0x01, 0x00, 0x00, false, false, ALL }, + { DLL_OFF, 0x1e, 0x01, 0x80, 0x07, false, false, ALL }, + { RZQ_7, 0x1e, 0x01, 0x02, 0x01, false, false, ALL }, + { RZQ_6, 0x1e, 0x01, 0x01, 0x00, false, false, ALL }, + { PASR, 0x1f, 0x01, 0x80, 0x07, false, false, ALL }, + { ODTS, 0x1f, 0x01, 0x08, 0x03, false, false, ALL }, + { ASR, 0x1f, 0x01, 0x04, 0x02, false, false, ALL }, + { ETR_1X, 0x1f, 0x01, 0x02, 0x01, false, false, ALL }, + { ETR, 0x1f, 0x01, 0x01, 0x00, false, false, ALL }, + { MODULE_CRC, 0x7f, 0x02, 0x00, 0x00, true, false, ALL }, + { MODULE_REVISION_CODE, 0x93, 0x02, 0x00, 0x00, true, false, ALL }, // Module Specific fields supported on both DDR3 and DDR4 { MODSPEC_COM_NOM_HEIGHT_MAX, 0x3c, 0x01, 0x1f, 0x00, false, false, ALL }, { MODSPEC_COM_MAX_THICK_BACK, 0x3d, 0x01, 0xf0, 0x04, false, false, ALL }, |
