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* [MIPS] Don't emit R_(MICRO)MIPS_JALR relocations against data symbolsAlex Richardson2020-01-131-53/+90
| | | | | | | | | | | | | | The R_(MICRO)MIPS_JALR optimization only works when used against functions. Using the relocation against a data symbol (e.g. function pointer) will cause some linkers that don't ignore the hint in this case (e.g. LLD prior to commit 5bab291b7b) to generate a relative branch to the data symbol which crashes at run time. Before this patch, LLVM was erroneously emitting these relocations against local-dynamic TLS function pointers and global function pointers with internal visibility. Reviewers: atanasyan, jrtc27, vstefanovic Reviewed By: atanasyan Differential Revision: https://reviews.llvm.org/D72571
* [SelectionDAG] ComputeKnownBits - minimum leading/trailing zero bits in ↵Simon Pilgrim2020-01-131-42/+20
| | | | | | | | | | LSHR/SHL (PR44526) As detailed in https://blog.regehr.org/archives/1709 we don't make use of the known leading/trailing zeros for shifted values in cases where we don't know the shift amount value. This patch adds support to SelectionDAG::ComputeKnownBits to use KnownBits::countMinTrailingZeros and countMinLeadingZeros to set the minimum guaranteed leading/trailing known zero bits. Differential Revision: https://reviews.llvm.org/D72573
* [MIPS] Regenerate shl/lshr shift testsSimon Pilgrim2020-01-122-221/+221
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* MipsDelaySlotFiller: Update registers def-uses for BUNDLE instructionsAlex Richardson2020-01-091-0/+104
| | | | | | | | | | | | | | | Summary: In commit b91f239485fb7bb8d29be3e0b60660a2de7570a9 I updated the MipsDelaySlotFiller to skip BUNDLE instructions. However, in addition to not considering BUNDLE instructions for the delay slot, we also need to ensure that the register def-use information is updated. Not updating this information caused run-time crashes (when using the out-of-tree CHERI backend) since later definitions could be overwritten with earlier register values. Reviewers: atanasyan Reviewed By: atanasyan Differential Revision: https://reviews.llvm.org/D72254
* GlobalISel: Correct result type for G_FCMP in lowerFPTOUIMatt Arsenault2020-01-062-36/+81
| | | | | Using the final result type doesn't make any sense. Use the natural default boolean type for the select condition.
* [MIPS GlobalISel] Select bitreverse. RecommitPetar Avramovic2019-12-302-0/+399
| | | | | | | | | | | | | | | G_BITREVERSE is generated from llvm.bitreverse.<type> intrinsics, clang genrates these intrinsics from __builtin_bitreverse32 and __builtin_bitreverse64. Add lower and narrowscalar for G_BITREVERSE. Lower G_BITREVERSE on MIPS32. Recommit notes: Introduce temporary variables in order to make sure instructions get inserted into MachineFunction in same order regardless of compiler used to build llvm. Differential Revision: https://reviews.llvm.org/D71363
* Revert "[MIPS GlobalISel] Select bitreverse"Dmitri Gribenko2019-12-302-399/+0
| | | | | | This reverts commit dbc136e0fe7e14c64dcb78e72321bb41af60afa4. It broke buildbots: http://lab.llvm.org:8011/builders/clang-x86_64-debian-fast/builds/21066
* [MIPS GlobalISel] Select bitreversePetar Avramovic2019-12-302-0/+399
| | | | | | | | | | G_BITREVERSE is generated from llvm.bitreverse.<type> intrinsics, clang genrates these intrinsics from __builtin_bitreverse32 and __builtin_bitreverse64. Add lower and narrowscalar for G_BITREVERSE. Lower G_BITREVERSE on MIPS32. Differential Revision: https://reviews.llvm.org/D71363
* [MIPS GlobalISel] Select bswapPetar Avramovic2019-12-304-0/+227
| | | | | | | | | G_BSWAP is generated from llvm.bswap.<type> intrinsics, clang genrates these intrinsics from __builtin_bswap32 and __builtin_bswap64. Add lower and narrowscalar for G_BSWAP. Lower G_BSWAP on MIPS32, select G_BSWAP on MIPS32 revision 2 and later. Differential Revision: https://reviews.llvm.org/D71362
* Migrate function attribute "no-frame-pointer-elim"="false" to ↵Fangrui Song2019-12-2414-16/+16
| | | | "frame-pointer"="none" as cleanups after D56351
* Migrate function attribute "no-frame-pointer-elim-non-leaf" to ↵Fangrui Song2019-12-2413-35/+35
| | | | "frame-pointer"="non-leaf" as cleanups after D56351
* Migrate function attribute "no-frame-pointer-elim" to "frame-pointer"="all" ↵Fangrui Song2019-12-2429-45/+45
| | | | as cleanups after D56351
* Mips: Make test resistant to future changesMatt Arsenault2019-12-211-0/+2
| | | | | | | This seems to have been relying on extra spills being inserted in these blocks to increase the code size to trigger branch relaxation. This broke when these spills were avoided. Add some asm to pad the size of the blocks to make it not matter.
* [Mips] Add support for min/max/umin/umax atomicsMirko Brkusanin2019-12-123-1/+4833
| | | | | | | | In order to properly implement these atomic we need one register more than other binary atomics. It is used for storing result from comparing values in addition to the one that is used for actual result of operation. https://reviews.llvm.org/D71028
* Handle BUNDLE instructions in MipsAsmPrinterAlex Richardson2019-12-041-0/+11
| | | | | | | | | | | | | | | | | | | | | | Summary: In our CHERI fork we use BUNDLE instructions to ensure that a three-instruction sequence to generate a program-counter-relative value is emitted without reordering or insertions (since that would break the 32-bit offset computation). Currently MipsAsmPrinter asserts when it encounters a pseudo instruction. To handle BUNDLE we can simply skip the instruction which will then make EmitInstruction() process the contents of the bundle in order. Reviewers: atanasyan Reviewed By: atanasyan Subscribers: merge_guards_bot, sdardis, hiraditya, jrtc27, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70945
* MipsDelaySlotFiller: Don't move BUNDLE instructions into the delay slotAlex Richardson2019-12-041-0/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: In our CHERI fork we use BUNDLE instructions to ensure that a three-instruction sequence to generate a program-counter-relative value is emitted without reordering or insertions (since that would break the 32-bit offset computation). This sequence is created in MipsExpandPseudo and we use finalizeBundle() to create the BUNDLE instruction. However, the delay slot filler currently breaks this pattern since the BUNDLE will be removed and so all instructions are moved into the delay slot. Since the delay slot only executes the first instruction, this results in incorrect computations (and run-time crashes) if the branch is taken. The original test cases uses CHERI instructions, so for the test case here I simple filled a BUNDLE with a no-op DADDiu $sp_64, -16 and DADDiu $sp_64, 16. Reviewers: atanasyan Reviewed By: atanasyan Subscribers: merge_guards_bot, sdardis, hiraditya, jrtc27, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70944
* [GlobalISel]: Allow targets to override how to widen constants during ↵Aditya Nandakumar2019-12-035-11/+10
| | | | | | | | | | | | | | | legalization https://reviews.llvm.org/D70922 This adds a hook to allow targets to define exactly what extension operation should be performed for widening constants. This handles cases like widening i1 true which would end up becoming -1 which affects code quality during combines. Additionally, in order to stay consistent with how DAG is promoting constants, we now signextend for byte sized types and zero extend otherwise (by default). Targets can of course override this if necessary.
* [mips] Add a 'generic' Mips CPUMiloš Stojanović2019-11-211-0/+4
| | | | | | | Having a generic CPU removes a warning when creating a subtarget without the CPU being explicitly specified. Differential Revision: https://reviews.llvm.org/D70490
* [MIPS GlobalISel] Select andi, ori and xoriPetar Avramovic2019-11-1523-517/+579
| | | | | | | | | | | | | Introduce IntImmLeaf version of PatLeaf immZExt16 for 32-bit immediates. Change immZExt16 with imm32ZExt16 for andi, ori and xori. This keeps same behavior for SDAG and allows for GlobalISel selectImpl to select 'G_CONSTANT imm' + G_AND, G_OR, G_XOR into ANDi, ORi, XORi, respectively, when 32-bit imm satisfies imm32ZExt16 predicate: zero extending 16 low bits of imm is equal to imm. Large number of test changes comes from zero extending of small types which is transformed into 'and' with bitmask in legalizer. Differential Revision:https://reviews.llvm.org/D70185
* [MIPS GlobalISel] Select addiuPetar Avramovic2019-11-153-4/+110
| | | | | | | | | | Introduce IntImmLeaf version of PatLeaf immSExt16 for 32-bit immediates. Change immSExt16 with imm32SExt16 for addiu. This keeps same behavior for SDAG and allows for GlobalISel selectImpl to select 'G_CONSTANT imm' + G_ADD into ADDIu when 32-bit imm satisfies imm32SExt16 predicate: sign extending 16 low bits of imm is equal to imm. Differential Revision: https://reviews.llvm.org/D70184
* [Mips] Add rematerialization support for ldi.fmtMirko Brkusanin2019-11-131-0/+107
| | | | | | | Instruction ldi.fmt can be considered cheap enough to avoid spill and restore of value that it produces since it's loaded from immediate. Differential Revision: https://reviews.llvm.org/D69898
* [mips] Show an error if 64-bit target triple provided with 32-bit CPUSimon Atanasyan2019-11-131-0/+16
| | | | | | | | | When a 64-bit triple is used emit an error if the CPU only supports 32-bit code. Patch by Miloš Stojanović. Differential Revision: https://reviews.llvm.org/D70018
* [mips][test] Add Mips CPU tests. NFCSimon Atanasyan2019-11-131-0/+65
| | | | | | | | Adding tests check all available CPUs on Mips. Patch by Miloš Stojanović. Differential Revision: https://reviews.llvm.org/D70017
* [mips] Fix `getRegForInlineAsmConstraint` to do not crash on empty ConstraintSimon Atanasyan2019-11-061-0/+14
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* [globalisel] Rename G_GEP to G_PTR_ADDDaniel Sanders2019-11-0517-55/+55
| | | | | | | | | | | | | | | | Summary: G_GEP is rather poorly named. It's a simple pointer+scalar addition and doesn't support any of the complexities of getelementptr. I therefore propose that we rename it. There's a G_PTR_MASK so let's follow that convention and go with G_PTR_ADD Reviewers: volkan, aditya_nandakumar, bogner, rovka, arsenm Subscribers: sdardis, jvesely, wdng, nhaehnle, hiraditya, jrtc27, atanasyan, arphaman, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69734
* [utils] Reflow asm check generation to tolerate blank linesSimon Atanasyan2019-11-011-3/+16
| | | | | | | | | | | | | | This change introduces two fixes. The second fix allows to generate a test to check the first fix. - Output `CHECK-EMPTY` prefix for an empty line in ASM output. Before that fix `update_llc_test_checks.py` incorrectly emits `CHECK-NEXT: <space>` prefix. - Fix the `ASM_FUNCTION_MIPS_RE` regex to stop on a real function epilogue not on an inline assembler prologue and include inline assembler code into a test. Differential Revision: https://reviews.llvm.org/D47192
* [MIPS GlobalISel] Select MSA vector generic and builtin fsqrtPetar Avramovic2019-10-256-0/+303
| | | | | | | | | | | | | selectImpl is able to select G_FSQRT when we set bank for vector operands to fprb. Add detailed tests. Note: G_FSQRT is generated from llvm-ir intrinsics llvm.sqrt.*, and at the moment MIPS is not able to generate this intrinsic for vector type (some targets generate vector llvm.sqrt.* from calls to a builtin function). __builtin_msa_fsqrt_<format> will be transformed into G_FSQRT in legalizeIntrinsic and selected in the same way. Differential Revision: https://reviews.llvm.org/D69376
* [MIPS GlobalISel] Select MSA vector generic and builtin fabsPetar Avramovic2019-10-246-0/+302
| | | | | | | | | | | | | | selectImpl is able to select G_FABS when we set bank for vector operands to fprb. Add detailed tests. Note: G_FABS is generated from llvm-ir intrinsics llvm.fabs.*, and at the moment MIPS is not able to generate this intrinsic for vector type (some targets generate vector llvm.fabs.* from calls to a builtin function). We can handle fabs using __builtin_msa_fmax_a_<format> and passing same vector as both arguments. __builtin_msa_fmax_a_<format> will be directly selected into FMAX_A_<format> in legalizeIntrinsic. Differential Revision: https://reviews.llvm.org/D69346
* [MIPS GlobalISel] MSA vector generic and builtin fadd, fsub, fmul, fdivPetar Avramovic2019-10-246-0/+1291
| | | | | | | | | | | Select vector G_FADD, G_FSUB, G_FMUL and G_FDIV for MIPS32 with MSA. We have to set bank for vector operands to fprb and selectImpl will do the rest. __builtin_msa_fadd_<format>, __builtin_msa_fsub_<format>, __builtin_msa_fmul_<format> and __builtin_msa_fdiv_<format> will be transformed into G_FADD, G_FSUB, G_FMUL and G_FDIV in legalizeIntrinsic respectively and selected in the same way. Differential Revision: https://reviews.llvm.org/D69340
* [MIPS GlobalISel] MSA vector generic and builtin sdiv, srem, udiv, uremPetar Avramovic2019-10-246-0/+2532
| | | | | | | | | | | Select vector G_SDIV, G_SREM, G_UDIV and G_UREM for MIPS32 with MSA. We have to set bank for vector operands to fprb and selectImpl will do the rest. __builtin_msa_div_s_<format>, __builtin_msa_mod_s_<format>, __builtin_msa_div_u_<format> and __builtin_msa_mod_u_<format> will be transformed into G_SDIV, G_SREM, G_UDIV and G_UREM in legalizeIntrinsic respectively and selected in the same way. Differential Revision: https://reviews.llvm.org/D69333
* [Mips] Use appropriate private label prefix based on Mips ABIMirko Brkusanin2019-10-231-2/+2
| | | | | | | | | | MipsMCAsmInfo was using '$' prefix for Mips32 and '.L' for Mips64 regardless of -target-abi option. By passing MCTargetOptions to MCAsmInfo we can find out Mips ABI and pick appropriate prefix. Tags: #llvm, #clang, #lldb Differential Revision: https://reviews.llvm.org/D66795
* [MIPS GlobalISel] Select MSA vector generic and builtin mulPetar Avramovic2019-10-236-0/+651
| | | | | | | | | | Select vector G_MUL for MIPS32 with MSA. We have to set bank for vector operands to fprb and selectImpl will do the rest. Manual selection of G_MUL is now done for gprb only. __builtin_msa_mulv_<format> will be transformed into G_MUL in legalizeIntrinsic and selected in the same way. Differential Revision: https://reviews.llvm.org/D69310
* [MIPS GlobalISel] Select MSA vector generic and builtin subPetar Avramovic2019-10-236-0/+823
| | | | | | | | | | | Select vector G_SUB for MIPS32 with MSA. We have to set bank for vector operands to fprb and selectImpl will do the rest. __builtin_msa_subv_<format> will be transformed into G_SUB in legalizeIntrinsic and selected in the same way. __builtin_msa_subvi_<format> will be directly selected into SUBVI_<format> in legalizeIntrinsic. Differential Revision: https://reviews.llvm.org/D69306
* [MIParser] Set RegClassOrRegBank during instruction parsingPetar Avramovic2019-10-222-32/+20
| | | | | | | | | | | | | | MachineRegisterInfo::createGenericVirtualRegister sets RegClassOrRegBank to static_cast<RegisterBank *>(nullptr). MIParser on the other hand doesn't. When we attempt to constrain Register Class on such VReg, additional COPY is generated. This way we avoid COPY instructions showing in test that have MIR input while they are not present with llvm-ir input that was used to create given MIR for a -run-pass test. Differential Revision: https://reviews.llvm.org/D68946 llvm-svn: 375502
* [MIPS GlobalISel] Select MSA vector generic and builtin addPetar Avramovic2019-10-226-0/+831
| | | | | | | | | | | | | | | Select vector G_ADD for MIPS32 with MSA. We have to set bank for vector operands to fprb and selectImpl will do the rest. __builtin_msa_addv_<format> will be transformed into G_ADD in legalizeIntrinsic and selected in the same way. __builtin_msa_addvi_<format> will be directly selected into ADDVI_<format> in legalizeIntrinsic. MIR tests for it have unnecessary additional copies. Capture current state of tests with run-pass=legalizer with a test in test/CodeGen/MIR/Mips. Differential Revision: https://reviews.llvm.org/D68984 llvm-svn: 375501
* [MIPS GlobalISel] Add MSA registers to fprb. Select vector load, storePetar Avramovic2019-10-154-0/+530
| | | | | | | | | | | | | | | | | | Add vector MSA register classes to fprb, they are 128 bit wide. MSA instructions use the same registers for both integer and floating point operations. Therefore we only need to check for vector element size during legalization or instruction selection. Add helper function in MipsLegalizerInfo and switch to legalIf LegalizeRuleSet to keep legalization rules compact since they depend on MipsSubtarget and presence of MSA. fprb is assigned to all vector operands. Move selectLoadStoreOpCode to MipsInstructionSelector in order to reduce number of arguments. Differential Revision: https://reviews.llvm.org/D68867 llvm-svn: 374872
* [update_mir_test_checks] Handle MI flags properlyRoman Tereshin2019-10-141-2/+2
| | | | | | | | | | | | | | previously we would generate literal check lines w/ no reg-exps for vregs as MI flags (nsw, ninf, etc.) won't be recognized as a part of MI. Fixing that. Includes updating the MIR tests that suffered from the problem. Reviewed By: bogner Differential Revision: https://reviews.llvm.org/D68905 llvm-svn: 374829
* [Mips] Fix 374055Mirko Brkusanin2019-10-101-8/+14
| | | | | | | | EXPENSIVE_CHECKS build was failing on new test. This is fixed by marking $ra register as undef. Test now has -verify-machineinstrs to check for operand flags. llvm-svn: 374320
* [Mips] Emit proper ABI for _mcount callsMirko Brkusanin2019-10-081-0/+117
| | | | | | | | | | | When -pg option is present than a call to _mcount is inserted into every function. However since the proper ABI was not followed then the generated gmon.out did not give proper results. By inserting needed instructions before every _mcount we can fix this. Differential Revision: https://reviews.llvm.org/D68390 llvm-svn: 374055
* [Mips] Always save RA when disabling frame pointer eliminationSimon Atanasyan2019-10-076-158/+271
| | | | | | | | | | | | This ensures that frame-based unwinding will continue to work when calling a noreturn function; there is not much use having the caller's frame pointer saved if you don't also have the caller's program counter. Patch by James Clarke. Differential Revision: https://reviews.llvm.org/D68542 llvm-svn: 373907
* [mips] Use llvm-readobj `-A` flag in test cases. NFCSimon Atanasyan2019-10-031-1/+1
| | | | llvm-svn: 373589
* Add an operand to memory intrinsics to denote the "tail" marker.Amara Emerson2019-09-282-3/+3
| | | | | | | | | | | | | | We need to propagate this information from the IR in order to be able to safely do tail call optimizations on the intrinsics during legalization. Assuming it's safe to do tail call opt without checking for the marker isn't safe because the mem libcall may use allocas from the caller. This adds an extra immediate operand to the end of the intrinsics and fixes the legalizer to handle it. Differential Revision: https://reviews.llvm.org/D68151 llvm-svn: 373140
* [MIPS GlobalISel] Lower aggregate structure return argumentsPetar Avramovic2019-09-262-0/+246
| | | | | | | | | | | | | | Implement aggregate structure split to simpler types in splitToValueTypes. splitToValueTypes is used for return values. According to MipsABIInfo from clang/lib/CodeGen/TargetInfo.cpp, aggregate structure arguments for O32 always get simplified and thus will remain unsupported by the MIPS GlobalISel for the time being. For O32, aggregate structures can be encountered only for complex number returns e.g. 'complex float' or 'complex double' from <complex.h>. Differential Revision: https://reviews.llvm.org/D67963 llvm-svn: 372957
* [MIPS GlobalISel] VarArg argument lowering, select G_VASTART and vacopyPetar Avramovic2019-09-235-0/+508
| | | | | | | | | | | | | | | | CC_Mips doesn't accept vararg functions for O32, so we have to explicitly use CC_Mips_FixedArg. For lowerCall we now properly figure out whether callee function is vararg or not, this has no effect for O32 since we always use CC_Mips_FixedArg. For lower formal arguments we need to copy arguments in register to stack and save pointer to start for argument list into MipsMachineFunction object so that G_VASTART could use it during instruction select. For vacopy we need to copy content from one vreg to another, load and store are used for that purpose. Differential Revision: https://reviews.llvm.org/D67756 llvm-svn: 372555
* [MIPS] For vectors, select `add %x, C` as `sub %x, -C` if it results in ↵Roman Lebedev2019-09-181-8/+5
| | | | | | | | | | | | | | | | | | | | | | | inline immediate Summary: As discussed in https://reviews.llvm.org/D62341#1515637, for MIPS `add %x, -1` isn't optimal. Unlike X86 there are no fastpaths to matearialize such `-1`/`1` vector constants, and `sub %x, 1` results in better codegen, so undo canonicalization Reviewers: atanasyan, Petar.Avramovic, RKSimon Reviewed By: atanasyan Subscribers: sdardis, arichardson, hiraditya, jrtc27, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66805 llvm-svn: 372254
* [CodeGen][MIPS][NFC] Some standalone tests for D66805 "or vectors, select ↵Roman Lebedev2019-09-181-0/+67
| | | | | | `add %x, C` as `sub %x, -C` if it results in inline immediate" llvm-svn: 372253
* [mips] Pass "xgot" flag as a subtarget featureSimon Atanasyan2019-09-183-9/+13
| | | | | | | | | We need "xgot" flag in the MipsAsmParser to implement correct expansion of some pseudo instructions in case of using 32-bit GOT (XGOT). MipsAsmParser does not have reference to MipsSubtarget but has a reference to "feature bit set". llvm-svn: 372220
* [MIPS GlobalISel] Select indirect branchPetar Avramovic2019-09-124-0/+196
| | | | | | | | Select G_BRINDIRECT for MIPS32. Differential Revision: https://reviews.llvm.org/D67441 llvm-svn: 371730
* [MIPS GlobalISel] Lower G_DYN_STACKALLOCPetar Avramovic2019-09-122-0/+151
| | | | | | | | | | IRTranslator creates G_DYN_STACKALLOC instruction during expansion of alloca when argument that tells number of elements to allocate on stack is a virtual register. Use default lowering for MIPS32. Differential Revision: https://reviews.llvm.org/D67440 llvm-svn: 371728
* [MIPS GlobalISel] Select G_IMPLICIT_DEFPetar Avramovic2019-09-124-0/+412
| | | | | | | | | | G_IMPLICIT_DEF is used for both integer and floating point implicit-def. Handle G_IMPLICIT_DEF as ambiguous opcode in MipsRegisterBankInfo. Select G_IMPLICIT_DEF for MIPS32. Differential Revision: https://reviews.llvm.org/D67439 llvm-svn: 371727
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