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| author | Petar Avramovic <Petar.Avramovic@rt-rk.com> | 2019-11-15 11:41:25 +0100 |
|---|---|---|
| committer | Petar Avramovic <Petar.Avramovic@rt-rk.com> | 2019-11-15 11:41:25 +0100 |
| commit | 1f559353a7821769c94f03b00cc9c2f65f982d42 (patch) | |
| tree | 5235bf29f843e3eb9525f26d24ef54e842cf7993 /llvm/test/CodeGen/Mips | |
| parent | dda8e9554071164c85ac7b8b14bc5349703deaab (diff) | |
| download | bcm5719-llvm-1f559353a7821769c94f03b00cc9c2f65f982d42.tar.gz bcm5719-llvm-1f559353a7821769c94f03b00cc9c2f65f982d42.zip | |
[MIPS GlobalISel] Select andi, ori and xori
Introduce IntImmLeaf version of PatLeaf immZExt16 for 32-bit immediates.
Change immZExt16 with imm32ZExt16 for andi, ori and xori.
This keeps same behavior for SDAG and allows for GlobalISel selectImpl
to select 'G_CONSTANT imm' + G_AND, G_OR, G_XOR into ANDi, ORi, XORi,
respectively, when 32-bit imm satisfies imm32ZExt16 predicate: zero
extending 16 low bits of imm is equal to imm.
Large number of test changes comes from zero extending of small types
which is transformed into 'and' with bitmask in legalizer.
Differential Revision:https://reviews.llvm.org/D70185
Diffstat (limited to 'llvm/test/CodeGen/Mips')
23 files changed, 579 insertions, 517 deletions
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bitwise.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bitwise.mir index 5dd195f4789..32090c3ccf6 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bitwise.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bitwise.mir @@ -3,8 +3,14 @@ --- | define void @and_i32() {entry: ret void} + define void @and_imm() {entry: ret void} + define void @and_not_imm32ZExt16() {entry: ret void} define void @or_i32() {entry: ret void} + define void @or_imm() {entry: ret void} + define void @or_not_imm32ZExt16() {entry: ret void} define void @xor_i32() {entry: ret void} + define void @xor_imm() {entry: ret void} + define void @xor_not_imm32ZExt16() {entry: ret void} define void @shl(i32) {entry: ret void} define void @ashr(i32) {entry: ret void} define void @lshr(i32) {entry: ret void} @@ -38,6 +44,53 @@ body: | ... --- +name: and_imm +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0 + + ; MIPS32-LABEL: name: and_imm + ; MIPS32: liveins: $a0 + ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 + ; MIPS32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 255 + ; MIPS32: $v0 = COPY [[ANDi]] + ; MIPS32: RetRA implicit $v0 + %0:gprb(s32) = COPY $a0 + %1:gprb(s32) = G_CONSTANT i32 255 + %2:gprb(s32) = G_AND %0, %1 + $v0 = COPY %2(s32) + RetRA implicit $v0 + +... +--- +name: and_not_imm32ZExt16 +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0 + + ; MIPS32-LABEL: name: and_not_imm32ZExt16 + ; MIPS32: liveins: $a0 + ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 + ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65280 + ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ADDiu]] + ; MIPS32: $v0 = COPY [[AND]] + ; MIPS32: RetRA implicit $v0 + %0:gprb(s32) = COPY $a0 + %1:gprb(s32) = G_CONSTANT i32 -256 + %2:gprb(s32) = G_AND %0, %1 + $v0 = COPY %2(s32) + RetRA implicit $v0 + +... +--- name: or_i32 alignment: 4 legalized: true @@ -62,6 +115,53 @@ body: | ... --- +name: or_imm +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0 + + ; MIPS32-LABEL: name: or_imm + ; MIPS32: liveins: $a0 + ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 + ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[COPY]], 65535 + ; MIPS32: $v0 = COPY [[ORi]] + ; MIPS32: RetRA implicit $v0 + %0:gprb(s32) = COPY $a0 + %1:gprb(s32) = G_CONSTANT i32 65535 + %2:gprb(s32) = G_OR %0, %1 + $v0 = COPY %2(s32) + RetRA implicit $v0 + +... +--- +name: or_not_imm32ZExt16 +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0 + + ; MIPS32-LABEL: name: or_not_imm32ZExt16 + ; MIPS32: liveins: $a0 + ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 + ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 1 + ; MIPS32: [[OR:%[0-9]+]]:gpr32 = OR [[COPY]], [[LUi]] + ; MIPS32: $v0 = COPY [[OR]] + ; MIPS32: RetRA implicit $v0 + %0:gprb(s32) = COPY $a0 + %1:gprb(s32) = G_CONSTANT i32 65536 + %2:gprb(s32) = G_OR %0, %1 + $v0 = COPY %2(s32) + RetRA implicit $v0 + +... +--- name: xor_i32 alignment: 4 legalized: true @@ -86,6 +186,52 @@ body: | ... --- +name: xor_imm +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0 + + ; MIPS32-LABEL: name: xor_imm + ; MIPS32: liveins: $a0 + ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 + ; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[COPY]], 1 + ; MIPS32: $v0 = COPY [[XORi]] + ; MIPS32: RetRA implicit $v0 + %0:gprb(s32) = COPY $a0 + %1:gprb(s32) = G_CONSTANT i32 1 + %2:gprb(s32) = G_XOR %0, %1 + $v0 = COPY %2(s32) + RetRA implicit $v0 + +... +--- +name: xor_not_imm32ZExt16 +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0 + + ; MIPS32-LABEL: name: xor_not_imm32ZExt16 + ; MIPS32: liveins: $a0 + ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 + ; MIPS32: [[NOR:%[0-9]+]]:gpr32 = NOR [[COPY]], $zero + ; MIPS32: $v0 = COPY [[NOR]] + ; MIPS32: RetRA implicit $v0 + %0:gprb(s32) = COPY $a0 + %1:gprb(s32) = G_CONSTANT i32 -1 + %2:gprb(s32) = G_XOR %0, %1 + $v0 = COPY %2(s32) + RetRA implicit $v0 + +... +--- name: shl alignment: 4 legalized: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir index a3686f90cc9..dc927bae11f 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir @@ -71,9 +71,8 @@ body: | ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 ; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2 - ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1 - ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]] - ; MIPS32: BNE [[AND]], $zero, %bb.1, implicit-def $at + ; MIPS32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1 + ; MIPS32: BNE [[ANDi]], $zero, %bb.1, implicit-def $at ; MIPS32: J %bb.2, implicit-def $at ; MIPS32: bb.1.if.then: ; MIPS32: $v0 = COPY [[COPY1]] diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/jump_table_and_brjt.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/jump_table_and_brjt.mir index d9c6f0d8324..34a21c371a1 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/jump_table_and_brjt.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/jump_table_and_brjt.mir @@ -85,8 +85,8 @@ body: | ; MIPS32: [[ORi5:%[0-9]+]]:gpr32 = ORi $zero, 0 ; MIPS32: [[SUBu:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi5]] ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[ORi]], [[SUBu]] - ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi3]] - ; MIPS32: BNE [[AND]], $zero, %bb.6, implicit-def $at + ; MIPS32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[SLTu]], 1 + ; MIPS32: BNE [[ANDi]], $zero, %bb.6, implicit-def $at ; MIPS32: bb.1.entry: ; MIPS32: successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000) ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) %jump-table.0 @@ -113,9 +113,8 @@ body: | ; MIPS32: [[ORi6:%[0-9]+]]:gpr32 = ORi $zero, 8 ; MIPS32: [[SUBu1:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi6]] ; MIPS32: [[SLTu1:%[0-9]+]]:gpr32 = SLTu [[ORi1]], [[SUBu1]] - ; MIPS32: [[ORi7:%[0-9]+]]:gpr32 = ORi $zero, 1 - ; MIPS32: [[AND1:%[0-9]+]]:gpr32 = AND [[SLTu1]], [[ORi7]] - ; MIPS32: BNE [[AND1]], $zero, %bb.13, implicit-def $at + ; MIPS32: [[ANDi1:%[0-9]+]]:gpr32 = ANDi [[SLTu1]], 1 + ; MIPS32: BNE [[ANDi1]], $zero, %bb.13, implicit-def $at ; MIPS32: bb.8.sw.epilog: ; MIPS32: successors: %bb.9(0x20000000), %bb.10(0x20000000), %bb.11(0x20000000), %bb.12(0x20000000) ; MIPS32: [[LUi1:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) %jump-table.1 @@ -153,8 +152,8 @@ body: | ; MIPS32_PIC: [[ORi5:%[0-9]+]]:gpr32 = ORi $zero, 0 ; MIPS32_PIC: [[SUBu:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi5]] ; MIPS32_PIC: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[ORi]], [[SUBu]] - ; MIPS32_PIC: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi3]] - ; MIPS32_PIC: BNE [[AND]], $zero, %bb.6, implicit-def $at + ; MIPS32_PIC: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[SLTu]], 1 + ; MIPS32_PIC: BNE [[ANDi]], $zero, %bb.6, implicit-def $at ; MIPS32_PIC: bb.1.entry: ; MIPS32_PIC: successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000) ; MIPS32_PIC: [[LW:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-got) %jump-table.0 :: (load 4 from got) @@ -182,9 +181,8 @@ body: | ; MIPS32_PIC: [[ORi6:%[0-9]+]]:gpr32 = ORi $zero, 8 ; MIPS32_PIC: [[SUBu1:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi6]] ; MIPS32_PIC: [[SLTu1:%[0-9]+]]:gpr32 = SLTu [[ORi1]], [[SUBu1]] - ; MIPS32_PIC: [[ORi7:%[0-9]+]]:gpr32 = ORi $zero, 1 - ; MIPS32_PIC: [[AND1:%[0-9]+]]:gpr32 = AND [[SLTu1]], [[ORi7]] - ; MIPS32_PIC: BNE [[AND1]], $zero, %bb.13, implicit-def $at + ; MIPS32_PIC: [[ANDi1:%[0-9]+]]:gpr32 = ANDi [[SLTu1]], 1 + ; MIPS32_PIC: BNE [[ANDi1]], $zero, %bb.13, implicit-def $at ; MIPS32_PIC: bb.8.sw.epilog: ; MIPS32_PIC: successors: %bb.9(0x20000000), %bb.10(0x20000000), %bb.11(0x20000000), %bb.12(0x20000000) ; MIPS32_PIC: [[LW2:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-got) %jump-table.1 :: (load 4 from got) diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir index 41bd42d691a..a77f60f6862 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir @@ -50,9 +50,8 @@ body: | ; MIPS32: [[PseudoMULTu:%[0-9]+]]:acc64 = PseudoMULTu [[COPY]], [[COPY1]] ; MIPS32: [[PseudoMFHI:%[0-9]+]]:gpr32 = PseudoMFHI [[PseudoMULTu]] ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu $zero, [[PseudoMFHI]] - ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1 - ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi]] - ; MIPS32: SB [[AND]], [[COPY3]], 0 :: (store 1 into %ir.pcarry_flag) + ; MIPS32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[SLTu]], 1 + ; MIPS32: SB [[ANDi]], [[COPY3]], 0 :: (store 1 into %ir.pcarry_flag) ; MIPS32: SW [[MUL]], [[COPY2]], 0 :: (store 4 into %ir.pmul) ; MIPS32: RetRA %0:gprb(s32) = COPY $a0 diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir index e907f79824e..07a03d1c422 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir @@ -78,9 +78,8 @@ body: | ; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 ; MIPS32FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 ; MIPS32FP32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2 - ; MIPS32FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1 - ; MIPS32FP32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]] - ; MIPS32FP32: BNE [[AND]], $zero, %bb.1, implicit-def $at + ; MIPS32FP32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1 + ; MIPS32FP32: BNE [[ANDi]], $zero, %bb.1, implicit-def $at ; MIPS32FP32: J %bb.2, implicit-def $at ; MIPS32FP32: bb.1.cond.true: ; MIPS32FP32: successors: %bb.3(0x80000000) @@ -98,9 +97,8 @@ body: | ; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 ; MIPS32FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 ; MIPS32FP64: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2 - ; MIPS32FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1 - ; MIPS32FP64: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]] - ; MIPS32FP64: BNE [[AND]], $zero, %bb.1, implicit-def $at + ; MIPS32FP64: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1 + ; MIPS32FP64: BNE [[ANDi]], $zero, %bb.1, implicit-def $at ; MIPS32FP64: J %bb.2, implicit-def $at ; MIPS32FP64: bb.1.cond.true: ; MIPS32FP64: successors: %bb.3(0x80000000) @@ -155,9 +153,8 @@ body: | ; MIPS32FP32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8) ; MIPS32FP32: [[ADDiu1:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.1, 0 ; MIPS32FP32: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDiu1]], 0 :: (load 4 from %fixed-stack.1) - ; MIPS32FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1 - ; MIPS32FP32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]] - ; MIPS32FP32: BNE [[AND]], $zero, %bb.1, implicit-def $at + ; MIPS32FP32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1 + ; MIPS32FP32: BNE [[ANDi]], $zero, %bb.1, implicit-def $at ; MIPS32FP32: J %bb.2, implicit-def $at ; MIPS32FP32: bb.1.cond.true: ; MIPS32FP32: successors: %bb.3(0x80000000) @@ -181,9 +178,8 @@ body: | ; MIPS32FP64: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8) ; MIPS32FP64: [[ADDiu1:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.1, 0 ; MIPS32FP64: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDiu1]], 0 :: (load 4 from %fixed-stack.1) - ; MIPS32FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1 - ; MIPS32FP64: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]] - ; MIPS32FP64: BNE [[AND]], $zero, %bb.1, implicit-def $at + ; MIPS32FP64: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1 + ; MIPS32FP64: BNE [[ANDi]], $zero, %bb.1, implicit-def $at ; MIPS32FP64: J %bb.2, implicit-def $at ; MIPS32FP64: bb.1.cond.true: ; MIPS32FP64: successors: %bb.3(0x80000000) @@ -239,9 +235,8 @@ body: | ; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 ; MIPS32FP32: [[MTC1_:%[0-9]+]]:fgr32 = MTC1 $a1 ; MIPS32FP32: [[MTC1_1:%[0-9]+]]:fgr32 = MTC1 $a2 - ; MIPS32FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1 - ; MIPS32FP32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]] - ; MIPS32FP32: BNE [[AND]], $zero, %bb.1, implicit-def $at + ; MIPS32FP32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1 + ; MIPS32FP32: BNE [[ANDi]], $zero, %bb.1, implicit-def $at ; MIPS32FP32: J %bb.2, implicit-def $at ; MIPS32FP32: bb.1.cond.true: ; MIPS32FP32: successors: %bb.3(0x80000000) @@ -259,9 +254,8 @@ body: | ; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 ; MIPS32FP64: [[MTC1_:%[0-9]+]]:fgr32 = MTC1 $a1 ; MIPS32FP64: [[MTC1_1:%[0-9]+]]:fgr32 = MTC1 $a2 - ; MIPS32FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1 - ; MIPS32FP64: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]] - ; MIPS32FP64: BNE [[AND]], $zero, %bb.1, implicit-def $at + ; MIPS32FP64: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1 + ; MIPS32FP64: BNE [[ANDi]], $zero, %bb.1, implicit-def $at ; MIPS32FP64: J %bb.2, implicit-def $at ; MIPS32FP64: bb.1.cond.true: ; MIPS32FP64: successors: %bb.3(0x80000000) @@ -312,9 +306,8 @@ body: | ; MIPS32FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7 ; MIPS32FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0 ; MIPS32FP32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8) - ; MIPS32FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1 - ; MIPS32FP32: [[AND:%[0-9]+]]:gpr32 = AND [[LW]], [[ORi]] - ; MIPS32FP32: BNE [[AND]], $zero, %bb.1, implicit-def $at + ; MIPS32FP32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[LW]], 1 + ; MIPS32FP32: BNE [[ANDi]], $zero, %bb.1, implicit-def $at ; MIPS32FP32: J %bb.2, implicit-def $at ; MIPS32FP32: bb.1.cond.true: ; MIPS32FP32: successors: %bb.3(0x80000000) @@ -333,9 +326,8 @@ body: | ; MIPS32FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7 ; MIPS32FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0 ; MIPS32FP64: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8) - ; MIPS32FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1 - ; MIPS32FP64: [[AND:%[0-9]+]]:gpr32 = AND [[LW]], [[ORi]] - ; MIPS32FP64: BNE [[AND]], $zero, %bb.1, implicit-def $at + ; MIPS32FP64: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[LW]], 1 + ; MIPS32FP64: BNE [[ANDi]], $zero, %bb.1, implicit-def $at ; MIPS32FP64: J %bb.2, implicit-def $at ; MIPS32FP64: bb.1.cond.true: ; MIPS32FP64: successors: %bb.3(0x80000000) diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir index 904def3a69f..84bd98c9b52 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir @@ -24,9 +24,8 @@ body: | ; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 ; MIPS32FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 ; MIPS32FP32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2 - ; MIPS32FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1 - ; MIPS32FP32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]] - ; MIPS32FP32: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[AND]], [[COPY2]] + ; MIPS32FP32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1 + ; MIPS32FP32: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[ANDi]], [[COPY2]] ; MIPS32FP32: $v0 = COPY [[MOVN_I_I]] ; MIPS32FP32: RetRA implicit $v0 ; MIPS32FP64-LABEL: name: select_i32 @@ -34,9 +33,8 @@ body: | ; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 ; MIPS32FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 ; MIPS32FP64: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2 - ; MIPS32FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1 - ; MIPS32FP64: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]] - ; MIPS32FP64: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[AND]], [[COPY2]] + ; MIPS32FP64: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1 + ; MIPS32FP64: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[ANDi]], [[COPY2]] ; MIPS32FP64: $v0 = COPY [[MOVN_I_I]] ; MIPS32FP64: RetRA implicit $v0 %3:gprb(s32) = COPY $a0 @@ -65,9 +63,8 @@ body: | ; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 ; MIPS32FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 ; MIPS32FP32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2 - ; MIPS32FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1 - ; MIPS32FP32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]] - ; MIPS32FP32: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[AND]], [[COPY2]] + ; MIPS32FP32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1 + ; MIPS32FP32: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[ANDi]], [[COPY2]] ; MIPS32FP32: $v0 = COPY [[MOVN_I_I]] ; MIPS32FP32: RetRA implicit $v0 ; MIPS32FP64-LABEL: name: select_ptr @@ -75,9 +72,8 @@ body: | ; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 ; MIPS32FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 ; MIPS32FP64: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2 - ; MIPS32FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1 - ; MIPS32FP64: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]] - ; MIPS32FP64: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[AND]], [[COPY2]] + ; MIPS32FP64: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1 + ; MIPS32FP64: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[ANDi]], [[COPY2]] ; MIPS32FP64: $v0 = COPY [[MOVN_I_I]] ; MIPS32FP64: RetRA implicit $v0 %3:gprb(s32) = COPY $a0 @@ -106,9 +102,8 @@ body: | ; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 ; MIPS32FP32: [[MTC1_:%[0-9]+]]:fgr32 = MTC1 $a1 ; MIPS32FP32: [[MTC1_1:%[0-9]+]]:fgr32 = MTC1 $a2 - ; MIPS32FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1 - ; MIPS32FP32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]] - ; MIPS32FP32: [[MOVN_I_S:%[0-9]+]]:fgr32 = MOVN_I_S [[MTC1_]], [[AND]], [[MTC1_1]] + ; MIPS32FP32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1 + ; MIPS32FP32: [[MOVN_I_S:%[0-9]+]]:fgr32 = MOVN_I_S [[MTC1_]], [[ANDi]], [[MTC1_1]] ; MIPS32FP32: $f0 = COPY [[MOVN_I_S]] ; MIPS32FP32: RetRA implicit $f0 ; MIPS32FP64-LABEL: name: select_float @@ -116,9 +111,8 @@ body: | ; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 ; MIPS32FP64: [[MTC1_:%[0-9]+]]:fgr32 = MTC1 $a1 ; MIPS32FP64: [[MTC1_1:%[0-9]+]]:fgr32 = MTC1 $a2 - ; MIPS32FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1 - ; MIPS32FP64: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]] - ; MIPS32FP64: [[MOVN_I_S:%[0-9]+]]:fgr32 = MOVN_I_S [[MTC1_]], [[AND]], [[MTC1_1]] + ; MIPS32FP64: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1 + ; MIPS32FP64: [[MOVN_I_S:%[0-9]+]]:fgr32 = MOVN_I_S [[MTC1_]], [[ANDi]], [[MTC1_1]] ; MIPS32FP64: $f0 = COPY [[MOVN_I_S]] ; MIPS32FP64: RetRA implicit $f0 %3:gprb(s32) = COPY $a0 @@ -150,9 +144,8 @@ body: | ; MIPS32FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7 ; MIPS32FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0 ; MIPS32FP32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8) - ; MIPS32FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1 - ; MIPS32FP32: [[AND:%[0-9]+]]:gpr32 = AND [[LW]], [[ORi]] - ; MIPS32FP32: [[MOVN_I_D32_:%[0-9]+]]:afgr64 = MOVN_I_D32 [[COPY]], [[AND]], [[COPY1]] + ; MIPS32FP32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[LW]], 1 + ; MIPS32FP32: [[MOVN_I_D32_:%[0-9]+]]:afgr64 = MOVN_I_D32 [[COPY]], [[ANDi]], [[COPY1]] ; MIPS32FP32: $d0 = COPY [[MOVN_I_D32_]] ; MIPS32FP32: RetRA implicit $d0 ; MIPS32FP64-LABEL: name: select_double @@ -161,9 +154,8 @@ body: | ; MIPS32FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7 ; MIPS32FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0 ; MIPS32FP64: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8) - ; MIPS32FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1 - ; MIPS32FP64: [[AND:%[0-9]+]]:gpr32 = AND [[LW]], [[ORi]] - ; MIPS32FP64: [[MOVN_I_D64_:%[0-9]+]]:fgr64 = MOVN_I_D64 [[COPY]], [[AND]], [[COPY1]] + ; MIPS32FP64: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[LW]], 1 + ; MIPS32FP64: [[MOVN_I_D64_:%[0-9]+]]:fgr64 = MOVN_I_D64 [[COPY]], [[ANDi]], [[COPY1]] ; MIPS32FP64: $d0 = COPY [[MOVN_I_D64_]] ; MIPS32FP64: RetRA implicit $d0 %0:fprb(s64) = COPY $d6 diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll index 31287f0d547..0b217b83747 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll @@ -28,8 +28,7 @@ define zeroext i8 @add_i8_zext(i8 zeroext %a, i8 zeroext %b) { ; MIPS32-LABEL: add_i8_zext: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: addu $1, $5, $4 -; MIPS32-NEXT: ori $2, $zero, 255 -; MIPS32-NEXT: and $2, $1, $2 +; MIPS32-NEXT: andi $2, $1, 255 ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop entry: @@ -65,8 +64,7 @@ define zeroext i16 @add_i16_zext(i16 zeroext %a, i16 zeroext %b) { ; MIPS32-LABEL: add_i16_zext: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: addu $1, $5, $4 -; MIPS32-NEXT: ori $2, $zero, 65535 -; MIPS32-NEXT: and $2, $1, $2 +; MIPS32-NEXT: andi $2, $1, 65535 ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop entry: @@ -91,8 +89,7 @@ define i64 @add_i64(i64 %a, i64 %b) { ; MIPS32-NEXT: addu $1, $6, $4 ; MIPS32-NEXT: sltu $2, $1, $4 ; MIPS32-NEXT: addu $3, $7, $5 -; MIPS32-NEXT: ori $4, $zero, 1 -; MIPS32-NEXT: and $2, $2, $4 +; MIPS32-NEXT: andi $2, $2, 1 ; MIPS32-NEXT: addu $3, $3, $2 ; MIPS32-NEXT: move $2, $1 ; MIPS32-NEXT: jr $ra @@ -118,16 +115,15 @@ define i128 @add_i128(i128 %a, i128 %b) { ; MIPS32-NEXT: addu $1, $1, $4 ; MIPS32-NEXT: sltu $4, $1, $4 ; MIPS32-NEXT: addu $5, $2, $5 -; MIPS32-NEXT: ori $9, $zero, 1 -; MIPS32-NEXT: and $4, $4, $9 +; MIPS32-NEXT: andi $4, $4, 1 ; MIPS32-NEXT: addu $4, $5, $4 ; MIPS32-NEXT: sltu $2, $4, $2 ; MIPS32-NEXT: addu $5, $3, $6 -; MIPS32-NEXT: and $2, $2, $9 +; MIPS32-NEXT: andi $2, $2, 1 ; MIPS32-NEXT: addu $2, $5, $2 ; MIPS32-NEXT: sltu $3, $2, $3 ; MIPS32-NEXT: addu $5, $8, $7 -; MIPS32-NEXT: and $3, $3, $9 +; MIPS32-NEXT: andi $3, $3, 1 ; MIPS32-NEXT: addu $5, $5, $3 ; MIPS32-NEXT: sw $2, 4($sp) # 4-byte Folded Spill ; MIPS32-NEXT: move $2, $1 @@ -181,8 +177,7 @@ define void @uadd_with_overflow(i32 %lhs, i32 %rhs, i32* %padd, i1* %pcarry_flag ; MIPS32: # %bb.0: ; MIPS32-NEXT: addu $1, $4, $5 ; MIPS32-NEXT: sltu $2, $1, $5 -; MIPS32-NEXT: ori $3, $zero, 1 -; MIPS32-NEXT: and $2, $2, $3 +; MIPS32-NEXT: andi $2, $2, 1 ; MIPS32-NEXT: sb $2, 0($7) ; MIPS32-NEXT: sw $1, 0($6) ; MIPS32-NEXT: jr $ra diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll index 2e918adb125..4022efcafb6 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll @@ -57,6 +57,29 @@ entry: ret i64 %and } +define i32 @and_imm(i32 %a) { +; MIPS32-LABEL: and_imm: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: andi $2, $4, 255 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %and = and i32 %a, 255 + ret i32 %and +} + +define i32 @and_not_imm32ZExt16(i32 %a) { +; MIPS32-LABEL: and_not_imm32ZExt16: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $1, $zero, 65280 +; MIPS32-NEXT: and $2, $4, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %and = and i32 %a, -256 + ret i32 %and +} + define i1 @or_i1(i1 %a, i1 %b) { ; MIPS32-LABEL: or_i1: ; MIPS32: # %bb.0: # %entry @@ -113,6 +136,29 @@ entry: ret i64 %or } +define i32 @or_imm(i32 %a) { +; MIPS32-LABEL: or_imm: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: ori $2, $4, 65535 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %or = or i32 %a, 65535 + ret i32 %or +} + +define i32 @or_not_imm32ZExt16(i32 %a) { +; MIPS32-LABEL: or_not_imm32ZExt16: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: lui $1, 1 +; MIPS32-NEXT: or $2, $4, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %or = or i32 %a, 65536 + ret i32 %or +} + define i1 @xor_i1(i1 %a, i1 %b) { ; MIPS32-LABEL: xor_i1: ; MIPS32: # %bb.0: # %entry @@ -169,6 +215,28 @@ entry: ret i64 %xor } +define i32 @xor_imm(i32 %a) { +; MIPS32-LABEL: xor_imm: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: xori $2, $4, 1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %xor = xor i32 %a, 1 + ret i32 %xor +} + +define i32 @xor_not_imm32ZExt16(i32 %a) { +; MIPS32-LABEL: xor_not_imm32ZExt16: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: not $2, $4 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %xor = xor i32 %a, -1 + ret i32 %xor +} + define i32 @shl(i32 %a) { ; MIPS32-LABEL: shl: ; MIPS32: # %bb.0: # %entry @@ -239,8 +307,7 @@ define i16 @shl_i16(i16 %a) { ; MIPS32-LABEL: shl_i16: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: ori $1, $zero, 2 -; MIPS32-NEXT: ori $2, $zero, 65535 -; MIPS32-NEXT: and $1, $1, $2 +; MIPS32-NEXT: andi $1, $1, 65535 ; MIPS32-NEXT: sllv $2, $4, $1 ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop @@ -253,8 +320,7 @@ define i8 @ashr_i8(i8 %a) { ; MIPS32-LABEL: ashr_i8: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: ori $1, $zero, 2 -; MIPS32-NEXT: ori $2, $zero, 255 -; MIPS32-NEXT: and $1, $1, $2 +; MIPS32-NEXT: andi $1, $1, 255 ; MIPS32-NEXT: sll $2, $4, 24 ; MIPS32-NEXT: sra $2, $2, 24 ; MIPS32-NEXT: srav $2, $2, $1 @@ -269,9 +335,8 @@ define i16 @lshr_i16(i16 %a) { ; MIPS32-LABEL: lshr_i16: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: ori $1, $zero, 2 -; MIPS32-NEXT: ori $2, $zero, 65535 -; MIPS32-NEXT: and $1, $1, $2 -; MIPS32-NEXT: and $2, $4, $2 +; MIPS32-NEXT: andi $1, $1, 65535 +; MIPS32-NEXT: andi $2, $4, 65535 ; MIPS32-NEXT: srlv $2, $2, $1 ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop @@ -296,12 +361,11 @@ define i64 @shl_i64(i64 %a, i64 %b) { ; MIPS32-NEXT: sllv $6, $5, $6 ; MIPS32-NEXT: or $3, $3, $6 ; MIPS32-NEXT: sllv $2, $4, $2 -; MIPS32-NEXT: ori $4, $zero, 1 -; MIPS32-NEXT: and $6, $1, $4 -; MIPS32-NEXT: movn $8, $10, $6 -; MIPS32-NEXT: and $1, $1, $4 +; MIPS32-NEXT: andi $4, $1, 1 +; MIPS32-NEXT: movn $8, $10, $4 +; MIPS32-NEXT: andi $1, $1, 1 ; MIPS32-NEXT: movn $2, $3, $1 -; MIPS32-NEXT: and $1, $9, $4 +; MIPS32-NEXT: andi $1, $9, 1 ; MIPS32-NEXT: movn $2, $5, $1 ; MIPS32-NEXT: sw $2, 4($sp) # 4-byte Folded Spill ; MIPS32-NEXT: move $2, $8 @@ -328,12 +392,11 @@ define i64 @ashl_i64(i64 %a, i64 %b) { ; MIPS32-NEXT: or $3, $6, $3 ; MIPS32-NEXT: sra $6, $5, 31 ; MIPS32-NEXT: srav $2, $5, $2 -; MIPS32-NEXT: ori $5, $zero, 1 -; MIPS32-NEXT: and $10, $1, $5 -; MIPS32-NEXT: movn $2, $3, $10 -; MIPS32-NEXT: and $3, $8, $5 +; MIPS32-NEXT: andi $5, $1, 1 +; MIPS32-NEXT: movn $2, $3, $5 +; MIPS32-NEXT: andi $3, $8, 1 ; MIPS32-NEXT: movn $2, $4, $3 -; MIPS32-NEXT: and $1, $1, $5 +; MIPS32-NEXT: andi $1, $1, 1 ; MIPS32-NEXT: movn $6, $9, $1 ; MIPS32-NEXT: move $3, $6 ; MIPS32-NEXT: jr $ra @@ -357,12 +420,11 @@ define i64 @lshr_i64(i64 %a, i64 %b) { ; MIPS32-NEXT: sllv $3, $5, $3 ; MIPS32-NEXT: or $3, $6, $3 ; MIPS32-NEXT: srlv $2, $5, $2 -; MIPS32-NEXT: ori $5, $zero, 1 -; MIPS32-NEXT: and $6, $1, $5 -; MIPS32-NEXT: movn $2, $3, $6 -; MIPS32-NEXT: and $3, $9, $5 +; MIPS32-NEXT: andi $5, $1, 1 +; MIPS32-NEXT: movn $2, $3, $5 +; MIPS32-NEXT: andi $3, $9, 1 ; MIPS32-NEXT: movn $2, $4, $3 -; MIPS32-NEXT: and $1, $1, $5 +; MIPS32-NEXT: andi $1, $1, 1 ; MIPS32-NEXT: movn $8, $10, $1 ; MIPS32-NEXT: move $3, $8 ; MIPS32-NEXT: jr $ra diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/branch.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/branch.ll index 8e5cce8e787..4600142cb9b 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/branch.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/branch.ll @@ -30,8 +30,7 @@ define i32 @Conditional_branch(i1 %cond, i32 %a, i32 %b) { ; MIPS32: # %bb.0: ; MIPS32-NEXT: addiu $sp, $sp, -8 ; MIPS32-NEXT: .cfi_def_cfa_offset 8 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: and $1, $4, $1 +; MIPS32-NEXT: andi $1, $4, 1 ; MIPS32-NEXT: sw $5, 4($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $6, 0($sp) # 4-byte Folded Spill ; MIPS32-NEXT: bnez $1, $BB1_2 diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/constants.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/constants.ll index 579a04cb9e3..bdafe26491a 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/constants.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/constants.ll @@ -50,8 +50,7 @@ define zeroext i16 @unsigned_i16() { ; MIPS32-LABEL: unsigned_i16: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: addiu $1, $zero, 32768 -; MIPS32-NEXT: ori $2, $zero, 65535 -; MIPS32-NEXT: and $2, $1, $2 +; MIPS32-NEXT: andi $2, $1, 65535 ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop entry: @@ -62,8 +61,7 @@ define zeroext i8 @unsigned_i8() { ; MIPS32-LABEL: unsigned_i8: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: addiu $1, $zero, 65408 -; MIPS32-NEXT: ori $2, $zero, 255 -; MIPS32-NEXT: and $2, $1, $2 +; MIPS32-NEXT: andi $2, $1, 255 ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop entry: @@ -74,8 +72,7 @@ define zeroext i1 @i1_true() { ; MIPS32-LABEL: i1_true: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: addiu $1, $zero, 65535 -; MIPS32-NEXT: ori $2, $zero, 1 -; MIPS32-NEXT: and $2, $1, $2 +; MIPS32-NEXT: andi $2, $1, 1 ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop entry: @@ -86,8 +83,7 @@ define zeroext i1 @i1_false() { ; MIPS32-LABEL: i1_false: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: ori $1, $zero, 0 -; MIPS32-NEXT: ori $2, $zero, 1 -; MIPS32-NEXT: and $2, $1, $2 +; MIPS32-NEXT: andi $2, $1, 1 ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop entry: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fptosi_and_fptoui.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fptosi_and_fptoui.ll index 0234c7feadf..8203f298ee6 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fptosi_and_fptoui.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fptosi_and_fptoui.ll @@ -175,8 +175,7 @@ define zeroext i16 @f32tou16(float %a) { ; MIPS32-NEXT: c.ult.s $f12, $f0 ; MIPS32-NEXT: movf $3, $zero, $fcc0 ; MIPS32-NEXT: movn $2, $1, $3 -; MIPS32-NEXT: ori $1, $zero, 65535 -; MIPS32-NEXT: and $2, $2, $1 +; MIPS32-NEXT: andi $2, $2, 65535 ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop entry: @@ -200,8 +199,7 @@ define zeroext i8 @f32tou8(float %a) { ; MIPS32-NEXT: c.ult.s $f12, $f0 ; MIPS32-NEXT: movf $3, $zero, $fcc0 ; MIPS32-NEXT: movn $2, $1, $3 -; MIPS32-NEXT: ori $1, $zero, 255 -; MIPS32-NEXT: and $2, $2, $1 +; MIPS32-NEXT: andi $2, $2, 255 ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop entry: @@ -290,8 +288,7 @@ define zeroext i16 @f64tou16(double %a) { ; FP32-NEXT: c.ult.d $f12, $f2 ; FP32-NEXT: movf $3, $zero, $fcc0 ; FP32-NEXT: movn $2, $1, $3 -; FP32-NEXT: ori $1, $zero, 65535 -; FP32-NEXT: and $2, $2, $1 +; FP32-NEXT: andi $2, $2, 65535 ; FP32-NEXT: jr $ra ; FP32-NEXT: nop ; @@ -312,8 +309,7 @@ define zeroext i16 @f64tou16(double %a) { ; FP64-NEXT: c.ult.d $f12, $f1 ; FP64-NEXT: movf $3, $zero, $fcc0 ; FP64-NEXT: movn $2, $1, $3 -; FP64-NEXT: ori $1, $zero, 65535 -; FP64-NEXT: and $2, $2, $1 +; FP64-NEXT: andi $2, $2, 65535 ; FP64-NEXT: jr $ra ; FP64-NEXT: nop entry: @@ -339,8 +335,7 @@ define zeroext i8 @f64tou8(double %a) { ; FP32-NEXT: c.ult.d $f12, $f2 ; FP32-NEXT: movf $3, $zero, $fcc0 ; FP32-NEXT: movn $2, $1, $3 -; FP32-NEXT: ori $1, $zero, 255 -; FP32-NEXT: and $2, $2, $1 +; FP32-NEXT: andi $2, $2, 255 ; FP32-NEXT: jr $ra ; FP32-NEXT: nop ; @@ -361,8 +356,7 @@ define zeroext i8 @f64tou8(double %a) { ; FP64-NEXT: c.ult.d $f12, $f1 ; FP64-NEXT: movf $3, $zero, $fcc0 ; FP64-NEXT: movn $2, $1, $3 -; FP64-NEXT: ori $1, $zero, 255 -; FP64-NEXT: and $2, $2, $1 +; FP64-NEXT: andi $2, $2, 255 ; FP64-NEXT: jr $ra ; FP64-NEXT: nop entry: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll index b336e957c50..7eb952b47c5 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll @@ -132,10 +132,9 @@ entry: define i1 @ult_i8(i8 %a, i8 %b) { ; MIPS32-LABEL: ult_i8: ; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: ori $1, $zero, 255 -; MIPS32-NEXT: and $2, $4, $1 -; MIPS32-NEXT: and $1, $5, $1 -; MIPS32-NEXT: sltu $2, $2, $1 +; MIPS32-NEXT: andi $1, $4, 255 +; MIPS32-NEXT: andi $2, $5, 255 +; MIPS32-NEXT: sltu $2, $1, $2 ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop entry: @@ -193,8 +192,7 @@ define i1 @sgt_i64(i64 %a, i64 %b) { ; MIPS32-NEXT: xor $2, $5, $7 ; MIPS32-NEXT: sltiu $2, $2, 1 ; MIPS32-NEXT: sltu $3, $6, $4 -; MIPS32-NEXT: ori $4, $zero, 1 -; MIPS32-NEXT: and $2, $2, $4 +; MIPS32-NEXT: andi $2, $2, 1 ; MIPS32-NEXT: movn $1, $3, $2 ; MIPS32-NEXT: move $2, $1 ; MIPS32-NEXT: jr $ra @@ -213,8 +211,7 @@ define i1 @sge_i64(i64 %a, i64 %b) { ; MIPS32-NEXT: sltiu $2, $2, 1 ; MIPS32-NEXT: sltu $3, $4, $6 ; MIPS32-NEXT: xori $3, $3, 1 -; MIPS32-NEXT: ori $4, $zero, 1 -; MIPS32-NEXT: and $2, $2, $4 +; MIPS32-NEXT: andi $2, $2, 1 ; MIPS32-NEXT: movn $1, $3, $2 ; MIPS32-NEXT: move $2, $1 ; MIPS32-NEXT: jr $ra @@ -231,8 +228,7 @@ define i1 @slt_i64(i64 %a, i64 %b) { ; MIPS32-NEXT: xor $2, $5, $7 ; MIPS32-NEXT: sltiu $2, $2, 1 ; MIPS32-NEXT: sltu $3, $4, $6 -; MIPS32-NEXT: ori $4, $zero, 1 -; MIPS32-NEXT: and $2, $2, $4 +; MIPS32-NEXT: andi $2, $2, 1 ; MIPS32-NEXT: movn $1, $3, $2 ; MIPS32-NEXT: move $2, $1 ; MIPS32-NEXT: jr $ra @@ -251,8 +247,7 @@ define i1 @sle_i64(i64 %a, i64 %b) { ; MIPS32-NEXT: sltiu $2, $2, 1 ; MIPS32-NEXT: sltu $3, $6, $4 ; MIPS32-NEXT: xori $3, $3, 1 -; MIPS32-NEXT: ori $4, $zero, 1 -; MIPS32-NEXT: and $2, $2, $4 +; MIPS32-NEXT: andi $2, $2, 1 ; MIPS32-NEXT: movn $1, $3, $2 ; MIPS32-NEXT: move $2, $1 ; MIPS32-NEXT: jr $ra @@ -269,8 +264,7 @@ define i1 @ugt_i64(i64 %a, i64 %b) { ; MIPS32-NEXT: xor $2, $5, $7 ; MIPS32-NEXT: sltiu $2, $2, 1 ; MIPS32-NEXT: sltu $3, $6, $4 -; MIPS32-NEXT: ori $4, $zero, 1 -; MIPS32-NEXT: and $2, $2, $4 +; MIPS32-NEXT: andi $2, $2, 1 ; MIPS32-NEXT: movn $1, $3, $2 ; MIPS32-NEXT: move $2, $1 ; MIPS32-NEXT: jr $ra @@ -289,8 +283,7 @@ define i1 @uge_i64(i64 %a, i64 %b) { ; MIPS32-NEXT: sltiu $2, $2, 1 ; MIPS32-NEXT: sltu $3, $4, $6 ; MIPS32-NEXT: xori $3, $3, 1 -; MIPS32-NEXT: ori $4, $zero, 1 -; MIPS32-NEXT: and $2, $2, $4 +; MIPS32-NEXT: andi $2, $2, 1 ; MIPS32-NEXT: movn $1, $3, $2 ; MIPS32-NEXT: move $2, $1 ; MIPS32-NEXT: jr $ra @@ -307,8 +300,7 @@ define i1 @ult_i64(i64 %a, i64 %b) { ; MIPS32-NEXT: xor $2, $5, $7 ; MIPS32-NEXT: sltiu $2, $2, 1 ; MIPS32-NEXT: sltu $3, $4, $6 -; MIPS32-NEXT: ori $4, $zero, 1 -; MIPS32-NEXT: and $2, $2, $4 +; MIPS32-NEXT: andi $2, $2, 1 ; MIPS32-NEXT: movn $1, $3, $2 ; MIPS32-NEXT: move $2, $1 ; MIPS32-NEXT: jr $ra @@ -327,8 +319,7 @@ define i1 @ule_i64(i64 %a, i64 %b) { ; MIPS32-NEXT: sltiu $2, $2, 1 ; MIPS32-NEXT: sltu $3, $6, $4 ; MIPS32-NEXT: xori $3, $3, 1 -; MIPS32-NEXT: ori $4, $zero, 1 -; MIPS32-NEXT: and $2, $2, $4 +; MIPS32-NEXT: andi $2, $2, 1 ; MIPS32-NEXT: movn $1, $3, $2 ; MIPS32-NEXT: move $2, $1 ; MIPS32-NEXT: jr $ra diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll index 90d3356d1b7..dcd6c76a8b2 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32 ; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -relocation-model=pic -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32_PIC @@ -15,7 +16,7 @@ define i32 @mod4_0_to_11(i32 %a) { ; MIPS32-NEXT: ori $8, $zero, 0 ; MIPS32-NEXT: subu $8, $4, $8 ; MIPS32-NEXT: sltu $1, $1, $8 -; MIPS32-NEXT: and $1, $1, $5 +; MIPS32-NEXT: andi $1, $1, 1 ; MIPS32-NEXT: sw $4, 28($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $2, 24($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $3, 20($sp) # 4-byte Folded Spill @@ -61,8 +62,7 @@ define i32 @mod4_0_to_11(i32 %a) { ; MIPS32-NEXT: subu $1, $2, $1 ; MIPS32-NEXT: lw $3, 24($sp) # 4-byte Folded Reload ; MIPS32-NEXT: sltu $4, $3, $1 -; MIPS32-NEXT: ori $5, $zero, 1 -; MIPS32-NEXT: and $4, $4, $5 +; MIPS32-NEXT: andi $4, $4, 1 ; MIPS32-NEXT: sw $1, 0($sp) # 4-byte Folded Spill ; MIPS32-NEXT: bnez $4, $BB0_13 ; MIPS32-NEXT: nop @@ -131,7 +131,7 @@ define i32 @mod4_0_to_11(i32 %a) { ; MIPS32_PIC-NEXT: ori $9, $zero, 0 ; MIPS32_PIC-NEXT: subu $9, $4, $9 ; MIPS32_PIC-NEXT: sltu $2, $2, $9 -; MIPS32_PIC-NEXT: and $2, $2, $6 +; MIPS32_PIC-NEXT: andi $2, $2, 1 ; MIPS32_PIC-NEXT: sw $1, 36($sp) # 4-byte Folded Spill ; MIPS32_PIC-NEXT: sw $4, 32($sp) # 4-byte Folded Spill ; MIPS32_PIC-NEXT: sw $3, 28($sp) # 4-byte Folded Spill @@ -180,8 +180,7 @@ define i32 @mod4_0_to_11(i32 %a) { ; MIPS32_PIC-NEXT: subu $1, $2, $1 ; MIPS32_PIC-NEXT: lw $3, 28($sp) # 4-byte Folded Reload ; MIPS32_PIC-NEXT: sltu $4, $3, $1 -; MIPS32_PIC-NEXT: ori $5, $zero, 1 -; MIPS32_PIC-NEXT: and $4, $4, $5 +; MIPS32_PIC-NEXT: andi $4, $4, 1 ; MIPS32_PIC-NEXT: sw $1, 4($sp) # 4-byte Folded Spill ; MIPS32_PIC-NEXT: bnez $4, $BB0_13 ; MIPS32_PIC-NEXT: nop diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s32.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s32.ll index 630aa1312d0..20e549b81a6 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s32.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s32.ll @@ -12,8 +12,7 @@ define void @long_chain_ambiguous_i32_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i32* ; MIPS32-NEXT: lw $2, 0($2) ; MIPS32-NEXT: addiu $3, $sp, 72 ; MIPS32-NEXT: lw $3, 0($3) -; MIPS32-NEXT: ori $8, $zero, 1 -; MIPS32-NEXT: and $8, $4, $8 +; MIPS32-NEXT: andi $8, $4, 1 ; MIPS32-NEXT: sw $1, 44($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $4, 40($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $5, 36($sp) # 4-byte Folded Spill @@ -24,16 +23,14 @@ define void @long_chain_ambiguous_i32_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i32* ; MIPS32-NEXT: bnez $8, $BB0_9 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.1: # %pre.PHI.1 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 36($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 -; MIPS32-NEXT: bnez $1, $BB0_4 +; MIPS32-NEXT: lw $1, 36($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 +; MIPS32-NEXT: bnez $2, $BB0_4 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.2: # %pre.PHI.1.0 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 32($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 -; MIPS32-NEXT: bnez $1, $BB0_5 +; MIPS32-NEXT: lw $1, 32($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 +; MIPS32-NEXT: bnez $2, $BB0_5 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.3: # %b.PHI.1.0 ; MIPS32-NEXT: lw $1, 28($sp) # 4-byte Folded Reload @@ -53,13 +50,12 @@ define void @long_chain_ambiguous_i32_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i32* ; MIPS32-NEXT: sw $2, 16($sp) # 4-byte Folded Spill ; MIPS32-NEXT: $BB0_6: # %b.PHI.1 ; MIPS32-NEXT: lw $1, 16($sp) # 4-byte Folded Reload -; MIPS32-NEXT: ori $2, $zero, 1 -; MIPS32-NEXT: lw $3, 32($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $2, $3, $2 +; MIPS32-NEXT: lw $2, 32($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $3, $2, 1 ; MIPS32-NEXT: move $4, $1 ; MIPS32-NEXT: sw $1, 12($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $4, 8($sp) # 4-byte Folded Spill -; MIPS32-NEXT: bnez $2, $BB0_8 +; MIPS32-NEXT: bnez $3, $BB0_8 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.7: # %b.PHI.1 ; MIPS32-NEXT: j $BB0_15 @@ -72,10 +68,9 @@ define void @long_chain_ambiguous_i32_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i32* ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop ; MIPS32-NEXT: $BB0_9: # %pre.PHI.2 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 40($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 -; MIPS32-NEXT: bnez $1, $BB0_11 +; MIPS32-NEXT: lw $1, 40($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 +; MIPS32-NEXT: bnez $2, $BB0_11 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.10: # %pre.PHI.2 ; MIPS32-NEXT: j $BB0_12 @@ -92,13 +87,12 @@ define void @long_chain_ambiguous_i32_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i32* ; MIPS32-NEXT: sw $2, 4($sp) # 4-byte Folded Spill ; MIPS32-NEXT: $BB0_13: # %b.PHI.2 ; MIPS32-NEXT: lw $1, 4($sp) # 4-byte Folded Reload -; MIPS32-NEXT: ori $2, $zero, 1 -; MIPS32-NEXT: lw $3, 36($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $2, $3, $2 +; MIPS32-NEXT: lw $2, 36($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $3, $2, 1 ; MIPS32-NEXT: move $4, $1 ; MIPS32-NEXT: sw $1, 0($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $4, 8($sp) # 4-byte Folded Spill -; MIPS32-NEXT: bnez $2, $BB0_15 +; MIPS32-NEXT: bnez $3, $BB0_15 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.14: # %b.PHI.2.end ; MIPS32-NEXT: lw $1, 0($sp) # 4-byte Folded Reload @@ -110,14 +104,13 @@ define void @long_chain_ambiguous_i32_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i32* ; MIPS32-NEXT: $BB0_15: # %b.PHI.3 ; MIPS32-NEXT: lw $1, 8($sp) # 4-byte Folded Reload ; MIPS32-NEXT: lw $2, 8($sp) # 4-byte Folded Reload -; MIPS32-NEXT: ori $3, $zero, 1 -; MIPS32-NEXT: lw $4, 32($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $5, $4, $3 -; MIPS32-NEXT: movn $1, $2, $5 -; MIPS32-NEXT: lw $5, 36($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $3, $5, $3 +; MIPS32-NEXT: lw $3, 32($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $4, $3, 1 +; MIPS32-NEXT: movn $1, $2, $4 +; MIPS32-NEXT: lw $4, 36($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $5, $4, 1 ; MIPS32-NEXT: move $6, $2 -; MIPS32-NEXT: movn $6, $1, $3 +; MIPS32-NEXT: movn $6, $1, $5 ; MIPS32-NEXT: lw $1, 20($sp) # 4-byte Folded Reload ; MIPS32-NEXT: sw $6, 0($1) ; MIPS32-NEXT: sw $2, 0($1) @@ -195,8 +188,7 @@ define void @long_chain_i32_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i32* %a, i32* % ; MIPS32-NEXT: addiu $3, $sp, 80 ; MIPS32-NEXT: lw $3, 0($3) ; MIPS32-NEXT: ori $8, $zero, 0 -; MIPS32-NEXT: ori $9, $zero, 1 -; MIPS32-NEXT: and $9, $4, $9 +; MIPS32-NEXT: andi $9, $4, 1 ; MIPS32-NEXT: sw $1, 52($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $4, 48($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $5, 44($sp) # 4-byte Folded Spill @@ -208,16 +200,14 @@ define void @long_chain_i32_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i32* %a, i32* % ; MIPS32-NEXT: bnez $9, $BB1_9 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.1: # %pre.PHI.1 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 44($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 -; MIPS32-NEXT: bnez $1, $BB1_4 +; MIPS32-NEXT: lw $1, 44($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 +; MIPS32-NEXT: bnez $2, $BB1_4 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.2: # %pre.PHI.1.0 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 40($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 -; MIPS32-NEXT: bnez $1, $BB1_5 +; MIPS32-NEXT: lw $1, 40($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 +; MIPS32-NEXT: bnez $2, $BB1_5 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.3: # %b.PHI.1.0 ; MIPS32-NEXT: lw $1, 36($sp) # 4-byte Folded Reload @@ -237,15 +227,14 @@ define void @long_chain_i32_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i32* %a, i32* % ; MIPS32-NEXT: sw $2, 20($sp) # 4-byte Folded Spill ; MIPS32-NEXT: $BB1_6: # %b.PHI.1 ; MIPS32-NEXT: lw $1, 20($sp) # 4-byte Folded Reload -; MIPS32-NEXT: ori $2, $zero, 1 -; MIPS32-NEXT: lw $3, 40($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $2, $3, $2 +; MIPS32-NEXT: lw $2, 40($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $3, $2, 1 ; MIPS32-NEXT: move $4, $1 ; MIPS32-NEXT: lw $5, 24($sp) # 4-byte Folded Reload ; MIPS32-NEXT: sw $1, 16($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $4, 12($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $5, 8($sp) # 4-byte Folded Spill -; MIPS32-NEXT: bnez $2, $BB1_8 +; MIPS32-NEXT: bnez $3, $BB1_8 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.7: # %b.PHI.1 ; MIPS32-NEXT: j $BB1_15 @@ -258,10 +247,9 @@ define void @long_chain_i32_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i32* %a, i32* % ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop ; MIPS32-NEXT: $BB1_9: # %pre.PHI.2 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 48($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 -; MIPS32-NEXT: bnez $1, $BB1_11 +; MIPS32-NEXT: lw $1, 48($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 +; MIPS32-NEXT: bnez $2, $BB1_11 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.10: # %pre.PHI.2 ; MIPS32-NEXT: j $BB1_12 @@ -278,15 +266,14 @@ define void @long_chain_i32_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i32* %a, i32* % ; MIPS32-NEXT: sw $2, 4($sp) # 4-byte Folded Spill ; MIPS32-NEXT: $BB1_13: # %b.PHI.2 ; MIPS32-NEXT: lw $1, 4($sp) # 4-byte Folded Reload -; MIPS32-NEXT: ori $2, $zero, 1 -; MIPS32-NEXT: lw $3, 44($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $2, $3, $2 +; MIPS32-NEXT: lw $2, 44($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $3, $2, 1 ; MIPS32-NEXT: move $4, $1 ; MIPS32-NEXT: move $5, $1 ; MIPS32-NEXT: sw $1, 0($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $4, 12($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $5, 8($sp) # 4-byte Folded Spill -; MIPS32-NEXT: bnez $2, $BB1_15 +; MIPS32-NEXT: bnez $3, $BB1_15 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.14: # %b.PHI.2.end ; MIPS32-NEXT: lw $1, 0($sp) # 4-byte Folded Reload @@ -298,14 +285,13 @@ define void @long_chain_i32_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i32* %a, i32* % ; MIPS32-NEXT: $BB1_15: # %b.PHI.3 ; MIPS32-NEXT: lw $1, 8($sp) # 4-byte Folded Reload ; MIPS32-NEXT: lw $2, 12($sp) # 4-byte Folded Reload -; MIPS32-NEXT: ori $3, $zero, 1 -; MIPS32-NEXT: lw $4, 40($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $5, $4, $3 -; MIPS32-NEXT: movn $1, $2, $5 -; MIPS32-NEXT: lw $5, 44($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $3, $5, $3 +; MIPS32-NEXT: lw $3, 40($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $4, $3, 1 +; MIPS32-NEXT: movn $1, $2, $4 +; MIPS32-NEXT: lw $4, 44($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $5, $4, 1 ; MIPS32-NEXT: move $6, $2 -; MIPS32-NEXT: movn $6, $1, $3 +; MIPS32-NEXT: movn $6, $1, $5 ; MIPS32-NEXT: lw $1, 28($sp) # 4-byte Folded Reload ; MIPS32-NEXT: sw $6, 0($1) ; MIPS32-NEXT: sw $2, 0($1) @@ -381,8 +367,7 @@ define void @long_chain_ambiguous_float_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, flo ; MIPS32-NEXT: lw $2, 0($2) ; MIPS32-NEXT: addiu $3, $sp, 72 ; MIPS32-NEXT: lw $3, 0($3) -; MIPS32-NEXT: ori $8, $zero, 1 -; MIPS32-NEXT: and $8, $4, $8 +; MIPS32-NEXT: andi $8, $4, 1 ; MIPS32-NEXT: sw $1, 44($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $4, 40($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $5, 36($sp) # 4-byte Folded Spill @@ -393,16 +378,14 @@ define void @long_chain_ambiguous_float_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, flo ; MIPS32-NEXT: bnez $8, $BB2_9 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.1: # %pre.PHI.1 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 36($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 -; MIPS32-NEXT: bnez $1, $BB2_4 +; MIPS32-NEXT: lw $1, 36($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 +; MIPS32-NEXT: bnez $2, $BB2_4 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.2: # %pre.PHI.1.0 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 32($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 -; MIPS32-NEXT: bnez $1, $BB2_5 +; MIPS32-NEXT: lw $1, 32($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 +; MIPS32-NEXT: bnez $2, $BB2_5 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.3: # %b.PHI.1.0 ; MIPS32-NEXT: lw $1, 28($sp) # 4-byte Folded Reload @@ -422,13 +405,12 @@ define void @long_chain_ambiguous_float_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, flo ; MIPS32-NEXT: sw $2, 16($sp) # 4-byte Folded Spill ; MIPS32-NEXT: $BB2_6: # %b.PHI.1 ; MIPS32-NEXT: lw $1, 16($sp) # 4-byte Folded Reload -; MIPS32-NEXT: ori $2, $zero, 1 -; MIPS32-NEXT: lw $3, 32($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $2, $3, $2 +; MIPS32-NEXT: lw $2, 32($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $3, $2, 1 ; MIPS32-NEXT: move $4, $1 ; MIPS32-NEXT: sw $1, 12($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $4, 8($sp) # 4-byte Folded Spill -; MIPS32-NEXT: bnez $2, $BB2_8 +; MIPS32-NEXT: bnez $3, $BB2_8 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.7: # %b.PHI.1 ; MIPS32-NEXT: j $BB2_15 @@ -441,10 +423,9 @@ define void @long_chain_ambiguous_float_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, flo ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop ; MIPS32-NEXT: $BB2_9: # %pre.PHI.2 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 40($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 -; MIPS32-NEXT: bnez $1, $BB2_11 +; MIPS32-NEXT: lw $1, 40($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 +; MIPS32-NEXT: bnez $2, $BB2_11 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.10: # %pre.PHI.2 ; MIPS32-NEXT: j $BB2_12 @@ -461,13 +442,12 @@ define void @long_chain_ambiguous_float_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, flo ; MIPS32-NEXT: sw $2, 4($sp) # 4-byte Folded Spill ; MIPS32-NEXT: $BB2_13: # %b.PHI.2 ; MIPS32-NEXT: lw $1, 4($sp) # 4-byte Folded Reload -; MIPS32-NEXT: ori $2, $zero, 1 -; MIPS32-NEXT: lw $3, 36($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $2, $3, $2 +; MIPS32-NEXT: lw $2, 36($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $3, $2, 1 ; MIPS32-NEXT: move $4, $1 ; MIPS32-NEXT: sw $1, 0($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $4, 8($sp) # 4-byte Folded Spill -; MIPS32-NEXT: bnez $2, $BB2_15 +; MIPS32-NEXT: bnez $3, $BB2_15 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.14: # %b.PHI.2.end ; MIPS32-NEXT: lw $1, 0($sp) # 4-byte Folded Reload @@ -479,14 +459,13 @@ define void @long_chain_ambiguous_float_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, flo ; MIPS32-NEXT: $BB2_15: # %b.PHI.3 ; MIPS32-NEXT: lw $1, 8($sp) # 4-byte Folded Reload ; MIPS32-NEXT: lw $2, 8($sp) # 4-byte Folded Reload -; MIPS32-NEXT: ori $3, $zero, 1 -; MIPS32-NEXT: lw $4, 32($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $5, $4, $3 -; MIPS32-NEXT: movn $1, $2, $5 -; MIPS32-NEXT: lw $5, 36($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $3, $5, $3 +; MIPS32-NEXT: lw $3, 32($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $4, $3, 1 +; MIPS32-NEXT: movn $1, $2, $4 +; MIPS32-NEXT: lw $4, 36($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $5, $4, 1 ; MIPS32-NEXT: move $6, $2 -; MIPS32-NEXT: movn $6, $1, $3 +; MIPS32-NEXT: movn $6, $1, $5 ; MIPS32-NEXT: lw $1, 20($sp) # 4-byte Folded Reload ; MIPS32-NEXT: sw $6, 0($1) ; MIPS32-NEXT: sw $2, 0($1) @@ -565,8 +544,7 @@ define void @long_chain_float_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, float* %a, fl ; MIPS32-NEXT: lw $3, 0($3) ; MIPS32-NEXT: ori $8, $zero, 0 ; MIPS32-NEXT: mtc1 $8, $f0 -; MIPS32-NEXT: ori $8, $zero, 1 -; MIPS32-NEXT: and $8, $4, $8 +; MIPS32-NEXT: andi $8, $4, 1 ; MIPS32-NEXT: sw $1, 52($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $4, 48($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $5, 44($sp) # 4-byte Folded Spill @@ -578,16 +556,14 @@ define void @long_chain_float_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, float* %a, fl ; MIPS32-NEXT: bnez $8, $BB3_9 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.1: # %pre.PHI.1 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 44($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 -; MIPS32-NEXT: bnez $1, $BB3_4 +; MIPS32-NEXT: lw $1, 44($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 +; MIPS32-NEXT: bnez $2, $BB3_4 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.2: # %pre.PHI.1.0 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 40($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 -; MIPS32-NEXT: bnez $1, $BB3_5 +; MIPS32-NEXT: lw $1, 40($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 +; MIPS32-NEXT: bnez $2, $BB3_5 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.3: # %b.PHI.1.0 ; MIPS32-NEXT: lw $1, 36($sp) # 4-byte Folded Reload @@ -607,15 +583,14 @@ define void @long_chain_float_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, float* %a, fl ; MIPS32-NEXT: swc1 $f0, 20($sp) # 4-byte Folded Spill ; MIPS32-NEXT: $BB3_6: # %b.PHI.1 ; MIPS32-NEXT: lwc1 $f0, 20($sp) # 4-byte Folded Reload -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 40($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 +; MIPS32-NEXT: lw $1, 40($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 ; MIPS32-NEXT: mov.s $f1, $f0 ; MIPS32-NEXT: lwc1 $f2, 24($sp) # 4-byte Folded Reload ; MIPS32-NEXT: swc1 $f0, 16($sp) # 4-byte Folded Spill ; MIPS32-NEXT: swc1 $f1, 12($sp) # 4-byte Folded Spill ; MIPS32-NEXT: swc1 $f2, 8($sp) # 4-byte Folded Spill -; MIPS32-NEXT: bnez $1, $BB3_8 +; MIPS32-NEXT: bnez $2, $BB3_8 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.7: # %b.PHI.1 ; MIPS32-NEXT: j $BB3_15 @@ -628,10 +603,9 @@ define void @long_chain_float_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, float* %a, fl ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop ; MIPS32-NEXT: $BB3_9: # %pre.PHI.2 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 48($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 -; MIPS32-NEXT: bnez $1, $BB3_11 +; MIPS32-NEXT: lw $1, 48($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 +; MIPS32-NEXT: bnez $2, $BB3_11 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.10: # %pre.PHI.2 ; MIPS32-NEXT: j $BB3_12 @@ -648,15 +622,14 @@ define void @long_chain_float_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, float* %a, fl ; MIPS32-NEXT: swc1 $f0, 4($sp) # 4-byte Folded Spill ; MIPS32-NEXT: $BB3_13: # %b.PHI.2 ; MIPS32-NEXT: lwc1 $f0, 4($sp) # 4-byte Folded Reload -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 44($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 +; MIPS32-NEXT: lw $1, 44($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 ; MIPS32-NEXT: mov.s $f1, $f0 ; MIPS32-NEXT: mov.s $f2, $f0 ; MIPS32-NEXT: swc1 $f0, 0($sp) # 4-byte Folded Spill ; MIPS32-NEXT: swc1 $f1, 12($sp) # 4-byte Folded Spill ; MIPS32-NEXT: swc1 $f2, 8($sp) # 4-byte Folded Spill -; MIPS32-NEXT: bnez $1, $BB3_15 +; MIPS32-NEXT: bnez $2, $BB3_15 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.14: # %b.PHI.2.end ; MIPS32-NEXT: lwc1 $f0, 0($sp) # 4-byte Folded Reload @@ -668,17 +641,16 @@ define void @long_chain_float_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, float* %a, fl ; MIPS32-NEXT: $BB3_15: # %b.PHI.3 ; MIPS32-NEXT: lwc1 $f0, 8($sp) # 4-byte Folded Reload ; MIPS32-NEXT: lwc1 $f1, 12($sp) # 4-byte Folded Reload -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 40($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $3, $2, $1 -; MIPS32-NEXT: movn.s $f0, $f1, $3 -; MIPS32-NEXT: lw $3, 44($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $3, $1 +; MIPS32-NEXT: lw $1, 40($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 +; MIPS32-NEXT: movn.s $f0, $f1, $2 +; MIPS32-NEXT: lw $2, 44($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $3, $2, 1 ; MIPS32-NEXT: mov.s $f2, $f1 -; MIPS32-NEXT: movn.s $f2, $f0, $1 -; MIPS32-NEXT: lw $1, 28($sp) # 4-byte Folded Reload -; MIPS32-NEXT: swc1 $f2, 0($1) -; MIPS32-NEXT: swc1 $f1, 0($1) +; MIPS32-NEXT: movn.s $f2, $f0, $3 +; MIPS32-NEXT: lw $3, 28($sp) # 4-byte Folded Reload +; MIPS32-NEXT: swc1 $f2, 0($3) +; MIPS32-NEXT: swc1 $f1, 0($3) ; MIPS32-NEXT: addiu $sp, $sp, 56 ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s64.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s64.ll index c1f43f6923f..a237099eb75 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s64.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s64.ll @@ -12,8 +12,7 @@ define void @long_chain_ambiguous_i64_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i64* ; MIPS32-NEXT: lw $2, 0($2) ; MIPS32-NEXT: addiu $3, $sp, 96 ; MIPS32-NEXT: lw $3, 0($3) -; MIPS32-NEXT: ori $8, $zero, 1 -; MIPS32-NEXT: and $8, $4, $8 +; MIPS32-NEXT: andi $8, $4, 1 ; MIPS32-NEXT: sw $1, 68($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $4, 64($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $5, 60($sp) # 4-byte Folded Spill @@ -24,16 +23,14 @@ define void @long_chain_ambiguous_i64_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i64* ; MIPS32-NEXT: bnez $8, $BB0_9 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.1: # %pre.PHI.1 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 60($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 -; MIPS32-NEXT: bnez $1, $BB0_4 +; MIPS32-NEXT: lw $1, 60($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 +; MIPS32-NEXT: bnez $2, $BB0_4 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.2: # %pre.PHI.1.0 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 56($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 -; MIPS32-NEXT: bnez $1, $BB0_5 +; MIPS32-NEXT: lw $1, 56($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 +; MIPS32-NEXT: bnez $2, $BB0_5 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.3: # %b.PHI.1.0 ; MIPS32-NEXT: lw $1, 52($sp) # 4-byte Folded Reload @@ -53,13 +50,12 @@ define void @long_chain_ambiguous_i64_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i64* ; MIPS32-NEXT: sdc1 $f0, 32($sp) # 8-byte Folded Spill ; MIPS32-NEXT: $BB0_6: # %b.PHI.1 ; MIPS32-NEXT: ldc1 $f0, 32($sp) # 8-byte Folded Reload -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 56($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 +; MIPS32-NEXT: lw $1, 56($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 ; MIPS32-NEXT: mov.d $f2, $f0 ; MIPS32-NEXT: sdc1 $f0, 24($sp) # 8-byte Folded Spill ; MIPS32-NEXT: sdc1 $f2, 16($sp) # 8-byte Folded Spill -; MIPS32-NEXT: bnez $1, $BB0_8 +; MIPS32-NEXT: bnez $2, $BB0_8 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.7: # %b.PHI.1 ; MIPS32-NEXT: j $BB0_15 @@ -72,10 +68,9 @@ define void @long_chain_ambiguous_i64_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i64* ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop ; MIPS32-NEXT: $BB0_9: # %pre.PHI.2 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 64($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 -; MIPS32-NEXT: bnez $1, $BB0_11 +; MIPS32-NEXT: lw $1, 64($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 +; MIPS32-NEXT: bnez $2, $BB0_11 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.10: # %pre.PHI.2 ; MIPS32-NEXT: j $BB0_12 @@ -92,13 +87,12 @@ define void @long_chain_ambiguous_i64_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i64* ; MIPS32-NEXT: sdc1 $f0, 8($sp) # 8-byte Folded Spill ; MIPS32-NEXT: $BB0_13: # %b.PHI.2 ; MIPS32-NEXT: ldc1 $f0, 8($sp) # 8-byte Folded Reload -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 60($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 +; MIPS32-NEXT: lw $1, 60($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 ; MIPS32-NEXT: mov.d $f2, $f0 ; MIPS32-NEXT: sdc1 $f0, 0($sp) # 8-byte Folded Spill ; MIPS32-NEXT: sdc1 $f2, 16($sp) # 8-byte Folded Spill -; MIPS32-NEXT: bnez $1, $BB0_15 +; MIPS32-NEXT: bnez $2, $BB0_15 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.14: # %b.PHI.2.end ; MIPS32-NEXT: ldc1 $f0, 0($sp) # 8-byte Folded Reload @@ -110,17 +104,16 @@ define void @long_chain_ambiguous_i64_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i64* ; MIPS32-NEXT: $BB0_15: # %b.PHI.3 ; MIPS32-NEXT: ldc1 $f0, 16($sp) # 8-byte Folded Reload ; MIPS32-NEXT: ldc1 $f2, 16($sp) # 8-byte Folded Reload -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 56($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $3, $2, $1 -; MIPS32-NEXT: movn.d $f0, $f2, $3 -; MIPS32-NEXT: lw $3, 60($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $3, $1 +; MIPS32-NEXT: lw $1, 56($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 +; MIPS32-NEXT: movn.d $f0, $f2, $2 +; MIPS32-NEXT: lw $2, 60($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $3, $2, 1 ; MIPS32-NEXT: mov.d $f4, $f2 -; MIPS32-NEXT: movn.d $f4, $f0, $1 -; MIPS32-NEXT: lw $1, 44($sp) # 4-byte Folded Reload -; MIPS32-NEXT: sdc1 $f4, 0($1) -; MIPS32-NEXT: sdc1 $f2, 0($1) +; MIPS32-NEXT: movn.d $f4, $f0, $3 +; MIPS32-NEXT: lw $3, 44($sp) # 4-byte Folded Reload +; MIPS32-NEXT: sdc1 $f4, 0($3) +; MIPS32-NEXT: sdc1 $f2, 0($3) ; MIPS32-NEXT: addiu $sp, $sp, 72 ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop @@ -195,8 +188,7 @@ define void @long_chain_i64_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i64* %a, i64* % ; MIPS32-NEXT: addiu $3, $sp, 104 ; MIPS32-NEXT: lw $3, 0($3) ; MIPS32-NEXT: ori $8, $zero, 0 -; MIPS32-NEXT: ori $9, $zero, 1 -; MIPS32-NEXT: and $9, $4, $9 +; MIPS32-NEXT: andi $9, $4, 1 ; MIPS32-NEXT: sw $1, 76($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $4, 72($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $5, 68($sp) # 4-byte Folded Spill @@ -208,16 +200,14 @@ define void @long_chain_i64_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i64* %a, i64* % ; MIPS32-NEXT: bnez $9, $BB1_9 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.1: # %pre.PHI.1 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 68($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 -; MIPS32-NEXT: bnez $1, $BB1_4 +; MIPS32-NEXT: lw $1, 68($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 +; MIPS32-NEXT: bnez $2, $BB1_4 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.2: # %pre.PHI.1.0 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 64($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 -; MIPS32-NEXT: bnez $1, $BB1_5 +; MIPS32-NEXT: lw $1, 64($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 +; MIPS32-NEXT: bnez $2, $BB1_5 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.3: # %b.PHI.1.0 ; MIPS32-NEXT: lw $1, 60($sp) # 4-byte Folded Reload @@ -244,9 +234,8 @@ define void @long_chain_i64_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i64* %a, i64* % ; MIPS32-NEXT: $BB1_6: # %b.PHI.1 ; MIPS32-NEXT: lw $1, 40($sp) # 4-byte Folded Reload ; MIPS32-NEXT: lw $2, 44($sp) # 4-byte Folded Reload -; MIPS32-NEXT: ori $3, $zero, 1 -; MIPS32-NEXT: lw $4, 64($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $3, $4, $3 +; MIPS32-NEXT: lw $3, 64($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $4, $3, 1 ; MIPS32-NEXT: move $5, $2 ; MIPS32-NEXT: move $6, $1 ; MIPS32-NEXT: lw $7, 48($sp) # 4-byte Folded Reload @@ -257,7 +246,7 @@ define void @long_chain_i64_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i64* %a, i64* % ; MIPS32-NEXT: sw $6, 24($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $7, 20($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $8, 16($sp) # 4-byte Folded Spill -; MIPS32-NEXT: bnez $3, $BB1_8 +; MIPS32-NEXT: bnez $4, $BB1_8 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.7: # %b.PHI.1 ; MIPS32-NEXT: j $BB1_15 @@ -272,10 +261,9 @@ define void @long_chain_i64_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i64* %a, i64* % ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop ; MIPS32-NEXT: $BB1_9: # %pre.PHI.2 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 72($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 -; MIPS32-NEXT: bnez $1, $BB1_11 +; MIPS32-NEXT: lw $1, 72($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 +; MIPS32-NEXT: bnez $2, $BB1_11 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.10: # %pre.PHI.2 ; MIPS32-NEXT: j $BB1_12 @@ -297,9 +285,8 @@ define void @long_chain_i64_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i64* %a, i64* % ; MIPS32-NEXT: $BB1_13: # %b.PHI.2 ; MIPS32-NEXT: lw $1, 8($sp) # 4-byte Folded Reload ; MIPS32-NEXT: lw $2, 12($sp) # 4-byte Folded Reload -; MIPS32-NEXT: ori $3, $zero, 1 -; MIPS32-NEXT: lw $4, 68($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $3, $4, $3 +; MIPS32-NEXT: lw $3, 68($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $4, $3, 1 ; MIPS32-NEXT: move $5, $2 ; MIPS32-NEXT: move $6, $1 ; MIPS32-NEXT: move $7, $2 @@ -310,7 +297,7 @@ define void @long_chain_i64_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i64* %a, i64* % ; MIPS32-NEXT: sw $6, 24($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $7, 20($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $8, 16($sp) # 4-byte Folded Spill -; MIPS32-NEXT: bnez $3, $BB1_15 +; MIPS32-NEXT: bnez $4, $BB1_15 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.14: # %b.PHI.2.end ; MIPS32-NEXT: lw $1, 0($sp) # 4-byte Folded Reload @@ -326,17 +313,16 @@ define void @long_chain_i64_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i64* %a, i64* % ; MIPS32-NEXT: lw $2, 20($sp) # 4-byte Folded Reload ; MIPS32-NEXT: lw $3, 24($sp) # 4-byte Folded Reload ; MIPS32-NEXT: lw $4, 28($sp) # 4-byte Folded Reload -; MIPS32-NEXT: ori $5, $zero, 1 -; MIPS32-NEXT: lw $6, 64($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $7, $6, $5 -; MIPS32-NEXT: movn $2, $4, $7 -; MIPS32-NEXT: movn $1, $3, $7 -; MIPS32-NEXT: lw $7, 68($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $5, $7, $5 +; MIPS32-NEXT: lw $5, 64($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $6, $5, 1 +; MIPS32-NEXT: movn $2, $4, $6 +; MIPS32-NEXT: movn $1, $3, $6 +; MIPS32-NEXT: lw $6, 68($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $7, $6, 1 ; MIPS32-NEXT: move $8, $4 -; MIPS32-NEXT: movn $8, $2, $5 +; MIPS32-NEXT: movn $8, $2, $7 ; MIPS32-NEXT: move $2, $3 -; MIPS32-NEXT: movn $2, $1, $5 +; MIPS32-NEXT: movn $2, $1, $7 ; MIPS32-NEXT: lw $1, 52($sp) # 4-byte Folded Reload ; MIPS32-NEXT: sw $8, 0($1) ; MIPS32-NEXT: sw $2, 4($1) @@ -414,8 +400,7 @@ define void @long_chain_ambiguous_double_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, do ; MIPS32-NEXT: lw $2, 0($2) ; MIPS32-NEXT: addiu $3, $sp, 96 ; MIPS32-NEXT: lw $3, 0($3) -; MIPS32-NEXT: ori $8, $zero, 1 -; MIPS32-NEXT: and $8, $4, $8 +; MIPS32-NEXT: andi $8, $4, 1 ; MIPS32-NEXT: sw $1, 68($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $4, 64($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $5, 60($sp) # 4-byte Folded Spill @@ -426,16 +411,14 @@ define void @long_chain_ambiguous_double_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, do ; MIPS32-NEXT: bnez $8, $BB2_9 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.1: # %pre.PHI.1 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 60($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 -; MIPS32-NEXT: bnez $1, $BB2_4 +; MIPS32-NEXT: lw $1, 60($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 +; MIPS32-NEXT: bnez $2, $BB2_4 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.2: # %pre.PHI.1.0 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 56($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 -; MIPS32-NEXT: bnez $1, $BB2_5 +; MIPS32-NEXT: lw $1, 56($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 +; MIPS32-NEXT: bnez $2, $BB2_5 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.3: # %b.PHI.1.0 ; MIPS32-NEXT: lw $1, 52($sp) # 4-byte Folded Reload @@ -455,13 +438,12 @@ define void @long_chain_ambiguous_double_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, do ; MIPS32-NEXT: sdc1 $f0, 32($sp) # 8-byte Folded Spill ; MIPS32-NEXT: $BB2_6: # %b.PHI.1 ; MIPS32-NEXT: ldc1 $f0, 32($sp) # 8-byte Folded Reload -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 56($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 +; MIPS32-NEXT: lw $1, 56($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 ; MIPS32-NEXT: mov.d $f2, $f0 ; MIPS32-NEXT: sdc1 $f0, 24($sp) # 8-byte Folded Spill ; MIPS32-NEXT: sdc1 $f2, 16($sp) # 8-byte Folded Spill -; MIPS32-NEXT: bnez $1, $BB2_8 +; MIPS32-NEXT: bnez $2, $BB2_8 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.7: # %b.PHI.1 ; MIPS32-NEXT: j $BB2_15 @@ -474,10 +456,9 @@ define void @long_chain_ambiguous_double_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, do ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop ; MIPS32-NEXT: $BB2_9: # %pre.PHI.2 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 64($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 -; MIPS32-NEXT: bnez $1, $BB2_11 +; MIPS32-NEXT: lw $1, 64($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 +; MIPS32-NEXT: bnez $2, $BB2_11 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.10: # %pre.PHI.2 ; MIPS32-NEXT: j $BB2_12 @@ -494,13 +475,12 @@ define void @long_chain_ambiguous_double_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, do ; MIPS32-NEXT: sdc1 $f0, 8($sp) # 8-byte Folded Spill ; MIPS32-NEXT: $BB2_13: # %b.PHI.2 ; MIPS32-NEXT: ldc1 $f0, 8($sp) # 8-byte Folded Reload -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 60($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 +; MIPS32-NEXT: lw $1, 60($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 ; MIPS32-NEXT: mov.d $f2, $f0 ; MIPS32-NEXT: sdc1 $f0, 0($sp) # 8-byte Folded Spill ; MIPS32-NEXT: sdc1 $f2, 16($sp) # 8-byte Folded Spill -; MIPS32-NEXT: bnez $1, $BB2_15 +; MIPS32-NEXT: bnez $2, $BB2_15 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.14: # %b.PHI.2.end ; MIPS32-NEXT: ldc1 $f0, 0($sp) # 8-byte Folded Reload @@ -512,17 +492,16 @@ define void @long_chain_ambiguous_double_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, do ; MIPS32-NEXT: $BB2_15: # %b.PHI.3 ; MIPS32-NEXT: ldc1 $f0, 16($sp) # 8-byte Folded Reload ; MIPS32-NEXT: ldc1 $f2, 16($sp) # 8-byte Folded Reload -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 56($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $3, $2, $1 -; MIPS32-NEXT: movn.d $f0, $f2, $3 -; MIPS32-NEXT: lw $3, 60($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $3, $1 +; MIPS32-NEXT: lw $1, 56($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 +; MIPS32-NEXT: movn.d $f0, $f2, $2 +; MIPS32-NEXT: lw $2, 60($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $3, $2, 1 ; MIPS32-NEXT: mov.d $f4, $f2 -; MIPS32-NEXT: movn.d $f4, $f0, $1 -; MIPS32-NEXT: lw $1, 44($sp) # 4-byte Folded Reload -; MIPS32-NEXT: sdc1 $f4, 0($1) -; MIPS32-NEXT: sdc1 $f2, 0($1) +; MIPS32-NEXT: movn.d $f4, $f0, $3 +; MIPS32-NEXT: lw $3, 44($sp) # 4-byte Folded Reload +; MIPS32-NEXT: sdc1 $f4, 0($3) +; MIPS32-NEXT: sdc1 $f2, 0($3) ; MIPS32-NEXT: addiu $sp, $sp, 72 ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop @@ -600,8 +579,7 @@ define void @long_chain_double_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, double* %a, ; MIPS32-NEXT: ori $9, $zero, 0 ; MIPS32-NEXT: mtc1 $9, $f0 ; MIPS32-NEXT: mtc1 $8, $f1 -; MIPS32-NEXT: ori $8, $zero, 1 -; MIPS32-NEXT: and $8, $4, $8 +; MIPS32-NEXT: andi $8, $4, 1 ; MIPS32-NEXT: sw $1, 84($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $4, 80($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $5, 76($sp) # 4-byte Folded Spill @@ -613,16 +591,14 @@ define void @long_chain_double_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, double* %a, ; MIPS32-NEXT: bnez $8, $BB3_9 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.1: # %pre.PHI.1 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 76($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 -; MIPS32-NEXT: bnez $1, $BB3_4 +; MIPS32-NEXT: lw $1, 76($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 +; MIPS32-NEXT: bnez $2, $BB3_4 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.2: # %pre.PHI.1.0 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 72($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 -; MIPS32-NEXT: bnez $1, $BB3_5 +; MIPS32-NEXT: lw $1, 72($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 +; MIPS32-NEXT: bnez $2, $BB3_5 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.3: # %b.PHI.1.0 ; MIPS32-NEXT: lw $1, 68($sp) # 4-byte Folded Reload @@ -642,15 +618,14 @@ define void @long_chain_double_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, double* %a, ; MIPS32-NEXT: sdc1 $f0, 40($sp) # 8-byte Folded Spill ; MIPS32-NEXT: $BB3_6: # %b.PHI.1 ; MIPS32-NEXT: ldc1 $f0, 40($sp) # 8-byte Folded Reload -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 72($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 +; MIPS32-NEXT: lw $1, 72($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 ; MIPS32-NEXT: mov.d $f2, $f0 ; MIPS32-NEXT: ldc1 $f4, 48($sp) # 8-byte Folded Reload ; MIPS32-NEXT: sdc1 $f0, 32($sp) # 8-byte Folded Spill ; MIPS32-NEXT: sdc1 $f2, 24($sp) # 8-byte Folded Spill ; MIPS32-NEXT: sdc1 $f4, 16($sp) # 8-byte Folded Spill -; MIPS32-NEXT: bnez $1, $BB3_8 +; MIPS32-NEXT: bnez $2, $BB3_8 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.7: # %b.PHI.1 ; MIPS32-NEXT: j $BB3_15 @@ -663,10 +638,9 @@ define void @long_chain_double_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, double* %a, ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop ; MIPS32-NEXT: $BB3_9: # %pre.PHI.2 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 80($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 -; MIPS32-NEXT: bnez $1, $BB3_11 +; MIPS32-NEXT: lw $1, 80($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 +; MIPS32-NEXT: bnez $2, $BB3_11 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.10: # %pre.PHI.2 ; MIPS32-NEXT: j $BB3_12 @@ -683,15 +657,14 @@ define void @long_chain_double_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, double* %a, ; MIPS32-NEXT: sdc1 $f0, 8($sp) # 8-byte Folded Spill ; MIPS32-NEXT: $BB3_13: # %b.PHI.2 ; MIPS32-NEXT: ldc1 $f0, 8($sp) # 8-byte Folded Reload -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 76($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $2, $1 +; MIPS32-NEXT: lw $1, 76($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 ; MIPS32-NEXT: mov.d $f2, $f0 ; MIPS32-NEXT: mov.d $f4, $f0 ; MIPS32-NEXT: sdc1 $f0, 0($sp) # 8-byte Folded Spill ; MIPS32-NEXT: sdc1 $f2, 24($sp) # 8-byte Folded Spill ; MIPS32-NEXT: sdc1 $f4, 16($sp) # 8-byte Folded Spill -; MIPS32-NEXT: bnez $1, $BB3_15 +; MIPS32-NEXT: bnez $2, $BB3_15 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.14: # %b.PHI.2.end ; MIPS32-NEXT: ldc1 $f0, 0($sp) # 8-byte Folded Reload @@ -703,17 +676,16 @@ define void @long_chain_double_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, double* %a, ; MIPS32-NEXT: $BB3_15: # %b.PHI.3 ; MIPS32-NEXT: ldc1 $f0, 16($sp) # 8-byte Folded Reload ; MIPS32-NEXT: ldc1 $f2, 24($sp) # 8-byte Folded Reload -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: lw $2, 72($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $3, $2, $1 -; MIPS32-NEXT: movn.d $f0, $f2, $3 -; MIPS32-NEXT: lw $3, 76($sp) # 4-byte Folded Reload -; MIPS32-NEXT: and $1, $3, $1 +; MIPS32-NEXT: lw $1, 72($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $2, $1, 1 +; MIPS32-NEXT: movn.d $f0, $f2, $2 +; MIPS32-NEXT: lw $2, 76($sp) # 4-byte Folded Reload +; MIPS32-NEXT: andi $3, $2, 1 ; MIPS32-NEXT: mov.d $f4, $f2 -; MIPS32-NEXT: movn.d $f4, $f0, $1 -; MIPS32-NEXT: lw $1, 60($sp) # 4-byte Folded Reload -; MIPS32-NEXT: sdc1 $f4, 0($1) -; MIPS32-NEXT: sdc1 $f2, 0($1) +; MIPS32-NEXT: movn.d $f4, $f0, $3 +; MIPS32-NEXT: lw $3, 60($sp) # 4-byte Folded Reload +; MIPS32-NEXT: sdc1 $f4, 0($3) +; MIPS32-NEXT: sdc1 $f2, 0($3) ; MIPS32-NEXT: addiu $sp, $sp, 88 ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll index 09a7439aaa5..659eadf181c 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll @@ -28,8 +28,7 @@ define zeroext i8 @mul_i8_zext(i8 zeroext %a, i8 zeroext %b) { ; MIPS32-LABEL: mul_i8_zext: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: mul $1, $5, $4 -; MIPS32-NEXT: ori $2, $zero, 255 -; MIPS32-NEXT: and $2, $1, $2 +; MIPS32-NEXT: andi $2, $1, 255 ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop entry: @@ -65,8 +64,7 @@ define zeroext i16 @mul_i16_zext(i16 zeroext %a, i16 zeroext %b) { ; MIPS32-LABEL: mul_i16_zext: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: mul $1, $5, $4 -; MIPS32-NEXT: ori $2, $zero, 65535 -; MIPS32-NEXT: and $2, $1, $2 +; MIPS32-NEXT: andi $2, $1, 65535 ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop entry: @@ -120,38 +118,37 @@ define i128 @mul_i128(i128 %a, i128 %b) { ; MIPS32-NEXT: mfhi $12 ; MIPS32-NEXT: addu $10, $10, $11 ; MIPS32-NEXT: sltu $11, $10, $11 -; MIPS32-NEXT: ori $13, $zero, 1 -; MIPS32-NEXT: and $11, $11, $13 +; MIPS32-NEXT: andi $11, $11, 1 ; MIPS32-NEXT: addu $10, $10, $12 ; MIPS32-NEXT: sltu $12, $10, $12 -; MIPS32-NEXT: and $12, $12, $13 +; MIPS32-NEXT: andi $12, $12, 1 ; MIPS32-NEXT: addu $11, $11, $12 ; MIPS32-NEXT: mul $12, $3, $4 -; MIPS32-NEXT: mul $14, $2, $5 -; MIPS32-NEXT: mul $15, $1, $6 +; MIPS32-NEXT: mul $13, $2, $5 +; MIPS32-NEXT: mul $14, $1, $6 ; MIPS32-NEXT: multu $2, $4 -; MIPS32-NEXT: mfhi $24 +; MIPS32-NEXT: mfhi $15 ; MIPS32-NEXT: multu $1, $5 -; MIPS32-NEXT: mfhi $25 +; MIPS32-NEXT: mfhi $24 +; MIPS32-NEXT: addu $12, $12, $13 +; MIPS32-NEXT: sltu $13, $12, $13 +; MIPS32-NEXT: andi $13, $13, 1 ; MIPS32-NEXT: addu $12, $12, $14 ; MIPS32-NEXT: sltu $14, $12, $14 -; MIPS32-NEXT: and $14, $14, $13 +; MIPS32-NEXT: andi $14, $14, 1 +; MIPS32-NEXT: addu $13, $13, $14 ; MIPS32-NEXT: addu $12, $12, $15 -; MIPS32-NEXT: sltu $15, $12, $15 -; MIPS32-NEXT: and $15, $15, $13 -; MIPS32-NEXT: addu $14, $14, $15 +; MIPS32-NEXT: sltu $14, $12, $15 +; MIPS32-NEXT: andi $14, $14, 1 +; MIPS32-NEXT: addu $13, $13, $14 ; MIPS32-NEXT: addu $12, $12, $24 -; MIPS32-NEXT: sltu $15, $12, $24 -; MIPS32-NEXT: and $15, $15, $13 -; MIPS32-NEXT: addu $14, $14, $15 -; MIPS32-NEXT: addu $12, $12, $25 -; MIPS32-NEXT: sltu $15, $12, $25 -; MIPS32-NEXT: and $15, $15, $13 -; MIPS32-NEXT: addu $14, $14, $15 +; MIPS32-NEXT: sltu $14, $12, $24 +; MIPS32-NEXT: andi $14, $14, 1 +; MIPS32-NEXT: addu $13, $13, $14 ; MIPS32-NEXT: addu $12, $12, $11 ; MIPS32-NEXT: sltu $11, $12, $11 -; MIPS32-NEXT: and $11, $11, $13 -; MIPS32-NEXT: addu $11, $14, $11 +; MIPS32-NEXT: andi $11, $11, 1 +; MIPS32-NEXT: addu $11, $13, $11 ; MIPS32-NEXT: mul $8, $8, $4 ; MIPS32-NEXT: mul $13, $3, $5 ; MIPS32-NEXT: mul $14, $2, $6 @@ -187,8 +184,7 @@ define void @umul_with_overflow(i32 %lhs, i32 %rhs, i32* %pmul, i1* %pcarry_flag ; MIPS32-NEXT: multu $4, $5 ; MIPS32-NEXT: mfhi $2 ; MIPS32-NEXT: sltu $2, $zero, $2 -; MIPS32-NEXT: ori $3, $zero, 1 -; MIPS32-NEXT: and $2, $2, $3 +; MIPS32-NEXT: andi $2, $2, 1 ; MIPS32-NEXT: sb $2, 0($7) ; MIPS32-NEXT: sw $1, 0($6) ; MIPS32-NEXT: jr $ra diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/phi.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/phi.ll index 91c8e608ee2..4facc766f00 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/phi.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/phi.ll @@ -6,8 +6,7 @@ define i1 @phi_i1(i1 %cnd, i1 %a, i1 %b) { ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: addiu $sp, $sp, -16 ; MIPS32-NEXT: .cfi_def_cfa_offset 16 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: and $1, $4, $1 +; MIPS32-NEXT: andi $1, $4, 1 ; MIPS32-NEXT: sw $5, 12($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $6, 8($sp) # 4-byte Folded Spill ; MIPS32-NEXT: bnez $1, $BB0_2 @@ -48,8 +47,7 @@ define i8 @phi_i8(i1 %cnd, i8 %a, i8 %b) { ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: addiu $sp, $sp, -16 ; MIPS32-NEXT: .cfi_def_cfa_offset 16 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: and $1, $4, $1 +; MIPS32-NEXT: andi $1, $4, 1 ; MIPS32-NEXT: sw $5, 12($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $6, 8($sp) # 4-byte Folded Spill ; MIPS32-NEXT: bnez $1, $BB1_2 @@ -90,8 +88,7 @@ define i16 @phi_i16(i1 %cnd, i16 %a, i16 %b) { ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: addiu $sp, $sp, -16 ; MIPS32-NEXT: .cfi_def_cfa_offset 16 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: and $1, $4, $1 +; MIPS32-NEXT: andi $1, $4, 1 ; MIPS32-NEXT: sw $5, 12($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $6, 8($sp) # 4-byte Folded Spill ; MIPS32-NEXT: bnez $1, $BB2_2 @@ -132,8 +129,7 @@ define i32 @phi_i32(i1 %cnd, i32 %a, i32 %b) { ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: addiu $sp, $sp, -16 ; MIPS32-NEXT: .cfi_def_cfa_offset 16 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: and $1, $4, $1 +; MIPS32-NEXT: andi $1, $4, 1 ; MIPS32-NEXT: sw $5, 12($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $6, 8($sp) # 4-byte Folded Spill ; MIPS32-NEXT: bnez $1, $BB3_2 @@ -178,8 +174,7 @@ define i64 @phi_i64(i1 %cnd, i64 %a, i64 %b) { ; MIPS32-NEXT: lw $1, 0($1) ; MIPS32-NEXT: addiu $2, $sp, 44 ; MIPS32-NEXT: lw $2, 0($2) -; MIPS32-NEXT: ori $3, $zero, 1 -; MIPS32-NEXT: and $3, $4, $3 +; MIPS32-NEXT: andi $3, $4, 1 ; MIPS32-NEXT: sw $1, 20($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $6, 16($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $7, 12($sp) # 4-byte Folded Spill @@ -229,8 +224,7 @@ define void @phi_ambiguous_i64_in_fpr(i1 %cnd, i64* %i64_ptr_a, i64* %i64_ptr_b, ; MIPS32-NEXT: .cfi_def_cfa_offset 32 ; MIPS32-NEXT: ldc1 $f0, 0($5) ; MIPS32-NEXT: ldc1 $f2, 0($6) -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: and $1, $4, $1 +; MIPS32-NEXT: andi $1, $4, 1 ; MIPS32-NEXT: sw $7, 28($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sdc1 $f0, 16($sp) # 8-byte Folded Spill ; MIPS32-NEXT: sdc1 $f2, 8($sp) # 8-byte Folded Spill @@ -278,8 +272,7 @@ define float @phi_float(i1 %cnd, float %a, float %b) { ; MIPS32-NEXT: .cfi_def_cfa_offset 16 ; MIPS32-NEXT: mtc1 $5, $f0 ; MIPS32-NEXT: mtc1 $6, $f1 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: and $1, $4, $1 +; MIPS32-NEXT: andi $1, $4, 1 ; MIPS32-NEXT: swc1 $f0, 12($sp) # 4-byte Folded Spill ; MIPS32-NEXT: swc1 $f1, 8($sp) # 4-byte Folded Spill ; MIPS32-NEXT: bnez $1, $BB6_2 @@ -321,8 +314,7 @@ define void @phi_ambiguous_float_in_gpr(i1 %cnd, float* %f32_ptr_a, float* %f32_ ; MIPS32-NEXT: .cfi_def_cfa_offset 16 ; MIPS32-NEXT: lw $1, 0($5) ; MIPS32-NEXT: lw $2, 0($6) -; MIPS32-NEXT: ori $3, $zero, 1 -; MIPS32-NEXT: and $3, $4, $3 +; MIPS32-NEXT: andi $3, $4, 1 ; MIPS32-NEXT: sw $1, 12($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $7, 8($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $2, 4($sp) # 4-byte Folded Spill @@ -370,8 +362,7 @@ define double @phi_double(double %a, double %b, i1 %cnd) { ; MIPS32-NEXT: .cfi_def_cfa_offset 24 ; MIPS32-NEXT: addiu $1, $sp, 40 ; MIPS32-NEXT: lw $1, 0($1) -; MIPS32-NEXT: ori $2, $zero, 1 -; MIPS32-NEXT: and $1, $1, $2 +; MIPS32-NEXT: andi $1, $1, 1 ; MIPS32-NEXT: sdc1 $f12, 16($sp) # 8-byte Folded Spill ; MIPS32-NEXT: sdc1 $f14, 8($sp) # 8-byte Folded Spill ; MIPS32-NEXT: bnez $1, $BB8_2 diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll index 7ce74bb68be..d2520daf6f2 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll @@ -157,11 +157,10 @@ entry: define signext i8 @udiv_i8(i8 signext %a, i8 signext %b) { ; MIPS32-LABEL: udiv_i8: ; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: ori $1, $zero, 255 -; MIPS32-NEXT: and $2, $5, $1 -; MIPS32-NEXT: and $1, $4, $1 -; MIPS32-NEXT: divu $zero, $2, $1 -; MIPS32-NEXT: teq $1, $zero, 7 +; MIPS32-NEXT: andi $1, $5, 255 +; MIPS32-NEXT: andi $2, $4, 255 +; MIPS32-NEXT: divu $zero, $1, $2 +; MIPS32-NEXT: teq $2, $zero, 7 ; MIPS32-NEXT: mflo $1 ; MIPS32-NEXT: sll $1, $1, 24 ; MIPS32-NEXT: sra $2, $1, 24 @@ -175,11 +174,10 @@ entry: define signext i16 @udiv_i16(i16 signext %a, i16 signext %b) { ; MIPS32-LABEL: udiv_i16: ; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: ori $1, $zero, 65535 -; MIPS32-NEXT: and $2, $5, $1 -; MIPS32-NEXT: and $1, $4, $1 -; MIPS32-NEXT: divu $zero, $2, $1 -; MIPS32-NEXT: teq $1, $zero, 7 +; MIPS32-NEXT: andi $1, $5, 65535 +; MIPS32-NEXT: andi $2, $4, 65535 +; MIPS32-NEXT: divu $zero, $1, $2 +; MIPS32-NEXT: teq $2, $zero, 7 ; MIPS32-NEXT: mflo $1 ; MIPS32-NEXT: sll $1, $1, 16 ; MIPS32-NEXT: sra $2, $1, 16 @@ -231,11 +229,10 @@ entry: define signext i8 @urem_i8(i8 signext %a, i8 signext %b) { ; MIPS32-LABEL: urem_i8: ; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: ori $1, $zero, 255 -; MIPS32-NEXT: and $2, $5, $1 -; MIPS32-NEXT: and $1, $4, $1 -; MIPS32-NEXT: divu $zero, $2, $1 -; MIPS32-NEXT: teq $1, $zero, 7 +; MIPS32-NEXT: andi $1, $5, 255 +; MIPS32-NEXT: andi $2, $4, 255 +; MIPS32-NEXT: divu $zero, $1, $2 +; MIPS32-NEXT: teq $2, $zero, 7 ; MIPS32-NEXT: mfhi $1 ; MIPS32-NEXT: sll $1, $1, 24 ; MIPS32-NEXT: sra $2, $1, 24 @@ -249,11 +246,10 @@ entry: define signext i16 @urem_i16(i16 signext %a, i16 signext %b) { ; MIPS32-LABEL: urem_i16: ; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: ori $1, $zero, 65535 -; MIPS32-NEXT: and $2, $5, $1 -; MIPS32-NEXT: and $1, $4, $1 -; MIPS32-NEXT: divu $zero, $2, $1 -; MIPS32-NEXT: teq $1, $zero, 7 +; MIPS32-NEXT: andi $1, $5, 65535 +; MIPS32-NEXT: andi $2, $4, 65535 +; MIPS32-NEXT: divu $zero, $1, $2 +; MIPS32-NEXT: teq $2, $zero, 7 ; MIPS32-NEXT: mfhi $1 ; MIPS32-NEXT: sll $1, $1, 16 ; MIPS32-NEXT: sra $2, $1, 16 diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll index e7b25219cdb..c127d120891 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll @@ -4,8 +4,7 @@ define i8 @select_i8(i1 %test, i8 %a, i8 %b) { ; MIPS32-LABEL: select_i8: ; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: and $1, $4, $1 +; MIPS32-NEXT: andi $1, $4, 1 ; MIPS32-NEXT: movn $6, $5, $1 ; MIPS32-NEXT: move $2, $6 ; MIPS32-NEXT: jr $ra @@ -18,8 +17,7 @@ entry: define i16 @select_i16(i1 %test, i16 %a, i16 %b) { ; MIPS32-LABEL: select_i16: ; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: and $1, $4, $1 +; MIPS32-NEXT: andi $1, $4, 1 ; MIPS32-NEXT: movn $6, $5, $1 ; MIPS32-NEXT: move $2, $6 ; MIPS32-NEXT: jr $ra @@ -32,8 +30,7 @@ entry: define i32 @select_i32(i1 %test, i32 %a, i32 %b) { ; MIPS32-LABEL: select_i32: ; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: and $1, $4, $1 +; MIPS32-NEXT: andi $1, $4, 1 ; MIPS32-NEXT: movn $6, $5, $1 ; MIPS32-NEXT: move $2, $6 ; MIPS32-NEXT: jr $ra @@ -46,8 +43,7 @@ entry: define i32* @select_ptr(i1 %test, i32* %a, i32* %b) { ; MIPS32-LABEL: select_ptr: ; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: and $1, $4, $1 +; MIPS32-NEXT: andi $1, $4, 1 ; MIPS32-NEXT: movn $6, $5, $1 ; MIPS32-NEXT: move $2, $6 ; MIPS32-NEXT: jr $ra @@ -62,8 +58,7 @@ define i32 @select_with_negation(i32 %a, i32 %b, i32 %x, i32 %y) { ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: slt $1, $4, $5 ; MIPS32-NEXT: not $1, $1 -; MIPS32-NEXT: ori $2, $zero, 1 -; MIPS32-NEXT: and $1, $1, $2 +; MIPS32-NEXT: andi $1, $1, 1 ; MIPS32-NEXT: movn $7, $6, $1 ; MIPS32-NEXT: move $2, $7 ; MIPS32-NEXT: jr $ra @@ -84,8 +79,7 @@ define i64 @select_i64(i1 %test, i64 %a, i64 %b) { ; MIPS32-NEXT: lw $1, 0($1) ; MIPS32-NEXT: addiu $2, $sp, 28 ; MIPS32-NEXT: lw $2, 0($2) -; MIPS32-NEXT: ori $3, $zero, 1 -; MIPS32-NEXT: and $3, $4, $3 +; MIPS32-NEXT: andi $3, $4, 1 ; MIPS32-NEXT: movn $1, $6, $3 ; MIPS32-NEXT: movn $2, $7, $3 ; MIPS32-NEXT: sw $2, 4($sp) # 4-byte Folded Spill @@ -104,8 +98,7 @@ define void @select_ambiguous_i64_in_fpr(i1 %test, i64* %i64_ptr_a, i64* %i64_pt ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: ldc1 $f0, 0($5) ; MIPS32-NEXT: ldc1 $f2, 0($6) -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: and $1, $4, $1 +; MIPS32-NEXT: andi $1, $4, 1 ; MIPS32-NEXT: movn.d $f2, $f0, $1 ; MIPS32-NEXT: sdc1 $f2, 0($7) ; MIPS32-NEXT: jr $ra @@ -123,8 +116,7 @@ define float @select_float(i1 %test, float %a, float %b) { ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: mtc1 $5, $f0 ; MIPS32-NEXT: mtc1 $6, $f1 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: and $1, $4, $1 +; MIPS32-NEXT: andi $1, $4, 1 ; MIPS32-NEXT: movn.s $f1, $f0, $1 ; MIPS32-NEXT: mov.s $f0, $f1 ; MIPS32-NEXT: jr $ra @@ -139,8 +131,7 @@ define void @select_ambiguous_float_in_gpr(i1 %test, float* %f32_ptr_a, float* % ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: lw $1, 0($5) ; MIPS32-NEXT: lw $2, 0($6) -; MIPS32-NEXT: ori $3, $zero, 1 -; MIPS32-NEXT: and $3, $4, $3 +; MIPS32-NEXT: andi $3, $4, 1 ; MIPS32-NEXT: movn $2, $1, $3 ; MIPS32-NEXT: sw $2, 0($7) ; MIPS32-NEXT: jr $ra @@ -158,8 +149,7 @@ define double @select_double(double %a, double %b, i1 %test) { ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: addiu $1, $sp, 16 ; MIPS32-NEXT: lw $1, 0($1) -; MIPS32-NEXT: ori $2, $zero, 1 -; MIPS32-NEXT: and $1, $1, $2 +; MIPS32-NEXT: andi $1, $1, 1 ; MIPS32-NEXT: movn.d $f14, $f12, $1 ; MIPS32-NEXT: mov.d $f0, $f14 ; MIPS32-NEXT: jr $ra diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sitofp_and_uitofp.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sitofp_and_uitofp.ll index 6406f64d82b..0017f0c0ed0 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sitofp_and_uitofp.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sitofp_and_uitofp.ll @@ -173,8 +173,7 @@ entry: define float @u16tof32(i16 zeroext %a) { ; FP32-LABEL: u16tof32: ; FP32: # %bb.0: # %entry -; FP32-NEXT: ori $1, $zero, 65535 -; FP32-NEXT: and $1, $4, $1 +; FP32-NEXT: andi $1, $4, 65535 ; FP32-NEXT: lui $2, 17200 ; FP32-NEXT: mtc1 $1, $f0 ; FP32-NEXT: mtc1 $2, $f1 @@ -189,8 +188,7 @@ define float @u16tof32(i16 zeroext %a) { ; ; FP64-LABEL: u16tof32: ; FP64: # %bb.0: # %entry -; FP64-NEXT: ori $1, $zero, 65535 -; FP64-NEXT: and $1, $4, $1 +; FP64-NEXT: andi $1, $4, 65535 ; FP64-NEXT: lui $2, 17200 ; FP64-NEXT: mtc1 $1, $f0 ; FP64-NEXT: mthc1 $2, $f0 @@ -210,8 +208,7 @@ entry: define float @u8tof32(i8 zeroext %a) { ; FP32-LABEL: u8tof32: ; FP32: # %bb.0: # %entry -; FP32-NEXT: ori $1, $zero, 255 -; FP32-NEXT: and $1, $4, $1 +; FP32-NEXT: andi $1, $4, 255 ; FP32-NEXT: lui $2, 17200 ; FP32-NEXT: mtc1 $1, $f0 ; FP32-NEXT: mtc1 $2, $f1 @@ -226,8 +223,7 @@ define float @u8tof32(i8 zeroext %a) { ; ; FP64-LABEL: u8tof32: ; FP64: # %bb.0: # %entry -; FP64-NEXT: ori $1, $zero, 255 -; FP64-NEXT: and $1, $4, $1 +; FP64-NEXT: andi $1, $4, 255 ; FP64-NEXT: lui $2, 17200 ; FP64-NEXT: mtc1 $1, $f0 ; FP64-NEXT: mthc1 $2, $f0 @@ -296,8 +292,7 @@ entry: define double @u16tof64(i16 zeroext %a) { ; FP32-LABEL: u16tof64: ; FP32: # %bb.0: # %entry -; FP32-NEXT: ori $1, $zero, 65535 -; FP32-NEXT: and $1, $4, $1 +; FP32-NEXT: andi $1, $4, 65535 ; FP32-NEXT: lui $2, 17200 ; FP32-NEXT: mtc1 $1, $f0 ; FP32-NEXT: mtc1 $2, $f1 @@ -311,8 +306,7 @@ define double @u16tof64(i16 zeroext %a) { ; ; FP64-LABEL: u16tof64: ; FP64: # %bb.0: # %entry -; FP64-NEXT: ori $1, $zero, 65535 -; FP64-NEXT: and $1, $4, $1 +; FP64-NEXT: andi $1, $4, 65535 ; FP64-NEXT: lui $2, 17200 ; FP64-NEXT: mtc1 $1, $f0 ; FP64-NEXT: mthc1 $2, $f0 @@ -331,8 +325,7 @@ entry: define double @u8tof64(i8 zeroext %a) { ; FP32-LABEL: u8tof64: ; FP32: # %bb.0: # %entry -; FP32-NEXT: ori $1, $zero, 255 -; FP32-NEXT: and $1, $4, $1 +; FP32-NEXT: andi $1, $4, 255 ; FP32-NEXT: lui $2, 17200 ; FP32-NEXT: mtc1 $1, $f0 ; FP32-NEXT: mtc1 $2, $f1 @@ -346,8 +339,7 @@ define double @u8tof64(i8 zeroext %a) { ; ; FP64-LABEL: u8tof64: ; FP64: # %bb.0: # %entry -; FP64-NEXT: ori $1, $zero, 255 -; FP64-NEXT: and $1, $4, $1 +; FP64-NEXT: andi $1, $4, 255 ; FP64-NEXT: lui $2, 17200 ; FP64-NEXT: mtc1 $1, $f0 ; FP64-NEXT: mthc1 $2, $f0 diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll index 0a15f673b66..66dc761c5fa 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll @@ -29,8 +29,7 @@ define zeroext i8 @sub_i8_zext(i8 zeroext %a, i8 zeroext %b) { ; MIPS32-LABEL: sub_i8_zext: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: subu $1, $5, $4 -; MIPS32-NEXT: ori $2, $zero, 255 -; MIPS32-NEXT: and $2, $1, $2 +; MIPS32-NEXT: andi $2, $1, 255 ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop entry: @@ -66,8 +65,7 @@ define zeroext i16 @sub_i16_zext(i16 zeroext %a, i16 zeroext %b) { ; MIPS32-LABEL: sub_i16_zext: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: subu $1, $5, $4 -; MIPS32-NEXT: ori $2, $zero, 65535 -; MIPS32-NEXT: and $2, $1, $2 +; MIPS32-NEXT: andi $2, $1, 65535 ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop entry: @@ -92,8 +90,7 @@ define i64 @sub_i64(i64 %a, i64 %b) { ; MIPS32-NEXT: subu $2, $6, $4 ; MIPS32-NEXT: sltu $1, $6, $4 ; MIPS32-NEXT: subu $3, $7, $5 -; MIPS32-NEXT: ori $4, $zero, 1 -; MIPS32-NEXT: and $1, $1, $4 +; MIPS32-NEXT: andi $1, $1, 1 ; MIPS32-NEXT: subu $3, $3, $1 ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop @@ -116,24 +113,23 @@ define i128 @sub_i128(i128 %a, i128 %b) { ; MIPS32-NEXT: subu $9, $1, $4 ; MIPS32-NEXT: sltu $1, $1, $4 ; MIPS32-NEXT: subu $4, $2, $5 -; MIPS32-NEXT: ori $10, $zero, 1 -; MIPS32-NEXT: and $11, $1, $10 -; MIPS32-NEXT: subu $4, $4, $11 -; MIPS32-NEXT: xor $11, $2, $5 -; MIPS32-NEXT: sltiu $11, $11, 1 +; MIPS32-NEXT: andi $10, $1, 1 +; MIPS32-NEXT: subu $4, $4, $10 +; MIPS32-NEXT: xor $10, $2, $5 +; MIPS32-NEXT: sltiu $10, $10, 1 ; MIPS32-NEXT: sltu $2, $2, $5 -; MIPS32-NEXT: and $5, $11, $10 +; MIPS32-NEXT: andi $5, $10, 1 ; MIPS32-NEXT: movn $2, $1, $5 ; MIPS32-NEXT: subu $1, $3, $6 -; MIPS32-NEXT: and $5, $2, $10 +; MIPS32-NEXT: andi $5, $2, 1 ; MIPS32-NEXT: subu $1, $1, $5 ; MIPS32-NEXT: xor $5, $3, $6 ; MIPS32-NEXT: sltiu $5, $5, 1 ; MIPS32-NEXT: sltu $3, $3, $6 -; MIPS32-NEXT: and $5, $5, $10 +; MIPS32-NEXT: andi $5, $5, 1 ; MIPS32-NEXT: movn $3, $2, $5 ; MIPS32-NEXT: subu $2, $8, $7 -; MIPS32-NEXT: and $3, $3, $10 +; MIPS32-NEXT: andi $3, $3, 1 ; MIPS32-NEXT: subu $5, $2, $3 ; MIPS32-NEXT: move $2, $9 ; MIPS32-NEXT: move $3, $4 diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/test_TypeInfoforMF.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/test_TypeInfoforMF.ll index e06bf060952..25e87da5ae4 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/test_TypeInfoforMF.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/test_TypeInfoforMF.ll @@ -57,8 +57,7 @@ define i32 @incoming_gpr(i32 %incoming_phys_reg, i1 %test, i32* %a) { ; MIPS32-LABEL: incoming_gpr: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: lw $1, 0($6) -; MIPS32-NEXT: ori $2, $zero, 1 -; MIPS32-NEXT: and $2, $5, $2 +; MIPS32-NEXT: andi $2, $5, 1 ; MIPS32-NEXT: movn $4, $1, $2 ; MIPS32-NEXT: move $2, $4 ; MIPS32-NEXT: jr $ra @@ -73,8 +72,7 @@ define float @incoming_fpr(float %incoming_phys_reg, i1 %test, float* %a) { ; MIPS32-LABEL: incoming_fpr: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: lwc1 $f0, 0($6) -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: and $1, $5, $1 +; MIPS32-NEXT: andi $1, $5, 1 ; MIPS32-NEXT: movn.s $f12, $f0, $1 ; MIPS32-NEXT: mov.s $f0, $f12 ; MIPS32-NEXT: jr $ra @@ -91,8 +89,7 @@ define i32 @incoming_i32_instr(i32 %val1, i32 %val2, i32* %i32_ptr, i1 %test) { ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: lw $1, 0($6) ; MIPS32-NEXT: addu $2, $5, $4 -; MIPS32-NEXT: ori $3, $zero, 1 -; MIPS32-NEXT: and $3, $7, $3 +; MIPS32-NEXT: andi $3, $7, 1 ; MIPS32-NEXT: movn $2, $1, $3 ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop @@ -108,8 +105,7 @@ define float @incoming_float_instr(float %val1, float %val2, float* %float_ptr, ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: lwc1 $f0, 0($6) ; MIPS32-NEXT: add.s $f1, $f14, $f12 -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: and $1, $7, $1 +; MIPS32-NEXT: andi $1, $7, 1 ; MIPS32-NEXT: movn.s $f1, $f0, $1 ; MIPS32-NEXT: mov.s $f0, $f1 ; MIPS32-NEXT: jr $ra diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/truncStore_and_aExtLoad.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/truncStore_and_aExtLoad.ll index e051b30797a..e4f93520fe9 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/truncStore_and_aExtLoad.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/truncStore_and_aExtLoad.ll @@ -27,8 +27,7 @@ define void @load_store_i1(i1* %px, i1* %py) { ; MIPS32-LABEL: load_store_i1: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: lbu $1, 0($5) -; MIPS32-NEXT: ori $2, $zero, 1 -; MIPS32-NEXT: and $1, $1, $2 +; MIPS32-NEXT: andi $1, $1, 1 ; MIPS32-NEXT: sb $1, 0($4) ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop |
