Revert "[MIPS GlobalISel] Select bitreverse"

This reverts commit dbc136e0fe7e14c64dcb78e72321bb41af60afa4.
It broke buildbots:
http://lab.llvm.org:8011/builders/clang-x86_64-debian-fast/builds/21066

2 files changed, 0 insertions, 399 deletions

diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitreverse.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitreverse.mir
deleted file mode 100644
index ca874f5e499..00000000000
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitreverse.mir
+++ /dev/null
@@ -1,215 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
-# RUN: llc -mtriple=mipsel-linux-gnu -run-pass=legalizer -mattr=+mips32r2 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R2
---- |
-
-  define void @bitreverse_i32() { entry: ret void }
-  define void @bitreverse_i64() { entry: ret void }
-
-...
----
-name:            bitreverse_i32
-alignment:       4
-tracksRegLiveness: true
-body:             |
-  bb.1.entry:
-    liveins: $a0
-
-    ; MIPS32-LABEL: name: bitreverse_i32
-    ; MIPS32: liveins: $a0
-    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
-    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
-    ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
-    ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
-    ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
-    ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65280
-    ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
-    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
-    ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s32)
-    ; MIPS32: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
-    ; MIPS32: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
-    ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
-    ; MIPS32: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND1]]
-    ; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
-    ; MIPS32: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -252645136
-    ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR2]], [[C3]](s32)
-    ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C4]]
-    ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[OR2]], [[C4]]
-    ; MIPS32: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C3]](s32)
-    ; MIPS32: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[AND2]]
-    ; MIPS32: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
-    ; MIPS32: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 -858993460
-    ; MIPS32: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[OR3]], [[C5]](s32)
-    ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SHL3]], [[C6]]
-    ; MIPS32: [[AND5:%[0-9]+]]:_(s32) = G_AND [[OR3]], [[C6]]
-    ; MIPS32: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[C5]](s32)
-    ; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND4]]
-    ; MIPS32: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1431655766
-    ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32)
-    ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SHL4]], [[C8]]
-    ; MIPS32: [[AND7:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]]
-    ; MIPS32: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[C7]](s32)
-    ; MIPS32: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[AND6]]
-    ; MIPS32: $v0 = COPY [[OR5]](s32)
-    ; MIPS32: RetRA implicit $v0
-    ; MIPS32R2-LABEL: name: bitreverse_i32
-    ; MIPS32R2: liveins: $a0
-    ; MIPS32R2: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
-    ; MIPS32R2: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
-    ; MIPS32R2: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
-    ; MIPS32R2: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -252645136
-    ; MIPS32R2: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BSWAP]], [[C]](s32)
-    ; MIPS32R2: [[AND:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C1]]
-    ; MIPS32R2: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BSWAP]], [[C1]]
-    ; MIPS32R2: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C]](s32)
-    ; MIPS32R2: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[AND]]
-    ; MIPS32R2: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
-    ; MIPS32R2: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -858993460
-    ; MIPS32R2: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[OR]], [[C2]](s32)
-    ; MIPS32R2: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL1]], [[C3]]
-    ; MIPS32R2: [[AND3:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C3]]
-    ; MIPS32R2: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C2]](s32)
-    ; MIPS32R2: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[AND2]]
-    ; MIPS32R2: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; MIPS32R2: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1431655766
-    ; MIPS32R2: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C4]](s32)
-    ; MIPS32R2: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C5]]
-    ; MIPS32R2: [[AND5:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C5]]
-    ; MIPS32R2: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[C4]](s32)
-    ; MIPS32R2: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[AND4]]
-    ; MIPS32R2: $v0 = COPY [[OR2]](s32)
-    ; MIPS32R2: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = G_BITREVERSE %0
-    $v0 = COPY %1(s32)
-    RetRA implicit $v0
-
-...
----
-name:            bitreverse_i64
-alignment:       4
-tracksRegLiveness: true
-body:             |
-  bb.1.entry:
-    liveins: $a0, $a1
-
-    ; MIPS32-LABEL: name: bitreverse_i64
-    ; MIPS32: liveins: $a0, $a1
-    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
-    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
-    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
-    ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
-    ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
-    ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
-    ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65280
-    ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
-    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
-    ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s32)
-    ; MIPS32: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
-    ; MIPS32: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
-    ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
-    ; MIPS32: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND1]]
-    ; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
-    ; MIPS32: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -252645136
-    ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR2]], [[C3]](s32)
-    ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C4]]
-    ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[OR2]], [[C4]]
-    ; MIPS32: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C3]](s32)
-    ; MIPS32: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[AND2]]
-    ; MIPS32: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
-    ; MIPS32: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 -858993460
-    ; MIPS32: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[OR3]], [[C5]](s32)
-    ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SHL3]], [[C6]]
-    ; MIPS32: [[AND5:%[0-9]+]]:_(s32) = G_AND [[OR3]], [[C6]]
-    ; MIPS32: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[C5]](s32)
-    ; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND4]]
-    ; MIPS32: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1431655766
-    ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32)
-    ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SHL4]], [[C8]]
-    ; MIPS32: [[AND7:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]]
-    ; MIPS32: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[C7]](s32)
-    ; MIPS32: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[AND6]]
-    ; MIPS32: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
-    ; MIPS32: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
-    ; MIPS32: [[OR6:%[0-9]+]]:_(s32) = G_OR [[LSHR5]], [[SHL5]]
-    ; MIPS32: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
-    ; MIPS32: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C2]](s32)
-    ; MIPS32: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL6]]
-    ; MIPS32: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
-    ; MIPS32: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C1]]
-    ; MIPS32: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[AND9]]
-    ; MIPS32: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[OR8]], [[C3]](s32)
-    ; MIPS32: [[AND10:%[0-9]+]]:_(s32) = G_AND [[SHL7]], [[C4]]
-    ; MIPS32: [[AND11:%[0-9]+]]:_(s32) = G_AND [[OR8]], [[C4]]
-    ; MIPS32: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND11]], [[C3]](s32)
-    ; MIPS32: [[OR9:%[0-9]+]]:_(s32) = G_OR [[LSHR7]], [[AND10]]
-    ; MIPS32: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[OR9]], [[C5]](s32)
-    ; MIPS32: [[AND12:%[0-9]+]]:_(s32) = G_AND [[SHL8]], [[C6]]
-    ; MIPS32: [[AND13:%[0-9]+]]:_(s32) = G_AND [[OR9]], [[C6]]
-    ; MIPS32: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND13]], [[C5]](s32)
-    ; MIPS32: [[OR10:%[0-9]+]]:_(s32) = G_OR [[LSHR8]], [[AND12]]
-    ; MIPS32: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[OR10]], [[C7]](s32)
-    ; MIPS32: [[AND14:%[0-9]+]]:_(s32) = G_AND [[SHL9]], [[C8]]
-    ; MIPS32: [[AND15:%[0-9]+]]:_(s32) = G_AND [[OR10]], [[C8]]
-    ; MIPS32: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND15]], [[C7]](s32)
-    ; MIPS32: [[OR11:%[0-9]+]]:_(s32) = G_OR [[LSHR9]], [[AND14]]
-    ; MIPS32: $v0 = COPY [[OR5]](s32)
-    ; MIPS32: $v1 = COPY [[OR11]](s32)
-    ; MIPS32: RetRA implicit $v0, implicit $v1
-    ; MIPS32R2-LABEL: name: bitreverse_i64
-    ; MIPS32R2: liveins: $a0, $a1
-    ; MIPS32R2: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
-    ; MIPS32R2: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
-    ; MIPS32R2: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]]
-    ; MIPS32R2: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
-    ; MIPS32R2: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -252645136
-    ; MIPS32R2: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BSWAP]], [[C]](s32)
-    ; MIPS32R2: [[AND:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C1]]
-    ; MIPS32R2: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BSWAP]], [[C1]]
-    ; MIPS32R2: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C]](s32)
-    ; MIPS32R2: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[AND]]
-    ; MIPS32R2: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
-    ; MIPS32R2: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -858993460
-    ; MIPS32R2: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[OR]], [[C2]](s32)
-    ; MIPS32R2: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL1]], [[C3]]
-    ; MIPS32R2: [[AND3:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C3]]
-    ; MIPS32R2: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C2]](s32)
-    ; MIPS32R2: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[AND2]]
-    ; MIPS32R2: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; MIPS32R2: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1431655766
-    ; MIPS32R2: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C4]](s32)
-    ; MIPS32R2: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C5]]
-    ; MIPS32R2: [[AND5:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C5]]
-    ; MIPS32R2: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[C4]](s32)
-    ; MIPS32R2: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[AND4]]
-    ; MIPS32R2: [[BSWAP1:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
-    ; MIPS32R2: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[BSWAP1]], [[C]](s32)
-    ; MIPS32R2: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SHL3]], [[C1]]
-    ; MIPS32R2: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BSWAP1]], [[C1]]
-    ; MIPS32R2: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[C]](s32)
-    ; MIPS32R2: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND6]]
-    ; MIPS32R2: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR3]], [[C2]](s32)
-    ; MIPS32R2: [[AND8:%[0-9]+]]:_(s32) = G_AND [[SHL4]], [[C3]]
-    ; MIPS32R2: [[AND9:%[0-9]+]]:_(s32) = G_AND [[OR3]], [[C3]]
-    ; MIPS32R2: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[C2]](s32)
-    ; MIPS32R2: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[AND8]]
-    ; MIPS32R2: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C4]](s32)
-    ; MIPS32R2: [[AND10:%[0-9]+]]:_(s32) = G_AND [[SHL5]], [[C5]]
-    ; MIPS32R2: [[AND11:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C5]]
-    ; MIPS32R2: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND11]], [[C4]](s32)
-    ; MIPS32R2: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR5]], [[AND10]]
-    ; MIPS32R2: $v0 = COPY [[OR2]](s32)
-    ; MIPS32R2: $v1 = COPY [[OR5]](s32)
-    ; MIPS32R2: RetRA implicit $v0, implicit $v1
-    %1:_(s32) = COPY $a0
-    %2:_(s32) = COPY $a1
-    %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
-    %3:_(s64) = G_BITREVERSE %0
-    %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)
-    $v0 = COPY %4(s32)
-    $v1 = COPY %5(s32)
-    RetRA implicit $v0, implicit $v1
-
-...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitreverse.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitreverse.ll
deleted file mode 100644
index 845d84d7551..00000000000
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitreverse.ll
+++ /dev/null
@@ -1,184 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mattr=+mips32r2 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32R2
-
-declare i32 @llvm.bitreverse.i32(i32)
-define i32 @bitreverse_i32(i32 signext %a) {
-; MIPS32-LABEL: bitreverse_i32:
-; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    sll $1, $4, 24
-; MIPS32-NEXT:    srl $2, $4, 24
-; MIPS32-NEXT:    or $1, $2, $1
-; MIPS32-NEXT:    andi $2, $4, 65280
-; MIPS32-NEXT:    sll $2, $2, 8
-; MIPS32-NEXT:    or $1, $1, $2
-; MIPS32-NEXT:    srl $2, $4, 8
-; MIPS32-NEXT:    andi $2, $2, 65280
-; MIPS32-NEXT:    or $1, $1, $2
-; MIPS32-NEXT:    lui $2, 61680
-; MIPS32-NEXT:    ori $2, $2, 61680
-; MIPS32-NEXT:    sll $3, $1, 4
-; MIPS32-NEXT:    and $3, $3, $2
-; MIPS32-NEXT:    and $1, $1, $2
-; MIPS32-NEXT:    srl $1, $1, 4
-; MIPS32-NEXT:    or $1, $1, $3
-; MIPS32-NEXT:    lui $2, 52428
-; MIPS32-NEXT:    ori $2, $2, 52428
-; MIPS32-NEXT:    sll $3, $1, 2
-; MIPS32-NEXT:    and $3, $3, $2
-; MIPS32-NEXT:    and $1, $1, $2
-; MIPS32-NEXT:    srl $1, $1, 2
-; MIPS32-NEXT:    or $1, $1, $3
-; MIPS32-NEXT:    lui $2, 43690
-; MIPS32-NEXT:    ori $2, $2, 43690
-; MIPS32-NEXT:    sll $3, $1, 1
-; MIPS32-NEXT:    and $3, $3, $2
-; MIPS32-NEXT:    and $1, $1, $2
-; MIPS32-NEXT:    srl $1, $1, 1
-; MIPS32-NEXT:    or $2, $1, $3
-; MIPS32-NEXT:    jr $ra
-; MIPS32-NEXT:    nop
-;
-; MIPS32R2-LABEL: bitreverse_i32:
-; MIPS32R2:       # %bb.0: # %entry
-; MIPS32R2-NEXT:    wsbh $1, $4
-; MIPS32R2-NEXT:    rotr $1, $1, 16
-; MIPS32R2-NEXT:    lui $2, 61680
-; MIPS32R2-NEXT:    ori $2, $2, 61680
-; MIPS32R2-NEXT:    sll $3, $1, 4
-; MIPS32R2-NEXT:    and $3, $3, $2
-; MIPS32R2-NEXT:    and $1, $1, $2
-; MIPS32R2-NEXT:    srl $1, $1, 4
-; MIPS32R2-NEXT:    or $1, $1, $3
-; MIPS32R2-NEXT:    lui $2, 52428
-; MIPS32R2-NEXT:    ori $2, $2, 52428
-; MIPS32R2-NEXT:    sll $3, $1, 2
-; MIPS32R2-NEXT:    and $3, $3, $2
-; MIPS32R2-NEXT:    and $1, $1, $2
-; MIPS32R2-NEXT:    srl $1, $1, 2
-; MIPS32R2-NEXT:    or $1, $1, $3
-; MIPS32R2-NEXT:    lui $2, 43690
-; MIPS32R2-NEXT:    ori $2, $2, 43690
-; MIPS32R2-NEXT:    sll $3, $1, 1
-; MIPS32R2-NEXT:    and $3, $3, $2
-; MIPS32R2-NEXT:    and $1, $1, $2
-; MIPS32R2-NEXT:    srl $1, $1, 1
-; MIPS32R2-NEXT:    or $2, $1, $3
-; MIPS32R2-NEXT:    jr $ra
-; MIPS32R2-NEXT:    nop
-entry:
-  %0 = call i32 @llvm.bitreverse.i32(i32 %a)
-  ret i32 %0
-}
-
-declare i64 @llvm.bitreverse.i64(i64)
-define i64 @bitreverse_i64(i64 signext %a) {
-; MIPS32-LABEL: bitreverse_i64:
-; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    sll $1, $5, 24
-; MIPS32-NEXT:    srl $2, $5, 24
-; MIPS32-NEXT:    or $1, $2, $1
-; MIPS32-NEXT:    andi $2, $5, 65280
-; MIPS32-NEXT:    sll $2, $2, 8
-; MIPS32-NEXT:    or $1, $1, $2
-; MIPS32-NEXT:    srl $2, $5, 8
-; MIPS32-NEXT:    andi $2, $2, 65280
-; MIPS32-NEXT:    or $1, $1, $2
-; MIPS32-NEXT:    lui $2, 61680
-; MIPS32-NEXT:    ori $2, $2, 61680
-; MIPS32-NEXT:    sll $3, $1, 4
-; MIPS32-NEXT:    and $3, $3, $2
-; MIPS32-NEXT:    and $1, $1, $2
-; MIPS32-NEXT:    srl $1, $1, 4
-; MIPS32-NEXT:    or $1, $1, $3
-; MIPS32-NEXT:    lui $3, 52428
-; MIPS32-NEXT:    ori $3, $3, 52428
-; MIPS32-NEXT:    sll $5, $1, 2
-; MIPS32-NEXT:    and $5, $5, $3
-; MIPS32-NEXT:    and $1, $1, $3
-; MIPS32-NEXT:    srl $1, $1, 2
-; MIPS32-NEXT:    or $1, $1, $5
-; MIPS32-NEXT:    lui $5, 43690
-; MIPS32-NEXT:    ori $5, $5, 43690
-; MIPS32-NEXT:    sll $6, $1, 1
-; MIPS32-NEXT:    and $6, $6, $5
-; MIPS32-NEXT:    and $1, $1, $5
-; MIPS32-NEXT:    srl $1, $1, 1
-; MIPS32-NEXT:    or $1, $1, $6
-; MIPS32-NEXT:    sll $6, $4, 24
-; MIPS32-NEXT:    srl $7, $4, 24
-; MIPS32-NEXT:    or $6, $7, $6
-; MIPS32-NEXT:    andi $7, $4, 65280
-; MIPS32-NEXT:    sll $7, $7, 8
-; MIPS32-NEXT:    or $6, $6, $7
-; MIPS32-NEXT:    srl $4, $4, 8
-; MIPS32-NEXT:    andi $4, $4, 65280
-; MIPS32-NEXT:    or $4, $6, $4
-; MIPS32-NEXT:    sll $6, $4, 4
-; MIPS32-NEXT:    and $6, $6, $2
-; MIPS32-NEXT:    and $2, $4, $2
-; MIPS32-NEXT:    srl $2, $2, 4
-; MIPS32-NEXT:    or $2, $2, $6
-; MIPS32-NEXT:    sll $4, $2, 2
-; MIPS32-NEXT:    and $4, $4, $3
-; MIPS32-NEXT:    and $2, $2, $3
-; MIPS32-NEXT:    srl $2, $2, 2
-; MIPS32-NEXT:    or $2, $2, $4
-; MIPS32-NEXT:    sll $3, $2, 1
-; MIPS32-NEXT:    and $3, $3, $5
-; MIPS32-NEXT:    and $2, $2, $5
-; MIPS32-NEXT:    srl $2, $2, 1
-; MIPS32-NEXT:    or $3, $2, $3
-; MIPS32-NEXT:    move $2, $1
-; MIPS32-NEXT:    jr $ra
-; MIPS32-NEXT:    nop
-;
-; MIPS32R2-LABEL: bitreverse_i64:
-; MIPS32R2:       # %bb.0: # %entry
-; MIPS32R2-NEXT:    wsbh $1, $5
-; MIPS32R2-NEXT:    rotr $1, $1, 16
-; MIPS32R2-NEXT:    lui $2, 61680
-; MIPS32R2-NEXT:    ori $2, $2, 61680
-; MIPS32R2-NEXT:    sll $3, $1, 4
-; MIPS32R2-NEXT:    and $3, $3, $2
-; MIPS32R2-NEXT:    and $1, $1, $2
-; MIPS32R2-NEXT:    srl $1, $1, 4
-; MIPS32R2-NEXT:    or $1, $1, $3
-; MIPS32R2-NEXT:    lui $3, 52428
-; MIPS32R2-NEXT:    ori $3, $3, 52428
-; MIPS32R2-NEXT:    sll $5, $1, 2
-; MIPS32R2-NEXT:    and $5, $5, $3
-; MIPS32R2-NEXT:    and $1, $1, $3
-; MIPS32R2-NEXT:    srl $1, $1, 2
-; MIPS32R2-NEXT:    or $1, $1, $5
-; MIPS32R2-NEXT:    lui $5, 43690
-; MIPS32R2-NEXT:    ori $5, $5, 43690
-; MIPS32R2-NEXT:    sll $6, $1, 1
-; MIPS32R2-NEXT:    and $6, $6, $5
-; MIPS32R2-NEXT:    and $1, $1, $5
-; MIPS32R2-NEXT:    srl $1, $1, 1
-; MIPS32R2-NEXT:    or $1, $1, $6
-; MIPS32R2-NEXT:    wsbh $4, $4
-; MIPS32R2-NEXT:    rotr $4, $4, 16
-; MIPS32R2-NEXT:    sll $6, $4, 4
-; MIPS32R2-NEXT:    and $6, $6, $2
-; MIPS32R2-NEXT:    and $2, $4, $2
-; MIPS32R2-NEXT:    srl $2, $2, 4
-; MIPS32R2-NEXT:    or $2, $2, $6
-; MIPS32R2-NEXT:    sll $4, $2, 2
-; MIPS32R2-NEXT:    and $4, $4, $3
-; MIPS32R2-NEXT:    and $2, $2, $3
-; MIPS32R2-NEXT:    srl $2, $2, 2
-; MIPS32R2-NEXT:    or $2, $2, $4
-; MIPS32R2-NEXT:    sll $3, $2, 1
-; MIPS32R2-NEXT:    and $3, $3, $5
-; MIPS32R2-NEXT:    and $2, $2, $5
-; MIPS32R2-NEXT:    srl $2, $2, 1
-; MIPS32R2-NEXT:    or $3, $2, $3
-; MIPS32R2-NEXT:    move $2, $1
-; MIPS32R2-NEXT:    jr $ra
-; MIPS32R2-NEXT:    nop
-entry:
-  %0 = call i64 @llvm.bitreverse.i64(i64 %a)
-  ret i64 %0
-}