[globalisel] Rename G_GEP to G_PTR_ADD

Summary:
G_GEP is rather poorly named. It's a simple pointer+scalar addition and
doesn't support any of the complexities of getelementptr. I therefore
propose that we rename it. There's a G_PTR_MASK so let's follow that
convention and go with G_PTR_ADD

Reviewers: volkan, aditya_nandakumar, bogner, rovka, arsenm

Subscribers: sdardis, jvesely, wdng, nhaehnle, hiraditya, jrtc27, atanasyan, arphaman, Petar.Avramovic, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69734

17 files changed, 55 insertions, 55 deletions

diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_store_fold.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_store_fold.mir
index d455825ba7f..de487f9aea5 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_store_fold.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_store_fold.mir
@@ -30,7 +30,7 @@ body:             |
     ; MIPS32: RetRA implicit $v0
     %0:gprb(p0) = COPY $a0
     %1:gprb(s32) = G_CONSTANT i32 32767
-    %2:gprb(p0) = G_GEP %0, %1(s32)
+    %2:gprb(p0) = G_PTR_ADD %0, %1(s32)
     %4:gprb(s32) = G_ZEXTLOAD %2(p0) :: (load 1)
     $v0 = COPY %4(s32)
     RetRA implicit $v0
@@ -55,7 +55,7 @@ body:             |
     %2:gprb(s32) = COPY $a0
     %1:gprb(p0) = COPY $a1
     %3:gprb(s32) = G_CONSTANT i32 -32768
-    %4:gprb(p0) = G_GEP %1, %3(s32)
+    %4:gprb(p0) = G_PTR_ADD %1, %3(s32)
     %5:gprb(s32) = COPY %2(s32)
     G_STORE %5(s32), %4(p0) :: (store 1)
     RetRA
@@ -82,7 +82,7 @@ body:             |
     %2:gprb(s32) = COPY $a0
     %1:gprb(p0) = COPY $a1
     %3:gprb(s32) = G_CONSTANT i32 32768
-    %4:gprb(p0) = G_GEP %1, %3(s32)
+    %4:gprb(p0) = G_PTR_ADD %1, %3(s32)
     %5:gprb(s32) = COPY %2(s32)
     G_STORE %5(s32), %4(p0) :: (store 1)
     RetRA
@@ -109,7 +109,7 @@ body:             |
     ; MIPS32: RetRA implicit $v0
     %0:gprb(p0) = COPY $a0
     %1:gprb(s32) = G_CONSTANT i32 -32769
-    %2:gprb(p0) = G_GEP %0, %1(s32)
+    %2:gprb(p0) = G_PTR_ADD %0, %1(s32)
     %4:gprb(s32) = G_SEXTLOAD %2(p0) :: (load 1)
     $v0 = COPY %4(s32)
     RetRA implicit $v0
@@ -133,7 +133,7 @@ body:             |
     ; MIPS32: RetRA implicit $f0
     %0:gprb(p0) = COPY $a0
     %1:gprb(s32) = G_CONSTANT i32 40
-    %2:gprb(p0) = G_GEP %0, %1(s32)
+    %2:gprb(p0) = G_PTR_ADD %0, %1(s32)
     %3:fprb(s32) = G_LOAD %2(p0) :: (load 4)
     $f0 = COPY %3(s32)
     RetRA implicit $f0
@@ -158,7 +158,7 @@ body:             |
     %0:fprb(s64) = COPY $d6
     %1:gprb(p0) = COPY $a2
     %2:gprb(s32) = G_CONSTANT i32 -80
-    %3:gprb(p0) = G_GEP %1, %2(s32)
+    %3:gprb(p0) = G_PTR_ADD %1, %2(s32)
     G_STORE %0(s64), %3(p0) :: (store 8)
     RetRA
 
@@ -181,7 +181,7 @@ body:             |
     ; MIPS32: RetRA implicit $v0
     %0:gprb(p0) = COPY $a0
     %1:gprb(s32) = G_CONSTANT i32 -20
-    %2:gprb(p0) = G_GEP %0, %1(s32)
+    %2:gprb(p0) = G_PTR_ADD %0, %1(s32)
     %4:gprb(s32) = G_LOAD %2(p0) :: (load 2)
     $v0 = COPY %4(s32)
     RetRA implicit $v0
@@ -206,7 +206,7 @@ body:             |
     %0:gprb(s32) = COPY $a0
     %1:gprb(p0) = COPY $a1
     %2:gprb(s32) = G_CONSTANT i32 40
-    %3:gprb(p0) = G_GEP %1, %2(s32)
+    %3:gprb(p0) = G_PTR_ADD %1, %2(s32)
     G_STORE %0(s32), %3(p0) :: (store 4)
     RetRA
 
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/stack_args.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/stack_args.mir
index 8de38342397..cd9074d6d21 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/stack_args.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/stack_args.mir
@@ -51,7 +51,7 @@ body:             |
     $a3 = COPY %3(s32)
     %7:gprb(p0) = COPY $sp
     %8:gprb(s32) = G_CONSTANT i32 16
-    %9:gprb(p0) = G_GEP %7, %8(s32)
+    %9:gprb(p0) = G_PTR_ADD %7, %8(s32)
     G_STORE %4(s32), %9(p0) :: (store 4 into stack + 16, align 4)
     JAL @f, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
     %6:gprb(s32) = COPY $v0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/var_arg.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/var_arg.mir
index 9f07f742e97..a84137835be 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/var_arg.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/var_arg.mir
@@ -112,7 +112,7 @@ body:             |
     SW %19, %9(p0), 0 :: (store 4)
     %11:gprb(p0) = G_LOAD %9(p0) :: (load 4 from %ir.aq)
     %12:gprb(s32) = G_CONSTANT i32 4
-    %13:gprb(p0) = G_GEP %11, %12(s32)
+    %13:gprb(p0) = G_PTR_ADD %11, %12(s32)
     G_STORE %13(p0), %9(p0) :: (store 4 into %ir.aq)
     %14:gprb(p0) = G_LOAD %11(p0) :: (load 4 from %ir.2)
     G_STORE %14(p0), %10(p0) :: (store 4 into %ir.s)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/aggregate_struct_return.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/aggregate_struct_return.ll
index 16c6b3089fa..f6b034ea7f8 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/aggregate_struct_return.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/aggregate_struct_return.ll
@@ -11,11 +11,11 @@ define { float, float } @add_complex_float({ float, float }* %a, { float, float
   ; MIPS32:   [[COPY2:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
   ; MIPS32:   [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY2]](p0) :: (load 4 from %ir..realp)
   ; MIPS32:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
-  ; MIPS32:   [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s32)
+  ; MIPS32:   [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
   ; MIPS32:   [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[GEP]](p0) :: (load 4 from %ir..imagp)
   ; MIPS32:   [[COPY3:%[0-9]+]]:_(p0) = COPY [[COPY1]](p0)
   ; MIPS32:   [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[COPY3]](p0) :: (load 4 from %ir..realp1)
-  ; MIPS32:   [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C]](s32)
+  ; MIPS32:   [[GEP1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C]](s32)
   ; MIPS32:   [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[GEP1]](p0) :: (load 4 from %ir..imagp3)
   ; MIPS32:   [[FADD:%[0-9]+]]:_(s32) = G_FADD [[LOAD]], [[LOAD2]]
   ; MIPS32:   [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[LOAD1]], [[LOAD3]]
@@ -48,11 +48,11 @@ define { double, double } @add_complex_double({ double, double }* %a, { double,
   ; MIPS32:   [[COPY2:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
   ; MIPS32:   [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY2]](p0) :: (load 8 from %ir..realp)
   ; MIPS32:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
-  ; MIPS32:   [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s32)
+  ; MIPS32:   [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
   ; MIPS32:   [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[GEP]](p0) :: (load 8 from %ir..imagp)
   ; MIPS32:   [[COPY3:%[0-9]+]]:_(p0) = COPY [[COPY1]](p0)
   ; MIPS32:   [[LOAD2:%[0-9]+]]:_(s64) = G_LOAD [[COPY3]](p0) :: (load 8 from %ir..realp1)
-  ; MIPS32:   [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C]](s32)
+  ; MIPS32:   [[GEP1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C]](s32)
   ; MIPS32:   [[LOAD3:%[0-9]+]]:_(s64) = G_LOAD [[GEP1]](p0) :: (load 8 from %ir..imagp3)
   ; MIPS32:   [[FADD:%[0-9]+]]:_(s64) = G_FADD [[LOAD]], [[LOAD2]]
   ; MIPS32:   [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[LOAD1]], [[LOAD3]]
@@ -88,7 +88,7 @@ define void @call_ret_complex_float({ float, float }* %z) {
   ; MIPS32:   ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
   ; MIPS32:   [[COPY3:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
   ; MIPS32:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
-  ; MIPS32:   [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s32)
+  ; MIPS32:   [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
   ; MIPS32:   G_STORE [[COPY1]](s32), [[COPY3]](p0) :: (store 4 into %ir..realp)
   ; MIPS32:   G_STORE [[COPY2]](s32), [[GEP]](p0) :: (store 4 into %ir..imagp)
   ; MIPS32:   RetRA
@@ -116,7 +116,7 @@ define void @call_ret_complex_double({ double, double }* %z) {
   ; MIPS32:   ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
   ; MIPS32:   [[COPY3:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
   ; MIPS32:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
-  ; MIPS32:   [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s32)
+  ; MIPS32:   [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
   ; MIPS32:   G_STORE [[COPY1]](s64), [[COPY3]](p0) :: (store 8 into %ir..realp)
   ; MIPS32:   G_STORE [[COPY2]](s64), [[GEP]](p0) :: (store 8 into %ir..imagp)
   ; MIPS32:   RetRA
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/extend_args.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/extend_args.ll
index a1743c4c7c8..2d0a26eff65 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/extend_args.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/extend_args.ll
@@ -63,7 +63,7 @@ define signext i8 @call_sext_stack_arg_i8(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i8
   ; MIPS32:   $a3 = COPY [[COPY3]](s32)
   ; MIPS32:   [[COPY4:%[0-9]+]]:_(p0) = COPY $sp
   ; MIPS32:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
-  ; MIPS32:   [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY4]], [[C]](s32)
+  ; MIPS32:   [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY4]], [[C]](s32)
   ; MIPS32:   [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s8)
   ; MIPS32:   G_STORE [[SEXT]](s32), [[GEP]](p0) :: (store 4 into stack + 16, align 8)
   ; MIPS32:   JAL @sext_stack_arg_i8, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
@@ -96,7 +96,7 @@ define zeroext i8 @call_zext_stack_arg_i8(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i8
   ; MIPS32:   $a3 = COPY [[COPY3]](s32)
   ; MIPS32:   [[COPY4:%[0-9]+]]:_(p0) = COPY $sp
   ; MIPS32:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
-  ; MIPS32:   [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY4]], [[C]](s32)
+  ; MIPS32:   [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY4]], [[C]](s32)
   ; MIPS32:   [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s8)
   ; MIPS32:   G_STORE [[ZEXT]](s32), [[GEP]](p0) :: (store 4 into stack + 16, align 8)
   ; MIPS32:   JAL @zext_stack_arg_i8, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
@@ -129,7 +129,7 @@ define i8 @call_aext_stack_arg_i8(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i8 %a) {
   ; MIPS32:   $a3 = COPY [[COPY3]](s32)
   ; MIPS32:   [[COPY4:%[0-9]+]]:_(p0) = COPY $sp
   ; MIPS32:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
-  ; MIPS32:   [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY4]], [[C]](s32)
+  ; MIPS32:   [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY4]], [[C]](s32)
   ; MIPS32:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
   ; MIPS32:   G_STORE [[ANYEXT]](s32), [[GEP]](p0) :: (store 4 into stack + 16, align 8)
   ; MIPS32:   JAL @aext_stack_arg_i8, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
@@ -206,7 +206,7 @@ define signext i16 @call_sext_stack_arg_i16(i32 %x1, i32 %x2, i32 %x3, i32 %x4,
   ; MIPS32:   $a3 = COPY [[COPY3]](s32)
   ; MIPS32:   [[COPY4:%[0-9]+]]:_(p0) = COPY $sp
   ; MIPS32:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
-  ; MIPS32:   [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY4]], [[C]](s32)
+  ; MIPS32:   [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY4]], [[C]](s32)
   ; MIPS32:   [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s16)
   ; MIPS32:   G_STORE [[SEXT]](s32), [[GEP]](p0) :: (store 4 into stack + 16, align 8)
   ; MIPS32:   JAL @sext_stack_arg_i16, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
@@ -239,7 +239,7 @@ define zeroext i16 @call_zext_stack_arg_i16(i32 %x1, i32 %x2, i32 %x3, i32 %x4,
   ; MIPS32:   $a3 = COPY [[COPY3]](s32)
   ; MIPS32:   [[COPY4:%[0-9]+]]:_(p0) = COPY $sp
   ; MIPS32:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
-  ; MIPS32:   [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY4]], [[C]](s32)
+  ; MIPS32:   [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY4]], [[C]](s32)
   ; MIPS32:   [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)
   ; MIPS32:   G_STORE [[ZEXT]](s32), [[GEP]](p0) :: (store 4 into stack + 16, align 8)
   ; MIPS32:   JAL @zext_stack_arg_i16, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
@@ -272,7 +272,7 @@ define i16 @call_aext_stack_arg_i16(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i16 %a)
   ; MIPS32:   $a3 = COPY [[COPY3]](s32)
   ; MIPS32:   [[COPY4:%[0-9]+]]:_(p0) = COPY $sp
   ; MIPS32:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
-  ; MIPS32:   [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY4]], [[C]](s32)
+  ; MIPS32:   [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY4]], [[C]](s32)
   ; MIPS32:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
   ; MIPS32:   G_STORE [[ANYEXT]](s32), [[GEP]](p0) :: (store 4 into stack + 16, align 8)
   ; MIPS32:   JAL @aext_stack_arg_i16, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/sret_pointer.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/sret_pointer.ll
index aab38d7042e..7d37239c4ba 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/sret_pointer.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/sret_pointer.ll
@@ -12,7 +12,7 @@ define void @ZeroInit(%struct.S* noalias sret %agg.result) {
   ; MIPS32:   [[COPY1:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
   ; MIPS32:   G_STORE [[C]](s32), [[COPY1]](p0) :: (store 4 into %ir.x)
   ; MIPS32:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
-  ; MIPS32:   [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C1]](s32)
+  ; MIPS32:   [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s32)
   ; MIPS32:   G_STORE [[C]](s32), [[GEP]](p0) :: (store 4 into %ir.y)
   ; MIPS32:   RetRA
 entry:
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/stack_args.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/stack_args.ll
index 37d75bc7f7d..e33991c8454 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/stack_args.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/stack_args.ll
@@ -20,7 +20,7 @@ define  i32 @g(i32  %x1, i32 %x2, i32 %x3, i32 %x4, i32 %x5){
   ; MIPS32:   $a3 = COPY [[COPY3]](s32)
   ; MIPS32:   [[COPY4:%[0-9]+]]:_(p0) = COPY $sp
   ; MIPS32:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
-  ; MIPS32:   [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY4]], [[C]](s32)
+  ; MIPS32:   [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY4]], [[C]](s32)
   ; MIPS32:   G_STORE [[LOAD]](s32), [[GEP]](p0) :: (store 4 into stack + 16, align 8)
   ; MIPS32:   JAL @f, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
   ; MIPS32:   [[COPY5:%[0-9]+]]:_(s32) = COPY $v0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll
index b3b68175ad0..8938c812889 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll
@@ -31,7 +31,7 @@ define void @testVaCopyArg(i8* %fmt, ...) {
   ; MIPS32:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.va_copy), [[FRAME_INDEX5]](p0), [[FRAME_INDEX4]](p0)
   ; MIPS32:   [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX5]](p0) :: (load 4 from %ir.aq)
   ; MIPS32:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
-  ; MIPS32:   [[GEP:%[0-9]+]]:_(p0) = G_GEP [[LOAD]], [[C]](s32)
+  ; MIPS32:   [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[LOAD]], [[C]](s32)
   ; MIPS32:   G_STORE [[GEP]](p0), [[FRAME_INDEX5]](p0) :: (store 4 into %ir.aq)
   ; MIPS32:   [[LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[LOAD]](p0) :: (load 4 from %ir.2)
   ; MIPS32:   G_STORE [[LOAD1]](p0), [[FRAME_INDEX6]](p0) :: (store 4 into %ir.s)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/dyn_stackalloc.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/dyn_stackalloc.mir
index 6724428dfaa..773933018ed 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/dyn_stackalloc.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/dyn_stackalloc.mir
@@ -52,7 +52,7 @@ body:             |
     ; MIPS32: $a2 = COPY [[COPY1]](s32)
     ; MIPS32: JAL &memset, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2
     ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
-    ; MIPS32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY3]], [[COPY1]](s32)
+    ; MIPS32: [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY3]], [[COPY1]](s32)
     ; MIPS32: [[COPY5:%[0-9]+]]:_(p0) = COPY [[GEP]](p0)
     ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
     ; MIPS32: G_STORE [[COPY6]](s32), [[COPY5]](p0) :: (store 1 into %ir.arrayidx)
@@ -74,7 +74,7 @@ body:             |
     %9:_(s32) = G_AND %7, %8
     %10:_(p0) = G_DYN_STACKALLOC %9(s32), 0
     G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memset), %10(p0), %0(s8), %1(s32), 0 :: (store 1 into %ir.vla)
-    %11:_(p0) = G_GEP %10, %1(s32)
+    %11:_(p0) = G_PTR_ADD %10, %1(s32)
     %12:_(p0) = COPY %11(p0)
     G_STORE %13(s8), %12(p0) :: (store 1 into %ir.arrayidx)
     ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/stack_args.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/stack_args.mir
index e601e8ab366..f389bbc5521 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/stack_args.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/stack_args.mir
@@ -31,7 +31,7 @@ body:             |
     ; MIPS32: $a3 = COPY [[COPY3]](s32)
     ; MIPS32: [[COPY4:%[0-9]+]]:_(p0) = COPY $sp
     ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
-    ; MIPS32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY4]], [[C]](s32)
+    ; MIPS32: [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY4]], [[C]](s32)
     ; MIPS32: G_STORE [[LOAD]](s32), [[GEP]](p0) :: (store 4 into stack + 16)
     ; MIPS32: JAL @f, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
     ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $v0
@@ -51,7 +51,7 @@ body:             |
     $a3 = COPY %3(s32)
     %7:_(p0) = COPY $sp
     %8:_(s32) = G_CONSTANT i32 16
-    %9:_(p0) = G_GEP %7, %8(s32)
+    %9:_(p0) = G_PTR_ADD %7, %8(s32)
     G_STORE %4(s32), %9(p0) :: (store 4 into stack + 16, align 4)
     JAL @f, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
     %6:_(s32) = COPY $v0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/var_arg.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/var_arg.mir
index 98a92d773c1..871e9ce673f 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/var_arg.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/var_arg.mir
@@ -76,7 +76,7 @@ body:             |
     ; MIPS32: G_STORE [[LOAD]](p0), [[FRAME_INDEX5]](p0) :: (store 4)
     ; MIPS32: [[LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX5]](p0) :: (load 4 from %ir.aq)
     ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
-    ; MIPS32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[LOAD1]], [[C]](s32)
+    ; MIPS32: [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[LOAD1]], [[C]](s32)
     ; MIPS32: G_STORE [[GEP]](p0), [[FRAME_INDEX5]](p0) :: (store 4 into %ir.aq)
     ; MIPS32: [[LOAD2:%[0-9]+]]:_(p0) = G_LOAD [[LOAD1]](p0) :: (load 4 from %ir.2)
     ; MIPS32: G_STORE [[LOAD2]](p0), [[FRAME_INDEX6]](p0) :: (store 4 into %ir.s)
@@ -108,7 +108,7 @@ body:             |
     G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.va_copy), %9(p0), %8(p0)
     %11:_(p0) = G_LOAD %9(p0) :: (load 4 from %ir.aq)
     %12:_(s32) = G_CONSTANT i32 4
-    %13:_(p0) = G_GEP %11, %12(s32)
+    %13:_(p0) = G_PTR_ADD %11, %12(s32)
     G_STORE %13(p0), %9(p0) :: (store 4 into %ir.aq)
     %14:_(p0) = G_LOAD %11(p0) :: (load 4 from %ir.2)
     G_STORE %14(p0), %10(p0) :: (store 4 into %ir.s)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir
index 0b23b4442c4..92e963196dd 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir
@@ -45,7 +45,7 @@ body:             |
     ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
     ; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.ptr, align 8)
     ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 4
-    ; MIPS32: [[GEP:%[0-9]+]]:gprb(p0) = G_GEP [[COPY]], [[C]](s32)
+    ; MIPS32: [[GEP:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
     ; MIPS32: [[LOAD1:%[0-9]+]]:gprb(s32) = G_LOAD [[GEP]](p0) :: (load 4 from %ir.ptr + 4, align 8)
     ; MIPS32: $v0 = COPY [[LOAD]](s32)
     ; MIPS32: $v1 = COPY [[LOAD1]](s32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir
index e386efbf45b..ed11ba2ed65 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir
@@ -476,21 +476,21 @@ body:             |
   ; MIPS32:   successors: %bb.6(0x80000000)
   ; MIPS32:   [[LOAD3:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY3]](p0) :: (load 4 from %ir.a, align 8)
   ; MIPS32:   [[C4:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 4
-  ; MIPS32:   [[GEP:%[0-9]+]]:gprb(p0) = G_GEP [[COPY3]], [[C4]](s32)
+  ; MIPS32:   [[GEP:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[COPY3]], [[C4]](s32)
   ; MIPS32:   [[LOAD4:%[0-9]+]]:gprb(s32) = G_LOAD [[GEP]](p0) :: (load 4 from %ir.a + 4, align 8)
   ; MIPS32:   G_BR %bb.6
   ; MIPS32: bb.4.b.PHI.1.1:
   ; MIPS32:   successors: %bb.6(0x80000000)
   ; MIPS32:   [[LOAD5:%[0-9]+]]:gprb(s32) = G_LOAD [[LOAD]](p0) :: (load 4 from %ir.b, align 8)
   ; MIPS32:   [[C5:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 4
-  ; MIPS32:   [[GEP1:%[0-9]+]]:gprb(p0) = G_GEP [[LOAD]], [[C5]](s32)
+  ; MIPS32:   [[GEP1:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[LOAD]], [[C5]](s32)
   ; MIPS32:   [[LOAD6:%[0-9]+]]:gprb(s32) = G_LOAD [[GEP1]](p0) :: (load 4 from %ir.b + 4, align 8)
   ; MIPS32:   G_BR %bb.6
   ; MIPS32: bb.5.b.PHI.1.2:
   ; MIPS32:   successors: %bb.6(0x80000000)
   ; MIPS32:   [[LOAD7:%[0-9]+]]:gprb(s32) = G_LOAD [[LOAD1]](p0) :: (load 4 from %ir.c, align 8)
   ; MIPS32:   [[C6:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 4
-  ; MIPS32:   [[GEP2:%[0-9]+]]:gprb(p0) = G_GEP [[LOAD1]], [[C6]](s32)
+  ; MIPS32:   [[GEP2:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[LOAD1]], [[C6]](s32)
   ; MIPS32:   [[LOAD8:%[0-9]+]]:gprb(s32) = G_LOAD [[GEP2]](p0) :: (load 4 from %ir.c + 4, align 8)
   ; MIPS32: bb.6.b.PHI.1:
   ; MIPS32:   successors: %bb.7(0x40000000), %bb.13(0x40000000)
@@ -504,7 +504,7 @@ body:             |
   ; MIPS32: bb.7.b.PHI.1.end:
   ; MIPS32:   G_STORE [[PHI]](s32), [[LOAD2]](p0) :: (store 4 into %ir.result, align 8)
   ; MIPS32:   [[C8:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 4
-  ; MIPS32:   [[GEP3:%[0-9]+]]:gprb(p0) = G_GEP [[LOAD2]], [[C8]](s32)
+  ; MIPS32:   [[GEP3:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[LOAD2]], [[C8]](s32)
   ; MIPS32:   G_STORE [[PHI1]](s32), [[GEP3]](p0) :: (store 4 into %ir.result + 4, align 8)
   ; MIPS32:   RetRA
   ; MIPS32: bb.8.pre.PHI.2:
@@ -518,14 +518,14 @@ body:             |
   ; MIPS32:   successors: %bb.11(0x80000000)
   ; MIPS32:   [[LOAD9:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY3]](p0) :: (load 4 from %ir.a, align 8)
   ; MIPS32:   [[C10:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 4
-  ; MIPS32:   [[GEP4:%[0-9]+]]:gprb(p0) = G_GEP [[COPY3]], [[C10]](s32)
+  ; MIPS32:   [[GEP4:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[COPY3]], [[C10]](s32)
   ; MIPS32:   [[LOAD10:%[0-9]+]]:gprb(s32) = G_LOAD [[GEP4]](p0) :: (load 4 from %ir.a + 4, align 8)
   ; MIPS32:   G_BR %bb.11
   ; MIPS32: bb.10.b.PHI.2.1:
   ; MIPS32:   successors: %bb.11(0x80000000)
   ; MIPS32:   [[LOAD11:%[0-9]+]]:gprb(s32) = G_LOAD [[LOAD]](p0) :: (load 4 from %ir.b, align 8)
   ; MIPS32:   [[C11:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 4
-  ; MIPS32:   [[GEP5:%[0-9]+]]:gprb(p0) = G_GEP [[LOAD]], [[C11]](s32)
+  ; MIPS32:   [[GEP5:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[LOAD]], [[C11]](s32)
   ; MIPS32:   [[LOAD12:%[0-9]+]]:gprb(s32) = G_LOAD [[GEP5]](p0) :: (load 4 from %ir.b + 4, align 8)
   ; MIPS32: bb.11.b.PHI.2:
   ; MIPS32:   successors: %bb.13(0x40000000), %bb.12(0x40000000)
@@ -538,7 +538,7 @@ body:             |
   ; MIPS32: bb.12.b.PHI.2.end:
   ; MIPS32:   G_STORE [[PHI2]](s32), [[LOAD2]](p0) :: (store 4 into %ir.result, align 8)
   ; MIPS32:   [[C13:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 4
-  ; MIPS32:   [[GEP6:%[0-9]+]]:gprb(p0) = G_GEP [[LOAD2]], [[C13]](s32)
+  ; MIPS32:   [[GEP6:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[LOAD2]], [[C13]](s32)
   ; MIPS32:   G_STORE [[PHI3]](s32), [[GEP6]](p0) :: (store 4 into %ir.result + 4, align 8)
   ; MIPS32:   RetRA
   ; MIPS32: bb.13.b.PHI.3:
@@ -557,11 +557,11 @@ body:             |
   ; MIPS32:   [[SELECT3:%[0-9]+]]:gprb(s32) = G_SELECT [[AND7]](s32), [[SELECT1]], [[PHI5]]
   ; MIPS32:   G_STORE [[SELECT2]](s32), [[LOAD2]](p0) :: (store 4 into %ir.result, align 8)
   ; MIPS32:   [[C15:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 4
-  ; MIPS32:   [[GEP7:%[0-9]+]]:gprb(p0) = G_GEP [[LOAD2]], [[C15]](s32)
+  ; MIPS32:   [[GEP7:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[LOAD2]], [[C15]](s32)
   ; MIPS32:   G_STORE [[SELECT3]](s32), [[GEP7]](p0) :: (store 4 into %ir.result + 4, align 8)
   ; MIPS32:   G_STORE [[PHI4]](s32), [[LOAD2]](p0) :: (store 4 into %ir.result, align 8)
   ; MIPS32:   [[C16:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 4
-  ; MIPS32:   [[GEP8:%[0-9]+]]:gprb(p0) = G_GEP [[LOAD2]], [[C16]](s32)
+  ; MIPS32:   [[GEP8:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[LOAD2]], [[C16]](s32)
   ; MIPS32:   G_STORE [[PHI5]](s32), [[GEP8]](p0) :: (store 4 into %ir.result + 4, align 8)
   ; MIPS32:   RetRA
   bb.1.entry:
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir
index e386efbf45b..ed11ba2ed65 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir
@@ -476,21 +476,21 @@ body:             |
   ; MIPS32:   successors: %bb.6(0x80000000)
   ; MIPS32:   [[LOAD3:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY3]](p0) :: (load 4 from %ir.a, align 8)
   ; MIPS32:   [[C4:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 4
-  ; MIPS32:   [[GEP:%[0-9]+]]:gprb(p0) = G_GEP [[COPY3]], [[C4]](s32)
+  ; MIPS32:   [[GEP:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[COPY3]], [[C4]](s32)
   ; MIPS32:   [[LOAD4:%[0-9]+]]:gprb(s32) = G_LOAD [[GEP]](p0) :: (load 4 from %ir.a + 4, align 8)
   ; MIPS32:   G_BR %bb.6
   ; MIPS32: bb.4.b.PHI.1.1:
   ; MIPS32:   successors: %bb.6(0x80000000)
   ; MIPS32:   [[LOAD5:%[0-9]+]]:gprb(s32) = G_LOAD [[LOAD]](p0) :: (load 4 from %ir.b, align 8)
   ; MIPS32:   [[C5:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 4
-  ; MIPS32:   [[GEP1:%[0-9]+]]:gprb(p0) = G_GEP [[LOAD]], [[C5]](s32)
+  ; MIPS32:   [[GEP1:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[LOAD]], [[C5]](s32)
   ; MIPS32:   [[LOAD6:%[0-9]+]]:gprb(s32) = G_LOAD [[GEP1]](p0) :: (load 4 from %ir.b + 4, align 8)
   ; MIPS32:   G_BR %bb.6
   ; MIPS32: bb.5.b.PHI.1.2:
   ; MIPS32:   successors: %bb.6(0x80000000)
   ; MIPS32:   [[LOAD7:%[0-9]+]]:gprb(s32) = G_LOAD [[LOAD1]](p0) :: (load 4 from %ir.c, align 8)
   ; MIPS32:   [[C6:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 4
-  ; MIPS32:   [[GEP2:%[0-9]+]]:gprb(p0) = G_GEP [[LOAD1]], [[C6]](s32)
+  ; MIPS32:   [[GEP2:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[LOAD1]], [[C6]](s32)
   ; MIPS32:   [[LOAD8:%[0-9]+]]:gprb(s32) = G_LOAD [[GEP2]](p0) :: (load 4 from %ir.c + 4, align 8)
   ; MIPS32: bb.6.b.PHI.1:
   ; MIPS32:   successors: %bb.7(0x40000000), %bb.13(0x40000000)
@@ -504,7 +504,7 @@ body:             |
   ; MIPS32: bb.7.b.PHI.1.end:
   ; MIPS32:   G_STORE [[PHI]](s32), [[LOAD2]](p0) :: (store 4 into %ir.result, align 8)
   ; MIPS32:   [[C8:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 4
-  ; MIPS32:   [[GEP3:%[0-9]+]]:gprb(p0) = G_GEP [[LOAD2]], [[C8]](s32)
+  ; MIPS32:   [[GEP3:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[LOAD2]], [[C8]](s32)
   ; MIPS32:   G_STORE [[PHI1]](s32), [[GEP3]](p0) :: (store 4 into %ir.result + 4, align 8)
   ; MIPS32:   RetRA
   ; MIPS32: bb.8.pre.PHI.2:
@@ -518,14 +518,14 @@ body:             |
   ; MIPS32:   successors: %bb.11(0x80000000)
   ; MIPS32:   [[LOAD9:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY3]](p0) :: (load 4 from %ir.a, align 8)
   ; MIPS32:   [[C10:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 4
-  ; MIPS32:   [[GEP4:%[0-9]+]]:gprb(p0) = G_GEP [[COPY3]], [[C10]](s32)
+  ; MIPS32:   [[GEP4:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[COPY3]], [[C10]](s32)
   ; MIPS32:   [[LOAD10:%[0-9]+]]:gprb(s32) = G_LOAD [[GEP4]](p0) :: (load 4 from %ir.a + 4, align 8)
   ; MIPS32:   G_BR %bb.11
   ; MIPS32: bb.10.b.PHI.2.1:
   ; MIPS32:   successors: %bb.11(0x80000000)
   ; MIPS32:   [[LOAD11:%[0-9]+]]:gprb(s32) = G_LOAD [[LOAD]](p0) :: (load 4 from %ir.b, align 8)
   ; MIPS32:   [[C11:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 4
-  ; MIPS32:   [[GEP5:%[0-9]+]]:gprb(p0) = G_GEP [[LOAD]], [[C11]](s32)
+  ; MIPS32:   [[GEP5:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[LOAD]], [[C11]](s32)
   ; MIPS32:   [[LOAD12:%[0-9]+]]:gprb(s32) = G_LOAD [[GEP5]](p0) :: (load 4 from %ir.b + 4, align 8)
   ; MIPS32: bb.11.b.PHI.2:
   ; MIPS32:   successors: %bb.13(0x40000000), %bb.12(0x40000000)
@@ -538,7 +538,7 @@ body:             |
   ; MIPS32: bb.12.b.PHI.2.end:
   ; MIPS32:   G_STORE [[PHI2]](s32), [[LOAD2]](p0) :: (store 4 into %ir.result, align 8)
   ; MIPS32:   [[C13:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 4
-  ; MIPS32:   [[GEP6:%[0-9]+]]:gprb(p0) = G_GEP [[LOAD2]], [[C13]](s32)
+  ; MIPS32:   [[GEP6:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[LOAD2]], [[C13]](s32)
   ; MIPS32:   G_STORE [[PHI3]](s32), [[GEP6]](p0) :: (store 4 into %ir.result + 4, align 8)
   ; MIPS32:   RetRA
   ; MIPS32: bb.13.b.PHI.3:
@@ -557,11 +557,11 @@ body:             |
   ; MIPS32:   [[SELECT3:%[0-9]+]]:gprb(s32) = G_SELECT [[AND7]](s32), [[SELECT1]], [[PHI5]]
   ; MIPS32:   G_STORE [[SELECT2]](s32), [[LOAD2]](p0) :: (store 4 into %ir.result, align 8)
   ; MIPS32:   [[C15:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 4
-  ; MIPS32:   [[GEP7:%[0-9]+]]:gprb(p0) = G_GEP [[LOAD2]], [[C15]](s32)
+  ; MIPS32:   [[GEP7:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[LOAD2]], [[C15]](s32)
   ; MIPS32:   G_STORE [[SELECT3]](s32), [[GEP7]](p0) :: (store 4 into %ir.result + 4, align 8)
   ; MIPS32:   G_STORE [[PHI4]](s32), [[LOAD2]](p0) :: (store 4 into %ir.result, align 8)
   ; MIPS32:   [[C16:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 4
-  ; MIPS32:   [[GEP8:%[0-9]+]]:gprb(p0) = G_GEP [[LOAD2]], [[C16]](s32)
+  ; MIPS32:   [[GEP8:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[LOAD2]], [[C16]](s32)
   ; MIPS32:   G_STORE [[PHI5]](s32), [[GEP8]](p0) :: (store 4 into %ir.result + 4, align 8)
   ; MIPS32:   RetRA
   bb.1.entry:
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir
index bdbd462b027..f8ba638aac6 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir
@@ -32,7 +32,7 @@ body:             |
     ; MIPS32: $a3 = COPY [[COPY3]](s32)
     ; MIPS32: [[COPY4:%[0-9]+]]:gprb(p0) = COPY $sp
     ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 16
-    ; MIPS32: [[GEP:%[0-9]+]]:gprb(p0) = G_GEP [[COPY4]], [[C]](s32)
+    ; MIPS32: [[GEP:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[COPY4]], [[C]](s32)
     ; MIPS32: G_STORE [[LOAD]](s32), [[GEP]](p0) :: (store 4 into stack + 16)
     ; MIPS32: JAL @f, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
     ; MIPS32: [[COPY5:%[0-9]+]]:gprb(s32) = COPY $v0
@@ -52,7 +52,7 @@ body:             |
     $a3 = COPY %3(s32)
     %7:_(p0) = COPY $sp
     %8:_(s32) = G_CONSTANT i32 16
-    %9:_(p0) = G_GEP %7, %8(s32)
+    %9:_(p0) = G_PTR_ADD %7, %8(s32)
     G_STORE %4(s32), %9(p0) :: (store 4 into stack + 16, align 4)
     JAL @f, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
     %6:_(s32) = COPY $v0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir
index b0d8b072d49..6d4ab7f1b34 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir
@@ -45,7 +45,7 @@ body:             |
     ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
     ; MIPS32: G_STORE [[COPY]](s32), [[COPY2]](p0) :: (store 4 into %ir.ptr, align 8)
     ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 4
-    ; MIPS32: [[GEP:%[0-9]+]]:gprb(p0) = G_GEP [[COPY2]], [[C]](s32)
+    ; MIPS32: [[GEP:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[COPY2]], [[C]](s32)
     ; MIPS32: G_STORE [[COPY1]](s32), [[GEP]](p0) :: (store 4 into %ir.ptr + 4, align 8)
     ; MIPS32: RetRA
     %2:_(s32) = COPY $a0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/var_arg.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/var_arg.mir
index d249396854d..903a755b473 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/var_arg.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/var_arg.mir
@@ -77,7 +77,7 @@ body:             |
     ; MIPS32: SW [[LW]], [[FRAME_INDEX5]](p0), 0 :: (store 4)
     ; MIPS32: [[LOAD:%[0-9]+]]:gprb(p0) = G_LOAD [[FRAME_INDEX5]](p0) :: (load 4 from %ir.aq)
     ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 4
-    ; MIPS32: [[GEP:%[0-9]+]]:gprb(p0) = G_GEP [[LOAD]], [[C]](s32)
+    ; MIPS32: [[GEP:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[LOAD]], [[C]](s32)
     ; MIPS32: G_STORE [[GEP]](p0), [[FRAME_INDEX5]](p0) :: (store 4 into %ir.aq)
     ; MIPS32: [[LOAD1:%[0-9]+]]:gprb(p0) = G_LOAD [[LOAD]](p0) :: (load 4 from %ir.2)
     ; MIPS32: G_STORE [[LOAD1]](p0), [[FRAME_INDEX6]](p0) :: (store 4 into %ir.s)
@@ -110,7 +110,7 @@ body:             |
     SW %19, %9(p0), 0 :: (store 4)
     %11:_(p0) = G_LOAD %9(p0) :: (load 4 from %ir.aq)
     %12:_(s32) = G_CONSTANT i32 4
-    %13:_(p0) = G_GEP %11, %12(s32)
+    %13:_(p0) = G_PTR_ADD %11, %12(s32)
     G_STORE %13(p0), %9(p0) :: (store 4 into %ir.aq)
     %14:_(p0) = G_LOAD %11(p0) :: (load 4 from %ir.2)
     G_STORE %14(p0), %10(p0) :: (store 4 into %ir.s)