[MIPS GlobalISel] Add MSA registers to fprb. Select vector load, store

Add vector MSA register classes to fprb, they are 128 bit wide.
MSA instructions use the same registers for both integer and floating
point operations. Therefore we only need to check for vector element
size during legalization or instruction selection.

Add helper function in MipsLegalizerInfo and switch to legalIf
LegalizeRuleSet to keep legalization rules compact since they depend
on MipsSubtarget and presence of MSA.
fprb is assigned to all vector operands.
Move selectLoadStoreOpCode to MipsInstructionSelector in order to
reduce number of arguments.

Differential Revision: https://reviews.llvm.org/D68867

llvm-svn: 374872

4 files changed, 530 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_store_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_store_vec.mir
new file mode 100644
index 00000000000..b44a92fd3b9
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_store_vec.mir
@@ -0,0 +1,156 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=msa,+fp64 -mattr=nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+--- |
+
+  define void @load_store_v16i8(<16 x i8>* %a, <16 x i8>* %b) { entry: ret void }
+  define void @load_store_v8i16(<8 x i16>* %a, <8 x i16>* %b) { entry: ret void }
+  define void @load_store_v4i32(<4 x i32>* %a, <4 x i32>* %b) { entry: ret void }
+  define void @load_store_v2i64(<2 x i64>* %a, <2 x i64>* %b) { entry: ret void }
+  define void @load_store_v4f32(<4 x float>* %a, <4 x float>* %b) { entry: ret void }
+  define void @load_store_v2f64(<2 x double>* %a, <2 x double>* %b) { entry: ret void }
+
+...
+---
+name:            load_store_v16i8
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: load_store_v16i8
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load 16 from %ir.b)
+    ; P5600: ST_B [[LD_B]], [[COPY]], 0 :: (store 16 into %ir.a)
+    ; P5600: RetRA
+    %0:gprb(p0) = COPY $a0
+    %1:gprb(p0) = COPY $a1
+    %2:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+    G_STORE %2(<16 x s8>), %0(p0) :: (store 16 into %ir.a)
+    RetRA
+
+...
+---
+name:            load_store_v8i16
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: load_store_v8i16
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load 16 from %ir.b)
+    ; P5600: ST_H [[LD_H]], [[COPY]], 0 :: (store 16 into %ir.a)
+    ; P5600: RetRA
+    %0:gprb(p0) = COPY $a0
+    %1:gprb(p0) = COPY $a1
+    %2:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+    G_STORE %2(<8 x s16>), %0(p0) :: (store 16 into %ir.a)
+    RetRA
+
+...
+---
+name:            load_store_v4i32
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: load_store_v4i32
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.b)
+    ; P5600: ST_W [[LD_W]], [[COPY]], 0 :: (store 16 into %ir.a)
+    ; P5600: RetRA
+    %0:gprb(p0) = COPY $a0
+    %1:gprb(p0) = COPY $a1
+    %2:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+    G_STORE %2(<4 x s32>), %0(p0) :: (store 16 into %ir.a)
+    RetRA
+
+...
+---
+name:            load_store_v2i64
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: load_store_v2i64
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load 16 from %ir.b)
+    ; P5600: ST_D [[LD_D]], [[COPY]], 0 :: (store 16 into %ir.a)
+    ; P5600: RetRA
+    %0:gprb(p0) = COPY $a0
+    %1:gprb(p0) = COPY $a1
+    %2:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+    G_STORE %2(<2 x s64>), %0(p0) :: (store 16 into %ir.a)
+    RetRA
+
+...
+---
+name:            load_store_v4f32
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: load_store_v4f32
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.b)
+    ; P5600: ST_W [[LD_W]], [[COPY]], 0 :: (store 16 into %ir.a)
+    ; P5600: RetRA
+    %0:gprb(p0) = COPY $a0
+    %1:gprb(p0) = COPY $a1
+    %2:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+    G_STORE %2(<4 x s32>), %0(p0) :: (store 16 into %ir.a)
+    RetRA
+
+...
+---
+name:            load_store_v2f64
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: load_store_v2f64
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load 16 from %ir.b)
+    ; P5600: ST_D [[LD_D]], [[COPY]], 0 :: (store 16 into %ir.a)
+    ; P5600: RetRA
+    %0:gprb(p0) = COPY $a0
+    %1:gprb(p0) = COPY $a1
+    %2:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+    G_STORE %2(<2 x s64>), %0(p0) :: (store 16 into %ir.a)
+    RetRA
+
+...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load_store_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load_store_vec.mir
new file mode 100644
index 00000000000..d191de0ab46
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load_store_vec.mir
@@ -0,0 +1,144 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=msa,+fp64 -mattr=nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+--- |
+
+  define void @load_store_v16i8(<16 x i8>* %a, <16 x i8>* %b) { entry: ret void }
+  define void @load_store_v8i16(<8 x i16>* %a, <8 x i16>* %b) { entry: ret void }
+  define void @load_store_v4i32(<4 x i32>* %a, <4 x i32>* %b) { entry: ret void }
+  define void @load_store_v2i64(<2 x i64>* %a, <2 x i64>* %b) { entry: ret void }
+  define void @load_store_v4f32(<4 x float>* %a, <4 x float>* %b) { entry: ret void }
+  define void @load_store_v2f64(<2 x double>* %a, <2 x double>* %b) { entry: ret void }
+
+...
+---
+name:            load_store_v16i8
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: load_store_v16i8
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+    ; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+    ; P5600: G_STORE [[LOAD]](<16 x s8>), [[COPY]](p0) :: (store 16 into %ir.a)
+    ; P5600: RetRA
+    %0:_(p0) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %2:_(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+    G_STORE %2(<16 x s8>), %0(p0) :: (store 16 into %ir.a)
+    RetRA
+
+...
+---
+name:            load_store_v8i16
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: load_store_v8i16
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+    ; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+    ; P5600: G_STORE [[LOAD]](<8 x s16>), [[COPY]](p0) :: (store 16 into %ir.a)
+    ; P5600: RetRA
+    %0:_(p0) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %2:_(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+    G_STORE %2(<8 x s16>), %0(p0) :: (store 16 into %ir.a)
+    RetRA
+
+...
+---
+name:            load_store_v4i32
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: load_store_v4i32
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+    ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+    ; P5600: G_STORE [[LOAD]](<4 x s32>), [[COPY]](p0) :: (store 16 into %ir.a)
+    ; P5600: RetRA
+    %0:_(p0) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %2:_(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+    G_STORE %2(<4 x s32>), %0(p0) :: (store 16 into %ir.a)
+    RetRA
+
+...
+---
+name:            load_store_v2i64
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: load_store_v2i64
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+    ; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+    ; P5600: G_STORE [[LOAD]](<2 x s64>), [[COPY]](p0) :: (store 16 into %ir.a)
+    ; P5600: RetRA
+    %0:_(p0) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %2:_(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+    G_STORE %2(<2 x s64>), %0(p0) :: (store 16 into %ir.a)
+    RetRA
+
+...
+---
+name:            load_store_v4f32
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: load_store_v4f32
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+    ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+    ; P5600: G_STORE [[LOAD]](<4 x s32>), [[COPY]](p0) :: (store 16 into %ir.a)
+    ; P5600: RetRA
+    %0:_(p0) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %2:_(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+    G_STORE %2(<4 x s32>), %0(p0) :: (store 16 into %ir.a)
+    RetRA
+
+...
+---
+name:            load_store_v2f64
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: load_store_v2f64
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+    ; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+    ; P5600: G_STORE [[LOAD]](<2 x s64>), [[COPY]](p0) :: (store 16 into %ir.a)
+    ; P5600: RetRA
+    %0:_(p0) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %2:_(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+    G_STORE %2(<2 x s64>), %0(p0) :: (store 16 into %ir.a)
+    RetRA
+
+...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_store_vec.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_store_vec.ll
new file mode 100644
index 00000000000..6da35aa47f0
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_store_vec.ll
@@ -0,0 +1,80 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r5 -mattr=msa,+fp64 -mattr=nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
+
+define void @load_store_v16i8(<16 x i8>* %a, <16 x i8>* %b) {
+; P5600-LABEL: load_store_v16i8:
+; P5600:       # %bb.0: # %entry
+; P5600-NEXT:    ld.b $w0, 0($5)
+; P5600-NEXT:    st.b $w0, 0($4)
+; P5600-NEXT:    jr $ra
+; P5600-NEXT:    nop
+entry:
+  %0 = load <16 x i8>, <16 x i8>* %b, align 16
+  store <16 x i8> %0, <16 x i8>* %a, align 16
+  ret void
+}
+
+define void @load_store_v8i16(<8 x i16>* %a, <8 x i16>* %b) {
+; P5600-LABEL: load_store_v8i16:
+; P5600:       # %bb.0: # %entry
+; P5600-NEXT:    ld.h $w0, 0($5)
+; P5600-NEXT:    st.h $w0, 0($4)
+; P5600-NEXT:    jr $ra
+; P5600-NEXT:    nop
+entry:
+  %0 = load <8 x i16>, <8 x i16>* %b, align 16
+  store <8 x i16> %0, <8 x i16>* %a, align 16
+  ret void
+}
+
+define void @load_store_v4i32(<4 x i32>* %a, <4 x i32>* %b) {
+; P5600-LABEL: load_store_v4i32:
+; P5600:       # %bb.0: # %entry
+; P5600-NEXT:    ld.w $w0, 0($5)
+; P5600-NEXT:    st.w $w0, 0($4)
+; P5600-NEXT:    jr $ra
+; P5600-NEXT:    nop
+entry:
+  %0 = load <4 x i32>, <4 x i32>* %b, align 16
+  store <4 x i32> %0, <4 x i32>* %a, align 16
+  ret void
+}
+
+define void @load_store_v2i64(<2 x i64>* %a, <2 x i64>* %b) {
+; P5600-LABEL: load_store_v2i64:
+; P5600:       # %bb.0: # %entry
+; P5600-NEXT:    ld.d $w0, 0($5)
+; P5600-NEXT:    st.d $w0, 0($4)
+; P5600-NEXT:    jr $ra
+; P5600-NEXT:    nop
+entry:
+  %0 = load <2 x i64>, <2 x i64>* %b, align 16
+  store <2 x i64> %0, <2 x i64>* %a, align 16
+  ret void
+}
+
+define void @load_store_v4f32(<4 x float>* %a, <4 x float>* %b) {
+; P5600-LABEL: load_store_v4f32:
+; P5600:       # %bb.0: # %entry
+; P5600-NEXT:    ld.w $w0, 0($5)
+; P5600-NEXT:    st.w $w0, 0($4)
+; P5600-NEXT:    jr $ra
+; P5600-NEXT:    nop
+entry:
+  %0 = load <4 x float>, <4 x float>* %b, align 16
+  store <4 x float> %0, <4 x float>* %a, align 16
+  ret void
+}
+
+define void @load_store_v2f64(<2 x double>* %a, <2 x double>* %b) {
+; P5600-LABEL: load_store_v2f64:
+; P5600:       # %bb.0: # %entry
+; P5600-NEXT:    ld.d $w0, 0($5)
+; P5600-NEXT:    st.d $w0, 0($4)
+; P5600-NEXT:    jr $ra
+; P5600-NEXT:    nop
+entry:
+  %0 = load <2 x double>, <2 x double>* %b, align 16
+  store <2 x double> %0, <2 x double>* %a, align 16
+  ret void
+}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_store_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_store_vec.mir
new file mode 100644
index 00000000000..7b42ca0be02
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_store_vec.mir
@@ -0,0 +1,150 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=msa,+fp64 -mattr=nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+--- |
+
+  define void @load_store_v16i8(<16 x i8>* %a, <16 x i8>* %b) { entry: ret void }
+  define void @load_store_v8i16(<8 x i16>* %a, <8 x i16>* %b) { entry: ret void }
+  define void @load_store_v4i32(<4 x i32>* %a, <4 x i32>* %b) { entry: ret void }
+  define void @load_store_v2i64(<2 x i64>* %a, <2 x i64>* %b) { entry: ret void }
+  define void @load_store_v4f32(<4 x float>* %a, <4 x float>* %b) { entry: ret void }
+  define void @load_store_v2f64(<2 x double>* %a, <2 x double>* %b) { entry: ret void }
+
+...
+---
+name:            load_store_v16i8
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: load_store_v16i8
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+    ; P5600: [[LOAD:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+    ; P5600: G_STORE [[LOAD]](<16 x s8>), [[COPY]](p0) :: (store 16 into %ir.a)
+    ; P5600: RetRA
+    %0:_(p0) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %2:_(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+    G_STORE %2(<16 x s8>), %0(p0) :: (store 16 into %ir.a)
+    RetRA
+
+...
+---
+name:            load_store_v8i16
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: load_store_v8i16
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+    ; P5600: [[LOAD:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+    ; P5600: G_STORE [[LOAD]](<8 x s16>), [[COPY]](p0) :: (store 16 into %ir.a)
+    ; P5600: RetRA
+    %0:_(p0) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %2:_(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+    G_STORE %2(<8 x s16>), %0(p0) :: (store 16 into %ir.a)
+    RetRA
+
+...
+---
+name:            load_store_v4i32
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: load_store_v4i32
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+    ; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+    ; P5600: G_STORE [[LOAD]](<4 x s32>), [[COPY]](p0) :: (store 16 into %ir.a)
+    ; P5600: RetRA
+    %0:_(p0) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %2:_(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+    G_STORE %2(<4 x s32>), %0(p0) :: (store 16 into %ir.a)
+    RetRA
+
+...
+---
+name:            load_store_v2i64
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: load_store_v2i64
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+    ; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+    ; P5600: G_STORE [[LOAD]](<2 x s64>), [[COPY]](p0) :: (store 16 into %ir.a)
+    ; P5600: RetRA
+    %0:_(p0) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %2:_(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+    G_STORE %2(<2 x s64>), %0(p0) :: (store 16 into %ir.a)
+    RetRA
+
+...
+---
+name:            load_store_v4f32
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: load_store_v4f32
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+    ; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+    ; P5600: G_STORE [[LOAD]](<4 x s32>), [[COPY]](p0) :: (store 16 into %ir.a)
+    ; P5600: RetRA
+    %0:_(p0) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %2:_(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+    G_STORE %2(<4 x s32>), %0(p0) :: (store 16 into %ir.a)
+    RetRA
+
+...
+---
+name:            load_store_v2f64
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: load_store_v2f64
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+    ; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+    ; P5600: G_STORE [[LOAD]](<2 x s64>), [[COPY]](p0) :: (store 16 into %ir.a)
+    ; P5600: RetRA
+    %0:_(p0) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %2:_(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+    G_STORE %2(<2 x s64>), %0(p0) :: (store 16 into %ir.a)
+    RetRA
+
+...