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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-12-12 14:33:10 +0530 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2019-12-21 04:56:20 -0500 |
| commit | f9677c47573f7933dd6ea6fe3086fb58e159969a (patch) | |
| tree | 49cfd78b4c7a6b9114e288a9fe1d8127ec64b6a4 /llvm/test/CodeGen/Mips | |
| parent | 42a26445f9e68d55bcc4b8d1b4ced83a56d7743c (diff) | |
| download | bcm5719-llvm-f9677c47573f7933dd6ea6fe3086fb58e159969a.tar.gz bcm5719-llvm-f9677c47573f7933dd6ea6fe3086fb58e159969a.zip | |
Mips: Make test resistant to future changes
This seems to have been relying on extra spills being inserted in
these blocks to increase the code size to trigger branch
relaxation. This broke when these spills were avoided. Add some asm to
pad the size of the blocks to make it not matter.
Diffstat (limited to 'llvm/test/CodeGen/Mips')
| -rw-r--r-- | llvm/test/CodeGen/Mips/branch-relaxation-with-hazard.ll | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/Mips/branch-relaxation-with-hazard.ll b/llvm/test/CodeGen/Mips/branch-relaxation-with-hazard.ll index eb9ee7e9d3f..530c3a7d24d 100644 --- a/llvm/test/CodeGen/Mips/branch-relaxation-with-hazard.ll +++ b/llvm/test/CodeGen/Mips/branch-relaxation-with-hazard.ll @@ -38,11 +38,13 @@ entry: br i1 %cmp, label %if.then, label %if.end4 if.then: + call void asm sideeffect ".space 10", "~{$1}"() %1 = load i32, i32* %argc.addr, align 4 %cmp1 = icmp sgt i32 %1, 3 br i1 %cmp1, label %if.then2, label %if.end if.then2: + call void asm sideeffect ".space 10", "~{$1}"() %call = call i32 bitcast (i32 (...)* @boo to i32 ()*)() store i32 %call, i32* %retval, align 4 br label %return |
