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path: root/llvm/lib/Target/R600/SIRegisterInfo.cpp
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* R600 -> AMDGPU renameTom Stellard2015-06-131-543/+0
| | | | llvm-svn: 239657
* R600/SI: Update tablegen defs to avoid restoring spilled sgprs to m0Tom Stellard2015-05-121-8/+0
| | | | | | | | We had code to do this in SIRegisterInfo::eliminateFrameIndex(), but it is easier to just change the definition of SI_SPILL_S32_RESTORE to only allow numbered sgprs. llvm-svn: 237143
* R600/SI: Remove M0Reg register classTom Stellard2015-05-121-1/+0
| | | | | | It is no longer used. llvm-svn: 237142
* R600/SI: Replace TRI->getRegClass(Reg) with TRI->getPhysRegClass(Reg)Tom Stellard2015-05-121-0/+1
| | | | | | | TRI->getRegClass() takes a register class ID, not a register. We were using this incorrectly in a few places. llvm-svn: 237132
* R600/SI: Insert more NOPs after READLANE on VI, don't use NOPs on CIMarek Olsak2015-03-241-1/+16
| | | | | | This is a candidate for stable. llvm-svn: 233080
* Remove the need to cache the subtarget in the R600 TargetRegisterInfoEric Christopher2015-03-111-9/+10
| | | | | | classes. llvm-svn: 231954
* Have getRegPressureSetLimit take a MachineFunction so that aEric Christopher2015-03-111-1/+2
| | | | | | we can inspect the subtarget and function when computing values. llvm-svn: 231951
* R600/SI: Limit SGPRs to 80 on Tonga and IcelandMarek Olsak2015-03-091-0/+17
| | | | | | This is a candidate for stable. llvm-svn: 231659
* R600/SI: Fix getNumSGPRsAllowed for VIMarek Olsak2015-03-091-11/+21
| | | | llvm-svn: 231658
* R600/SI: Consistently put soffset before the offset operand for mubuf ↵Tom Stellard2015-02-271-1/+1
| | | | | | | | instructions This matches the assembly syntax. llvm-svn: 230758
* R600/SI: Determine target-specific encoding of READLANE and WRITELANE early v2Marek Olsak2015-02-031-2/+6
| | | | | | | | | | | | | These are VOP2 on SI and VOP3 on VI, and their pseudos are neither, which can be a problem. In order to make isVOP2 and isVOP3 queries behave as expected, the encoding must be determined first. This doesn't fix any known issue, but better safe than sorry. v2: add and use getMCOpcodeFromPseudo Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 227987
* R600/SI: Handle SI_SPILL_V96_RESTORE in SIRegisterInfo::eliminateFrameIndex()Tom Stellard2015-01-301-0/+1
| | | | | | This fixes a crash in Unigine Heaven. llvm-svn: 227618
* R600/SI: Remove stray debug statementsTom Stellard2015-01-291-5/+1
| | | | llvm-svn: 227462
* R600/SI: Define a schedule model and enable the generic machine schedulerTom Stellard2015-01-291-3/+52
| | | | | | The schedule model is not complete yet, and could be improved. llvm-svn: 227461
* R600/SI: Add subtarget feature to enable VGPR spilling for all shader typesTom Stellard2015-01-201-0/+2
| | | | | | | This is disabled by default, but can be enabled with the subtarget feature: 'vgpr-spilling' llvm-svn: 226597
* R600/SI: Fix simple-loop.ll testTom Stellard2015-01-201-1/+1
| | | | llvm-svn: 226596
* R600/SI: Use external symbols for scratch bufferTom Stellard2015-01-201-28/+6
| | | | | | | | We were passing the scratch buffer address to the shaders via user sgprs, but now we use external symbols and have the driver patch the shader using reloc information. llvm-svn: 226586
* R600/SI: Add kill flag when copying scratch offset to a registerTom Stellard2015-01-201-1/+1
| | | | | | | This allows us to re-use the same register for the scratch offset when accessing large private arrays. llvm-svn: 226585
* R600/SI: Spill VGPRs to scratch space for compute shadersTom Stellard2015-01-141-62/+94
| | | | llvm-svn: 225988
* R600/SI: Use RegisterOperands to specify which operands can accept immediatesTom Stellard2015-01-121-29/+5
| | | | | | | | | | | | There are some operands which can take either immediates or registers and we were previously using different register class to distinguish between operands that could take immediates and those that could not. This patch switches to using RegisterOperands which should simplify the backend by reducing the number of register classes and also make it easier to implement the assembler. llvm-svn: 225662
* R600/SI: Remove VReg_32 register classTom Stellard2015-01-071-5/+5
| | | | | | | | | | | Use VGPR_32 register class instead. These two register classes were identical and having separate classes was causing SIInstrInfo::isLegalOperands() to be overly conservative in some cases. This change is necessary to prevent future paches from missing a folding opportunity in fneg-fabs.ll. llvm-svn: 225382
* R600/SI: Make sure non-inline constants aren't folded into mubuf soffset operandTom Stellard2014-12-191-0/+1
| | | | | | | | mubuf instructions now define the soffset field using the SCSrc_32 register class which indicates that only SGPRs and inline constants are allowed. llvm-svn: 224622
* R600/SI: Fix allocating flat_scr_lo / flat_scr_hiMatt Arsenault2014-11-251-0/+2
| | | | | | | | Only the super register flat_scr was marked as reserved, so in some cases with high register usage it would still try to allocate the subregisters. llvm-svn: 222737
* R600/SI: Fix spilling of m0 registerTom Stellard2014-11-141-1/+9
| | | | | | | | | | If we have spilled the value of the m0 register, then we need to restore it with v_readlane_b32 to a regular sgpr, because v_readlane_b32 can't write to m0. v_readlane_b32 can't write to m0, so llvm-svn: 222036
* R600/SI: Make constant array staticMatt Arsenault2014-11-141-1/+1
| | | | llvm-svn: 221965
* R600/SI: Add new helper isSGPRClassIDMatt Arsenault2014-09-241-7/+0
| | | | | | Move these into header since they are trivial llvm-svn: 218360
* R600/SI: Mark EXEC_LO and EXEC_HI as reservedTom Stellard2014-09-241-0/+6
| | | | | | | These registers can be allocated and used like other 32-bit registers, but it seems like a likely source for bugs. llvm-svn: 218350
* R600/SI: Fix SIRegisterInfo::getPhysRegSubReg()Tom Stellard2014-09-241-1/+10
| | | | | | | | Correctly handle special registers: EXEC, EXEC_LO, EXEC_HI, VCC_LO, VCC_HI, and M0. The previous implementation would assertion fail when passed these registers. llvm-svn: 218349
* R600/SI: Implement VGPR register spilling for compute at -O0 v3Tom Stellard2014-09-241-1/+114
| | | | | | | | | | | | | | VGPRs are spilled to LDS. This still needs more testing, but we need to at least enable it at -O0, because the fast register allocator spills all registers that are live at the end of blocks and without this some future commits will break the flat-address-space.ll test. v2: Only calculate thread id once v3: Move insertion of spill instructions to SIRegisterInfo::eliminateFrameIndex() llvm-svn: 218348
* R600/SI: Clean up checks for legality of immediate operandsTom Stellard2014-09-231-3/+21
| | | | | | | | | | | | | | There are new register classes VCSrc_* which represent operands that can take an SGPR, VGPR or inline constant. The VSrc_* class is now used to represent operands that can take an SGPR, VGPR, or a 32-bit immediate. This allows us to have more accurate checks for legality of immediates, since before we had no way to distinguish between operands that supported any 32-bit immediate and operands which could only support inline constants. llvm-svn: 218334
* R600/SI: Add enums for some hard-coded valuesTom Stellard2014-09-221-0/+8
| | | | llvm-svn: 218250
* R600/SI: Add preliminary support for flat address spaceMatt Arsenault2014-09-151-0/+23
| | | | llvm-svn: 217777
* R600/SI: Use eliminateFrameIndex() to expand SGPR spill pseudosTom Stellard2014-08-211-9/+98
| | | | | | | | | | | | | | | This will simplify the SGPR spilling and also allow us to use MachineFrameInfo for calculating offsets, which should be more reliable than our custom code. This fixes a crash in some cases where a register would be spilled in a branch such that the VGPR defined for spilling did not dominate all the uses when restoring. This fixes a crash in an ocl conformance test. The test requries register spilling and is too big to include. llvm-svn: 216217
* R600/SI: Handle VCC in SIRegisterInfo::getPhysRegSubReg()Tom Stellard2014-08-211-0/+11
| | | | | | | This fixes a crash in an ocl conformance test. The test requries register spilling and is too big to include. llvm-svn: 216216
* R600: silence GCC warningSaleem Abdulrasool2014-07-211-0/+1
| | | | | | | | | | GCC believes it may be possible to not return a value from the switch: lib/Target/R600/SIRegisterInfo.cpp:187:1: warning: control reaches end of non-void function [-Wreturn-type] Add an unreachable label to indicate that this is not possible and still permit switch coverage checking. llvm-svn: 213572
* R600/SI: Use scratch memory for large private arraysTom Stellard2014-07-211-2/+46
| | | | llvm-svn: 213551
* R600/SI: Add verifier check for immediates in register operands.Tom Stellard2014-07-021-0/+16
| | | | llvm-svn: 212214
* R600: Remove AMDIL instruction and register definitionsTom Stellard2014-06-131-9/+0
| | | | | | Most of these are no longer used any more. llvm-svn: 210915
* R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtargetTom Stellard2014-06-131-5/+4
| | | | llvm-svn: 210869
* Use range forMatt Arsenault2014-05-121-4/+3
| | | | llvm-svn: 208617
* R600/SI: Only create one instruction when spilling/restoring register v3Tom Stellard2014-05-021-0/+7
| | | | | | | | | | | | | | | | | | The register spiller assumes that only one new instruction is created when spilling and restoring registers, so we need to emit pseudo instructions for vector register spills and lower them after register allocation. v2: - Fix calculation of lane index - Extend VGPR liveness to end of program. v3: - Use SIMM16 field of S_NOP to specify multiple NOPs. https://bugs.freedesktop.org/show_bug.cgi?id=75005 llvm-svn: 207843
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-2/+2
| | | | llvm-svn: 207197
* R600/SI: Return the correct index for VGPRs in getHWRegIndex()Tom Stellard2014-03-311-1/+1
| | | | | | The register index is stored in the low 8-bits of the encoding. llvm-svn: 205186
* Fix known typosAlp Toker2014-01-241-1/+1
| | | | | | | Sweep the codebase for common typos. Includes some changes to visible function names that were misspelt. llvm-svn: 200018
* R600/SI: Fix moveToVALU when the first operand is VSrc.Matt Arsenault2013-11-181-0/+2
| | | | | | | Moving into a VSrc doesn't always work, since it could be replaced with an SGPR later. llvm-svn: 195042
* R600/SI: Add VReg_96 register class to SIRegisterInfo::hasVGPRs()Tom Stellard2013-11-151-0/+1
| | | | | | This fixes a crash with GNOME settings manager. llvm-svn: 194836
* R600/SI: Add support for private address space load/storeTom Stellard2013-11-131-0/+8
| | | | | | | Private address space is emulated using the register file with MOVRELS and MOVRELD instructions. llvm-svn: 194626
* R600/SI: Prefer SALU instructions for bit shift operationsTom Stellard2013-11-131-6/+42
| | | | | | | | | | | | | | All shift operations will be selected as SALU instructions and then if necessary lowered to VALU instructions in the SIFixSGPRCopies pass. This allows us to do more operations on the SALU which will improve performance and is also required for implementing private memory using indirect addressing, since the private memory pointers must stay in the scalar registers. This patch includes some fixes from Matt Arsenault. llvm-svn: 194625
* Make method staticMatt Arsenault2013-11-101-1/+1
| | | | llvm-svn: 194340
* R600/SI: Mark the EXEC register as reservedTom Stellard2013-10-101-0/+1
| | | | | | | | This prevents the machine verifier from complaining about uses of an undefined physical register. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 192364
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