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* R600 -> AMDGPU renameTom Stellard2015-06-13121-44549/+0
| | | | llvm-svn: 239657
* R600/SI: Add assembler support for FLAT instructionsTom Stellard2015-06-124-89/+194
| | | | | | | | - Add glc, slc, and tfe operands to flat instructions - Add missing flat instructions - Fix the encoding of flat_load_dwordx3 and flat_store_dwordx3. llvm-svn: 239637
* Remove a hack that tries to align '*'.Rafael Espindola2015-06-121-1/+1
| | | | | | | | | | | | The alignment is not required, so we can just remove it for now. The old code is a hack as it depends on the buffer management to find the current column. If the alignment is really desirable, the proper way to do it is to pass in a formatted_raw_stream that knows the current column. llvm-svn: 239603
* Replace string GNU Triples with llvm::Triple in TargetMachine. NFC.Daniel Sanders2015-06-112-19/+20
| | | | | | | | | | | | | | | | | | Summary: For the moment, TargetMachine::getTargetTriple() still returns a StringRef. This continues the patch series to eliminate StringRef forms of GNU triples from the internals of LLVM that began in r239036. Reviewers: rengolin Reviewed By: rengolin Subscribers: ted, llvm-commits, rengolin, jholewinski Differential Revision: http://reviews.llvm.org/D10362 llvm-svn: 239554
* [CodeGen] ArrayRef'ize cond/pred in various TII APIs. NFC.Ahmed Bougacha2015-06-114-17/+17
| | | | llvm-svn: 239553
* Replace string GNU Triples with llvm::Triple in computeDataLayout(). NFC.Daniel Sanders2015-06-111-5/+4
| | | | | | | | | | | | | | | | Summary: This continues the patch series to eliminate StringRef forms of GNU triples from the internals of LLVM that began in r239036. Reviewers: rengolin Reviewed By: rengolin Subscribers: llvm-commits, jfb, rengolin Differential Revision: http://reviews.llvm.org/D10361 llvm-svn: 239538
* R600/SI: Define latency for flat instructionsTom Stellard2015-06-111-0/+1
| | | | llvm-svn: 239535
* R600/SI: Move flat instruction defs to CIInstructions.tdTom Stellard2015-06-112-108/+110
| | | | llvm-svn: 239534
* Replace string GNU Triples with llvm::Triple in MCSubtargetInfo and ↵Daniel Sanders2015-06-104-14/+14
| | | | | | | | | | | | | | | | | | create*MCSubtargetInfo(). NFC. Summary: This continues the patch series to eliminate StringRef forms of GNU triples from the internals of LLVM that began in r239036. Reviewers: rafael Reviewed By: rafael Subscribers: rafael, ted, jfb, llvm-commits, rengolin, jholewinski Differential Revision: http://reviews.llvm.org/D10311 llvm-svn: 239467
* Replace string GNU Triples with llvm::Triple in MCAsmBackend subclasses and ↵Daniel Sanders2015-06-102-3/+3
| | | | | | | | | | | | | | | | | | create*AsmBackend(). NFC. Summary: This continues the patch series to eliminate StringRef forms of GNU triples from the internals of LLVM that began in r239036. Reviewers: echristo, rafael Reviewed By: rafael Subscribers: rafael, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D10243 llvm-svn: 239464
* R600: Switch to using generic min / max nodes.Matt Arsenault2015-06-096-56/+39
| | | | llvm-svn: 239377
* MC: Add target hook to control symbol quotingMatt Arsenault2015-06-091-1/+1
| | | | llvm-svn: 239370
* Fix clang-cl self-host -Wc++11-narrowing bugReid Kleckner2015-06-081-1/+1
| | | | | | | Use unsigned as the underlying storage type of the AMDGPU address space enum. llvm-svn: 239355
* [InstrInfo] Refactor foldOperandImpl to thread through InsertPt. NFCKeno Fischer2015-06-082-8/+8
| | | | | | | | | | | | | | | | | | Summary: This was a longstanding FIXME and is a necessary precursor to cases where foldOperandImpl may have to create more than one instruction (e.g. to constrain a register class). This is the split out NFC changes from D6262. Reviewers: pete, ributzka, uweigand, mcrosier Reviewed By: mcrosier Subscribers: mcrosier, ted, llvm-commits Differential Revision: http://reviews.llvm.org/D10174 llvm-svn: 239336
* MC: Clean up the naming for MCMachObjectWriter. NFC.Jim Grosbach2015-06-041-1/+1
| | | | | | | | | | | | | | | | | | s/ExecutePostLayoutBinding/executePostLayoutBinding/ s/ComputeSymbolTable/computeSymbolTable/ s/BindIndirectSymbols/bindIndirectSymbols/ s/RecordTLVPRelocation/recordTLVPRelocation/ s/RecordScatteredRelocation/recordScatteredRelocation/ s/WriteLinkerOptionsLoadCommand/writeLinkerOptionsLoadCommand/ s/WriteLinkeditLoadCommand/writeLinkeditLoadCommand/ s/WriteNlist/writeNlist/ s/WriteDysymtabLoadCommand/writeDysymtabLoadCommand/ s/WriteSymtabLoadCommand/writeSymtabLoadCommand/ s/WriteSection/writeSection/ s/WriteSegmentLoadCommand/writeSegmentLoadCommand/ s/WriteHeader/writeHeader/ llvm-svn: 239119
* MC: Clean up naming in MCObjectWriter. NFC.Jim Grosbach2015-06-041-3/+3
| | | | | | | | | | | | | | | | | | | | s/WriteObject/writeObject/ s/RecordRelocation/recordRelocation/ s/IsSymbolRefDifferenceFullyResolved/isSymbolRefDifferenceFullyResolved/ s/Write8/write8/ s/WriteLE16/writeLE16/ s/WriteLE32/writeLE32/ s/WriteLE64/writeLE64/ s/WriteBE16/writeBE16/ s/WriteBE32/writeBE32/ s/WriteBE64/writeBE64/ s/Write16/write16/ s/Write32/write32/ s/Write64/write64/ s/WriteZeroes/writeZeroes/ s/WriteBytes/writeBytes/ llvm-svn: 239108
* R600/SI: Reimplement isLegalAddressingModeMatt Arsenault2015-06-042-31/+70
| | | | | | | | | | | Now that we sometimes know the address space, this can theoretically do a better job. This needs better test coverage, but this mostly depends on first updating the loop optimizatiosn to provide the address space. llvm-svn: 239053
* R600/SI: Fix some cases for load / store of halfMatt Arsenault2015-06-042-3/+42
| | | | | | | Mostly argument loads were producing broken zextloads from an FP type. llvm-svn: 239049
* Replace custom fixed endian to raw_ostream emission with EndianStream.Benjamin Kramer2015-06-041-6/+3
| | | | | | Less code, clearer and more efficient. No functionality change intended. llvm-svn: 239040
* Replace string GNU Triples with llvm::Triple in MCAsmInfo subclasses and ↵Daniel Sanders2015-06-042-3/+3
| | | | | | | | | | | | | | | | | | | | create*AsmInfo(). NFC. Summary: This is the first of several patches to eliminate StringRef forms of GNU triples from the internals of LLVM. After this is complete, GNU triples will be replaced by a more authoratitive representation in the form of an LLVM TargetTuple. Reviewers: rengolin Reviewed By: rengolin Subscribers: ted, llvm-commits, rengolin, jholewinski Differential Revision: http://reviews.llvm.org/D10236 llvm-svn: 239036
* R600: Re-enable sub-reg livenessTom Stellard2015-06-041-1/+1
| | | | | | The bug in the R600 backend that this uncovered has been fixed. llvm-svn: 238999
* R600/SI: Don't hardcode pointer typeMatt Arsenault2015-06-011-4/+5
| | | | llvm-svn: 238789
* Add address space argument to isLegalAddressingModeMatt Arsenault2015-06-012-2/+2
| | | | | | | | | | This is important because of different addressing modes depending on the address space for GPU targets. This only adds the argument, and does not update any of the uses to provide the correct address space. llvm-svn: 238723
* MC: Clean up MCExpr naming. NFC.Jim Grosbach2015-05-302-5/+5
| | | | llvm-svn: 238634
* R600: Rely on TypeLegalizer to use divrem instead of div/remJan Vesely2015-05-271-43/+0
| | | | | reviewer: tstellardAMD llvm-svn: 238337
* R600: Use SIGN_EXTEND_INREG for SEXT loadsJan Vesely2015-05-261-6/+3
| | | | | | Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Matt Arsenault <Matthew.Arsenault@amd.com> llvm-svn: 238229
* R600: Add comments to subword private address load lowering codeJan Vesely2015-05-261-0/+13
| | | | | | | | v2: Use C++ comments and end with periods Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Matt Arsenault <Matthew.Arsenault@amd.com> llvm-svn: 238228
* R600/SI: Add assembler support for all CI and VI VOP2 instructionsTom Stellard2015-05-263-3/+70
| | | | llvm-svn: 238211
* Use std::bitset for SubtargetFeatures.Michael Kuperstein2015-05-262-3/+3
| | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first several times this was committed (e.g. r229831, r233055), it caused several buildbot failures. Apparently the reason for most failures was both clang and gcc's inability to deal with large numbers (> 10K) of bitset constructor calls in tablegen-generated initializers of instruction info tables. This should now be fixed. llvm-svn: 238192
* Remove most uses of MCSectionData from MCAssembler.Rafael Espindola2015-05-261-1/+1
| | | | llvm-svn: 238172
* Turn MCSectionData into a field of MCSection.Rafael Espindola2015-05-251-1/+1
| | | | | | | This also changes MCAssembler to store a vector of MCSections instead of an iplist of MCSectionData. llvm-svn: 238159
* R600/SI: Remove some unnecessary patterns from VINTRP multiclassTom Stellard2015-05-252-11/+9
| | | | | | | DisableEncoding and Constraints can be set using let statements around the multiclass defs. llvm-svn: 238148
* R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chipsTom Stellard2015-05-255-10/+50
| | | | | | The src and dst register cannot be the same on chips with 16 lds banks. llvm-svn: 238147
* R600/SI: Use NAME rather than opName as the key to the MCOpcode tablesTom Stellard2015-05-252-7/+7
| | | | | | | | This lets us drop a parameter the opName parameter to the VINTRP multiclass and makes it possible to create multiple VINTRP defs with the same asm mnemonic. llvm-svn: 238146
* Add target hook to allow merging stores of nonzero constantsMatt Arsenault2015-05-242-0/+10
| | | | | | | | | | On GPU targets, materializing constants is cheap and stores are expensive, so only doing this for zero vectors was silly. Most of the new testcases aren't optimally merged, and are for later improvements. llvm-svn: 238108
* Move alignment from MCSectionData to MCSection.Rafael Espindola2015-05-211-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | This starts merging MCSection and MCSectionData. There are a few issues with the current split between MCSection and MCSectionData. * It optimizes the the not as important case. We want the production of .o files to be really fast, but the split puts the information used for .o emission in a separate data structure. * The ELF/COFF/MachO hierarchy is not represented in MCSectionData, leading to some ad-hoc ways to represent the various flags. * It makes it harder to remember where each item is. The attached patch starts merging the two by moving the alignment from MCSectionData to MCSection. Most of the patch is actually just dropping 'const', since MCSectionData is mutable, but MCSection was not. llvm-svn: 237936
* Simplify IRBuilder::CreateCall* by using ArrayRef+initializer_list/braced ↵David Blaikie2015-05-181-6/+5
| | | | | | init only llvm-svn: 237624
* MC: Clean up method names in MCContext.Jim Grosbach2015-05-184-6/+6
| | | | | | | The naming was a mish-mash of old and new style. Update to be consistent with the new. NFC. llvm-svn: 237594
* MC: MCCodeGenInfo naming update. NFC.Jim Grosbach2015-05-151-1/+1
| | | | | | s/InitMCCodeGenInfo/initMCCodeGenInfo/ llvm-svn: 237471
* MC: Update MCCodeEmitter naming. NFC.Jim Grosbach2015-05-153-5/+5
| | | | | | s/EncodeInstruction/encodeInstruction/ llvm-svn: 237469
* MC: Update MCFixup naming. NFC.Jim Grosbach2015-05-151-2/+2
| | | | | | s/MCFixup::Create/MCFixup::create/ llvm-svn: 237468
* MC: Modernize MCOperand API naming. NFC.Jim Grosbach2015-05-132-12/+12
| | | | | | MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
* Reverting r237234, "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-05-132-3/+3
| | | | | | | The buildbots are still not satisfied. MIPS and ARM are failing (even though at least MIPS was expected to pass). llvm-svn: 237245
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-05-132-3/+3
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first two times this was committed (r229831, r233055), it caused several buildbot failures. At least some of the ARM and MIPS ones were due to gcc/binutils issues, and should now be fixed. llvm-svn: 237234
* R600/SI: Fix bug in VGPR spillingTom Stellard2015-05-125-76/+69
| | | | | | | | | | | | AMDGPU::SI_SPILL_V96_RESTORE was missing from a switch statement, which caused the srsrc and soffset register to not be set correctly. This commit replaces the switch statement with a SITargetInfo query to make sure all spill instructions are covered. Differential Revision: http://reviews.llvm.org/D9582 llvm-svn: 237164
* R600/SI: add pass to mark CF live ranges as non-spillableTom Stellard2015-05-124-0/+110
| | | | | | | | | | | | | | | | | | | | | | Spilling can insert instructions almost anywhere, and this can mess up control flow lowering in a multitude of ways, due to instruction reordering. Let's sort this out the easy way: never spill registers involved with control flow, i.e. saved EXEC masks. Unfortunately, this does not work at all with optimizations disabled, as the register allocator ignores spill weights. This should be addressed in a future commit. The test was reduced from the "stacks" shader of [1]. Some issues trigger the machine verifier while another one is checked manually. [1] http://madebyevan.com/webgl-path-tracing/ v2: only insert pass with optimizations enabled, merge test runs. Patch by: Grigori Goronzy llvm-svn: 237152
* R600/SI: Update tablegen defs to avoid restoring spilled sgprs to m0Tom Stellard2015-05-122-9/+4
| | | | | | | | We had code to do this in SIRegisterInfo::eliminateFrameIndex(), but it is easier to just change the definition of SI_SPILL_S32_RESTORE to only allow numbered sgprs. llvm-svn: 237143
* R600/SI: Remove M0Reg register classTom Stellard2015-05-123-4/+1
| | | | | | It is no longer used. llvm-svn: 237142
* R600/SI: Remove explicit m0 operand from DS instructionsTom Stellard2015-05-126-118/+259
| | | | | | | Instead add m0 as an implicit operand. This helps avoid spills of the m0 register in some cases. llvm-svn: 237141
* R600/SI: Remove explicit m0 operand from v_interp instructionsTom Stellard2015-05-126-33/+59
| | | | | | | Instead add m0 as an implicit operand. This helps avoid spills of the m0 register in some cases. llvm-svn: 237140
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