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author | Tom Stellard <thomas.stellard@amd.com> | 2014-09-23 21:26:25 +0000 |
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committer | Tom Stellard <thomas.stellard@amd.com> | 2014-09-23 21:26:25 +0000 |
commit | 73ae1cb59a4a3fe25c8678846816b37bfb87edfe (patch) | |
tree | 21be006366c091b8a8e1d2ac25e6372477f0c65c /llvm/lib/Target/R600/SIRegisterInfo.cpp | |
parent | bdf54a21b5e3392b431b6569007cb61689c76a3c (diff) | |
download | bcm5719-llvm-73ae1cb59a4a3fe25c8678846816b37bfb87edfe.tar.gz bcm5719-llvm-73ae1cb59a4a3fe25c8678846816b37bfb87edfe.zip |
R600/SI: Clean up checks for legality of immediate operands
There are new register classes VCSrc_* which represent operands that
can take an SGPR, VGPR or inline constant. The VSrc_* class is now used
to represent operands that can take an SGPR, VGPR, or a 32-bit
immediate.
This allows us to have more accurate checks for legality of
immediates, since before we had no way to distinguish between operands
that supported any 32-bit immediate and operands which could only
support inline constants.
llvm-svn: 218334
Diffstat (limited to 'llvm/lib/Target/R600/SIRegisterInfo.cpp')
-rw-r--r-- | llvm/lib/Target/R600/SIRegisterInfo.cpp | 24 |
1 files changed, 21 insertions, 3 deletions
diff --git a/llvm/lib/Target/R600/SIRegisterInfo.cpp b/llvm/lib/Target/R600/SIRegisterInfo.cpp index d1666fdd1f6..3924e21003c 100644 --- a/llvm/lib/Target/R600/SIRegisterInfo.cpp +++ b/llvm/lib/Target/R600/SIRegisterInfo.cpp @@ -275,7 +275,7 @@ unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg, return SubRC->getRegister(Index + Channel); } -bool SIRegisterInfo::regClassCanUseImmediate(int RCID) const { +bool SIRegisterInfo::regClassCanUseLiteralConstant(int RCID) const { switch (RCID) { default: return false; case AMDGPU::SSrc_32RegClassID: @@ -286,11 +286,29 @@ bool SIRegisterInfo::regClassCanUseImmediate(int RCID) const { } } -bool SIRegisterInfo::regClassCanUseImmediate( +bool SIRegisterInfo::regClassCanUseLiteralConstant( const TargetRegisterClass *RC) const { - return regClassCanUseImmediate(RC->getID()); + return regClassCanUseLiteralConstant(RC->getID()); } +bool SIRegisterInfo::regClassCanUseInlineConstant(int RCID) const { + if (regClassCanUseLiteralConstant(RCID)) + return true; + + switch (RCID) { + default: return false; + case AMDGPU::VCSrc_32RegClassID: + case AMDGPU::VCSrc_64RegClassID: + return true; + } +} + +bool SIRegisterInfo::regClassCanUseInlineConstant( + const TargetRegisterClass *RC) const { + return regClassCanUseInlineConstant(RC->getID()); +} + + unsigned SIRegisterInfo::getPreloadedValue(const MachineFunction &MF, enum PreloadedValue Value) const { |