diff options
| author | Tom Stellard <thomas.stellard@amd.com> | 2014-12-19 22:15:30 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2014-12-19 22:15:30 +0000 |
| commit | c3d7eeb6e561ecafd8e86fb52b287f0dcbd7453c (patch) | |
| tree | e4b2bd856d5f61571a28c0b76feaeba74b68b851 /llvm/lib/Target/R600/SIRegisterInfo.cpp | |
| parent | e8270225a29d22c40e4aee105229d64c7329aeee (diff) | |
| download | bcm5719-llvm-c3d7eeb6e561ecafd8e86fb52b287f0dcbd7453c.tar.gz bcm5719-llvm-c3d7eeb6e561ecafd8e86fb52b287f0dcbd7453c.zip | |
R600/SI: Make sure non-inline constants aren't folded into mubuf soffset operand
mubuf instructions now define the soffset field using the SCSrc_32
register class which indicates that only SGPRs and inline constants
are allowed.
llvm-svn: 224622
Diffstat (limited to 'llvm/lib/Target/R600/SIRegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/R600/SIRegisterInfo.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/R600/SIRegisterInfo.cpp b/llvm/lib/Target/R600/SIRegisterInfo.cpp index 5dc0f755f14..7bd573cb6a6 100644 --- a/llvm/lib/Target/R600/SIRegisterInfo.cpp +++ b/llvm/lib/Target/R600/SIRegisterInfo.cpp @@ -414,6 +414,7 @@ bool SIRegisterInfo::regClassCanUseInlineConstant(int RCID) const { default: return false; case AMDGPU::VCSrc_32RegClassID: case AMDGPU::VCSrc_64RegClassID: + case AMDGPU::SCSrc_32RegClassID: return true; } } |
