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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-11-25 07:53:06 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-11-25 07:53:06 +0000 |
| commit | e335fd343e92e76d0182096f9b1f369c045ffff6 (patch) | |
| tree | 2aae351737bc98e20cd371d8fecb4357454b3263 /llvm/lib/Target/R600/SIRegisterInfo.cpp | |
| parent | 8cf0dbb01518d08481cfab598a31d4c580ace53f (diff) | |
| download | bcm5719-llvm-e335fd343e92e76d0182096f9b1f369c045ffff6.tar.gz bcm5719-llvm-e335fd343e92e76d0182096f9b1f369c045ffff6.zip | |
R600/SI: Fix allocating flat_scr_lo / flat_scr_hi
Only the super register flat_scr was marked as reserved,
so in some cases with high register usage it would still
try to allocate the subregisters.
llvm-svn: 222737
Diffstat (limited to 'llvm/lib/Target/R600/SIRegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/R600/SIRegisterInfo.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/R600/SIRegisterInfo.cpp b/llvm/lib/Target/R600/SIRegisterInfo.cpp index cffea129de9..5dc0f755f14 100644 --- a/llvm/lib/Target/R600/SIRegisterInfo.cpp +++ b/llvm/lib/Target/R600/SIRegisterInfo.cpp @@ -40,6 +40,8 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const { Reserved.set(AMDGPU::INDIRECT_BASE_ADDR); Reserved.set(AMDGPU::FLAT_SCR); + Reserved.set(AMDGPU::FLAT_SCR_LO); + Reserved.set(AMDGPU::FLAT_SCR_HI); // Reserve some VGPRs to use as temp registers in case we have to spill VGPRs Reserved.set(AMDGPU::VGPR255); |
