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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-09-15 15:41:53 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-09-15 15:41:53 +0000 |
commit | 3f98140c87728cec3247e2dbe0a9990e48afa984 (patch) | |
tree | 221a264a783c12b722ae3e15e68f0798a35ce101 /llvm/lib/Target/R600/SIRegisterInfo.cpp | |
parent | 65f67e4dfe837d8aff8d9b30cecc7247466d6f52 (diff) | |
download | bcm5719-llvm-3f98140c87728cec3247e2dbe0a9990e48afa984.tar.gz bcm5719-llvm-3f98140c87728cec3247e2dbe0a9990e48afa984.zip |
R600/SI: Add preliminary support for flat address space
llvm-svn: 217777
Diffstat (limited to 'llvm/lib/Target/R600/SIRegisterInfo.cpp')
-rw-r--r-- | llvm/lib/Target/R600/SIRegisterInfo.cpp | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/llvm/lib/Target/R600/SIRegisterInfo.cpp b/llvm/lib/Target/R600/SIRegisterInfo.cpp index 8663df88922..823c9e90c5d 100644 --- a/llvm/lib/Target/R600/SIRegisterInfo.cpp +++ b/llvm/lib/Target/R600/SIRegisterInfo.cpp @@ -33,6 +33,7 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const { BitVector Reserved(getNumRegs()); Reserved.set(AMDGPU::EXEC); Reserved.set(AMDGPU::INDIRECT_BASE_ADDR); + Reserved.set(AMDGPU::FLAT_SCR); return Reserved; } @@ -246,6 +247,28 @@ unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg, default: llvm_unreachable("Invalid SubIdx for VCC"); } break; + + case AMDGPU::FLAT_SCR: + switch (Channel) { + case 0: + return AMDGPU::FLAT_SCR_LO; + case 1: + return AMDGPU::FLAT_SCR_HI; + default: + llvm_unreachable("Invalid SubIdx for FLAT_SCR"); + } + break; + + case AMDGPU::EXEC: + switch (Channel) { + case 0: + return AMDGPU::EXEC_LO; + case 1: + return AMDGPU::EXEC_HI; + default: + llvm_unreachable("Invalid SubIdx for EXEC"); + } + break; } unsigned Index = getHWRegIndex(Reg); |