| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Replace the existing ARM disassembler with a new one based on the FixedLenDec... | Owen Anderson | 2011-08-09 | 1 | -3894/+0 |
| * | ARM simplify the postidx_reg operand encoding. | Jim Grosbach | 2011-08-05 | 1 | -2/+8 |
| * | ARM refactoring assembly parsing of memory address operands. | Jim Grosbach | 2011-08-03 | 1 | -14/+23 |
| * | ARM SRS instruction parsing, diassembly and encoding support. | Jim Grosbach | 2011-07-29 | 1 | -10/+7 |
| * | ARM assembly parsing and encoding for RFE instruction. | Jim Grosbach | 2011-07-29 | 1 | -4/+11 |
| * | Revert r136295. It broke nightly testers because some parts of codegen weren... | Owen Anderson | 2011-07-28 | 1 | -1/+10 |
| * | Refactor and improve the encodings/decodings for addrmode3 loads, and make th... | Owen Anderson | 2011-07-27 | 1 | -10/+1 |
| * | ARM parsing and encoding of SBFX and UBFX. | Jim Grosbach | 2011-07-27 | 1 | -1/+1 |
| * | ARM cleanup of rot_imm encoding. | Jim Grosbach | 2011-07-26 | 1 | -2/+1 |
| * | ARM assembly parsing and encoding for SSAT instruction. | Jim Grosbach | 2011-07-25 | 1 | -9/+3 |
| * | ARM SSAT instruction 5-bit immediate handling. | Jim Grosbach | 2011-07-22 | 1 | -2/+0 |
| * | Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn n... | Owen Anderson | 2011-07-21 | 1 | -2/+68 |
| * | Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate A... | Evan Cheng | 2011-07-20 | 1 | -2/+4 |
| * | ARM PKH shift ammount operand printing tweaks. | Jim Grosbach | 2011-07-20 | 1 | -7/+2 |
| * | ARM: Tidy up representation of PKH instruction. | Jim Grosbach | 2011-07-20 | 1 | -1/+4 |
| * | Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues ... | Owen Anderson | 2011-07-15 | 1 | -5/+0 |
| * | Eliminate "const" from extern const to fix breakeage since r135184 on msvc. | NAKAMURA Takumi | 2011-07-15 | 1 | -1/+1 |
| * | Next round of MC refactoring. This patch factor MC table instantiations, MC | Evan Cheng | 2011-07-14 | 1 | -3/+4 |
| * | ARM ISB instruction assembly parsing. | Jim Grosbach | 2011-07-14 | 1 | -1/+1 |
| * | Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc | Evan Cheng | 2011-06-28 | 1 | -0/+1 |
| * | - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and | Evan Cheng | 2011-06-28 | 1 | -83/+83 |
| * | Fix Bug 9386 - ARM disassembler failed to disassemble conditional bx | Johnny Chen | 2011-05-22 | 1 | -3/+4 |
| * | Fix a bug in the case that there is no add or subtract symbol and the offset | Kevin Enderby | 2011-04-27 | 1 | -2/+6 |
| * | A8.6.315 VLD3 (single 3-element structure to all lanes) | Johnny Chen | 2011-04-15 | 1 | -0/+6 |
| * | The ARM disassembler did not handle the alignment correctly for VLD*DUP* inst... | Johnny Chen | 2011-04-15 | 1 | -0/+27 |
| * | Check for unallocated instruction encodings when disassembling Thumb Branch i... | Johnny Chen | 2011-04-13 | 1 | -5/+11 |
| * | Trivial comment fix. | Johnny Chen | 2011-04-11 | 1 | -1/+1 |
| * | Check invalid register encodings for LdFrm/StFrm ARM instructions and flag th... | Johnny Chen | 2011-04-11 | 1 | -0/+68 |
| * | Adding support for printing operands symbolically to llvm's public 'C' | Kevin Enderby | 2011-04-11 | 1 | -1/+80 |
| * | Fix an apparent typo that made GCC complain | Matt Beaumont-Gay | 2011-04-08 | 1 | -1/+1 |
| * | Check opcoe (dmb, dsb) instead of bitfields matching. | Johnny Chen | 2011-04-08 | 1 | -12/+1 |
| * | Hanlde the checking of bad regs for SMMLAR properly, instead of asserting. | Johnny Chen | 2011-04-08 | 1 | -9/+10 |
| * | Sanity check the option operand for DMB/DSB. | Johnny Chen | 2011-04-08 | 1 | -6/+12 |
| * | Add sanity checking for bad register specifier(s) for the DPFrm instructions. | Johnny Chen | 2011-04-08 | 1 | -0/+30 |
| * | Add sanity checking for invalid register encodings for signed/unsigned extend... | Johnny Chen | 2011-04-07 | 1 | -0/+5 |
| * | Add sanity checking for invalid register encodings for saturating instructions. | Johnny Chen | 2011-04-07 | 1 | -0/+5 |
| * | Add some more comments about checkings of invalid register numbers. | Johnny Chen | 2011-04-07 | 1 | -0/+5 |
| * | Sanity check MSRi for invalid mask values and reject it as invalid. | Johnny Chen | 2011-04-07 | 1 | -0/+5 |
| * | The ARM disassembler was not recognizing USADA8 instruction. Need to add che... | Johnny Chen | 2011-04-07 | 1 | -3/+5 |
| * | Should also check SMLAD for invalid register values. | Johnny Chen | 2011-04-07 | 1 | -6/+12 |
| * | A8.6.393 | Johnny Chen | 2011-04-06 | 1 | -26/+47 |
| * | A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP" | Johnny Chen | 2011-04-06 | 1 | -1/+14 |
| * | Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong. | Johnny Chen | 2011-04-06 | 1 | -1/+1 |
| * | Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function. | Johnny Chen | 2011-04-06 | 1 | -7/+3 |
| * | Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal... | Johnny Chen | 2011-04-05 | 1 | -1/+7 |
| * | A7.3 register encoding | Johnny Chen | 2011-04-05 | 1 | -0/+10 |
| * | ARM disassembler was erroneously accepting an invalid RSC instruction. | Johnny Chen | 2011-04-05 | 1 | -0/+6 |
| * | ARM disassembler was erroneously accepting an invalid LSL instruction. | Johnny Chen | 2011-04-05 | 1 | -0/+4 |
| * | The r128085 checkin modified the operand ordering for MRC/MRC2 instructions. | Johnny Chen | 2011-04-05 | 1 | -7/+19 |
| * | ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error. | Johnny Chen | 2011-04-05 | 1 | -2/+10 |
