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| author | Jim Grosbach <grosbach@apple.com> | 2011-07-22 23:16:18 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-07-22 23:16:18 +0000 |
| commit | 801e0a3fdebc6c2d22706967874a572846f3e5d8 (patch) | |
| tree | 67276c24f7b34d10d94cb0c5cf299359aa310f06 /llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | |
| parent | c8eab671cf3f9d3fe19f87d0ede9451072ff9866 (diff) | |
| download | bcm5719-llvm-801e0a3fdebc6c2d22706967874a572846f3e5d8.tar.gz bcm5719-llvm-801e0a3fdebc6c2d22706967874a572846f3e5d8.zip | |
ARM SSAT instruction 5-bit immediate handling.
The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield.
Update the representation such that we store the operand as 0-31, allowing us
to remove the encoder method and the special case handling in the disassembler.
Update the assembly parser and the instruction printer accordingly.
llvm-svn: 135823
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index 40e48129a8a..38c77d479db 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -1726,8 +1726,6 @@ static bool DisassembleSatFrm(MCInst &MI, unsigned Opcode, uint32_t insn, decodeRd(insn)))); unsigned Pos = slice(insn, 20, 16); - if (Opcode == ARM::SSAT || Opcode == ARM::SSAT16) - Pos += 1; MI.addOperand(MCOperand::CreateImm(Pos)); MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, |
