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* Replace the existing ARM disassembler with a new one based on the ↵Owen Anderson2011-08-091-3894/+0
| | | | | | | | | | FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
* ARM simplify the postidx_reg operand encoding.Jim Grosbach2011-08-051-2/+8
| | | | | | | The immediate portion of the operand is just a boolean (the 'U' bit indicating add vs. subtract). Treat it as such. llvm-svn: 136969
* ARM refactoring assembly parsing of memory address operands.Jim Grosbach2011-08-031-14/+23
| | | | | | | | | | | | | | | | | | | | | | Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
* ARM SRS instruction parsing, diassembly and encoding support.Jim Grosbach2011-07-291-10/+7
| | | | | | | | Fix the instruction encoding for operands. Refactor mode to use explicit instruction definitions per FIXME to be more consistent with loads/stores. Fix disassembler accordingly. Add tests. llvm-svn: 136509
* ARM assembly parsing and encoding for RFE instruction.Jim Grosbach2011-07-291-4/+11
| | | | | | | | | | | Fill in the missing fixed bits and the register operand bits of the instruction encoding. Refactor the definition to make the mode explicit, which is consistent with how loads and stores are normally represented and makes parsing much easier. Add parsing aliases for pseudo-instruction variants. Update the disassembler for the new representations. Add tests for parsing and encoding. llvm-svn: 136479
* Revert r136295. It broke nightly testers because some parts of codegen ↵Owen Anderson2011-07-281-1/+10
| | | | | | weren't aware of the changes to operand ordering. I hope to revive this sometime in the future, but it's not strictly necessary for now. llvm-svn: 136362
* Refactor and improve the encodings/decodings for addrmode3 loads, and make ↵Owen Anderson2011-07-271-10/+1
| | | | | | the writeback operand always the first. llvm-svn: 136295
* ARM parsing and encoding of SBFX and UBFX.Jim Grosbach2011-07-271-1/+1
| | | | | | | | | Encode the width operand as it encodes in the instruction, which simplifies the disassembler and the encoder, by using the imm1_32 operand def. Add a diagnostic for the context-sensitive constraint that the width must be in the range [1,32-lsb]. llvm-svn: 136264
* ARM cleanup of rot_imm encoding.Jim Grosbach2011-07-261-2/+1
| | | | | | | | Start of cleaning this up a bit. First step is to remove the encoder hook by storing the operand as the bits it'll actually encode to so it can just be directly used. Map it to the assembly source values 8/16/24 when we print it. llvm-svn: 136152
* ARM assembly parsing and encoding for SSAT instruction.Jim Grosbach2011-07-251-9/+3
| | | | | | | | | | | | Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the shift operand to correctly handle the allowed shift types and immediate ranges and issue meaningful diagnostics when an illegal value or shift type is specified. Add aliases to parse an ommitted shift operand (default value of 'lsl #0'). Add tests for diagnostics and proper encoding. llvm-svn: 135990
* ARM SSAT instruction 5-bit immediate handling.Jim Grosbach2011-07-221-2/+0
| | | | | | | | | The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield. Update the representation such that we store the operand as 0-31, allowing us to remove the encoder method and the special case handling in the disassembler. Update the assembly parser and the instruction printer accordingly. llvm-svn: 135823
* Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn ↵Owen Anderson2011-07-211-2/+68
| | | | | | necessitates a lot of changes to related bits. llvm-svn: 135722
* Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ↵Evan Cheng2011-07-201-2/+4
| | | | | | ARM MC code from target. llvm-svn: 135636
* ARM PKH shift ammount operand printing tweaks.Jim Grosbach2011-07-201-7/+2
| | | | | | | | | | Move the shift operator and special value (32 encoded as 0 for PKHTB) handling into the instruction printer. This cleans up a bit of the disassembler special casing for these instructions, more easily handles not printing the operand at all for "lsl #0" and prepares for correct asm parsing of these operands. llvm-svn: 135626
* ARM: Tidy up representation of PKH instruction.Jim Grosbach2011-07-201-1/+4
| | | | | | | | | The shift type is implied by the instruction (PKHBT vs. PKHTB) and so shouldn't be also encoded as part of the shift value immediate. Otherwise we're able to represent invalid instructions, plus it needlessly complicates the representation. Preparatory work for asm parsing of these instructions. llvm-svn: 135616
* Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues ↵Owen Anderson2011-07-151-5/+0
| | | | | | to simplify the path towards an auto-generated disassembler. llvm-svn: 135290
* Eliminate "const" from extern const to fix breakeage since r135184 on msvc.NAKAMURA Takumi2011-07-151-1/+1
| | | | | | MSVC decorates (and distinguishes) "const" in mangler. It brought linkage error between "extern const" declarations and definitions. llvm-svn: 135269
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-141-3/+4
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* ARM ISB instruction assembly parsing.Jim Grosbach2011-07-141-1/+1
| | | | | | | The ISB instruction takes an optional operand, just like DMB/DSB. Typically only 'sy' is meaningful. llvm-svn: 135156
* Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng2011-06-281-0/+1
| | | | llvm-svn: 134024
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-83/+83
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Fix Bug 9386 - ARM disassembler failed to disassemble conditional bxJohnny Chen2011-05-221-3/+4
| | | | | | | Modified the patch to .td file supplied by Jyun-Yan You. Add a test case and modified ARMDisassemblerCore.cpp a little bit. llvm-svn: 131859
* Fix a bug in the case that there is no add or subtract symbol and the offsetKevin Enderby2011-04-271-2/+6
| | | | | | value is zero so it does not add a NULL expr operand. llvm-svn: 130330
* A8.6.315 VLD3 (single 3-element structure to all lanes)Johnny Chen2011-04-151-0/+6
| | | | | | | | The a bit must be encoded as 0. rdar://problem/9292625 llvm-svn: 129618
* The ARM disassembler did not handle the alignment correctly for VLD*DUP* ↵Johnny Chen2011-04-151-0/+27
| | | | | | | | instructions (single element or n-element structure to all lanes). llvm-svn: 129550
* Check for unallocated instruction encodings when disassembling Thumb Branch ↵Johnny Chen2011-04-131-5/+11
| | | | | | | | instructions (tBcc and t2Bcc). rdar://problem/9280470 llvm-svn: 129471
* Trivial comment fix.Johnny Chen2011-04-111-1/+1
| | | | llvm-svn: 129288
* Check invalid register encodings for LdFrm/StFrm ARM instructions and flag ↵Johnny Chen2011-04-111-0/+68
| | | | | | | | them as invalid instructions. llvm-svn: 129286
* Adding support for printing operands symbolically to llvm's public 'C'Kevin Enderby2011-04-111-1/+80
| | | | | | | | | | | | | disassembler API. Hooked this up to the ARM target so such tools as Darwin's otool(1) can now print things like branch targets for example this: blx _puts instead of this: blx #-36 And even print the expression encoded in the Mach-O relocation entried for things like this: movt r0, :upper16:((_foo-_bar)+1234) llvm-svn: 129284
* Fix an apparent typo that made GCC complainMatt Beaumont-Gay2011-04-081-1/+1
| | | | llvm-svn: 129160
* Check opcoe (dmb, dsb) instead of bitfields matching.Johnny Chen2011-04-081-12/+1
| | | | llvm-svn: 129148
* Hanlde the checking of bad regs for SMMLAR properly, instead of asserting.Johnny Chen2011-04-081-9/+10
| | | | | | | PR9650 rdar://problem/9257565 llvm-svn: 129147
* Sanity check the option operand for DMB/DSB.Johnny Chen2011-04-081-6/+12
| | | | | | | PR9648 rdar://problem/9257634 llvm-svn: 129146
* Add sanity checking for bad register specifier(s) for the DPFrm instructions.Johnny Chen2011-04-081-0/+30
| | | | | | Add more test cases to exercise the logical branches related to the above change. llvm-svn: 129117
* Add sanity checking for invalid register encodings for signed/unsigned ↵Johnny Chen2011-04-071-0/+5
| | | | | | | | extend instructions. Add some test cases. llvm-svn: 129098
* Add sanity checking for invalid register encodings for saturating instructions.Johnny Chen2011-04-071-0/+5
| | | | llvm-svn: 129096
* Add some more comments about checkings of invalid register numbers.Johnny Chen2011-04-071-0/+5
| | | | | | And two test cases. llvm-svn: 129090
* Sanity check MSRi for invalid mask values and reject it as invalid.Johnny Chen2011-04-071-0/+5
| | | | | | rdar://problem/9246844 llvm-svn: 129050
* The ARM disassembler was not recognizing USADA8 instruction. Need to add ↵Johnny Chen2011-04-071-3/+5
| | | | | | | | | | checking for register values for USAD8 and USADA8. rdar://problem/9247060 llvm-svn: 129047
* Should also check SMLAD for invalid register values.Johnny Chen2011-04-071-6/+12
| | | | | | rdar://problem/9246650 llvm-svn: 129042
* A8.6.393Johnny Chen2011-04-061-26/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | The ARM disassembler should reject invalid (type, align) encodings as invalid instructions. So, instead of: Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| ------------------------------------------------------------------------------------------------- vst2.32 {d0, d2}, [r3, :256], r3 we now have: Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| ------------------------------------------------------------------------------------------------- mc-input.txt:1:1: warning: invalid instruction encoding 0xb3 0x9 0x3 0xf4 ^ llvm-svn: 129033
* A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"Johnny Chen2011-04-061-1/+14
| | | | | | | | | | Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits specified, if coproc == 10 or 11, we should reject the insn as invalid. rdar://problem/9239922 rdar://problem/9239596 llvm-svn: 129027
* Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong.Johnny Chen2011-04-061-1/+1
| | | | | | | | | Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000, in class NVLaneOp. rdar://problem/9240648 llvm-svn: 129015
* Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function.Johnny Chen2011-04-061-7/+3
| | | | | | | | | | Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25}) is 1, Inst{4} should be 0. Otherwise, we should reject the insn as invalid. rdar://problem/9239347 rdar://problem/9239467 llvm-svn: 128977
* Fix a typo in the handling of PKHTB opcode, plus add sanity check for ↵Johnny Chen2011-04-051-1/+7
| | | | | | | | | | illegal register encodings for DisassembleArithMiscFrm(). rdar://problem/9238659 llvm-svn: 128958
* A7.3 register encodingJohnny Chen2011-04-051-0/+10
| | | | | | | | | | | | | Qd -> bit[12] == 0 Qn -> bit[16] == 0 Qm -> bit[0] == 0 If one of these bits is 1, the instruction is UNDEFINED. rdar://problem/9238399 rdar://problem/9238445 llvm-svn: 128949
* ARM disassembler was erroneously accepting an invalid RSC instruction.Johnny Chen2011-04-051-0/+6
| | | | | | | | Added checks for regs which should not be 15. rdar://problem/9237734 llvm-svn: 128945
* ARM disassembler was erroneously accepting an invalid LSL instruction.Johnny Chen2011-04-051-0/+4
| | | | | | | | | For register-controlled shifts, we should check that the encoding constraint Inst{7} = 0 and Inst{4} = 1 is satisfied. rdar://problem/9237693 llvm-svn: 128941
* The r128085 checkin modified the operand ordering for MRC/MRC2 instructions.Johnny Chen2011-04-051-7/+19
| | | | | | | | Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change. rdar://problem/9236873 llvm-svn: 128922
* ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error.Johnny Chen2011-04-051-2/+10
| | | | llvm-svn: 128913
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