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* CMake: Make most target symbols hidden by defaultTom Stellard2020-01-141-1/+1
* [ARM][Thumb2] Fix ADD/SUB invalid writes to SPDiogo Sampaio2020-01-141-4/+69
* [Disassembler] Delete the VStream parameter of MCDisassembler::getInstruction()Fangrui Song2020-01-111-13/+7
* Reverting, broke some bots. Need further investigation.Diogo Sampaio2020-01-101-69/+4
* [ARM][Thumb2] Fix ADD/SUB invalid writes to SPDiogo Sampaio2020-01-101-4/+69
* [cmake] Explicitly mark libraries defined in lib/ as "Component Libraries"Tom Stellard2019-11-211-1/+1
* [ARM][MVE] Decoding of uqrshl and sqrshl accepts unpredictable encodingsOliver Stannard2019-09-091-0/+6
* [ARM] MVE VPNOTDavid Green2019-07-281-0/+10
* [ARM] Rename NEONModImm to VMOVModImm. NFCDavid Green2019-07-231-4/+4
* [ARM] Add <saturate> operand to SQRSHRL and UQRSHLLMikhail Maltsev2019-07-191-0/+7
* [ARM] Fix integer UB in MVE load/store immediate handling.Simon Tatham2019-06-281-2/+2
* [ARM] Fix handling of zero offsets in LOB instructions.Simon Tatham2019-06-271-8/+8
* [ARM] Make coprocessor number restrictions consistent.Simon Tatham2019-06-271-8/+1
* [ARM] Tighten restrictions on use of SP in v8.1-M CSEL.Simon Tatham2019-06-271-1/+13
* [ARM] Add remaining miscellaneous MVE instructions.Simon Tatham2019-06-251-1/+22
* [ARM] Add MVE vector load/store instructions.Simon Tatham2019-06-251-0/+157
* [ARM] Add MVE interleaving load/store family.Simon Tatham2019-06-241-0/+36
* Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.Simon Pilgrim2019-06-211-1/+1
* [ARM] Add MVE 64-bit GPR <-> vector move instructions.Simon Tatham2019-06-211-0/+69
* [ARM] Add MVE vector instructions that take a scalar input.Simon Tatham2019-06-211-0/+29
* [ARM] Add a batch of similarly encoded MVE instructions.Simon Tatham2019-06-211-0/+27
* [ARM] Fix -Wimplicit-fallthrough after D62675Fangrui Song2019-06-211-0/+2
* [ARM] Add MVE vector compare instructions.Simon Tatham2019-06-211-0/+43
* [ARM] Add a batch of MVE floating-point instructions.Simon Tatham2019-06-211-0/+49
* [ARM] Add a batch of MVE integer instructions.Simon Tatham2019-06-201-0/+31
* [llvm-objdump] Switch between ARM/Thumb based on mapping symbols.Eli Friedman2019-06-201-29/+28
* [ARM] Add MVE vector bit-operations (register inputs).Simon Tatham2019-06-191-0/+14
* [ARM] Rename MVE instructions in Tablegen for consistency.Simon Tatham2019-06-181-6/+6
* [ARM] Set up infrastructure for MVE vector instructions.Simon Tatham2019-06-131-26/+265
* [ARM] Refactor handling of IT mask operands.Simon Tatham2019-06-131-9/+16
* [ARM] First MVE instructions: scalar shifts.Mikhail Maltsev2019-06-111-0/+118
* [ARM] Add the non-MVE instructions in Arm v8.1-M.Simon Tatham2019-06-111-15/+351
* Revert CMake: Make most target symbols hidden by defaultTom Stellard2019-06-111-1/+1
* CMake: Make most target symbols hidden by defaultTom Stellard2019-06-101-1/+1
* Revert rL362953 and its followup rL362955.Simon Tatham2019-06-101-351/+15
* [ARM] Add the non-MVE instructions in Arm v8.1-M.Simon Tatham2019-06-101-15/+351
* [ARM] Replace fp-only-sp and d16 with fp64 and d32.Simon Tatham2019-05-281-2/+2
* [ARM] Create a TargetInfo header. NFCRichard Trieu2019-05-141-0/+1
* ARM: disallow add/sub to sp unless Rn is also sp.Tim Northover2019-04-231-1/+13
* [ARM][FIX] Fix vfmal.f16 and vfmsl.f16 operandDiogo N. Sampaio2019-03-081-0/+9
* [ARM] Make fullfp16 instructions not conditionalisable.Simon Tatham2019-02-251-4/+12
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-192-8/+6
* Remove trailing spaceFangrui Song2018-07-301-5/+5
* ARM: correctly decode VFP instructions following unpredictable t2ITTim Northover2018-06-261-0/+2
* ARM: diagnose unpredictable IT instructionsTim Northover2018-06-261-1/+4
* [ARM]Decoding MSR with unpredictable destination register causes an assertSimi Pallipurath2018-03-061-2/+3
* [ARM] Re-commit r324600 with fixed LLVMBuild.txtOliver Stannard2018-02-082-10/+3
* Revert r324600 as it breaks a buildbotOliver Stannard2018-02-081-2/+9
* [ARM] Fix disassembly of invalid banked register movesOliver Stannard2018-02-081-9/+2
* [ARM] Armv8.2-A FP16 code generation (part 1/3)Sjoerd Meijer2018-01-261-0/+7
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