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| author | Johnny Chen <johnny.chen@apple.com> | 2011-04-06 01:18:32 +0000 |
|---|---|---|
| committer | Johnny Chen <johnny.chen@apple.com> | 2011-04-06 01:18:32 +0000 |
| commit | 0ec0e98a6ab3692754245ed20b5494777fe9fdc5 (patch) | |
| tree | 907fbedef8bf594bab69094ff9ca3450eca0b2f6 /llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | |
| parent | ae6a89a89085b54a9b520ab4cc82024977898322 (diff) | |
| download | bcm5719-llvm-0ec0e98a6ab3692754245ed20b5494777fe9fdc5.tar.gz bcm5719-llvm-0ec0e98a6ab3692754245ed20b5494777fe9fdc5.zip | |
Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function.
Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25})
is 1, Inst{4} should be 0. Otherwise, we should reject the insn as invalid.
rdar://problem/9239347
rdar://problem/9239467
llvm-svn: 128977
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index 8c89505a20f..509a01949d5 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -547,7 +547,7 @@ static bool BadRegsMulFrm(unsigned Opcode, uint32_t insn) { return false; case ARM::SMLAL: case ARM::SMULL: case ARM::UMAAL: case ARM::UMLAL: case ARM::UMULL: case ARM::SMLALBB: case ARM::SMLALBT: case ARM::SMLALTB: - case ARM::SMLALTT: case ARM::SMLSLD: + case ARM::SMLALTT: case ARM::SMLSLD: case ARM::SMLSLDX: if (R19_16 == 15 || R15_12 == 15 || R11_8 == 15 || R3_0 == 15) return true; if (R19_16 == R15_12) @@ -1201,12 +1201,8 @@ static bool DisassembleLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn, } OpIdx += 1; } else { - // The opcode ARM::LDRT actually corresponds to both Encoding A1 and A2 of - // A8.6.86 LDRT. So if Inst{4} != 0 while Inst{25} (getIBit(insn)) == 1, - // we should reject this insn as invalid. - // - // Ditto for LDRBT. - if ((Opcode == ARM::LDRT || Opcode == ARM::LDRBT) && (slice(insn,4,4) == 1)) + // If Inst{25} = 1 and Inst{4} != 0, we should reject this as invalid. + if (slice(insn,4,4) == 1) return false; // Disassemble the offset reg (Rm), shift type, and immediate shift length. |
