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* Update for feedback from Jim.Owen Anderson2011-08-261-3/+3
| | | | llvm-svn: 138642
* ARMDisassembler: Always return a size, even when disassembling fails.Benjamin Kramer2011-08-261-3/+11
| | | | | | This should fix PR10772. llvm-svn: 138636
* Support an extension of ARM asm syntax to allow immediate operands to ADR ↵Owen Anderson2011-08-261-6/+9
| | | | | | instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here. llvm-svn: 138635
* Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT ↵Owen Anderson2011-08-261-0/+2
| | | | | | | | instructions when decoding their successors. This is the last disassembly crash detected by exhaustive Thumb2 instruction space. Major thanks to Chandler Carruth for making this kind of exhaustive testing possible. llvm-svn: 138625
* Port over additional encoding tests to decoding tests, and fix an operand ↵Owen Anderson2011-08-251-1/+1
| | | | | | ordering bug this exposed. llvm-svn: 138575
* Perform more thorough checking of t2IT mask parameters, which fixes all ↵Owen Anderson2011-08-241-0/+13
| | | | | | remaining crashers when disassembling the entire 16-bit instruction space. llvm-svn: 138507
* Be careful not to walk off the end of the operand info list while updating ↵Owen Anderson2011-08-241-1/+2
| | | | | | VFP predicates. llvm-svn: 138492
* Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng2011-08-241-1/+1
| | | | | | These are strictly utilities for registering targets and components. llvm-svn: 138450
* Be stricter in enforcing IT instruction predicate values, so that we don't ↵Owen Anderson2011-08-241-0/+14
| | | | | | end up trying to print out an illegal predicate. llvm-svn: 138443
* Fix decoding of Thumb2 prefetch instructions, which account for all the ↵Owen Anderson2011-08-231-3/+9
| | | | | | remaining Thumb2 decoding failures found by randomized testing so far. llvm-svn: 138341
* Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same ↵Owen Anderson2011-08-231-9/+43
| | | | | | instructions. llvm-svn: 138339
* Reject invalid imod values in t2CPS instructions.Owen Anderson2011-08-221-1/+10
| | | | llvm-svn: 138306
* Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming ↵Owen Anderson2011-08-221-0/+45
| | | | | | majority of decoder crashes detected by randomized testing. llvm-svn: 138269
* Fix another batch of VLD/VST decoding crashes discovered by randomized testing.Owen Anderson2011-08-221-16/+40
| | | | llvm-svn: 138255
* Correct writeback handling of duplicating VLD instructions. Discovered by ↵Owen Anderson2011-08-221-4/+4
| | | | | | randomized testing. llvm-svn: 138251
* Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add ↵Owen Anderson2011-08-221-1/+1
| | | | | | more tests. llvm-svn: 138246
* STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST ↵Owen Anderson2011-08-181-0/+4
| | | | | | | | for the purposes of decoding all operands except the predicate. Found by randomized testing. llvm-svn: 138003
* Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs ↵Owen Anderson2011-08-181-8/+42
| | | | | | have it unset. llvm-svn: 138000
* Remember to fill in some operands so we can print _something_ coherent even ↵Owen Anderson2011-08-181-1/+4
| | | | | | when decoding the CPS instruction soft-fails. llvm-svn: 137997
* Improve handling of failure and unpredictable cases for CPS, STR, and SMLA ↵Owen Anderson2011-08-181-11/+18
| | | | | | | | instructions. Fixes a large class of disassembler crashes found by randomized testing. llvm-svn: 137995
* Tidy up. 80 columns.Jim Grosbach2011-08-171-34/+49
| | | | llvm-svn: 137881
* ARM clean up the imm_sr operand class representation.Jim Grosbach2011-08-171-11/+0
| | | | | | | | | Represent the operand value as it will be encoded in the instruction. This allows removing the specialized encoder and decoder methods entirely. Add an assembler match class while we're at it to lay groundwork for parsing the thumb shift instructions. llvm-svn: 137879
* Be more careful in the Thumb decoder hooks to avoid walking off the end of ↵Owen Anderson2011-08-171-8/+12
| | | | | | the OpInfo array. llvm-svn: 137838
* Allow the MCDisassembler to return a "soft fail" status code, indicating an ↵Owen Anderson2011-08-171-582/+649
| | | | | | | | instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment. Patch by James Molloy. llvm-svn: 137830
* Separate out Thumb1 instructions that need an S bit operand from those that ↵Owen Anderson2011-08-161-0/+8
| | | | | | do not, for the purposes of decoding them. llvm-svn: 137787
* Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the ↵Owen Anderson2011-08-151-16/+21
| | | | | | Thumb2 NEON decoding hooks to bring us closer to correctness. llvm-svn: 137686
* Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM ↵Owen Anderson2011-08-151-0/+15
| | | | | | | | mode. Update tests to reflect this fact. Patch by James Molloy. llvm-svn: 137647
* Fix problems decoding the to/from-lane NEON memory instructions, and add a ↵Owen Anderson2011-08-151-0/+460
| | | | | | comprehensive NEON decoding testcase. llvm-svn: 137635
* Fix some remaining issues with decoding ARM-mode memory instructions, and ↵Owen Anderson2011-08-121-19/+10
| | | | | | add another batch of tests. llvm-svn: 137502
* Fix decoding of ARM-mode STRH.Owen Anderson2011-08-121-0/+3
| | | | llvm-svn: 137499
* Fix decoding of pre-indexed stores.Owen Anderson2011-08-121-0/+41
| | | | llvm-svn: 137487
* Separate decoding for STREXD and LDREXD to make each work better.Owen Anderson2011-08-121-5/+22
| | | | llvm-svn: 137476
* ARM STRT assembly parsing and encoding.Jim Grosbach2011-08-111-2/+2
| | | | llvm-svn: 137372
* Add another accidentally omitted predicate operand.Owen Anderson2011-08-111-0/+2
| | | | llvm-svn: 137370
* Add missing predicate operand on SMLA and friends.Owen Anderson2011-08-111-0/+2
| | | | llvm-svn: 137368
* Fix decoding support for STREXD and LDREXD.Owen Anderson2011-08-111-0/+23
| | | | llvm-svn: 137356
* Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.Owen Anderson2011-08-111-0/+4
| | | | llvm-svn: 137347
* Continue to tighten decoding by performing more operand validation.Owen Anderson2011-08-111-0/+10
| | | | llvm-svn: 137340
* ARM STRBT assembly parsing and encoding.Jim Grosbach2011-08-111-2/+2
| | | | llvm-svn: 137337
* Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.Owen Anderson2011-08-111-0/+2
| | | | llvm-svn: 137325
* Tighten operand decoding of addrmode2 instruction. The offset register ↵Owen Anderson2011-08-111-1/+1
| | | | | | cannot be PC. llvm-svn: 137323
* Improve error checking in the new ARM disassembler. Patch by James Molloy.Owen Anderson2011-08-111-116/+159
| | | | llvm-svn: 137320
* ARM LDRT assembly parsing and encoding.Jim Grosbach2011-08-101-2/+2
| | | | llvm-svn: 137282
* Add initial support for decoding NEON instructions in Thumb2 mode.Owen Anderson2011-08-101-2/+52
| | | | llvm-svn: 137236
* Cleanups based on Nick Lewycky's feedback.Owen Anderson2011-08-101-19/+22
| | | | llvm-svn: 137224
* Push GPRnopc through a large number of instruction definitions to tighten ↵Owen Anderson2011-08-101-4/+4
| | | | | | operand decoding. llvm-svn: 137189
* Tighten operand checking of register-shifted-register operands.Owen Anderson2011-08-091-2/+2
| | | | llvm-svn: 137180
* Tighten operand checking on memory barrier instructions.Owen Anderson2011-08-091-2/+24
| | | | llvm-svn: 137176
* Tighten operand checking on CPS instructions.Owen Anderson2011-08-091-0/+5
| | | | llvm-svn: 137172
* Create a new register class for the set of all GPRs except the PC. Use it ↵Owen Anderson2011-08-091-0/+8
| | | | | | to tighten our decoding of BFI. llvm-svn: 137168
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