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authorOwen Anderson <resistor@mac.com>2011-08-09 23:05:39 +0000
committerOwen Anderson <resistor@mac.com>2011-08-09 23:05:39 +0000
commit3d2e0e9db69da97b159c4788f0b1200bc901ebc4 (patch)
tree45377074620d29f6106152a5930263b8edc3ce22 /llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
parentecc4ffc9414c90b205c54f6851b4a08aaec4f366 (diff)
downloadbcm5719-llvm-3d2e0e9db69da97b159c4788f0b1200bc901ebc4.tar.gz
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Tighten operand checking on CPS instructions.
llvm-svn: 137172
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
-rw-r--r--llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp5
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index d7b88560d71..a3fa138ba64 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -83,6 +83,8 @@ static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
const void *Decoder);
static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
+static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder);
static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
@@ -1139,6 +1141,9 @@ static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
unsigned mode = fieldFromInstruction32(Insn, 0, 5);
+ // imod == '01' --> UNPREDICTABLE
+ if (imod == 1) return false;
+
if (M && mode && imod && iflags) {
Inst.setOpcode(ARM::CPS3p);
Inst.addOperand(MCOperand::CreateImm(imod));
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