Fix decoding support for STREXD and LDREXD.

llvm-svn: 137356

1 files changed, 23 insertions, 0 deletions

diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index d2809f0c2c9..e4d7393bebd 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -135,6 +135,8 @@ static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
 static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
+static bool DecodeDoubleRegExclusive(llvm::MCInst &Inst, unsigned Insn,
+                               uint64_t Address, const void *Decoder);
 
 
 static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
@@ -2481,3 +2483,24 @@ static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
   Inst.addOperand(MCOperand::CreateImm(Val));
   return true;
 }
+
+static bool DecodeDoubleRegExclusive(llvm::MCInst &Inst, unsigned Insn,
+                                          uint64_t Address, const void *Decoder) {
+  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
+  unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
+  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+
+  if (Inst.getOpcode() == ARM::STREXD)
+    if (!DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+
+  if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false;
+  if (Rd == Rn || Rd == Rt || Rd == Rt+1) return false;
+
+  if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false;
+  if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false;
+  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+
+  return true;
+}
+
+