| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Update for feedback from Jim. | Owen Anderson | 2011-08-26 | 1 | -3/+3 |
| * | ARMDisassembler: Always return a size, even when disassembling fails. | Benjamin Kramer | 2011-08-26 | 1 | -3/+11 |
| * | Support an extension of ARM asm syntax to allow immediate operands to ADR ins... | Owen Anderson | 2011-08-26 | 1 | -6/+9 |
| * | Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT i... | Owen Anderson | 2011-08-26 | 1 | -0/+2 |
| * | Port over additional encoding tests to decoding tests, and fix an operand ord... | Owen Anderson | 2011-08-25 | 1 | -1/+1 |
| * | Perform more thorough checking of t2IT mask parameters, which fixes all remai... | Owen Anderson | 2011-08-24 | 1 | -0/+13 |
| * | Be careful not to walk off the end of the operand info list while updating VF... | Owen Anderson | 2011-08-24 | 1 | -1/+2 |
| * | Move TargetRegistry and TargetSelect from Target to Support where they belong. | Evan Cheng | 2011-08-24 | 1 | -1/+1 |
| * | Be stricter in enforcing IT instruction predicate values, so that we don't en... | Owen Anderson | 2011-08-24 | 1 | -0/+14 |
| * | Fix decoding of Thumb2 prefetch instructions, which account for all the remai... | Owen Anderson | 2011-08-23 | 1 | -3/+9 |
| * | Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same in... | Owen Anderson | 2011-08-23 | 1 | -9/+43 |
| * | Reject invalid imod values in t2CPS instructions. | Owen Anderson | 2011-08-22 | 1 | -1/+10 |
| * | Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming major... | Owen Anderson | 2011-08-22 | 1 | -0/+45 |
| * | Fix another batch of VLD/VST decoding crashes discovered by randomized testing. | Owen Anderson | 2011-08-22 | 1 | -16/+40 |
| * | Correct writeback handling of duplicating VLD instructions. Discovered by ra... | Owen Anderson | 2011-08-22 | 1 | -4/+4 |
| * | Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add ... | Owen Anderson | 2011-08-22 | 1 | -1/+1 |
| * | STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST fo... | Owen Anderson | 2011-08-18 | 1 | -0/+4 |
| * | Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs ... | Owen Anderson | 2011-08-18 | 1 | -8/+42 |
| * | Remember to fill in some operands so we can print _something_ coherent even w... | Owen Anderson | 2011-08-18 | 1 | -1/+4 |
| * | Improve handling of failure and unpredictable cases for CPS, STR, and SMLA in... | Owen Anderson | 2011-08-18 | 1 | -11/+18 |
| * | Tidy up. 80 columns. | Jim Grosbach | 2011-08-17 | 1 | -34/+49 |
| * | ARM clean up the imm_sr operand class representation. | Jim Grosbach | 2011-08-17 | 1 | -11/+0 |
| * | Be more careful in the Thumb decoder hooks to avoid walking off the end of th... | Owen Anderson | 2011-08-17 | 1 | -8/+12 |
| * | Allow the MCDisassembler to return a "soft fail" status code, indicating an i... | Owen Anderson | 2011-08-17 | 1 | -582/+649 |
| * | Separate out Thumb1 instructions that need an S bit operand from those that d... | Owen Anderson | 2011-08-16 | 1 | -0/+8 |
| * | Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2... | Owen Anderson | 2011-08-15 | 1 | -16/+21 |
| * | Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM ... | Owen Anderson | 2011-08-15 | 1 | -0/+15 |
| * | Fix problems decoding the to/from-lane NEON memory instructions, and add a co... | Owen Anderson | 2011-08-15 | 1 | -0/+460 |
| * | Fix some remaining issues with decoding ARM-mode memory instructions, and add... | Owen Anderson | 2011-08-12 | 1 | -19/+10 |
| * | Fix decoding of ARM-mode STRH. | Owen Anderson | 2011-08-12 | 1 | -0/+3 |
| * | Fix decoding of pre-indexed stores. | Owen Anderson | 2011-08-12 | 1 | -0/+41 |
| * | Separate decoding for STREXD and LDREXD to make each work better. | Owen Anderson | 2011-08-12 | 1 | -5/+22 |
| * | ARM STRT assembly parsing and encoding. | Jim Grosbach | 2011-08-11 | 1 | -2/+2 |
| * | Add another accidentally omitted predicate operand. | Owen Anderson | 2011-08-11 | 1 | -0/+2 |
| * | Add missing predicate operand on SMLA and friends. | Owen Anderson | 2011-08-11 | 1 | -0/+2 |
| * | Fix decoding support for STREXD and LDREXD. | Owen Anderson | 2011-08-11 | 1 | -0/+23 |
| * | Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>. | Owen Anderson | 2011-08-11 | 1 | -0/+4 |
| * | Continue to tighten decoding by performing more operand validation. | Owen Anderson | 2011-08-11 | 1 | -0/+10 |
| * | ARM STRBT assembly parsing and encoding. | Jim Grosbach | 2011-08-11 | 1 | -2/+2 |
| * | Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases. | Owen Anderson | 2011-08-11 | 1 | -0/+2 |
| * | Tighten operand decoding of addrmode2 instruction. The offset register canno... | Owen Anderson | 2011-08-11 | 1 | -1/+1 |
| * | Improve error checking in the new ARM disassembler. Patch by James Molloy. | Owen Anderson | 2011-08-11 | 1 | -116/+159 |
| * | ARM LDRT assembly parsing and encoding. | Jim Grosbach | 2011-08-10 | 1 | -2/+2 |
| * | Add initial support for decoding NEON instructions in Thumb2 mode. | Owen Anderson | 2011-08-10 | 1 | -2/+52 |
| * | Cleanups based on Nick Lewycky's feedback. | Owen Anderson | 2011-08-10 | 1 | -19/+22 |
| * | Push GPRnopc through a large number of instruction definitions to tighten ope... | Owen Anderson | 2011-08-10 | 1 | -4/+4 |
| * | Tighten operand checking of register-shifted-register operands. | Owen Anderson | 2011-08-09 | 1 | -2/+2 |
| * | Tighten operand checking on memory barrier instructions. | Owen Anderson | 2011-08-09 | 1 | -2/+24 |
| * | Tighten operand checking on CPS instructions. | Owen Anderson | 2011-08-09 | 1 | -0/+5 |
| * | Create a new register class for the set of all GPRs except the PC. Use it to... | Owen Anderson | 2011-08-09 | 1 | -0/+8 |
