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| author | Owen Anderson <resistor@mac.com> | 2011-08-11 22:08:38 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-08-11 22:08:38 +0000 |
| commit | ff0b4423301bc241d0e61fc6cfdfe3554b34b804 (patch) | |
| tree | b2104b8875fba0913cd2825044e64b96917fd4f8 /llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | 228b5fefbb8646e5627e050987d12d9615601637 (diff) | |
| download | bcm5719-llvm-ff0b4423301bc241d0e61fc6cfdfe3554b34b804.tar.gz bcm5719-llvm-ff0b4423301bc241d0e61fc6cfdfe3554b34b804.zip | |
Add another accidentally omitted predicate operand.
llvm-svn: 137370
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index b5adc4977e6..240293a2e67 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -2491,6 +2491,7 @@ static bool DecodeDoubleRegExclusive(llvm::MCInst &Inst, unsigned Insn, unsigned Rd = fieldFromInstruction32(Insn, 12, 4); unsigned Rt = fieldFromInstruction32(Insn, 0, 4); unsigned Rn = fieldFromInstruction32(Insn, 16, 4); + unsigned pred = fieldFromInstruction32(Insn, 28, 4); if (Inst.getOpcode() == ARM::STREXD) if (!DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)) return false; @@ -2501,6 +2502,7 @@ static bool DecodeDoubleRegExclusive(llvm::MCInst &Inst, unsigned Insn, if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false; if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; + if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; return true; } |
