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| author | Owen Anderson <resistor@mac.com> | 2011-08-09 22:48:45 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-08-09 22:48:45 +0000 |
| commit | 042619f97d1060841eb196f3f6c113358de8c1fe (patch) | |
| tree | c44a6ff005cef85ca6578e7c948eb08659f2d9f7 /llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | 1c49954b513cc2c8057968d1352131776dafdefa (diff) | |
| download | bcm5719-llvm-042619f97d1060841eb196f3f6c113358de8c1fe.tar.gz bcm5719-llvm-042619f97d1060841eb196f3f6c113358de8c1fe.zip | |
Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI.
llvm-svn: 137168
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 307ce885369..d7b88560d71 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -28,6 +28,8 @@ // Definitions are further down. static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); +static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, + uint64_t Address, const void *Decoder); static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, @@ -471,6 +473,12 @@ static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, return true; } +static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) { + if (RegNo == 15) return false; + return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); +} + static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 7) |
