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path: root/llvm/lib/Target/ARM/ARMISelLowering.cpp
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* [ARM] Adjust isLegalT1AddressImmediate for non-legal typesDavid Green2019-06-081-2/+2
* [ARM] Add MVE addressing to isLegalT2AddressImmediateDavid Green2019-06-081-1/+20
* [ARM] Add fp16 addressing to isLegalT2AddressImmediateDavid Green2019-06-081-0/+3
* [ARM][FIX] Ran out of registers due tail recursionDiogo N. Sampaio2019-06-031-40/+37
* [ARM] LowerVECTOR_SHUFFLE - fix uninitialized variable warnings. NFCI.Simon Pilgrim2019-05-301-4/+4
* [ARM] Replace fp-only-sp and d16 with fp64 and d32.Simon Tatham2019-05-281-35/+35
* [AMDGPU] Divergence driven ISel. Assign register class for cross block va...Alexander Timofeev2019-05-261-1/+3
* [ARM] Select a number of fp16 rounding functionsDavid Green2019-05-261-0/+2
* [ARM] Promote various fp16 math intrinsicsDavid Green2019-05-261-0/+11
* [ARM] Promote fp16 fremDavid Green2019-05-261-0/+5
* Revert r361644, "[AMDGPU] Divergence driven ISel. Assign register class for c...Peter Collingbourne2019-05-251-3/+1
* [AMDGPU] Divergence driven ISel. Assign register class for cross block values...Alexander Timofeev2019-05-241-1/+3
* [ARM] Don't use the Machine Scheduler for cortex-m at minsizeDavid Green2019-05-151-1/+1
* [ARM] Glue register copies to tail calls.Eli Friedman2019-05-061-26/+4
* [TargetLowering] Change getOptimalMemOpType to take a function attribute listSjoerd Meijer2019-04-301-8/+5
* [ARM] Rewrite isLegalT2AddressImmediateDavid Green2019-04-211-29/+24
* [TargetLowering] Rename preferShiftsToClearExtremeBits and shouldFoldShiftPai...Simon Pilgrim2019-04-161-3/+2
* [IR] Refactor attribute methods in Function class (NFC)Evandro Menezes2019-04-041-4/+4
* [ARM] Optimize expressions like "return x != 0;" for Thumb1.Eli Friedman2019-04-021-11/+13
* [ARM] Add missing memory operands to a bunch of instructions.Eli Friedman2019-03-251-3/+9
* [Thumb] Fix infinite loop in ABS expansion (PR41160)Simon Pilgrim2019-03-211-1/+4
* Fix unused variable warning. NFCI.Simon Pilgrim2019-03-191-2/+1
* [SelectionDAG] Handle unary SelectPatternFlavor for ABS case in SelectionDAGB...Simon Pilgrim2019-03-191-0/+54
* [TargetLowering] Add code size information on isFPImmLegal. NFCAdhemerval Zanella2019-03-181-1/+2
* [ARM] Fixed an assumption of power-of-2 vector MVTTim Renouf2019-03-171-6/+6
* [ARM] Sink zext/sext operands for add and sub to enable vsubl generation.Florian Hahn2019-03-061-0/+42
* [ARM] Fix select_cc lowering for fp16Oliver Stannard2019-03-051-7/+11
* [ARM] Consider undefined-on-NaN conditions in checkVSELConstraintsOliver Stannard2019-03-011-5/+6
* [Target][ARM] Add a usage for SrcSz to unbreak build-bots without assertionsKadir Cetinkaya2019-02-281-0/+1
* Add support for computing "zext of value" in KnownBits. NFCIBjorn Pettersson2019-02-281-2/+1
* [ARM] Add OptMinSize to ARMSubtargetSam Parker2019-02-081-9/+12
* [opaque pointer types] Pass value type to GetElementPtr creation.James Y Knight2019-02-011-3/+5
* [ARM] Deduplicate table generated CC analysis codeReid Kleckner2019-01-281-2/+0
* Reapply "IR: Add fp operations to atomicrmw"Matt Arsenault2019-01-221-0/+3
* Revert r351778: IR: Add fp operations to atomicrmwChandler Carruth2019-01-221-3/+0
* IR: Add fp operations to atomicrmwMatt Arsenault2019-01-221-0/+3
* [ARM] Combine ands+lsls to lsls+lsrs for Thumb1.Eli Friedman2019-01-221-4/+60
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [ARM] ComputeKnownBits to handle extract vectorsDiogo N. Sampaio2019-01-071-0/+27
* [ARM] Always use the version of computeKnownBits that returns a value. NFCI.Simon Pilgrim2018-12-211-8/+5
* [ARM] Complete the Thumb1 shift+and->shift+shift transforms.Eli Friedman2018-12-201-7/+46
* ARM: use acquire/release instruction variants when available.Tim Northover2018-12-171-1/+2
* ARM: use target-specific SUBS node when combining cmp with cmov.Tim Northover2018-12-031-11/+20
* [ARM] Don't expand sdiv when optimising for minsizeSjoerd Meijer2018-11-301-0/+44
* [ARM] Fix CPSR liveness in tMOVCCr_pseudo lowering.Eli Friedman2018-11-071-0/+44
* [NFC] Rename minnan and maxnan to minimum and maximumThomas Lively2018-10-241-13/+13
* ARM: Use BKPT instead of TRAP to implement llvm.debugtrap.Peter Collingbourne2018-10-241-0/+1
* ARM: handle checking aliases with out-of-bounds GEPsSaleem Abdulrasool2018-10-241-3/+5
* [ARM][NEON] Improve vector popcnt lowering with PADDL (PR39281)Simon Pilgrim2018-10-151-130/+26
* [ARM] Fix correctness checks in promoteToConstantPool.Eli Friedman2018-09-281-46/+15
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