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path: root/llvm/lib/Target/ARM/ARMISelLowering.cpp
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* [ARM] Only produce qadd8b under hasV6OpsDavid Green2020-05-191-1/+1
* Don't generate libcalls for wide shift on Windows ARM (PR42711)Hans Wennborg2020-02-251-1/+1
* [FPEnv][ARM] Don't call mutateStrictFPToFP when loweringJohn Brawn2020-02-181-2/+10
* [ARM] Fix infinite loop when lowering STRICT_FP_EXTENDJohn Brawn2020-02-181-0/+9
* [FPEnv][ARM] Add lowering of STRICT_FSETCC and STRICT_FSETCCSJohn Brawn2020-02-181-3/+63
* Revert "[ARM] Improve codegen of volatile load/store of i64"Victor Campos2020-02-081-55/+2
* [TargetLowering][ARM][Mips][WebAssembly] Remove the ordered FP compare from R...Craig Topper2020-01-101-4/+0
* CodeGen: Use LLT instead of EVT in getRegisterByNameMatt Arsenault2020-01-091-1/+1
* [ARM] Improve codegen of volatile load/store of i64Victor Campos2020-01-071-2/+55
* [NFC] Fix trivial typos in commentsJames Henderson2020-01-061-1/+1
* [ARM] Use isFMAFasterThanFMulAndFAdd for scalars as well as MVE vectorsDavid Green2020-01-051-4/+7
* Move tail call disabling code to target independent codeReid Kleckner2020-01-031-5/+2
* [DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG fo...QingShan Zhang2020-01-031-0/+7
* [ARM] Sink splat to ICmpDavid Green2019-12-301-0/+1
* [ARM] [Windows] Use COFF stubs for calls to extern_weak functionsMartin Storsjö2019-12-231-4/+6
* Revert "[ARM] Improve codegen of volatile load/store of i64"Victor Campos2019-12-201-55/+2
* [ARM] Improve codegen of volatile load/store of i64Victor Campos2019-12-191-2/+55
* [ARM] Add custom strict fp conversion lowering when non-strict is customJohn Brawn2019-12-131-33/+64
* [NFC] Use EVT instead of bool for getSetCCInverse()Alex Richardson2019-12-131-5/+5
* [ARM][MVE] Sink vector shift operandSam Parker2019-12-121-3/+28
* Revert "[ARM][MVE] Sink vector shift operand"Sam Parker2019-12-121-27/+3
* [ARM][MVE] Sink vector shift operandSam Parker2019-12-121-3/+27
* [IR] Split out target specific intrinsic enums into separate headersReid Kleckner2019-12-111-0/+1
* [ARM] Attempt to use whole register vmovs for MVE shuffles.David Green2019-12-081-0/+90
* [ARM] Disable VLD4 under MVEDavid Green2019-12-081-1/+6
* [ARM] Add some VCMP folding and canonicalisationDavid Green2019-12-021-8/+43
* Revert "[ARM] Allocatable Global Register Variables for ARM"Carey Williams2019-11-291-9/+3
* [ARM] Replace arm_neon_vqadds with sadd_satDavid Green2019-11-271-0/+3
* [Codegen][ARM] Add addressing modes from masked loads and storesDavid Green2019-11-261-18/+56
* [ARM] MVE interleaving load and stores.David Green2019-11-191-31/+90
* DAG: Add function context to isFMAFasterThanFMulAndFAddMatt Arsenault2019-11-191-1/+2
* [SVE][CodeGen] Scalable vector MVT size queriesGraham Hunter2019-11-181-1/+1
* [ARM] Allocatable Global Register Variables for ARMAnna Welker2019-11-181-3/+9
* [ARM,MVE] Use VMOV.{S8,S16} for sign-extended extractelement.Simon Tatham2019-11-131-3/+4
* [AArch64][X86] Don't assume __powidf2 is available on Windows.Eli Friedman2019-11-081-56/+5
* [ARM] Use isFMAFasterThanFMulAndFAdd for MVEDavid Green2019-11-041-0/+30
* Add Windows Control Flow Guard checks (/guard:cf).Andrew Paverd2019-10-281-0/+3
* [ARM][AArch64] Implement __cls, __clsl and __clsll intrinsics from ACLEvhscampos2019-10-281-0/+43
* [ARM] Begin adding IR intrinsics for MVE instructions.Simon Tatham2019-10-241-0/+4
* [ARM] Add qadd lowering from a sadd_satDavid Green2019-10-211-4/+5
* [Alignment][NFC] TargetCallingConv::setOrigAlign and TargetLowering::getABIAl...Guillaume Chatelet2019-10-211-6/+5
* [ARM] Lower sadd_sat to qadd8 and qadd16David Green2019-10-211-1/+58
* [DAGCombine][ARM] Enable extending masked loadsSam Parker2019-10-171-3/+14
* [ARM] Selection for MVE VMOVNDavid Green2019-10-141-0/+35
* [ARM] VQSUB instructionDavid Green2019-10-101-0/+2
* [ARM] VQADD instructionsDavid Green2019-10-101-0/+2
* [ISEL][ARM][AARCH64] Tracking simple parameter forwarding registersNikola Prica2019-10-081-1/+8
* [ARM] Generate vcmp instead of vcmpeKristof Beyls2019-10-081-36/+15
* [ARM] Make helpers static. NFC.Benjamin Kramer2019-10-021-3/+5
* [ARM] Identity shuffles are legalDavid Green2019-10-021-0/+1
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