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path: root/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
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* AMDGPU/SI: Use v_readfirstlane_b32 when restoring SGPRs spilled to scratchTom Stellard2016-05-021-2/+1
* AMDGPU/SI: Set the kill flag on temp VGPRs used to restore SGPRs from scratchTom Stellard2016-05-021-1/+1
* AMDGPU/SI: Enable the post-ra schedulerTom Stellard2016-04-301-16/+11
* [AMDGPU] Move reserved vgpr count for trap handler usage to SIMachineFunction...Konstantin Zhuravlyov2016-04-261-2/+3
* [AMDGPU] Reserve VGPRs for trap handler usage if instructedKonstantin Zhuravlyov2016-04-261-0/+11
* AMDGPU: Add queue ptr intrinsicMatt Arsenault2016-04-251-1/+2
* Silence some "initialized but unused" warnings from MSVC -- the function bein...Aaron Ballman2016-04-181-13/+2
* AMDGPU: Enable LocalStackSlotAllocation passMatt Arsenault2016-04-161-0/+138
* AMDGPU: allow specifying a workgroup size that needs to fit in a compute unitTom Stellard2016-04-141-52/+73
* AMDGPU/SI: Add support for spilling VGPRs without having to scavenge registersTom Stellard2016-04-131-10/+27
* [AMDGPU][llvm-mc] Support of Trap Handler registers (TTMP0..11 and TBA/TMA)gi...Artem Tamazov2016-04-131-1/+25
* AMDGPU/SI: Add MachineBasicBlock parameter to SIInstrInfo::insertWaitStatesTom Stellard2016-04-071-2/+2
* AMDGPU: Cache information about register pressure setsTom Stellard2016-03-231-24/+33
* AMDGPU/SI: add llvm.amdgcn.buffer.load/store.format intrinsicsNicolai Haehnle2016-03-101-3/+3
* AMDGPU/SI: Add support for spiling SGPRs to scratch bufferTom Stellard2016-03-041-17/+69
* AMDGPU/SI: Enable frame index scavenging during PrologEpilogueInserterTom Stellard2016-03-041-7/+13
* AMDGPU/SI: Detect uniform branches and emit s_cbranch instructionsTom Stellard2016-02-121-1/+4
* AMDGPU: Set flat_scratch from flat_scratch_init regMatt Arsenault2016-02-121-0/+5
* AMDGPU/SI: Make sure MIMG descriptors and samplers stay in SGPRsTom Stellard2016-02-111-0/+18
* AMDGPU: Release the scavenged offset register during VGPR spillNicolai Haehnle2016-02-101-1/+8
* AMDGPU/SI: Add SI Machine SchedulerNicolai Haehnle2016-01-131-1/+14
* AMDGPU/SI: Fold operands with sub-registersNicolai Haehnle2016-01-071-4/+30
* AMDGPU/SI: xnack_mask is always reserved on VINicolai Haehnle2016-01-071-31/+16
* AMDGPU: add +xnack featureNicolai Haehnle2016-01-041-6/+27
* AMDGPU: Avoid assertions after SGPR spilling failedNicolai Haehnle2016-01-041-10/+0
* AMDGPU: Fix off-by-one in SIRegisterInfo::eliminateFrameIndexNicolai Haehnle2015-12-171-6/+7
* Squelch unused variable warning in SIRegisterInfo.cpp.Matt Arsenault2015-12-011-1/+2
* AMDGPU: Rework how private buffer passed for HSAMatt Arsenault2015-11-301-18/+62
* AMDGPU: Rename enums to be consistent with HSA code object terminologyMatt Arsenault2015-11-301-14/+14
* AMDGPU: Remove SIPrepareScratchRegsMatt Arsenault2015-11-301-0/+19
* AMDGPU: Add llvm.amdgcn.dispatch.ptr intrinsicTom Stellard2015-11-261-0/+6
* Revert "Remove unnecessary call to getAllocatableRegClass"Tom Stellard2015-11-121-1/+7
* AMDGPU: Set isAllocatable = 0 on VS_32/VS_64Matt Arsenault2015-11-111-7/+1
* AMDGPU: Hack for VS_32 register pressureMatt Arsenault2015-11-061-4/+10
* AMDGPU: s[102:103] is unavailable on VIMatt Arsenault2015-11-031-1/+10
* AMDGPU: Define correct number of SGPRsMatt Arsenault2015-11-031-0/+4
* AMDGPU: Stop reserving v[254:255]Matt Arsenault2015-10-201-4/+0
* Make a bunch of static arrays const.Craig Topper2015-10-181-1/+1
* AMDGPU: Make SIInsertWaits about a factor of 4 fasterMatt Arsenault2015-10-011-0/+2
* AMDGPU: Switch over reg class size instead of checking all super classesMatt Arsenault2015-09-261-20/+34
* Introduce target hook for optimizing register copiesMatt Arsenault2015-09-241-0/+24
* Untabify.NAKAMURA Takumi2015-09-221-1/+1
* Reformat blank lines.NAKAMURA Takumi2015-09-221-1/+0
* AMDGPU: Remove dead codeMatt Arsenault2015-09-191-8/+0
* AMDGPU: Set mem operands for spill instructionsMatt Arsenault2015-08-291-8/+9
* AMDGPU: Make sure to reserve super registersMatt Arsenault2015-08-261-16/+15
* MachineRegisterInfo: Introduce isPhysRegUsed()Matthias Braun2015-08-181-6/+3
* AMDGPU/SI: Add missing spill classTom Stellard2015-08-141-1/+2
* AMDGPU: Remove SCCReg.Matt Arsenault2015-08-051-2/+0
* MachineRegisterInfo: Remove UsedPhysReg infrastructureMatthias Braun2015-07-141-1/+1
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