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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-11-03 22:39:50 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-11-03 22:39:50 +0000 |
| commit | 192b282bf3dd285da991a6aeb49831d3fd93b85c (patch) | |
| tree | 26796093b51d9e72792cd0a1f9e41b6a28645801 /llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | |
| parent | d77f0d2526e28611b09121324540e8faaa5cab1a (diff) | |
| download | bcm5719-llvm-192b282bf3dd285da991a6aeb49831d3fd93b85c.tar.gz bcm5719-llvm-192b282bf3dd285da991a6aeb49831d3fd93b85c.zip | |
AMDGPU: Define correct number of SGPRs
There are actually 104 so 2 were missing.
More assembler tests with high register number tuples
will be included in later patches.
llvm-svn: 251999
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 30920a0bb93..1315b6a7b3a 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -41,6 +41,10 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const { reserveRegisterTuples(Reserved, AMDGPU::EXEC); reserveRegisterTuples(Reserved, AMDGPU::FLAT_SCR); + // Reserve the last 2 registers so we will always have at least 2 more that + // will physically contain VCC. + reserveRegisterTuples(Reserved, AMDGPU::SGPR102_SGPR103); + // Tonga and Iceland can only allocate a fixed number of SGPRs due // to a hw bug. if (MF.getSubtarget<AMDGPUSubtarget>().hasSGPRInitBug()) { |
