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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-08-29 06:48:57 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-08-29 06:48:57 +0000 |
| commit | 9a32cd3d3b79f94aa7e9d016a5e6eeb2650dd8a8 (patch) | |
| tree | 19456f5949c32f1889e6768ec6aa9b71492ba678 /llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | |
| parent | 5c004a7c610396fe2503380d46adb88da1de9df8 (diff) | |
| download | bcm5719-llvm-9a32cd3d3b79f94aa7e9d016a5e6eeb2650dd8a8.tar.gz bcm5719-llvm-9a32cd3d3b79f94aa7e9d016a5e6eeb2650dd8a8.zip | |
AMDGPU: Set mem operands for spill instructions
llvm-svn: 246357
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 610ebd88062..03b415bd3ae 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -177,14 +177,15 @@ void SIRegisterInfo::buildScratchLoadStore(MachineBasicBlock::iterator MI, bool IsKill = (i == e - 1); BuildMI(*MBB, MI, DL, TII->get(LoadStoreOp)) - .addReg(SubReg, getDefRegState(IsLoad)) - .addReg(ScratchRsrcReg, getKillRegState(IsKill)) - .addReg(SOffset) - .addImm(Offset) - .addImm(0) // glc - .addImm(0) // slc - .addImm(0) // tfe - .addReg(Value, RegState::Implicit | getDefRegState(IsLoad)); + .addReg(SubReg, getDefRegState(IsLoad)) + .addReg(ScratchRsrcReg, getKillRegState(IsKill)) + .addReg(SOffset) + .addImm(Offset) + .addImm(0) // glc + .addImm(0) // slc + .addImm(0) // tfe + .addReg(Value, RegState::Implicit | getDefRegState(IsLoad)) + .setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); } } |
