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| author | Tom Stellard <thomas.stellard@amd.com> | 2016-05-02 20:11:44 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2016-05-02 20:11:44 +0000 |
| commit | 154c9cdd2418f5336780deee8c5be13c67e5c3be (patch) | |
| tree | 991e06c270e656d077a4a9be7ed2e3318bb27016 /llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | |
| parent | 76af416afc02c53ce636057661d88e54dbfd2465 (diff) | |
| download | bcm5719-llvm-154c9cdd2418f5336780deee8c5be13c67e5c3be.tar.gz bcm5719-llvm-154c9cdd2418f5336780deee8c5be13c67e5c3be.zip | |
AMDGPU/SI: Use v_readfirstlane_b32 when restoring SGPRs spilled to scratch
We were using v_readlane_b32 with the lane set to zero, but this won't
work if thread 0 is not active.
Differential Revision: http://reviews.llvm.org/D19745
llvm-svn: 268295
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 9012b3110b3..ac569d967c1 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -589,9 +589,8 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, .addImm(i * 4) // offset .addMemOperand(MMO); BuildMI(*MBB, MI, DL, - TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32), SubReg) + TII->get(AMDGPU::V_READFIRSTLANE_B32), SubReg) .addReg(TmpReg, RegState::Kill) - .addImm(0) .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine); } } |
