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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-09-19 06:41:10 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-09-19 06:41:10 +0000 |
| commit | 1fafdc82d66186365b57e1172bf07ae3a2d3c7ce (patch) | |
| tree | e1ef9ddad7757d6c4ad92c079bed5c7a5c8a5723 /llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | |
| parent | 8823b84fae793ce000fda0af7180c43d744f32cd (diff) | |
| download | bcm5719-llvm-1fafdc82d66186365b57e1172bf07ae3a2d3c7ce.tar.gz bcm5719-llvm-1fafdc82d66186365b57e1172bf07ae3a2d3c7ce.zip | |
AMDGPU: Remove dead code
getCFGStructurizerRegClass is not used for SI, so
move it into R600 specific stuff.
llvm-svn: 248087
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 03b415bd3ae..2b03a453a3a 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -323,14 +323,6 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, } } -const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass( - MVT VT) const { - switch(VT.SimpleTy) { - default: - case MVT::i32: return &AMDGPU::VGPR_32RegClass; - } -} - unsigned SIRegisterInfo::getHWRegIndex(unsigned Reg) const { return getEncodingValue(Reg) & 0xff; } |

