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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-10-20 03:59:58 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-10-20 03:59:58 +0000 |
| commit | 8f18917a9050e87c8f6ff84493f3eff8467378d2 (patch) | |
| tree | 0b0182afeba4ad05899c1c1ef79a692f598b6e79 /llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | |
| parent | c8f89e86d5ba6787b5c4ecdbfc935b64a5edfa31 (diff) | |
| download | bcm5719-llvm-8f18917a9050e87c8f6ff84493f3eff8467378d2.tar.gz bcm5719-llvm-8f18917a9050e87c8f6ff84493f3eff8467378d2.zip | |
AMDGPU: Stop reserving v[254:255]
This wasn't doing anything useful. They weren't explicitly used
anywhere, and the RegScavenger ignores reserved registers.
This for some reason caused a random scheduling change in the test.
Getting the check lines to pass is too frustrating, and there's probably
not too much value in checking the vector case's operands N times.
llvm-svn: 250794
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 54e6085d4b4..30920a0bb93 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -41,10 +41,6 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const { reserveRegisterTuples(Reserved, AMDGPU::EXEC); reserveRegisterTuples(Reserved, AMDGPU::FLAT_SCR); - // Reserve some VGPRs to use as temp registers in case we have to spill VGPRs - reserveRegisterTuples(Reserved, AMDGPU::VGPR254); - reserveRegisterTuples(Reserved, AMDGPU::VGPR255); - // Tonga and Iceland can only allocate a fixed number of SGPRs due // to a hw bug. if (MF.getSubtarget<AMDGPUSubtarget>().hasSGPRInitBug()) { |
