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path: root/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
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* Remove more calls to getSubtargetImpl from the schedulers andEric Christopher2014-10-091-17/+14
* Cache TargetLowering on SelectionDAGISel and update previousEric Christopher2014-10-081-2/+2
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-10/+12
* fixed typoSanjay Patel2014-07-141-1/+1
* The hazard recognizer only needs a subtarget, not a target machineEric Christopher2014-06-131-1/+2
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final...Craig Topper2014-04-291-1/+1
* [Modules] Remove potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-1/+2
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check i...Craig Topper2014-04-141-35/+35
* Remove copy ctors that did the same thing as the default one.Benjamin Kramer2014-03-111-8/+0
* [C++11] Add 'override' keyword to virtual methods that override their base cl...Craig Topper2014-03-081-15/+15
* [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer2014-03-021-3/+3
* Fix spelling intruction -> instruction.Robert Wilhelm2013-09-281-1/+1
* Add 'const' qualifier to some arrays.Craig Topper2013-07-151-1/+2
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector s...Craig Topper2013-07-141-11/+11
* Cache the TargetLowering info object as a pointer.Bill Wendling2013-06-061-2/+2
* Track IR ordering of SelectionDAG nodes 3/4.Andrew Trick2013-05-251-1/+1
* Revert "pre-RA-sched: fix TargetOpcode usage"Christian Konig2013-03-201-18/+12
* pre-RA-sched: fix TargetOpcode usageChristian Konig2013-03-201-12/+18
* pre-RA-sched debug-only fixAndrew Trick2013-03-071-2/+4
* pre-RA-sched assertion fix. This bug was exposed by r176037.Andrew Trick2013-03-071-3/+0
* pre-RA-sched fix: only reevaluate physreg interferences when necessary.Andrew Trick2013-02-251-33/+61
* Add a special handling case for untyped CopyFromReg node in GetCostForDef() o...Weiming Zhao2013-01-291-1/+11
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-2/+2
* Change TargetLowering::getRepRegClassFor to take an MVT, instead ofPatrik Hagglund2012-12-131-8/+8
* Revert EVT->MVT changes, r169836-169851, due to buildbot failures.Patrik Hagglund2012-12-111-8/+8
* Change TargetLowering::getRepRegClassFor to take an MVT, instead ofPatrik Hagglund2012-12-111-8/+8
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-10/+10
* misched: Infrastructure for weak DAG edges.Andrew Trick2012-11-121-1/+1
* ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies.Andrew Trick2012-11-061-22/+14
* Move TargetData to DataLayout.Micah Villmow2012-10-081-1/+1
* Release build: guard dump functions withManman Ren2012-09-111-2/+2
* Release build: guard dump functions with "ifndef NDEBUG"Manman Ren2012-09-061-0/+4
* Add a new optimization pass: Stack Coloring, that merges disjoint static allo...Nadav Rotem2012-09-061-0/+2
* Fix a typo (the the => the)Sylvestre Ledru2012-07-231-1/+1
* sdsched: Use the right heuristics when -mcpu is not provided and we have no i...Andrew Trick2012-06-051-13/+12
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-011-1/+1
* Mark some static arrays as const.Craig Topper2012-05-241-1/+1
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-071-5/+6
* Source order scheduler should not preschedule nodes with multiple uses. rdar:...Evan Cheng2012-03-221-7/+11
* Use uint16_t to store instruction implicit uses and defs. Reduces static data.Craig Topper2012-03-081-6/+6
* misched preparation: rename core scheduler methods for consistency.Andrew Trick2012-03-071-12/+12
* misched preparation: modularize schedule printing.Andrew Trick2012-03-071-0/+6
* misched preparation: modularize schedule verification.Andrew Trick2012-03-071-1/+1
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-041-1/+1
* Add register mask support to ScheduleDAGRRList.Jakob Stoklund Olesen2012-02-131-11/+49
* Make sure we correctly set LiveRegGens when a call is unscheduled. <rdar://p...Eli Friedman2011-12-071-1/+8
* Fix an assertion in the scheduler. PR11386. No testcase included because it...Eli Friedman2011-12-071-3/+2
* These global variables aren't thread-safe, STATISTIC is. Andy Trick tells meNick Lewycky2011-12-071-66/+12
* Rename MVT::untyped to MVT::Untyped to match similar nomenclature.Owen Anderson2011-11-161-2/+2
* Added custom lowering for load->dec->store sequence in x86 when the EFLAGS re...Pete Cooper2011-11-151-0/+5
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