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authorRobert Wilhelm <robert.wilhelm@gmx.net>2013-09-28 11:46:15 +0000
committerRobert Wilhelm <robert.wilhelm@gmx.net>2013-09-28 11:46:15 +0000
commitf0cfb83bb4249b1bf716fa2445aaefecedf4d7a9 (patch)
tree1f6dedad33513a38bd430348ca9149e143a08501 /llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
parent5b013f5050681682a26c51539d629c27280725c3 (diff)
downloadbcm5719-llvm-f0cfb83bb4249b1bf716fa2445aaefecedf4d7a9.tar.gz
bcm5719-llvm-f0cfb83bb4249b1bf716fa2445aaefecedf4d7a9.zip
Fix spelling intruction -> instruction.
llvm-svn: 191610
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index f5fe168547c..1a562d74b41 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -718,7 +718,7 @@ void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU) {
// indicate the scheduled cycle.
SU->setHeightToAtLeast(CurCycle);
- // Reserve resources for the scheduled intruction.
+ // Reserve resources for the scheduled instruction.
EmitNode(SU);
Sequence.push_back(SU);
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