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| author | Andrew Trick <atrick@apple.com> | 2012-03-07 05:21:36 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-03-07 05:21:36 +0000 |
| commit | 46a58664f7c9a4a15988074fd5d6ae11992b4b21 (patch) | |
| tree | b0119d1bc47ee4042210e14f1b98c162e48f3aea /llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | |
| parent | 7c6c41a56ab0885c96f30444df73014c92ecb625 (diff) | |
| download | bcm5719-llvm-46a58664f7c9a4a15988074fd5d6ae11992b4b21.tar.gz bcm5719-llvm-46a58664f7c9a4a15988074fd5d6ae11992b4b21.zip | |
misched preparation: modularize schedule verification.
ScheduleDAG will not refer to the scheduled instruction sequence.
llvm-svn: 152204
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 1017d36b236..1a1fab0b310 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -1475,7 +1475,7 @@ void ScheduleDAGRRList::ListScheduleBottomUp() { std::reverse(Sequence.begin(), Sequence.end()); #ifndef NDEBUG - VerifySchedule(/*isBottomUp=*/true); + VerifyScheduledSequence(/*isBottomUp=*/true); #endif } |
