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path: root/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
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* [ScheduleDAG] When a node is cloned, add an edge between the nodes.Eli Friedman2019-10-041-0/+4
* Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders2019-08-011-7/+7
* [ScheduleDAGRRList] Recompute topological ordering on demand.Florian Hahn2019-04-171-24/+36
* Implementation of asm-goto support in LLVMCraig Topper2019-02-081-1/+3
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [ScheduleDAGRRList] Do not preschedule the node has ADJCALLSTACKDOWN parentShiva Chen2019-01-181-0/+23
* ScheduleDAG: Cleanup dumping code; NFCMatthias Braun2018-09-191-6/+6
* [ScheduleDAG] Fix unfolding of SUnits to already existent nodes.Nirav Dave2018-07-181-18/+30
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-69/+73
* IWYU for llvm-config.h in llvm, additions.Nico Weber2018-04-301-0/+1
* Fix layering of MachineValueType.h by moving it from CodeGen to SupportDavid Blaikie2018-03-231-1/+1
* [ARM] Allow the scheduler to clone a node with glue to avoid a copy CPSR ↔ ...Roger Ferrer Ibanez2018-01-311-4/+16
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-3/+2
* [CodeGen] Always use `printReg` to print registers in both MIR and debugFrancis Visoiu Mistrih2017-11-301-4/+6
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-4/+4
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-081-1/+1
* Reverting r315590; it did not include changes for llvm-tblgen, which is causi...Aaron Ballman2017-10-151-2/+2
* [dump] Remove NDEBUG from test to enable dump methods [NFC]Don Hinton2017-10-121-2/+2
* [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; ot...Eugene Zelenko2017-10-101-56/+80
* Remove usages of deprecated std::unary_function and std::binary_function.Benjamin Kramer2017-09-141-1/+1
* [ScheduleDAG] Don't schedule node with physical register interferenceEli Friedman2017-08-011-25/+37
* [SelectionDAG] Fix an use-after-free issue introduced in r305775.Haojian Wu2017-06-201-2/+2
* [SelectionDAG] Get rid of recursion in CalcNodeSethiUllmanNumberMax Kazantsev2017-06-201-19/+59
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-1/+1
* [ScheduleDAG] Deal with already scheduled loads in ScheduleDAG.Nirav Dave2017-05-311-128/+150
* Refactoring with range-based for, NFCKrzysztof Parzyszek2017-05-041-31/+26
* [ARM] ScheduleDAGRRList::DelayForLiveRegsBottomUp must consider OptionalDefsArtyom Skrobov2017-04-231-0/+12
* Remove redundant type castsSerge Pavlov2017-04-121-12/+8
* [SelectionDAG] Check CALLSEQ_BEGIN nodes in DelayForLiveRegsSam Parker2017-04-111-1/+2
* Cleanup dump() functions.Matthias Braun2017-01-281-5/+5
* Add iterator_range<regclass_iterator> to {Target,MC}RegisterInfo, NFCKrzysztof Parzyszek2017-01-251-6/+3
* Use the range variant of find instead of unpacking begin/endDavid Majnemer2016-08-111-3/+2
* rangify; NFCISanjay Patel2016-02-031-159/+129
* Replace uint16_t with the MCPhysReg typedef in many places. A lot of physical...Craig Topper2015-12-051-6/+6
* Fix accidental off by one changeFiona Glaser2015-12-021-1/+1
* Scheduler / Regalloc: use unique_ptr[] instead of std::vectorFiona Glaser2015-12-021-11/+13
* Convert a bunch of loops to foreach. NFC.Pete Cooper2015-06-261-16/+14
* Fix instruction scheduling live register trackingPawel Bylica2015-06-241-8/+17
* Use 'override/final' instead of 'virtual' for overridden methodsAlexander Kornienko2015-04-111-1/+1
* Fix a bug in SelectionDAG scheduling backtracking code: PR22304.Andrew Trick2015-03-271-1/+2
* Update SetVector to rely on the underlying set's insert to return a pair<iter...David Blaikie2014-11-191-3/+4
* Move register class name strings to a single array in MCRegisterInfo to reduc...Craig Topper2014-11-171-2/+2
* Convert some EVTs to MVTs where only a SimpleValueType is needed.Craig Topper2014-11-161-6/+6
* ScheduleDAG: record PhysReg dependencies represented by CopyFromReg nodesTim Northover2014-10-231-7/+13
* Remove more calls to getSubtargetImpl from the schedulers andEric Christopher2014-10-091-17/+14
* Cache TargetLowering on SelectionDAGISel and update previousEric Christopher2014-10-081-2/+2
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-10/+12
* fixed typoSanjay Patel2014-07-141-1/+1
* The hazard recognizer only needs a subtarget, not a target machineEric Christopher2014-06-131-1/+2
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final...Craig Topper2014-04-291-1/+1
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